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ROM0 now has the spectrum rom

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This commit is contained in:
Adrian Scripca
2022-03-30 13:18:06 +03:00
parent c59b02b186
commit 9d6eb7a9fa
94 changed files with 27700 additions and 9902 deletions
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db/altsyncram_qh91.tdf
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--altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" ENABLE_RUNTIME_MOD="NO" INIT_FILE="./rom/gw03.hex" LOW_POWER_MODE="AUTO" NUMWORDS_A=16384 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="CLOCK0" WIDTH_A=8 WIDTH_BYTEENA_A=1 WIDTHAD_A=14 address_a clock0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 13.1 cbx_altsyncram 2013:10:17:09:48:19:SJ cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_lpm_mux 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ cbx_stratixiii 2013:10:17:09:48:19:SJ cbx_stratixv 2013:10:17:09:48:19:SJ cbx_util_mgl 2013:10:17:09:48:19:SJ VERSION_END
-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
FUNCTION decode_c8a (data[0..0])
RETURNS ( eq[1..0]);
FUNCTION mux_3nb (data[15..0], sel[0..0])
RETURNS ( result[7..0]);
FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
--synthesis_resources = lut 9 M9K 16 reg 2
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
SUBDESIGN altsyncram_qh91
(
address_a[13..0] : input;
clock0 : input;
q_a[7..0] : output;
)
VARIABLE
address_reg_a[0..0] : dffe;
out_address_reg_a[0..0] : dffe;
rden_decode : decode_c8a;
mux2 : mux_3nb;
ram_block1a0 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "./rom/gw03.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a1 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "./rom/gw03.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 1,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a2 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "./rom/gw03.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 2,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a3 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "./rom/gw03.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 3,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a4 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "./rom/gw03.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 4,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a5 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "./rom/gw03.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 5,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a6 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "./rom/gw03.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 6,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a7 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "./rom/gw03.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 7,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a8 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "./rom/gw03.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a9 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "./rom/gw03.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 1,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a10 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "./rom/gw03.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 2,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a11 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "./rom/gw03.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 3,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a12 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "./rom/gw03.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 4,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a13 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "./rom/gw03.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 5,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a14 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "./rom/gw03.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 6,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a15 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "ena0",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "./rom/gw03.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 13,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 7,
PORT_A_LAST_ADDRESS = 16383,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 8,
RAM_BLOCK_TYPE = "AUTO"
);
address_a_sel[0..0] : WIRE;
address_a_wire[13..0] : WIRE;
rden_decode_addr_sel_a[0..0] : WIRE;
BEGIN
address_reg_a[].clk = clock0;
address_reg_a[].d = address_a_sel[];
out_address_reg_a[].clk = clock0;
out_address_reg_a[].d = address_reg_a[].q;
rden_decode.data[] = rden_decode_addr_sel_a[];
mux2.data[] = ( ram_block1a[15..0].portadataout[0..0]);
mux2.sel[] = out_address_reg_a[].q;
ram_block1a[15..0].clk0 = clock0;
ram_block1a[15..0].ena0 = ( rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0]);
ram_block1a[15..0].portaaddr[] = ( address_a_wire[12..0]);
ram_block1a[15..0].portare = B"1111111111111111";
address_a_sel[0..0] = address_a[13..13];
address_a_wire[] = address_a[];
q_a[] = mux2.result[];
rden_decode_addr_sel_a[0..0] = address_a_wire[13..13];
END;
--VALID FILE
db/decode_c8a.tdf
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--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_DECODES=2 LPM_WIDTH=1 data eq
--VERSION_BEGIN 13.1 cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ VERSION_END
-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--synthesis_resources = lut 1
SUBDESIGN decode_c8a
(
data[0..0] : input;
eq[1..0] : output;
)
VARIABLE
enable : NODE;
eq_node[1..0] : WIRE;
BEGIN
enable = VCC;
eq[] = eq_node[];
eq_node[] = ( (data[] & enable), ((! data[]) & enable));
END;
--VALID FILE
db/logic_util_heursitic.dat
BIN
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db/mux_3nb.tdf
+53
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--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_SIZE=2 LPM_WIDTH=8 LPM_WIDTHS=1 data result sel
--VERSION_BEGIN 13.1 cbx_lpm_mux 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ VERSION_END
-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--synthesis_resources = lut 8
SUBDESIGN mux_3nb
(
data[15..0] : input;
result[7..0] : output;
sel[0..0] : input;
)
VARIABLE
result_node[7..0] : WIRE;
sel_node[0..0] : WIRE;
w_data109w[1..0] : WIRE;
w_data121w[1..0] : WIRE;
w_data133w[1..0] : WIRE;
w_data145w[1..0] : WIRE;
w_data157w[1..0] : WIRE;
w_data169w[1..0] : WIRE;
w_data83w[1..0] : WIRE;
w_data97w[1..0] : WIRE;
BEGIN
result[] = result_node[];
result_node[] = ( ((sel_node[] & w_data169w[1..1]) # ((! sel_node[]) & w_data169w[0..0])), ((sel_node[] & w_data157w[1..1]) # ((! sel_node[]) & w_data157w[0..0])), ((sel_node[] & w_data145w[1..1]) # ((! sel_node[]) & w_data145w[0..0])), ((sel_node[] & w_data133w[1..1]) # ((! sel_node[]) & w_data133w[0..0])), ((sel_node[] & w_data121w[1..1]) # ((! sel_node[]) & w_data121w[0..0])), ((sel_node[] & w_data109w[1..1]) # ((! sel_node[]) & w_data109w[0..0])), ((sel_node[] & w_data97w[1..1]) # ((! sel_node[]) & w_data97w[0..0])), ((sel_node[] & w_data83w[1..1]) # ((! sel_node[]) & w_data83w[0..0])));
sel_node[] = ( sel[0..0]);
w_data109w[] = ( data[10..10], data[2..2]);
w_data121w[] = ( data[11..11], data[3..3]);
w_data133w[] = ( data[12..12], data[4..4]);
w_data145w[] = ( data[13..13], data[5..5]);
w_data157w[] = ( data[14..14], data[6..6]);
w_data169w[] = ( data[15..15], data[7..7]);
w_data83w[] = ( data[8..8], data[0..0]);
w_data97w[] = ( data[9..9], data[1..1]);
END;
--VALID FILE
db/prev_cmp_spectrum.qmsg
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db/spectrum.asm.qmsg
+6 -6
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648633116429 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648635142046 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648633116430 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 12:38:36 2022 " "Processing started: Wed Mar 30 12:38:36 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648633116430 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1648633116430 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648635142047 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 13:12:21 2022 " "Processing started: Wed Mar 30 13:12:21 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648635142047 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1648635142047 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1648633116430 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1648635142047 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1648633117331 ""} { "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1648635143022 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1648633117357 ""} { "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1648635143049 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "393 " "Peak virtual memory: 393 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648633117592 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 12:38:37 2022 " "Processing ended: Wed Mar 30 12:38:37 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648633117592 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648633117592 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648633117592 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1648633117592 ""} { "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "385 " "Peak virtual memory: 385 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648635143323 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:12:23 2022 " "Processing ended: Wed Mar 30 13:12:23 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648635143323 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648635143323 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648635143323 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1648635143323 ""}
db/spectrum.asm.rdb
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db/spectrum.cbx.xml
+1 -1
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@@ -1,6 +1,6 @@
<?xml version="1.0" ?> <?xml version="1.0" ?>
<LOG_ROOT> <LOG_ROOT>
<PROJECT NAME="spectrum"> <PROJECT NAME="spectrum">
<CBX_INST_ENTRY INSTANCE_NAME="|spectrum|rom0:rom|altsyncram:altsyncram_component" CBX_FILE_NAME="altsyncram_ro91.tdf"/> <CBX_INST_ENTRY INSTANCE_NAME="|spectrum|rom0:rom|altsyncram:altsyncram_component" CBX_FILE_NAME="altsyncram_qh91.tdf"/>
</PROJECT> </PROJECT>
</LOG_ROOT> </LOG_ROOT>
db/spectrum.cmp.bpm
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db/spectrum.cycloneive_io_sim_cache.45um_tt_1200mv_85c_slow.hsd
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db/spectrum.eda.qmsg
+12 -12
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@@ -1,12 +1,12 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648633122029 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648635147928 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648633122030 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 12:38:41 2022 " "Processing started: Wed Mar 30 12:38:41 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648633122030 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648633122030 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648635147929 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 13:12:27 2022 " "Processing started: Wed Mar 30 13:12:27 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648635147929 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648635147929 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648633122031 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648635147929 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648633122334 ""} { "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648635148267 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648633122355 ""} { "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648635148299 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_fast.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_fast.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648633122376 ""} { "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_fast.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_fast.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648635148332 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648633122396 ""} { "Info" "IWSC_DONE_HDL_GENERATION" "spectrum.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648635148365 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648633122418 ""} { "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648635148393 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648633122437 ""} { "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648635148420 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_v_fast.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648633122456 ""} { "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_v_fast.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648635148446 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_v.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_v.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648633122475 ""} { "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_v.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_v.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648635148473 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "344 " "Peak virtual memory: 344 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648633122507 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 12:38:42 2022 " "Processing ended: Wed Mar 30 12:38:42 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648633122507 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648633122507 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648633122507 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648633122507 ""} { "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "343 " "Peak virtual memory: 343 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648635148515 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:12:28 2022 " "Processing ended: Wed Mar 30 13:12:28 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648635148515 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648635148515 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648635148515 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648635148515 ""}
db/spectrum.fit.qmsg
+48 -48
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File diff suppressed because one or more lines are too long
db/spectrum.hier_info
+289 -21
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@@ -14,6 +14,17 @@ LED[7] <= rom0:rom.q
address[0] => address[0].IN1 address[0] => address[0].IN1
address[1] => address[1].IN1 address[1] => address[1].IN1
address[2] => address[2].IN1 address[2] => address[2].IN1
address[3] => address[3].IN1
address[4] => address[4].IN1
address[5] => address[5].IN1
address[6] => address[6].IN1
address[7] => address[7].IN1
address[8] => address[8].IN1
address[9] => address[9].IN1
address[10] => address[10].IN1
address[11] => address[11].IN1
address[12] => address[12].IN1
address[13] => address[13].IN1
clock => clock.IN1 clock => clock.IN1
q[0] <= altsyncram:altsyncram_component.q_a q[0] <= altsyncram:altsyncram_component.q_a
q[1] <= altsyncram:altsyncram_component.q_a q[1] <= altsyncram:altsyncram_component.q_a
@@ -39,13 +50,24 @@ data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~ data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~ data_a[7] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~ data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_ro91:auto_generated.address_a[0] address_a[0] => altsyncram_qh91:auto_generated.address_a[0]
address_a[1] => altsyncram_ro91:auto_generated.address_a[1] address_a[1] => altsyncram_qh91:auto_generated.address_a[1]
address_a[2] => altsyncram_ro91:auto_generated.address_a[2] address_a[2] => altsyncram_qh91:auto_generated.address_a[2]
address_a[3] => altsyncram_qh91:auto_generated.address_a[3]
address_a[4] => altsyncram_qh91:auto_generated.address_a[4]
address_a[5] => altsyncram_qh91:auto_generated.address_a[5]
address_a[6] => altsyncram_qh91:auto_generated.address_a[6]
address_a[7] => altsyncram_qh91:auto_generated.address_a[7]
address_a[8] => altsyncram_qh91:auto_generated.address_a[8]
address_a[9] => altsyncram_qh91:auto_generated.address_a[9]
address_a[10] => altsyncram_qh91:auto_generated.address_a[10]
address_a[11] => altsyncram_qh91:auto_generated.address_a[11]
address_a[12] => altsyncram_qh91:auto_generated.address_a[12]
address_a[13] => altsyncram_qh91:auto_generated.address_a[13]
address_b[0] => ~NO_FANOUT~ address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~ addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~ addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_ro91:auto_generated.clock0 clock0 => altsyncram_qh91:auto_generated.clock0
clock1 => ~NO_FANOUT~ clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~ clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~ clocken1 => ~NO_FANOUT~
@@ -55,21 +77,21 @@ aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~ aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~ byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~ byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_ro91:auto_generated.q_a[0] q_a[0] <= altsyncram_qh91:auto_generated.q_a[0]
q_a[1] <= altsyncram_ro91:auto_generated.q_a[1] q_a[1] <= altsyncram_qh91:auto_generated.q_a[1]
q_a[2] <= altsyncram_ro91:auto_generated.q_a[2] q_a[2] <= altsyncram_qh91:auto_generated.q_a[2]
q_a[3] <= altsyncram_ro91:auto_generated.q_a[3] q_a[3] <= altsyncram_qh91:auto_generated.q_a[3]
q_a[4] <= altsyncram_ro91:auto_generated.q_a[4] q_a[4] <= altsyncram_qh91:auto_generated.q_a[4]
q_a[5] <= altsyncram_ro91:auto_generated.q_a[5] q_a[5] <= altsyncram_qh91:auto_generated.q_a[5]
q_a[6] <= altsyncram_ro91:auto_generated.q_a[6] q_a[6] <= altsyncram_qh91:auto_generated.q_a[6]
q_a[7] <= altsyncram_ro91:auto_generated.q_a[7] q_a[7] <= altsyncram_qh91:auto_generated.q_a[7]
q_b[0] <= <GND> q_b[0] <= <GND>
eccstatus[0] <= <GND> eccstatus[0] <= <GND>
eccstatus[1] <= <GND> eccstatus[1] <= <GND>
eccstatus[2] <= <GND> eccstatus[2] <= <GND>
|spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated
address_a[0] => ram_block1a0.PORTAADDR address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR address_a[0] => ram_block1a2.PORTAADDR
@@ -78,6 +100,14 @@ address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[0] => ram_block1a12.PORTAADDR
address_a[0] => ram_block1a13.PORTAADDR
address_a[0] => ram_block1a14.PORTAADDR
address_a[0] => ram_block1a15.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1 address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1 address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1 address_a[1] => ram_block1a2.PORTAADDR1
@@ -86,6 +116,14 @@ address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1 address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1 address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1 address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[1] => ram_block1a12.PORTAADDR1
address_a[1] => ram_block1a13.PORTAADDR1
address_a[1] => ram_block1a14.PORTAADDR1
address_a[1] => ram_block1a15.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2 address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2 address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2 address_a[2] => ram_block1a2.PORTAADDR2
@@ -94,6 +132,176 @@ address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2 address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2 address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2 address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2
address_a[2] => ram_block1a12.PORTAADDR2
address_a[2] => ram_block1a13.PORTAADDR2
address_a[2] => ram_block1a14.PORTAADDR2
address_a[2] => ram_block1a15.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[3] => ram_block1a10.PORTAADDR3
address_a[3] => ram_block1a11.PORTAADDR3
address_a[3] => ram_block1a12.PORTAADDR3
address_a[3] => ram_block1a13.PORTAADDR3
address_a[3] => ram_block1a14.PORTAADDR3
address_a[3] => ram_block1a15.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[4] => ram_block1a10.PORTAADDR4
address_a[4] => ram_block1a11.PORTAADDR4
address_a[4] => ram_block1a12.PORTAADDR4
address_a[4] => ram_block1a13.PORTAADDR4
address_a[4] => ram_block1a14.PORTAADDR4
address_a[4] => ram_block1a15.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[5] => ram_block1a8.PORTAADDR5
address_a[5] => ram_block1a9.PORTAADDR5
address_a[5] => ram_block1a10.PORTAADDR5
address_a[5] => ram_block1a11.PORTAADDR5
address_a[5] => ram_block1a12.PORTAADDR5
address_a[5] => ram_block1a13.PORTAADDR5
address_a[5] => ram_block1a14.PORTAADDR5
address_a[5] => ram_block1a15.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[6] => ram_block1a8.PORTAADDR6
address_a[6] => ram_block1a9.PORTAADDR6
address_a[6] => ram_block1a10.PORTAADDR6
address_a[6] => ram_block1a11.PORTAADDR6
address_a[6] => ram_block1a12.PORTAADDR6
address_a[6] => ram_block1a13.PORTAADDR6
address_a[6] => ram_block1a14.PORTAADDR6
address_a[6] => ram_block1a15.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[7] => ram_block1a8.PORTAADDR7
address_a[7] => ram_block1a9.PORTAADDR7
address_a[7] => ram_block1a10.PORTAADDR7
address_a[7] => ram_block1a11.PORTAADDR7
address_a[7] => ram_block1a12.PORTAADDR7
address_a[7] => ram_block1a13.PORTAADDR7
address_a[7] => ram_block1a14.PORTAADDR7
address_a[7] => ram_block1a15.PORTAADDR7
address_a[8] => ram_block1a0.PORTAADDR8
address_a[8] => ram_block1a1.PORTAADDR8
address_a[8] => ram_block1a2.PORTAADDR8
address_a[8] => ram_block1a3.PORTAADDR8
address_a[8] => ram_block1a4.PORTAADDR8
address_a[8] => ram_block1a5.PORTAADDR8
address_a[8] => ram_block1a6.PORTAADDR8
address_a[8] => ram_block1a7.PORTAADDR8
address_a[8] => ram_block1a8.PORTAADDR8
address_a[8] => ram_block1a9.PORTAADDR8
address_a[8] => ram_block1a10.PORTAADDR8
address_a[8] => ram_block1a11.PORTAADDR8
address_a[8] => ram_block1a12.PORTAADDR8
address_a[8] => ram_block1a13.PORTAADDR8
address_a[8] => ram_block1a14.PORTAADDR8
address_a[8] => ram_block1a15.PORTAADDR8
address_a[9] => ram_block1a0.PORTAADDR9
address_a[9] => ram_block1a1.PORTAADDR9
address_a[9] => ram_block1a2.PORTAADDR9
address_a[9] => ram_block1a3.PORTAADDR9
address_a[9] => ram_block1a4.PORTAADDR9
address_a[9] => ram_block1a5.PORTAADDR9
address_a[9] => ram_block1a6.PORTAADDR9
address_a[9] => ram_block1a7.PORTAADDR9
address_a[9] => ram_block1a8.PORTAADDR9
address_a[9] => ram_block1a9.PORTAADDR9
address_a[9] => ram_block1a10.PORTAADDR9
address_a[9] => ram_block1a11.PORTAADDR9
address_a[9] => ram_block1a12.PORTAADDR9
address_a[9] => ram_block1a13.PORTAADDR9
address_a[9] => ram_block1a14.PORTAADDR9
address_a[9] => ram_block1a15.PORTAADDR9
address_a[10] => ram_block1a0.PORTAADDR10
address_a[10] => ram_block1a1.PORTAADDR10
address_a[10] => ram_block1a2.PORTAADDR10
address_a[10] => ram_block1a3.PORTAADDR10
address_a[10] => ram_block1a4.PORTAADDR10
address_a[10] => ram_block1a5.PORTAADDR10
address_a[10] => ram_block1a6.PORTAADDR10
address_a[10] => ram_block1a7.PORTAADDR10
address_a[10] => ram_block1a8.PORTAADDR10
address_a[10] => ram_block1a9.PORTAADDR10
address_a[10] => ram_block1a10.PORTAADDR10
address_a[10] => ram_block1a11.PORTAADDR10
address_a[10] => ram_block1a12.PORTAADDR10
address_a[10] => ram_block1a13.PORTAADDR10
address_a[10] => ram_block1a14.PORTAADDR10
address_a[10] => ram_block1a15.PORTAADDR10
address_a[11] => ram_block1a0.PORTAADDR11
address_a[11] => ram_block1a1.PORTAADDR11
address_a[11] => ram_block1a2.PORTAADDR11
address_a[11] => ram_block1a3.PORTAADDR11
address_a[11] => ram_block1a4.PORTAADDR11
address_a[11] => ram_block1a5.PORTAADDR11
address_a[11] => ram_block1a6.PORTAADDR11
address_a[11] => ram_block1a7.PORTAADDR11
address_a[11] => ram_block1a8.PORTAADDR11
address_a[11] => ram_block1a9.PORTAADDR11
address_a[11] => ram_block1a10.PORTAADDR11
address_a[11] => ram_block1a11.PORTAADDR11
address_a[11] => ram_block1a12.PORTAADDR11
address_a[11] => ram_block1a13.PORTAADDR11
address_a[11] => ram_block1a14.PORTAADDR11
address_a[11] => ram_block1a15.PORTAADDR11
address_a[12] => ram_block1a0.PORTAADDR12
address_a[12] => ram_block1a1.PORTAADDR12
address_a[12] => ram_block1a2.PORTAADDR12
address_a[12] => ram_block1a3.PORTAADDR12
address_a[12] => ram_block1a4.PORTAADDR12
address_a[12] => ram_block1a5.PORTAADDR12
address_a[12] => ram_block1a6.PORTAADDR12
address_a[12] => ram_block1a7.PORTAADDR12
address_a[12] => ram_block1a8.PORTAADDR12
address_a[12] => ram_block1a9.PORTAADDR12
address_a[12] => ram_block1a10.PORTAADDR12
address_a[12] => ram_block1a11.PORTAADDR12
address_a[12] => ram_block1a12.PORTAADDR12
address_a[12] => ram_block1a13.PORTAADDR12
address_a[12] => ram_block1a14.PORTAADDR12
address_a[12] => ram_block1a15.PORTAADDR12
address_a[13] => address_reg_a[0].DATAIN
address_a[13] => decode_c8a:rden_decode.data[0]
clock0 => ram_block1a0.CLK0 clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0 clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0 clock0 => ram_block1a2.CLK0
@@ -102,13 +310,73 @@ clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0 clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0 clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0 clock0 => ram_block1a7.CLK0
q_a[0] <= ram_block1a0.PORTADATAOUT clock0 => ram_block1a8.CLK0
q_a[1] <= ram_block1a1.PORTADATAOUT clock0 => ram_block1a9.CLK0
q_a[2] <= ram_block1a2.PORTADATAOUT clock0 => ram_block1a10.CLK0
q_a[3] <= ram_block1a3.PORTADATAOUT clock0 => ram_block1a11.CLK0
q_a[4] <= ram_block1a4.PORTADATAOUT clock0 => ram_block1a12.CLK0
q_a[5] <= ram_block1a5.PORTADATAOUT clock0 => ram_block1a13.CLK0
q_a[6] <= ram_block1a6.PORTADATAOUT clock0 => ram_block1a14.CLK0
q_a[7] <= ram_block1a7.PORTADATAOUT clock0 => ram_block1a15.CLK0
clock0 => address_reg_a[0].CLK
clock0 => out_address_reg_a[0].CLK
q_a[0] <= mux_3nb:mux2.result[0]
q_a[1] <= mux_3nb:mux2.result[1]
q_a[2] <= mux_3nb:mux2.result[2]
q_a[3] <= mux_3nb:mux2.result[3]
q_a[4] <= mux_3nb:mux2.result[4]
q_a[5] <= mux_3nb:mux2.result[5]
q_a[6] <= mux_3nb:mux2.result[6]
q_a[7] <= mux_3nb:mux2.result[7]
|spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|decode_c8a:rden_decode
data[0] => eq_node[1].IN0
data[0] => eq_node[0].IN0
eq[0] <= eq_node[0].DB_MAX_OUTPUT_PORT_TYPE
eq[1] <= eq_node[1].DB_MAX_OUTPUT_PORT_TYPE
|spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|mux_3nb:mux2
data[0] => result_node[0].IN1
data[1] => result_node[1].IN1
data[2] => result_node[2].IN1
data[3] => result_node[3].IN1
data[4] => result_node[4].IN1
data[5] => result_node[5].IN1
data[6] => result_node[6].IN1
data[7] => result_node[7].IN1
data[8] => result_node[0].IN1
data[9] => result_node[1].IN1
data[10] => result_node[2].IN1
data[11] => result_node[3].IN1
data[12] => result_node[4].IN1
data[13] => result_node[5].IN1
data[14] => result_node[6].IN1
data[15] => result_node[7].IN1
result[0] <= result_node[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= result_node[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= result_node[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= result_node[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= result_node[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= result_node[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= result_node[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= result_node[7].DB_MAX_OUTPUT_PORT_TYPE
sel[0] => result_node[7].IN0
sel[0] => _.IN0
sel[0] => result_node[6].IN0
sel[0] => _.IN0
sel[0] => result_node[5].IN0
sel[0] => _.IN0
sel[0] => result_node[4].IN0
sel[0] => _.IN0
sel[0] => result_node[3].IN0
sel[0] => _.IN0
sel[0] => result_node[2].IN0
sel[0] => _.IN0
sel[0] => result_node[1].IN0
sel[0] => _.IN0
sel[0] => result_node[0].IN0
sel[0] => _.IN0
db/spectrum.hif
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db/spectrum.lpc.html
+34 -2
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@@ -16,8 +16,40 @@
<TH>Output only Bidir</TH> <TH>Output only Bidir</TH>
</TR> </TR>
<TR > <TR >
<TD >rom|altsyncram_component|auto_generated|mux2</TD>
<TD >17</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >8</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >rom|altsyncram_component|auto_generated|rden_decode</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >rom|altsyncram_component|auto_generated</TD> <TD >rom|altsyncram_component|auto_generated</TD>
<TD >4</TD> <TD >15</TD>
<TD >0</TD> <TD >0</TD>
<TD >0</TD> <TD >0</TD>
<TD >0</TD> <TD >0</TD>
@@ -33,7 +65,7 @@
</TR> </TR>
<TR > <TR >
<TD >rom</TD> <TD >rom</TD>
<TD >4</TD> <TD >15</TD>
<TD >0</TD> <TD >0</TD>
<TD >0</TD> <TD >0</TD>
<TD >0</TD> <TD >0</TD>
db/spectrum.lpc.rdb
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db/spectrum.lpc.txt
+32 -2
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@@ -1,8 +1,38 @@
+--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+
; Legal Partition Candidates ; ; Legal Partition Candidates ;
+--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+
Hierarchy : rom|altsyncram_component|auto_generated|mux2
Input : 17
Constant Input : 0
Unused Input : 0
Floating Input : 0
Output : 8
Constant Output : 0
Unused Output : 0
Floating Output : 0
Bidir : 0
Constant Bidir : 0
Unused Bidir : 0
Input only Bidir : 0
Output only Bidir : 0
Hierarchy : rom|altsyncram_component|auto_generated|rden_decode
Input : 1
Constant Input : 0
Unused Input : 0
Floating Input : 0
Output : 2
Constant Output : 0
Unused Output : 0
Floating Output : 0
Bidir : 0
Constant Bidir : 0
Unused Bidir : 0
Input only Bidir : 0
Output only Bidir : 0
Hierarchy : rom|altsyncram_component|auto_generated Hierarchy : rom|altsyncram_component|auto_generated
Input : 4 Input : 15
Constant Input : 0 Constant Input : 0
Unused Input : 0 Unused Input : 0
Floating Input : 0 Floating Input : 0
@@ -17,7 +47,7 @@ Input only Bidir : 0
Output only Bidir : 0 Output only Bidir : 0
Hierarchy : rom Hierarchy : rom
Input : 4 Input : 15
Constant Input : 0 Constant Input : 0
Unused Input : 0 Unused Input : 0
Floating Input : 0 Floating Input : 0
db/spectrum.map.bpm
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db/spectrum.map.cdb
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db/spectrum.map.hdb
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db/spectrum.map.kpt
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db/spectrum.map.qmsg
+23 -19
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@@ -1,19 +1,23 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648633107075 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648635132020 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648633107076 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 12:38:26 2022 " "Processing started: Wed Mar 30 12:38:26 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648633107076 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648633107076 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648635132022 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 13:12:11 2022 " "Processing started: Wed Mar 30 13:12:11 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648635132022 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648635132022 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum " "Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648633107076 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum " "Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648635132022 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648633107239 ""} { "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648635132212 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spectrum.v 1 1 " "Found 1 design units, including 1 entities, in source file spectrum.v" { { "Info" "ISGN_ENTITY_NAME" "1 spectrum " "Found entity 1: spectrum" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648633107303 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648633107303 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spectrum.v 1 1 " "Found 1 design units, including 1 entities, in source file spectrum.v" { { "Info" "ISGN_ENTITY_NAME" "1 spectrum " "Found entity 1: spectrum" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648635132282 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648635132282 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom0.v 1 1 " "Found 1 design units, including 1 entities, in source file rom0.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom0 " "Found entity 1: rom0" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648633107306 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648633107306 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom0.v 1 1 " "Found 1 design units, including 1 entities, in source file rom0.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom0 " "Found entity 1: rom0" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648635132284 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648635132284 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "spectrum " "Elaborating entity \"spectrum\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1648633107357 ""} { "Info" "ISGN_START_ELABORATION_TOP" "spectrum " "Elaborating entity \"spectrum\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1648635132338 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 21 spectrum.v(19) " "Verilog HDL assignment warning at spectrum.v(19): truncated value with size 32 to match size of target (21)" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 19 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1648633107359 "|spectrum"} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 22 spectrum.v(18) " "Verilog HDL assignment warning at spectrum.v(18): truncated value with size 32 to match size of target (22)" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 18 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1648635132340 "|spectrum"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 spectrum.v(21) " "Verilog HDL assignment warning at spectrum.v(21): truncated value with size 32 to match size of target (3)" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 21 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1648633107359 "|spectrum"} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 spectrum.v(20) " "Verilog HDL assignment warning at spectrum.v(20): truncated value with size 32 to match size of target (14)" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 20 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1648635132340 "|spectrum"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom0 rom0:rom " "Elaborating entity \"rom0\" for hierarchy \"rom0:rom\"" { } { { "spectrum.v" "rom" { Text "/home/benny/work/fpga/projects/spectrum.v" 14 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107369 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom0 rom0:rom " "Elaborating entity \"rom0\" for hierarchy \"rom0:rom\"" { } { { "spectrum.v" "rom" { Text "/home/benny/work/fpga/projects/spectrum.v" 13 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132350 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram rom0:rom\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "altsyncram_component" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107416 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram rom0:rom\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "altsyncram_component" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132402 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "rom0:rom\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_ELABORATION_HEADER" "rom0:rom\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648635132403 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rom0:rom\|altsyncram:altsyncram_component " "Instantiated megafunction \"rom0:rom\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file led_patterns.mif " "Parameter \"init_file\" = \"led_patterns.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 8 " "Parameter \"numwords_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 3 " "Parameter \"widthad_a\" = \"3\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} } { { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_TOP" "rom0:rom\|altsyncram:altsyncram_component " "Instantiated megafunction \"rom0:rom\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132403 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132403 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132403 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file ./rom/gw03.hex " "Parameter \"init_file\" = \"./rom/gw03.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132403 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132403 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132403 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132403 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 16384 " "Parameter \"numwords_a\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132403 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132403 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132403 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132403 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 14 " "Parameter \"widthad_a\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132403 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132403 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132403 ""} } { { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648635132403 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_ro91.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_ro91.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_ro91 " "Found entity 1: altsyncram_ro91" { } { { "db/altsyncram_ro91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_ro91.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648633107463 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648633107463 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_qh91.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_qh91.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_qh91 " "Found entity 1: altsyncram_qh91" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 31 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648635132451 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648635132451 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_ro91 rom0:rom\|altsyncram:altsyncram_component\|altsyncram_ro91:auto_generated " "Elaborating entity \"altsyncram_ro91\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_ro91:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107464 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_qh91 rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated " "Elaborating entity \"altsyncram_qh91\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132452 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1648633107974 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_c8a.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_c8a.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_c8a " "Found entity 1: decode_c8a" { } { { "db/decode_c8a.tdf" "" { Text "/home/benny/work/fpga/projects/db/decode_c8a.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648635132495 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648635132495 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1648633108175 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648633108175 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_c8a rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|decode_c8a:rden_decode " "Elaborating entity \"decode_c8a\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|decode_c8a:rden_decode\"" { } { { "db/altsyncram_qh91.tdf" "rden_decode" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 40 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132495 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "71 " "Implemented 71 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Implemented 1 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1648633108217 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1648633108217 ""} { "Info" "ICUT_CUT_TM_LCELLS" "54 " "Implemented 54 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1648633108217 ""} { "Info" "ICUT_CUT_TM_RAMS" "8 " "Implemented 8 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Quartus II" 0 -1 1648633108217 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1648633108217 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_3nb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_3nb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_3nb " "Found entity 1: mux_3nb" { } { { "db/mux_3nb.tdf" "" { Text "/home/benny/work/fpga/projects/db/mux_3nb.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648635132537 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648635132537 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "384 " "Peak virtual memory: 384 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648633108224 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 12:38:28 2022 " "Processing ended: Wed Mar 30 12:38:28 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648633108224 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648633108224 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648633108224 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648633108224 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_3nb rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|mux_3nb:mux2 " "Elaborating entity \"mux_3nb\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|mux_3nb:mux2\"" { } { { "db/altsyncram_qh91.tdf" "mux2" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 41 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132537 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1648635133078 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1648635133316 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648635133316 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "79 " "Implemented 79 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Implemented 1 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1648635133366 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1648635133366 ""} { "Info" "ICUT_CUT_TM_LCELLS" "54 " "Implemented 54 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1648635133366 ""} { "Info" "ICUT_CUT_TM_RAMS" "16 " "Implemented 16 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Quartus II" 0 -1 1648635133366 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1648635133366 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "392 " "Peak virtual memory: 392 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648635133374 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:12:13 2022 " "Processing ended: Wed Mar 30 13:12:13 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648635133374 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648635133374 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648635133374 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648635133374 ""}
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648633118951 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648635144709 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648633118952 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 12:38:38 2022 " "Processing started: Wed Mar 30 12:38:38 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648633118952 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648633118952 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648635144710 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 13:12:24 2022 " "Processing started: Wed Mar 30 13:12:24 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648635144710 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648635144710 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta spectrum -c spectrum " "Command: quartus_sta spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648633118952 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta spectrum -c spectrum " "Command: quartus_sta spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648635144711 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1648633118980 ""} { "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1648635144738 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648633119080 ""} { "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648635144851 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648633119082 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648635144852 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648633119126 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648635144896 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648633119126 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648635144896 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "spectrum.sdc " "Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1648633119323 ""} { "Critical Warning" "WSTA_SDC_NOT_FOUND" "spectrum.sdc " "Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1648635145098 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1648633119324 ""} { "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1648635145098 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119325 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119325 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145099 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145099 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1648633119451 ""} { "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1648635145225 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119452 ""} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145225 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1648633119452 ""} { "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1648635145226 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1648633119457 ""} { "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1648635145236 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648633119465 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648633119465 ""} { "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648635145248 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648635145248 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.763 " "Worst-case setup slack is -2.763" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119466 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119466 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.763 -43.394 CLOCK_50 " " -2.763 -43.394 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119466 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648633119466 ""} { "Info" "ISTA_WORST_CASE_SLACK" "setup -1.788 " "Worst-case setup slack is -1.788" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145249 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145249 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.788 -88.557 CLOCK_50 " " -1.788 -88.557 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145249 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648635145249 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.343 " "Worst-case hold slack is 0.343" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119466 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119466 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.343 0.000 CLOCK_50 " " 0.343 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119466 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648633119466 ""} { "Info" "ISTA_WORST_CASE_SLACK" "hold 0.260 " "Worst-case hold slack is 0.260" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145250 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145250 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.260 0.000 CLOCK_50 " " 0.260 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145250 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648635145250 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648633119467 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648635145251 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648633119468 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648635145251 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119468 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119468 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -46.633 CLOCK_50 " " -3.000 -46.633 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119468 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648633119468 ""} { "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145252 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145252 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -110.836 CLOCK_50 " " -3.000 -110.836 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145252 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648635145252 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648633119483 ""} { "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648635145268 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1648633119506 ""} { "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1648635145291 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1648633119876 ""} { "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1648635145672 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119892 ""} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145692 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648633119894 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648633119894 ""} { "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648635145695 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648635145695 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.331 " "Worst-case setup slack is -2.331" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119895 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119895 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.331 -34.994 CLOCK_50 " " -2.331 -34.994 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119895 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648633119895 ""} { "Info" "ISTA_WORST_CASE_SLACK" "setup -1.527 " "Worst-case setup slack is -1.527" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145696 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145696 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.527 -72.611 CLOCK_50 " " -1.527 -72.611 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145696 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648635145696 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.299 " "Worst-case hold slack is 0.299" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119896 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119896 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.299 0.000 CLOCK_50 " " 0.299 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119896 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648633119896 ""} { "Info" "ISTA_WORST_CASE_SLACK" "hold 0.255 " "Worst-case hold slack is 0.255" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145698 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145698 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.255 0.000 CLOCK_50 " " 0.255 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145698 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648635145698 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648633119897 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648635145699 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648633119898 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648635145700 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119899 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119899 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -46.624 CLOCK_50 " " -3.000 -46.624 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119899 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648633119899 ""} { "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145701 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145701 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -110.824 CLOCK_50 " " -3.000 -110.824 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145701 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648635145701 ""}
{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648633119916 ""} { "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648635145717 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648633120038 ""} { "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145841 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648633120038 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648633120038 ""} { "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648635145842 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648635145842 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.122 " "Worst-case setup slack is -1.122" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633120040 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633120040 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.122 -9.363 CLOCK_50 " " -1.122 -9.363 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633120040 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648633120040 ""} { "Info" "ISTA_WORST_CASE_SLACK" "setup -0.529 " "Worst-case setup slack is -0.529" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145843 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145843 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.529 -18.538 CLOCK_50 " " -0.529 -18.538 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145843 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648635145843 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.178 " "Worst-case hold slack is 0.178" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633120043 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633120043 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.178 0.000 CLOCK_50 " " 0.178 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633120043 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648633120043 ""} { "Info" "ISTA_WORST_CASE_SLACK" "hold 0.123 " "Worst-case hold slack is 0.123" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145845 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145845 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.123 0.000 CLOCK_50 " " 0.123 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145845 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648635145845 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648633120045 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648635145847 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648633120047 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648635145848 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633120049 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633120049 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -45.480 CLOCK_50 " " -3.000 -45.480 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633120049 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648633120049 ""} { "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145850 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145850 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -93.684 CLOCK_50 " " -3.000 -93.684 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145850 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648635145850 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648633120349 ""} { "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648635146144 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648633120349 ""} { "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648635146145 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "415 " "Peak virtual memory: 415 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648633120383 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 12:38:40 2022 " "Processing ended: Wed Mar 30 12:38:40 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648633120383 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648633120383 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648633120383 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648633120383 ""} { "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "407 " "Peak virtual memory: 407 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648635146186 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:12:26 2022 " "Processing ended: Wed Mar 30 13:12:26 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648635146186 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648635146186 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648635146186 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648635146186 ""}
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greybox_tmp/cbx_args.txt
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@@ -1,13 +1,13 @@
ADDRESS_ACLR_A=NONE ADDRESS_ACLR_A=NONE
CLOCK_ENABLE_INPUT_A=BYPASS CLOCK_ENABLE_INPUT_A=BYPASS
CLOCK_ENABLE_OUTPUT_A=BYPASS CLOCK_ENABLE_OUTPUT_A=BYPASS
INIT_FILE=led_patterns.mif INIT_FILE=./rom/gw03.hex
INTENDED_DEVICE_FAMILY="Cyclone IV E" INTENDED_DEVICE_FAMILY="Cyclone IV E"
NUMWORDS_A=8 NUMWORDS_A=16384
OPERATION_MODE=ROM OPERATION_MODE=ROM
OUTDATA_ACLR_A=NONE OUTDATA_ACLR_A=NONE
OUTDATA_REG_A=CLOCK0 OUTDATA_REG_A=CLOCK0
WIDTHAD_A=3 WIDTHAD_A=14
WIDTH_A=8 WIDTH_A=8
WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_A=1
DEVICE_FAMILY="Cyclone IV E" DEVICE_FAMILY="Cyclone IV E"
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incremental_db/compiled_partitions/spectrum.root_partition.map.kpt
BIN
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output_files/spectrum.asm.rpt
+8 -8
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@@ -1,5 +1,5 @@
Assembler report for spectrum Assembler report for spectrum
Wed Mar 30 12:38:37 2022 Wed Mar 30 13:12:23 2022
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
@@ -37,7 +37,7 @@ applicable agreement for further details.
+---------------------------------------------------------------+ +---------------------------------------------------------------+
; Assembler Summary ; ; Assembler Summary ;
+-----------------------+---------------------------------------+ +-----------------------+---------------------------------------+
; Assembler Status ; Successful - Wed Mar 30 12:38:37 2022 ; ; Assembler Status ; Successful - Wed Mar 30 13:12:23 2022 ;
; Revision Name ; spectrum ; ; Revision Name ; spectrum ;
; Top-level Entity Name ; spectrum ; ; Top-level Entity Name ; spectrum ;
; Family ; Cyclone IV E ; ; Family ; Cyclone IV E ;
@@ -162,8 +162,8 @@ Default Value : On
; Option ; Setting ; ; Option ; Setting ;
+----------------+-----------------------+ +----------------+-----------------------+
; Device ; EP4CE22F17C6 ; ; Device ; EP4CE22F17C6 ;
; JTAG usercode ; 0x00139765 ; ; JTAG usercode ; 0x00315633 ;
; Checksum ; 0x00139765 ; ; Checksum ; 0x00315633 ;
+----------------+-----------------------+ +----------------+-----------------------+
@@ -173,14 +173,14 @@ Default Value : On
Info: ******************************************************************* Info: *******************************************************************
Info: Running Quartus II 32-bit Assembler Info: Running Quartus II 32-bit Assembler
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
Info: Processing started: Wed Mar 30 12:38:36 2022 Info: Processing started: Wed Mar 30 13:12:21 2022
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum
Info (115031): Writing out detailed assembly data for power analysis Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files Info (115030): Assembler is generating device programming files
Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 393 megabytes Info: Peak virtual memory: 385 megabytes
Info: Processing ended: Wed Mar 30 12:38:37 2022 Info: Processing ended: Wed Mar 30 13:12:23 2022
Info: Elapsed time: 00:00:01 Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:01 Info: Total CPU time (on all processors): 00:00:01
output_files/spectrum.done
+1 -1
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@@ -1 +1 @@
Wed Mar 30 12:38:42 2022 Wed Mar 30 13:12:28 2022
output_files/spectrum.eda.rpt
+5 -5
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@@ -1,5 +1,5 @@
EDA Netlist Writer report for spectrum EDA Netlist Writer report for spectrum
Wed Mar 30 12:38:42 2022 Wed Mar 30 13:12:28 2022
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
@@ -36,7 +36,7 @@ applicable agreement for further details.
+-------------------------------------------------------------------+ +-------------------------------------------------------------------+
; EDA Netlist Writer Summary ; ; EDA Netlist Writer Summary ;
+---------------------------+---------------------------------------+ +---------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Wed Mar 30 12:38:42 2022 ; ; EDA Netlist Writer Status ; Successful - Wed Mar 30 13:12:28 2022 ;
; Revision Name ; spectrum ; ; Revision Name ; spectrum ;
; Top-level Entity Name ; spectrum ; ; Top-level Entity Name ; spectrum ;
; Family ; Cyclone IV E ; ; Family ; Cyclone IV E ;
@@ -88,7 +88,7 @@ applicable agreement for further details.
Info: ******************************************************************* Info: *******************************************************************
Info: Running Quartus II 32-bit EDA Netlist Writer Info: Running Quartus II 32-bit EDA Netlist Writer
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
Info: Processing started: Wed Mar 30 12:38:41 2022 Info: Processing started: Wed Mar 30 13:12:27 2022
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum
Info (204019): Generated file spectrum_6_1200mv_85c_slow.vo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file spectrum_6_1200mv_85c_slow.vo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file spectrum_6_1200mv_0c_slow.vo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file spectrum_6_1200mv_0c_slow.vo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool
@@ -99,8 +99,8 @@ Info (204019): Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder "/home/b
Info (204019): Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file spectrum_v.sdo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file spectrum_v.sdo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool
Info: Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings Info: Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 344 megabytes Info: Peak virtual memory: 343 megabytes
Info: Processing ended: Wed Mar 30 12:38:42 2022 Info: Processing ended: Wed Mar 30 13:12:28 2022
Info: Elapsed time: 00:00:01 Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01 Info: Total CPU time (on all processors): 00:00:01
output_files/spectrum.fit.rpt
+2434 -267
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output_files/spectrum.fit.summary
+6 -6
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@@ -1,16 +1,16 @@
Fitter Status : Successful - Wed Mar 30 12:38:34 2022 Fitter Status : Successful - Wed Mar 30 13:12:20 2022
Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
Revision Name : spectrum Revision Name : spectrum
Top-level Entity Name : spectrum Top-level Entity Name : spectrum
Family : Cyclone IV E Family : Cyclone IV E
Device : EP4CE22F17C6 Device : EP4CE22F17C6
Timing Models : Final Timing Models : Final
Total logic elements : 33 / 22,320 ( < 1 % ) Total logic elements : 55 / 22,320 ( < 1 % )
Total combinational functions : 33 / 22,320 ( < 1 % ) Total combinational functions : 52 / 22,320 ( < 1 % )
Dedicated logic registers : 24 / 22,320 ( < 1 % ) Dedicated logic registers : 38 / 22,320 ( < 1 % )
Total registers : 24 Total registers : 38
Total pins : 9 / 154 ( 6 % ) Total pins : 9 / 154 ( 6 % )
Total virtual pins : 0 Total virtual pins : 0
Total memory bits : 64 / 608,256 ( < 1 % ) Total memory bits : 131,072 / 608,256 ( 22 % )
Embedded Multiplier 9-bit elements : 0 / 132 ( 0 % ) Embedded Multiplier 9-bit elements : 0 / 132 ( 0 % )
Total PLLs : 0 / 4 ( 0 % ) Total PLLs : 0 / 4 ( 0 % )
output_files/spectrum.flow.rpt
+17 -17
View File
@@ -1,5 +1,5 @@
Flow report for spectrum Flow report for spectrum
Wed Mar 30 12:38:42 2022 Wed Mar 30 13:12:28 2022
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
@@ -40,20 +40,20 @@ applicable agreement for further details.
+---------------------------------------------------------------------------------+ +---------------------------------------------------------------------------------+
; Flow Summary ; ; Flow Summary ;
+------------------------------------+--------------------------------------------+ +------------------------------------+--------------------------------------------+
; Flow Status ; Successful - Wed Mar 30 12:38:42 2022 ; ; Flow Status ; Successful - Wed Mar 30 13:12:28 2022 ;
; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ; ; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
; Revision Name ; spectrum ; ; Revision Name ; spectrum ;
; Top-level Entity Name ; spectrum ; ; Top-level Entity Name ; spectrum ;
; Family ; Cyclone IV E ; ; Family ; Cyclone IV E ;
; Device ; EP4CE22F17C6 ; ; Device ; EP4CE22F17C6 ;
; Timing Models ; Final ; ; Timing Models ; Final ;
; Total logic elements ; 33 / 22,320 ( < 1 % ) ; ; Total logic elements ; 55 / 22,320 ( < 1 % ) ;
; Total combinational functions ; 33 / 22,320 ( < 1 % ) ; ; Total combinational functions ; 52 / 22,320 ( < 1 % ) ;
; Dedicated logic registers ; 24 / 22,320 ( < 1 % ) ; ; Dedicated logic registers ; 38 / 22,320 ( < 1 % ) ;
; Total registers ; 24 ; ; Total registers ; 38 ;
; Total pins ; 9 / 154 ( 6 % ) ; ; Total pins ; 9 / 154 ( 6 % ) ;
; Total virtual pins ; 0 ; ; Total virtual pins ; 0 ;
; Total memory bits ; 64 / 608,256 ( < 1 % ) ; ; Total memory bits ; 131,072 / 608,256 ( 22 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ; ; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ; ; Total PLLs ; 0 / 4 ( 0 % ) ;
+------------------------------------+--------------------------------------------+ +------------------------------------+--------------------------------------------+
@@ -64,7 +64,7 @@ applicable agreement for further details.
+-------------------+---------------------+ +-------------------+---------------------+
; Option ; Setting ; ; Option ; Setting ;
+-------------------+---------------------+ +-------------------+---------------------+
; Start date & time ; 03/30/2022 12:38:27 ; ; Start date & time ; 03/30/2022 13:12:12 ;
; Main task ; Compilation ; ; Main task ; Compilation ;
; Revision Name ; spectrum ; ; Revision Name ; spectrum ;
+-------------------+---------------------+ +-------------------+---------------------+
@@ -74,7 +74,7 @@ applicable agreement for further details.
; Flow Non-Default Global Settings ; ; Flow Non-Default Global Settings ;
+--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+
Assignment Name : COMPILER_SIGNATURE_ID Assignment Name : COMPILER_SIGNATURE_ID
Value : 0.164863310720961 Value : 0.164863513225804
Default Value : -- Default Value : --
Entity Name : -- Entity Name : --
Section Id : -- Section Id : --
@@ -160,35 +160,35 @@ Section Id : --
Module Name : Analysis & Synthesis Module Name : Analysis & Synthesis
Elapsed Time : 00:00:02 Elapsed Time : 00:00:02
Average Processors Used : 1.0 Average Processors Used : 1.0
Peak Virtual Memory : 373 MB Peak Virtual Memory : 381 MB
Total CPU Time (on all processors) : 00:00:01 Total CPU Time (on all processors) : 00:00:01
Module Name : Fitter Module Name : Fitter
Elapsed Time : 00:00:05 Elapsed Time : 00:00:06
Average Processors Used : 1.0 Average Processors Used : 1.0
Peak Virtual Memory : 600 MB Peak Virtual Memory : 595 MB
Total CPU Time (on all processors) : 00:00:06 Total CPU Time (on all processors) : 00:00:06
Module Name : Assembler Module Name : Assembler
Elapsed Time : 00:00:01 Elapsed Time : 00:00:02
Average Processors Used : 1.0 Average Processors Used : 1.0
Peak Virtual Memory : 393 MB Peak Virtual Memory : 385 MB
Total CPU Time (on all processors) : 00:00:01 Total CPU Time (on all processors) : 00:00:01
Module Name : TimeQuest Timing Analyzer Module Name : TimeQuest Timing Analyzer
Elapsed Time : 00:00:02 Elapsed Time : 00:00:02
Average Processors Used : 1.0 Average Processors Used : 1.0
Peak Virtual Memory : 415 MB Peak Virtual Memory : 407 MB
Total CPU Time (on all processors) : 00:00:02 Total CPU Time (on all processors) : 00:00:02
Module Name : EDA Netlist Writer Module Name : EDA Netlist Writer
Elapsed Time : 00:00:01 Elapsed Time : 00:00:01
Average Processors Used : 1.0 Average Processors Used : 1.0
Peak Virtual Memory : 332 MB Peak Virtual Memory : 331 MB
Total CPU Time (on all processors) : 00:00:01 Total CPU Time (on all processors) : 00:00:01
Module Name : Total Module Name : Total
Elapsed Time : 00:00:11 Elapsed Time : 00:00:13
Average Processors Used : -- Average Processors Used : --
Peak Virtual Memory : -- Peak Virtual Memory : --
Total CPU Time (on all processors) : 00:00:11 Total CPU Time (on all processors) : 00:00:11
output_files/spectrum.jdi
+1 -1
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@@ -1,6 +1,6 @@
<sld_project_info> <sld_project_info>
<project> <project>
<hash md5_digest_80b="cb6c551d4ff42d38b754"/> <hash md5_digest_80b="517dc0b141e7ba08df4a"/>
</project> </project>
<file_info> <file_info>
<file device="EP4CE22F17C6" path="spectrum.sof" usercode="0xFFFFFFFF"/> <file device="EP4CE22F17C6" path="spectrum.sof" usercode="0xFFFFFFFF"/>
output_files/spectrum.map.rpt
+99 -69
View File
@@ -1,5 +1,5 @@
Analysis & Synthesis report for spectrum Analysis & Synthesis report for spectrum
Wed Mar 30 12:38:28 2022 Wed Mar 30 13:12:13 2022
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
@@ -16,7 +16,7 @@ Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
8. Analysis & Synthesis RAM Summary 8. Analysis & Synthesis RAM Summary
9. Analysis & Synthesis IP Cores Summary 9. Analysis & Synthesis IP Cores Summary
10. General Register Statistics 10. General Register Statistics
11. Source assignments for rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated 11. Source assignments for rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated
12. Parameter Settings for User Entity Instance: rom0:rom|altsyncram:altsyncram_component 12. Parameter Settings for User Entity Instance: rom0:rom|altsyncram:altsyncram_component
13. altsyncram Parameter Settings by Entity Instance 13. altsyncram Parameter Settings by Entity Instance
14. Elapsed Time Per Partition 14. Elapsed Time Per Partition
@@ -46,18 +46,18 @@ applicable agreement for further details.
+---------------------------------------------------------------------------------+ +---------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ; ; Analysis & Synthesis Summary ;
+------------------------------------+--------------------------------------------+ +------------------------------------+--------------------------------------------+
; Analysis & Synthesis Status ; Successful - Wed Mar 30 12:38:28 2022 ; ; Analysis & Synthesis Status ; Successful - Wed Mar 30 13:12:13 2022 ;
; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ; ; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
; Revision Name ; spectrum ; ; Revision Name ; spectrum ;
; Top-level Entity Name ; spectrum ; ; Top-level Entity Name ; spectrum ;
; Family ; Cyclone IV E ; ; Family ; Cyclone IV E ;
; Total logic elements ; 33 ; ; Total logic elements ; 54 ;
; Total combinational functions ; 33 ; ; Total combinational functions ; 52 ;
; Dedicated logic registers ; 24 ; ; Dedicated logic registers ; 38 ;
; Total registers ; 24 ; ; Total registers ; 38 ;
; Total pins ; 9 ; ; Total pins ; 9 ;
; Total virtual pins ; 0 ; ; Total virtual pins ; 0 ;
; Total memory bits ; 64 ; ; Total memory bits ; 131,072 ;
; Embedded Multiplier 9-bit elements ; 0 ; ; Embedded Multiplier 9-bit elements ; 0 ;
; Total PLLs ; 0 ; ; Total PLLs ; 0 ;
+------------------------------------+--------------------------------------------+ +------------------------------------+--------------------------------------------+
@@ -405,12 +405,6 @@ File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/projects/spectrum.v File Name with Absolute Path : /home/benny/work/fpga/projects/spectrum.v
Library : Library :
File Name with User-Entered Path : led_patterns.mif
Used in Netlist : yes
File Type : User Memory Initialization File
File Name with Absolute Path : /home/benny/work/fpga/projects/led_patterns.mif
Library :
File Name with User-Entered Path : rom0.v File Name with User-Entered Path : rom0.v
Used in Netlist : yes Used in Netlist : yes
File Type : User Wizard-Generated File File Type : User Wizard-Generated File
@@ -471,10 +465,28 @@ File Type : Megafunction
File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/altdpram.inc File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/altdpram.inc
Library : Library :
File Name with User-Entered Path : db/altsyncram_ro91.tdf File Name with User-Entered Path : db/altsyncram_qh91.tdf
Used in Netlist : yes Used in Netlist : yes
File Type : Auto-Generated Megafunction File Type : Auto-Generated Megafunction
File Name with Absolute Path : /home/benny/work/fpga/projects/db/altsyncram_ro91.tdf File Name with Absolute Path : /home/benny/work/fpga/projects/db/altsyncram_qh91.tdf
Library :
File Name with User-Entered Path : rom/gw03.hex
Used in Netlist : yes
File Type : Auto-Found Memory Initialization File
File Name with Absolute Path : /home/benny/work/fpga/projects/rom/gw03.hex
Library :
File Name with User-Entered Path : db/decode_c8a.tdf
Used in Netlist : yes
File Type : Auto-Generated Megafunction
File Name with Absolute Path : /home/benny/work/fpga/projects/db/decode_c8a.tdf
Library :
File Name with User-Entered Path : db/mux_3nb.tdf
Used in Netlist : yes
File Type : Auto-Generated Megafunction
File Name with Absolute Path : /home/benny/work/fpga/projects/db/mux_3nb.tdf
Library : Library :
+--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+
@@ -485,29 +497,29 @@ Library :
+---------------------------------------------+----------------+ +---------------------------------------------+----------------+
; Resource ; Usage ; ; Resource ; Usage ;
+---------------------------------------------+----------------+ +---------------------------------------------+----------------+
; Estimated Total logic elements ; 33 ; ; Estimated Total logic elements ; 54 ;
; ; ; ; ; ;
; Total combinational functions ; 33 ; ; Total combinational functions ; 52 ;
; Logic element usage by number of LUT inputs ; ; ; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 10 ; ; -- 4 input functions ; 8 ;
; -- 3 input functions ; 1 ; ; -- 3 input functions ; 10 ;
; -- <=2 input functions ; 22 ; ; -- <=2 input functions ; 34 ;
; ; ; ; ; ;
; Logic elements by mode ; ; ; Logic elements by mode ; ;
; -- normal mode ; 13 ; ; -- normal mode ; 20 ;
; -- arithmetic mode ; 20 ; ; -- arithmetic mode ; 32 ;
; ; ; ; ; ;
; Total registers ; 24 ; ; Total registers ; 38 ;
; -- Dedicated logic registers ; 24 ; ; -- Dedicated logic registers ; 38 ;
; -- I/O registers ; 0 ; ; -- I/O registers ; 0 ;
; ; ; ; ; ;
; I/O pins ; 9 ; ; I/O pins ; 9 ;
; Total memory bits ; 64 ; ; Total memory bits ; 131072 ;
; Embedded Multiplier 9-bit elements ; 0 ; ; Embedded Multiplier 9-bit elements ; 0 ;
; Maximum fan-out node ; CLOCK_50~input ; ; Maximum fan-out node ; CLOCK_50~input ;
; Maximum fan-out ; 32 ; ; Maximum fan-out ; 54 ;
; Total fan-out ; 183 ; ; Total fan-out ; 473 ;
; Average fan-out ; 2.20 ; ; Average fan-out ; 3.81 ;
+---------------------------------------------+----------------+ +---------------------------------------------+----------------+
@@ -515,9 +527,9 @@ Library :
; Analysis & Synthesis Resource Utilization by Entity ; ; Analysis & Synthesis Resource Utilization by Entity ;
+--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+
Compilation Hierarchy Node : |spectrum Compilation Hierarchy Node : |spectrum
LC Combinationals : 33 (33) LC Combinationals : 52 (44)
LC Registers : 24 (24) LC Registers : 38 (36)
Memory Bits : 64 Memory Bits : 131072
DSP Elements : 0 DSP Elements : 0
DSP 9x9 : 0 DSP 9x9 : 0
DSP 18x18 : 0 DSP 18x18 : 0
@@ -527,9 +539,9 @@ Full Hierarchy Name : |spectrum
Library Name : work Library Name : work
Compilation Hierarchy Node : |rom0:rom| Compilation Hierarchy Node : |rom0:rom|
LC Combinationals : 0 (0) LC Combinationals : 8 (0)
LC Registers : 0 (0) LC Registers : 2 (0)
Memory Bits : 64 Memory Bits : 131072
DSP Elements : 0 DSP Elements : 0
DSP 9x9 : 0 DSP 9x9 : 0
DSP 18x18 : 0 DSP 18x18 : 0
@@ -539,9 +551,9 @@ Full Hierarchy Name : |spectrum|rom0:rom
Library Name : work Library Name : work
Compilation Hierarchy Node : |altsyncram:altsyncram_component| Compilation Hierarchy Node : |altsyncram:altsyncram_component|
LC Combinationals : 0 (0) LC Combinationals : 8 (0)
LC Registers : 0 (0) LC Registers : 2 (0)
Memory Bits : 64 Memory Bits : 131072
DSP Elements : 0 DSP Elements : 0
DSP 9x9 : 0 DSP 9x9 : 0
DSP 18x18 : 0 DSP 18x18 : 0
@@ -550,16 +562,28 @@ Virtual Pins : 0
Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component
Library Name : work Library Name : work
Compilation Hierarchy Node : |altsyncram_ro91:auto_generated| Compilation Hierarchy Node : |altsyncram_qh91:auto_generated|
LC Combinationals : 0 (0) LC Combinationals : 8 (0)
LC Registers : 0 (0) LC Registers : 2 (2)
Memory Bits : 64 Memory Bits : 131072
DSP Elements : 0 DSP Elements : 0
DSP 9x9 : 0 DSP 9x9 : 0
DSP 18x18 : 0 DSP 18x18 : 0
Pins : 0 Pins : 0
Virtual Pins : 0 Virtual Pins : 0
Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated
Library Name : work
Compilation Hierarchy Node : |mux_3nb:mux2|
LC Combinationals : 8 (8)
LC Registers : 0 (0)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|mux_3nb:mux2
Library Name : work Library Name : work
+--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+
@@ -569,15 +593,15 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ; ; Analysis & Synthesis RAM Summary ;
+--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+
Name : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ALTSYNCRAM Name : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM
Type : AUTO Type : AUTO
Mode : ROM Mode : ROM
Port A Depth : 8 Port A Depth : 16384
Port A Width : 8 Port A Width : 8
Port B Depth : -- Port B Depth : --
Port B Width : -- Port B Width : --
Size : 64 Size : 131072
MIF : led_patterns.mif MIF : ./rom/gw03.hex
+--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+
@@ -601,18 +625,18 @@ IP Include File : /home/benny/work/fpga/projects/rom0.v
+----------------------------------------------+-------+ +----------------------------------------------+-------+
; Statistic ; Value ; ; Statistic ; Value ;
+----------------------------------------------+-------+ +----------------------------------------------+-------+
; Total registers ; 24 ; ; Total registers ; 38 ;
; Number of registers using Synchronous Clear ; 0 ; ; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ; ; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ; ; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ; ; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ; ; Number of registers using Clock Enable ; 13 ;
; Number of registers using Preset ; 0 ; ; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+ +----------------------------------------------+-------+
+--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+
; Source assignments for rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated ; ; Source assignments for rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated ;
+--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+
Assignment : OPTIMIZE_POWER_DURING_SYNTHESIS Assignment : OPTIMIZE_POWER_DURING_SYNTHESIS
Value : NORMAL_COMPILATION Value : NORMAL_COMPILATION
@@ -658,11 +682,11 @@ Value : 8
Type : Signed Integer Type : Signed Integer
Parameter Name : WIDTHAD_A Parameter Name : WIDTHAD_A
Value : 3 Value : 14
Type : Signed Integer Type : Signed Integer
Parameter Name : NUMWORDS_A Parameter Name : NUMWORDS_A
Value : 8 Value : 16384
Type : Signed Integer Type : Signed Integer
Parameter Name : OUTDATA_REG_A Parameter Name : OUTDATA_REG_A
@@ -778,7 +802,7 @@ Value : NEW_DATA_NO_NBE_READ
Type : Untyped Type : Untyped
Parameter Name : INIT_FILE Parameter Name : INIT_FILE
Value : led_patterns.mif Value : ./rom/gw03.hex
Type : Untyped Type : Untyped
Parameter Name : INIT_FILE_LAYOUT Parameter Name : INIT_FILE_LAYOUT
@@ -830,7 +854,7 @@ Value : Cyclone IV E
Type : Untyped Type : Untyped
Parameter Name : CBXI_PARAMETER Parameter Name : CBXI_PARAMETER
Value : altsyncram_ro91 Value : altsyncram_qh91
Type : Untyped Type : Untyped
+--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+
@@ -846,7 +870,7 @@ Note: In order to hide this table in the UI and the text report file, please set
; Entity Instance ; rom0:rom|altsyncram:altsyncram_component ; ; Entity Instance ; rom0:rom|altsyncram:altsyncram_component ;
; -- OPERATION_MODE ; ROM ; ; -- OPERATION_MODE ; ROM ;
; -- WIDTH_A ; 8 ; ; -- WIDTH_A ; 8 ;
; -- NUMWORDS_A ; 8 ; ; -- NUMWORDS_A ; 16384 ;
; -- OUTDATA_REG_A ; CLOCK0 ; ; -- OUTDATA_REG_A ; CLOCK0 ;
; -- WIDTH_B ; 1 ; ; -- WIDTH_B ; 1 ;
; -- NUMWORDS_B ; 1 ; ; -- NUMWORDS_B ; 1 ;
@@ -872,7 +896,7 @@ Note: In order to hide this table in the UI and the text report file, please set
Info: ******************************************************************* Info: *******************************************************************
Info: Running Quartus II 32-bit Analysis & Synthesis Info: Running Quartus II 32-bit Analysis & Synthesis
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
Info: Processing started: Wed Mar 30 12:38:26 2022 Info: Processing started: Wed Mar 30 13:12:11 2022
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum Info: Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum
Warning (20028): Parallel compilation is not licensed and has been disabled Warning (20028): Parallel compilation is not licensed and has been disabled
Info (12021): Found 1 design units, including 1 entities, in source file spectrum.v Info (12021): Found 1 design units, including 1 entities, in source file spectrum.v
@@ -880,8 +904,8 @@ Info (12021): Found 1 design units, including 1 entities, in source file spectru
Info (12021): Found 1 design units, including 1 entities, in source file rom0.v Info (12021): Found 1 design units, including 1 entities, in source file rom0.v
Info (12023): Found entity 1: rom0 Info (12023): Found entity 1: rom0
Info (12127): Elaborating entity "spectrum" for the top level hierarchy Info (12127): Elaborating entity "spectrum" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at spectrum.v(19): truncated value with size 32 to match size of target (21) Warning (10230): Verilog HDL assignment warning at spectrum.v(18): truncated value with size 32 to match size of target (22)
Warning (10230): Verilog HDL assignment warning at spectrum.v(21): truncated value with size 32 to match size of target (3) Warning (10230): Verilog HDL assignment warning at spectrum.v(20): truncated value with size 32 to match size of target (14)
Info (12128): Elaborating entity "rom0" for hierarchy "rom0:rom" Info (12128): Elaborating entity "rom0" for hierarchy "rom0:rom"
Info (12128): Elaborating entity "altsyncram" for hierarchy "rom0:rom|altsyncram:altsyncram_component" Info (12128): Elaborating entity "altsyncram" for hierarchy "rom0:rom|altsyncram:altsyncram_component"
Info (12130): Elaborated megafunction instantiation "rom0:rom|altsyncram:altsyncram_component" Info (12130): Elaborated megafunction instantiation "rom0:rom|altsyncram:altsyncram_component"
@@ -889,32 +913,38 @@ Info (12133): Instantiated megafunction "rom0:rom|altsyncram:altsyncram_componen
Info (12134): Parameter "address_aclr_a" = "NONE" Info (12134): Parameter "address_aclr_a" = "NONE"
Info (12134): Parameter "clock_enable_input_a" = "BYPASS" Info (12134): Parameter "clock_enable_input_a" = "BYPASS"
Info (12134): Parameter "clock_enable_output_a" = "BYPASS" Info (12134): Parameter "clock_enable_output_a" = "BYPASS"
Info (12134): Parameter "init_file" = "led_patterns.mif" Info (12134): Parameter "init_file" = "./rom/gw03.hex"
Info (12134): Parameter "intended_device_family" = "Cyclone IV E" Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
Info (12134): Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO" Info (12134): Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO"
Info (12134): Parameter "lpm_type" = "altsyncram" Info (12134): Parameter "lpm_type" = "altsyncram"
Info (12134): Parameter "numwords_a" = "8" Info (12134): Parameter "numwords_a" = "16384"
Info (12134): Parameter "operation_mode" = "ROM" Info (12134): Parameter "operation_mode" = "ROM"
Info (12134): Parameter "outdata_aclr_a" = "NONE" Info (12134): Parameter "outdata_aclr_a" = "NONE"
Info (12134): Parameter "outdata_reg_a" = "CLOCK0" Info (12134): Parameter "outdata_reg_a" = "CLOCK0"
Info (12134): Parameter "widthad_a" = "3" Info (12134): Parameter "widthad_a" = "14"
Info (12134): Parameter "width_a" = "8" Info (12134): Parameter "width_a" = "8"
Info (12134): Parameter "width_byteena_a" = "1" Info (12134): Parameter "width_byteena_a" = "1"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_ro91.tdf Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_qh91.tdf
Info (12023): Found entity 1: altsyncram_ro91 Info (12023): Found entity 1: altsyncram_qh91
Info (12128): Elaborating entity "altsyncram_ro91" for hierarchy "rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated" Info (12128): Elaborating entity "altsyncram_qh91" for hierarchy "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated"
Info (12021): Found 1 design units, including 1 entities, in source file db/decode_c8a.tdf
Info (12023): Found entity 1: decode_c8a
Info (12128): Elaborating entity "decode_c8a" for hierarchy "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|decode_c8a:rden_decode"
Info (12021): Found 1 design units, including 1 entities, in source file db/mux_3nb.tdf
Info (12023): Found entity 1: mux_3nb
Info (12128): Elaborating entity "mux_3nb" for hierarchy "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|mux_3nb:mux2"
Info (286030): Timing-Driven Synthesis is running Info (286030): Timing-Driven Synthesis is running
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Info (21057): Implemented 71 device resources after synthesis - the final resource count might be different Info (21057): Implemented 79 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 1 input pins Info (21058): Implemented 1 input pins
Info (21059): Implemented 8 output pins Info (21059): Implemented 8 output pins
Info (21061): Implemented 54 logic cells Info (21061): Implemented 54 logic cells
Info (21064): Implemented 8 RAM segments Info (21064): Implemented 16 RAM segments
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 3 warnings Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 3 warnings
Info: Peak virtual memory: 384 megabytes Info: Peak virtual memory: 392 megabytes
Info: Processing ended: Wed Mar 30 12:38:28 2022 Info: Processing ended: Wed Mar 30 13:12:13 2022
Info: Elapsed time: 00:00:02 Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:01 Info: Total CPU time (on all processors): 00:00:02
output_files/spectrum.map.summary
+6 -6
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@@ -1,14 +1,14 @@
Analysis & Synthesis Status : Successful - Wed Mar 30 12:38:28 2022 Analysis & Synthesis Status : Successful - Wed Mar 30 13:12:13 2022
Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
Revision Name : spectrum Revision Name : spectrum
Top-level Entity Name : spectrum Top-level Entity Name : spectrum
Family : Cyclone IV E Family : Cyclone IV E
Total logic elements : 33 Total logic elements : 54
Total combinational functions : 33 Total combinational functions : 52
Dedicated logic registers : 24 Dedicated logic registers : 38
Total registers : 24 Total registers : 38
Total pins : 9 Total pins : 9
Total virtual pins : 0 Total virtual pins : 0
Total memory bits : 64 Total memory bits : 131,072
Embedded Multiplier 9-bit elements : 0 Embedded Multiplier 9-bit elements : 0
Total PLLs : 0 Total PLLs : 0
output_files/spectrum.sof
BIN
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Binary file not shown.
output_files/spectrum.sta.rpt
+6107 -6107
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File diff suppressed because it is too large Load Diff
output_files/spectrum.sta.summary
+12 -12
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@@ -3,39 +3,39 @@ TimeQuest Timing Analyzer Summary
------------------------------------------------------------ ------------------------------------------------------------
Type : Slow 1200mV 85C Model Setup 'CLOCK_50' Type : Slow 1200mV 85C Model Setup 'CLOCK_50'
Slack : -2.763 Slack : -1.788
TNS : -43.394 TNS : -88.557
Type : Slow 1200mV 85C Model Hold 'CLOCK_50' Type : Slow 1200mV 85C Model Hold 'CLOCK_50'
Slack : 0.343 Slack : 0.260
TNS : 0.000 TNS : 0.000
Type : Slow 1200mV 85C Model Minimum Pulse Width 'CLOCK_50' Type : Slow 1200mV 85C Model Minimum Pulse Width 'CLOCK_50'
Slack : -3.000 Slack : -3.000
TNS : -46.633 TNS : -110.836
Type : Slow 1200mV 0C Model Setup 'CLOCK_50' Type : Slow 1200mV 0C Model Setup 'CLOCK_50'
Slack : -2.331 Slack : -1.527
TNS : -34.994 TNS : -72.611
Type : Slow 1200mV 0C Model Hold 'CLOCK_50' Type : Slow 1200mV 0C Model Hold 'CLOCK_50'
Slack : 0.299 Slack : 0.255
TNS : 0.000 TNS : 0.000
Type : Slow 1200mV 0C Model Minimum Pulse Width 'CLOCK_50' Type : Slow 1200mV 0C Model Minimum Pulse Width 'CLOCK_50'
Slack : -3.000 Slack : -3.000
TNS : -46.624 TNS : -110.824
Type : Fast 1200mV 0C Model Setup 'CLOCK_50' Type : Fast 1200mV 0C Model Setup 'CLOCK_50'
Slack : -1.122 Slack : -0.529
TNS : -9.363 TNS : -18.538
Type : Fast 1200mV 0C Model Hold 'CLOCK_50' Type : Fast 1200mV 0C Model Hold 'CLOCK_50'
Slack : 0.178 Slack : 0.123
TNS : 0.000 TNS : 0.000
Type : Fast 1200mV 0C Model Minimum Pulse Width 'CLOCK_50' Type : Fast 1200mV 0C Model Minimum Pulse Width 'CLOCK_50'
Slack : -3.000 Slack : -3.000
TNS : -45.480 TNS : -93.684
------------------------------------------------------------ ------------------------------------------------------------
rom/gw03.hex
+514
View File
@@ -0,0 +1,514 @@
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rom/gw03.rom
BIN
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rom0.cnx
-98
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@@ -1,98 +0,0 @@
VERSION: WM1.0
MODULE: altsyncram
PRIVATE: ADDRESSSTALL_A NUMERIC "0"
PRIVATE: AclrAddr NUMERIC "0"
PRIVATE: AclrByte NUMERIC "0"
PRIVATE: AclrOutput NUMERIC "0"
PRIVATE: BYTE_ENABLE NUMERIC "0"
PRIVATE: BYTE_SIZE NUMERIC "8"
PRIVATE: BlankMemory NUMERIC "0"
PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
PRIVATE: Clken NUMERIC "0"
PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
PRIVATE: INIT_TO_SIM_X NUMERIC "0"
PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
PRIVATE: JTAG_ENABLED NUMERIC "0"
PRIVATE: JTAG_ID STRING "NONE"
PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
PRIVATE: MIFfilename STRING "led_patterns.mif"
PRIVATE: NUMWORDS_A NUMERIC "8"
PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
PRIVATE: RegAddr NUMERIC "1"
PRIVATE: RegOutput NUMERIC "1"
PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
PRIVATE: SingleClock NUMERIC "1"
PRIVATE: UseDQRAM NUMERIC "0"
PRIVATE: WidthAddr NUMERIC "3"
PRIVATE: WidthData NUMERIC "8"
PRIVATE: rden NUMERIC "0"
LIBRARY: altera_mf altera_mf.altera_mf_components.all
CONSTANT: ADDRESS_ACLR_A STRING "NONE"
CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
CONSTANT: INIT_FILE STRING "led_patterns.mif"
CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
CONSTANT: LPM_TYPE STRING "altsyncram"
CONSTANT: NUMWORDS_A NUMERIC "8"
CONSTANT: OPERATION_MODE STRING "ROM"
CONSTANT: OUTDATA_ACLR_A STRING "NONE"
CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
CONSTANT: WIDTHAD_A NUMERIC "3"
CONSTANT: WIDTH_A NUMERIC "8"
CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
USED_PORT: address 0 0 3 0 INPUT NODEFVAL "address[2..0]"
USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
CONNECT: @address_a 0 0 3 0 address 0 0 3 0
CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
CONNECT: q 0 0 8 0 @q_a 0 0 8 0
GEN_FILE: TYPE_NORMAL rom0.v TRUE
GEN_FILE: TYPE_NORMAL rom0.inc FALSE
GEN_FILE: TYPE_NORMAL rom0.cmp FALSE
GEN_FILE: TYPE_NORMAL rom0.bsf FALSE
GEN_FILE: TYPE_NORMAL rom0_inst.v FALSE
GEN_FILE: TYPE_NORMAL rom0_bb.v TRUE
LIB_FILE: altera_mf
LICENSE_ID: "DEVICE_FAMILY_Cyclone III" 30229803K6032210322T
LICENSE_ID: "DEVICE_FAMILY_Cyclone IV E" 30229803A6032210322A
LICENSE_ID: "DEVICE_FAMILY_Cyclone V" 30229803A6032210322B
LICENSE_ID: "DEVICE_FAMILY_Cyclone IV GX" 30229803A6032210322B
LICENSE_ID: "DEVICE_FAMILY_Cyclone III LS" 30229803A6032210322B
LICENSE_ID: "FEATURE_STRATIXGX_DPA" 30229803M6032210322T
LICENSE_ID: "FEATURE_STRATIXGX_BASIC" 30229803A6032210322B
SUPPORTED_DEVICE_FAMILY: "Cyclone III"
SUPPORTED_DEVICE_FAMILY: "Cyclone IV E"
SUPPORTED_DEVICE_FAMILY: "Cyclone V"
SUPPORTED_DEVICE_FAMILY: "Cyclone IV GX"
SUPPORTED_DEVICE_FAMILY: "Cyclone III LS"
SUPPORTED_DEVICE_FAMILY: "Cyclone IV E"
WIZARD_TITLE: "ROM: 1-PORT"
QUARTUS_VERSION: "Version 13.1"
QUARTUS_SVERSION: "13.1.0 Build 162 10/23/2013 SJ Web Edition:10/23/2013"
QUARTUS_BUILD_DATE: "10/23/2013"
ALTERA_COPYRIGHT: "Copyright (C) 1991-2013 Altera Corporation"
RESC_INFO: ON
HELP_MENU_ITEM: FALSE "IUG_ALIAS$STRATIX_WEB_LINK$http://www.altera.com/literature/hb/stx/ch_3_vol_2.pdf"
HELP_MENU_ITEM: FALSE "ALIAS$STRATIX_WEB_MENU_LABEL$TriMatrix Memory Blocks in Stratix (GX)"
HELP_MENU_ITEM: FALSE "IUG_ALIAS$CYCLONE_IV_WEB_LINK$http://www.altera.com/literature/hb/cyclone-iv/cyiv-51003.pdf"
HELP_MENU_ITEM: FALSE "ALIAS$CYCLONE_IV_WEB_MENU_LABEL$Cyclone IV Memory Blocks"
HELP_MENU_ITEM: FALSE "IUG_ALIAS$CYCLONEII_WEB_LINK$http://www.altera.com/literature/hb/cyc2/cyc2_cii51008.pdf"
HELP_MENU_ITEM: FALSE "ALIAS$CYCLONEII_WEB_MENU_LABEL$Cyclone II Memory Blocks"
HELP_MENU_ITEM: FALSE "IUG_ALIAS$CYCLONE_WEB_LINK$http://www.altera.com/literature/hb/cyc/cyc_c51007.pdf"
HELP_MENU_ITEM: FALSE "ALIAS$CYCLONE_WEB_MENU_LABEL$Memory Implementations Using Cyclone Memory Blocks"
HELP_MENU_ITEM: FALSE "IUG_ALIAS$STRATIXII_WEB_LINK$http://www.altera.com/literature/hb/stx2/stx2_sii52002.pdf"
HELP_MENU_ITEM: FALSE "ALIAS$STRATIXII_WEB_MENU_LABEL$TriMatrix Memory Blocks in Stratix II"
HELP_MENU_ITEM: FALSE "IUG_ALIAS$STRATIXIII_WEB_LINK$http://www.altera.com/literature/hb/stx3/stx3_siii51004.pdf"
HELP_MENU_ITEM: FALSE "ALIAS$STRATIXIII_WEB_MENU_LABEL$TriMatrix Embedded Memory Blocks in Stratix III"
HELP_MENU_ITEM: FALSE "IUG_ALIAS$APEX_WEB_LINK$http://www.altera.com/literature/an/an179.pdf"
HELP_MENU_ITEM: FALSE "ALIAS$APEX_WEB_MENU_LABEL$Designing with ESBs"
HELP_MENU_ITEM: FALSE "IUG$ROM Megafunction User Guide$http://www.altera.com/literature/ug/ug_memrom.pdf"
rom0.v
+17 -12
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@@ -41,7 +41,7 @@ module rom0 (
clock, clock,
q); q);
input [2:0] address; input [13:0] address;
input clock; input clock;
output [7:0] q; output [7:0] q;
`ifndef ALTERA_RESERVED_QIS `ifndef ALTERA_RESERVED_QIS
@@ -83,15 +83,20 @@ module rom0 (
altsyncram_component.address_aclr_a = "NONE", altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS", altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS", altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "led_patterns.mif", `ifdef NO_PLI
altsyncram_component.init_file = "./rom/gw03.rif"
`else
altsyncram_component.init_file = "./rom/gw03.hex"
`endif
,
altsyncram_component.intended_device_family = "Cyclone IV E", altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram", altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 8, altsyncram_component.numwords_a = 16384,
altsyncram_component.operation_mode = "ROM", altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE", altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0", altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.widthad_a = 3, altsyncram_component.widthad_a = 14,
altsyncram_component.width_a = 8, altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1; altsyncram_component.width_byteena_a = 1;
@@ -118,36 +123,36 @@ endmodule
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" // Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "led_patterns.mif" // Retrieval info: PRIVATE: MIFfilename STRING "./rom/gw03.hex"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8" // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "16384"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1" // Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1" // Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1" // Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" // Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "3" // Retrieval info: PRIVATE: WidthAddr NUMERIC "14"
// Retrieval info: PRIVATE: WidthData NUMERIC "8" // Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0" // Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" // Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "led_patterns.mif" // Retrieval info: CONSTANT: INIT_FILE STRING "./rom/gw03.hex"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8" // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" // Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "3" // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" // Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 3 0 INPUT NODEFVAL "address[2..0]" // Retrieval info: USED_PORT: address 0 0 14 0 INPUT NODEFVAL "address[13..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" // Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: CONNECT: @address_a 0 0 3 0 address 0 0 3 0 // Retrieval info: CONNECT: @address_a 0 0 14 0 address 0 0 14 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 // Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL rom0.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL rom0.v TRUE
rom0_bb.v
+9 -9
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@@ -36,7 +36,7 @@ module rom0 (
clock, clock,
q); q);
input [2:0] address; input [13:0] address;
input clock; input clock;
output [7:0] q; output [7:0] q;
`ifndef ALTERA_RESERVED_QIS `ifndef ALTERA_RESERVED_QIS
@@ -69,36 +69,36 @@ endmodule
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" // Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "led_patterns.mif" // Retrieval info: PRIVATE: MIFfilename STRING "./rom/gw03.hex"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8" // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "16384"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1" // Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1" // Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1" // Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" // Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "3" // Retrieval info: PRIVATE: WidthAddr NUMERIC "14"
// Retrieval info: PRIVATE: WidthData NUMERIC "8" // Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0" // Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" // Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "led_patterns.mif" // Retrieval info: CONSTANT: INIT_FILE STRING "./rom/gw03.hex"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8" // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" // Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "3" // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" // Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 3 0 INPUT NODEFVAL "address[2..0]" // Retrieval info: USED_PORT: address 0 0 14 0 INPUT NODEFVAL "address[13..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" // Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: CONNECT: @address_a 0 0 3 0 address 0 0 3 0 // Retrieval info: CONNECT: @address_a 0 0 14 0 address 0 0 14 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 // Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL rom0.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL rom0.v TRUE
simulation/modelsim/spectrum.vo
+2086 -493
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simulation/modelsim/spectrum_6_1200mv_0c_slow.vo
+2086 -493
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simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo
+2208 -230
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simulation/modelsim/spectrum_6_1200mv_85c_slow.vo
+2086 -493
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simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo
+2215 -237
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simulation/modelsim/spectrum_min_1200mv_0c_fast.vo
+2086 -493
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simulation/modelsim/spectrum_min_1200mv_0c_v_fast.sdo
+2205 -227
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simulation/modelsim/spectrum_modelsim.xrf
+84 -30
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@@ -15,7 +15,10 @@ source_file = 1, /home/benny/altera/13.1/quartus/libraries/megafunctions/altrom.
source_file = 1, /home/benny/altera/13.1/quartus/libraries/megafunctions/altram.inc source_file = 1, /home/benny/altera/13.1/quartus/libraries/megafunctions/altram.inc
source_file = 1, /home/benny/altera/13.1/quartus/libraries/megafunctions/altdpram.inc source_file = 1, /home/benny/altera/13.1/quartus/libraries/megafunctions/altdpram.inc
source_file = 1, /home/benny/altera/13.1/quartus/libraries/megafunctions/cbx.lst source_file = 1, /home/benny/altera/13.1/quartus/libraries/megafunctions/cbx.lst
source_file = 1, /home/benny/work/fpga/projects/db/altsyncram_ro91.tdf source_file = 1, /home/benny/work/fpga/projects/db/altsyncram_qh91.tdf
source_file = 1, /home/benny/work/fpga/projects/rom/gw03.hex
source_file = 1, /home/benny/work/fpga/projects/db/decode_c8a.tdf
source_file = 1, /home/benny/work/fpga/projects/db/mux_3nb.tdf
design_name = spectrum design_name = spectrum
instance = comp, \LED[0]~output , LED[0]~output, spectrum, 1 instance = comp, \LED[0]~output , LED[0]~output, spectrum, 1
instance = comp, \LED[1]~output , LED[1]~output, spectrum, 1 instance = comp, \LED[1]~output , LED[1]~output, spectrum, 1
@@ -27,61 +30,112 @@ instance = comp, \LED[6]~output , LED[6]~output, spectrum, 1
instance = comp, \LED[7]~output , LED[7]~output, spectrum, 1 instance = comp, \LED[7]~output , LED[7]~output, spectrum, 1
instance = comp, \CLOCK_50~input , CLOCK_50~input, spectrum, 1 instance = comp, \CLOCK_50~input , CLOCK_50~input, spectrum, 1
instance = comp, \CLOCK_50~inputclkctrl , CLOCK_50~inputclkctrl, spectrum, 1 instance = comp, \CLOCK_50~inputclkctrl , CLOCK_50~inputclkctrl, spectrum, 1
instance = comp, \counter[20] , counter[20], spectrum, 1 instance = comp, \counter[0]~63 , counter[0]~63, spectrum, 1
instance = comp, \Add0~0 , Add0~0, spectrum, 1
instance = comp, \counter[0] , counter[0], spectrum, 1 instance = comp, \counter[0] , counter[0], spectrum, 1
instance = comp, \Add0~2 , Add0~2, spectrum, 1 instance = comp, \counter[1]~21 , counter[1]~21, spectrum, 1
instance = comp, \counter[1] , counter[1], spectrum, 1 instance = comp, \counter[1] , counter[1], spectrum, 1
instance = comp, \Add0~4 , Add0~4, spectrum, 1 instance = comp, \counter[2]~23 , counter[2]~23, spectrum, 1
instance = comp, \counter[2] , counter[2], spectrum, 1 instance = comp, \counter[2] , counter[2], spectrum, 1
instance = comp, \Add0~6 , Add0~6, spectrum, 1 instance = comp, \counter[3]~25 , counter[3]~25, spectrum, 1
instance = comp, \counter[3] , counter[3], spectrum, 1 instance = comp, \counter[3] , counter[3], spectrum, 1
instance = comp, \Add0~8 , Add0~8, spectrum, 1 instance = comp, \counter[4]~27 , counter[4]~27, spectrum, 1
instance = comp, \counter[4] , counter[4], spectrum, 1 instance = comp, \counter[4] , counter[4], spectrum, 1
instance = comp, \Add0~10 , Add0~10, spectrum, 1 instance = comp, \counter[5]~29 , counter[5]~29, spectrum, 1
instance = comp, \counter[5] , counter[5], spectrum, 1 instance = comp, \counter[5] , counter[5], spectrum, 1
instance = comp, \Add0~12 , Add0~12, spectrum, 1 instance = comp, \counter[6]~31 , counter[6]~31, spectrum, 1
instance = comp, \counter[6] , counter[6], spectrum, 1 instance = comp, \counter[6] , counter[6], spectrum, 1
instance = comp, \Add0~14 , Add0~14, spectrum, 1 instance = comp, \counter[7]~33 , counter[7]~33, spectrum, 1
instance = comp, \counter[7] , counter[7], spectrum, 1 instance = comp, \counter[7] , counter[7], spectrum, 1
instance = comp, \Add0~16 , Add0~16, spectrum, 1 instance = comp, \counter[8]~35 , counter[8]~35, spectrum, 1
instance = comp, \counter[8] , counter[8], spectrum, 1 instance = comp, \counter[8] , counter[8], spectrum, 1
instance = comp, \Add0~18 , Add0~18, spectrum, 1 instance = comp, \counter[9]~37 , counter[9]~37, spectrum, 1
instance = comp, \counter[9] , counter[9], spectrum, 1 instance = comp, \counter[9] , counter[9], spectrum, 1
instance = comp, \Add0~20 , Add0~20, spectrum, 1 instance = comp, \counter[10]~39 , counter[10]~39, spectrum, 1
instance = comp, \counter[10] , counter[10], spectrum, 1 instance = comp, \counter[10] , counter[10], spectrum, 1
instance = comp, \Add0~22 , Add0~22, spectrum, 1 instance = comp, \counter[11]~41 , counter[11]~41, spectrum, 1
instance = comp, \counter[11]~feeder , counter[11]~feeder, spectrum, 1
instance = comp, \counter[11] , counter[11], spectrum, 1 instance = comp, \counter[11] , counter[11], spectrum, 1
instance = comp, \Add0~24 , Add0~24, spectrum, 1 instance = comp, \counter[12]~43 , counter[12]~43, spectrum, 1
instance = comp, \counter[12] , counter[12], spectrum, 1 instance = comp, \counter[12] , counter[12], spectrum, 1
instance = comp, \Add0~26 , Add0~26, spectrum, 1 instance = comp, \counter[13]~45 , counter[13]~45, spectrum, 1
instance = comp, \counter[13] , counter[13], spectrum, 1 instance = comp, \counter[13] , counter[13], spectrum, 1
instance = comp, \Add0~28 , Add0~28, spectrum, 1 instance = comp, \counter[14]~47 , counter[14]~47, spectrum, 1
instance = comp, \counter[14] , counter[14], spectrum, 1 instance = comp, \counter[14] , counter[14], spectrum, 1
instance = comp, \Add0~30 , Add0~30, spectrum, 1 instance = comp, \counter[15]~49 , counter[15]~49, spectrum, 1
instance = comp, \counter[15] , counter[15], spectrum, 1 instance = comp, \counter[15] , counter[15], spectrum, 1
instance = comp, \Add0~32 , Add0~32, spectrum, 1 instance = comp, \counter[16]~51 , counter[16]~51, spectrum, 1
instance = comp, \counter[16] , counter[16], spectrum, 1 instance = comp, \counter[16] , counter[16], spectrum, 1
instance = comp, \Add0~34 , Add0~34, spectrum, 1 instance = comp, \counter[17]~53 , counter[17]~53, spectrum, 1
instance = comp, \counter[17] , counter[17], spectrum, 1 instance = comp, \counter[17] , counter[17], spectrum, 1
instance = comp, \Add0~36 , Add0~36, spectrum, 1 instance = comp, \counter[18]~55 , counter[18]~55, spectrum, 1
instance = comp, \counter[18] , counter[18], spectrum, 1 instance = comp, \counter[18] , counter[18], spectrum, 1
instance = comp, \Add0~38 , Add0~38, spectrum, 1 instance = comp, \counter[19]~57 , counter[19]~57, spectrum, 1
instance = comp, \counter[19] , counter[19], spectrum, 1 instance = comp, \counter[19] , counter[19], spectrum, 1
instance = comp, \Add0~40 , Add0~40, spectrum, 1
instance = comp, \Equal0~5 , Equal0~5, spectrum, 1 instance = comp, \Equal0~5 , Equal0~5, spectrum, 1
instance = comp, \Equal0~1 , Equal0~1, spectrum, 1
instance = comp, \Equal0~0 , Equal0~0, spectrum, 1 instance = comp, \Equal0~0 , Equal0~0, spectrum, 1
instance = comp, \Equal0~1 , Equal0~1, spectrum, 1
instance = comp, \Equal0~2 , Equal0~2, spectrum, 1 instance = comp, \Equal0~2 , Equal0~2, spectrum, 1
instance = comp, \Equal0~3 , Equal0~3, spectrum, 1 instance = comp, \Equal0~3 , Equal0~3, spectrum, 1
instance = comp, \Equal0~4 , Equal0~4, spectrum, 1 instance = comp, \Equal0~4 , Equal0~4, spectrum, 1
instance = comp, \address[0]~0 , address[0]~0, spectrum, 1 instance = comp, \counter[20]~59 , counter[20]~59, spectrum, 1
instance = comp, \address[0] , address[0], spectrum, 1 instance = comp, \counter[20] , counter[20], spectrum, 1
instance = comp, \Equal0~6 , Equal0~6, spectrum, 1 instance = comp, \counter[21]~61 , counter[21]~61, spectrum, 1
instance = comp, \counter[21] , counter[21], spectrum, 1
instance = comp, \Equal0~7 , Equal0~7, spectrum, 1 instance = comp, \Equal0~7 , Equal0~7, spectrum, 1
instance = comp, \address[1]~1 , address[1]~1, spectrum, 1 instance = comp, \address[0]~39 , address[0]~39, spectrum, 1
instance = comp, \address[0] , address[0], spectrum, 1
instance = comp, \address[1]~13 , address[1]~13, spectrum, 1
instance = comp, \Equal0~6 , Equal0~6, spectrum, 1
instance = comp, \address[1] , address[1], spectrum, 1 instance = comp, \address[1] , address[1], spectrum, 1
instance = comp, \address[1]~2 , address[1]~2, spectrum, 1 instance = comp, \address[2]~15 , address[2]~15, spectrum, 1
instance = comp, \address[2]~3 , address[2]~3, spectrum, 1
instance = comp, \address[2] , address[2], spectrum, 1 instance = comp, \address[2] , address[2], spectrum, 1
instance = comp, \address[3]~17 , address[3]~17, spectrum, 1
instance = comp, \address[3] , address[3], spectrum, 1
instance = comp, \address[4]~19 , address[4]~19, spectrum, 1
instance = comp, \address[4] , address[4], spectrum, 1
instance = comp, \address[5]~21 , address[5]~21, spectrum, 1
instance = comp, \address[5] , address[5], spectrum, 1
instance = comp, \address[6]~23 , address[6]~23, spectrum, 1
instance = comp, \address[6] , address[6], spectrum, 1
instance = comp, \address[7]~25 , address[7]~25, spectrum, 1
instance = comp, \address[7] , address[7], spectrum, 1
instance = comp, \address[8]~27 , address[8]~27, spectrum, 1
instance = comp, \address[8] , address[8], spectrum, 1
instance = comp, \address[9]~29 , address[9]~29, spectrum, 1
instance = comp, \address[9] , address[9], spectrum, 1
instance = comp, \address[10]~31 , address[10]~31, spectrum, 1
instance = comp, \address[10] , address[10], spectrum, 1
instance = comp, \address[11]~33 , address[11]~33, spectrum, 1
instance = comp, \address[11] , address[11], spectrum, 1
instance = comp, \address[12]~35 , address[12]~35, spectrum, 1
instance = comp, \address[12] , address[12], spectrum, 1
instance = comp, \address[13]~37 , address[13]~37, spectrum, 1
instance = comp, \address[13] , address[13], spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder , rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|address_reg_a[0] , rom|altsyncram_component|auto_generated|address_reg_a[0], spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder , rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|out_address_reg_a[0] , rom|altsyncram_component|auto_generated|out_address_reg_a[0], spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a8 , rom|altsyncram_component|auto_generated|ram_block1a8, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a0 , rom|altsyncram_component|auto_generated|ram_block1a0, spectrum, 1 instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a0 , rom|altsyncram_component|auto_generated|ram_block1a0, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0 , rom|altsyncram_component|auto_generated|mux2|result_node[0]~0, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a1 , rom|altsyncram_component|auto_generated|ram_block1a1, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a9 , rom|altsyncram_component|auto_generated|ram_block1a9, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1 , rom|altsyncram_component|auto_generated|mux2|result_node[1]~1, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a2 , rom|altsyncram_component|auto_generated|ram_block1a2, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a10 , rom|altsyncram_component|auto_generated|ram_block1a10, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2 , rom|altsyncram_component|auto_generated|mux2|result_node[2]~2, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a11 , rom|altsyncram_component|auto_generated|ram_block1a11, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a3 , rom|altsyncram_component|auto_generated|ram_block1a3, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3 , rom|altsyncram_component|auto_generated|mux2|result_node[3]~3, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a4 , rom|altsyncram_component|auto_generated|ram_block1a4, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a12 , rom|altsyncram_component|auto_generated|ram_block1a12, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4 , rom|altsyncram_component|auto_generated|mux2|result_node[4]~4, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a13 , rom|altsyncram_component|auto_generated|ram_block1a13, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a5 , rom|altsyncram_component|auto_generated|ram_block1a5, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5 , rom|altsyncram_component|auto_generated|mux2|result_node[5]~5, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a14 , rom|altsyncram_component|auto_generated|ram_block1a14, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a6 , rom|altsyncram_component|auto_generated|ram_block1a6, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6 , rom|altsyncram_component|auto_generated|mux2|result_node[6]~6, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a7 , rom|altsyncram_component|auto_generated|ram_block1a7, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a15 , rom|altsyncram_component|auto_generated|ram_block1a15, spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7 , rom|altsyncram_component|auto_generated|mux2|result_node[7]~7, spectrum, 1
simulation/modelsim/spectrum_v.sdo
+2215 -237
View File
File diff suppressed because it is too large Load Diff
spectrum.v
+4 -4
View File
@@ -3,7 +3,7 @@ module spectrum(
output wire[7:0] LED output wire[7:0] LED
); );
reg[2:0] address; reg[13:0] address;
wire[7:0] mem_data; wire[7:0] mem_data;
rom0 rom( rom0 rom(
@@ -12,12 +12,12 @@ rom0 rom(
.q(mem_data) .q(mem_data)
); );
reg[20:0] counter; reg[21:0] counter;
always @(posedge CLOCK_50) always @(posedge CLOCK_50)
begin begin
counter = counter + 1; counter <= counter + 1;
if (counter == 0) if (counter == 0)
address = address + 1; address <= address + 1;
end end
assign LED = mem_data; assign LED = mem_data;