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9d6eb7a9faa86667827181dc7f534b5a360972fc
de0-zx-spectrum/simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo
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benny 9d6eb7a9fa ROM0 now has the spectrum rom
2022-03-30 13:18:06 +03:00

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// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//
// Device: Altera EP4CE22F17C6 Package FBGA256
//
//
// This file contains Slow Corner delays for the design using part EP4CE22F17C6,
// with speed grade 6, core voltage 1.2V, and temperature 85 Celsius
//
//
// This SDF file should be used for ModelSim-Altera (Verilog) only
//
(DELAYFILE
(SDFVERSION "2.1")
(DESIGN "spectrum")
(DATE "03/30/2022 13:12:28")
(VENDOR "Altera")
(PROGRAM "Quartus II 32-bit")
(VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
(DIVIDER .)
(TIMESCALE 1 ps)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE LED\[0\]\~output)
(DELAY
(ABSOLUTE
(PORT i (1643:1643:1643) (1694:1694:1694))
(IOPATH i o (2535:2535:2535) (2445:2445:2445))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE LED\[1\]\~output)
(DELAY
(ABSOLUTE
(PORT i (1565:1565:1565) (1603:1603:1603))
(IOPATH i o (2535:2535:2535) (2445:2445:2445))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE LED\[2\]\~output)
(DELAY
(ABSOLUTE
(PORT i (1737:1737:1737) (1749:1749:1749))
(IOPATH i o (2535:2535:2535) (2445:2445:2445))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE LED\[3\]\~output)
(DELAY
(ABSOLUTE
(PORT i (1124:1124:1124) (1166:1166:1166))
(IOPATH i o (2535:2535:2535) (2445:2445:2445))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE LED\[4\]\~output)
(DELAY
(ABSOLUTE
(PORT i (1456:1456:1456) (1512:1512:1512))
(IOPATH i o (2582:2582:2582) (2502:2502:2502))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE LED\[5\]\~output)
(DELAY
(ABSOLUTE
(PORT i (2115:2115:2115) (2173:2173:2173))
(IOPATH i o (4477:4477:4477) (4127:4127:4127))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE LED\[6\]\~output)
(DELAY
(ABSOLUTE
(PORT i (2428:2428:2428) (2433:2433:2433))
(IOPATH i o (2455:2455:2455) (2378:2378:2378))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE LED\[7\]\~output)
(DELAY
(ABSOLUTE
(PORT i (957:957:957) (1031:1031:1031))
(IOPATH i o (4477:4477:4477) (4127:4127:4127))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_ibuf")
(INSTANCE CLOCK_50\~input)
(DELAY
(ABSOLUTE
(IOPATH i o (479:479:479) (732:732:732))
)
)
)
(CELL
(CELLTYPE "cycloneive_clkctrl")
(INSTANCE CLOCK_50\~inputclkctrl)
(DELAY
(ABSOLUTE
(PORT inclk[0] (154:154:154) (138:138:138))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[0\]\~63)
(DELAY
(ABSOLUTE
(IOPATH datac combout (353:353:353) (369:369:369))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[0\])
(DELAY
(ABSOLUTE
(PORT clk (1532:1532:1532) (1545:1545:1545))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[1\]\~21)
(DELAY
(ABSOLUTE
(PORT dataa (253:253:253) (345:345:345))
(PORT datab (251:251:251) (336:336:336))
(IOPATH dataa combout (339:339:339) (367:367:367))
(IOPATH dataa cout (436:436:436) (315:315:315))
(IOPATH datab combout (344:344:344) (369:369:369))
(IOPATH datab cout (446:446:446) (318:318:318))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[1\])
(DELAY
(ABSOLUTE
(PORT clk (1532:1532:1532) (1545:1545:1545))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[2\]\~23)
(DELAY
(ABSOLUTE
(PORT datab (251:251:251) (336:336:336))
(IOPATH datab combout (365:365:365) (373:373:373))
(IOPATH datab cout (446:446:446) (318:318:318))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[2\])
(DELAY
(ABSOLUTE
(PORT clk (1532:1532:1532) (1545:1545:1545))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[3\]\~25)
(DELAY
(ABSOLUTE
(PORT datab (250:250:250) (335:335:335))
(IOPATH datab combout (355:355:355) (369:369:369))
(IOPATH datab cout (446:446:446) (318:318:318))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[3\])
(DELAY
(ABSOLUTE
(PORT clk (1532:1532:1532) (1545:1545:1545))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[4\]\~27)
(DELAY
(ABSOLUTE
(PORT datab (250:250:250) (335:335:335))
(IOPATH datab combout (365:365:365) (373:373:373))
(IOPATH datab cout (446:446:446) (318:318:318))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[4\])
(DELAY
(ABSOLUTE
(PORT clk (1532:1532:1532) (1545:1545:1545))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[5\]\~29)
(DELAY
(ABSOLUTE
(PORT datab (263:263:263) (346:346:346))
(IOPATH datab combout (355:355:355) (369:369:369))
(IOPATH datab cout (446:446:446) (318:318:318))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[5\])
(DELAY
(ABSOLUTE
(PORT clk (1532:1532:1532) (1545:1545:1545))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[6\]\~31)
(DELAY
(ABSOLUTE
(PORT dataa (252:252:252) (342:342:342))
(IOPATH dataa combout (356:356:356) (368:368:368))
(IOPATH dataa cout (436:436:436) (315:315:315))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[6\])
(DELAY
(ABSOLUTE
(PORT clk (1532:1532:1532) (1545:1545:1545))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[7\]\~33)
(DELAY
(ABSOLUTE
(PORT datab (250:250:250) (335:335:335))
(IOPATH datab combout (355:355:355) (369:369:369))
(IOPATH datab cout (446:446:446) (318:318:318))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[7\])
(DELAY
(ABSOLUTE
(PORT clk (1532:1532:1532) (1545:1545:1545))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[8\]\~35)
(DELAY
(ABSOLUTE
(PORT dataa (251:251:251) (341:341:341))
(IOPATH dataa combout (356:356:356) (368:368:368))
(IOPATH dataa cout (436:436:436) (315:315:315))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[8\])
(DELAY
(ABSOLUTE
(PORT clk (1532:1532:1532) (1545:1545:1545))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[9\]\~37)
(DELAY
(ABSOLUTE
(PORT datab (249:249:249) (333:333:333))
(IOPATH datab combout (355:355:355) (369:369:369))
(IOPATH datab cout (446:446:446) (318:318:318))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[9\])
(DELAY
(ABSOLUTE
(PORT clk (1532:1532:1532) (1545:1545:1545))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[10\]\~39)
(DELAY
(ABSOLUTE
(PORT dataa (252:252:252) (340:340:340))
(IOPATH dataa combout (356:356:356) (368:368:368))
(IOPATH dataa cout (436:436:436) (315:315:315))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[10\])
(DELAY
(ABSOLUTE
(PORT clk (1532:1532:1532) (1545:1545:1545))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[11\]\~41)
(DELAY
(ABSOLUTE
(PORT dataa (704:704:704) (765:765:765))
(IOPATH dataa combout (354:354:354) (367:367:367))
(IOPATH dataa cout (436:436:436) (315:315:315))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[11\]\~feeder)
(DELAY
(ABSOLUTE
(PORT datad (318:318:318) (335:335:335))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[11\])
(DELAY
(ABSOLUTE
(PORT clk (1532:1532:1532) (1545:1545:1545))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[12\]\~43)
(DELAY
(ABSOLUTE
(PORT datab (248:248:248) (333:333:333))
(IOPATH datab combout (365:365:365) (373:373:373))
(IOPATH datab cout (446:446:446) (318:318:318))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[12\])
(DELAY
(ABSOLUTE
(PORT clk (1532:1532:1532) (1545:1545:1545))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[13\]\~45)
(DELAY
(ABSOLUTE
(PORT datab (249:249:249) (335:335:335))
(IOPATH datab combout (355:355:355) (369:369:369))
(IOPATH datab cout (446:446:446) (318:318:318))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[13\])
(DELAY
(ABSOLUTE
(PORT clk (1532:1532:1532) (1545:1545:1545))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[14\]\~47)
(DELAY
(ABSOLUTE
(PORT dataa (251:251:251) (342:342:342))
(IOPATH dataa combout (356:356:356) (368:368:368))
(IOPATH dataa cout (436:436:436) (315:315:315))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[14\])
(DELAY
(ABSOLUTE
(PORT clk (1532:1532:1532) (1545:1545:1545))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[15\]\~49)
(DELAY
(ABSOLUTE
(PORT datab (251:251:251) (335:335:335))
(IOPATH datab combout (355:355:355) (369:369:369))
(IOPATH datab cout (446:446:446) (318:318:318))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[15\])
(DELAY
(ABSOLUTE
(PORT clk (1532:1532:1532) (1545:1545:1545))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[16\]\~51)
(DELAY
(ABSOLUTE
(PORT dataa (253:253:253) (343:343:343))
(IOPATH dataa combout (356:356:356) (368:368:368))
(IOPATH dataa cout (436:436:436) (315:315:315))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[16\])
(DELAY
(ABSOLUTE
(PORT clk (1532:1532:1532) (1545:1545:1545))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[17\]\~53)
(DELAY
(ABSOLUTE
(PORT dataa (253:253:253) (345:345:345))
(IOPATH dataa combout (354:354:354) (367:367:367))
(IOPATH dataa cout (436:436:436) (315:315:315))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[17\])
(DELAY
(ABSOLUTE
(PORT clk (1532:1532:1532) (1545:1545:1545))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[18\]\~55)
(DELAY
(ABSOLUTE
(PORT datab (252:252:252) (338:338:338))
(IOPATH datab combout (365:365:365) (373:373:373))
(IOPATH datab cout (446:446:446) (318:318:318))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[18\])
(DELAY
(ABSOLUTE
(PORT clk (1532:1532:1532) (1545:1545:1545))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[19\]\~57)
(DELAY
(ABSOLUTE
(PORT datab (252:252:252) (338:338:338))
(IOPATH datab combout (355:355:355) (369:369:369))
(IOPATH datab cout (446:446:446) (318:318:318))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[19\])
(DELAY
(ABSOLUTE
(PORT clk (1532:1532:1532) (1545:1545:1545))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE Equal0\~5)
(DELAY
(ABSOLUTE
(PORT dataa (254:254:254) (346:346:346))
(PORT datab (252:252:252) (336:336:336))
(PORT datac (225:225:225) (305:305:305))
(PORT datad (226:226:226) (300:300:300))
(IOPATH dataa combout (350:350:350) (366:366:366))
(IOPATH datab combout (350:350:350) (368:368:368))
(IOPATH datac combout (241:241:241) (241:241:241))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE Equal0\~0)
(DELAY
(ABSOLUTE
(PORT dataa (253:253:253) (343:343:343))
(PORT datab (250:250:250) (336:336:336))
(PORT datac (224:224:224) (302:302:302))
(PORT datad (225:225:225) (296:296:296))
(IOPATH dataa combout (350:350:350) (366:366:366))
(IOPATH datab combout (350:350:350) (368:368:368))
(IOPATH datac combout (241:241:241) (241:241:241))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE Equal0\~1)
(DELAY
(ABSOLUTE
(PORT dataa (253:253:253) (344:344:344))
(PORT datab (251:251:251) (337:337:337))
(PORT datac (381:381:381) (440:440:440))
(PORT datad (225:225:225) (297:297:297))
(IOPATH dataa combout (350:350:350) (366:366:366))
(IOPATH datab combout (350:350:350) (368:368:368))
(IOPATH datac combout (241:241:241) (241:241:241))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE Equal0\~2)
(DELAY
(ABSOLUTE
(PORT dataa (255:255:255) (347:347:347))
(PORT datab (262:262:262) (344:344:344))
(PORT datac (226:226:226) (308:308:308))
(PORT datad (228:228:228) (300:300:300))
(IOPATH dataa combout (350:350:350) (366:366:366))
(IOPATH datab combout (350:350:350) (368:368:368))
(IOPATH datac combout (241:241:241) (241:241:241))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE Equal0\~3)
(DELAY
(ABSOLUTE
(PORT dataa (254:254:254) (346:346:346))
(PORT datab (253:253:253) (339:339:339))
(PORT datac (225:225:225) (305:305:305))
(PORT datad (227:227:227) (300:300:300))
(IOPATH dataa combout (350:350:350) (366:366:366))
(IOPATH datab combout (350:350:350) (368:368:368))
(IOPATH datac combout (241:241:241) (241:241:241))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE Equal0\~4)
(DELAY
(ABSOLUTE
(PORT dataa (337:337:337) (370:370:370))
(PORT datab (345:345:345) (370:370:370))
(PORT datac (335:335:335) (354:354:354))
(PORT datad (589:589:589) (601:601:601))
(IOPATH dataa combout (300:300:300) (307:307:307))
(IOPATH datab combout (300:300:300) (308:308:308))
(IOPATH datac combout (241:241:241) (242:242:242))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[20\]\~59)
(DELAY
(ABSOLUTE
(PORT datab (264:264:264) (347:347:347))
(IOPATH datab combout (365:365:365) (373:373:373))
(IOPATH datab cout (446:446:446) (318:318:318))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[20\])
(DELAY
(ABSOLUTE
(PORT clk (1898:1898:1898) (1920:1920:1920))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[21\]\~61)
(DELAY
(ABSOLUTE
(PORT datad (239:239:239) (309:309:309))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[21\])
(DELAY
(ABSOLUTE
(PORT clk (1898:1898:1898) (1920:1920:1920))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE Equal0\~7)
(DELAY
(ABSOLUTE
(PORT datac (669:669:669) (728:728:728))
(PORT datad (646:646:646) (700:700:700))
(IOPATH datac combout (241:241:241) (241:241:241))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE address\[0\]\~39)
(DELAY
(ABSOLUTE
(PORT dataa (644:644:644) (663:663:663))
(PORT datab (207:207:207) (248:248:248))
(PORT datad (330:330:330) (347:347:347))
(IOPATH dataa combout (324:324:324) (328:328:328))
(IOPATH datab combout (333:333:333) (332:332:332))
(IOPATH datac combout (353:353:353) (369:369:369))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE address\[0\])
(DELAY
(ABSOLUTE
(PORT clk (1868:1868:1868) (1877:1877:1877))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE address\[1\]\~13)
(DELAY
(ABSOLUTE
(PORT dataa (268:268:268) (356:356:356))
(PORT datab (261:261:261) (343:343:343))
(IOPATH dataa combout (339:339:339) (367:367:367))
(IOPATH dataa cout (436:436:436) (315:315:315))
(IOPATH datab combout (344:344:344) (369:369:369))
(IOPATH datab cout (446:446:446) (318:318:318))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE Equal0\~6)
(DELAY
(ABSOLUTE
(PORT dataa (707:707:707) (763:763:763))
(PORT datab (674:674:674) (730:730:730))
(PORT datac (613:613:613) (625:625:625))
(PORT datad (181:181:181) (210:210:210))
(IOPATH dataa combout (301:301:301) (299:299:299))
(IOPATH datab combout (300:300:300) (308:308:308))
(IOPATH datac combout (241:241:241) (242:242:242))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE address\[1\])
(DELAY
(ABSOLUTE
(PORT clk (1532:1532:1532) (1545:1545:1545))
(PORT d (74:74:74) (91:91:91))
(PORT ena (795:795:795) (792:792:792))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
(HOLD ena (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE address\[2\]\~15)
(DELAY
(ABSOLUTE
(PORT datab (261:261:261) (343:343:343))
(IOPATH datab combout (365:365:365) (373:373:373))
(IOPATH datab cout (446:446:446) (318:318:318))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE address\[2\])
(DELAY
(ABSOLUTE
(PORT clk (1532:1532:1532) (1545:1545:1545))
(PORT d (74:74:74) (91:91:91))
(PORT ena (795:795:795) (792:792:792))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
(HOLD ena (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE address\[3\]\~17)
(DELAY
(ABSOLUTE
(PORT datab (282:282:282) (364:364:364))
(IOPATH datab combout (355:355:355) (369:369:369))
(IOPATH datab cout (446:446:446) (318:318:318))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE address\[3\])
(DELAY
(ABSOLUTE
(PORT clk (1532:1532:1532) (1545:1545:1545))
(PORT d (74:74:74) (91:91:91))
(PORT ena (795:795:795) (792:792:792))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
(HOLD ena (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE address\[4\]\~19)
(DELAY
(ABSOLUTE
(PORT dataa (265:265:265) (351:351:351))
(IOPATH dataa combout (356:356:356) (368:368:368))
(IOPATH dataa cout (436:436:436) (315:315:315))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE address\[4\])
(DELAY
(ABSOLUTE
(PORT clk (1532:1532:1532) (1545:1545:1545))
(PORT d (74:74:74) (91:91:91))
(PORT ena (795:795:795) (792:792:792))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
(HOLD ena (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE address\[5\]\~21)
(DELAY
(ABSOLUTE
(PORT datab (263:263:263) (345:345:345))
(IOPATH datab combout (355:355:355) (369:369:369))
(IOPATH datab cout (446:446:446) (318:318:318))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE address\[5\])
(DELAY
(ABSOLUTE
(PORT clk (1532:1532:1532) (1545:1545:1545))
(PORT d (74:74:74) (91:91:91))
(PORT ena (795:795:795) (792:792:792))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
(HOLD ena (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE address\[6\]\~23)
(DELAY
(ABSOLUTE
(PORT dataa (266:266:266) (353:353:353))
(IOPATH dataa combout (356:356:356) (368:368:368))
(IOPATH dataa cout (436:436:436) (315:315:315))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE address\[6\])
(DELAY
(ABSOLUTE
(PORT clk (1532:1532:1532) (1545:1545:1545))
(PORT d (74:74:74) (91:91:91))
(PORT ena (795:795:795) (792:792:792))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
(HOLD ena (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE address\[7\]\~25)
(DELAY
(ABSOLUTE
(PORT dataa (266:266:266) (353:353:353))
(IOPATH dataa combout (354:354:354) (367:367:367))
(IOPATH dataa cout (436:436:436) (315:315:315))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE address\[7\])
(DELAY
(ABSOLUTE
(PORT clk (1532:1532:1532) (1545:1545:1545))
(PORT d (74:74:74) (91:91:91))
(PORT ena (795:795:795) (792:792:792))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
(HOLD ena (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE address\[8\]\~27)
(DELAY
(ABSOLUTE
(PORT datab (264:264:264) (347:347:347))
(IOPATH datab combout (365:365:365) (373:373:373))
(IOPATH datab cout (446:446:446) (318:318:318))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE address\[8\])
(DELAY
(ABSOLUTE
(PORT clk (1532:1532:1532) (1545:1545:1545))
(PORT d (74:74:74) (91:91:91))
(PORT ena (795:795:795) (792:792:792))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
(HOLD ena (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE address\[9\]\~29)
(DELAY
(ABSOLUTE
(PORT datab (264:264:264) (347:347:347))
(IOPATH datab combout (355:355:355) (369:369:369))
(IOPATH datab cout (446:446:446) (318:318:318))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE address\[9\])
(DELAY
(ABSOLUTE
(PORT clk (1532:1532:1532) (1545:1545:1545))
(PORT d (74:74:74) (91:91:91))
(PORT ena (795:795:795) (792:792:792))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
(HOLD ena (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE address\[10\]\~31)
(DELAY
(ABSOLUTE
(PORT datab (264:264:264) (347:347:347))
(IOPATH datab combout (365:365:365) (373:373:373))
(IOPATH datab cout (446:446:446) (318:318:318))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE address\[10\])
(DELAY
(ABSOLUTE
(PORT clk (1532:1532:1532) (1545:1545:1545))
(PORT d (74:74:74) (91:91:91))
(PORT ena (795:795:795) (792:792:792))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
(HOLD ena (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE address\[11\]\~33)
(DELAY
(ABSOLUTE
(PORT datab (264:264:264) (347:347:347))
(IOPATH datab combout (355:355:355) (369:369:369))
(IOPATH datab cout (446:446:446) (318:318:318))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE address\[11\])
(DELAY
(ABSOLUTE
(PORT clk (1532:1532:1532) (1545:1545:1545))
(PORT d (74:74:74) (91:91:91))
(PORT ena (795:795:795) (792:792:792))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
(HOLD ena (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE address\[12\]\~35)
(DELAY
(ABSOLUTE
(PORT dataa (266:266:266) (352:352:352))
(IOPATH dataa combout (356:356:356) (368:368:368))
(IOPATH dataa cout (436:436:436) (315:315:315))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
(IOPATH cin cout (58:58:58) (58:58:58))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE address\[12\])
(DELAY
(ABSOLUTE
(PORT clk (1532:1532:1532) (1545:1545:1545))
(PORT d (74:74:74) (91:91:91))
(PORT ena (795:795:795) (792:792:792))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
(HOLD ena (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE address\[13\]\~37)
(DELAY
(ABSOLUTE
(PORT datad (258:258:258) (327:327:327))
(IOPATH datad combout (130:130:130) (120:120:120))
(IOPATH cin combout (455:455:455) (437:437:437))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE address\[13\])
(DELAY
(ABSOLUTE
(PORT clk (1532:1532:1532) (1545:1545:1545))
(PORT d (74:74:74) (91:91:91))
(PORT ena (795:795:795) (792:792:792))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
(HOLD ena (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE rom\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder)
(DELAY
(ABSOLUTE
(PORT datad (428:428:428) (485:485:485))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE rom\|altsyncram_component\|auto_generated\|address_reg_a\[0\])
(DELAY
(ABSOLUTE
(PORT clk (1531:1531:1531) (1545:1545:1545))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE rom\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]\~feeder)
(DELAY
(ABSOLUTE
(PORT datad (220:220:220) (290:290:290))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE rom\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\])
(DELAY
(ABSOLUTE
(PORT clk (1531:1531:1531) (1545:1545:1545))
(PORT d (74:74:74) (91:91:91))
(IOPATH (posedge clk) q (199:199:199) (199:199:199))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (157:157:157))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1232:1232:1232) (1314:1314:1314))
(PORT d[1] (1273:1273:1273) (1381:1381:1381))
(PORT d[2] (1342:1342:1342) (1456:1456:1456))
(PORT d[3] (1317:1317:1317) (1435:1435:1435))
(PORT d[4] (1249:1249:1249) (1341:1341:1341))
(PORT d[5] (1362:1362:1362) (1458:1458:1458))
(PORT d[6] (1704:1704:1704) (1869:1869:1869))
(PORT d[7] (1310:1310:1310) (1434:1434:1434))
(PORT d[8] (1316:1316:1316) (1419:1419:1419))
(PORT d[9] (1359:1359:1359) (1447:1447:1447))
(PORT d[10] (1320:1320:1320) (1425:1425:1425))
(PORT d[11] (1570:1570:1570) (1654:1654:1654))
(PORT d[12] (1289:1289:1289) (1390:1390:1390))
(PORT clk (1856:1856:1856) (1882:1882:1882))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1856:1856:1856) (1882:1882:1882))
(PORT d[0] (1167:1167:1167) (1189:1189:1189))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1857:1857:1857) (1883:1883:1883))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1819:1819:1819) (1845:1845:1845))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (1004:1004:1004) (1008:1008:1008))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1005:1005:1005) (1009:1009:1009))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1005:1005:1005) (1009:1009:1009))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1005:1005:1005) (1009:1009:1009))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1152:1152:1152) (1246:1246:1246))
(PORT d[1] (973:973:973) (1069:1069:1069))
(PORT d[2] (1034:1034:1034) (1138:1138:1138))
(PORT d[3] (1341:1341:1341) (1439:1439:1439))
(PORT d[4] (1248:1248:1248) (1333:1333:1333))
(PORT d[5] (1325:1325:1325) (1408:1408:1408))
(PORT d[6] (1491:1491:1491) (1664:1664:1664))
(PORT d[7] (1263:1263:1263) (1339:1339:1339))
(PORT d[8] (1326:1326:1326) (1417:1417:1417))
(PORT d[9] (1388:1388:1388) (1482:1482:1482))
(PORT d[10] (1305:1305:1305) (1406:1406:1406))
(PORT d[11] (1274:1274:1274) (1349:1349:1349))
(PORT d[12] (1340:1340:1340) (1438:1438:1438))
(PORT clk (1857:1857:1857) (1883:1883:1883))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1857:1857:1857) (1883:1883:1883))
(PORT d[0] (954:954:954) (925:925:925))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1858:1858:1858) (1884:1884:1884))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1820:1820:1820) (1846:1846:1846))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (1005:1005:1005) (1009:1009:1009))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1006:1006:1006) (1010:1010:1010))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1006:1006:1006) (1010:1010:1010))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1006:1006:1006) (1010:1010:1010))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~0)
(DELAY
(ABSOLUTE
(PORT datab (956:956:956) (1072:1072:1072))
(PORT datac (880:880:880) (883:883:883))
(PORT datad (605:605:605) (612:612:612))
(IOPATH datab combout (342:342:342) (342:342:342))
(IOPATH datac combout (243:243:243) (242:242:242))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1457:1457:1457) (1535:1535:1535))
(PORT d[1] (1538:1538:1538) (1599:1599:1599))
(PORT d[2] (1565:1565:1565) (1669:1669:1669))
(PORT d[3] (1248:1248:1248) (1294:1294:1294))
(PORT d[4] (1607:1607:1607) (1738:1738:1738))
(PORT d[5] (1904:1904:1904) (2043:2043:2043))
(PORT d[6] (1250:1250:1250) (1306:1306:1306))
(PORT d[7] (1340:1340:1340) (1441:1441:1441))
(PORT d[8] (1887:1887:1887) (2029:2029:2029))
(PORT d[9] (1230:1230:1230) (1303:1303:1303))
(PORT d[10] (1415:1415:1415) (1517:1517:1517))
(PORT d[11] (1208:1208:1208) (1273:1273:1273))
(PORT d[12] (1256:1256:1256) (1338:1338:1338))
(PORT clk (1848:1848:1848) (1875:1875:1875))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1848:1848:1848) (1875:1875:1875))
(PORT d[0] (1141:1141:1141) (1128:1128:1128))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1849:1849:1849) (1876:1876:1876))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1811:1811:1811) (1838:1838:1838))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (996:996:996) (1001:1001:1001))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (997:997:997) (1002:1002:1002))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (997:997:997) (1002:1002:1002))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (997:997:997) (1002:1002:1002))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1500:1500:1500) (1594:1594:1594))
(PORT d[1] (1355:1355:1355) (1470:1470:1470))
(PORT d[2] (1591:1591:1591) (1703:1703:1703))
(PORT d[3] (1336:1336:1336) (1417:1417:1417))
(PORT d[4] (1313:1313:1313) (1422:1422:1422))
(PORT d[5] (1595:1595:1595) (1733:1733:1733))
(PORT d[6] (1268:1268:1268) (1373:1373:1373))
(PORT d[7] (1255:1255:1255) (1355:1355:1355))
(PORT d[8] (1615:1615:1615) (1750:1750:1750))
(PORT d[9] (1326:1326:1326) (1421:1421:1421))
(PORT d[10] (1812:1812:1812) (1937:1937:1937))
(PORT d[11] (1293:1293:1293) (1402:1402:1402))
(PORT d[12] (1561:1561:1561) (1676:1676:1676))
(PORT clk (1848:1848:1848) (1875:1875:1875))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1848:1848:1848) (1875:1875:1875))
(PORT d[0] (1207:1207:1207) (1256:1256:1256))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1849:1849:1849) (1876:1876:1876))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1811:1811:1811) (1838:1838:1838))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (996:996:996) (1001:1001:1001))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (997:997:997) (1002:1002:1002))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (997:997:997) (1002:1002:1002))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (997:997:997) (1002:1002:1002))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~1)
(DELAY
(ABSOLUTE
(PORT dataa (626:626:626) (652:652:652))
(PORT datac (877:877:877) (907:907:907))
(PORT datad (1342:1342:1342) (1396:1396:1396))
(IOPATH dataa combout (354:354:354) (367:367:367))
(IOPATH datac combout (241:241:241) (242:242:242))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1238:1238:1238) (1323:1323:1323))
(PORT d[1] (1282:1282:1282) (1374:1374:1374))
(PORT d[2] (1603:1603:1603) (1716:1716:1716))
(PORT d[3] (1381:1381:1381) (1467:1467:1467))
(PORT d[4] (1282:1282:1282) (1376:1376:1376))
(PORT d[5] (1277:1277:1277) (1395:1395:1395))
(PORT d[6] (1716:1716:1716) (1879:1879:1879))
(PORT d[7] (1344:1344:1344) (1433:1433:1433))
(PORT d[8] (1329:1329:1329) (1433:1433:1433))
(PORT d[9] (1412:1412:1412) (1507:1507:1507))
(PORT d[10] (1764:1764:1764) (1843:1843:1843))
(PORT d[11] (1578:1578:1578) (1656:1656:1656))
(PORT d[12] (1322:1322:1322) (1422:1422:1422))
(PORT clk (1855:1855:1855) (1880:1880:1880))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1855:1855:1855) (1880:1880:1880))
(PORT d[0] (1242:1242:1242) (1194:1194:1194))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1856:1856:1856) (1881:1881:1881))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1818:1818:1818) (1843:1843:1843))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (1003:1003:1003) (1006:1006:1006))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1004:1004:1004) (1007:1007:1007))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1004:1004:1004) (1007:1007:1007))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1004:1004:1004) (1007:1007:1007))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (963:963:963) (1054:1054:1054))
(PORT d[1] (1258:1258:1258) (1343:1343:1343))
(PORT d[2] (1047:1047:1047) (1135:1135:1135))
(PORT d[3] (1074:1074:1074) (1167:1167:1167))
(PORT d[4] (966:966:966) (1059:1059:1059))
(PORT d[5] (1239:1239:1239) (1332:1332:1332))
(PORT d[6] (1463:1463:1463) (1631:1631:1631))
(PORT d[7] (1262:1262:1262) (1338:1338:1338))
(PORT d[8] (1053:1053:1053) (1156:1156:1156))
(PORT d[9] (1100:1100:1100) (1206:1206:1206))
(PORT d[10] (1512:1512:1512) (1581:1581:1581))
(PORT d[11] (1273:1273:1273) (1348:1348:1348))
(PORT d[12] (1313:1313:1313) (1405:1405:1405))
(PORT clk (1857:1857:1857) (1883:1883:1883))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1857:1857:1857) (1883:1883:1883))
(PORT d[0] (924:924:924) (953:953:953))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1858:1858:1858) (1884:1884:1884))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1820:1820:1820) (1846:1846:1846))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (1005:1005:1005) (1009:1009:1009))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1006:1006:1006) (1010:1010:1010))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1006:1006:1006) (1010:1010:1010))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1006:1006:1006) (1010:1010:1010))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~2)
(DELAY
(ABSOLUTE
(PORT datab (980:980:980) (1094:1094:1094))
(PORT datac (902:902:902) (940:940:940))
(PORT datad (596:596:596) (601:601:601))
(IOPATH datab combout (365:365:365) (373:373:373))
(IOPATH datac combout (243:243:243) (242:242:242))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (930:930:930) (988:988:988))
(PORT d[1] (979:979:979) (1053:1053:1053))
(PORT d[2] (1080:1080:1080) (1156:1156:1156))
(PORT d[3] (1058:1058:1058) (1130:1130:1130))
(PORT d[4] (956:956:956) (1028:1028:1028))
(PORT d[5] (1006:1006:1006) (1083:1083:1083))
(PORT d[6] (1424:1424:1424) (1563:1563:1563))
(PORT d[7] (1240:1240:1240) (1316:1316:1316))
(PORT d[8] (1625:1625:1625) (1738:1738:1738))
(PORT d[9] (1086:1086:1086) (1162:1162:1162))
(PORT d[10] (1042:1042:1042) (1125:1125:1125))
(PORT d[11] (1300:1300:1300) (1361:1361:1361))
(PORT d[12] (1299:1299:1299) (1370:1370:1370))
(PORT clk (1857:1857:1857) (1884:1884:1884))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1857:1857:1857) (1884:1884:1884))
(PORT d[0] (908:908:908) (912:912:912))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1858:1858:1858) (1885:1885:1885))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1820:1820:1820) (1847:1847:1847))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (1005:1005:1005) (1010:1010:1010))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1006:1006:1006) (1011:1011:1011))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1006:1006:1006) (1011:1011:1011))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1006:1006:1006) (1011:1011:1011))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1205:1205:1205) (1260:1260:1260))
(PORT d[1] (651:651:651) (711:711:711))
(PORT d[2] (713:713:713) (781:781:781))
(PORT d[3] (760:760:760) (830:830:830))
(PORT d[4] (659:659:659) (721:721:721))
(PORT d[5] (734:734:734) (814:814:814))
(PORT d[6] (761:761:761) (832:832:832))
(PORT d[7] (740:740:740) (819:819:819))
(PORT d[8] (756:756:756) (828:828:828))
(PORT d[9] (769:769:769) (847:847:847))
(PORT d[10] (1226:1226:1226) (1292:1292:1292))
(PORT d[11] (741:741:741) (813:813:813))
(PORT d[12] (751:751:751) (826:826:826))
(PORT clk (1857:1857:1857) (1884:1884:1884))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1857:1857:1857) (1884:1884:1884))
(PORT d[0] (642:642:642) (628:628:628))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1858:1858:1858) (1885:1885:1885))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1820:1820:1820) (1847:1847:1847))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (1005:1005:1005) (1010:1010:1010))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1006:1006:1006) (1011:1011:1011))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1006:1006:1006) (1011:1011:1011))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1006:1006:1006) (1011:1011:1011))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~3)
(DELAY
(ABSOLUTE
(PORT dataa (918:918:918) (939:939:939))
(PORT datac (648:648:648) (723:723:723))
(PORT datad (603:603:603) (610:610:610))
(IOPATH dataa combout (341:341:341) (347:347:347))
(IOPATH datac combout (243:243:243) (241:241:241))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1471:1471:1471) (1551:1551:1551))
(PORT d[1] (1529:1529:1529) (1590:1590:1590))
(PORT d[2] (1557:1557:1557) (1660:1660:1660))
(PORT d[3] (988:988:988) (1045:1045:1045))
(PORT d[4] (976:976:976) (1062:1062:1062))
(PORT d[5] (1604:1604:1604) (1749:1749:1749))
(PORT d[6] (996:996:996) (1079:1079:1079))
(PORT d[7] (948:948:948) (1026:1026:1026))
(PORT d[8] (1601:1601:1601) (1742:1742:1742))
(PORT d[9] (998:998:998) (1064:1064:1064))
(PORT d[10] (979:979:979) (1057:1057:1057))
(PORT d[11] (958:958:958) (1040:1040:1040))
(PORT d[12] (969:969:969) (1047:1047:1047))
(PORT clk (1849:1849:1849) (1875:1875:1875))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1849:1849:1849) (1875:1875:1875))
(PORT d[0] (904:904:904) (885:885:885))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1850:1850:1850) (1876:1876:1876))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1812:1812:1812) (1838:1838:1838))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (997:997:997) (1001:1001:1001))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (998:998:998) (1002:1002:1002))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (998:998:998) (1002:1002:1002))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (998:998:998) (1002:1002:1002))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1219:1219:1219) (1307:1307:1307))
(PORT d[1] (1255:1255:1255) (1323:1323:1323))
(PORT d[2] (1279:1279:1279) (1381:1381:1381))
(PORT d[3] (1279:1279:1279) (1328:1328:1328))
(PORT d[4] (1603:1603:1603) (1733:1733:1733))
(PORT d[5] (1603:1603:1603) (1748:1748:1748))
(PORT d[6] (1281:1281:1281) (1369:1369:1369))
(PORT d[7] (1245:1245:1245) (1325:1325:1325))
(PORT d[8] (1600:1600:1600) (1741:1741:1741))
(PORT d[9] (1266:1266:1266) (1335:1335:1335))
(PORT d[10] (1838:1838:1838) (1967:1967:1967))
(PORT d[11] (1283:1283:1283) (1373:1373:1373))
(PORT d[12] (1245:1245:1245) (1330:1330:1330))
(PORT clk (1849:1849:1849) (1875:1875:1875))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1849:1849:1849) (1875:1875:1875))
(PORT d[0] (1151:1151:1151) (1179:1179:1179))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1850:1850:1850) (1876:1876:1876))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1812:1812:1812) (1838:1838:1838))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (997:997:997) (1001:1001:1001))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (998:998:998) (1002:1002:1002))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (998:998:998) (1002:1002:1002))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (998:998:998) (1002:1002:1002))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~4)
(DELAY
(ABSOLUTE
(PORT datab (640:640:640) (651:651:651))
(PORT datac (859:859:859) (855:855:855))
(PORT datad (794:794:794) (853:853:853))
(IOPATH datab combout (355:355:355) (369:369:369))
(IOPATH datac combout (241:241:241) (242:242:242))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1508:1508:1508) (1612:1612:1612))
(PORT d[1] (1896:1896:1896) (2041:2041:2041))
(PORT d[2] (1251:1251:1251) (1359:1359:1359))
(PORT d[3] (1319:1319:1319) (1368:1368:1368))
(PORT d[4] (1294:1294:1294) (1407:1407:1407))
(PORT d[5] (1248:1248:1248) (1360:1360:1360))
(PORT d[6] (1297:1297:1297) (1411:1411:1411))
(PORT d[7] (1260:1260:1260) (1366:1366:1366))
(PORT d[8] (1608:1608:1608) (1726:1726:1726))
(PORT d[9] (1309:1309:1309) (1408:1408:1408))
(PORT d[10] (1860:1860:1860) (1990:1990:1990))
(PORT d[11] (1271:1271:1271) (1381:1381:1381))
(PORT d[12] (1527:1527:1527) (1637:1637:1637))
(PORT clk (1848:1848:1848) (1875:1875:1875))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1848:1848:1848) (1875:1875:1875))
(PORT d[0] (1193:1193:1193) (1239:1239:1239))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1849:1849:1849) (1876:1876:1876))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1811:1811:1811) (1838:1838:1838))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (996:996:996) (1001:1001:1001))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (997:997:997) (1002:1002:1002))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (997:997:997) (1002:1002:1002))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (997:997:997) (1002:1002:1002))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1555:1555:1555) (1667:1667:1667))
(PORT d[1] (1626:1626:1626) (1776:1776:1776))
(PORT d[2] (1557:1557:1557) (1668:1668:1668))
(PORT d[3] (1644:1644:1644) (1709:1709:1709))
(PORT d[4] (1593:1593:1593) (1715:1715:1715))
(PORT d[5] (1575:1575:1575) (1680:1680:1680))
(PORT d[6] (1565:1565:1565) (1670:1670:1670))
(PORT d[7] (1531:1531:1531) (1632:1632:1632))
(PORT d[8] (1555:1555:1555) (1659:1659:1659))
(PORT d[9] (1587:1587:1587) (1682:1682:1682))
(PORT d[10] (1533:1533:1533) (1638:1638:1638))
(PORT d[11] (1559:1559:1559) (1667:1667:1667))
(PORT d[12] (1527:1527:1527) (1639:1639:1639))
(PORT clk (1847:1847:1847) (1874:1874:1874))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1847:1847:1847) (1874:1874:1874))
(PORT d[0] (1489:1489:1489) (1442:1442:1442))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1848:1848:1848) (1875:1875:1875))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1810:1810:1810) (1837:1837:1837))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (995:995:995) (1000:1000:1000))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (996:996:996) (1001:1001:1001))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (996:996:996) (1001:1001:1001))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (996:996:996) (1001:1001:1001))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~5)
(DELAY
(ABSOLUTE
(PORT datab (626:626:626) (635:635:635))
(PORT datac (909:909:909) (911:911:911))
(PORT datad (1120:1120:1120) (1222:1222:1222))
(IOPATH datab combout (306:306:306) (311:311:311))
(IOPATH datac combout (243:243:243) (241:241:241))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (965:965:965) (1030:1030:1030))
(PORT d[1] (1241:1241:1241) (1329:1329:1329))
(PORT d[2] (1056:1056:1056) (1157:1157:1157))
(PORT d[3] (1088:1088:1088) (1177:1177:1177))
(PORT d[4] (990:990:990) (1084:1084:1084))
(PORT d[5] (1067:1067:1067) (1137:1137:1137))
(PORT d[6] (1434:1434:1434) (1593:1593:1593))
(PORT d[7] (1278:1278:1278) (1382:1382:1382))
(PORT d[8] (1052:1052:1052) (1156:1156:1156))
(PORT d[9] (1060:1060:1060) (1159:1159:1159))
(PORT d[10] (1022:1022:1022) (1126:1126:1126))
(PORT d[11] (1256:1256:1256) (1351:1351:1351))
(PORT d[12] (1309:1309:1309) (1400:1400:1400))
(PORT clk (1857:1857:1857) (1883:1883:1883))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1857:1857:1857) (1883:1883:1883))
(PORT d[0] (918:918:918) (941:941:941))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1858:1858:1858) (1884:1884:1884))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1820:1820:1820) (1846:1846:1846))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (1005:1005:1005) (1009:1009:1009))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1006:1006:1006) (1010:1010:1010))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1006:1006:1006) (1010:1010:1010))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1006:1006:1006) (1010:1010:1010))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (921:921:921) (982:982:982))
(PORT d[1] (652:652:652) (711:711:711))
(PORT d[2] (1323:1323:1323) (1400:1400:1400))
(PORT d[3] (1338:1338:1338) (1452:1452:1452))
(PORT d[4] (929:929:929) (988:988:988))
(PORT d[5] (1048:1048:1048) (1131:1131:1131))
(PORT d[6] (1394:1394:1394) (1522:1522:1522))
(PORT d[7] (1240:1240:1240) (1309:1309:1309))
(PORT d[8] (1638:1638:1638) (1740:1740:1740))
(PORT d[9] (1048:1048:1048) (1110:1110:1110))
(PORT d[10] (1044:1044:1044) (1103:1103:1103))
(PORT d[11] (1204:1204:1204) (1263:1263:1263))
(PORT d[12] (1258:1258:1258) (1304:1304:1304))
(PORT clk (1857:1857:1857) (1883:1883:1883))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1857:1857:1857) (1883:1883:1883))
(PORT d[0] (887:887:887) (888:888:888))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1858:1858:1858) (1884:1884:1884))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1820:1820:1820) (1846:1846:1846))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (1005:1005:1005) (1009:1009:1009))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1006:1006:1006) (1010:1010:1010))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1006:1006:1006) (1010:1010:1010))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1006:1006:1006) (1010:1010:1010))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~6)
(DELAY
(ABSOLUTE
(PORT dataa (694:694:694) (743:743:743))
(PORT datac (917:917:917) (955:955:955))
(PORT datad (347:347:347) (362:362:362))
(IOPATH dataa combout (341:341:341) (347:347:347))
(IOPATH datac combout (243:243:243) (241:241:241))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1471:1471:1471) (1578:1578:1578))
(PORT d[1] (1888:1888:1888) (2030:2030:2030))
(PORT d[2] (1880:1880:1880) (2006:2006:2006))
(PORT d[3] (1371:1371:1371) (1434:1434:1434))
(PORT d[4] (1886:1886:1886) (2001:2001:2001))
(PORT d[5] (1321:1321:1321) (1439:1439:1439))
(PORT d[6] (1325:1325:1325) (1443:1443:1443))
(PORT d[7] (1261:1261:1261) (1367:1367:1367))
(PORT d[8] (1312:1312:1312) (1427:1427:1427))
(PORT d[9] (1283:1283:1283) (1377:1377:1377))
(PORT d[10] (1803:1803:1803) (1907:1907:1907))
(PORT d[11] (1272:1272:1272) (1382:1382:1382))
(PORT d[12] (1256:1256:1256) (1366:1366:1366))
(PORT clk (1848:1848:1848) (1875:1875:1875))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1848:1848:1848) (1875:1875:1875))
(PORT d[0] (1266:1266:1266) (1210:1210:1210))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1849:1849:1849) (1876:1876:1876))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1811:1811:1811) (1838:1838:1838))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (996:996:996) (1001:1001:1001))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (997:997:997) (1002:1002:1002))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (997:997:997) (1002:1002:1002))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (997:997:997) (1002:1002:1002))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1817:1817:1817) (1923:1923:1923))
(PORT d[1] (1607:1607:1607) (1705:1705:1705))
(PORT d[2] (1576:1576:1576) (1716:1716:1716))
(PORT d[3] (1616:1616:1616) (1679:1679:1679))
(PORT d[4] (1594:1594:1594) (1718:1718:1718))
(PORT d[5] (1563:1563:1563) (1701:1701:1701))
(PORT d[6] (1548:1548:1548) (1655:1655:1655))
(PORT d[7] (1539:1539:1539) (1642:1642:1642))
(PORT d[8] (1532:1532:1532) (1634:1634:1634))
(PORT d[9] (1589:1589:1589) (1705:1705:1705))
(PORT d[10] (1503:1503:1503) (1601:1601:1601))
(PORT d[11] (1561:1561:1561) (1686:1686:1686))
(PORT d[12] (1531:1531:1531) (1649:1649:1649))
(PORT clk (1846:1846:1846) (1872:1872:1872))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (187:187:187))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1846:1846:1846) (1872:1872:1872))
(PORT d[0] (1495:1495:1495) (1543:1543:1543))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1847:1847:1847) (1873:1873:1873))
(IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1809:1809:1809) (1835:1835:1835))
(IOPATH (posedge clk) q (301:301:301) (301:301:301))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (51:51:51))
(HOLD d (posedge clk) (159:159:159))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (994:994:994) (998:998:998))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (995:995:995) (999:999:999))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (995:995:995) (999:999:999))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (995:995:995) (999:999:999))
(IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~7)
(DELAY
(ABSOLUTE
(PORT datab (636:636:636) (645:645:645))
(PORT datac (906:906:906) (905:905:905))
(PORT datad (1123:1123:1123) (1224:1224:1224))
(IOPATH datab combout (355:355:355) (369:369:369))
(IOPATH datac combout (241:241:241) (242:242:242))
(IOPATH datad combout (130:130:130) (120:120:120))
)
)
)
)
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