diff --git a/db/altsyncram_qh91.tdf b/db/altsyncram_qh91.tdf new file mode 100644 index 0000000..6b39768 --- /dev/null +++ b/db/altsyncram_qh91.tdf @@ -0,0 +1,415 @@ +--altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" ENABLE_RUNTIME_MOD="NO" INIT_FILE="./rom/gw03.hex" LOW_POWER_MODE="AUTO" NUMWORDS_A=16384 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="CLOCK0" WIDTH_A=8 WIDTH_BYTEENA_A=1 WIDTHAD_A=14 address_a clock0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 13.1 cbx_altsyncram 2013:10:17:09:48:19:SJ cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_lpm_mux 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ cbx_stratixiii 2013:10:17:09:48:19:SJ cbx_stratixv 2013:10:17:09:48:19:SJ cbx_util_mgl 2013:10:17:09:48:19:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION decode_c8a (data[0..0]) +RETURNS ( eq[1..0]); +FUNCTION mux_3nb (data[15..0], sel[0..0]) +RETURNS ( result[7..0]); +FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) +RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = lut 9 M9K 16 reg 2 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_qh91 +( + address_a[13..0] : input; + clock0 : input; + q_a[7..0] : output; +) +VARIABLE + address_reg_a[0..0] : dffe; + out_address_reg_a[0..0] : dffe; + rden_decode : decode_c8a; + mux2 : mux_3nb; + ram_block1a0 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "./rom/gw03.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "./rom/gw03.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "./rom/gw03.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "./rom/gw03.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "./rom/gw03.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "./rom/gw03.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "./rom/gw03.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "./rom/gw03.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 8191, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a8 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "./rom/gw03.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a9 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "./rom/gw03.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a10 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "./rom/gw03.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a11 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "./rom/gw03.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a12 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "./rom/gw03.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a13 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "./rom/gw03.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a14 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "./rom/gw03.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a15 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "./rom/gw03.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 13, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 8192, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 16383, + PORT_A_LOGICAL_RAM_DEPTH = 16384, + PORT_A_LOGICAL_RAM_WIDTH = 8, + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_sel[0..0] : WIRE; + address_a_wire[13..0] : WIRE; + rden_decode_addr_sel_a[0..0] : WIRE; + +BEGIN + address_reg_a[].clk = clock0; + address_reg_a[].d = address_a_sel[]; + out_address_reg_a[].clk = clock0; + out_address_reg_a[].d = address_reg_a[].q; + rden_decode.data[] = rden_decode_addr_sel_a[]; + mux2.data[] = ( ram_block1a[15..0].portadataout[0..0]); + mux2.sel[] = out_address_reg_a[].q; + ram_block1a[15..0].clk0 = clock0; + ram_block1a[15..0].ena0 = ( rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0]); + ram_block1a[15..0].portaaddr[] = ( address_a_wire[12..0]); + ram_block1a[15..0].portare = B"1111111111111111"; + address_a_sel[0..0] = address_a[13..13]; + address_a_wire[] = address_a[]; + q_a[] = mux2.result[]; + rden_decode_addr_sel_a[0..0] = address_a_wire[13..13]; +END; +--VALID FILE diff --git a/db/decode_c8a.tdf b/db/decode_c8a.tdf new file mode 100644 index 0000000..90dd99f --- /dev/null +++ b/db/decode_c8a.tdf @@ -0,0 +1,36 @@ +--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_DECODES=2 LPM_WIDTH=1 data eq +--VERSION_BEGIN 13.1 cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + + +--synthesis_resources = lut 1 +SUBDESIGN decode_c8a +( + data[0..0] : input; + eq[1..0] : output; +) +VARIABLE + enable : NODE; + eq_node[1..0] : WIRE; + +BEGIN + enable = VCC; + eq[] = eq_node[]; + eq_node[] = ( (data[] & enable), ((! data[]) & enable)); +END; +--VALID FILE diff --git a/db/logic_util_heursitic.dat b/db/logic_util_heursitic.dat index 02d6608..793e066 100644 Binary files a/db/logic_util_heursitic.dat and b/db/logic_util_heursitic.dat differ diff --git a/db/mux_3nb.tdf b/db/mux_3nb.tdf new file mode 100644 index 0000000..d2122e3 --- /dev/null +++ b/db/mux_3nb.tdf @@ -0,0 +1,53 @@ +--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_SIZE=2 LPM_WIDTH=8 LPM_WIDTHS=1 data result sel +--VERSION_BEGIN 13.1 cbx_lpm_mux 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + + +--synthesis_resources = lut 8 +SUBDESIGN mux_3nb +( + data[15..0] : input; + result[7..0] : output; + sel[0..0] : input; +) +VARIABLE + result_node[7..0] : WIRE; + sel_node[0..0] : WIRE; + w_data109w[1..0] : WIRE; + w_data121w[1..0] : WIRE; + w_data133w[1..0] : WIRE; + w_data145w[1..0] : WIRE; + w_data157w[1..0] : WIRE; + w_data169w[1..0] : WIRE; + w_data83w[1..0] : WIRE; + w_data97w[1..0] : WIRE; + +BEGIN + result[] = result_node[]; + result_node[] = ( ((sel_node[] & w_data169w[1..1]) # ((! sel_node[]) & w_data169w[0..0])), ((sel_node[] & w_data157w[1..1]) # ((! sel_node[]) & w_data157w[0..0])), ((sel_node[] & w_data145w[1..1]) # ((! sel_node[]) & w_data145w[0..0])), ((sel_node[] & w_data133w[1..1]) # ((! sel_node[]) & w_data133w[0..0])), ((sel_node[] & w_data121w[1..1]) # ((! sel_node[]) & w_data121w[0..0])), ((sel_node[] & w_data109w[1..1]) # ((! sel_node[]) & w_data109w[0..0])), ((sel_node[] & w_data97w[1..1]) # ((! sel_node[]) & w_data97w[0..0])), ((sel_node[] & w_data83w[1..1]) # ((! sel_node[]) & w_data83w[0..0]))); + sel_node[] = ( sel[0..0]); + w_data109w[] = ( data[10..10], data[2..2]); + w_data121w[] = ( data[11..11], data[3..3]); + w_data133w[] = ( data[12..12], data[4..4]); + w_data145w[] = ( data[13..13], data[5..5]); + w_data157w[] = ( data[14..14], data[6..6]); + w_data169w[] = ( data[15..15], data[7..7]); + w_data83w[] = ( data[8..8], data[0..0]); + w_data97w[] = ( data[9..9], data[1..1]); +END; +--VALID FILE diff --git a/db/prev_cmp_spectrum.qmsg b/db/prev_cmp_spectrum.qmsg index 5fb3e8b..0881b5a 100644 --- a/db/prev_cmp_spectrum.qmsg +++ b/db/prev_cmp_spectrum.qmsg @@ -1,135 +1,139 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648632788486 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648632788487 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 12:33:08 2022 " "Processing started: Wed Mar 30 12:33:08 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648632788487 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648632788487 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum " "Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648632788487 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648632788648 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spectrum.v 1 1 " "Found 1 design units, including 1 entities, in source file spectrum.v" { { "Info" "ISGN_ENTITY_NAME" "1 spectrum " "Found entity 1: spectrum" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648632788712 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648632788712 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom0.v 1 1 " "Found 1 design units, including 1 entities, in source file rom0.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom0 " "Found entity 1: rom0" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648632788715 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648632788715 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "spectrum " "Elaborating entity \"spectrum\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1648632788766 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 21 spectrum.v(19) " "Verilog HDL assignment warning at spectrum.v(19): truncated value with size 32 to match size of target (21)" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 19 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1648632788767 "|spectrum"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 spectrum.v(21) " "Verilog HDL assignment warning at spectrum.v(21): truncated value with size 32 to match size of target (3)" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 21 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1648632788767 "|spectrum"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom0 rom0:rom " "Elaborating entity \"rom0\" for hierarchy \"rom0:rom\"" { } { { "spectrum.v" "rom" { Text "/home/benny/work/fpga/projects/spectrum.v" 14 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648632788769 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram rom0:rom\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "altsyncram_component" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648632788816 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "rom0:rom\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648632788817 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rom0:rom\|altsyncram:altsyncram_component " "Instantiated megafunction \"rom0:rom\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648632788818 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648632788818 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648632788818 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file led_patterns.mif " "Parameter \"init_file\" = \"led_patterns.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648632788818 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648632788818 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648632788818 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648632788818 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 8 " "Parameter \"numwords_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648632788818 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648632788818 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648632788818 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648632788818 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 3 " "Parameter \"widthad_a\" = \"3\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648632788818 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648632788818 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648632788818 ""} } { { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648632788818 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_ro91.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_ro91.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_ro91 " "Found entity 1: altsyncram_ro91" { } { { "db/altsyncram_ro91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_ro91.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648632788865 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648632788865 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_ro91 rom0:rom\|altsyncram:altsyncram_component\|altsyncram_ro91:auto_generated " "Elaborating entity \"altsyncram_ro91\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_ro91:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648632788865 ""} -{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1648632789369 ""} -{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1648632789571 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648632789571 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "48 " "Implemented 48 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Implemented 1 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1648632789615 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1648632789615 ""} { "Info" "ICUT_CUT_TM_LCELLS" "31 " "Implemented 31 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1648632789615 ""} { "Info" "ICUT_CUT_TM_RAMS" "8 " "Implemented 8 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Quartus II" 0 -1 1648632789615 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1648632789615 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "391 " "Peak virtual memory: 391 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648632789622 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 12:33:09 2022 " "Processing ended: Wed Mar 30 12:33:09 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648632789622 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648632789622 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648632789622 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648632789622 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648632790943 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648632790943 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 12:33:10 2022 " "Processing started: Wed Mar 30 12:33:10 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648632790943 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1648632790943 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_fit --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1648632790944 ""} -{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1648632790969 ""} -{ "Info" "0" "" "Project = spectrum" { } { } 0 0 "Project = spectrum" 0 0 "Fitter" 0 0 1648632790970 ""} -{ "Info" "0" "" "Revision = spectrum" { } { } 0 0 "Revision = spectrum" 0 0 "Fitter" 0 0 1648632790970 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1648632791017 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "spectrum EP4CE22F17C6 " "Selected device EP4CE22F17C6 for design \"spectrum\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1648632791021 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648632791062 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648632791063 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648632791063 ""} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1648632791140 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1648632791151 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17C6 " "Device EP4CE10F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648632791355 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C6 " "Device EP4CE6F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648632791355 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C6 " "Device EP4CE15F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648632791355 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1648632791355 ""} -{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 330 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648632791360 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 332 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648632791360 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 334 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648632791360 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 336 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648632791360 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 338 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648632791360 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1648632791360 ""} -{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1648632791362 ""} -{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1648632791363 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "spectrum.sdc " "Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1648632792037 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1648632792037 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1648632792039 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1648632792039 ""} -{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1648632792040 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p)) " "Automatically promoted node CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G18 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648632792047 ""} } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 325 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648632792047 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1648632792282 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648632792282 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648632792283 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648632792283 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648632792284 ""} -{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1648632792284 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1648632792284 ""} -{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1648632792284 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1648632792285 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1648632792285 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1648632792285 ""} -{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS_N " "Node \"ADC_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SADDR " "Node \"ADC_SADDR\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SADDR" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCLK " "Node \"ADC_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDAT " "Node \"ADC_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_ASDO " "Node \"EPCS_ASDO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_ASDO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DATA0 " "Node \"EPCS_DATA0\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DATA0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DCLK " "Node \"EPCS_DCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_NCSO " "Node \"EPCS_NCSO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_NCSO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[0\] " "Node \"GPIO_0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[10\] " "Node \"GPIO_0\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[11\] " "Node \"GPIO_0\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[12\] " "Node \"GPIO_0\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[13\] " "Node \"GPIO_0\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[14\] " "Node \"GPIO_0\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[15\] " "Node \"GPIO_0\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[16\] " "Node \"GPIO_0\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[17\] " "Node \"GPIO_0\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[18\] " "Node \"GPIO_0\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[19\] " "Node \"GPIO_0\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[1\] " "Node \"GPIO_0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[20\] " "Node \"GPIO_0\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[21\] " "Node \"GPIO_0\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[22\] " "Node \"GPIO_0\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[23\] " "Node \"GPIO_0\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[24\] " "Node \"GPIO_0\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[25\] " "Node \"GPIO_0\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[26\] " "Node \"GPIO_0\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[27\] " "Node \"GPIO_0\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[28\] " "Node \"GPIO_0\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[29\] " "Node \"GPIO_0\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[2\] " "Node \"GPIO_0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[30\] " "Node \"GPIO_0\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[31\] " "Node \"GPIO_0\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[32\] " "Node \"GPIO_0\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[33\] " "Node \"GPIO_0\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[3\] " "Node \"GPIO_0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[4\] " "Node \"GPIO_0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[5\] " "Node \"GPIO_0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[6\] " "Node \"GPIO_0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[7\] " "Node \"GPIO_0\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[8\] " "Node \"GPIO_0\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[9\] " "Node \"GPIO_0\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[0\] " "Node \"GPIO_0_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[1\] " "Node \"GPIO_0_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[0\] " "Node \"GPIO_1\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[10\] " "Node \"GPIO_1\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[11\] " "Node \"GPIO_1\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[12\] " "Node \"GPIO_1\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[13\] " "Node \"GPIO_1\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[14\] " "Node \"GPIO_1\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[15\] " "Node \"GPIO_1\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[16\] " "Node \"GPIO_1\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[17\] " "Node \"GPIO_1\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[18\] " "Node \"GPIO_1\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[19\] " "Node \"GPIO_1\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[1\] " "Node \"GPIO_1\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[20\] " "Node \"GPIO_1\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[21\] " "Node \"GPIO_1\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[22\] " "Node \"GPIO_1\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[23\] " "Node \"GPIO_1\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[24\] " "Node \"GPIO_1\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[25\] " "Node \"GPIO_1\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[26\] " "Node \"GPIO_1\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[27\] " "Node \"GPIO_1\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[28\] " "Node \"GPIO_1\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[29\] " "Node \"GPIO_1\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[2\] " "Node \"GPIO_1\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[30\] " "Node \"GPIO_1\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[31\] " "Node \"GPIO_1\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[32\] " "Node \"GPIO_1\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[33\] " "Node \"GPIO_1\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[3\] " "Node \"GPIO_1\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[4\] " "Node \"GPIO_1\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[5\] " "Node \"GPIO_1\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[6\] " "Node \"GPIO_1\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[7\] " "Node \"GPIO_1\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[8\] " "Node \"GPIO_1\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[9\] " "Node \"GPIO_1\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[0\] " "Node \"GPIO_1_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[1\] " "Node \"GPIO_1_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[0\] " "Node \"GPIO_2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[10\] " "Node \"GPIO_2\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[11\] " "Node \"GPIO_2\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[12\] " "Node \"GPIO_2\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[1\] " "Node \"GPIO_2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[2\] " "Node \"GPIO_2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[3\] " "Node \"GPIO_2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[4\] " "Node \"GPIO_2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[5\] " "Node \"GPIO_2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[6\] " "Node \"GPIO_2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[7\] " "Node \"GPIO_2\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[8\] " "Node \"GPIO_2\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[9\] " "Node \"GPIO_2\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[0\] " "Node \"GPIO_2_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[1\] " "Node \"GPIO_2_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[2\] " "Node \"GPIO_2_IN\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_CS_N " "Node \"G_SENSOR_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_INT " "Node \"G_SENSOR_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1648632792298 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648632792305 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1648632793268 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648632793338 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1648632793346 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1648632793795 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648632793795 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1648632794036 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X32_Y23 X42_Y34 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X32_Y23 to location X42_Y34" { } { { "loc" "" { Generic "/home/benny/work/fpga/projects/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X32_Y23 to location X42_Y34"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X32_Y23 to location X42_Y34"} 32 23 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1648632794638 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1648632794638 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648632795024 ""} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1648632795025 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1648632795025 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.24 " "Total time spent on timing analysis during the Fitter is 0.24 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1648632795035 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648632795087 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648632795247 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648632795292 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648632795424 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648632795700 ""} -{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1648632796044 ""} -{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "1 Cyclone IV E " "1 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK_50 3.3-V LVTTL R8 " "Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at R8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { CLOCK_50 } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 15 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648632796047 ""} } { } 0 169177 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1648632796047 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/projects/output_files/spectrum.fit.smsg " "Generated suppressed messages file /home/benny/work/fpga/projects/output_files/spectrum.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1648632796089 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 152 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 152 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "594 " "Peak virtual memory: 594 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648632796269 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 12:33:16 2022 " "Processing ended: Wed Mar 30 12:33:16 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648632796269 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648632796269 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648632796269 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1648632796269 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1648632797767 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648632797768 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 12:33:17 2022 " "Processing started: Wed Mar 30 12:33:17 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648632797768 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1648632797768 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1648632797768 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1648632798672 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1648632798698 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "390 " "Peak virtual memory: 390 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648632798946 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 12:33:18 2022 " "Processing ended: Wed Mar 30 12:33:18 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648632798946 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648632798946 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648632798946 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1648632798946 ""} -{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1648632799033 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1648632800321 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648632800322 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 12:33:20 2022 " "Processing started: Wed Mar 30 12:33:20 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648632800322 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648632800322 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta spectrum -c spectrum " "Command: quartus_sta spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648632800322 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1648632800349 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648632800451 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648632800453 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648632800497 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648632800498 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "spectrum.sdc " "Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1648632800697 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1648632800697 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648632800698 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648632800698 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1648632800824 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648632800825 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1648632800825 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1648632800830 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648632800838 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648632800838 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.756 " "Worst-case setup slack is -1.756" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632800839 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632800839 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.756 -35.786 CLOCK_50 " " -1.756 -35.786 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632800839 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648632800839 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.343 " "Worst-case hold slack is 0.343" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632800840 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632800840 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.343 0.000 CLOCK_50 " " 0.343 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632800840 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648632800840 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648632800840 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648632800841 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632800841 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632800841 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -46.624 CLOCK_50 " " -3.000 -46.624 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632800841 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648632800841 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648632800855 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1648632800878 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1648632801246 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648632801263 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648632801264 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648632801264 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.484 " "Worst-case setup slack is -1.484" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632801265 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632801265 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.484 -28.518 CLOCK_50 " " -1.484 -28.518 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632801265 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648632801265 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.298 " "Worst-case hold slack is 0.298" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632801267 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632801267 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.298 0.000 CLOCK_50 " " 0.298 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632801267 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648632801267 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648632801268 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648632801269 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632801270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632801270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -46.624 CLOCK_50 " " -3.000 -46.624 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632801270 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648632801270 ""} -{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648632801285 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648632801405 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648632801405 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648632801405 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.389 " "Worst-case setup slack is -0.389" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632801407 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632801407 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.389 -5.690 CLOCK_50 " " -0.389 -5.690 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632801407 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648632801407 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.178 " "Worst-case hold slack is 0.178" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632801409 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632801409 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.178 0.000 CLOCK_50 " " 0.178 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632801409 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648632801409 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648632801410 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648632801412 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632801413 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632801413 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -45.739 CLOCK_50 " " -3.000 -45.739 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632801413 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648632801413 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648632801708 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648632801708 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "415 " "Peak virtual memory: 415 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648632801742 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 12:33:21 2022 " "Processing ended: Wed Mar 30 12:33:21 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648632801742 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648632801742 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648632801742 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648632801742 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648632803343 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648632803344 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 12:33:23 2022 " "Processing started: Wed Mar 30 12:33:23 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648632803344 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648632803344 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648632803345 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648632803637 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648632803657 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_fast.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_fast.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648632803678 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648632803698 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648632803719 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648632803738 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_v_fast.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648632803757 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_v.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_v.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648632803776 ""} -{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "352 " "Peak virtual memory: 352 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648632803807 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 12:33:23 2022 " "Processing ended: Wed Mar 30 12:33:23 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648632803807 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648632803807 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648632803807 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648632803807 ""} -{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 160 s " "Quartus II Full Compilation was successful. 0 errors, 160 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648632803907 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648634803174 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648634803175 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 13:06:43 2022 " "Processing started: Wed Mar 30 13:06:43 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648634803175 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648634803175 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum " "Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648634803175 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648634803341 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spectrum.v 1 1 " "Found 1 design units, including 1 entities, in source file spectrum.v" { { "Info" "ISGN_ENTITY_NAME" "1 spectrum " "Found entity 1: spectrum" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648634803406 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648634803406 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom0.v 1 1 " "Found 1 design units, including 1 entities, in source file rom0.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom0 " "Found entity 1: rom0" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648634803407 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648634803407 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "spectrum " "Elaborating entity \"spectrum\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1648634803460 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 22 spectrum.v(18) " "Verilog HDL assignment warning at spectrum.v(18): truncated value with size 32 to match size of target (22)" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 18 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1648634803462 "|spectrum"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 spectrum.v(20) " "Verilog HDL assignment warning at spectrum.v(20): truncated value with size 32 to match size of target (14)" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 20 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1648634803462 "|spectrum"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom0 rom0:rom " "Elaborating entity \"rom0\" for hierarchy \"rom0:rom\"" { } { { "spectrum.v" "rom" { Text "/home/benny/work/fpga/projects/spectrum.v" 13 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648634803472 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram rom0:rom\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "altsyncram_component" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648634803521 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "rom0:rom\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648634803522 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rom0:rom\|altsyncram:altsyncram_component " "Instantiated megafunction \"rom0:rom\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648634803522 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648634803522 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648634803522 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file ./rom/gw03.hex " "Parameter \"init_file\" = \"./rom/gw03.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648634803522 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648634803522 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648634803522 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648634803522 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 16384 " "Parameter \"numwords_a\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648634803522 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648634803522 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648634803522 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648634803522 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 14 " "Parameter \"widthad_a\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648634803522 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648634803522 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648634803522 ""} } { { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648634803522 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_qh91.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_qh91.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_qh91 " "Found entity 1: altsyncram_qh91" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 31 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648634803569 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648634803569 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_qh91 rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated " "Elaborating entity \"altsyncram_qh91\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648634803570 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_c8a.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_c8a.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_c8a " "Found entity 1: decode_c8a" { } { { "db/decode_c8a.tdf" "" { Text "/home/benny/work/fpga/projects/db/decode_c8a.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648634803611 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648634803611 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_c8a rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|decode_c8a:rden_decode " "Elaborating entity \"decode_c8a\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|decode_c8a:rden_decode\"" { } { { "db/altsyncram_qh91.tdf" "rden_decode" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 40 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648634803612 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_3nb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_3nb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_3nb " "Found entity 1: mux_3nb" { } { { "db/mux_3nb.tdf" "" { Text "/home/benny/work/fpga/projects/db/mux_3nb.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648634803653 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648634803653 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_3nb rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|mux_3nb:mux2 " "Elaborating entity \"mux_3nb\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|mux_3nb:mux2\"" { } { { "db/altsyncram_qh91.tdf" "mux2" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 41 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648634803654 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1648634804177 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1648634804394 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648634804394 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "101 " "Implemented 101 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Implemented 1 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1648634804440 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1648634804440 ""} { "Info" "ICUT_CUT_TM_LCELLS" "76 " "Implemented 76 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1648634804440 ""} { "Info" "ICUT_CUT_TM_RAMS" "16 " "Implemented 16 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Quartus II" 0 -1 1648634804440 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1648634804440 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "392 " "Peak virtual memory: 392 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648634804448 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:06:44 2022 " "Processing ended: Wed Mar 30 13:06:44 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648634804448 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648634804448 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648634804448 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648634804448 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648634805764 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648634805765 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 13:06:45 2022 " "Processing started: Wed Mar 30 13:06:45 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648634805765 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1648634805765 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_fit --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1648634805765 ""} +{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1648634805789 ""} +{ "Info" "0" "" "Project = spectrum" { } { } 0 0 "Project = spectrum" 0 0 "Fitter" 0 0 1648634805790 ""} +{ "Info" "0" "" "Revision = spectrum" { } { } 0 0 "Revision = spectrum" 0 0 "Fitter" 0 0 1648634805790 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1648634805837 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "spectrum EP4CE22F17C6 " "Selected device EP4CE22F17C6 for design \"spectrum\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1648634805841 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648634805881 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648634805882 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648634805882 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1648634805956 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1648634805967 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17C6 " "Device EP4CE10F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648634806173 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C6 " "Device EP4CE6F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648634806173 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C6 " "Device EP4CE15F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648634806173 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1648634806173 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 601 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648634806178 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 603 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648634806178 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 605 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648634806178 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 607 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648634806178 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 609 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648634806178 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1648634806178 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1648634806180 ""} +{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1648634806182 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "spectrum.sdc " "Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1648634806857 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1648634806858 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1648634806860 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1648634806860 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1648634806861 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p)) " "Automatically promoted node CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G18 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648634806870 ""} } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 596 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648634806870 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1648634807110 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648634807111 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648634807111 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648634807112 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648634807112 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1648634807113 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1648634807113 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1648634807113 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1648634807113 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1648634807114 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1648634807114 ""} +{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS_N " "Node \"ADC_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SADDR " "Node \"ADC_SADDR\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SADDR" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCLK " "Node \"ADC_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDAT " "Node \"ADC_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_ASDO " "Node \"EPCS_ASDO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_ASDO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DATA0 " "Node \"EPCS_DATA0\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DATA0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DCLK " "Node \"EPCS_DCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_NCSO " "Node \"EPCS_NCSO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_NCSO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[0\] " "Node \"GPIO_0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[10\] " "Node \"GPIO_0\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[11\] " "Node \"GPIO_0\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[12\] " "Node \"GPIO_0\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[13\] " "Node \"GPIO_0\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[14\] " "Node \"GPIO_0\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[15\] " "Node \"GPIO_0\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[16\] " "Node \"GPIO_0\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[17\] " "Node \"GPIO_0\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[18\] " "Node \"GPIO_0\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[19\] " "Node \"GPIO_0\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[1\] " "Node \"GPIO_0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[20\] " "Node \"GPIO_0\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[21\] " "Node \"GPIO_0\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[22\] " "Node \"GPIO_0\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[23\] " "Node \"GPIO_0\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[24\] " "Node \"GPIO_0\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[25\] " "Node \"GPIO_0\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[26\] " "Node \"GPIO_0\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[27\] " "Node \"GPIO_0\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[28\] " "Node \"GPIO_0\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[29\] " "Node \"GPIO_0\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[2\] " "Node \"GPIO_0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[30\] " "Node \"GPIO_0\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[31\] " "Node \"GPIO_0\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[32\] " "Node \"GPIO_0\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[33\] " "Node \"GPIO_0\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[3\] " "Node \"GPIO_0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[4\] " "Node \"GPIO_0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[5\] " "Node \"GPIO_0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[6\] " "Node \"GPIO_0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[7\] " "Node \"GPIO_0\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[8\] " "Node \"GPIO_0\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[9\] " "Node \"GPIO_0\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[0\] " "Node \"GPIO_0_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[1\] " "Node \"GPIO_0_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[0\] " "Node \"GPIO_1\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[10\] " "Node \"GPIO_1\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[11\] " "Node \"GPIO_1\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[12\] " "Node \"GPIO_1\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[13\] " "Node \"GPIO_1\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[14\] " "Node \"GPIO_1\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[15\] " "Node \"GPIO_1\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[16\] " "Node \"GPIO_1\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[17\] " "Node \"GPIO_1\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[18\] " "Node \"GPIO_1\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[19\] " "Node \"GPIO_1\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[1\] " "Node \"GPIO_1\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[20\] " "Node \"GPIO_1\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[21\] " "Node \"GPIO_1\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[22\] " "Node \"GPIO_1\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[23\] " "Node \"GPIO_1\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[24\] " "Node \"GPIO_1\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[25\] " "Node \"GPIO_1\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[26\] " "Node \"GPIO_1\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[27\] " "Node \"GPIO_1\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[28\] " "Node \"GPIO_1\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[29\] " "Node \"GPIO_1\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[2\] " "Node \"GPIO_1\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[30\] " "Node \"GPIO_1\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[31\] " "Node \"GPIO_1\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[32\] " "Node \"GPIO_1\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[33\] " "Node \"GPIO_1\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[3\] " "Node \"GPIO_1\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[4\] " "Node \"GPIO_1\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[5\] " "Node \"GPIO_1\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[6\] " "Node \"GPIO_1\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[7\] " "Node \"GPIO_1\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[8\] " "Node \"GPIO_1\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[9\] " "Node \"GPIO_1\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[0\] " "Node \"GPIO_1_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[1\] " "Node \"GPIO_1_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[0\] " "Node \"GPIO_2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[10\] " "Node \"GPIO_2\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[11\] " "Node \"GPIO_2\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[12\] " "Node \"GPIO_2\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[1\] " "Node \"GPIO_2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[2\] " "Node \"GPIO_2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[3\] " "Node \"GPIO_2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[4\] " "Node \"GPIO_2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[5\] " "Node \"GPIO_2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[6\] " "Node \"GPIO_2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[7\] " "Node \"GPIO_2\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[8\] " "Node \"GPIO_2\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[9\] " "Node \"GPIO_2\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[0\] " "Node \"GPIO_2_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[1\] " "Node \"GPIO_2_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[2\] " "Node \"GPIO_2_IN\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_CS_N " "Node \"G_SENSOR_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_INT " "Node \"G_SENSOR_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648634807129 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1648634807129 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648634807135 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1648634808106 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648634808179 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1648634808188 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1648634808979 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648634808979 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1648634809228 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "1 X21_Y11 X31_Y22 " "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22" { } { { "loc" "" { Generic "/home/benny/work/fpga/projects/" { { 1 { 0 "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22"} { { 11 { 0 "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22"} 21 11 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1648634809877 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1648634809877 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648634810349 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1648634810350 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1648634810350 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.26 " "Total time spent on timing analysis during the Fitter is 0.26 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1648634810362 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648634810415 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648634810595 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648634810641 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648634810790 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648634811085 ""} +{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1648634811434 ""} +{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "1 Cyclone IV E " "1 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK_50 3.3-V LVTTL R8 " "Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at R8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { CLOCK_50 } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 17 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648634811437 ""} } { } 0 169177 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1648634811437 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/projects/output_files/spectrum.fit.smsg " "Generated suppressed messages file /home/benny/work/fpga/projects/output_files/spectrum.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1648634811493 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 152 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 152 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "594 " "Peak virtual memory: 594 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648634811738 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:06:51 2022 " "Processing ended: Wed Mar 30 13:06:51 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648634811738 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648634811738 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648634811738 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1648634811738 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1648634813398 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648634813399 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 13:06:53 2022 " "Processing started: Wed Mar 30 13:06:53 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648634813399 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1648634813399 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1648634813399 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1648634814362 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1648634814388 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "383 " "Peak virtual memory: 383 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648634814651 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:06:54 2022 " "Processing ended: Wed Mar 30 13:06:54 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648634814651 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648634814651 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648634814651 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1648634814651 ""} +{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1648634814756 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1648634816039 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648634816039 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 13:06:55 2022 " "Processing started: Wed Mar 30 13:06:55 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648634816039 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648634816039 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta spectrum -c spectrum " "Command: quartus_sta spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648634816040 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1648634816067 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648634816188 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648634816190 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648634816236 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648634816236 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "spectrum.sdc " "Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1648634816441 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1648634816442 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648634816443 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648634816443 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1648634816572 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648634816573 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1648634816573 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1648634816584 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648634816597 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648634816597 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.318 " "Worst-case setup slack is -3.318" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634816598 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634816598 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.318 -121.810 CLOCK_50 " " -3.318 -121.810 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634816598 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648634816598 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.345 " "Worst-case hold slack is 0.345" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634816599 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634816599 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.345 0.000 CLOCK_50 " " 0.345 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634816599 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648634816599 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648634816600 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648634816600 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634816601 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634816601 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -110.850 CLOCK_50 " " -3.000 -110.850 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634816601 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648634816601 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648634816618 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1648634816642 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1648634817030 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648634817051 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648634817054 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648634817054 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.835 " "Worst-case setup slack is -2.835" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634817055 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634817055 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.835 -101.390 CLOCK_50 " " -2.835 -101.390 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634817055 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648634817055 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.299 " "Worst-case hold slack is 0.299" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634817057 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634817057 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.299 0.000 CLOCK_50 " " 0.299 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634817057 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648634817057 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648634817058 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648634817059 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634817060 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634817060 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -110.818 CLOCK_50 " " -3.000 -110.818 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634817060 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648634817060 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648634817078 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648634817204 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648634817204 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648634817204 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.447 " "Worst-case setup slack is -1.447" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634817206 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634817206 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.447 -37.857 CLOCK_50 " " -1.447 -37.857 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634817206 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648634817206 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.179 " "Worst-case hold slack is 0.179" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634817208 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634817208 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.179 0.000 CLOCK_50 " " 0.179 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634817208 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648634817208 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648634817210 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648634817211 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634817213 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634817213 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -94.264 CLOCK_50 " " -3.000 -94.264 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648634817213 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648634817213 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648634817512 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648634817513 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "418 " "Peak virtual memory: 418 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648634817554 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:06:57 2022 " "Processing ended: Wed Mar 30 13:06:57 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648634817554 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648634817554 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648634817554 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648634817554 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648634819209 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648634819210 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 13:06:59 2022 " "Processing started: Wed Mar 30 13:06:59 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648634819210 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648634819210 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648634819210 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648634819534 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648634819566 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_fast.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_fast.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648634819600 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648634819632 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648634819660 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648634819685 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_v_fast.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648634819711 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_v.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_v.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648634819737 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "347 " "Peak virtual memory: 347 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648634819778 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:06:59 2022 " "Processing ended: Wed Mar 30 13:06:59 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648634819778 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648634819778 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648634819778 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648634819778 ""} +{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 160 s " "Quartus II Full Compilation was successful. 0 errors, 160 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648634819883 ""} diff --git a/db/spectrum.(0).cnf.cdb b/db/spectrum.(0).cnf.cdb index 3f83dc8..f6b8a6c 100644 Binary files a/db/spectrum.(0).cnf.cdb and b/db/spectrum.(0).cnf.cdb differ diff --git a/db/spectrum.(0).cnf.hdb b/db/spectrum.(0).cnf.hdb index 9e5ab7f..f49b15e 100644 Binary files a/db/spectrum.(0).cnf.hdb and b/db/spectrum.(0).cnf.hdb differ diff --git a/db/spectrum.(1).cnf.cdb b/db/spectrum.(1).cnf.cdb index 0fe2d99..eebc780 100644 Binary files a/db/spectrum.(1).cnf.cdb and b/db/spectrum.(1).cnf.cdb differ diff --git a/db/spectrum.(1).cnf.hdb b/db/spectrum.(1).cnf.hdb index b4f72d4..84260fc 100644 Binary files a/db/spectrum.(1).cnf.hdb and b/db/spectrum.(1).cnf.hdb differ diff --git a/db/spectrum.(4).cnf.cdb b/db/spectrum.(4).cnf.cdb new file mode 100644 index 0000000..0ed57e8 Binary files /dev/null and b/db/spectrum.(4).cnf.cdb differ diff --git a/db/spectrum.(4).cnf.hdb b/db/spectrum.(4).cnf.hdb new file mode 100644 index 0000000..87c05b9 Binary files /dev/null and b/db/spectrum.(4).cnf.hdb differ diff --git a/db/spectrum.(5).cnf.cdb b/db/spectrum.(5).cnf.cdb new file mode 100644 index 0000000..e0c05d1 Binary files /dev/null and b/db/spectrum.(5).cnf.cdb differ diff --git a/db/spectrum.(5).cnf.hdb b/db/spectrum.(5).cnf.hdb new file mode 100644 index 0000000..1eb5b78 Binary files /dev/null and b/db/spectrum.(5).cnf.hdb differ diff --git a/db/spectrum.(6).cnf.cdb b/db/spectrum.(6).cnf.cdb new file mode 100644 index 0000000..7e896dc Binary files /dev/null and b/db/spectrum.(6).cnf.cdb differ diff --git a/db/spectrum.(6).cnf.hdb b/db/spectrum.(6).cnf.hdb new file mode 100644 index 0000000..dfab121 Binary files /dev/null and b/db/spectrum.(6).cnf.hdb differ diff --git a/db/spectrum.(7).cnf.cdb b/db/spectrum.(7).cnf.cdb new file mode 100644 index 0000000..bfccce3 Binary files /dev/null and b/db/spectrum.(7).cnf.cdb differ diff --git a/db/spectrum.(7).cnf.hdb b/db/spectrum.(7).cnf.hdb new file mode 100644 index 0000000..341920e Binary files /dev/null and b/db/spectrum.(7).cnf.hdb differ diff --git a/db/spectrum.asm.qmsg b/db/spectrum.asm.qmsg index 9f4c00f..71e39ad 100644 --- a/db/spectrum.asm.qmsg +++ b/db/spectrum.asm.qmsg @@ -1,6 +1,6 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648633116429 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648633116430 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 12:38:36 2022 " "Processing started: Wed Mar 30 12:38:36 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648633116430 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1648633116430 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1648633116430 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1648633117331 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1648633117357 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "393 " "Peak virtual memory: 393 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648633117592 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 12:38:37 2022 " "Processing ended: Wed Mar 30 12:38:37 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648633117592 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648633117592 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648633117592 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1648633117592 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648635142046 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648635142047 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 13:12:21 2022 " "Processing started: Wed Mar 30 13:12:21 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648635142047 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1648635142047 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1648635142047 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1648635143022 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1648635143049 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "385 " "Peak virtual memory: 385 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648635143323 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:12:23 2022 " "Processing ended: Wed Mar 30 13:12:23 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648635143323 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648635143323 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648635143323 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1648635143323 ""} diff --git a/db/spectrum.asm.rdb b/db/spectrum.asm.rdb index a2cfdbe..42edf94 100644 Binary files a/db/spectrum.asm.rdb and b/db/spectrum.asm.rdb differ diff --git a/db/spectrum.asm_labs.ddb b/db/spectrum.asm_labs.ddb index 7e9aafd..f597537 100644 Binary files a/db/spectrum.asm_labs.ddb and b/db/spectrum.asm_labs.ddb differ diff --git a/db/spectrum.cbx.xml b/db/spectrum.cbx.xml index c2640c4..331b0f0 100644 --- a/db/spectrum.cbx.xml +++ b/db/spectrum.cbx.xml @@ -1,6 +1,6 @@ - + diff --git a/db/spectrum.cmp.bpm b/db/spectrum.cmp.bpm index 0f55d39..38e7f41 100644 Binary files a/db/spectrum.cmp.bpm and b/db/spectrum.cmp.bpm differ diff --git a/db/spectrum.cmp.cdb b/db/spectrum.cmp.cdb index b081f7f..ffc02ea 100644 Binary files a/db/spectrum.cmp.cdb and b/db/spectrum.cmp.cdb differ diff --git a/db/spectrum.cmp.hdb b/db/spectrum.cmp.hdb index 9cf556a..b5c9680 100644 Binary files a/db/spectrum.cmp.hdb and b/db/spectrum.cmp.hdb differ diff --git a/db/spectrum.cmp.idb b/db/spectrum.cmp.idb index fb207aa..bfa8deb 100644 Binary files a/db/spectrum.cmp.idb and b/db/spectrum.cmp.idb differ diff --git a/db/spectrum.cmp.rdb b/db/spectrum.cmp.rdb index 061060a..63cdcb7 100644 Binary files a/db/spectrum.cmp.rdb and b/db/spectrum.cmp.rdb differ diff --git a/db/spectrum.cycloneive_io_sim_cache.45um_tt_1200mv_85c_slow.hsd b/db/spectrum.cycloneive_io_sim_cache.45um_tt_1200mv_85c_slow.hsd index 7fbf94b..2005c89 100644 Binary files a/db/spectrum.cycloneive_io_sim_cache.45um_tt_1200mv_85c_slow.hsd and b/db/spectrum.cycloneive_io_sim_cache.45um_tt_1200mv_85c_slow.hsd differ diff --git a/db/spectrum.eda.qmsg b/db/spectrum.eda.qmsg index 09b95d4..dcb7668 100644 --- a/db/spectrum.eda.qmsg +++ b/db/spectrum.eda.qmsg @@ -1,12 +1,12 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648633122029 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648633122030 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 12:38:41 2022 " "Processing started: Wed Mar 30 12:38:41 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648633122030 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648633122030 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648633122031 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648633122334 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648633122355 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_fast.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_fast.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648633122376 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648633122396 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648633122418 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648633122437 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_v_fast.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648633122456 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_v.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_v.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648633122475 ""} -{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "344 " "Peak virtual memory: 344 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648633122507 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 12:38:42 2022 " "Processing ended: Wed Mar 30 12:38:42 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648633122507 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648633122507 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648633122507 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648633122507 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648635147928 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648635147929 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 13:12:27 2022 " "Processing started: Wed Mar 30 13:12:27 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648635147929 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648635147929 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648635147929 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648635148267 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648635148299 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_fast.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_fast.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648635148332 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648635148365 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648635148393 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648635148420 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_v_fast.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648635148446 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_v.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_v.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648635148473 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "343 " "Peak virtual memory: 343 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648635148515 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:12:28 2022 " "Processing ended: Wed Mar 30 13:12:28 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648635148515 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648635148515 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648635148515 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648635148515 ""} diff --git a/db/spectrum.fit.qmsg b/db/spectrum.fit.qmsg index b2d009d..75195a4 100644 --- a/db/spectrum.fit.qmsg +++ b/db/spectrum.fit.qmsg @@ -1,48 +1,48 @@ -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1648633109609 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "spectrum EP4CE22F17C6 " "Selected device EP4CE22F17C6 for design \"spectrum\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1648633109613 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648633109651 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648633109652 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648633109652 ""} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1648633109724 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1648633109735 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17C6 " "Device EP4CE10F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648633109936 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C6 " "Device EP4CE6F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648633109936 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C6 " "Device EP4CE15F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648633109936 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1648633109936 ""} -{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 334 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648633109941 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 336 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648633109941 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 338 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648633109941 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 340 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648633109941 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 342 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648633109941 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1648633109941 ""} -{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1648633109942 ""} -{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1648633109944 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "spectrum.sdc " "Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1648633110614 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1648633110615 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1648633110617 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1648633110617 ""} -{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1648633110617 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p)) " "Automatically promoted node CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G18 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648633110629 ""} } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 329 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648633110629 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1648633110867 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648633110868 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648633110868 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648633110869 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648633110869 ""} -{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1648633110869 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1648633110869 ""} -{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1648633110870 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1648633110870 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1648633110870 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1648633110870 ""} -{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS_N " "Node \"ADC_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SADDR " "Node \"ADC_SADDR\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SADDR" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCLK " "Node \"ADC_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDAT " "Node \"ADC_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_ASDO " "Node \"EPCS_ASDO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_ASDO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DATA0 " "Node \"EPCS_DATA0\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DATA0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DCLK " "Node \"EPCS_DCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_NCSO " "Node \"EPCS_NCSO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_NCSO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[0\] " "Node \"GPIO_0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[10\] " "Node \"GPIO_0\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[11\] " "Node \"GPIO_0\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[12\] " "Node \"GPIO_0\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[13\] " "Node \"GPIO_0\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[14\] " "Node \"GPIO_0\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[15\] " "Node \"GPIO_0\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[16\] " "Node \"GPIO_0\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[17\] " "Node \"GPIO_0\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[18\] " "Node \"GPIO_0\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[19\] " "Node \"GPIO_0\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[1\] " "Node \"GPIO_0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[20\] " "Node \"GPIO_0\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[21\] " "Node \"GPIO_0\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[22\] " "Node \"GPIO_0\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[23\] " "Node \"GPIO_0\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[24\] " "Node \"GPIO_0\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[25\] " "Node \"GPIO_0\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[26\] " "Node \"GPIO_0\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[27\] " "Node \"GPIO_0\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[28\] " "Node \"GPIO_0\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[29\] " "Node \"GPIO_0\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[2\] " "Node \"GPIO_0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[30\] " "Node \"GPIO_0\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[31\] " "Node \"GPIO_0\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[32\] " "Node \"GPIO_0\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[33\] " "Node \"GPIO_0\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[3\] " "Node \"GPIO_0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[4\] " "Node \"GPIO_0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[5\] " "Node \"GPIO_0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[6\] " "Node \"GPIO_0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[7\] " "Node \"GPIO_0\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[8\] " "Node \"GPIO_0\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[9\] " "Node \"GPIO_0\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[0\] " "Node \"GPIO_0_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[1\] " "Node \"GPIO_0_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[0\] " "Node \"GPIO_1\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[10\] " "Node \"GPIO_1\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[11\] " "Node \"GPIO_1\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[12\] " "Node \"GPIO_1\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[13\] " "Node \"GPIO_1\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[14\] " "Node \"GPIO_1\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[15\] " "Node \"GPIO_1\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[16\] " "Node \"GPIO_1\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[17\] " "Node \"GPIO_1\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[18\] " "Node \"GPIO_1\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[19\] " "Node \"GPIO_1\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[1\] " "Node \"GPIO_1\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[20\] " "Node \"GPIO_1\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[21\] " "Node \"GPIO_1\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[22\] " "Node \"GPIO_1\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[23\] " "Node \"GPIO_1\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[24\] " "Node \"GPIO_1\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[25\] " "Node \"GPIO_1\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[26\] " "Node \"GPIO_1\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[27\] " "Node \"GPIO_1\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[28\] " "Node \"GPIO_1\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[29\] " "Node \"GPIO_1\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[2\] " "Node \"GPIO_1\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[30\] " "Node \"GPIO_1\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[31\] " "Node \"GPIO_1\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[32\] " "Node \"GPIO_1\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[33\] " "Node \"GPIO_1\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[3\] " "Node \"GPIO_1\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[4\] " "Node \"GPIO_1\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[5\] " "Node \"GPIO_1\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[6\] " "Node \"GPIO_1\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[7\] " "Node \"GPIO_1\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[8\] " "Node \"GPIO_1\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[9\] " "Node \"GPIO_1\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[0\] " "Node \"GPIO_1_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[1\] " "Node \"GPIO_1_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[0\] " "Node \"GPIO_2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[10\] " "Node \"GPIO_2\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[11\] " "Node \"GPIO_2\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[12\] " "Node \"GPIO_2\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[1\] " "Node \"GPIO_2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[2\] " "Node \"GPIO_2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[3\] " "Node \"GPIO_2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[4\] " "Node \"GPIO_2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[5\] " "Node \"GPIO_2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[6\] " "Node \"GPIO_2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[7\] " "Node \"GPIO_2\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[8\] " "Node \"GPIO_2\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[9\] " "Node \"GPIO_2\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[0\] " "Node \"GPIO_2_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[1\] " "Node \"GPIO_2_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[2\] " "Node \"GPIO_2_IN\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_CS_N " "Node \"G_SENSOR_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_INT " "Node \"G_SENSOR_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1648633110884 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648633110890 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1648633111853 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648633111921 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1648633111930 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1648633112388 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648633112388 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1648633112627 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X32_Y23 X42_Y34 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X32_Y23 to location X42_Y34" { } { { "loc" "" { Generic "/home/benny/work/fpga/projects/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X32_Y23 to location X42_Y34"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X32_Y23 to location X42_Y34"} 32 23 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1648633113211 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1648633113211 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648633113709 ""} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1648633113709 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1648633113709 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.16 " "Total time spent on timing analysis during the Fitter is 0.16 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1648633113719 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648633113772 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648633113931 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648633113976 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648633114109 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648633114385 ""} -{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1648633114735 ""} -{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "1 Cyclone IV E " "1 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK_50 3.3-V LVTTL R8 " "Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at R8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { CLOCK_50 } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 15 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648633114738 ""} } { } 0 169177 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1648633114738 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/projects/output_files/spectrum.fit.smsg " "Generated suppressed messages file /home/benny/work/fpga/projects/output_files/spectrum.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1648633114780 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 152 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 152 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "600 " "Peak virtual memory: 600 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648633114959 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 12:38:34 2022 " "Processing ended: Wed Mar 30 12:38:34 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648633114959 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648633114959 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648633114959 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1648633114959 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1648635134783 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "spectrum EP4CE22F17C6 " "Selected device EP4CE22F17C6 for design \"spectrum\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1648635134787 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648635134825 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648635134826 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648635134826 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1648635134900 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1648635134910 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17C6 " "Device EP4CE10F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648635135113 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C6 " "Device EP4CE6F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648635135113 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C6 " "Device EP4CE15F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648635135113 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1648635135113 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 599 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648635135117 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 601 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648635135117 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 603 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648635135117 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 605 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648635135117 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 607 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648635135117 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1648635135117 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1648635135119 ""} +{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1648635135121 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "spectrum.sdc " "Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1648635135787 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1648635135788 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1648635135790 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1648635135791 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1648635135791 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p)) " "Automatically promoted node CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G18 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648635135800 ""} } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 594 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648635135800 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1648635136038 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648635136038 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648635136039 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648635136040 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648635136040 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1648635136041 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1648635136041 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1648635136041 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1648635136041 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1648635136041 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1648635136041 ""} +{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS_N " "Node \"ADC_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SADDR " "Node \"ADC_SADDR\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SADDR" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCLK " "Node \"ADC_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDAT " "Node \"ADC_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_ASDO " "Node \"EPCS_ASDO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_ASDO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DATA0 " "Node \"EPCS_DATA0\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DATA0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DCLK " "Node \"EPCS_DCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_NCSO " "Node \"EPCS_NCSO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_NCSO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[0\] " "Node \"GPIO_0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[10\] " "Node \"GPIO_0\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[11\] " "Node \"GPIO_0\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[12\] " "Node \"GPIO_0\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[13\] " "Node \"GPIO_0\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[14\] " "Node \"GPIO_0\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[15\] " "Node \"GPIO_0\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[16\] " "Node \"GPIO_0\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[17\] " "Node \"GPIO_0\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[18\] " "Node \"GPIO_0\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[19\] " "Node \"GPIO_0\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[1\] " "Node \"GPIO_0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[20\] " "Node \"GPIO_0\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[21\] " "Node \"GPIO_0\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[22\] " "Node \"GPIO_0\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[23\] " "Node \"GPIO_0\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[24\] " "Node \"GPIO_0\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[25\] " "Node \"GPIO_0\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[26\] " "Node \"GPIO_0\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[27\] " "Node \"GPIO_0\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[28\] " "Node \"GPIO_0\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[29\] " "Node \"GPIO_0\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[2\] " "Node \"GPIO_0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[30\] " "Node \"GPIO_0\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[31\] " "Node \"GPIO_0\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[32\] " "Node \"GPIO_0\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[33\] " "Node \"GPIO_0\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[3\] " "Node \"GPIO_0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[4\] " "Node \"GPIO_0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[5\] " "Node \"GPIO_0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[6\] " "Node \"GPIO_0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[7\] " "Node \"GPIO_0\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[8\] " "Node \"GPIO_0\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[9\] " "Node \"GPIO_0\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[0\] " "Node \"GPIO_0_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[1\] " "Node \"GPIO_0_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[0\] " "Node \"GPIO_1\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[10\] " "Node \"GPIO_1\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[11\] " "Node \"GPIO_1\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[12\] " "Node \"GPIO_1\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[13\] " "Node \"GPIO_1\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[14\] " "Node \"GPIO_1\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[15\] " "Node \"GPIO_1\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[16\] " "Node \"GPIO_1\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[17\] " "Node \"GPIO_1\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[18\] " "Node \"GPIO_1\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[19\] " "Node \"GPIO_1\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[1\] " "Node \"GPIO_1\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[20\] " "Node \"GPIO_1\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[21\] " "Node \"GPIO_1\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[22\] " "Node \"GPIO_1\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[23\] " "Node \"GPIO_1\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[24\] " "Node \"GPIO_1\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[25\] " "Node \"GPIO_1\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[26\] " "Node \"GPIO_1\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[27\] " "Node \"GPIO_1\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[28\] " "Node \"GPIO_1\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[29\] " "Node \"GPIO_1\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[2\] " "Node \"GPIO_1\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[30\] " "Node \"GPIO_1\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[31\] " "Node \"GPIO_1\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[32\] " "Node \"GPIO_1\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[33\] " "Node \"GPIO_1\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[3\] " "Node \"GPIO_1\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[4\] " "Node \"GPIO_1\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[5\] " "Node \"GPIO_1\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[6\] " "Node \"GPIO_1\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[7\] " "Node \"GPIO_1\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[8\] " "Node \"GPIO_1\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[9\] " "Node \"GPIO_1\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[0\] " "Node \"GPIO_1_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[1\] " "Node \"GPIO_1_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[0\] " "Node \"GPIO_2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[10\] " "Node \"GPIO_2\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[11\] " "Node \"GPIO_2\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[12\] " "Node \"GPIO_2\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[1\] " "Node \"GPIO_2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[2\] " "Node \"GPIO_2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[3\] " "Node \"GPIO_2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[4\] " "Node \"GPIO_2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[5\] " "Node \"GPIO_2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[6\] " "Node \"GPIO_2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[7\] " "Node \"GPIO_2\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[8\] " "Node \"GPIO_2\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[9\] " "Node \"GPIO_2\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[0\] " "Node \"GPIO_2_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[1\] " "Node \"GPIO_2_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[2\] " "Node \"GPIO_2_IN\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_CS_N " "Node \"G_SENSOR_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_INT " "Node \"G_SENSOR_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648635136056 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1648635136056 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648635136063 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1648635137043 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648635137115 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1648635137123 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1648635137770 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648635137770 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1648635138018 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "2 X21_Y11 X31_Y22 " "Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22" { } { { "loc" "" { Generic "/home/benny/work/fpga/projects/" { { 1 { 0 "Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22"} { { 11 { 0 "Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22"} 21 11 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1648635138667 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1648635138667 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648635139098 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1648635139098 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1648635139098 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.22 " "Total time spent on timing analysis during the Fitter is 0.22 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1648635139111 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648635139164 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648635139345 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648635139390 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648635139538 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648635139840 ""} +{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1648635140193 ""} +{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "1 Cyclone IV E " "1 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK_50 3.3-V LVTTL R8 " "Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at R8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { CLOCK_50 } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 17 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648635140197 ""} } { } 0 169177 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1648635140197 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/projects/output_files/spectrum.fit.smsg " "Generated suppressed messages file /home/benny/work/fpga/projects/output_files/spectrum.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1648635140253 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 152 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 152 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "595 " "Peak virtual memory: 595 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648635140493 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:12:20 2022 " "Processing ended: Wed Mar 30 13:12:20 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648635140493 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648635140493 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648635140493 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1648635140493 ""} diff --git a/db/spectrum.hier_info b/db/spectrum.hier_info index 8eef65f..a594bd4 100644 --- a/db/spectrum.hier_info +++ b/db/spectrum.hier_info @@ -14,6 +14,17 @@ LED[7] <= rom0:rom.q address[0] => address[0].IN1 address[1] => address[1].IN1 address[2] => address[2].IN1 +address[3] => address[3].IN1 +address[4] => address[4].IN1 +address[5] => address[5].IN1 +address[6] => address[6].IN1 +address[7] => address[7].IN1 +address[8] => address[8].IN1 +address[9] => address[9].IN1 +address[10] => address[10].IN1 +address[11] => address[11].IN1 +address[12] => address[12].IN1 +address[13] => address[13].IN1 clock => clock.IN1 q[0] <= altsyncram:altsyncram_component.q_a q[1] <= altsyncram:altsyncram_component.q_a @@ -39,13 +50,24 @@ data_a[5] => ~NO_FANOUT~ data_a[6] => ~NO_FANOUT~ data_a[7] => ~NO_FANOUT~ data_b[0] => ~NO_FANOUT~ -address_a[0] => altsyncram_ro91:auto_generated.address_a[0] -address_a[1] => altsyncram_ro91:auto_generated.address_a[1] -address_a[2] => altsyncram_ro91:auto_generated.address_a[2] +address_a[0] => altsyncram_qh91:auto_generated.address_a[0] +address_a[1] => altsyncram_qh91:auto_generated.address_a[1] +address_a[2] => altsyncram_qh91:auto_generated.address_a[2] +address_a[3] => altsyncram_qh91:auto_generated.address_a[3] +address_a[4] => altsyncram_qh91:auto_generated.address_a[4] +address_a[5] => altsyncram_qh91:auto_generated.address_a[5] +address_a[6] => altsyncram_qh91:auto_generated.address_a[6] +address_a[7] => altsyncram_qh91:auto_generated.address_a[7] +address_a[8] => altsyncram_qh91:auto_generated.address_a[8] +address_a[9] => altsyncram_qh91:auto_generated.address_a[9] +address_a[10] => altsyncram_qh91:auto_generated.address_a[10] +address_a[11] => altsyncram_qh91:auto_generated.address_a[11] +address_a[12] => altsyncram_qh91:auto_generated.address_a[12] +address_a[13] => altsyncram_qh91:auto_generated.address_a[13] address_b[0] => ~NO_FANOUT~ addressstall_a => ~NO_FANOUT~ addressstall_b => ~NO_FANOUT~ -clock0 => altsyncram_ro91:auto_generated.clock0 +clock0 => altsyncram_qh91:auto_generated.clock0 clock1 => ~NO_FANOUT~ clocken0 => ~NO_FANOUT~ clocken1 => ~NO_FANOUT~ @@ -55,21 +77,21 @@ aclr0 => ~NO_FANOUT~ aclr1 => ~NO_FANOUT~ byteena_a[0] => ~NO_FANOUT~ byteena_b[0] => ~NO_FANOUT~ -q_a[0] <= altsyncram_ro91:auto_generated.q_a[0] -q_a[1] <= altsyncram_ro91:auto_generated.q_a[1] -q_a[2] <= altsyncram_ro91:auto_generated.q_a[2] -q_a[3] <= altsyncram_ro91:auto_generated.q_a[3] -q_a[4] <= altsyncram_ro91:auto_generated.q_a[4] -q_a[5] <= altsyncram_ro91:auto_generated.q_a[5] -q_a[6] <= altsyncram_ro91:auto_generated.q_a[6] -q_a[7] <= altsyncram_ro91:auto_generated.q_a[7] +q_a[0] <= altsyncram_qh91:auto_generated.q_a[0] +q_a[1] <= altsyncram_qh91:auto_generated.q_a[1] +q_a[2] <= altsyncram_qh91:auto_generated.q_a[2] +q_a[3] <= altsyncram_qh91:auto_generated.q_a[3] +q_a[4] <= altsyncram_qh91:auto_generated.q_a[4] +q_a[5] <= altsyncram_qh91:auto_generated.q_a[5] +q_a[6] <= altsyncram_qh91:auto_generated.q_a[6] +q_a[7] <= altsyncram_qh91:auto_generated.q_a[7] q_b[0] <= eccstatus[0] <= eccstatus[1] <= eccstatus[2] <= -|spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated +|spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated address_a[0] => ram_block1a0.PORTAADDR address_a[0] => ram_block1a1.PORTAADDR address_a[0] => ram_block1a2.PORTAADDR @@ -78,6 +100,14 @@ address_a[0] => ram_block1a4.PORTAADDR address_a[0] => ram_block1a5.PORTAADDR address_a[0] => ram_block1a6.PORTAADDR address_a[0] => ram_block1a7.PORTAADDR +address_a[0] => ram_block1a8.PORTAADDR +address_a[0] => ram_block1a9.PORTAADDR +address_a[0] => ram_block1a10.PORTAADDR +address_a[0] => ram_block1a11.PORTAADDR +address_a[0] => ram_block1a12.PORTAADDR +address_a[0] => ram_block1a13.PORTAADDR +address_a[0] => ram_block1a14.PORTAADDR +address_a[0] => ram_block1a15.PORTAADDR address_a[1] => ram_block1a0.PORTAADDR1 address_a[1] => ram_block1a1.PORTAADDR1 address_a[1] => ram_block1a2.PORTAADDR1 @@ -86,6 +116,14 @@ address_a[1] => ram_block1a4.PORTAADDR1 address_a[1] => ram_block1a5.PORTAADDR1 address_a[1] => ram_block1a6.PORTAADDR1 address_a[1] => ram_block1a7.PORTAADDR1 +address_a[1] => ram_block1a8.PORTAADDR1 +address_a[1] => ram_block1a9.PORTAADDR1 +address_a[1] => ram_block1a10.PORTAADDR1 +address_a[1] => ram_block1a11.PORTAADDR1 +address_a[1] => ram_block1a12.PORTAADDR1 +address_a[1] => ram_block1a13.PORTAADDR1 +address_a[1] => ram_block1a14.PORTAADDR1 +address_a[1] => ram_block1a15.PORTAADDR1 address_a[2] => ram_block1a0.PORTAADDR2 address_a[2] => ram_block1a1.PORTAADDR2 address_a[2] => ram_block1a2.PORTAADDR2 @@ -94,6 +132,176 @@ address_a[2] => ram_block1a4.PORTAADDR2 address_a[2] => ram_block1a5.PORTAADDR2 address_a[2] => ram_block1a6.PORTAADDR2 address_a[2] => ram_block1a7.PORTAADDR2 +address_a[2] => ram_block1a8.PORTAADDR2 +address_a[2] => ram_block1a9.PORTAADDR2 +address_a[2] => ram_block1a10.PORTAADDR2 +address_a[2] => ram_block1a11.PORTAADDR2 +address_a[2] => ram_block1a12.PORTAADDR2 +address_a[2] => ram_block1a13.PORTAADDR2 +address_a[2] => ram_block1a14.PORTAADDR2 +address_a[2] => ram_block1a15.PORTAADDR2 +address_a[3] => ram_block1a0.PORTAADDR3 +address_a[3] => ram_block1a1.PORTAADDR3 +address_a[3] => ram_block1a2.PORTAADDR3 +address_a[3] => ram_block1a3.PORTAADDR3 +address_a[3] => ram_block1a4.PORTAADDR3 +address_a[3] => ram_block1a5.PORTAADDR3 +address_a[3] => ram_block1a6.PORTAADDR3 +address_a[3] => ram_block1a7.PORTAADDR3 +address_a[3] => ram_block1a8.PORTAADDR3 +address_a[3] => ram_block1a9.PORTAADDR3 +address_a[3] => ram_block1a10.PORTAADDR3 +address_a[3] => ram_block1a11.PORTAADDR3 +address_a[3] => ram_block1a12.PORTAADDR3 +address_a[3] => ram_block1a13.PORTAADDR3 +address_a[3] => ram_block1a14.PORTAADDR3 +address_a[3] => ram_block1a15.PORTAADDR3 +address_a[4] => ram_block1a0.PORTAADDR4 +address_a[4] => ram_block1a1.PORTAADDR4 +address_a[4] => ram_block1a2.PORTAADDR4 +address_a[4] => ram_block1a3.PORTAADDR4 +address_a[4] => ram_block1a4.PORTAADDR4 +address_a[4] => ram_block1a5.PORTAADDR4 +address_a[4] => ram_block1a6.PORTAADDR4 +address_a[4] => ram_block1a7.PORTAADDR4 +address_a[4] => ram_block1a8.PORTAADDR4 +address_a[4] => ram_block1a9.PORTAADDR4 +address_a[4] => ram_block1a10.PORTAADDR4 +address_a[4] => ram_block1a11.PORTAADDR4 +address_a[4] => ram_block1a12.PORTAADDR4 +address_a[4] => ram_block1a13.PORTAADDR4 +address_a[4] => ram_block1a14.PORTAADDR4 +address_a[4] => ram_block1a15.PORTAADDR4 +address_a[5] => ram_block1a0.PORTAADDR5 +address_a[5] => ram_block1a1.PORTAADDR5 +address_a[5] => ram_block1a2.PORTAADDR5 +address_a[5] => ram_block1a3.PORTAADDR5 +address_a[5] => ram_block1a4.PORTAADDR5 +address_a[5] => ram_block1a5.PORTAADDR5 +address_a[5] => ram_block1a6.PORTAADDR5 +address_a[5] => ram_block1a7.PORTAADDR5 +address_a[5] => ram_block1a8.PORTAADDR5 +address_a[5] => ram_block1a9.PORTAADDR5 +address_a[5] => ram_block1a10.PORTAADDR5 +address_a[5] => ram_block1a11.PORTAADDR5 +address_a[5] => ram_block1a12.PORTAADDR5 +address_a[5] => ram_block1a13.PORTAADDR5 +address_a[5] => ram_block1a14.PORTAADDR5 +address_a[5] => ram_block1a15.PORTAADDR5 +address_a[6] => ram_block1a0.PORTAADDR6 +address_a[6] => ram_block1a1.PORTAADDR6 +address_a[6] => ram_block1a2.PORTAADDR6 +address_a[6] => ram_block1a3.PORTAADDR6 +address_a[6] => ram_block1a4.PORTAADDR6 +address_a[6] => ram_block1a5.PORTAADDR6 +address_a[6] => ram_block1a6.PORTAADDR6 +address_a[6] => ram_block1a7.PORTAADDR6 +address_a[6] => ram_block1a8.PORTAADDR6 +address_a[6] => ram_block1a9.PORTAADDR6 +address_a[6] => ram_block1a10.PORTAADDR6 +address_a[6] => ram_block1a11.PORTAADDR6 +address_a[6] => ram_block1a12.PORTAADDR6 +address_a[6] => ram_block1a13.PORTAADDR6 +address_a[6] => ram_block1a14.PORTAADDR6 +address_a[6] => ram_block1a15.PORTAADDR6 +address_a[7] => ram_block1a0.PORTAADDR7 +address_a[7] => ram_block1a1.PORTAADDR7 +address_a[7] => ram_block1a2.PORTAADDR7 +address_a[7] => ram_block1a3.PORTAADDR7 +address_a[7] => ram_block1a4.PORTAADDR7 +address_a[7] => ram_block1a5.PORTAADDR7 +address_a[7] => ram_block1a6.PORTAADDR7 +address_a[7] => ram_block1a7.PORTAADDR7 +address_a[7] => ram_block1a8.PORTAADDR7 +address_a[7] => ram_block1a9.PORTAADDR7 +address_a[7] => ram_block1a10.PORTAADDR7 +address_a[7] => ram_block1a11.PORTAADDR7 +address_a[7] => ram_block1a12.PORTAADDR7 +address_a[7] => ram_block1a13.PORTAADDR7 +address_a[7] => ram_block1a14.PORTAADDR7 +address_a[7] => ram_block1a15.PORTAADDR7 +address_a[8] => ram_block1a0.PORTAADDR8 +address_a[8] => ram_block1a1.PORTAADDR8 +address_a[8] => ram_block1a2.PORTAADDR8 +address_a[8] => ram_block1a3.PORTAADDR8 +address_a[8] => ram_block1a4.PORTAADDR8 +address_a[8] => ram_block1a5.PORTAADDR8 +address_a[8] => ram_block1a6.PORTAADDR8 +address_a[8] => ram_block1a7.PORTAADDR8 +address_a[8] => ram_block1a8.PORTAADDR8 +address_a[8] => ram_block1a9.PORTAADDR8 +address_a[8] => ram_block1a10.PORTAADDR8 +address_a[8] => ram_block1a11.PORTAADDR8 +address_a[8] => ram_block1a12.PORTAADDR8 +address_a[8] => ram_block1a13.PORTAADDR8 +address_a[8] => ram_block1a14.PORTAADDR8 +address_a[8] => ram_block1a15.PORTAADDR8 +address_a[9] => ram_block1a0.PORTAADDR9 +address_a[9] => ram_block1a1.PORTAADDR9 +address_a[9] => ram_block1a2.PORTAADDR9 +address_a[9] => ram_block1a3.PORTAADDR9 +address_a[9] => ram_block1a4.PORTAADDR9 +address_a[9] => ram_block1a5.PORTAADDR9 +address_a[9] => ram_block1a6.PORTAADDR9 +address_a[9] => ram_block1a7.PORTAADDR9 +address_a[9] => ram_block1a8.PORTAADDR9 +address_a[9] => ram_block1a9.PORTAADDR9 +address_a[9] => ram_block1a10.PORTAADDR9 +address_a[9] => ram_block1a11.PORTAADDR9 +address_a[9] => ram_block1a12.PORTAADDR9 +address_a[9] => ram_block1a13.PORTAADDR9 +address_a[9] => ram_block1a14.PORTAADDR9 +address_a[9] => ram_block1a15.PORTAADDR9 +address_a[10] => ram_block1a0.PORTAADDR10 +address_a[10] => ram_block1a1.PORTAADDR10 +address_a[10] => ram_block1a2.PORTAADDR10 +address_a[10] => ram_block1a3.PORTAADDR10 +address_a[10] => ram_block1a4.PORTAADDR10 +address_a[10] => ram_block1a5.PORTAADDR10 +address_a[10] => ram_block1a6.PORTAADDR10 +address_a[10] => ram_block1a7.PORTAADDR10 +address_a[10] => ram_block1a8.PORTAADDR10 +address_a[10] => ram_block1a9.PORTAADDR10 +address_a[10] => ram_block1a10.PORTAADDR10 +address_a[10] => ram_block1a11.PORTAADDR10 +address_a[10] => ram_block1a12.PORTAADDR10 +address_a[10] => ram_block1a13.PORTAADDR10 +address_a[10] => ram_block1a14.PORTAADDR10 +address_a[10] => ram_block1a15.PORTAADDR10 +address_a[11] => ram_block1a0.PORTAADDR11 +address_a[11] => ram_block1a1.PORTAADDR11 +address_a[11] => ram_block1a2.PORTAADDR11 +address_a[11] => ram_block1a3.PORTAADDR11 +address_a[11] => ram_block1a4.PORTAADDR11 +address_a[11] => ram_block1a5.PORTAADDR11 +address_a[11] => ram_block1a6.PORTAADDR11 +address_a[11] => ram_block1a7.PORTAADDR11 +address_a[11] => ram_block1a8.PORTAADDR11 +address_a[11] => ram_block1a9.PORTAADDR11 +address_a[11] => ram_block1a10.PORTAADDR11 +address_a[11] => ram_block1a11.PORTAADDR11 +address_a[11] => ram_block1a12.PORTAADDR11 +address_a[11] => ram_block1a13.PORTAADDR11 +address_a[11] => ram_block1a14.PORTAADDR11 +address_a[11] => ram_block1a15.PORTAADDR11 +address_a[12] => ram_block1a0.PORTAADDR12 +address_a[12] => ram_block1a1.PORTAADDR12 +address_a[12] => ram_block1a2.PORTAADDR12 +address_a[12] => ram_block1a3.PORTAADDR12 +address_a[12] => ram_block1a4.PORTAADDR12 +address_a[12] => ram_block1a5.PORTAADDR12 +address_a[12] => ram_block1a6.PORTAADDR12 +address_a[12] => ram_block1a7.PORTAADDR12 +address_a[12] => ram_block1a8.PORTAADDR12 +address_a[12] => ram_block1a9.PORTAADDR12 +address_a[12] => ram_block1a10.PORTAADDR12 +address_a[12] => ram_block1a11.PORTAADDR12 +address_a[12] => ram_block1a12.PORTAADDR12 +address_a[12] => ram_block1a13.PORTAADDR12 +address_a[12] => ram_block1a14.PORTAADDR12 +address_a[12] => ram_block1a15.PORTAADDR12 +address_a[13] => address_reg_a[0].DATAIN +address_a[13] => decode_c8a:rden_decode.data[0] clock0 => ram_block1a0.CLK0 clock0 => ram_block1a1.CLK0 clock0 => ram_block1a2.CLK0 @@ -102,13 +310,73 @@ clock0 => ram_block1a4.CLK0 clock0 => ram_block1a5.CLK0 clock0 => ram_block1a6.CLK0 clock0 => ram_block1a7.CLK0 -q_a[0] <= ram_block1a0.PORTADATAOUT -q_a[1] <= ram_block1a1.PORTADATAOUT -q_a[2] <= ram_block1a2.PORTADATAOUT -q_a[3] <= ram_block1a3.PORTADATAOUT -q_a[4] <= ram_block1a4.PORTADATAOUT -q_a[5] <= ram_block1a5.PORTADATAOUT -q_a[6] <= ram_block1a6.PORTADATAOUT -q_a[7] <= ram_block1a7.PORTADATAOUT +clock0 => ram_block1a8.CLK0 +clock0 => ram_block1a9.CLK0 +clock0 => ram_block1a10.CLK0 +clock0 => ram_block1a11.CLK0 +clock0 => ram_block1a12.CLK0 +clock0 => ram_block1a13.CLK0 +clock0 => ram_block1a14.CLK0 +clock0 => ram_block1a15.CLK0 +clock0 => address_reg_a[0].CLK +clock0 => out_address_reg_a[0].CLK +q_a[0] <= mux_3nb:mux2.result[0] +q_a[1] <= mux_3nb:mux2.result[1] +q_a[2] <= mux_3nb:mux2.result[2] +q_a[3] <= mux_3nb:mux2.result[3] +q_a[4] <= mux_3nb:mux2.result[4] +q_a[5] <= mux_3nb:mux2.result[5] +q_a[6] <= mux_3nb:mux2.result[6] +q_a[7] <= mux_3nb:mux2.result[7] + + +|spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|decode_c8a:rden_decode +data[0] => eq_node[1].IN0 +data[0] => eq_node[0].IN0 +eq[0] <= eq_node[0].DB_MAX_OUTPUT_PORT_TYPE +eq[1] <= eq_node[1].DB_MAX_OUTPUT_PORT_TYPE + + +|spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|mux_3nb:mux2 +data[0] => result_node[0].IN1 +data[1] => result_node[1].IN1 +data[2] => result_node[2].IN1 +data[3] => result_node[3].IN1 +data[4] => result_node[4].IN1 +data[5] => result_node[5].IN1 +data[6] => result_node[6].IN1 +data[7] => result_node[7].IN1 +data[8] => result_node[0].IN1 +data[9] => result_node[1].IN1 +data[10] => result_node[2].IN1 +data[11] => result_node[3].IN1 +data[12] => result_node[4].IN1 +data[13] => result_node[5].IN1 +data[14] => result_node[6].IN1 +data[15] => result_node[7].IN1 +result[0] <= result_node[0].DB_MAX_OUTPUT_PORT_TYPE +result[1] <= result_node[1].DB_MAX_OUTPUT_PORT_TYPE +result[2] <= result_node[2].DB_MAX_OUTPUT_PORT_TYPE +result[3] <= result_node[3].DB_MAX_OUTPUT_PORT_TYPE +result[4] <= result_node[4].DB_MAX_OUTPUT_PORT_TYPE +result[5] <= result_node[5].DB_MAX_OUTPUT_PORT_TYPE +result[6] <= result_node[6].DB_MAX_OUTPUT_PORT_TYPE +result[7] <= result_node[7].DB_MAX_OUTPUT_PORT_TYPE +sel[0] => result_node[7].IN0 +sel[0] => _.IN0 +sel[0] => result_node[6].IN0 +sel[0] => _.IN0 +sel[0] => result_node[5].IN0 +sel[0] => _.IN0 +sel[0] => result_node[4].IN0 +sel[0] => _.IN0 +sel[0] => result_node[3].IN0 +sel[0] => _.IN0 +sel[0] => result_node[2].IN0 +sel[0] => _.IN0 +sel[0] => result_node[1].IN0 +sel[0] => _.IN0 +sel[0] => result_node[0].IN0 +sel[0] => _.IN0 diff --git a/db/spectrum.hif b/db/spectrum.hif index 0eb8925..a5d2bd5 100644 Binary files a/db/spectrum.hif and b/db/spectrum.hif differ diff --git a/db/spectrum.lpc.html b/db/spectrum.lpc.html index 64d61ed..4e15f36 100644 --- a/db/spectrum.lpc.html +++ b/db/spectrum.lpc.html @@ -16,8 +16,40 @@ Output only Bidir +rom|altsyncram_component|auto_generated|mux2 +17 +0 +0 +0 +8 +0 +0 +0 +0 +0 +0 +0 +0 + + +rom|altsyncram_component|auto_generated|rden_decode +1 +0 +0 +0 +2 +0 +0 +0 +0 +0 +0 +0 +0 + + rom|altsyncram_component|auto_generated -4 +15 0 0 0 @@ -33,7 +65,7 @@ rom -4 +15 0 0 0 diff --git a/db/spectrum.lpc.rdb b/db/spectrum.lpc.rdb index 7e954c4..60aa6e4 100644 Binary files a/db/spectrum.lpc.rdb and b/db/spectrum.lpc.rdb differ diff --git a/db/spectrum.lpc.txt b/db/spectrum.lpc.txt index 0c0421d..f5b698d 100644 --- a/db/spectrum.lpc.txt +++ b/db/spectrum.lpc.txt @@ -1,8 +1,38 @@ +--------------------------------------------------------------------------------+ ; Legal Partition Candidates ; +--------------------------------------------------------------------------------+ +Hierarchy : rom|altsyncram_component|auto_generated|mux2 +Input : 17 +Constant Input : 0 +Unused Input : 0 +Floating Input : 0 +Output : 8 +Constant Output : 0 +Unused Output : 0 +Floating Output : 0 +Bidir : 0 +Constant Bidir : 0 +Unused Bidir : 0 +Input only Bidir : 0 +Output only Bidir : 0 + +Hierarchy : rom|altsyncram_component|auto_generated|rden_decode +Input : 1 +Constant Input : 0 +Unused Input : 0 +Floating Input : 0 +Output : 2 +Constant Output : 0 +Unused Output : 0 +Floating Output : 0 +Bidir : 0 +Constant Bidir : 0 +Unused Bidir : 0 +Input only Bidir : 0 +Output only Bidir : 0 + Hierarchy : rom|altsyncram_component|auto_generated -Input : 4 +Input : 15 Constant Input : 0 Unused Input : 0 Floating Input : 0 @@ -17,7 +47,7 @@ Input only Bidir : 0 Output only Bidir : 0 Hierarchy : rom -Input : 4 +Input : 15 Constant Input : 0 Unused Input : 0 Floating Input : 0 diff --git a/db/spectrum.map.bpm b/db/spectrum.map.bpm index de551a6..2ca9d2f 100644 Binary files a/db/spectrum.map.bpm and b/db/spectrum.map.bpm differ diff --git a/db/spectrum.map.cdb b/db/spectrum.map.cdb index 1de03c9..afe5518 100644 Binary files a/db/spectrum.map.cdb and b/db/spectrum.map.cdb differ diff --git a/db/spectrum.map.hdb b/db/spectrum.map.hdb index 43258f9..014c8c0 100644 Binary files a/db/spectrum.map.hdb and b/db/spectrum.map.hdb differ diff --git a/db/spectrum.map.kpt b/db/spectrum.map.kpt index d696b5c..9ceab4e 100644 Binary files a/db/spectrum.map.kpt and b/db/spectrum.map.kpt differ diff --git a/db/spectrum.map.qmsg b/db/spectrum.map.qmsg index df94b18..6061c3b 100644 --- a/db/spectrum.map.qmsg +++ b/db/spectrum.map.qmsg @@ -1,19 +1,23 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648633107075 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648633107076 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 12:38:26 2022 " "Processing started: Wed Mar 30 12:38:26 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648633107076 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648633107076 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum " "Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648633107076 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648633107239 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spectrum.v 1 1 " "Found 1 design units, including 1 entities, in source file spectrum.v" { { "Info" "ISGN_ENTITY_NAME" "1 spectrum " "Found entity 1: spectrum" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648633107303 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648633107303 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom0.v 1 1 " "Found 1 design units, including 1 entities, in source file rom0.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom0 " "Found entity 1: rom0" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648633107306 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648633107306 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "spectrum " "Elaborating entity \"spectrum\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1648633107357 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 21 spectrum.v(19) " "Verilog HDL assignment warning at spectrum.v(19): truncated value with size 32 to match size of target (21)" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 19 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1648633107359 "|spectrum"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 spectrum.v(21) " "Verilog HDL assignment warning at spectrum.v(21): truncated value with size 32 to match size of target (3)" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 21 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1648633107359 "|spectrum"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom0 rom0:rom " "Elaborating entity \"rom0\" for hierarchy \"rom0:rom\"" { } { { "spectrum.v" "rom" { Text "/home/benny/work/fpga/projects/spectrum.v" 14 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107369 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram rom0:rom\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "altsyncram_component" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107416 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "rom0:rom\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rom0:rom\|altsyncram:altsyncram_component " "Instantiated megafunction \"rom0:rom\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file led_patterns.mif " "Parameter \"init_file\" = \"led_patterns.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 8 " "Parameter \"numwords_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 3 " "Parameter \"widthad_a\" = \"3\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} } { { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648633107417 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_ro91.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_ro91.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_ro91 " "Found entity 1: altsyncram_ro91" { } { { "db/altsyncram_ro91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_ro91.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648633107463 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648633107463 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_ro91 rom0:rom\|altsyncram:altsyncram_component\|altsyncram_ro91:auto_generated " "Elaborating entity \"altsyncram_ro91\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_ro91:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107464 ""} -{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1648633107974 ""} -{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1648633108175 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648633108175 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "71 " "Implemented 71 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Implemented 1 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1648633108217 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1648633108217 ""} { "Info" "ICUT_CUT_TM_LCELLS" "54 " "Implemented 54 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1648633108217 ""} { "Info" "ICUT_CUT_TM_RAMS" "8 " "Implemented 8 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Quartus II" 0 -1 1648633108217 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1648633108217 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "384 " "Peak virtual memory: 384 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648633108224 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 12:38:28 2022 " "Processing ended: Wed Mar 30 12:38:28 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648633108224 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648633108224 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648633108224 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648633108224 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648635132020 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648635132022 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 13:12:11 2022 " "Processing started: Wed Mar 30 13:12:11 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648635132022 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648635132022 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum " "Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648635132022 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648635132212 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spectrum.v 1 1 " "Found 1 design units, including 1 entities, in source file spectrum.v" { { "Info" "ISGN_ENTITY_NAME" "1 spectrum " "Found entity 1: spectrum" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648635132282 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648635132282 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom0.v 1 1 " "Found 1 design units, including 1 entities, in source file rom0.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom0 " "Found entity 1: rom0" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648635132284 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648635132284 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "spectrum " "Elaborating entity \"spectrum\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1648635132338 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 22 spectrum.v(18) " "Verilog HDL assignment warning at spectrum.v(18): truncated value with size 32 to match size of target (22)" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 18 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1648635132340 "|spectrum"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 spectrum.v(20) " "Verilog HDL assignment warning at spectrum.v(20): truncated value with size 32 to match size of target (14)" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 20 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1648635132340 "|spectrum"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom0 rom0:rom " "Elaborating entity \"rom0\" for hierarchy \"rom0:rom\"" { } { { "spectrum.v" "rom" { Text "/home/benny/work/fpga/projects/spectrum.v" 13 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132350 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram rom0:rom\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "altsyncram_component" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132402 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "rom0:rom\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648635132403 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rom0:rom\|altsyncram:altsyncram_component " "Instantiated megafunction \"rom0:rom\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132403 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132403 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132403 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file ./rom/gw03.hex " "Parameter \"init_file\" = \"./rom/gw03.hex\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132403 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132403 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132403 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132403 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 16384 " "Parameter \"numwords_a\" = \"16384\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132403 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132403 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132403 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132403 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 14 " "Parameter \"widthad_a\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132403 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132403 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132403 ""} } { { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648635132403 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_qh91.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_qh91.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_qh91 " "Found entity 1: altsyncram_qh91" { } { { "db/altsyncram_qh91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 31 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648635132451 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648635132451 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_qh91 rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated " "Elaborating entity \"altsyncram_qh91\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132452 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_c8a.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_c8a.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_c8a " "Found entity 1: decode_c8a" { } { { "db/decode_c8a.tdf" "" { Text "/home/benny/work/fpga/projects/db/decode_c8a.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648635132495 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648635132495 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_c8a rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|decode_c8a:rden_decode " "Elaborating entity \"decode_c8a\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|decode_c8a:rden_decode\"" { } { { "db/altsyncram_qh91.tdf" "rden_decode" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 40 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132495 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_3nb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_3nb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_3nb " "Found entity 1: mux_3nb" { } { { "db/mux_3nb.tdf" "" { Text "/home/benny/work/fpga/projects/db/mux_3nb.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648635132537 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648635132537 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_3nb rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|mux_3nb:mux2 " "Elaborating entity \"mux_3nb\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_qh91:auto_generated\|mux_3nb:mux2\"" { } { { "db/altsyncram_qh91.tdf" "mux2" { Text "/home/benny/work/fpga/projects/db/altsyncram_qh91.tdf" 41 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648635132537 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1648635133078 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1648635133316 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648635133316 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "79 " "Implemented 79 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Implemented 1 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1648635133366 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1648635133366 ""} { "Info" "ICUT_CUT_TM_LCELLS" "54 " "Implemented 54 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1648635133366 ""} { "Info" "ICUT_CUT_TM_RAMS" "16 " "Implemented 16 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Quartus II" 0 -1 1648635133366 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1648635133366 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "392 " "Peak virtual memory: 392 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648635133374 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:12:13 2022 " "Processing ended: Wed Mar 30 13:12:13 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648635133374 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648635133374 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648635133374 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648635133374 ""} diff --git a/db/spectrum.map.rdb b/db/spectrum.map.rdb index af645e1..f2733e7 100644 Binary files a/db/spectrum.map.rdb and b/db/spectrum.map.rdb differ diff --git a/db/spectrum.map_bb.cdb b/db/spectrum.map_bb.cdb index 62e3482..05be201 100644 Binary files a/db/spectrum.map_bb.cdb and b/db/spectrum.map_bb.cdb differ diff --git a/db/spectrum.map_bb.hdb b/db/spectrum.map_bb.hdb index 2c52639..f81bc6e 100644 Binary files a/db/spectrum.map_bb.hdb and b/db/spectrum.map_bb.hdb differ diff --git a/db/spectrum.pre_map.hdb b/db/spectrum.pre_map.hdb index f253d5f..690c2ed 100644 Binary files a/db/spectrum.pre_map.hdb and b/db/spectrum.pre_map.hdb differ diff --git a/db/spectrum.routing.rdb b/db/spectrum.routing.rdb index 94d9041..9e044fd 100644 Binary files a/db/spectrum.routing.rdb and b/db/spectrum.routing.rdb differ diff --git a/db/spectrum.rtlv.hdb b/db/spectrum.rtlv.hdb index d4688ac..965ec73 100644 Binary files a/db/spectrum.rtlv.hdb and b/db/spectrum.rtlv.hdb differ diff --git a/db/spectrum.rtlv_sg.cdb b/db/spectrum.rtlv_sg.cdb index 722a8c8..ba4e5ec 100644 Binary files a/db/spectrum.rtlv_sg.cdb and b/db/spectrum.rtlv_sg.cdb differ diff --git a/db/spectrum.rtlv_sg_swap.cdb b/db/spectrum.rtlv_sg_swap.cdb index 3e6cc42..2cbcdfd 100644 Binary files a/db/spectrum.rtlv_sg_swap.cdb and b/db/spectrum.rtlv_sg_swap.cdb differ diff --git a/db/spectrum.sgdiff.cdb b/db/spectrum.sgdiff.cdb index b821413..d96709b 100644 Binary files a/db/spectrum.sgdiff.cdb and b/db/spectrum.sgdiff.cdb differ diff --git a/db/spectrum.sgdiff.hdb b/db/spectrum.sgdiff.hdb index 82753ed..79a4646 100644 Binary files a/db/spectrum.sgdiff.hdb and b/db/spectrum.sgdiff.hdb differ diff --git a/db/spectrum.sta.qmsg b/db/spectrum.sta.qmsg index 36eb91b..7625903 100644 --- a/db/spectrum.sta.qmsg +++ b/db/spectrum.sta.qmsg @@ -1,42 +1,42 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648633118951 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648633118952 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 12:38:38 2022 " "Processing started: Wed Mar 30 12:38:38 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648633118952 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648633118952 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta spectrum -c spectrum " "Command: quartus_sta spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648633118952 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1648633118980 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648633119080 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648633119082 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648633119126 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648633119126 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "spectrum.sdc " "Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1648633119323 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1648633119324 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119325 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119325 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1648633119451 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119452 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1648633119452 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1648633119457 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648633119465 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648633119465 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.763 " "Worst-case setup slack is -2.763" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119466 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119466 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.763 -43.394 CLOCK_50 " " -2.763 -43.394 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119466 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648633119466 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.343 " "Worst-case hold slack is 0.343" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119466 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119466 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.343 0.000 CLOCK_50 " " 0.343 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119466 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648633119466 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648633119467 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648633119468 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119468 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119468 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -46.633 CLOCK_50 " " -3.000 -46.633 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119468 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648633119468 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648633119483 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1648633119506 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1648633119876 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119892 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648633119894 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648633119894 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.331 " "Worst-case setup slack is -2.331" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119895 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119895 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.331 -34.994 CLOCK_50 " " -2.331 -34.994 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119895 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648633119895 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.299 " "Worst-case hold slack is 0.299" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119896 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119896 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.299 0.000 CLOCK_50 " " 0.299 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119896 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648633119896 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648633119897 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648633119898 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119899 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119899 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -46.624 CLOCK_50 " " -3.000 -46.624 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119899 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648633119899 ""} -{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648633119916 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648633120038 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648633120038 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648633120038 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.122 " "Worst-case setup slack is -1.122" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633120040 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633120040 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.122 -9.363 CLOCK_50 " " -1.122 -9.363 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633120040 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648633120040 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.178 " "Worst-case hold slack is 0.178" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633120043 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633120043 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.178 0.000 CLOCK_50 " " 0.178 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633120043 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648633120043 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648633120045 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648633120047 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633120049 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633120049 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -45.480 CLOCK_50 " " -3.000 -45.480 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633120049 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648633120049 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648633120349 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648633120349 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "415 " "Peak virtual memory: 415 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648633120383 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 12:38:40 2022 " "Processing ended: Wed Mar 30 12:38:40 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648633120383 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648633120383 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648633120383 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648633120383 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648635144709 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648635144710 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 13:12:24 2022 " "Processing started: Wed Mar 30 13:12:24 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648635144710 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648635144710 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta spectrum -c spectrum " "Command: quartus_sta spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648635144711 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1648635144738 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648635144851 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648635144852 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648635144896 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648635144896 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "spectrum.sdc " "Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1648635145098 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1648635145098 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145099 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145099 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1648635145225 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145225 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1648635145226 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1648635145236 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648635145248 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648635145248 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.788 " "Worst-case setup slack is -1.788" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145249 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145249 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.788 -88.557 CLOCK_50 " " -1.788 -88.557 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145249 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648635145249 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.260 " "Worst-case hold slack is 0.260" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145250 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145250 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.260 0.000 CLOCK_50 " " 0.260 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145250 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648635145250 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648635145251 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648635145251 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145252 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145252 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -110.836 CLOCK_50 " " -3.000 -110.836 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145252 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648635145252 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648635145268 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1648635145291 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1648635145672 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145692 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648635145695 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648635145695 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.527 " "Worst-case setup slack is -1.527" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145696 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145696 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.527 -72.611 CLOCK_50 " " -1.527 -72.611 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145696 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648635145696 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.255 " "Worst-case hold slack is 0.255" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145698 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145698 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.255 0.000 CLOCK_50 " " 0.255 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145698 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648635145698 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648635145699 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648635145700 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145701 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145701 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -110.824 CLOCK_50 " " -3.000 -110.824 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145701 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648635145701 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648635145717 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145841 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648635145842 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648635145842 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.529 " "Worst-case setup slack is -0.529" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145843 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145843 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.529 -18.538 CLOCK_50 " " -0.529 -18.538 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145843 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648635145843 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.123 " "Worst-case hold slack is 0.123" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145845 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145845 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.123 0.000 CLOCK_50 " " 0.123 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145845 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648635145845 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648635145847 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648635145848 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145850 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145850 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -93.684 CLOCK_50 " " -3.000 -93.684 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648635145850 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648635145850 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648635146144 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648635146145 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "407 " "Peak virtual memory: 407 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648635146186 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 13:12:26 2022 " "Processing ended: Wed Mar 30 13:12:26 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648635146186 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648635146186 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648635146186 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648635146186 ""} diff --git a/db/spectrum.sta.rdb b/db/spectrum.sta.rdb index 85eafb1..b56815f 100644 Binary files a/db/spectrum.sta.rdb and b/db/spectrum.sta.rdb differ diff --git a/db/spectrum.sta_cmp.6_slow_1200mv_85c.tdb b/db/spectrum.sta_cmp.6_slow_1200mv_85c.tdb index a411007..4624648 100644 Binary files a/db/spectrum.sta_cmp.6_slow_1200mv_85c.tdb and b/db/spectrum.sta_cmp.6_slow_1200mv_85c.tdb differ diff --git a/db/spectrum.tiscmp.fast_1200mv_0c.ddb b/db/spectrum.tiscmp.fast_1200mv_0c.ddb index 9c4bf0a..f14c9a9 100644 Binary files a/db/spectrum.tiscmp.fast_1200mv_0c.ddb and b/db/spectrum.tiscmp.fast_1200mv_0c.ddb differ diff --git a/db/spectrum.tiscmp.slow_1200mv_0c.ddb b/db/spectrum.tiscmp.slow_1200mv_0c.ddb index d7eb207..2229f97 100644 Binary files a/db/spectrum.tiscmp.slow_1200mv_0c.ddb and b/db/spectrum.tiscmp.slow_1200mv_0c.ddb differ diff --git a/db/spectrum.tiscmp.slow_1200mv_85c.ddb b/db/spectrum.tiscmp.slow_1200mv_85c.ddb index 3035867..b3bdc65 100644 Binary files a/db/spectrum.tiscmp.slow_1200mv_85c.ddb and b/db/spectrum.tiscmp.slow_1200mv_85c.ddb differ diff --git a/db/spectrum.vpr.ammdb b/db/spectrum.vpr.ammdb index 06d6bfa..9078051 100644 Binary files a/db/spectrum.vpr.ammdb and b/db/spectrum.vpr.ammdb differ diff --git a/greybox_tmp/cbx_args.txt b/greybox_tmp/cbx_args.txt index d4ad6e2..43c0e8e 100644 --- a/greybox_tmp/cbx_args.txt +++ b/greybox_tmp/cbx_args.txt @@ -1,13 +1,13 @@ ADDRESS_ACLR_A=NONE CLOCK_ENABLE_INPUT_A=BYPASS CLOCK_ENABLE_OUTPUT_A=BYPASS -INIT_FILE=led_patterns.mif +INIT_FILE=./rom/gw03.hex INTENDED_DEVICE_FAMILY="Cyclone IV E" -NUMWORDS_A=8 +NUMWORDS_A=16384 OPERATION_MODE=ROM OUTDATA_ACLR_A=NONE OUTDATA_REG_A=CLOCK0 -WIDTHAD_A=3 +WIDTHAD_A=14 WIDTH_A=8 WIDTH_BYTEENA_A=1 DEVICE_FAMILY="Cyclone IV E" diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.ammdb b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.ammdb index 36f0f06..0895966 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.ammdb and b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.ammdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.cdb b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.cdb index b673015..0c493b6 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.cdb and b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.cdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.hdb b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.hdb index 49e2853..1f8f2be 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.hdb and b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.hdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.rcfdb b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.rcfdb index 9c58c40..1426ce6 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.rcfdb and b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.rcfdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.cdb b/incremental_db/compiled_partitions/spectrum.root_partition.map.cdb index e14e8a3..79c3fa4 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.map.cdb and b/incremental_db/compiled_partitions/spectrum.root_partition.map.cdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.dpi b/incremental_db/compiled_partitions/spectrum.root_partition.map.dpi index 2703abc..fafb254 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.map.dpi and b/incremental_db/compiled_partitions/spectrum.root_partition.map.dpi differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.cdb b/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.cdb index ecf5e6e..b9156de 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.cdb and b/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.cdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hdb b/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hdb index f3a40d7..bd583cd 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hdb and b/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.hdb b/incremental_db/compiled_partitions/spectrum.root_partition.map.hdb index 73492e1..de9ae64 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.map.hdb and b/incremental_db/compiled_partitions/spectrum.root_partition.map.hdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.kpt b/incremental_db/compiled_partitions/spectrum.root_partition.map.kpt index 461d6ec..ee77b94 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.map.kpt and b/incremental_db/compiled_partitions/spectrum.root_partition.map.kpt differ diff --git a/output_files/spectrum.asm.rpt b/output_files/spectrum.asm.rpt index bf2d0d1..df09700 100644 --- a/output_files/spectrum.asm.rpt +++ b/output_files/spectrum.asm.rpt @@ -1,5 +1,5 @@ Assembler report for spectrum -Wed Mar 30 12:38:37 2022 +Wed Mar 30 13:12:23 2022 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition @@ -37,7 +37,7 @@ applicable agreement for further details. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Wed Mar 30 12:38:37 2022 ; +; Assembler Status ; Successful - Wed Mar 30 13:12:23 2022 ; ; Revision Name ; spectrum ; ; Top-level Entity Name ; spectrum ; ; Family ; Cyclone IV E ; @@ -162,8 +162,8 @@ Default Value : On ; Option ; Setting ; +----------------+-----------------------+ ; Device ; EP4CE22F17C6 ; -; JTAG usercode ; 0x00139765 ; -; Checksum ; 0x00139765 ; +; JTAG usercode ; 0x00315633 ; +; Checksum ; 0x00315633 ; +----------------+-----------------------+ @@ -173,14 +173,14 @@ Default Value : On Info: ******************************************************************* Info: Running Quartus II 32-bit Assembler Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition - Info: Processing started: Wed Mar 30 12:38:36 2022 + Info: Processing started: Wed Mar 30 13:12:21 2022 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 393 megabytes - Info: Processing ended: Wed Mar 30 12:38:37 2022 - Info: Elapsed time: 00:00:01 + Info: Peak virtual memory: 385 megabytes + Info: Processing ended: Wed Mar 30 13:12:23 2022 + Info: Elapsed time: 00:00:02 Info: Total CPU time (on all processors): 00:00:01 diff --git a/output_files/spectrum.done b/output_files/spectrum.done index 49347a3..cdf40b2 100644 --- a/output_files/spectrum.done +++ b/output_files/spectrum.done @@ -1 +1 @@ -Wed Mar 30 12:38:42 2022 +Wed Mar 30 13:12:28 2022 diff --git a/output_files/spectrum.eda.rpt b/output_files/spectrum.eda.rpt index 55633f7..63ed9b7 100644 --- a/output_files/spectrum.eda.rpt +++ b/output_files/spectrum.eda.rpt @@ -1,5 +1,5 @@ EDA Netlist Writer report for spectrum -Wed Mar 30 12:38:42 2022 +Wed Mar 30 13:12:28 2022 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition @@ -36,7 +36,7 @@ applicable agreement for further details. +-------------------------------------------------------------------+ ; EDA Netlist Writer Summary ; +---------------------------+---------------------------------------+ -; EDA Netlist Writer Status ; Successful - Wed Mar 30 12:38:42 2022 ; +; EDA Netlist Writer Status ; Successful - Wed Mar 30 13:12:28 2022 ; ; Revision Name ; spectrum ; ; Top-level Entity Name ; spectrum ; ; Family ; Cyclone IV E ; @@ -88,7 +88,7 @@ applicable agreement for further details. Info: ******************************************************************* Info: Running Quartus II 32-bit EDA Netlist Writer Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition - Info: Processing started: Wed Mar 30 12:38:41 2022 + Info: Processing started: Wed Mar 30 13:12:27 2022 Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum Info (204019): Generated file spectrum_6_1200mv_85c_slow.vo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file spectrum_6_1200mv_0c_slow.vo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool @@ -99,8 +99,8 @@ Info (204019): Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder "/home/b Info (204019): Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file spectrum_v.sdo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool Info: Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 344 megabytes - Info: Processing ended: Wed Mar 30 12:38:42 2022 + Info: Peak virtual memory: 343 megabytes + Info: Processing ended: Wed Mar 30 13:12:28 2022 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 diff --git a/output_files/spectrum.fit.rpt b/output_files/spectrum.fit.rpt index febc4a2..d951405 100644 --- a/output_files/spectrum.fit.rpt +++ b/output_files/spectrum.fit.rpt @@ -1,5 +1,5 @@ Fitter report for spectrum -Wed Mar 30 12:38:34 2022 +Wed Mar 30 13:12:20 2022 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition @@ -30,7 +30,7 @@ Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition 22. Global & Other Fast Signals 23. Non-Global High Fan-Out Signals 24. Fitter RAM Summary - 25. |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ALTSYNCRAM + 25. |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM 26. Routing Usage Summary 27. LAB Logic Elements 28. LAB-wide Signals @@ -42,8 +42,10 @@ Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition 34. I/O Rules Matrix 35. Fitter Device Options 36. Operating Settings and Conditions - 37. Fitter Messages - 38. Fitter Suppressed Messages + 37. Estimated Delay Added for Hold Timing Summary + 38. Estimated Delay Added for Hold Timing Details + 39. Fitter Messages + 40. Fitter Suppressed Messages @@ -69,20 +71,20 @@ applicable agreement for further details. +---------------------------------------------------------------------------------+ ; Fitter Summary ; +------------------------------------+--------------------------------------------+ -; Fitter Status ; Successful - Wed Mar 30 12:38:34 2022 ; +; Fitter Status ; Successful - Wed Mar 30 13:12:20 2022 ; ; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ; ; Revision Name ; spectrum ; ; Top-level Entity Name ; spectrum ; ; Family ; Cyclone IV E ; ; Device ; EP4CE22F17C6 ; ; Timing Models ; Final ; -; Total logic elements ; 33 / 22,320 ( < 1 % ) ; -; Total combinational functions ; 33 / 22,320 ( < 1 % ) ; -; Dedicated logic registers ; 24 / 22,320 ( < 1 % ) ; -; Total registers ; 24 ; +; Total logic elements ; 55 / 22,320 ( < 1 % ) ; +; Total combinational functions ; 52 / 22,320 ( < 1 % ) ; +; Dedicated logic registers ; 38 / 22,320 ( < 1 % ) ; +; Total registers ; 38 ; ; Total pins ; 9 / 154 ( 6 % ) ; ; Total virtual pins ; 0 ; -; Total memory bits ; 64 / 608,256 ( < 1 % ) ; +; Total memory bits ; 131,072 / 608,256 ( 22 % ) ; ; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ; ; Total PLLs ; 0 / 4 ( 0 % ) ; +------------------------------------+--------------------------------------------+ @@ -2374,14 +2376,14 @@ From Design Partitions [A] : From Rapid Recompile [B] : Type : -- Requested -Total [A + B] : 0.00 % ( 0 / 95 ) -From Design Partitions [A] : 0.00 % ( 0 / 95 ) -From Rapid Recompile [B] : 0.00 % ( 0 / 95 ) +Total [A + B] : 0.00 % ( 0 / 136 ) +From Design Partitions [A] : 0.00 % ( 0 / 136 ) +From Rapid Recompile [B] : 0.00 % ( 0 / 136 ) Type : -- Achieved -Total [A + B] : 0.00 % ( 0 / 95 ) -From Design Partitions [A] : 0.00 % ( 0 / 95 ) -From Rapid Recompile [B] : 0.00 % ( 0 / 95 ) +Total [A + B] : 0.00 % ( 0 / 136 ) +From Design Partitions [A] : 0.00 % ( 0 / 136 ) +From Rapid Recompile [B] : 0.00 % ( 0 / 136 ) Type : Total [A + B] : @@ -2432,7 +2434,7 @@ Contents : hard_block:auto_generated_inst ; Incremental Compilation Placement Preservation ; +--------------------------------------------------------------------------------+ Partition Name : Top -Preservation Achieved : 0.00 % ( 0 / 85 ) +Preservation Achieved : 0.00 % ( 0 / 126 ) Preservation Level Used : N/A Netlist Type Used : Source File Preservation Method : N/A @@ -2454,54 +2456,54 @@ Notes : The pin-out file can be found in /home/benny/work/fpga/projects/output_files/spectrum.pin. -+-----------------------------------------------------------------------+ -; Fitter Resource Usage Summary ; -+---------------------------------------------+-------------------------+ -; Resource ; Usage ; -+---------------------------------------------+-------------------------+ -; Total logic elements ; 33 / 22,320 ( < 1 % ) ; -; -- Combinational with no register ; 9 ; -; -- Register only ; 0 ; -; -- Combinational with a register ; 24 ; -; ; ; -; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 10 ; -; -- 3 input functions ; 1 ; -; -- <=2 input functions ; 22 ; -; -- Register only ; 0 ; -; ; ; -; Logic elements by mode ; ; -; -- normal mode ; 13 ; -; -- arithmetic mode ; 20 ; -; ; ; -; Total registers* ; 24 / 23,018 ( < 1 % ) ; -; -- Dedicated logic registers ; 24 / 22,320 ( < 1 % ) ; -; -- I/O registers ; 0 / 698 ( 0 % ) ; -; ; ; -; Total LABs: partially or completely used ; 3 / 1,395 ( < 1 % ) ; -; Virtual pins ; 0 ; -; I/O pins ; 9 / 154 ( 6 % ) ; -; -- Clock pins ; 1 / 7 ( 14 % ) ; -; -- Dedicated input pins ; 0 / 9 ( 0 % ) ; -; ; ; -; Global signals ; 1 ; -; M9Ks ; 1 / 66 ( 2 % ) ; -; Total block memory bits ; 64 / 608,256 ( < 1 % ) ; -; Total block memory implementation bits ; 9,216 / 608,256 ( 2 % ) ; -; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ; -; PLLs ; 0 / 4 ( 0 % ) ; -; Global clocks ; 1 / 20 ( 5 % ) ; -; JTAGs ; 0 / 1 ( 0 % ) ; -; CRC blocks ; 0 / 1 ( 0 % ) ; -; ASMI blocks ; 0 / 1 ( 0 % ) ; -; Impedance control blocks ; 0 / 4 ( 0 % ) ; -; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ; -; Peak interconnect usage (total/H/V) ; 0% / 0% / 0% ; -; Maximum fan-out ; 25 ; -; Highest non-global fan-out ; 4 ; -; Total fan-out ; 161 ; -; Average fan-out ; 1.85 ; -+---------------------------------------------+-------------------------+ ++--------------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+----------------------------+ +; Resource ; Usage ; ++---------------------------------------------+----------------------------+ +; Total logic elements ; 55 / 22,320 ( < 1 % ) ; +; -- Combinational with no register ; 17 ; +; -- Register only ; 3 ; +; -- Combinational with a register ; 35 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 8 ; +; -- 3 input functions ; 10 ; +; -- <=2 input functions ; 34 ; +; -- Register only ; 3 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 20 ; +; -- arithmetic mode ; 32 ; +; ; ; +; Total registers* ; 38 / 23,018 ( < 1 % ) ; +; -- Dedicated logic registers ; 38 / 22,320 ( < 1 % ) ; +; -- I/O registers ; 0 / 698 ( 0 % ) ; +; ; ; +; Total LABs: partially or completely used ; 12 / 1,395 ( < 1 % ) ; +; Virtual pins ; 0 ; +; I/O pins ; 9 / 154 ( 6 % ) ; +; -- Clock pins ; 1 / 7 ( 14 % ) ; +; -- Dedicated input pins ; 0 / 9 ( 0 % ) ; +; ; ; +; Global signals ; 1 ; +; M9Ks ; 16 / 66 ( 24 % ) ; +; Total block memory bits ; 131,072 / 608,256 ( 22 % ) ; +; Total block memory implementation bits ; 147,456 / 608,256 ( 24 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ; +; PLLs ; 0 / 4 ( 0 % ) ; +; Global clocks ; 1 / 20 ( 5 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; ASMI blocks ; 0 / 1 ( 0 % ) ; +; Impedance control blocks ; 0 / 4 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ; +; Peak interconnect usage (total/H/V) ; 2% / 2% / 2% ; +; Maximum fan-out ; 54 ; +; Highest non-global fan-out ; 18 ; +; Total fan-out ; 482 ; +; Average fan-out ; 3.49 ; ++---------------------------------------------+----------------------------+ * Register count does not include registers inside RAM blocks or DSP blocks. @@ -2518,19 +2520,19 @@ Top : hard_block:auto_generated_inst : Statistic : Total logic elements -Top : 33 / 22320 ( < 1 % ) +Top : 55 / 22320 ( < 1 % ) hard_block:auto_generated_inst : 0 / 22320 ( 0 % ) Statistic : -- Combinational with no register -Top : 9 +Top : 17 hard_block:auto_generated_inst : 0 Statistic : -- Register only -Top : 0 +Top : 3 hard_block:auto_generated_inst : 0 Statistic : -- Combinational with a register -Top : 24 +Top : 35 hard_block:auto_generated_inst : 0 Statistic : @@ -2542,19 +2544,19 @@ Top : hard_block:auto_generated_inst : Statistic : -- 4 input functions -Top : 10 +Top : 8 hard_block:auto_generated_inst : 0 Statistic : -- 3 input functions -Top : 1 +Top : 10 hard_block:auto_generated_inst : 0 Statistic : -- <=2 input functions -Top : 22 +Top : 34 hard_block:auto_generated_inst : 0 Statistic : -- Register only -Top : 0 +Top : 3 hard_block:auto_generated_inst : 0 Statistic : @@ -2566,11 +2568,11 @@ Top : hard_block:auto_generated_inst : Statistic : -- normal mode -Top : 13 +Top : 20 hard_block:auto_generated_inst : 0 Statistic : -- arithmetic mode -Top : 20 +Top : 32 hard_block:auto_generated_inst : 0 Statistic : @@ -2578,11 +2580,11 @@ Top : hard_block:auto_generated_inst : Statistic : Total registers -Top : 24 +Top : 38 hard_block:auto_generated_inst : 0 Statistic : -- Dedicated logic registers -Top : 24 / 22320 ( < 1 % ) +Top : 38 / 22320 ( < 1 % ) hard_block:auto_generated_inst : 0 / 22320 ( 0 % ) Statistic : -- I/O registers @@ -2594,7 +2596,7 @@ Top : hard_block:auto_generated_inst : Statistic : Total LABs: partially or completely used -Top : 3 / 1395 ( < 1 % ) +Top : 12 / 1395 ( < 1 % ) hard_block:auto_generated_inst : 0 / 1395 ( 0 % ) Statistic : @@ -2614,15 +2616,15 @@ Top : 0 / 132 ( 0 % ) hard_block:auto_generated_inst : 0 / 132 ( 0 % ) Statistic : Total memory bits -Top : 64 +Top : 131072 hard_block:auto_generated_inst : 0 Statistic : Total RAM block bits -Top : 9216 +Top : 147456 hard_block:auto_generated_inst : 0 Statistic : M9K -Top : 1 / 66 ( 1 % ) +Top : 16 / 66 ( 24 % ) hard_block:auto_generated_inst : 0 / 66 ( 0 % ) Statistic : Clock control block @@ -2662,11 +2664,11 @@ Top : hard_block:auto_generated_inst : Statistic : -- Total Connections -Top : 156 +Top : 477 hard_block:auto_generated_inst : 5 Statistic : -- Registered Connections -Top : 38 +Top : 312 hard_block:auto_generated_inst : 0 Statistic : @@ -2773,7 +2775,7 @@ I/O Bank : 3 X coordinate : 27 Y coordinate : 0 Z coordinate : 21 -Combinational Fan-Out : 25 +Combinational Fan-Out : 54 Registered Fan-Out : 0 Global : yes Input Register : no @@ -6225,71 +6227,88 @@ Note: Pin directions (input, output or bidir) are based on device operating in u ; Fitter Resource Utilization by Entity ; +--------------------------------------------------------------------------------+ Compilation Hierarchy Node : |spectrum -Logic Cells : 33 (33) -Dedicated Logic Registers : 24 (24) +Logic Cells : 55 (45) +Dedicated Logic Registers : 38 (36) I/O Registers : 0 (0) -Memory Bits : 64 -M9Ks : 1 +Memory Bits : 131072 +M9Ks : 16 DSP Elements : 0 DSP 9x9 : 0 DSP 18x18 : 0 Pins : 9 Virtual Pins : 0 -LUT-Only LCs : 9 (9) -Register-Only LCs : 0 (0) -LUT/Register LCs : 24 (24) +LUT-Only LCs : 17 (9) +Register-Only LCs : 3 (1) +LUT/Register LCs : 35 (35) Full Hierarchy Name : |spectrum Library Name : work Compilation Hierarchy Node : |rom0:rom| -Logic Cells : 0 (0) -Dedicated Logic Registers : 0 (0) +Logic Cells : 10 (0) +Dedicated Logic Registers : 2 (0) I/O Registers : 0 (0) -Memory Bits : 64 -M9Ks : 1 +Memory Bits : 131072 +M9Ks : 16 DSP Elements : 0 DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 0 (0) -Register-Only LCs : 0 (0) +LUT-Only LCs : 8 (0) +Register-Only LCs : 2 (0) LUT/Register LCs : 0 (0) Full Hierarchy Name : |spectrum|rom0:rom Library Name : work Compilation Hierarchy Node : |altsyncram:altsyncram_component| -Logic Cells : 0 (0) -Dedicated Logic Registers : 0 (0) +Logic Cells : 10 (0) +Dedicated Logic Registers : 2 (0) I/O Registers : 0 (0) -Memory Bits : 64 -M9Ks : 1 +Memory Bits : 131072 +M9Ks : 16 DSP Elements : 0 DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 0 (0) -Register-Only LCs : 0 (0) +LUT-Only LCs : 8 (0) +Register-Only LCs : 2 (0) LUT/Register LCs : 0 (0) Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component Library Name : work -Compilation Hierarchy Node : |altsyncram_ro91:auto_generated| -Logic Cells : 0 (0) -Dedicated Logic Registers : 0 (0) +Compilation Hierarchy Node : |altsyncram_qh91:auto_generated| +Logic Cells : 10 (2) +Dedicated Logic Registers : 2 (2) I/O Registers : 0 (0) -Memory Bits : 64 -M9Ks : 1 +Memory Bits : 131072 +M9Ks : 16 DSP Elements : 0 DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -LUT-Only LCs : 0 (0) +LUT-Only LCs : 8 (0) +Register-Only LCs : 2 (2) +LUT/Register LCs : 0 (0) +Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated +Library Name : work + +Compilation Hierarchy Node : |mux_3nb:mux2| +Logic Cells : 8 (8) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 0 +M9Ks : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 8 (8) Register-Only LCs : 0 (0) LUT/Register LCs : 0 (0) -Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated +Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|mux_3nb:mux2 Library Name : work +--------------------------------------------------------------------------------+ @@ -6389,12 +6408,30 @@ Setting : +--------------------------------------------------------------------------------+ Name : CLOCK_50 Location : PIN_R8 -Fan-Out : 25 +Fan-Out : 54 Usage : Clock Global : yes Global Resource Used : Global Clock Global Line Name : GCLK18 Enable Signal Source Name : -- + +Name : Equal0~6 +Location : LCCOMB_X29_Y18_N26 +Fan-Out : 13 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- + +Name : address[13] +Location : FF_X29_Y18_N25 +Fan-Out : 18 +Usage : Clock enable +Global : no +Global Resource Used : -- +Global Line Name : -- +Enable Signal Source Name : -- +--------------------------------------------------------------------------------+ @@ -6404,7 +6441,7 @@ Enable Signal Source Name : -- +--------------------------------------------------------------------------------+ Name : CLOCK_50 Location : PIN_R8 -Fan-Out : 25 +Fan-Out : 54 Fan-Out Using Intentional Clock Skew : 3 Global Resource Used : Global Clock Global Line Name : GCLK18 @@ -6413,107 +6450,160 @@ Enable Signal Source Name : -- -+------------------------------------------------------------------------------------------+ -; Non-Global High Fan-Out Signals ; -+--------------------------------------------------------------------------------+---------+ -; Name ; Fan-Out ; -+--------------------------------------------------------------------------------+---------+ -; address[0] ; 4 ; -; Add0~40 ; 4 ; -; Equal0~4 ; 3 ; -; address[1] ; 3 ; -; Add0~38 ; 3 ; -; Add0~36 ; 3 ; -; Add0~34 ; 3 ; -; Add0~32 ; 3 ; -; Equal0~5 ; 2 ; -; address[2] ; 2 ; -; Add0~30 ; 2 ; -; Add0~28 ; 2 ; -; Add0~26 ; 2 ; -; Add0~24 ; 2 ; -; Add0~22 ; 2 ; -; Add0~20 ; 2 ; -; Add0~18 ; 2 ; -; Add0~16 ; 2 ; -; Add0~14 ; 2 ; -; Add0~12 ; 2 ; -; Add0~10 ; 2 ; -; Add0~8 ; 2 ; -; Add0~6 ; 2 ; -; Add0~4 ; 2 ; -; Add0~2 ; 2 ; -; Add0~0 ; 2 ; -; address[2]~3 ; 1 ; -; address[1]~2 ; 1 ; -; address[1]~1 ; 1 ; -; Equal0~7 ; 1 ; -; Equal0~6 ; 1 ; -; address[0]~0 ; 1 ; -; Equal0~3 ; 1 ; -; Equal0~2 ; 1 ; -; Equal0~1 ; 1 ; -; Equal0~0 ; 1 ; -; counter[0] ; 1 ; -; counter[1] ; 1 ; -; counter[2] ; 1 ; -; counter[3] ; 1 ; -; counter[4] ; 1 ; -; counter[5] ; 1 ; -; counter[6] ; 1 ; -; counter[7] ; 1 ; -; counter[8] ; 1 ; -; counter[9] ; 1 ; -; counter[10] ; 1 ; -; counter[11] ; 1 ; -; counter[12] ; 1 ; -; counter[13] ; 1 ; -; counter[14] ; 1 ; -; counter[15] ; 1 ; -; counter[16] ; 1 ; -; counter[17] ; 1 ; -; counter[18] ; 1 ; -; counter[19] ; 1 ; -; counter[20] ; 1 ; -; Add0~39 ; 1 ; -; Add0~37 ; 1 ; -; Add0~35 ; 1 ; -; Add0~33 ; 1 ; -; Add0~31 ; 1 ; -; Add0~29 ; 1 ; -; Add0~27 ; 1 ; -; Add0~25 ; 1 ; -; Add0~23 ; 1 ; -; Add0~21 ; 1 ; -; Add0~19 ; 1 ; -; Add0~17 ; 1 ; -; Add0~15 ; 1 ; -; Add0~13 ; 1 ; -; Add0~11 ; 1 ; -; Add0~9 ; 1 ; -; Add0~7 ; 1 ; -; Add0~5 ; 1 ; -; Add0~3 ; 1 ; -; Add0~1 ; 1 ; -; rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[1] ; 1 ; -; rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[2] ; 1 ; -; rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[3] ; 1 ; -; rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[4] ; 1 ; -; rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[5] ; 1 ; -; rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[6] ; 1 ; -; rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[7] ; 1 ; -; rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[0] ; 1 ; -+--------------------------------------------------------------------------------+---------+ ++-----------------------------------------------------------------------------------------------------------------+ +; Non-Global High Fan-Out Signals ; ++-------------------------------------------------------------------------------------------------------+---------+ +; Name ; Fan-Out ; ++-------------------------------------------------------------------------------------------------------+---------+ +; address[0] ; 18 ; +; address[13] ; 18 ; +; address[12] ; 17 ; +; address[11] ; 17 ; +; address[10] ; 17 ; +; address[9] ; 17 ; +; address[8] ; 17 ; +; address[7] ; 17 ; +; address[6] ; 17 ; +; address[5] ; 17 ; +; address[4] ; 17 ; +; address[3] ; 17 ; +; address[2] ; 17 ; +; address[1] ; 17 ; +; Equal0~6 ; 13 ; +; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|out_address_reg_a[0] ; 8 ; +; counter[0] ; 3 ; +; counter[21] ; 3 ; +; counter[20] ; 3 ; +; Equal0~5 ; 2 ; +; Equal0~4 ; 2 ; +; counter[19] ; 2 ; +; counter[18] ; 2 ; +; counter[17] ; 2 ; +; counter[16] ; 2 ; +; counter[15] ; 2 ; +; counter[14] ; 2 ; +; counter[13] ; 2 ; +; counter[12] ; 2 ; +; counter[11] ; 2 ; +; counter[10] ; 2 ; +; counter[9] ; 2 ; +; counter[8] ; 2 ; +; counter[7] ; 2 ; +; counter[6] ; 2 ; +; counter[5] ; 2 ; +; counter[4] ; 2 ; +; counter[3] ; 2 ; +; counter[2] ; 2 ; +; counter[1] ; 2 ; +; counter[0]~63 ; 1 ; +; address[0]~39 ; 1 ; +; Equal0~7 ; 1 ; +; Equal0~3 ; 1 ; +; Equal0~2 ; 1 ; +; Equal0~1 ; 1 ; +; Equal0~0 ; 1 ; +; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0] ; 1 ; +; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|mux_3nb:mux2|result_node[7]~7 ; 1 ; +; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|mux_3nb:mux2|result_node[6]~6 ; 1 ; +; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|mux_3nb:mux2|result_node[5]~5 ; 1 ; +; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|mux_3nb:mux2|result_node[4]~4 ; 1 ; +; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|mux_3nb:mux2|result_node[3]~3 ; 1 ; +; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|mux_3nb:mux2|result_node[2]~2 ; 1 ; +; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|mux_3nb:mux2|result_node[1]~1 ; 1 ; +; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|mux_3nb:mux2|result_node[0]~0 ; 1 ; +; counter[21]~61 ; 1 ; +; counter[20]~60 ; 1 ; +; counter[20]~59 ; 1 ; +; counter[19]~58 ; 1 ; +; counter[19]~57 ; 1 ; +; counter[18]~56 ; 1 ; +; counter[18]~55 ; 1 ; +; counter[17]~54 ; 1 ; +; counter[17]~53 ; 1 ; +; counter[16]~52 ; 1 ; +; counter[16]~51 ; 1 ; +; counter[15]~50 ; 1 ; +; counter[15]~49 ; 1 ; +; counter[14]~48 ; 1 ; +; counter[14]~47 ; 1 ; +; counter[13]~46 ; 1 ; +; counter[13]~45 ; 1 ; +; counter[12]~44 ; 1 ; +; counter[12]~43 ; 1 ; +; counter[11]~42 ; 1 ; +; counter[11]~41 ; 1 ; +; counter[10]~40 ; 1 ; +; counter[10]~39 ; 1 ; +; counter[9]~38 ; 1 ; +; counter[9]~37 ; 1 ; +; counter[8]~36 ; 1 ; +; counter[8]~35 ; 1 ; +; counter[7]~34 ; 1 ; +; counter[7]~33 ; 1 ; +; counter[6]~32 ; 1 ; +; counter[6]~31 ; 1 ; +; counter[5]~30 ; 1 ; +; counter[5]~29 ; 1 ; +; counter[4]~28 ; 1 ; +; counter[4]~27 ; 1 ; +; counter[3]~26 ; 1 ; +; counter[3]~25 ; 1 ; +; counter[2]~24 ; 1 ; +; counter[2]~23 ; 1 ; +; counter[1]~22 ; 1 ; +; counter[1]~21 ; 1 ; +; address[13]~37 ; 1 ; +; address[12]~36 ; 1 ; +; address[12]~35 ; 1 ; +; address[11]~34 ; 1 ; +; address[11]~33 ; 1 ; +; address[10]~32 ; 1 ; +; address[10]~31 ; 1 ; +; address[9]~30 ; 1 ; +; address[9]~29 ; 1 ; +; address[8]~28 ; 1 ; +; address[8]~27 ; 1 ; +; address[7]~26 ; 1 ; +; address[7]~25 ; 1 ; +; address[6]~24 ; 1 ; +; address[6]~23 ; 1 ; +; address[5]~22 ; 1 ; +; address[5]~21 ; 1 ; +; address[4]~20 ; 1 ; +; address[4]~19 ; 1 ; +; address[3]~18 ; 1 ; +; address[3]~17 ; 1 ; +; address[2]~16 ; 1 ; +; address[2]~15 ; 1 ; +; address[1]~14 ; 1 ; +; address[1]~13 ; 1 ; +; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 ; 1 ; +; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 ; 1 ; +; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 ; 1 ; +; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 ; 1 ; +; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 ; 1 ; +; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 ; 1 ; +; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 ; 1 ; +; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 ; 1 ; +; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 ; 1 ; +; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 ; 1 ; +; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 ; 1 ; +; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 ; 1 ; +; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 ; 1 ; +; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 ; 1 ; +; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 ; 1 ; +; rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 ; 1 ; ++-------------------------------------------------------------------------------------------------------+---------+ +--------------------------------------------------------------------------------+ ; Fitter RAM Summary ; +--------------------------------------------------------------------------------+ -Name : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ALTSYNCRAM +Name : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM Type : AUTO Mode : ROM Clock Mode : Single Clock -Port A Depth : 8 +Port A Depth : 16384 Port A Width : 8 Port B Depth : -- Port B Width : -- @@ -6521,15 +6611,15 @@ Port A Input Registers : yes Port A Output Registers : yes Port B Input Registers : -- Port B Output Registers : -- -Size : 64 -Implementation Port A Depth : 8 +Size : 131072 +Implementation Port A Depth : 16384 Implementation Port A Width : 8 Implementation Port B Depth : -- Implementation Port B Width : -- -Implementation Bits : 64 -M9Ks : 1 -MIF : led_patterns.mif -Location : M9K_X33_Y26_N0 +Implementation Bits : 131072 +M9Ks : 16 +MIF : ./rom/gw03.hex +Location : M9K_X33_Y13_N0, M9K_X33_Y14_N0, M9K_X22_Y16_N0, M9K_X22_Y19_N0, M9K_X33_Y15_N0, M9K_X33_Y12_N0, M9K_X33_Y17_N0, M9K_X33_Y18_N0, M9K_X22_Y17_N0, M9K_X22_Y18_N0, M9K_X22_Y15_N0, M9K_X22_Y13_N0, M9K_X33_Y16_N0, M9K_X33_Y19_N0, M9K_X22_Y12_N0, M9K_X22_Y14_N0 Mixed Width RDW Mode : Don't care Port A RDW Mode : Old data Port B RDW Mode : Old data @@ -6541,130 +6631,2187 @@ Note: Fitter may spread logical memories into multiple blocks to improve timing. RAM content values are presented in the following format: (Binary) (Octal) (Decimal) (Hexadecimal) +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ALTSYNCRAM ; +; |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM ; +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Addr ; +0 ; +1 ; +2 ; +3 ; +4 ; +5 ; +6 ; +7 ; +----------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+ -;0;(10000001) (201) (129) (81) ;(01000010) (102) (66) (42) ;(00100100) (44) (36) (24) ;(00011000) (30) (24) (18) ;(00011000) (30) (24) (18) ;(00100100) (44) (36) (24) ;(01000010) (102) (66) (42) ;(10000001) (201) (129) (81) ; +;0;(11110011) (363) (243) (F3) ;(10101111) (257) (175) (AF) ;(00010001) (21) (17) (11) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11000011) (303) (195) (C3) ;(11001011) (313) (203) (CB) ;(00010001) (21) (17) (11) ; +;8;(00101010) (52) (42) (2A) ;(01011101) (135) (93) (5D) ;(01011100) (134) (92) (5C) ;(00100010) (42) (34) (22) ;(01011111) (137) (95) (5F) ;(01011100) (134) (92) (5C) ;(00011000) (30) (24) (18) ;(01000011) (103) (67) (43) ; +;16;(11000011) (303) (195) (C3) ;(11110010) (362) (242) (F2) ;(00010101) (25) (21) (15) ;(10101111) (257) (175) (AF) ;(11000011) (303) (195) (C3) ;(00001010) (12) (10) (0A) ;(00001100) (14) (12) (0C) ;(00100000) (40) (32) (20) ; +;24;(00101010) (52) (42) (2A) ;(01011101) (135) (93) (5D) ;(01011100) (134) (92) (5C) ;(01111110) (176) (126) (7E) ;(11001101) (315) (205) (CD) ;(01111101) (175) (125) (7D) ;(00000000) (0) (0) (00) ;(11010000) (320) (208) (D0) ; +;32;(11001101) (315) (205) (CD) ;(01110100) (164) (116) (74) ;(00000000) (0) (0) (00) ;(00011000) (30) (24) (18) ;(11110111) (367) (247) (F7) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ;(11111111) (377) (255) (FF) ; +;40;(11000011) (303) (195) (C3) ;(01011011) (133) (91) (5B) ;(00110011) (63) (51) (33) ;(00111010) (72) (58) (3A) ;(00111000) (70) (56) (38) ;(01011100) (134) (92) (5C) ;(00001111) (17) (15) (0F) ;(11001001) (311) (201) (C9) ; +;48;(11000101) (305) (197) (C5) ;(00101010) (52) (42) (2A) ;(01100001) (141) (97) (61) ;(01011100) (134) (92) (5C) ;(11100101) (345) (229) (E5) ;(11000011) (303) (195) (C3) ;(10011110) (236) (158) (9E) ;(00010110) (26) (22) (16) ; +;56;(11110101) (365) (245) (F5) ;(11100101) (345) (229) (E5) ;(00101010) (52) (42) (2A) ;(01111000) (170) (120) (78) ;(01011100) (134) (92) (5C) ;(00100011) (43) (35) (23) ;(00100010) (42) (34) (22) ;(01111000) (170) (120) (78) ; +;64;(01011100) (134) (92) (5C) ;(01111100) (174) (124) (7C) ;(10110101) (265) (181) (B5) ;(00100000) (40) (32) (20) ;(00000011) (3) (3) (03) ;(11111101) (375) (253) (FD) ;(00110100) (64) (52) (34) ;(01000000) (100) (64) (40) ; +;72;(11000101) (305) (197) (C5) ;(11010101) (325) (213) (D5) ;(11001101) (315) (205) (CD) ;(10111111) (277) (191) (BF) ;(00000010) (2) (2) (02) ;(11010001) (321) (209) (D1) ;(11000001) (301) (193) (C1) ;(11100001) (341) (225) (E1) ; +;80;(11110001) (361) (241) (F1) ;(11111011) (373) (251) (FB) ;(11001001) (311) (201) (C9) ;(11100001) (341) (225) (E1) ;(01101110) (156) (110) (6E) ;(11111101) (375) (253) (FD) ;(01110101) (165) (117) (75) ;(00000000) (0) (0) (00) ; +;88;(11101101) (355) (237) (ED) ;(01111011) (173) (123) (7B) ;(00111101) (75) (61) (3D) ;(01011100) (134) (92) (5C) ;(11000011) (303) (195) (C3) ;(11000101) (305) (197) (C5) ;(00010110) (26) (22) (16) ;(11001101) (315) (205) (CD) ; +;96;(11010100) (324) (212) (D4) ;(00010110) (26) (22) (16) ;(11010010) (322) (210) (D2) ;(00011100) (34) (28) (1C) ;(00010010) (22) (18) (12) ;(11001001) (311) (201) (C9) ;(11110101) (365) (245) (F5) ;(11100101) (345) (229) (E5) ; +;104;(11001101) (315) (205) (CD) ;(01011111) (137) (95) (5F) ;(00000000) (0) (0) (00) ;(01111100) (174) (124) (7C) ;(10110101) (265) (181) (B5) ;(00101000) (50) (40) (28) ;(00000001) (1) (1) (01) ;(11101001) (351) (233) (E9) ; +;112;(11100001) (341) (225) (E1) ;(11110001) (361) (241) (F1) ;(11101101) (355) (237) (ED) ;(01000101) (105) (69) (45) ;(00101010) (52) (42) (2A) ;(01011101) (135) (93) (5D) ;(01011100) (134) (92) (5C) ;(00100011) (43) (35) (23) ; +;120;(00100010) (42) (34) (22) ;(01011101) (135) (93) (5D) ;(01011100) (134) (92) (5C) ;(01111110) (176) (126) (7E) ;(11001001) (311) (201) (C9) ;(11111110) (376) (254) (FE) ;(00100001) (41) (33) (21) ;(11010000) (320) (208) (D0) ; +;128;(11111110) (376) (254) (FE) ;(00001101) (15) (13) (0D) ;(11001000) (310) (200) (C8) ;(11111110) (376) (254) (FE) ;(00010000) (20) (16) (10) ;(11011000) (330) (216) (D8) ;(11111110) (376) (254) (FE) ;(00011000) (30) (24) (18) ; +;136;(00111111) (77) (63) (3F) ;(11011000) (330) (216) (D8) ;(00100011) (43) (35) (23) ;(11111110) (376) (254) (FE) ;(00010110) (26) (22) (16) ;(00111000) (70) (56) (38) ;(00000001) (1) (1) (01) ;(00100011) (43) (35) (23) ; +;144;(00110111) (67) (55) (37) ;(00100010) (42) (34) (22) ;(01011101) (135) (93) (5D) ;(01011100) (134) (92) (5C) ;(11001001) (311) (201) (C9) ;(10111111) (277) (191) (BF) ;(01010010) (122) (82) (52) ;(01001110) (116) (78) (4E) ; +;152;(11000100) (304) (196) (C4) ;(01001001) (111) (73) (49) ;(01001110) (116) (78) (4E) ;(01001011) (113) (75) (4B) ;(01000101) (105) (69) (45) ;(01011001) (131) (89) (59) ;(10100100) (244) (164) (A4) ;(01010000) (120) (80) (50) ; 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+;16120;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(11111111) (377) (255) (FF) ; +;16128;(00000000) (0) (0) (00) ;(00011100) (34) (28) (1C) ;(00100010) (42) (34) (22) ;(01111000) (170) (120) (78) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(01111110) (176) (126) (7E) ;(00000000) (0) (0) (00) ; +;16136;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00111000) (70) (56) (38) ;(00000100) (4) (4) (04) ;(00111100) (74) (60) (3C) ;(01000100) (104) (68) (44) ;(00111100) (74) (60) (3C) ;(00000000) (0) (0) (00) ; +;16144;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00111100) (74) (60) (3C) ;(00100010) (42) (34) (22) ;(00100010) (42) (34) (22) ;(00111100) (74) (60) (3C) ;(00000000) (0) (0) (00) ; +;16152;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00011100) (34) (28) (1C) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00011100) (34) (28) (1C) ;(00000000) (0) (0) (00) ; +;16160;(00000000) (0) (0) (00) ;(00000100) (4) (4) (04) ;(00000100) (4) (4) (04) ;(00111100) (74) (60) (3C) ;(01000100) (104) (68) (44) ;(01000100) (104) (68) (44) ;(00111100) (74) (60) (3C) ;(00000000) (0) (0) (00) ; +;16168;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00111000) (70) (56) (38) ;(01000100) (104) (68) (44) ;(01111000) (170) (120) (78) ;(01000000) (100) (64) (40) ;(00111100) (74) (60) (3C) ;(00000000) (0) (0) (00) ; +;16176;(00000000) (0) (0) (00) ;(00001100) (14) (12) (0C) ;(00010000) (20) (16) (10) ;(00011000) (30) (24) (18) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ; +;16184;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00111100) (74) (60) (3C) ;(01000100) (104) (68) (44) ;(01000100) (104) (68) (44) ;(00111100) (74) (60) (3C) ;(00000100) (4) (4) (04) ;(00111000) (70) (56) (38) ; +;16192;(00000000) (0) (0) (00) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ;(01111000) (170) (120) (78) ;(01000100) (104) (68) (44) ;(01000100) (104) (68) (44) ;(01000100) (104) (68) (44) ;(00000000) (0) (0) (00) ; +;16200;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ;(00110000) (60) (48) (30) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00111000) (70) (56) (38) ;(00000000) (0) (0) (00) ; +;16208;(00000000) (0) (0) (00) ;(00000100) (4) (4) (04) ;(00000000) (0) (0) (00) ;(00000100) (4) (4) (04) ;(00000100) (4) (4) (04) ;(00000100) (4) (4) (04) ;(00100100) (44) (36) (24) ;(00011000) (30) (24) (18) ; +;16216;(00000000) (0) (0) (00) ;(00100000) (40) (32) (20) ;(00101000) (50) (40) (28) ;(00110000) (60) (48) (30) ;(00110000) (60) (48) (30) ;(00101000) (50) (40) (28) ;(00100100) (44) (36) (24) ;(00000000) (0) (0) (00) ; +;16224;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00001100) (14) (12) (0C) ;(00000000) (0) (0) (00) ; +;16232;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01101000) (150) (104) (68) ;(01010100) (124) (84) (54) ;(01010100) (124) (84) (54) ;(01010100) (124) (84) (54) ;(01010100) (124) (84) (54) ;(00000000) (0) (0) (00) ; +;16240;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01111000) (170) (120) (78) ;(01000100) (104) (68) (44) ;(01000100) (104) (68) (44) ;(01000100) (104) (68) (44) ;(01000100) (104) (68) (44) ;(00000000) (0) (0) (00) ; +;16248;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00111000) (70) (56) (38) ;(01000100) (104) (68) (44) ;(01000100) (104) (68) (44) ;(01000100) (104) (68) (44) ;(00111000) (70) (56) (38) ;(00000000) (0) (0) (00) ; +;16256;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01111000) (170) (120) (78) ;(01000100) (104) (68) (44) ;(01000100) (104) (68) (44) ;(01111000) (170) (120) (78) ;(01000000) (100) (64) (40) ;(01000000) (100) (64) (40) ; +;16264;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00111100) (74) (60) (3C) ;(01000100) (104) (68) (44) ;(01000100) (104) (68) (44) ;(00111100) (74) (60) (3C) ;(00000100) (4) (4) (04) ;(00000110) (6) (6) (06) ; +;16272;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00011100) (34) (28) (1C) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00100000) (40) (32) (20) ;(00000000) (0) (0) (00) ; +;16280;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00111000) (70) (56) (38) ;(01000000) (100) (64) (40) ;(00111000) (70) (56) (38) ;(00000100) (4) (4) (04) ;(01111000) (170) (120) (78) ;(00000000) (0) (0) (00) ; +;16288;(00000000) (0) (0) (00) ;(00010000) (20) (16) (10) ;(00111000) (70) (56) (38) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(00001100) (14) (12) (0C) ;(00000000) (0) (0) (00) ; +;16296;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01000100) (104) (68) (44) ;(01000100) (104) (68) (44) ;(01000100) (104) (68) (44) ;(01000100) (104) (68) (44) ;(00111000) (70) (56) (38) ;(00000000) (0) (0) (00) ; +;16304;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01000100) (104) (68) (44) ;(01000100) (104) (68) (44) ;(00101000) (50) (40) (28) ;(00101000) (50) (40) (28) ;(00010000) (20) (16) (10) ;(00000000) (0) (0) (00) ; +;16312;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01000100) (104) (68) (44) ;(01010100) (124) (84) (54) ;(01010100) (124) (84) (54) ;(01010100) (124) (84) (54) ;(00101000) (50) (40) (28) ;(00000000) (0) (0) (00) ; +;16320;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01000100) (104) (68) (44) ;(00101000) (50) (40) (28) ;(00010000) (20) (16) (10) ;(00101000) (50) (40) (28) ;(01000100) (104) (68) (44) ;(00000000) (0) (0) (00) ; +;16328;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01000100) (104) (68) (44) ;(01000100) (104) (68) (44) ;(01000100) (104) (68) (44) ;(00111100) (74) (60) (3C) ;(00000100) (4) (4) (04) ;(00111000) (70) (56) (38) ; +;16336;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(01111100) (174) (124) (7C) ;(00001000) (10) (8) (08) ;(00010000) (20) (16) (10) ;(00100000) (40) (32) (20) ;(01111100) (174) (124) (7C) ;(00000000) (0) (0) (00) ; +;16344;(00000000) (0) (0) (00) ;(00001110) (16) (14) (0E) ;(00001000) (10) (8) (08) ;(00110000) (60) (48) (30) ;(00001000) (10) (8) (08) ;(00001000) (10) (8) (08) ;(00001110) (16) (14) (0E) ;(00000000) (0) (0) (00) ; +;16352;(00000000) (0) (0) (00) ;(00001000) (10) (8) (08) ;(00001000) (10) (8) (08) ;(00001000) (10) (8) (08) ;(00001000) (10) (8) (08) ;(00001000) (10) (8) (08) ;(00001000) (10) (8) (08) ;(00000000) (0) (0) (00) ; +;16360;(00000000) (0) (0) (00) ;(01110000) (160) (112) (70) ;(00010000) (20) (16) (10) ;(00001100) (14) (12) (0C) ;(00010000) (20) (16) (10) ;(00010000) (20) (16) (10) ;(01110000) (160) (112) (70) ;(00000000) (0) (0) (00) ; +;16368;(00000000) (0) (0) (00) ;(00010100) (24) (20) (14) ;(00101000) (50) (40) (28) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ;(00000000) (0) (0) (00) ; +;16376;(00111100) (74) (60) (3C) ;(01000010) (102) (66) (42) ;(10011001) (231) (153) (99) ;(10100001) (241) (161) (A1) ;(10100001) (241) (161) (A1) ;(10011001) (231) (153) (99) ;(01000010) (102) (66) (42) ;(00111100) (74) (60) (3C) ; -+-----------------------------------------------+ -; Routing Usage Summary ; -+-----------------------+-----------------------+ -; Routing Resource Type ; Usage ; -+-----------------------+-----------------------+ -; Block interconnects ; 42 / 71,559 ( < 1 % ) ; -; C16 interconnects ; 3 / 2,597 ( < 1 % ) ; -; C4 interconnects ; 20 / 46,848 ( < 1 % ) ; -; Direct links ; 24 / 71,559 ( < 1 % ) ; -; Global clocks ; 1 / 20 ( 5 % ) ; -; Local interconnects ; 24 / 24,624 ( < 1 % ) ; -; R24 interconnects ; 7 / 2,496 ( < 1 % ) ; -; R4 interconnects ; 27 / 62,424 ( < 1 % ) ; -+-----------------------+-----------------------+ ++------------------------------------------------+ +; Routing Usage Summary ; ++-----------------------+------------------------+ +; Routing Resource Type ; Usage ; ++-----------------------+------------------------+ +; Block interconnects ; 272 / 71,559 ( < 1 % ) ; +; C16 interconnects ; 4 / 2,597 ( < 1 % ) ; +; C4 interconnects ; 129 / 46,848 ( < 1 % ) ; +; Direct links ; 7 / 71,559 ( < 1 % ) ; +; Global clocks ; 1 / 20 ( 5 % ) ; +; Local interconnects ; 39 / 24,624 ( < 1 % ) ; +; R24 interconnects ; 8 / 2,496 ( < 1 % ) ; +; R4 interconnects ; 213 / 62,424 ( < 1 % ) ; ++-----------------------+------------------------+ +---------------------------------------------------------------------------+ ; LAB Logic Elements ; -+---------------------------------------------+-----------------------------+ -; Number of Logic Elements (Average = 11.00) ; Number of LABs (Total = 3) ; -+---------------------------------------------+-----------------------------+ -; 1 ; 0 ; -; 2 ; 0 ; -; 3 ; 0 ; -; 4 ; 0 ; -; 5 ; 0 ; -; 6 ; 1 ; -; 7 ; 0 ; -; 8 ; 0 ; -; 9 ; 0 ; -; 10 ; 0 ; -; 11 ; 0 ; -; 12 ; 1 ; -; 13 ; 0 ; -; 14 ; 0 ; -; 15 ; 1 ; -; 16 ; 0 ; -+---------------------------------------------+-----------------------------+ ++--------------------------------------------+------------------------------+ +; Number of Logic Elements (Average = 4.58) ; Number of LABs (Total = 12) ; ++--------------------------------------------+------------------------------+ +; 1 ; 8 ; +; 2 ; 1 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 1 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 2 ; ++--------------------------------------------+------------------------------+ -+------------------------------------------------------------------+ -; LAB-wide Signals ; -+------------------------------------+-----------------------------+ -; LAB-wide Signals (Average = 1.00) ; Number of LABs (Total = 3) ; -+------------------------------------+-----------------------------+ -; 1 Clock ; 3 ; -+------------------------------------+-----------------------------+ ++-------------------------------------------------------------------+ +; LAB-wide Signals ; ++------------------------------------+------------------------------+ +; LAB-wide Signals (Average = 0.33) ; Number of LABs (Total = 12) ; ++------------------------------------+------------------------------+ +; 1 Clock ; 4 ; ++------------------------------------+------------------------------+ +----------------------------------------------------------------------------+ ; LAB Signals Sourced ; -+----------------------------------------------+-----------------------------+ -; Number of Signals Sourced (Average = 19.00) ; Number of LABs (Total = 3) ; -+----------------------------------------------+-----------------------------+ -; 0 ; 0 ; -; 1 ; 0 ; -; 2 ; 0 ; -; 3 ; 0 ; -; 4 ; 0 ; -; 5 ; 0 ; -; 6 ; 0 ; -; 7 ; 0 ; -; 8 ; 0 ; -; 9 ; 1 ; -; 10 ; 0 ; -; 11 ; 0 ; -; 12 ; 0 ; -; 13 ; 0 ; -; 14 ; 0 ; -; 15 ; 0 ; -; 16 ; 0 ; -; 17 ; 0 ; -; 18 ; 0 ; -; 19 ; 0 ; -; 20 ; 0 ; -; 21 ; 0 ; -; 22 ; 1 ; -; 23 ; 0 ; -; 24 ; 0 ; -; 25 ; 0 ; -; 26 ; 1 ; -+----------------------------------------------+-----------------------------+ ++---------------------------------------------+------------------------------+ +; Number of Signals Sourced (Average = 7.75) ; Number of LABs (Total = 12) ; ++---------------------------------------------+------------------------------+ +; 0 ; 0 ; +; 1 ; 8 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 1 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 0 ; +; 17 ; 0 ; +; 18 ; 0 ; +; 19 ; 0 ; +; 20 ; 0 ; +; 21 ; 0 ; +; 22 ; 0 ; +; 23 ; 1 ; +; 24 ; 0 ; +; 25 ; 0 ; +; 26 ; 0 ; +; 27 ; 0 ; +; 28 ; 1 ; +; 29 ; 0 ; +; 30 ; 1 ; ++---------------------------------------------+------------------------------+ -+-------------------------------------------------------------------------------+ -; LAB Signals Sourced Out ; -+-------------------------------------------------+-----------------------------+ -; Number of Signals Sourced Out (Average = 4.33) ; Number of LABs (Total = 3) ; -+-------------------------------------------------+-----------------------------+ -; 0 ; 0 ; -; 1 ; 0 ; -; 2 ; 0 ; -; 3 ; 1 ; -; 4 ; 1 ; -; 5 ; 0 ; -; 6 ; 1 ; -+-------------------------------------------------+-----------------------------+ ++--------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+------------------------------+ +; Number of Signals Sourced Out (Average = 2.75) ; Number of LABs (Total = 12) ; ++-------------------------------------------------+------------------------------+ +; 0 ; 0 ; +; 1 ; 9 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 2 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 1 ; ++-------------------------------------------------+------------------------------+ -+---------------------------------------------------------------------------+ -; LAB Distinct Inputs ; -+---------------------------------------------+-----------------------------+ -; Number of Distinct Inputs (Average = 4.67) ; Number of LABs (Total = 3) ; -+---------------------------------------------+-----------------------------+ -; 0 ; 0 ; -; 1 ; 1 ; -; 2 ; 1 ; -; 3 ; 0 ; -; 4 ; 0 ; -; 5 ; 0 ; -; 6 ; 0 ; -; 7 ; 0 ; -; 8 ; 0 ; -; 9 ; 0 ; -; 10 ; 0 ; -; 11 ; 1 ; -+---------------------------------------------+-----------------------------+ ++----------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++---------------------------------------------+------------------------------+ +; Number of Distinct Inputs (Average = 3.50) ; Number of LABs (Total = 12) ; ++---------------------------------------------+------------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 1 ; +; 3 ; 9 ; +; 4 ; 1 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 1 ; ++---------------------------------------------+------------------------------+ +------------------------------------------+ @@ -7415,6 +9562,26 @@ IO_000042 : Inapplicable +---------------------------+--------+ ++--------------------------------------------------------------------------------+ +; Estimated Delay Added for Hold Timing Summary ; ++--------------------------------------------------------------------------------+ ++--------------------------------------------------------------------------------+ + +Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off. +This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer. + + ++--------------------------------------------------------------------------------+ +; Estimated Delay Added for Hold Timing Details ; ++--------------------------------------------------------------------------------+ +Source Register : address[0] +Destination Register : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 +Delay Added in ns : 0.035 ++--------------------------------------------------------------------------------+ + +Note: This table only shows the top 1 path(s) that have the largest delay added for hold. + + +-----------------+ ; Fitter Messages ; +-----------------+ @@ -7598,27 +9765,27 @@ Info (170189): Fitter placement preparation operations beginning Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful -Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 +Info (170192): Fitter placement operations ending: elapsed time is 00:00:01 Info (170193): Fitter routing operations beginning Info (170195): Router estimated average interconnect usage is 0% of the available device resources - Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X32_Y23 to location X42_Y34 + Info (170196): Router estimated peak interconnect usage is 2% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22 Info (170194): Fitter routing operations ending: elapsed time is 00:00:01 Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. Info (170201): Optimizations that may affect the design's routability were skipped -Info (11888): Total time spent on timing analysis during the Fitter is 0.16 seconds. +Info (11888): Total time spent on timing analysis during the Fitter is 0.22 seconds. Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully -Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01 +Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00 Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. Warning (169177): 1 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems. Info (169178): Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at R8 Info (144001): Generated suppressed messages file /home/benny/work/fpga/projects/output_files/spectrum.fit.smsg Info: Quartus II 32-bit Fitter was successful. 0 errors, 152 warnings - Info: Peak virtual memory: 600 megabytes - Info: Processing ended: Wed Mar 30 12:38:34 2022 - Info: Elapsed time: 00:00:05 + Info: Peak virtual memory: 595 megabytes + Info: Processing ended: Wed Mar 30 13:12:20 2022 + Info: Elapsed time: 00:00:06 Info: Total CPU time (on all processors): 00:00:06 diff --git a/output_files/spectrum.fit.summary b/output_files/spectrum.fit.summary index dbfec8e..a90c61d 100644 --- a/output_files/spectrum.fit.summary +++ b/output_files/spectrum.fit.summary @@ -1,16 +1,16 @@ -Fitter Status : Successful - Wed Mar 30 12:38:34 2022 +Fitter Status : Successful - Wed Mar 30 13:12:20 2022 Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition Revision Name : spectrum Top-level Entity Name : spectrum Family : Cyclone IV E Device : EP4CE22F17C6 Timing Models : Final -Total logic elements : 33 / 22,320 ( < 1 % ) - Total combinational functions : 33 / 22,320 ( < 1 % ) - Dedicated logic registers : 24 / 22,320 ( < 1 % ) -Total registers : 24 +Total logic elements : 55 / 22,320 ( < 1 % ) + Total combinational functions : 52 / 22,320 ( < 1 % ) + Dedicated logic registers : 38 / 22,320 ( < 1 % ) +Total registers : 38 Total pins : 9 / 154 ( 6 % ) Total virtual pins : 0 -Total memory bits : 64 / 608,256 ( < 1 % ) +Total memory bits : 131,072 / 608,256 ( 22 % ) Embedded Multiplier 9-bit elements : 0 / 132 ( 0 % ) Total PLLs : 0 / 4 ( 0 % ) diff --git a/output_files/spectrum.flow.rpt b/output_files/spectrum.flow.rpt index c3a2fdd..5937fc4 100644 --- a/output_files/spectrum.flow.rpt +++ b/output_files/spectrum.flow.rpt @@ -1,5 +1,5 @@ Flow report for spectrum -Wed Mar 30 12:38:42 2022 +Wed Mar 30 13:12:28 2022 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition @@ -40,20 +40,20 @@ applicable agreement for further details. +---------------------------------------------------------------------------------+ ; Flow Summary ; +------------------------------------+--------------------------------------------+ -; Flow Status ; Successful - Wed Mar 30 12:38:42 2022 ; +; Flow Status ; Successful - Wed Mar 30 13:12:28 2022 ; ; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ; ; Revision Name ; spectrum ; ; Top-level Entity Name ; spectrum ; ; Family ; Cyclone IV E ; ; Device ; EP4CE22F17C6 ; ; Timing Models ; Final ; -; Total logic elements ; 33 / 22,320 ( < 1 % ) ; -; Total combinational functions ; 33 / 22,320 ( < 1 % ) ; -; Dedicated logic registers ; 24 / 22,320 ( < 1 % ) ; -; Total registers ; 24 ; +; Total logic elements ; 55 / 22,320 ( < 1 % ) ; +; Total combinational functions ; 52 / 22,320 ( < 1 % ) ; +; Dedicated logic registers ; 38 / 22,320 ( < 1 % ) ; +; Total registers ; 38 ; ; Total pins ; 9 / 154 ( 6 % ) ; ; Total virtual pins ; 0 ; -; Total memory bits ; 64 / 608,256 ( < 1 % ) ; +; Total memory bits ; 131,072 / 608,256 ( 22 % ) ; ; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ; ; Total PLLs ; 0 / 4 ( 0 % ) ; +------------------------------------+--------------------------------------------+ @@ -64,7 +64,7 @@ applicable agreement for further details. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 03/30/2022 12:38:27 ; +; Start date & time ; 03/30/2022 13:12:12 ; ; Main task ; Compilation ; ; Revision Name ; spectrum ; +-------------------+---------------------+ @@ -74,7 +74,7 @@ applicable agreement for further details. ; Flow Non-Default Global Settings ; +--------------------------------------------------------------------------------+ Assignment Name : COMPILER_SIGNATURE_ID -Value : 0.164863310720961 +Value : 0.164863513225804 Default Value : -- Entity Name : -- Section Id : -- @@ -160,35 +160,35 @@ Section Id : -- Module Name : Analysis & Synthesis Elapsed Time : 00:00:02 Average Processors Used : 1.0 -Peak Virtual Memory : 373 MB +Peak Virtual Memory : 381 MB Total CPU Time (on all processors) : 00:00:01 Module Name : Fitter -Elapsed Time : 00:00:05 +Elapsed Time : 00:00:06 Average Processors Used : 1.0 -Peak Virtual Memory : 600 MB +Peak Virtual Memory : 595 MB Total CPU Time (on all processors) : 00:00:06 Module Name : Assembler -Elapsed Time : 00:00:01 +Elapsed Time : 00:00:02 Average Processors Used : 1.0 -Peak Virtual Memory : 393 MB +Peak Virtual Memory : 385 MB Total CPU Time (on all processors) : 00:00:01 Module Name : TimeQuest Timing Analyzer Elapsed Time : 00:00:02 Average Processors Used : 1.0 -Peak Virtual Memory : 415 MB +Peak Virtual Memory : 407 MB Total CPU Time (on all processors) : 00:00:02 Module Name : EDA Netlist Writer Elapsed Time : 00:00:01 Average Processors Used : 1.0 -Peak Virtual Memory : 332 MB +Peak Virtual Memory : 331 MB Total CPU Time (on all processors) : 00:00:01 Module Name : Total -Elapsed Time : 00:00:11 +Elapsed Time : 00:00:13 Average Processors Used : -- Peak Virtual Memory : -- Total CPU Time (on all processors) : 00:00:11 diff --git a/output_files/spectrum.jdi b/output_files/spectrum.jdi index ade2713..29a146b 100644 --- a/output_files/spectrum.jdi +++ b/output_files/spectrum.jdi @@ -1,6 +1,6 @@ - + diff --git a/output_files/spectrum.map.rpt b/output_files/spectrum.map.rpt index 12cac49..c1ced8f 100644 --- a/output_files/spectrum.map.rpt +++ b/output_files/spectrum.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for spectrum -Wed Mar 30 12:38:28 2022 +Wed Mar 30 13:12:13 2022 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition @@ -16,7 +16,7 @@ Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition 8. Analysis & Synthesis RAM Summary 9. Analysis & Synthesis IP Cores Summary 10. General Register Statistics - 11. Source assignments for rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated + 11. Source assignments for rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated 12. Parameter Settings for User Entity Instance: rom0:rom|altsyncram:altsyncram_component 13. altsyncram Parameter Settings by Entity Instance 14. Elapsed Time Per Partition @@ -46,18 +46,18 @@ applicable agreement for further details. +---------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +------------------------------------+--------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Wed Mar 30 12:38:28 2022 ; +; Analysis & Synthesis Status ; Successful - Wed Mar 30 13:12:13 2022 ; ; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ; ; Revision Name ; spectrum ; ; Top-level Entity Name ; spectrum ; ; Family ; Cyclone IV E ; -; Total logic elements ; 33 ; -; Total combinational functions ; 33 ; -; Dedicated logic registers ; 24 ; -; Total registers ; 24 ; +; Total logic elements ; 54 ; +; Total combinational functions ; 52 ; +; Dedicated logic registers ; 38 ; +; Total registers ; 38 ; ; Total pins ; 9 ; ; Total virtual pins ; 0 ; -; Total memory bits ; 64 ; +; Total memory bits ; 131,072 ; ; Embedded Multiplier 9-bit elements ; 0 ; ; Total PLLs ; 0 ; +------------------------------------+--------------------------------------------+ @@ -405,12 +405,6 @@ File Type : User Verilog HDL File File Name with Absolute Path : /home/benny/work/fpga/projects/spectrum.v Library : -File Name with User-Entered Path : led_patterns.mif -Used in Netlist : yes -File Type : User Memory Initialization File -File Name with Absolute Path : /home/benny/work/fpga/projects/led_patterns.mif -Library : - File Name with User-Entered Path : rom0.v Used in Netlist : yes File Type : User Wizard-Generated File @@ -471,10 +465,28 @@ File Type : Megafunction File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/altdpram.inc Library : -File Name with User-Entered Path : db/altsyncram_ro91.tdf +File Name with User-Entered Path : db/altsyncram_qh91.tdf Used in Netlist : yes File Type : Auto-Generated Megafunction -File Name with Absolute Path : /home/benny/work/fpga/projects/db/altsyncram_ro91.tdf +File Name with Absolute Path : /home/benny/work/fpga/projects/db/altsyncram_qh91.tdf +Library : + +File Name with User-Entered Path : rom/gw03.hex +Used in Netlist : yes +File Type : Auto-Found Memory Initialization File +File Name with Absolute Path : /home/benny/work/fpga/projects/rom/gw03.hex +Library : + +File Name with User-Entered Path : db/decode_c8a.tdf +Used in Netlist : yes +File Type : Auto-Generated Megafunction +File Name with Absolute Path : /home/benny/work/fpga/projects/db/decode_c8a.tdf +Library : + +File Name with User-Entered Path : db/mux_3nb.tdf +Used in Netlist : yes +File Type : Auto-Generated Megafunction +File Name with Absolute Path : /home/benny/work/fpga/projects/db/mux_3nb.tdf Library : +--------------------------------------------------------------------------------+ @@ -485,29 +497,29 @@ Library : +---------------------------------------------+----------------+ ; Resource ; Usage ; +---------------------------------------------+----------------+ -; Estimated Total logic elements ; 33 ; +; Estimated Total logic elements ; 54 ; ; ; ; -; Total combinational functions ; 33 ; +; Total combinational functions ; 52 ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 10 ; -; -- 3 input functions ; 1 ; -; -- <=2 input functions ; 22 ; +; -- 4 input functions ; 8 ; +; -- 3 input functions ; 10 ; +; -- <=2 input functions ; 34 ; ; ; ; ; Logic elements by mode ; ; -; -- normal mode ; 13 ; -; -- arithmetic mode ; 20 ; +; -- normal mode ; 20 ; +; -- arithmetic mode ; 32 ; ; ; ; -; Total registers ; 24 ; -; -- Dedicated logic registers ; 24 ; +; Total registers ; 38 ; +; -- Dedicated logic registers ; 38 ; ; -- I/O registers ; 0 ; ; ; ; ; I/O pins ; 9 ; -; Total memory bits ; 64 ; +; Total memory bits ; 131072 ; ; Embedded Multiplier 9-bit elements ; 0 ; ; Maximum fan-out node ; CLOCK_50~input ; -; Maximum fan-out ; 32 ; -; Total fan-out ; 183 ; -; Average fan-out ; 2.20 ; +; Maximum fan-out ; 54 ; +; Total fan-out ; 473 ; +; Average fan-out ; 3.81 ; +---------------------------------------------+----------------+ @@ -515,9 +527,9 @@ Library : ; Analysis & Synthesis Resource Utilization by Entity ; +--------------------------------------------------------------------------------+ Compilation Hierarchy Node : |spectrum -LC Combinationals : 33 (33) -LC Registers : 24 (24) -Memory Bits : 64 +LC Combinationals : 52 (44) +LC Registers : 38 (36) +Memory Bits : 131072 DSP Elements : 0 DSP 9x9 : 0 DSP 18x18 : 0 @@ -527,9 +539,9 @@ Full Hierarchy Name : |spectrum Library Name : work Compilation Hierarchy Node : |rom0:rom| -LC Combinationals : 0 (0) -LC Registers : 0 (0) -Memory Bits : 64 +LC Combinationals : 8 (0) +LC Registers : 2 (0) +Memory Bits : 131072 DSP Elements : 0 DSP 9x9 : 0 DSP 18x18 : 0 @@ -539,9 +551,9 @@ Full Hierarchy Name : |spectrum|rom0:rom Library Name : work Compilation Hierarchy Node : |altsyncram:altsyncram_component| -LC Combinationals : 0 (0) -LC Registers : 0 (0) -Memory Bits : 64 +LC Combinationals : 8 (0) +LC Registers : 2 (0) +Memory Bits : 131072 DSP Elements : 0 DSP 9x9 : 0 DSP 18x18 : 0 @@ -550,16 +562,28 @@ Virtual Pins : 0 Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component Library Name : work -Compilation Hierarchy Node : |altsyncram_ro91:auto_generated| -LC Combinationals : 0 (0) -LC Registers : 0 (0) -Memory Bits : 64 +Compilation Hierarchy Node : |altsyncram_qh91:auto_generated| +LC Combinationals : 8 (0) +LC Registers : 2 (2) +Memory Bits : 131072 DSP Elements : 0 DSP 9x9 : 0 DSP 18x18 : 0 Pins : 0 Virtual Pins : 0 -Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated +Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated +Library Name : work + +Compilation Hierarchy Node : |mux_3nb:mux2| +LC Combinationals : 8 (8) +LC Registers : 0 (0) +Memory Bits : 0 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|mux_3nb:mux2 Library Name : work +--------------------------------------------------------------------------------+ @@ -569,15 +593,15 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +--------------------------------------------------------------------------------+ ; Analysis & Synthesis RAM Summary ; +--------------------------------------------------------------------------------+ -Name : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ALTSYNCRAM +Name : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM Type : AUTO Mode : ROM -Port A Depth : 8 +Port A Depth : 16384 Port A Width : 8 Port B Depth : -- Port B Width : -- -Size : 64 -MIF : led_patterns.mif +Size : 131072 +MIF : ./rom/gw03.hex +--------------------------------------------------------------------------------+ @@ -601,18 +625,18 @@ IP Include File : /home/benny/work/fpga/projects/rom0.v +----------------------------------------------+-------+ ; Statistic ; Value ; +----------------------------------------------+-------+ -; Total registers ; 24 ; +; Total registers ; 38 ; ; Number of registers using Synchronous Clear ; 0 ; ; Number of registers using Synchronous Load ; 0 ; ; Number of registers using Asynchronous Clear ; 0 ; ; Number of registers using Asynchronous Load ; 0 ; -; Number of registers using Clock Enable ; 0 ; +; Number of registers using Clock Enable ; 13 ; ; Number of registers using Preset ; 0 ; +----------------------------------------------+-------+ +--------------------------------------------------------------------------------+ -; Source assignments for rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated ; +; Source assignments for rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated ; +--------------------------------------------------------------------------------+ Assignment : OPTIMIZE_POWER_DURING_SYNTHESIS Value : NORMAL_COMPILATION @@ -658,11 +682,11 @@ Value : 8 Type : Signed Integer Parameter Name : WIDTHAD_A -Value : 3 +Value : 14 Type : Signed Integer Parameter Name : NUMWORDS_A -Value : 8 +Value : 16384 Type : Signed Integer Parameter Name : OUTDATA_REG_A @@ -778,7 +802,7 @@ Value : NEW_DATA_NO_NBE_READ Type : Untyped Parameter Name : INIT_FILE -Value : led_patterns.mif +Value : ./rom/gw03.hex Type : Untyped Parameter Name : INIT_FILE_LAYOUT @@ -830,7 +854,7 @@ Value : Cyclone IV E Type : Untyped Parameter Name : CBXI_PARAMETER -Value : altsyncram_ro91 +Value : altsyncram_qh91 Type : Untyped +--------------------------------------------------------------------------------+ @@ -846,7 +870,7 @@ Note: In order to hide this table in the UI and the text report file, please set ; Entity Instance ; rom0:rom|altsyncram:altsyncram_component ; ; -- OPERATION_MODE ; ROM ; ; -- WIDTH_A ; 8 ; -; -- NUMWORDS_A ; 8 ; +; -- NUMWORDS_A ; 16384 ; ; -- OUTDATA_REG_A ; CLOCK0 ; ; -- WIDTH_B ; 1 ; ; -- NUMWORDS_B ; 1 ; @@ -872,7 +896,7 @@ Note: In order to hide this table in the UI and the text report file, please set Info: ******************************************************************* Info: Running Quartus II 32-bit Analysis & Synthesis Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition - Info: Processing started: Wed Mar 30 12:38:26 2022 + Info: Processing started: Wed Mar 30 13:12:11 2022 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum Warning (20028): Parallel compilation is not licensed and has been disabled Info (12021): Found 1 design units, including 1 entities, in source file spectrum.v @@ -880,8 +904,8 @@ Info (12021): Found 1 design units, including 1 entities, in source file spectru Info (12021): Found 1 design units, including 1 entities, in source file rom0.v Info (12023): Found entity 1: rom0 Info (12127): Elaborating entity "spectrum" for the top level hierarchy -Warning (10230): Verilog HDL assignment warning at spectrum.v(19): truncated value with size 32 to match size of target (21) -Warning (10230): Verilog HDL assignment warning at spectrum.v(21): truncated value with size 32 to match size of target (3) +Warning (10230): Verilog HDL assignment warning at spectrum.v(18): truncated value with size 32 to match size of target (22) +Warning (10230): Verilog HDL assignment warning at spectrum.v(20): truncated value with size 32 to match size of target (14) Info (12128): Elaborating entity "rom0" for hierarchy "rom0:rom" Info (12128): Elaborating entity "altsyncram" for hierarchy "rom0:rom|altsyncram:altsyncram_component" Info (12130): Elaborated megafunction instantiation "rom0:rom|altsyncram:altsyncram_component" @@ -889,32 +913,38 @@ Info (12133): Instantiated megafunction "rom0:rom|altsyncram:altsyncram_componen Info (12134): Parameter "address_aclr_a" = "NONE" Info (12134): Parameter "clock_enable_input_a" = "BYPASS" Info (12134): Parameter "clock_enable_output_a" = "BYPASS" - Info (12134): Parameter "init_file" = "led_patterns.mif" + Info (12134): Parameter "init_file" = "./rom/gw03.hex" Info (12134): Parameter "intended_device_family" = "Cyclone IV E" Info (12134): Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO" Info (12134): Parameter "lpm_type" = "altsyncram" - Info (12134): Parameter "numwords_a" = "8" + Info (12134): Parameter "numwords_a" = "16384" Info (12134): Parameter "operation_mode" = "ROM" Info (12134): Parameter "outdata_aclr_a" = "NONE" Info (12134): Parameter "outdata_reg_a" = "CLOCK0" - Info (12134): Parameter "widthad_a" = "3" + Info (12134): Parameter "widthad_a" = "14" Info (12134): Parameter "width_a" = "8" Info (12134): Parameter "width_byteena_a" = "1" -Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_ro91.tdf - Info (12023): Found entity 1: altsyncram_ro91 -Info (12128): Elaborating entity "altsyncram_ro91" for hierarchy "rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated" +Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_qh91.tdf + Info (12023): Found entity 1: altsyncram_qh91 +Info (12128): Elaborating entity "altsyncram_qh91" for hierarchy "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated" +Info (12021): Found 1 design units, including 1 entities, in source file db/decode_c8a.tdf + Info (12023): Found entity 1: decode_c8a +Info (12128): Elaborating entity "decode_c8a" for hierarchy "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|decode_c8a:rden_decode" +Info (12021): Found 1 design units, including 1 entities, in source file db/mux_3nb.tdf + Info (12023): Found entity 1: mux_3nb +Info (12128): Elaborating entity "mux_3nb" for hierarchy "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|mux_3nb:mux2" Info (286030): Timing-Driven Synthesis is running Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL -Info (21057): Implemented 71 device resources after synthesis - the final resource count might be different +Info (21057): Implemented 79 device resources after synthesis - the final resource count might be different Info (21058): Implemented 1 input pins Info (21059): Implemented 8 output pins Info (21061): Implemented 54 logic cells - Info (21064): Implemented 8 RAM segments + Info (21064): Implemented 16 RAM segments Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 3 warnings - Info: Peak virtual memory: 384 megabytes - Info: Processing ended: Wed Mar 30 12:38:28 2022 + Info: Peak virtual memory: 392 megabytes + Info: Processing ended: Wed Mar 30 13:12:13 2022 Info: Elapsed time: 00:00:02 - Info: Total CPU time (on all processors): 00:00:01 + Info: Total CPU time (on all processors): 00:00:02 diff --git a/output_files/spectrum.map.summary b/output_files/spectrum.map.summary index 5783484..3445a44 100644 --- a/output_files/spectrum.map.summary +++ b/output_files/spectrum.map.summary @@ -1,14 +1,14 @@ -Analysis & Synthesis Status : Successful - Wed Mar 30 12:38:28 2022 +Analysis & Synthesis Status : Successful - Wed Mar 30 13:12:13 2022 Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition Revision Name : spectrum Top-level Entity Name : spectrum Family : Cyclone IV E -Total logic elements : 33 - Total combinational functions : 33 - Dedicated logic registers : 24 -Total registers : 24 +Total logic elements : 54 + Total combinational functions : 52 + Dedicated logic registers : 38 +Total registers : 38 Total pins : 9 Total virtual pins : 0 -Total memory bits : 64 +Total memory bits : 131,072 Embedded Multiplier 9-bit elements : 0 Total PLLs : 0 diff --git a/output_files/spectrum.sof b/output_files/spectrum.sof index 63061a7..442db49 100644 Binary files a/output_files/spectrum.sof and b/output_files/spectrum.sof differ diff --git a/output_files/spectrum.sta.rpt b/output_files/spectrum.sta.rpt index 11debb1..511d49e 100644 --- a/output_files/spectrum.sta.rpt +++ b/output_files/spectrum.sta.rpt @@ -1,5 +1,5 @@ TimeQuest Timing Analyzer report for spectrum -Wed Mar 30 12:38:40 2022 +Wed Mar 30 13:12:26 2022 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition @@ -133,7 +133,7 @@ Targets : { CLOCK_50 } +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Fmax Summary ; +--------------------------------------------------------------------------------+ -Fmax : 265.75 MHz +Fmax : 358.68 MHz Restricted Fmax : 250.0 MHz Clock Name : CLOCK_50 Note : limit due to minimum period restriction (max I/O toggle rate) @@ -152,8 +152,8 @@ HTML report is unavailable in plain text report export. ; Slow 1200mV 85C Model Setup Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 -Slack : -2.763 -End Point TNS : -43.394 +Slack : -1.788 +End Point TNS : -88.557 +--------------------------------------------------------------------------------+ @@ -162,7 +162,7 @@ End Point TNS : -43.394 ; Slow 1200mV 85C Model Hold Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 -Slack : 0.343 +Slack : 0.260 End Point TNS : 0.000 +--------------------------------------------------------------------------------+ @@ -185,7 +185,7 @@ No paths to report. +--------------------------------------------------------------------------------+ Clock : CLOCK_50 Slack : -3.000 -End Point TNS : -46.633 +End Point TNS : -110.836 +--------------------------------------------------------------------------------+ @@ -193,905 +193,905 @@ End Point TNS : -46.633 +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Setup: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ -Slack : -2.763 -From Node : counter[1] -To Node : address[2] +Slack : -1.788 +From Node : counter[14] +To Node : address[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 4.047 +Clock Skew : -0.063 +Data Delay : 2.720 -Slack : -2.682 -From Node : counter[0] -To Node : address[2] +Slack : -1.788 +From Node : counter[14] +To Node : address[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.966 +Clock Skew : -0.063 +Data Delay : 2.720 -Slack : -2.665 -From Node : counter[1] -To Node : address[1] +Slack : -1.788 +From Node : counter[14] +To Node : address[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.949 +Clock Skew : -0.063 +Data Delay : 2.720 -Slack : -2.659 -From Node : counter[5] -To Node : address[2] +Slack : -1.788 +From Node : counter[14] +To Node : address[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.943 +Clock Skew : -0.063 +Data Delay : 2.720 -Slack : -2.647 -From Node : counter[3] -To Node : address[2] +Slack : -1.788 +From Node : counter[14] +To Node : address[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.931 +Clock Skew : -0.063 +Data Delay : 2.720 -Slack : -2.584 -From Node : counter[0] -To Node : address[1] +Slack : -1.788 +From Node : counter[14] +To Node : address[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.868 +Clock Skew : -0.063 +Data Delay : 2.720 -Slack : -2.578 -From Node : counter[4] -To Node : address[2] +Slack : -1.788 +From Node : counter[14] +To Node : address[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.862 +Clock Skew : -0.063 +Data Delay : 2.720 -Slack : -2.564 -From Node : counter[2] -To Node : address[2] +Slack : -1.788 +From Node : counter[14] +To Node : address[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.848 +Clock Skew : -0.063 +Data Delay : 2.720 -Slack : -2.541 -From Node : counter[7] -To Node : address[2] +Slack : -1.788 +From Node : counter[14] +To Node : address[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.825 +Clock Skew : -0.063 +Data Delay : 2.720 -Slack : -2.502 -From Node : counter[5] -To Node : address[1] +Slack : -1.788 +From Node : counter[14] +To Node : address[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.786 +Clock Skew : -0.063 +Data Delay : 2.720 -Slack : -2.490 -From Node : counter[3] -To Node : address[1] +Slack : -1.788 +From Node : counter[14] +To Node : address[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.774 +Clock Skew : -0.063 +Data Delay : 2.720 -Slack : -2.462 -From Node : counter[6] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.746 - -Slack : -2.426 -From Node : counter[1] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.710 - -Slack : -2.421 -From Node : counter[4] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.705 - -Slack : -2.407 -From Node : counter[2] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.691 - -Slack : -2.384 -From Node : counter[7] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.668 - -Slack : -2.345 -From Node : counter[0] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.629 - -Slack : -2.322 -From Node : counter[5] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.606 - -Slack : -2.311 -From Node : counter[11] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.595 - -Slack : -2.310 -From Node : counter[3] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.594 - -Slack : -2.305 -From Node : counter[6] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.589 - -Slack : -2.293 -From Node : counter[9] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.577 - -Slack : -2.241 -From Node : counter[4] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.525 - -Slack : -2.227 -From Node : counter[2] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.511 - -Slack : -2.214 -From Node : counter[8] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.498 - -Slack : -2.204 -From Node : counter[7] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.488 - -Slack : -2.194 -From Node : counter[13] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.478 - -Slack : -2.125 -From Node : counter[6] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.409 - -Slack : -2.111 -From Node : counter[12] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.395 - -Slack : -2.097 -From Node : counter[10] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.381 - -Slack : -2.079 -From Node : counter[15] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.363 - -Slack : -1.998 +Slack : -1.788 From Node : counter[14] To Node : address[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.282 +Clock Skew : -0.063 +Data Delay : 2.720 -Slack : -1.990 -From Node : counter[8] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.274 - -Slack : -1.987 -From Node : counter[11] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.271 - -Slack : -1.974 -From Node : counter[11] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.258 - -Slack : -1.969 -From Node : counter[9] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.253 - -Slack : -1.959 -From Node : counter[17] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.243 - -Slack : -1.956 -From Node : counter[9] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.240 - -Slack : -1.882 -From Node : counter[16] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.166 - -Slack : -1.877 -From Node : counter[8] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.161 - -Slack : -1.873 -From Node : counter[10] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.157 - -Slack : -1.870 -From Node : counter[13] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.154 - -Slack : -1.857 -From Node : counter[13] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.141 - -Slack : -1.830 -From Node : counter[12] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.114 - -Slack : -1.774 -From Node : counter[12] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.058 - -Slack : -1.760 -From Node : counter[10] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.044 - -Slack : -1.756 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.069 -Data Delay : 2.616 - -Slack : -1.756 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.069 -Data Delay : 2.616 - -Slack : -1.756 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.069 -Data Delay : 2.616 - -Slack : -1.756 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[4] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.069 -Data Delay : 2.616 - -Slack : -1.756 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[3] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.069 -Data Delay : 2.616 - -Slack : -1.756 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.069 -Data Delay : 2.616 - -Slack : -1.756 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.069 -Data Delay : 2.616 - -Slack : -1.756 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.069 -Data Delay : 2.616 - -Slack : -1.755 -From Node : counter[15] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.039 - -Slack : -1.742 -From Node : counter[15] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 3.026 - -Slack : -1.678 +Slack : -1.788 From Node : counter[14] To Node : address[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 2.962 +Clock Skew : -0.063 +Data Delay : 2.720 -Slack : -1.661 -From Node : counter[14] -To Node : address[0] +Slack : -1.781 +From Node : counter[13] +To Node : address[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 2.945 +Clock Skew : -0.063 +Data Delay : 2.713 -Slack : -1.635 -From Node : counter[17] -To Node : address[1] +Slack : -1.781 +From Node : counter[13] +To Node : address[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 2.919 +Clock Skew : -0.063 +Data Delay : 2.713 -Slack : -1.622 -From Node : counter[17] -To Node : address[0] +Slack : -1.781 +From Node : counter[13] +To Node : address[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 2.906 +Clock Skew : -0.063 +Data Delay : 2.713 -Slack : -1.609 -From Node : counter[1] -To Node : counter[20] +Slack : -1.781 +From Node : counter[13] +To Node : address[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.062 -Data Delay : 2.542 +Clock Skew : -0.063 +Data Delay : 2.713 -Slack : -1.581 -From Node : counter[18] +Slack : -1.781 +From Node : counter[13] +To Node : address[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.713 + +Slack : -1.781 +From Node : counter[13] +To Node : address[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.713 + +Slack : -1.781 +From Node : counter[13] +To Node : address[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.713 + +Slack : -1.781 +From Node : counter[13] +To Node : address[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.713 + +Slack : -1.781 +From Node : counter[13] +To Node : address[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.713 + +Slack : -1.781 +From Node : counter[13] +To Node : address[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.713 + +Slack : -1.781 +From Node : counter[13] +To Node : address[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.713 + +Slack : -1.781 +From Node : counter[13] To Node : address[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 2.865 +Clock Skew : -0.063 +Data Delay : 2.713 -Slack : -1.566 -From Node : counter[16] +Slack : -1.781 +From Node : counter[13] To Node : address[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 2.850 +Clock Skew : -0.063 +Data Delay : 2.713 -Slack : -1.545 -From Node : counter[16] -To Node : address[0] +Slack : -1.756 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 2.829 +Clock Skew : -0.069 +Data Delay : 2.616 -Slack : -1.528 -From Node : counter[0] -To Node : counter[20] +Slack : -1.756 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.062 -Data Delay : 2.461 +Clock Skew : -0.069 +Data Delay : 2.616 -Slack : -1.521 -From Node : counter[19] -To Node : address[1] +Slack : -1.756 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 2.805 +Clock Skew : -0.069 +Data Delay : 2.616 -Slack : -1.505 -From Node : counter[5] -To Node : counter[20] +Slack : -1.756 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.062 -Data Delay : 2.438 +Clock Skew : -0.069 +Data Delay : 2.616 -Slack : -1.493 -From Node : counter[1] -To Node : counter[18] +Slack : -1.756 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.062 -Data Delay : 2.426 +Clock Skew : -0.069 +Data Delay : 2.616 -Slack : -1.493 -From Node : counter[3] -To Node : counter[20] +Slack : -1.756 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.062 -Data Delay : 2.426 +Clock Skew : -0.069 +Data Delay : 2.616 -Slack : -1.487 -From Node : counter[0] -To Node : counter[19] +Slack : -1.756 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.062 -Data Delay : 2.420 +Clock Skew : -0.069 +Data Delay : 2.616 -Slack : -1.487 -From Node : counter[1] -To Node : counter[19] +Slack : -1.756 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.062 -Data Delay : 2.420 +Clock Skew : -0.069 +Data Delay : 2.616 -Slack : -1.475 -From Node : counter[19] +Slack : -1.756 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.069 +Data Delay : 2.616 + +Slack : -1.756 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.069 +Data Delay : 2.616 + +Slack : -1.756 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.069 +Data Delay : 2.616 + +Slack : -1.756 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.069 +Data Delay : 2.616 + +Slack : -1.756 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.069 +Data Delay : 2.616 + +Slack : -1.756 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.069 +Data Delay : 2.616 + +Slack : -1.756 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.069 +Data Delay : 2.616 + +Slack : -1.756 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.069 +Data Delay : 2.616 + +Slack : -1.705 +From Node : counter[6] +To Node : address[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.637 + +Slack : -1.705 +From Node : counter[6] +To Node : address[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.637 + +Slack : -1.705 +From Node : counter[6] +To Node : address[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.637 + +Slack : -1.705 +From Node : counter[6] +To Node : address[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.637 + +Slack : -1.705 +From Node : counter[6] +To Node : address[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.637 + +Slack : -1.705 +From Node : counter[6] +To Node : address[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.637 + +Slack : -1.705 +From Node : counter[6] +To Node : address[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.637 + +Slack : -1.705 +From Node : counter[6] +To Node : address[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.637 + +Slack : -1.705 +From Node : counter[6] +To Node : address[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.637 + +Slack : -1.705 +From Node : counter[6] +To Node : address[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.637 + +Slack : -1.705 +From Node : counter[6] +To Node : address[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.637 + +Slack : -1.705 +From Node : counter[6] To Node : address[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 2.759 +Clock Skew : -0.063 +Data Delay : 2.637 -Slack : -1.442 -From Node : counter[18] +Slack : -1.705 +From Node : counter[6] To Node : address[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 2.726 +Clock Skew : -0.063 +Data Delay : 2.637 -Slack : -1.424 -From Node : counter[4] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.062 -Data Delay : 2.357 - -Slack : -1.412 -From Node : counter[0] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.062 -Data Delay : 2.345 - -Slack : -1.410 -From Node : counter[2] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.062 -Data Delay : 2.343 - -Slack : -1.398 -From Node : counter[4] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.062 -Data Delay : 2.331 - -Slack : -1.389 -From Node : counter[5] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.062 -Data Delay : 2.322 - -Slack : -1.387 +Slack : -1.698 From Node : counter[7] -To Node : counter[20] +To Node : address[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.062 -Data Delay : 2.320 +Clock Skew : -0.063 +Data Delay : 2.630 -Slack : -1.383 -From Node : counter[5] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.062 -Data Delay : 2.316 - -Slack : -1.377 -From Node : counter[1] -To Node : counter[16] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.062 -Data Delay : 2.310 - -Slack : -1.377 -From Node : counter[3] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.062 -Data Delay : 2.310 - -Slack : -1.375 -From Node : counter[2] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.062 -Data Delay : 2.308 - -Slack : -1.371 -From Node : counter[0] -To Node : counter[17] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.062 -Data Delay : 2.304 - -Slack : -1.371 -From Node : counter[1] -To Node : counter[17] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.062 -Data Delay : 2.304 - -Slack : -1.371 -From Node : counter[3] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.062 -Data Delay : 2.304 - -Slack : -1.308 -From Node : counter[6] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.062 -Data Delay : 2.241 - -Slack : -1.308 -From Node : counter[4] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.062 -Data Delay : 2.241 - -Slack : -1.296 -From Node : counter[0] -To Node : counter[16] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.062 -Data Delay : 2.229 - -Slack : -1.294 -From Node : counter[2] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.062 -Data Delay : 2.227 - -Slack : -1.282 -From Node : counter[6] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.062 -Data Delay : 2.215 - -Slack : -1.282 -From Node : counter[4] -To Node : counter[17] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.062 -Data Delay : 2.215 - -Slack : -1.278 -From Node : counter[19] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.289 -Data Delay : 2.562 - -Slack : -1.273 -From Node : counter[5] -To Node : counter[16] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.062 -Data Delay : 2.206 - -Slack : -1.271 +Slack : -1.698 From Node : counter[7] -To Node : counter[18] +To Node : address[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.062 -Data Delay : 2.204 +Clock Skew : -0.063 +Data Delay : 2.630 -Slack : -1.267 -From Node : counter[5] -To Node : counter[17] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.062 -Data Delay : 2.200 - -Slack : -1.265 +Slack : -1.698 From Node : counter[7] -To Node : counter[19] +To Node : address[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.062 -Data Delay : 2.198 +Clock Skew : -0.063 +Data Delay : 2.630 -Slack : -1.261 +Slack : -1.698 +From Node : counter[7] +To Node : address[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.630 + +Slack : -1.698 +From Node : counter[7] +To Node : address[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.630 + +Slack : -1.698 +From Node : counter[7] +To Node : address[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.630 + +Slack : -1.698 +From Node : counter[7] +To Node : address[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.630 + +Slack : -1.698 +From Node : counter[7] +To Node : address[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.630 + +Slack : -1.698 +From Node : counter[7] +To Node : address[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.630 + +Slack : -1.698 +From Node : counter[7] +To Node : address[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.630 + +Slack : -1.698 +From Node : counter[7] +To Node : address[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.630 + +Slack : -1.698 +From Node : counter[7] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.630 + +Slack : -1.698 +From Node : counter[7] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.630 + +Slack : -1.691 From Node : counter[1] -To Node : counter[14] +To Node : address[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.062 -Data Delay : 2.194 +Clock Skew : -0.063 +Data Delay : 2.623 -Slack : -1.261 -From Node : counter[3] -To Node : counter[16] +Slack : -1.691 +From Node : counter[1] +To Node : address[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.062 -Data Delay : 2.194 +Clock Skew : -0.063 +Data Delay : 2.623 -Slack : -1.259 -From Node : counter[2] -To Node : counter[17] +Slack : -1.691 +From Node : counter[1] +To Node : address[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.062 -Data Delay : 2.192 +Clock Skew : -0.063 +Data Delay : 2.623 + +Slack : -1.691 +From Node : counter[1] +To Node : address[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.623 + +Slack : -1.691 +From Node : counter[1] +To Node : address[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.623 + +Slack : -1.691 +From Node : counter[1] +To Node : address[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.623 + +Slack : -1.691 +From Node : counter[1] +To Node : address[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.623 + +Slack : -1.691 +From Node : counter[1] +To Node : address[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.623 + +Slack : -1.691 +From Node : counter[1] +To Node : address[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.623 + +Slack : -1.691 +From Node : counter[1] +To Node : address[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.623 + +Slack : -1.691 +From Node : counter[1] +To Node : address[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.623 + +Slack : -1.691 +From Node : counter[1] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.623 + +Slack : -1.691 +From Node : counter[1] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.623 + +Slack : -1.684 +From Node : counter[0] +To Node : address[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.616 + +Slack : -1.684 +From Node : counter[0] +To Node : address[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.616 + +Slack : -1.684 +From Node : counter[0] +To Node : address[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.616 + +Slack : -1.684 +From Node : counter[0] +To Node : address[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.616 + +Slack : -1.684 +From Node : counter[0] +To Node : address[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.616 + +Slack : -1.684 +From Node : counter[0] +To Node : address[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.616 + +Slack : -1.684 +From Node : counter[0] +To Node : address[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.616 + +Slack : -1.684 +From Node : counter[0] +To Node : address[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.616 + +Slack : -1.684 +From Node : counter[0] +To Node : address[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.616 + +Slack : -1.684 +From Node : counter[0] +To Node : address[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.616 + +Slack : -1.684 +From Node : counter[0] +To Node : address[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.616 + +Slack : -1.684 +From Node : counter[0] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.616 + +Slack : -1.684 +From Node : counter[0] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.616 + +Slack : -1.673 +From Node : counter[5] +To Node : address[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.605 + +Slack : -1.673 +From Node : counter[5] +To Node : address[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.605 + +Slack : -1.673 +From Node : counter[5] +To Node : address[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.605 + +Slack : -1.673 +From Node : counter[5] +To Node : address[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.605 + +Slack : -1.673 +From Node : counter[5] +To Node : address[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.605 + +Slack : -1.673 +From Node : counter[5] +To Node : address[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.063 +Data Delay : 2.605 +--------------------------------------------------------------------------------+ @@ -1099,905 +1099,905 @@ Data Delay : 2.192 +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Hold: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ -Slack : 0.343 -From Node : address[2] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 0.577 - -Slack : 0.343 +Slack : 0.260 From Node : address[1] -To Node : address[1] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 0.577 +Clock Skew : 0.377 +Data Delay : 0.824 -Slack : 0.343 +Slack : 0.260 +From Node : address[1] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.377 +Data Delay : 0.824 + +Slack : 0.267 +From Node : address[4] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.377 +Data Delay : 0.831 + +Slack : 0.319 +From Node : address[2] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.377 +Data Delay : 0.883 + +Slack : 0.339 +From Node : address[5] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.377 +Data Delay : 0.903 + +Slack : 0.344 From Node : address[0] To Node : address[0] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.077 +Clock Skew : 0.076 Data Delay : 0.577 -Slack : 0.370 -From Node : counter[20] -To Node : counter[20] +Slack : 0.345 +From Node : address[7] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.589 +Clock Skew : 0.377 +Data Delay : 0.909 -Slack : 0.547 -From Node : counter[9] -To Node : counter[9] +Slack : 0.346 +From Node : address[11] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.766 +Clock Skew : 0.377 +Data Delay : 0.910 -Slack : 0.551 -From Node : counter[10] -To Node : counter[10] +Slack : 0.355 +From Node : address[12] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.770 +Clock Skew : 0.377 +Data Delay : 0.919 -Slack : 0.551 -From Node : counter[8] -To Node : counter[8] +Slack : 0.360 +From Node : address[8] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.770 +Clock Skew : 0.377 +Data Delay : 0.924 -Slack : 0.551 -From Node : counter[3] -To Node : counter[3] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.770 - -Slack : 0.551 -From Node : counter[1] -To Node : counter[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.770 - -Slack : 0.553 -From Node : counter[2] -To Node : counter[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.772 - -Slack : 0.568 +Slack : 0.361 From Node : counter[0] To Node : counter[0] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.787 +Data Delay : 0.580 -Slack : 0.681 +Slack : 0.364 +From Node : address[3] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.377 +Data Delay : 0.928 + +Slack : 0.365 +From Node : address[6] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.377 +Data Delay : 0.929 + +Slack : 0.373 +From Node : address[9] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.377 +Data Delay : 0.937 + +Slack : 0.375 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|out_address_reg_a[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.594 + +Slack : 0.376 +From Node : counter[21] +To Node : counter[21] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 0.610 + +Slack : 0.408 +From Node : address[13] +To Node : address[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.628 + +Slack : 0.484 +From Node : counter[19] +To Node : counter[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.428 +Data Delay : 1.069 + +Slack : 0.486 +From Node : counter[19] +To Node : counter[21] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.428 +Data Delay : 1.071 + +Slack : 0.526 +From Node : address[4] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.377 +Data Delay : 1.090 + +Slack : 0.537 +From Node : address[7] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.385 +Data Delay : 1.109 + +Slack : 0.545 +From Node : address[4] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.393 +Data Delay : 1.125 + +Slack : 0.546 +From Node : address[11] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.385 +Data Delay : 1.118 + +Slack : 0.552 +From Node : address[4] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.377 +Data Delay : 1.116 + +Slack : 0.552 +From Node : address[1] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.393 +Data Delay : 1.132 + +Slack : 0.556 +From Node : address[12] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.385 +Data Delay : 1.128 + +Slack : 0.556 From Node : counter[14] To Node : counter[14] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.900 +Data Delay : 0.775 -Slack : 0.683 -From Node : counter[19] -To Node : counter[19] +Slack : 0.556 +From Node : counter[10] +To Node : counter[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.902 +Data Delay : 0.775 -Slack : 0.684 -From Node : counter[7] -To Node : counter[7] +Slack : 0.556 +From Node : counter[8] +To Node : counter[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.903 +Data Delay : 0.775 -Slack : 0.684 -From Node : counter[5] -To Node : counter[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.903 - -Slack : 0.685 -From Node : counter[16] -To Node : counter[16] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.904 - -Slack : 0.686 -From Node : counter[18] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.905 - -Slack : 0.686 -From Node : address[1] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 0.920 - -Slack : 0.687 -From Node : counter[17] -To Node : counter[17] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.906 - -Slack : 0.687 +Slack : 0.557 From Node : counter[12] To Node : counter[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.906 +Data Delay : 0.776 -Slack : 0.687 +Slack : 0.557 From Node : counter[6] To Node : counter[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.906 +Data Delay : 0.776 -Slack : 0.687 +Slack : 0.558 +From Node : counter[16] +To Node : counter[16] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.777 + +Slack : 0.558 +From Node : counter[20] +To Node : counter[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 0.792 + +Slack : 0.559 +From Node : counter[17] +To Node : counter[17] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.778 + +Slack : 0.559 From Node : counter[4] To Node : counter[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.906 +Data Delay : 0.778 -Slack : 0.690 -From Node : counter[15] -To Node : counter[15] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.909 - -Slack : 0.690 +Slack : 0.560 From Node : counter[13] To Node : counter[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.909 +Data Delay : 0.779 -Slack : 0.691 -From Node : counter[11] -To Node : counter[11] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 0.910 - -Slack : 0.822 +Slack : 0.560 From Node : counter[9] -To Node : counter[10] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.041 - -Slack : 0.825 -From Node : counter[1] -To Node : counter[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.044 - -Slack : 0.825 -From Node : counter[3] -To Node : counter[4] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.044 - -Slack : 0.838 -From Node : counter[8] To Node : counter[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 1.057 +Data Delay : 0.779 -Slack : 0.838 +Slack : 0.560 +From Node : counter[2] +To Node : counter[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.779 + +Slack : 0.561 +From Node : counter[18] +To Node : counter[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.780 + +Slack : 0.561 +From Node : counter[7] +To Node : counter[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.780 + +Slack : 0.561 +From Node : counter[3] +To Node : counter[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.780 + +Slack : 0.562 +From Node : counter[15] +To Node : counter[15] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.781 + +Slack : 0.563 +From Node : address[4] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.385 +Data Delay : 1.135 + +Slack : 0.563 +From Node : counter[19] +To Node : counter[19] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.782 + +Slack : 0.567 +From Node : address[10] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.385 +Data Delay : 1.139 + +Slack : 0.568 +From Node : address[4] +To Node : address[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.788 + +Slack : 0.569 +From Node : address[4] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.393 +Data Delay : 1.149 + +Slack : 0.569 +From Node : address[12] +To Node : address[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.789 + +Slack : 0.569 +From Node : address[6] +To Node : address[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.789 + +Slack : 0.569 +From Node : address[2] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.789 + +Slack : 0.570 +From Node : address[7] +To Node : address[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.790 + +Slack : 0.571 +From Node : address[10] +To Node : address[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.791 + +Slack : 0.571 From Node : counter[0] To Node : counter[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 1.057 +Data Delay : 0.790 -Slack : 0.838 -From Node : counter[10] -To Node : counter[11] +Slack : 0.572 +From Node : address[8] +To Node : address[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.792 + +Slack : 0.573 +From Node : address[5] +To Node : address[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.793 + +Slack : 0.573 +From Node : counter[1] +To Node : counter[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 1.057 +Data Delay : 0.792 -Slack : 0.840 -From Node : counter[2] -To Node : counter[3] +Slack : 0.574 +From Node : address[13] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 1.059 +Data Delay : 0.793 -Slack : 0.840 -From Node : counter[10] -To Node : counter[12] +Slack : 0.574 +From Node : address[3] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.385 +Data Delay : 1.146 + +Slack : 0.574 +From Node : address[1] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.377 +Data Delay : 1.138 + +Slack : 0.574 +From Node : address[11] +To Node : address[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.794 + +Slack : 0.574 +From Node : address[9] +To Node : address[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.794 + +Slack : 0.574 +From Node : counter[5] +To Node : counter[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 1.059 +Data Delay : 0.793 -Slack : 0.840 -From Node : counter[8] -To Node : counter[10] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.059 - -Slack : 0.840 -From Node : counter[0] -To Node : counter[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.059 - -Slack : 0.842 -From Node : counter[2] -To Node : counter[4] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.061 - -Slack : 0.861 -From Node : counter[20] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.446 - -Slack : 0.871 -From Node : address[0] +Slack : 0.579 +From Node : address[1] To Node : address[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 1.105 +Clock Skew : 0.063 +Data Delay : 0.799 -Slack : 0.932 -From Node : counter[9] -To Node : counter[11] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.151 - -Slack : 0.934 -From Node : counter[9] -To Node : counter[12] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.153 - -Slack : 0.935 -From Node : counter[3] -To Node : counter[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.154 - -Slack : 0.935 -From Node : counter[1] -To Node : counter[3] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.154 - -Slack : 0.937 -From Node : counter[3] -To Node : counter[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.156 - -Slack : 0.937 -From Node : counter[1] -To Node : counter[4] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.156 - -Slack : 0.950 -From Node : counter[10] -To Node : counter[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.169 - -Slack : 0.950 -From Node : counter[8] -To Node : counter[11] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.169 - -Slack : 0.950 -From Node : counter[0] -To Node : counter[3] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.169 - -Slack : 0.952 -From Node : counter[10] -To Node : counter[14] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.171 - -Slack : 0.952 -From Node : counter[8] -To Node : counter[12] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.171 - -Slack : 0.952 -From Node : counter[2] -To Node : counter[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.171 - -Slack : 0.952 -From Node : counter[0] -To Node : counter[4] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.171 - -Slack : 0.954 -From Node : counter[2] -To Node : counter[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.173 - -Slack : 0.958 -From Node : counter[19] +Slack : 0.579 +From Node : counter[18] To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.177 +Clock Skew : 0.428 +Data Delay : 1.164 -Slack : 0.958 -From Node : counter[7] -To Node : counter[8] +Slack : 0.581 +From Node : counter[18] +To Node : counter[21] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.177 +Clock Skew : 0.428 +Data Delay : 1.166 -Slack : 0.958 -From Node : counter[5] -To Node : counter[6] +Slack : 0.582 +From Node : address[6] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.177 +Clock Skew : 0.385 +Data Delay : 1.154 -Slack : 0.962 +Slack : 0.584 +From Node : address[9] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.385 +Data Delay : 1.156 + +Slack : 0.591 +From Node : address[3] +To Node : address[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.063 +Data Delay : 0.811 + +Slack : 0.593 From Node : counter[17] -To Node : counter[18] +To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.181 +Clock Skew : 0.428 +Data Delay : 1.178 -Slack : 0.964 -From Node : counter[15] -To Node : counter[16] +Slack : 0.595 +From Node : counter[17] +To Node : counter[21] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.183 +Clock Skew : 0.428 +Data Delay : 1.180 -Slack : 0.964 -From Node : counter[13] -To Node : counter[14] +Slack : 0.600 +From Node : address[10] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.183 +Clock Skew : 0.393 +Data Delay : 1.180 -Slack : 0.965 -From Node : counter[11] -To Node : counter[12] +Slack : 0.601 +From Node : address[5] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.184 +Clock Skew : 0.377 +Data Delay : 1.165 -Slack : 0.969 -From Node : counter[14] -To Node : counter[15] +Slack : 0.611 +From Node : address[2] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.188 - -Slack : 0.971 -From Node : counter[14] -To Node : counter[16] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.190 - -Slack : 0.972 -From Node : counter[16] -To Node : counter[17] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 +Clock Skew : 0.393 Data Delay : 1.191 -Slack : 0.974 -From Node : counter[18] -To Node : counter[19] +Slack : 0.624 +From Node : address[2] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.193 +Clock Skew : 0.393 +Data Delay : 1.204 -Slack : 0.974 -From Node : counter[12] -To Node : counter[13] +Slack : 0.628 +From Node : address[8] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.193 +Clock Skew : 0.393 +Data Delay : 1.208 -Slack : 0.974 +Slack : 0.629 +From Node : address[8] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.393 +Data Delay : 1.209 + +Slack : 0.632 +From Node : address[2] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.393 +Data Delay : 1.212 + +Slack : 0.635 +From Node : address[10] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.377 +Data Delay : 1.199 + +Slack : 0.636 +From Node : address[9] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.393 +Data Delay : 1.216 + +Slack : 0.637 +From Node : address[10] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.377 +Data Delay : 1.201 + +Slack : 0.641 +From Node : address[5] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.377 +Data Delay : 1.205 + +Slack : 0.641 +From Node : address[9] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.377 +Data Delay : 1.205 + +Slack : 0.642 +From Node : address[5] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.393 +Data Delay : 1.222 + +Slack : 0.650 +From Node : address[3] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.377 +Data Delay : 1.214 + +Slack : 0.650 +From Node : address[3] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.393 +Data Delay : 1.230 + +Slack : 0.663 +From Node : address[3] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.393 +Data Delay : 1.243 + +Slack : 0.672 +From Node : address[2] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.377 +Data Delay : 1.236 + +Slack : 0.675 +From Node : address[9] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.393 +Data Delay : 1.255 + +Slack : 0.677 +From Node : address[9] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.377 +Data Delay : 1.241 + +Slack : 0.689 From Node : counter[16] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.193 - -Slack : 0.975 -From Node : counter[6] -To Node : counter[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.194 - -Slack : 0.975 -From Node : counter[4] -To Node : counter[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.194 - -Slack : 0.976 -From Node : counter[12] -To Node : counter[14] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.195 - -Slack : 0.976 -From Node : counter[18] To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.195 +Clock Skew : 0.428 +Data Delay : 1.274 -Slack : 0.977 -From Node : counter[4] -To Node : counter[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.196 - -Slack : 0.977 -From Node : counter[6] -To Node : counter[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.196 - -Slack : 1.044 -From Node : counter[9] -To Node : counter[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.263 - -Slack : 1.046 -From Node : counter[9] -To Node : counter[14] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.265 - -Slack : 1.047 -From Node : counter[1] -To Node : counter[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.266 - -Slack : 1.047 -From Node : counter[3] -To Node : counter[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.266 - -Slack : 1.049 -From Node : counter[1] -To Node : counter[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.268 - -Slack : 1.049 -From Node : counter[3] -To Node : counter[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.268 - -Slack : 1.053 -From Node : counter[19] -To Node : address[1] +Slack : 0.691 +From Node : counter[16] +To Node : counter[21] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.428 -Data Delay : 1.638 +Data Delay : 1.276 -Slack : 1.058 -From Node : counter[20] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.643 - -Slack : 1.062 -From Node : counter[10] -To Node : counter[15] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.281 - -Slack : 1.062 -From Node : counter[8] -To Node : counter[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.281 - -Slack : 1.062 -From Node : counter[0] -To Node : counter[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.281 - -Slack : 1.064 -From Node : counter[10] -To Node : counter[16] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.283 - -Slack : 1.064 -From Node : counter[8] -To Node : counter[14] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.283 - -Slack : 1.064 -From Node : counter[2] -To Node : counter[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.283 - -Slack : 1.064 -From Node : counter[0] -To Node : counter[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.283 - -Slack : 1.066 -From Node : counter[2] -To Node : counter[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.285 - -Slack : 1.068 -From Node : counter[7] -To Node : counter[9] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.287 - -Slack : 1.068 -From Node : counter[5] -To Node : counter[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.287 - -Slack : 1.070 -From Node : counter[7] -To Node : counter[10] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.289 - -Slack : 1.070 -From Node : counter[5] -To Node : counter[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.289 - -Slack : 1.072 -From Node : counter[17] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.291 - -Slack : 1.074 +Slack : 0.707 From Node : counter[15] -To Node : counter[17] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.293 - -Slack : 1.074 -From Node : counter[17] To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.293 +Clock Skew : 0.428 +Data Delay : 1.292 -Slack : 1.074 -From Node : counter[13] -To Node : counter[15] +Slack : 0.709 +From Node : counter[15] +To Node : counter[21] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.293 - -Slack : 1.075 -From Node : counter[11] -To Node : counter[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 +Clock Skew : 0.428 Data Delay : 1.294 -Slack : 1.076 -From Node : counter[15] -To Node : counter[18] +Slack : 0.787 +From Node : address[11] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.295 +Clock Skew : 0.384 +Data Delay : 1.358 -Slack : 1.076 -From Node : counter[13] -To Node : counter[16] +Slack : 0.790 +From Node : address[11] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.295 +Clock Skew : 0.377 +Data Delay : 1.354 -Slack : 1.077 -From Node : counter[11] -To Node : counter[14] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.296 - -Slack : 1.081 +Slack : 0.799 From Node : counter[14] -To Node : counter[17] +To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.062 -Data Delay : 1.300 +Clock Skew : 0.428 +Data Delay : 1.384 + +Slack : 0.801 +From Node : counter[14] +To Node : counter[21] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.428 +Data Delay : 1.386 + +Slack : 0.808 +From Node : address[5] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.393 +Data Delay : 1.388 + +Slack : 0.808 +From Node : address[9] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.384 +Data Delay : 1.379 + +Slack : 0.810 +From Node : address[1] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.393 +Data Delay : 1.390 +--------------------------------------------------------------------------------+ @@ -2019,7 +2019,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[0] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 Slack : -2.174 Actual Width : 1.000 @@ -2027,7 +2027,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[1] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 Slack : -2.174 Actual Width : 1.000 @@ -2035,7 +2035,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[2] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 Slack : -2.174 Actual Width : 1.000 @@ -2043,7 +2043,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[3] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 Slack : -2.174 Actual Width : 1.000 @@ -2051,7 +2051,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[4] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 Slack : -2.174 Actual Width : 1.000 @@ -2059,7 +2059,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[5] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 Slack : -2.174 Actual Width : 1.000 @@ -2067,7 +2067,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[6] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 Slack : -2.174 Actual Width : 1.000 @@ -2075,7 +2075,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[7] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 Slack : -2.174 Actual Width : 1.000 @@ -2083,7 +2083,191 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0 Slack : -1.000 Actual Width : 1.000 @@ -2093,6 +2277,38 @@ Clock : CLOCK_50 Clock Edge : Rise Target : address[0] +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : address[10] + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : address[11] + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : address[12] + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : address[13] + Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 @@ -2109,6 +2325,62 @@ Clock : CLOCK_50 Clock Edge : Rise Target : address[2] +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : address[3] + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : address[4] + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : address[5] + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : address[6] + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : address[7] + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : address[8] + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : address[9] + Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 @@ -2213,6 +2485,14 @@ Clock : CLOCK_50 Clock Edge : Rise Target : counter[20] +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[21] + Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 @@ -2277,13 +2557,149 @@ Clock : CLOCK_50 Clock Edge : Rise Target : counter[9] +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0] + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|out_address_reg_a[0] + Slack : -0.011 Actual Width : 0.219 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 + +Slack : -0.011 +Actual Width : 0.219 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 + +Slack : -0.011 +Actual Width : 0.219 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 + +Slack : -0.011 +Actual Width : 0.219 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 + +Slack : -0.011 +Actual Width : 0.219 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 + +Slack : -0.011 +Actual Width : 0.219 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 + +Slack : -0.011 +Actual Width : 0.219 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0 + +Slack : -0.010 +Actual Width : 0.220 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 + +Slack : -0.010 +Actual Width : 0.220 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 + +Slack : -0.010 +Actual Width : 0.220 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 + +Slack : -0.010 +Actual Width : 0.220 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 + +Slack : -0.010 +Actual Width : 0.220 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 + +Slack : -0.010 +Actual Width : 0.220 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 + +Slack : -0.010 +Actual Width : 0.220 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 + +Slack : -0.010 +Actual Width : 0.220 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0 + +Slack : -0.009 +Actual Width : 0.221 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0 Slack : -0.007 Actual Width : 0.223 @@ -2291,7 +2707,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[0] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 Slack : -0.007 Actual Width : 0.223 @@ -2299,7 +2715,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[1] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 Slack : -0.007 Actual Width : 0.223 @@ -2307,7 +2723,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[2] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 Slack : -0.007 Actual Width : 0.223 @@ -2315,7 +2731,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[3] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 Slack : -0.007 Actual Width : 0.223 @@ -2323,7 +2739,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[4] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 Slack : -0.007 Actual Width : 0.223 @@ -2331,7 +2747,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[5] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 Slack : -0.007 Actual Width : 0.223 @@ -2339,471 +2755,55 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[6] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 -Slack : -0.007 -Actual Width : 0.223 +Slack : -0.006 +Actual Width : 0.224 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[7] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 -Slack : 0.088 -Actual Width : 0.272 -Required Width : 0.184 +Slack : -0.006 +Actual Width : 0.224 +Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : address[0] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 -Slack : 0.088 -Actual Width : 0.272 -Required Width : 0.184 +Slack : -0.006 +Actual Width : 0.224 +Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : address[1] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 -Slack : 0.088 -Actual Width : 0.272 -Required Width : 0.184 +Slack : -0.006 +Actual Width : 0.224 +Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : address[2] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 -Slack : 0.097 -Actual Width : 0.281 -Required Width : 0.184 +Slack : -0.006 +Actual Width : 0.224 +Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : counter[0] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 -Slack : 0.097 -Actual Width : 0.281 -Required Width : 0.184 +Slack : -0.006 +Actual Width : 0.224 +Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : counter[10] - -Slack : 0.097 -Actual Width : 0.281 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[11] - -Slack : 0.097 -Actual Width : 0.281 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[12] - -Slack : 0.097 -Actual Width : 0.281 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[13] - -Slack : 0.097 -Actual Width : 0.281 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[14] - -Slack : 0.097 -Actual Width : 0.281 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[15] - -Slack : 0.097 -Actual Width : 0.281 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[16] - -Slack : 0.097 -Actual Width : 0.281 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[17] - -Slack : 0.097 -Actual Width : 0.281 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[18] - -Slack : 0.097 -Actual Width : 0.281 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[19] - -Slack : 0.097 -Actual Width : 0.281 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[1] - -Slack : 0.097 -Actual Width : 0.281 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[20] - -Slack : 0.097 -Actual Width : 0.281 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[2] - -Slack : 0.097 -Actual Width : 0.281 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[3] - -Slack : 0.097 -Actual Width : 0.281 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[4] - -Slack : 0.097 -Actual Width : 0.281 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[5] - -Slack : 0.097 -Actual Width : 0.281 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[6] - -Slack : 0.097 -Actual Width : 0.281 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[7] - -Slack : 0.097 -Actual Width : 0.281 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[8] - -Slack : 0.097 -Actual Width : 0.281 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[9] - -Slack : 0.247 -Actual Width : 0.247 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : CLOCK_50~input|o - -Slack : 0.250 -Actual Width : 0.250 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : address[0]|clk - -Slack : 0.250 -Actual Width : 0.250 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : address[1]|clk - -Slack : 0.250 -Actual Width : 0.250 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : address[2]|clk - -Slack : 0.258 -Actual Width : 0.258 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom|altsyncram_component|auto_generated|ram_block1a0|clk0 - -Slack : 0.259 -Actual Width : 0.259 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[0]|clk - -Slack : 0.259 -Actual Width : 0.259 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[10]|clk - -Slack : 0.259 -Actual Width : 0.259 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[11]|clk - -Slack : 0.259 -Actual Width : 0.259 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[12]|clk - -Slack : 0.259 -Actual Width : 0.259 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[13]|clk - -Slack : 0.259 -Actual Width : 0.259 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[14]|clk - -Slack : 0.259 -Actual Width : 0.259 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[15]|clk - -Slack : 0.259 -Actual Width : 0.259 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[16]|clk - -Slack : 0.259 -Actual Width : 0.259 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[17]|clk - -Slack : 0.259 -Actual Width : 0.259 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[18]|clk - -Slack : 0.259 -Actual Width : 0.259 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[19]|clk - -Slack : 0.259 -Actual Width : 0.259 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[1]|clk - -Slack : 0.259 -Actual Width : 0.259 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[20]|clk - -Slack : 0.259 -Actual Width : 0.259 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[2]|clk - -Slack : 0.259 -Actual Width : 0.259 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[3]|clk - -Slack : 0.259 -Actual Width : 0.259 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[4]|clk - -Slack : 0.259 -Actual Width : 0.259 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[5]|clk - -Slack : 0.259 -Actual Width : 0.259 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[6]|clk - -Slack : 0.259 -Actual Width : 0.259 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[7]|clk - -Slack : 0.259 -Actual Width : 0.259 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[8]|clk - -Slack : 0.259 -Actual Width : 0.259 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[9]|clk - -Slack : 0.263 -Actual Width : 0.263 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : CLOCK_50~inputclkctrl|inclk[0] - -Slack : 0.263 -Actual Width : 0.263 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : CLOCK_50~inputclkctrl|outclk - -Slack : 0.500 -Actual Width : 0.500 -Required Width : 0.000 -Type : High Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : CLOCK_50~input|i - -Slack : 0.500 -Actual Width : 0.500 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : CLOCK_50~input|i - -Slack : 0.501 -Actual Width : 0.717 -Required Width : 0.216 -Type : High Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[0] - -Slack : 0.501 -Actual Width : 0.717 -Required Width : 0.216 -Type : High Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[10] - -Slack : 0.501 -Actual Width : 0.717 -Required Width : 0.216 -Type : High Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[11] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +--------------------------------------------------------------------------------+ @@ -2813,64 +2813,64 @@ Target : counter[11] +--------------------------------------------------------------------------------+ Data Port : LED[*] Clock Port : CLOCK_50 -Rise : 8.682 -Fall : 8.416 +Rise : 10.470 +Fall : 10.183 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[0] Clock Port : CLOCK_50 -Rise : 6.626 -Fall : 6.525 +Rise : 8.036 +Fall : 8.004 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[1] Clock Port : CLOCK_50 -Rise : 6.680 -Fall : 6.629 +Rise : 7.982 +Fall : 7.929 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[2] Clock Port : CLOCK_50 -Rise : 7.094 -Fall : 7.015 +Rise : 8.151 +Fall : 8.115 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[3] Clock Port : CLOCK_50 -Rise : 6.726 -Fall : 6.609 +Rise : 7.654 +Fall : 7.638 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[4] Clock Port : CLOCK_50 -Rise : 7.077 -Fall : 7.019 +Rise : 7.866 +Fall : 7.844 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[5] Clock Port : CLOCK_50 -Rise : 8.550 -Fall : 8.235 +Rise : 10.470 +Fall : 10.183 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[6] Clock Port : CLOCK_50 -Rise : 7.046 -Fall : 6.990 +Rise : 8.654 +Fall : 8.642 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[7] Clock Port : CLOCK_50 -Rise : 8.682 -Fall : 8.416 +Rise : 9.306 +Fall : 9.035 Clock Edge : Rise Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ @@ -2882,64 +2882,64 @@ Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ Data Port : LED[*] Clock Port : CLOCK_50 -Rise : 6.415 -Fall : 6.314 +Rise : 6.669 +Fall : 6.608 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[0] Clock Port : CLOCK_50 -Rise : 6.415 -Fall : 6.314 +Rise : 7.397 +Fall : 7.346 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[1] Clock Port : CLOCK_50 -Rise : 6.467 -Fall : 6.414 +Rise : 7.524 +Fall : 7.491 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[2] Clock Port : CLOCK_50 -Rise : 6.865 -Fall : 6.785 +Rise : 7.479 +Fall : 7.390 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[3] Clock Port : CLOCK_50 -Rise : 6.512 -Fall : 6.396 +Rise : 6.669 +Fall : 6.608 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[4] Clock Port : CLOCK_50 -Rise : 6.852 -Fall : 6.792 +Rise : 7.067 +Fall : 7.031 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[5] Clock Port : CLOCK_50 -Rise : 8.342 -Fall : 8.024 +Rise : 9.908 +Fall : 9.604 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[6] Clock Port : CLOCK_50 -Rise : 6.817 -Fall : 6.759 +Rise : 7.824 +Fall : 7.751 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[7] Clock Port : CLOCK_50 -Rise : 8.468 -Fall : 8.198 +Rise : 8.799 +Fall : 8.511 Clock Edge : Rise Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ @@ -2955,7 +2955,7 @@ No synchronizer chains to report. +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Fmax Summary ; +--------------------------------------------------------------------------------+ -Fmax : 300.21 MHz +Fmax : 395.73 MHz Restricted Fmax : 250.0 MHz Clock Name : CLOCK_50 Note : limit due to minimum period restriction (max I/O toggle rate) @@ -2968,8 +2968,8 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp ; Slow 1200mV 0C Model Setup Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 -Slack : -2.331 -End Point TNS : -34.994 +Slack : -1.527 +End Point TNS : -72.611 +--------------------------------------------------------------------------------+ @@ -2978,7 +2978,7 @@ End Point TNS : -34.994 ; Slow 1200mV 0C Model Hold Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 -Slack : 0.299 +Slack : 0.255 End Point TNS : 0.000 +--------------------------------------------------------------------------------+ @@ -3001,7 +3001,7 @@ No paths to report. +--------------------------------------------------------------------------------+ Clock : CLOCK_50 Slack : -3.000 -End Point TNS : -46.624 +End Point TNS : -110.824 +--------------------------------------------------------------------------------+ @@ -3009,905 +3009,905 @@ End Point TNS : -46.624 +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Setup: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ -Slack : -2.331 -From Node : counter[1] -To Node : address[2] +Slack : -1.527 +From Node : counter[14] +To Node : address[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 3.586 +Clock Skew : -0.056 +Data Delay : 2.466 -Slack : -2.266 -From Node : counter[1] -To Node : address[1] +Slack : -1.527 +From Node : counter[14] +To Node : address[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 3.521 +Clock Skew : -0.056 +Data Delay : 2.466 -Slack : -2.266 -From Node : counter[0] -To Node : address[2] +Slack : -1.527 +From Node : counter[14] +To Node : address[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 3.521 +Clock Skew : -0.056 +Data Delay : 2.466 -Slack : -2.235 -From Node : counter[5] -To Node : address[2] +Slack : -1.527 +From Node : counter[14] +To Node : address[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 3.490 +Clock Skew : -0.056 +Data Delay : 2.466 -Slack : -2.223 -From Node : counter[3] -To Node : address[2] +Slack : -1.527 +From Node : counter[14] +To Node : address[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 3.478 +Clock Skew : -0.056 +Data Delay : 2.466 -Slack : -2.201 -From Node : counter[0] -To Node : address[1] +Slack : -1.527 +From Node : counter[14] +To Node : address[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 3.456 +Clock Skew : -0.056 +Data Delay : 2.466 -Slack : -2.167 -From Node : counter[4] -To Node : address[2] +Slack : -1.527 +From Node : counter[14] +To Node : address[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 3.422 +Clock Skew : -0.056 +Data Delay : 2.466 -Slack : -2.153 -From Node : counter[2] -To Node : address[2] +Slack : -1.527 +From Node : counter[14] +To Node : address[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 3.408 +Clock Skew : -0.056 +Data Delay : 2.466 -Slack : -2.134 -From Node : counter[7] -To Node : address[2] +Slack : -1.527 +From Node : counter[14] +To Node : address[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 3.389 +Clock Skew : -0.056 +Data Delay : 2.466 -Slack : -2.133 -From Node : counter[5] -To Node : address[1] +Slack : -1.527 +From Node : counter[14] +To Node : address[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 3.388 +Clock Skew : -0.056 +Data Delay : 2.466 -Slack : -2.121 -From Node : counter[3] -To Node : address[1] +Slack : -1.527 +From Node : counter[14] +To Node : address[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 3.376 +Clock Skew : -0.056 +Data Delay : 2.466 -Slack : -2.066 -From Node : counter[6] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 3.321 - -Slack : -2.065 -From Node : counter[4] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 3.320 - -Slack : -2.051 -From Node : counter[2] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 3.306 - -Slack : -2.050 -From Node : counter[1] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 3.305 - -Slack : -2.032 -From Node : counter[7] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 3.287 - -Slack : -1.985 -From Node : counter[0] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 3.240 - -Slack : -1.964 -From Node : counter[6] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 3.219 - -Slack : -1.936 -From Node : counter[5] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 3.191 - -Slack : -1.932 -From Node : counter[11] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 3.187 - -Slack : -1.924 -From Node : counter[3] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 3.179 - -Slack : -1.917 -From Node : counter[9] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 3.172 - -Slack : -1.868 -From Node : counter[4] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 3.123 - -Slack : -1.854 -From Node : counter[2] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 3.109 - -Slack : -1.851 -From Node : counter[8] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 3.106 - -Slack : -1.835 -From Node : counter[7] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 3.090 - -Slack : -1.832 -From Node : counter[13] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 3.087 - -Slack : -1.767 -From Node : counter[6] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 3.022 - -Slack : -1.763 -From Node : counter[12] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 3.018 - -Slack : -1.750 -From Node : counter[10] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 3.005 - -Slack : -1.733 -From Node : counter[15] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 2.988 - -Slack : -1.682 -From Node : counter[8] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 2.937 - -Slack : -1.670 +Slack : -1.527 From Node : counter[14] To Node : address[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 2.925 +Clock Skew : -0.056 +Data Delay : 2.466 -Slack : -1.659 -From Node : counter[11] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 2.914 - -Slack : -1.644 -From Node : counter[9] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 2.899 - -Slack : -1.633 -From Node : counter[11] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 2.888 - -Slack : -1.629 -From Node : counter[17] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 2.884 - -Slack : -1.618 -From Node : counter[9] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 2.873 - -Slack : -1.581 -From Node : counter[10] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 2.836 - -Slack : -1.568 -From Node : counter[16] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 2.823 - -Slack : -1.559 -From Node : counter[13] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 2.814 - -Slack : -1.552 -From Node : counter[8] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 2.807 - -Slack : -1.533 -From Node : counter[13] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 2.788 - -Slack : -1.531 -From Node : counter[12] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 2.786 - -Slack : -1.484 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.069 -Data Delay : 2.353 - -Slack : -1.484 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.069 -Data Delay : 2.353 - -Slack : -1.484 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.069 -Data Delay : 2.353 - -Slack : -1.484 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[4] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.069 -Data Delay : 2.353 - -Slack : -1.484 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[3] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.069 -Data Delay : 2.353 - -Slack : -1.484 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.069 -Data Delay : 2.353 - -Slack : -1.484 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.069 -Data Delay : 2.353 - -Slack : -1.484 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.069 -Data Delay : 2.353 - -Slack : -1.464 -From Node : counter[12] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 2.719 - -Slack : -1.460 -From Node : counter[15] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 2.715 - -Slack : -1.451 -From Node : counter[10] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 2.706 - -Slack : -1.434 -From Node : counter[15] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 2.689 - -Slack : -1.407 +Slack : -1.527 From Node : counter[14] To Node : address[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 2.662 +Clock Skew : -0.056 +Data Delay : 2.466 -Slack : -1.371 -From Node : counter[14] -To Node : address[0] +Slack : -1.520 +From Node : counter[13] +To Node : address[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 2.626 +Clock Skew : -0.056 +Data Delay : 2.459 -Slack : -1.356 -From Node : counter[17] -To Node : address[1] +Slack : -1.520 +From Node : counter[13] +To Node : address[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 2.611 +Clock Skew : -0.056 +Data Delay : 2.459 -Slack : -1.330 -From Node : counter[17] -To Node : address[0] +Slack : -1.520 +From Node : counter[13] +To Node : address[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 2.585 +Clock Skew : -0.056 +Data Delay : 2.459 -Slack : -1.312 -From Node : counter[18] +Slack : -1.520 +From Node : counter[13] +To Node : address[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.459 + +Slack : -1.520 +From Node : counter[13] +To Node : address[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.459 + +Slack : -1.520 +From Node : counter[13] +To Node : address[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.459 + +Slack : -1.520 +From Node : counter[13] +To Node : address[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.459 + +Slack : -1.520 +From Node : counter[13] +To Node : address[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.459 + +Slack : -1.520 +From Node : counter[13] +To Node : address[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.459 + +Slack : -1.520 +From Node : counter[13] +To Node : address[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.459 + +Slack : -1.520 +From Node : counter[13] +To Node : address[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.459 + +Slack : -1.520 +From Node : counter[13] To Node : address[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 2.567 +Clock Skew : -0.056 +Data Delay : 2.459 -Slack : -1.311 -From Node : counter[16] +Slack : -1.520 +From Node : counter[13] To Node : address[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 2.566 +Clock Skew : -0.056 +Data Delay : 2.459 -Slack : -1.289 -From Node : counter[1] -To Node : counter[20] +Slack : -1.484 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.055 -Data Delay : 2.229 +Clock Skew : -0.069 +Data Delay : 2.353 -Slack : -1.269 -From Node : counter[16] -To Node : address[0] +Slack : -1.484 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 2.524 +Clock Skew : -0.069 +Data Delay : 2.353 -Slack : -1.260 -From Node : counter[19] -To Node : address[1] +Slack : -1.484 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 2.515 +Clock Skew : -0.069 +Data Delay : 2.353 -Slack : -1.224 -From Node : counter[0] -To Node : counter[20] +Slack : -1.484 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.055 -Data Delay : 2.164 +Clock Skew : -0.069 +Data Delay : 2.353 -Slack : -1.218 -From Node : counter[19] +Slack : -1.484 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.069 +Data Delay : 2.353 + +Slack : -1.484 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.069 +Data Delay : 2.353 + +Slack : -1.484 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.069 +Data Delay : 2.353 + +Slack : -1.484 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.069 +Data Delay : 2.353 + +Slack : -1.484 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.069 +Data Delay : 2.353 + +Slack : -1.484 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.069 +Data Delay : 2.353 + +Slack : -1.484 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.069 +Data Delay : 2.353 + +Slack : -1.484 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.069 +Data Delay : 2.353 + +Slack : -1.484 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.069 +Data Delay : 2.353 + +Slack : -1.484 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.069 +Data Delay : 2.353 + +Slack : -1.484 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.069 +Data Delay : 2.353 + +Slack : -1.484 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.069 +Data Delay : 2.353 + +Slack : -1.448 +From Node : counter[6] +To Node : address[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.387 + +Slack : -1.448 +From Node : counter[6] +To Node : address[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.387 + +Slack : -1.448 +From Node : counter[6] +To Node : address[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.387 + +Slack : -1.448 +From Node : counter[6] +To Node : address[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.387 + +Slack : -1.448 +From Node : counter[6] +To Node : address[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.387 + +Slack : -1.448 +From Node : counter[6] +To Node : address[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.387 + +Slack : -1.448 +From Node : counter[6] +To Node : address[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.387 + +Slack : -1.448 +From Node : counter[6] +To Node : address[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.387 + +Slack : -1.448 +From Node : counter[6] +To Node : address[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.387 + +Slack : -1.448 +From Node : counter[6] +To Node : address[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.387 + +Slack : -1.448 +From Node : counter[6] +To Node : address[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.387 + +Slack : -1.448 +From Node : counter[6] To Node : address[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 2.473 +Clock Skew : -0.056 +Data Delay : 2.387 -Slack : -1.201 -From Node : counter[5] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.055 -Data Delay : 2.141 - -Slack : -1.194 -From Node : counter[18] +Slack : -1.448 +From Node : counter[6] To Node : address[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 2.449 +Clock Skew : -0.056 +Data Delay : 2.387 -Slack : -1.189 -From Node : counter[1] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.055 -Data Delay : 2.129 - -Slack : -1.189 -From Node : counter[3] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.055 -Data Delay : 2.129 - -Slack : -1.186 -From Node : counter[0] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.055 -Data Delay : 2.126 - -Slack : -1.171 -From Node : counter[1] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.055 -Data Delay : 2.111 - -Slack : -1.133 -From Node : counter[4] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.055 -Data Delay : 2.073 - -Slack : -1.124 -From Node : counter[0] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.055 -Data Delay : 2.064 - -Slack : -1.123 -From Node : counter[4] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.055 -Data Delay : 2.063 - -Slack : -1.119 -From Node : counter[2] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.055 -Data Delay : 2.059 - -Slack : -1.101 -From Node : counter[5] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.055 -Data Delay : 2.041 - -Slack : -1.100 +Slack : -1.442 From Node : counter[7] -To Node : counter[20] +To Node : address[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.055 -Data Delay : 2.040 +Clock Skew : -0.056 +Data Delay : 2.381 -Slack : -1.090 -From Node : counter[2] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.055 -Data Delay : 2.030 - -Slack : -1.089 -From Node : counter[1] -To Node : counter[16] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.055 -Data Delay : 2.029 - -Slack : -1.089 -From Node : counter[3] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.055 -Data Delay : 2.029 - -Slack : -1.086 -From Node : counter[0] -To Node : counter[17] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.055 -Data Delay : 2.026 - -Slack : -1.083 -From Node : counter[5] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.055 -Data Delay : 2.023 - -Slack : -1.071 -From Node : counter[3] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.055 -Data Delay : 2.011 - -Slack : -1.071 -From Node : counter[1] -To Node : counter[17] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.055 -Data Delay : 2.011 - -Slack : -1.033 -From Node : counter[4] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.055 -Data Delay : 1.973 - -Slack : -1.032 -From Node : counter[6] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.055 -Data Delay : 1.972 - -Slack : -1.031 -From Node : counter[19] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 2.286 - -Slack : -1.028 -From Node : counter[18] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.260 -Data Delay : 2.283 - -Slack : -1.024 -From Node : counter[0] -To Node : counter[16] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.055 -Data Delay : 1.964 - -Slack : -1.023 -From Node : counter[6] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.055 -Data Delay : 1.963 - -Slack : -1.023 -From Node : counter[4] -To Node : counter[17] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.055 -Data Delay : 1.963 - -Slack : -1.019 -From Node : counter[2] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.055 -Data Delay : 1.959 - -Slack : -1.001 -From Node : counter[5] -To Node : counter[16] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.055 -Data Delay : 1.941 - -Slack : -1.000 +Slack : -1.442 From Node : counter[7] -To Node : counter[18] +To Node : address[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.055 -Data Delay : 1.940 +Clock Skew : -0.056 +Data Delay : 2.381 -Slack : -0.990 -From Node : counter[2] -To Node : counter[17] +Slack : -1.442 +From Node : counter[7] +To Node : address[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.055 -Data Delay : 1.930 +Clock Skew : -0.056 +Data Delay : 2.381 -Slack : -0.989 +Slack : -1.442 +From Node : counter[7] +To Node : address[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.381 + +Slack : -1.442 +From Node : counter[7] +To Node : address[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.381 + +Slack : -1.442 +From Node : counter[7] +To Node : address[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.381 + +Slack : -1.442 +From Node : counter[7] +To Node : address[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.381 + +Slack : -1.442 +From Node : counter[7] +To Node : address[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.381 + +Slack : -1.442 +From Node : counter[7] +To Node : address[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.381 + +Slack : -1.442 +From Node : counter[7] +To Node : address[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.381 + +Slack : -1.442 +From Node : counter[7] +To Node : address[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.381 + +Slack : -1.442 +From Node : counter[7] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.381 + +Slack : -1.442 +From Node : counter[7] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.381 + +Slack : -1.431 From Node : counter[1] -To Node : counter[14] +To Node : address[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.055 -Data Delay : 1.929 +Clock Skew : -0.056 +Data Delay : 2.370 -Slack : -0.989 -From Node : counter[3] -To Node : counter[16] +Slack : -1.431 +From Node : counter[1] +To Node : address[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.055 -Data Delay : 1.929 +Clock Skew : -0.056 +Data Delay : 2.370 -Slack : -0.986 +Slack : -1.431 +From Node : counter[1] +To Node : address[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.370 + +Slack : -1.431 +From Node : counter[1] +To Node : address[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.370 + +Slack : -1.431 +From Node : counter[1] +To Node : address[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.370 + +Slack : -1.431 +From Node : counter[1] +To Node : address[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.370 + +Slack : -1.431 +From Node : counter[1] +To Node : address[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.370 + +Slack : -1.431 +From Node : counter[1] +To Node : address[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.370 + +Slack : -1.431 +From Node : counter[1] +To Node : address[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.370 + +Slack : -1.431 +From Node : counter[1] +To Node : address[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.370 + +Slack : -1.431 +From Node : counter[1] +To Node : address[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.370 + +Slack : -1.431 +From Node : counter[1] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.370 + +Slack : -1.431 +From Node : counter[1] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.370 + +Slack : -1.425 From Node : counter[0] -To Node : counter[15] +To Node : address[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.055 -Data Delay : 1.926 +Clock Skew : -0.056 +Data Delay : 2.364 + +Slack : -1.425 +From Node : counter[0] +To Node : address[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.364 + +Slack : -1.425 +From Node : counter[0] +To Node : address[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.364 + +Slack : -1.425 +From Node : counter[0] +To Node : address[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.364 + +Slack : -1.425 +From Node : counter[0] +To Node : address[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.364 + +Slack : -1.425 +From Node : counter[0] +To Node : address[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.364 + +Slack : -1.425 +From Node : counter[0] +To Node : address[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.364 + +Slack : -1.425 +From Node : counter[0] +To Node : address[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.364 + +Slack : -1.425 +From Node : counter[0] +To Node : address[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.364 + +Slack : -1.425 +From Node : counter[0] +To Node : address[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.364 + +Slack : -1.425 +From Node : counter[0] +To Node : address[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.364 + +Slack : -1.425 +From Node : counter[0] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.364 + +Slack : -1.425 +From Node : counter[0] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.364 + +Slack : -1.423 +From Node : counter[5] +To Node : address[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.362 + +Slack : -1.423 +From Node : counter[5] +To Node : address[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.362 + +Slack : -1.423 +From Node : counter[5] +To Node : address[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.362 + +Slack : -1.423 +From Node : counter[5] +To Node : address[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.362 + +Slack : -1.423 +From Node : counter[5] +To Node : address[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.362 + +Slack : -1.423 +From Node : counter[5] +To Node : address[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.056 +Data Delay : 2.362 +--------------------------------------------------------------------------------+ @@ -3915,905 +3915,905 @@ Data Delay : 1.926 +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Hold: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ -Slack : 0.299 -From Node : address[2] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.511 - -Slack : 0.299 +Slack : 0.255 From Node : address[1] -To Node : address[1] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.511 +Clock Skew : 0.337 +Data Delay : 0.761 -Slack : 0.299 +Slack : 0.255 +From Node : address[1] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.337 +Data Delay : 0.761 + +Slack : 0.261 +From Node : address[4] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.337 +Data Delay : 0.767 + +Slack : 0.300 From Node : address[0] To Node : address[0] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.068 +Clock Skew : 0.067 Data Delay : 0.511 -Slack : 0.330 -From Node : counter[20] -To Node : counter[20] +Slack : 0.312 +From Node : address[2] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.529 +Clock Skew : 0.337 +Data Delay : 0.818 -Slack : 0.491 -From Node : counter[9] -To Node : counter[9] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.690 - -Slack : 0.495 -From Node : counter[10] -To Node : counter[10] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.694 - -Slack : 0.496 -From Node : counter[8] -To Node : counter[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.695 - -Slack : 0.496 -From Node : counter[3] -To Node : counter[3] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.695 - -Slack : 0.496 -From Node : counter[1] -To Node : counter[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.695 - -Slack : 0.498 -From Node : counter[2] -To Node : counter[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.697 - -Slack : 0.509 +Slack : 0.319 From Node : counter[0] To Node : counter[0] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.708 +Clock Skew : 0.056 +Data Delay : 0.519 -Slack : 0.618 -From Node : counter[5] -To Node : counter[5] +Slack : 0.329 +From Node : address[5] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.337 +Data Delay : 0.835 + +Slack : 0.334 +From Node : address[7] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.337 +Data Delay : 0.840 + +Slack : 0.335 +From Node : address[11] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.337 +Data Delay : 0.841 + +Slack : 0.335 +From Node : counter[21] +To Node : counter[21] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 0.547 + +Slack : 0.341 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|out_address_reg_a[0] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 0.817 +Data Delay : 0.540 -Slack : 0.622 -From Node : counter[12] -To Node : counter[12] +Slack : 0.344 +From Node : address[12] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.337 +Data Delay : 0.850 + +Slack : 0.346 +From Node : address[8] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.337 +Data Delay : 0.852 + +Slack : 0.353 +From Node : address[6] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.337 +Data Delay : 0.859 + +Slack : 0.354 +From Node : address[3] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.337 +Data Delay : 0.860 + +Slack : 0.357 +From Node : address[9] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.337 +Data Delay : 0.863 + +Slack : 0.365 +From Node : address[13] +To Node : address[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 0.821 +Data Delay : 0.564 -Slack : 0.625 -From Node : counter[17] -To Node : counter[17] +Slack : 0.425 +From Node : counter[19] +To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.824 +Clock Skew : 0.384 +Data Delay : 0.953 -Slack : 0.625 +Slack : 0.432 +From Node : counter[19] +To Node : counter[21] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.384 +Data Delay : 0.960 + +Slack : 0.498 +From Node : counter[10] +To Node : counter[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.698 + +Slack : 0.499 +From Node : address[4] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.337 +Data Delay : 1.005 + +Slack : 0.499 From Node : counter[14] To Node : counter[14] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.824 +Clock Skew : 0.056 +Data Delay : 0.699 -Slack : 0.625 +Slack : 0.499 +From Node : counter[8] +To Node : counter[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.699 + +Slack : 0.499 From Node : counter[6] To Node : counter[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.824 +Clock Skew : 0.056 +Data Delay : 0.699 -Slack : 0.626 -From Node : counter[19] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.825 - -Slack : 0.626 -From Node : counter[18] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.825 - -Slack : 0.626 -From Node : counter[4] -To Node : counter[4] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.825 - -Slack : 0.626 -From Node : address[1] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.838 - -Slack : 0.628 -From Node : counter[15] -To Node : counter[15] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.827 - -Slack : 0.628 -From Node : counter[13] -To Node : counter[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.827 - -Slack : 0.628 -From Node : counter[7] -To Node : counter[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.827 - -Slack : 0.629 +Slack : 0.500 From Node : counter[16] To Node : counter[16] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.828 +Clock Skew : 0.056 +Data Delay : 0.700 -Slack : 0.629 -From Node : counter[11] -To Node : counter[11] +Slack : 0.500 +From Node : counter[12] +To Node : counter[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.828 +Clock Skew : 0.056 +Data Delay : 0.700 -Slack : 0.735 -From Node : counter[9] -To Node : counter[10] +Slack : 0.502 +From Node : counter[17] +To Node : counter[17] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.934 +Clock Skew : 0.056 +Data Delay : 0.702 -Slack : 0.741 -From Node : counter[1] -To Node : counter[2] +Slack : 0.502 +From Node : counter[13] +To Node : counter[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.940 +Clock Skew : 0.056 +Data Delay : 0.702 -Slack : 0.741 -From Node : counter[3] +Slack : 0.502 +From Node : counter[7] +To Node : counter[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.702 + +Slack : 0.502 +From Node : counter[4] To Node : counter[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.940 +Clock Skew : 0.056 +Data Delay : 0.702 -Slack : 0.743 +Slack : 0.502 +From Node : counter[2] +To Node : counter[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.702 + +Slack : 0.502 +From Node : counter[20] +To Node : counter[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 0.714 + +Slack : 0.503 +From Node : counter[18] +To Node : counter[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.703 + +Slack : 0.503 +From Node : counter[9] +To Node : counter[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.703 + +Slack : 0.504 +From Node : counter[19] +To Node : counter[19] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.704 + +Slack : 0.504 +From Node : counter[15] +To Node : counter[15] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.704 + +Slack : 0.504 +From Node : counter[3] +To Node : counter[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.704 + +Slack : 0.509 +From Node : counter[18] +To Node : counter[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.384 +Data Delay : 1.037 + +Slack : 0.511 +From Node : address[4] +To Node : address[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.710 + +Slack : 0.512 +From Node : address[12] +To Node : address[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.711 + +Slack : 0.512 +From Node : address[6] +To Node : address[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.711 + +Slack : 0.512 +From Node : address[2] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.711 + +Slack : 0.513 +From Node : address[7] +To Node : address[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.712 + +Slack : 0.513 From Node : counter[0] To Node : counter[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.942 +Clock Skew : 0.056 +Data Delay : 0.713 -Slack : 0.744 -From Node : counter[10] -To Node : counter[11] +Slack : 0.514 +From Node : address[7] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.343 +Data Delay : 1.026 + +Slack : 0.515 +From Node : address[10] +To Node : address[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 0.943 +Data Delay : 0.714 -Slack : 0.745 -From Node : counter[8] -To Node : counter[9] +Slack : 0.515 +From Node : address[8] +To Node : address[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 0.944 +Data Delay : 0.714 -Slack : 0.747 -From Node : counter[2] -To Node : counter[3] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.946 - -Slack : 0.750 -From Node : counter[0] -To Node : counter[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.949 - -Slack : 0.751 -From Node : counter[10] -To Node : counter[12] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.950 - -Slack : 0.752 -From Node : counter[8] -To Node : counter[10] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.951 - -Slack : 0.754 -From Node : counter[2] -To Node : counter[4] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.953 - -Slack : 0.790 -From Node : counter[20] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.383 -Data Delay : 1.317 - -Slack : 0.804 -From Node : address[0] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 1.016 - -Slack : 0.824 -From Node : counter[9] -To Node : counter[11] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.023 - -Slack : 0.830 -From Node : counter[3] +Slack : 0.515 +From Node : counter[5] To Node : counter[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.029 +Clock Skew : 0.056 +Data Delay : 0.715 -Slack : 0.830 +Slack : 0.515 From Node : counter[1] -To Node : counter[3] +To Node : counter[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.029 +Clock Skew : 0.056 +Data Delay : 0.715 -Slack : 0.831 -From Node : counter[9] -To Node : counter[12] +Slack : 0.516 +From Node : address[5] +To Node : address[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 1.030 +Data Delay : 0.715 -Slack : 0.837 -From Node : counter[3] -To Node : counter[6] +Slack : 0.516 +From Node : counter[18] +To Node : counter[21] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.036 +Clock Skew : 0.384 +Data Delay : 1.044 -Slack : 0.837 -From Node : counter[1] -To Node : counter[4] +Slack : 0.517 +From Node : address[11] +To Node : address[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 1.036 +Data Delay : 0.716 -Slack : 0.839 -From Node : counter[0] -To Node : counter[3] +Slack : 0.517 +From Node : address[9] +To Node : address[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 +Data Delay : 0.716 + +Slack : 0.518 +From Node : address[4] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.351 Data Delay : 1.038 -Slack : 0.840 -From Node : counter[10] -To Node : counter[13] +Slack : 0.519 +From Node : counter[17] +To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.039 - -Slack : 0.841 -From Node : counter[8] -To Node : counter[11] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.040 - -Slack : 0.843 -From Node : counter[2] -To Node : counter[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.042 - -Slack : 0.846 -From Node : counter[0] -To Node : counter[4] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.045 - -Slack : 0.847 -From Node : counter[10] -To Node : counter[14] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.046 - -Slack : 0.848 -From Node : counter[8] -To Node : counter[12] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 +Clock Skew : 0.384 Data Delay : 1.047 -Slack : 0.850 -From Node : counter[2] -To Node : counter[6] +Slack : 0.522 +From Node : address[4] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.049 +Clock Skew : 0.337 +Data Delay : 1.028 -Slack : 0.863 -From Node : counter[5] -To Node : counter[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.062 - -Slack : 0.869 -From Node : counter[17] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.068 - -Slack : 0.870 -From Node : counter[19] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.069 - -Slack : 0.871 -From Node : counter[12] -To Node : counter[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.070 - -Slack : 0.873 -From Node : counter[7] -To Node : counter[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.072 - -Slack : 0.873 -From Node : counter[15] -To Node : counter[16] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.072 - -Slack : 0.873 -From Node : counter[13] -To Node : counter[14] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.072 - -Slack : 0.874 -From Node : counter[14] -To Node : counter[15] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.073 - -Slack : 0.874 -From Node : counter[6] -To Node : counter[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.073 - -Slack : 0.874 -From Node : counter[11] -To Node : counter[12] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.073 - -Slack : 0.875 -From Node : counter[18] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.074 - -Slack : 0.875 -From Node : counter[4] -To Node : counter[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.074 - -Slack : 0.878 -From Node : counter[16] -To Node : counter[17] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.077 - -Slack : 0.878 -From Node : counter[12] -To Node : counter[14] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.077 - -Slack : 0.881 -From Node : counter[6] -To Node : counter[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.080 - -Slack : 0.881 -From Node : counter[14] -To Node : counter[16] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.080 - -Slack : 0.882 -From Node : counter[4] -To Node : counter[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.081 - -Slack : 0.882 -From Node : counter[18] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.081 - -Slack : 0.885 -From Node : counter[16] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.084 - -Slack : 0.920 -From Node : counter[9] -To Node : counter[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.119 - -Slack : 0.926 -From Node : counter[1] -To Node : counter[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.125 - -Slack : 0.926 -From Node : counter[3] -To Node : counter[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.125 - -Slack : 0.927 -From Node : counter[9] -To Node : counter[14] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.126 - -Slack : 0.933 -From Node : counter[1] -To Node : counter[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.132 - -Slack : 0.933 -From Node : counter[3] -To Node : counter[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.132 - -Slack : 0.935 -From Node : counter[0] -To Node : counter[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.134 - -Slack : 0.936 -From Node : counter[10] -To Node : counter[15] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.135 - -Slack : 0.937 -From Node : counter[8] -To Node : counter[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.136 - -Slack : 0.939 -From Node : counter[2] -To Node : counter[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.138 - -Slack : 0.942 -From Node : counter[0] -To Node : counter[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.141 - -Slack : 0.943 -From Node : counter[10] -To Node : counter[16] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.142 - -Slack : 0.944 -From Node : counter[8] -To Node : counter[14] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.143 - -Slack : 0.946 -From Node : counter[2] -To Node : counter[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.145 - -Slack : 0.952 -From Node : counter[5] -To Node : counter[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.151 - -Slack : 0.953 -From Node : counter[20] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.383 -Data Delay : 1.480 - -Slack : 0.954 -From Node : counter[17] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.153 - -Slack : 0.957 -From Node : counter[19] +Slack : 0.524 +From Node : address[1] To Node : address[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.383 -Data Delay : 1.484 +Clock Skew : 0.055 +Data Delay : 0.723 -Slack : 0.958 -From Node : counter[11] -To Node : counter[13] +Slack : 0.525 +From Node : address[11] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.157 +Clock Skew : 0.343 +Data Delay : 1.037 -Slack : 0.958 -From Node : counter[13] -To Node : counter[15] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.157 - -Slack : 0.959 -From Node : counter[15] -To Node : counter[17] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.158 - -Slack : 0.959 -From Node : counter[5] -To Node : counter[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.158 - -Slack : 0.960 -From Node : counter[7] -To Node : counter[9] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.159 - -Slack : 0.965 +Slack : 0.526 From Node : counter[17] +To Node : counter[21] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.384 +Data Delay : 1.054 + +Slack : 0.527 +From Node : address[13] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.726 + +Slack : 0.527 +From Node : address[1] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.351 +Data Delay : 1.047 + +Slack : 0.532 +From Node : address[3] +To Node : address[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.731 + +Slack : 0.537 +From Node : address[4] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.351 +Data Delay : 1.057 + +Slack : 0.541 +From Node : address[1] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.337 +Data Delay : 1.047 + +Slack : 0.542 +From Node : address[12] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.343 +Data Delay : 1.054 + +Slack : 0.544 +From Node : address[4] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.343 +Data Delay : 1.056 + +Slack : 0.544 +From Node : address[10] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.343 +Data Delay : 1.056 + +Slack : 0.554 +From Node : address[3] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.343 +Data Delay : 1.066 + +Slack : 0.558 +From Node : address[9] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.343 +Data Delay : 1.070 + +Slack : 0.559 +From Node : address[6] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.343 +Data Delay : 1.071 + +Slack : 0.567 +From Node : address[5] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.337 +Data Delay : 1.073 + +Slack : 0.570 +From Node : address[10] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.351 +Data Delay : 1.090 + +Slack : 0.581 +From Node : address[2] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.351 +Data Delay : 1.101 + +Slack : 0.592 +From Node : address[2] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.351 +Data Delay : 1.112 + +Slack : 0.596 +From Node : address[8] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.351 +Data Delay : 1.116 + +Slack : 0.597 +From Node : address[8] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.351 +Data Delay : 1.117 + +Slack : 0.598 +From Node : address[10] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.337 +Data Delay : 1.104 + +Slack : 0.601 +From Node : counter[16] To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.164 +Clock Skew : 0.384 +Data Delay : 1.129 -Slack : 0.967 -From Node : counter[12] +Slack : 0.602 +From Node : address[2] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.351 +Data Delay : 1.122 + +Slack : 0.602 +From Node : address[9] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.351 +Data Delay : 1.122 + +Slack : 0.603 +From Node : address[10] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.337 +Data Delay : 1.109 + +Slack : 0.607 +From Node : address[5] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.337 +Data Delay : 1.113 + +Slack : 0.607 +From Node : address[9] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.337 +Data Delay : 1.113 + +Slack : 0.608 +From Node : address[5] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.351 +Data Delay : 1.128 + +Slack : 0.608 +From Node : counter[16] +To Node : counter[21] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.384 +Data Delay : 1.136 + +Slack : 0.615 +From Node : address[3] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.337 +Data Delay : 1.121 + +Slack : 0.616 +From Node : address[3] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.351 +Data Delay : 1.136 + +Slack : 0.617 +From Node : counter[15] +To Node : counter[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.384 +Data Delay : 1.145 + +Slack : 0.624 +From Node : counter[15] +To Node : counter[21] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.384 +Data Delay : 1.152 + +Slack : 0.628 +From Node : address[3] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.351 +Data Delay : 1.148 + +Slack : 0.633 +From Node : address[2] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.337 +Data Delay : 1.139 + +Slack : 0.635 +From Node : address[9] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.337 +Data Delay : 1.141 + +Slack : 0.638 +From Node : address[9] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.351 +Data Delay : 1.158 + +Slack : 0.696 +From Node : counter[14] +To Node : counter[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.384 +Data Delay : 1.224 + +Slack : 0.703 +From Node : counter[14] +To Node : counter[21] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.384 +Data Delay : 1.231 + +Slack : 0.711 +From Node : counter[13] +To Node : counter[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.384 +Data Delay : 1.239 + +Slack : 0.718 +From Node : counter[13] +To Node : counter[21] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.384 +Data Delay : 1.246 + +Slack : 0.743 +From Node : counter[6] +To Node : counter[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.943 + +Slack : 0.743 +From Node : counter[8] +To Node : counter[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.056 +Data Delay : 0.943 + +Slack : 0.743 +From Node : counter[14] To Node : counter[15] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.166 - -Slack : 0.969 -From Node : counter[7] -To Node : counter[10] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.168 - -Slack : 0.969 -From Node : counter[15] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.168 - -Slack : 0.969 -From Node : counter[13] -To Node : counter[16] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.168 - -Slack : 0.970 -From Node : counter[11] -To Node : counter[14] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 1.169 +Clock Skew : 0.056 +Data Delay : 0.943 +--------------------------------------------------------------------------------+ @@ -4835,7 +4835,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[0] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 Slack : -2.174 Actual Width : 1.000 @@ -4843,7 +4843,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[1] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 Slack : -2.174 Actual Width : 1.000 @@ -4851,7 +4851,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[2] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 Slack : -2.174 Actual Width : 1.000 @@ -4859,7 +4859,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[3] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 Slack : -2.174 Actual Width : 1.000 @@ -4867,7 +4867,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[4] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 Slack : -2.174 Actual Width : 1.000 @@ -4875,7 +4875,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[5] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 Slack : -2.174 Actual Width : 1.000 @@ -4883,7 +4883,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[6] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 Slack : -2.174 Actual Width : 1.000 @@ -4891,7 +4891,7 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[7] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 Slack : -2.174 Actual Width : 1.000 @@ -4899,7 +4899,191 @@ Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0 Slack : -1.000 Actual Width : 1.000 @@ -4909,6 +5093,38 @@ Clock : CLOCK_50 Clock Edge : Rise Target : address[0] +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : address[10] + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : address[11] + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : address[12] + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : address[13] + Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 @@ -4925,6 +5141,62 @@ Clock : CLOCK_50 Clock Edge : Rise Target : address[2] +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : address[3] + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : address[4] + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : address[5] + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : address[6] + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : address[7] + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : address[8] + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : address[9] + Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 @@ -5029,6 +5301,14 @@ Clock : CLOCK_50 Clock Edge : Rise Target : counter[20] +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[21] + Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 @@ -5093,13 +5373,181 @@ Clock : CLOCK_50 Clock Edge : Rise Target : counter[9] +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0] + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|out_address_reg_a[0] + +Slack : -0.011 +Actual Width : 0.219 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 + +Slack : -0.011 +Actual Width : 0.219 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 + +Slack : -0.011 +Actual Width : 0.219 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 + +Slack : -0.011 +Actual Width : 0.219 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0 + Slack : -0.010 Actual Width : 0.220 Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 + +Slack : -0.010 +Actual Width : 0.220 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 + +Slack : -0.010 +Actual Width : 0.220 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 + +Slack : -0.010 +Actual Width : 0.220 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 + +Slack : -0.010 +Actual Width : 0.220 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 + +Slack : -0.010 +Actual Width : 0.220 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 + +Slack : -0.010 +Actual Width : 0.220 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 + +Slack : -0.010 +Actual Width : 0.220 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0 + +Slack : -0.009 +Actual Width : 0.221 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 + +Slack : -0.009 +Actual Width : 0.221 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 + +Slack : -0.009 +Actual Width : 0.221 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0 + +Slack : -0.009 +Actual Width : 0.221 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 + +Slack : -0.007 +Actual Width : 0.223 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 + +Slack : -0.007 +Actual Width : 0.223 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 + +Slack : -0.007 +Actual Width : 0.223 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 + +Slack : -0.007 +Actual Width : 0.223 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 Slack : -0.006 Actual Width : 0.224 @@ -5107,7 +5555,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[0] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 Slack : -0.006 Actual Width : 0.224 @@ -5115,7 +5563,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[1] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 Slack : -0.006 Actual Width : 0.224 @@ -5123,7 +5571,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[2] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 Slack : -0.006 Actual Width : 0.224 @@ -5131,7 +5579,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[3] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 Slack : -0.006 Actual Width : 0.224 @@ -5139,7 +5587,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[4] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 Slack : -0.006 Actual Width : 0.224 @@ -5147,7 +5595,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[5] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 Slack : -0.006 Actual Width : 0.224 @@ -5155,7 +5603,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[6] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 Slack : -0.006 Actual Width : 0.224 @@ -5163,463 +5611,15 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[7] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 -Slack : 0.096 -Actual Width : 0.280 -Required Width : 0.184 +Slack : -0.005 +Actual Width : 0.225 +Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : address[0] - -Slack : 0.096 -Actual Width : 0.280 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : address[1] - -Slack : 0.096 -Actual Width : 0.280 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : address[2] - -Slack : 0.098 -Actual Width : 0.282 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[0] - -Slack : 0.098 -Actual Width : 0.282 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[10] - -Slack : 0.098 -Actual Width : 0.282 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[11] - -Slack : 0.098 -Actual Width : 0.282 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[12] - -Slack : 0.098 -Actual Width : 0.282 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[13] - -Slack : 0.098 -Actual Width : 0.282 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[14] - -Slack : 0.098 -Actual Width : 0.282 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[15] - -Slack : 0.098 -Actual Width : 0.282 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[16] - -Slack : 0.098 -Actual Width : 0.282 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[17] - -Slack : 0.098 -Actual Width : 0.282 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[18] - -Slack : 0.098 -Actual Width : 0.282 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[19] - -Slack : 0.098 -Actual Width : 0.282 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[1] - -Slack : 0.098 -Actual Width : 0.282 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[20] - -Slack : 0.098 -Actual Width : 0.282 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[2] - -Slack : 0.098 -Actual Width : 0.282 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[3] - -Slack : 0.098 -Actual Width : 0.282 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[4] - -Slack : 0.098 -Actual Width : 0.282 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[5] - -Slack : 0.098 -Actual Width : 0.282 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[6] - -Slack : 0.098 -Actual Width : 0.282 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[7] - -Slack : 0.098 -Actual Width : 0.282 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[8] - -Slack : 0.098 -Actual Width : 0.282 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[9] - -Slack : 0.251 -Actual Width : 0.251 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : CLOCK_50~input|o - -Slack : 0.256 -Actual Width : 0.256 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : address[0]|clk - -Slack : 0.256 -Actual Width : 0.256 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : address[1]|clk - -Slack : 0.256 -Actual Width : 0.256 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : address[2]|clk - -Slack : 0.257 -Actual Width : 0.257 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom|altsyncram_component|auto_generated|ram_block1a0|clk0 - -Slack : 0.258 -Actual Width : 0.258 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[0]|clk - -Slack : 0.258 -Actual Width : 0.258 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[10]|clk - -Slack : 0.258 -Actual Width : 0.258 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[11]|clk - -Slack : 0.258 -Actual Width : 0.258 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[12]|clk - -Slack : 0.258 -Actual Width : 0.258 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[13]|clk - -Slack : 0.258 -Actual Width : 0.258 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[14]|clk - -Slack : 0.258 -Actual Width : 0.258 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[15]|clk - -Slack : 0.258 -Actual Width : 0.258 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[16]|clk - -Slack : 0.258 -Actual Width : 0.258 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[17]|clk - -Slack : 0.258 -Actual Width : 0.258 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[18]|clk - -Slack : 0.258 -Actual Width : 0.258 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[19]|clk - -Slack : 0.258 -Actual Width : 0.258 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[1]|clk - -Slack : 0.258 -Actual Width : 0.258 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[20]|clk - -Slack : 0.258 -Actual Width : 0.258 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[2]|clk - -Slack : 0.258 -Actual Width : 0.258 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[3]|clk - -Slack : 0.258 -Actual Width : 0.258 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[4]|clk - -Slack : 0.258 -Actual Width : 0.258 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[5]|clk - -Slack : 0.258 -Actual Width : 0.258 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[6]|clk - -Slack : 0.258 -Actual Width : 0.258 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[7]|clk - -Slack : 0.258 -Actual Width : 0.258 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[8]|clk - -Slack : 0.258 -Actual Width : 0.258 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[9]|clk - -Slack : 0.260 -Actual Width : 0.260 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : CLOCK_50~inputclkctrl|inclk[0] - -Slack : 0.260 -Actual Width : 0.260 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : CLOCK_50~inputclkctrl|outclk - -Slack : 0.500 -Actual Width : 0.500 -Required Width : 0.000 -Type : High Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : CLOCK_50~input|i - -Slack : 0.500 -Actual Width : 0.500 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : CLOCK_50~input|i - -Slack : 0.502 -Actual Width : 0.718 -Required Width : 0.216 -Type : High Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[0] - -Slack : 0.502 -Actual Width : 0.718 -Required Width : 0.216 -Type : High Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[10] - -Slack : 0.502 -Actual Width : 0.718 -Required Width : 0.216 -Type : High Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[11] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 +--------------------------------------------------------------------------------+ @@ -5629,64 +5629,64 @@ Target : counter[11] +--------------------------------------------------------------------------------+ Data Port : LED[*] Clock Port : CLOCK_50 -Rise : 7.790 -Fall : 7.377 +Rise : 9.439 +Fall : 8.980 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[0] Clock Port : CLOCK_50 -Rise : 5.977 -Fall : 5.870 +Rise : 7.273 +Fall : 7.194 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[1] Clock Port : CLOCK_50 -Rise : 6.028 -Fall : 5.911 +Rise : 7.209 +Fall : 7.095 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[2] Clock Port : CLOCK_50 -Rise : 6.408 -Fall : 6.271 +Rise : 7.387 +Fall : 7.257 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[3] Clock Port : CLOCK_50 -Rise : 6.070 -Fall : 5.920 +Rise : 6.922 +Fall : 6.837 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[4] Clock Port : CLOCK_50 -Rise : 6.384 -Fall : 6.235 +Rise : 7.090 +Fall : 6.963 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[5] Clock Port : CLOCK_50 -Rise : 7.673 -Fall : 7.213 +Rise : 9.439 +Fall : 8.980 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[6] Clock Port : CLOCK_50 -Rise : 6.381 -Fall : 6.262 +Rise : 7.889 +Fall : 7.717 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[7] Clock Port : CLOCK_50 -Rise : 7.790 -Fall : 7.377 +Rise : 8.347 +Fall : 7.950 Clock Edge : Rise Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ @@ -5698,64 +5698,64 @@ Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ Data Port : LED[*] Clock Port : CLOCK_50 -Rise : 5.770 -Fall : 5.664 +Rise : 6.027 +Fall : 5.921 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[0] Clock Port : CLOCK_50 -Rise : 5.770 -Fall : 5.664 +Rise : 6.683 +Fall : 6.586 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[1] Clock Port : CLOCK_50 -Rise : 5.819 -Fall : 5.703 +Rise : 6.797 +Fall : 6.677 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[2] Clock Port : CLOCK_50 -Rise : 6.184 -Fall : 6.049 +Rise : 6.758 +Fall : 6.608 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[3] Clock Port : CLOCK_50 -Rise : 5.860 -Fall : 5.712 +Rise : 6.027 +Fall : 5.921 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[4] Clock Port : CLOCK_50 -Rise : 6.162 -Fall : 6.015 +Rise : 6.376 +Fall : 6.259 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[5] Clock Port : CLOCK_50 -Rise : 7.467 -Fall : 7.009 +Rise : 8.947 +Fall : 8.480 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[6] Clock Port : CLOCK_50 -Rise : 6.156 -Fall : 6.039 +Rise : 7.114 +Fall : 6.908 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[7] Clock Port : CLOCK_50 -Rise : 7.580 -Fall : 7.166 +Rise : 7.910 +Fall : 7.506 Clock Edge : Rise Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ @@ -5772,8 +5772,8 @@ No synchronizer chains to report. ; Fast 1200mV 0C Model Setup Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 -Slack : -1.122 -End Point TNS : -9.363 +Slack : -0.529 +End Point TNS : -18.538 +--------------------------------------------------------------------------------+ @@ -5782,7 +5782,7 @@ End Point TNS : -9.363 ; Fast 1200mV 0C Model Hold Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 -Slack : 0.178 +Slack : 0.123 End Point TNS : 0.000 +--------------------------------------------------------------------------------+ @@ -5805,7 +5805,7 @@ No paths to report. +--------------------------------------------------------------------------------+ Clock : CLOCK_50 Slack : -3.000 -End Point TNS : -45.480 +End Point TNS : -93.684 +--------------------------------------------------------------------------------+ @@ -5813,905 +5813,905 @@ End Point TNS : -45.480 +--------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Setup: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ -Slack : -1.122 -From Node : counter[1] -To Node : address[2] +Slack : -0.529 +From Node : counter[14] +To Node : address[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 2.262 +Clock Skew : -0.037 +Data Delay : 1.479 -Slack : -1.072 -From Node : counter[0] -To Node : address[2] +Slack : -0.529 +From Node : counter[14] +To Node : address[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 2.212 +Clock Skew : -0.037 +Data Delay : 1.479 -Slack : -1.064 -From Node : counter[5] -To Node : address[2] +Slack : -0.529 +From Node : counter[14] +To Node : address[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 2.204 +Clock Skew : -0.037 +Data Delay : 1.479 -Slack : -1.059 -From Node : counter[1] -To Node : address[1] +Slack : -0.529 +From Node : counter[14] +To Node : address[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 2.199 +Clock Skew : -0.037 +Data Delay : 1.479 -Slack : -1.054 -From Node : counter[3] -To Node : address[2] +Slack : -0.529 +From Node : counter[14] +To Node : address[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 2.194 +Clock Skew : -0.037 +Data Delay : 1.479 -Slack : -1.014 -From Node : counter[4] -To Node : address[2] +Slack : -0.529 +From Node : counter[14] +To Node : address[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 2.154 +Clock Skew : -0.037 +Data Delay : 1.479 -Slack : -1.009 -From Node : counter[0] -To Node : address[1] +Slack : -0.529 +From Node : counter[14] +To Node : address[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 2.149 +Clock Skew : -0.037 +Data Delay : 1.479 -Slack : -1.006 -From Node : counter[2] -To Node : address[2] +Slack : -0.529 +From Node : counter[14] +To Node : address[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 2.146 +Clock Skew : -0.037 +Data Delay : 1.479 -Slack : -0.996 -From Node : counter[7] -To Node : address[2] +Slack : -0.529 +From Node : counter[14] +To Node : address[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 2.136 +Clock Skew : -0.037 +Data Delay : 1.479 -Slack : -0.946 -From Node : counter[6] -To Node : address[2] +Slack : -0.529 +From Node : counter[14] +To Node : address[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 2.086 +Clock Skew : -0.037 +Data Delay : 1.479 -Slack : -0.938 -From Node : counter[5] -To Node : address[1] +Slack : -0.529 +From Node : counter[14] +To Node : address[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 2.078 +Clock Skew : -0.037 +Data Delay : 1.479 -Slack : -0.928 -From Node : counter[3] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 2.068 - -Slack : -0.927 -From Node : counter[1] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 2.067 - -Slack : -0.894 -From Node : counter[2] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 2.034 - -Slack : -0.888 -From Node : counter[4] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 2.028 - -Slack : -0.877 -From Node : counter[0] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 2.017 - -Slack : -0.870 -From Node : counter[7] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 2.010 - -Slack : -0.869 -From Node : counter[5] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 2.009 - -Slack : -0.859 -From Node : counter[11] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.999 - -Slack : -0.859 -From Node : counter[3] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.999 - -Slack : -0.845 -From Node : counter[9] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.985 - -Slack : -0.820 -From Node : counter[6] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.960 - -Slack : -0.819 -From Node : counter[4] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.959 - -Slack : -0.811 -From Node : counter[2] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.951 - -Slack : -0.801 -From Node : counter[8] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.941 - -Slack : -0.801 -From Node : counter[7] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.941 - -Slack : -0.791 -From Node : counter[13] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.931 - -Slack : -0.751 -From Node : counter[6] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.891 - -Slack : -0.743 -From Node : counter[12] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.883 - -Slack : -0.733 -From Node : counter[10] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.873 - -Slack : -0.723 -From Node : counter[15] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.863 - -Slack : -0.682 -From Node : counter[11] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.822 - -Slack : -0.676 +Slack : -0.529 From Node : counter[14] To Node : address[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.816 +Clock Skew : -0.037 +Data Delay : 1.479 -Slack : -0.668 -From Node : counter[9] +Slack : -0.529 +From Node : counter[14] To Node : address[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.808 +Clock Skew : -0.037 +Data Delay : 1.479 -Slack : -0.664 +Slack : -0.529 +From Node : counter[13] +To Node : address[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.479 + +Slack : -0.529 +From Node : counter[13] +To Node : address[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.479 + +Slack : -0.529 +From Node : counter[13] +To Node : address[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.479 + +Slack : -0.529 +From Node : counter[13] +To Node : address[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.479 + +Slack : -0.529 +From Node : counter[13] +To Node : address[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.479 + +Slack : -0.529 +From Node : counter[13] +To Node : address[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.479 + +Slack : -0.529 +From Node : counter[13] +To Node : address[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.479 + +Slack : -0.529 +From Node : counter[13] +To Node : address[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.479 + +Slack : -0.529 +From Node : counter[13] +To Node : address[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.479 + +Slack : -0.529 +From Node : counter[13] +To Node : address[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.479 + +Slack : -0.529 +From Node : counter[13] +To Node : address[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.479 + +Slack : -0.529 +From Node : counter[13] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.479 + +Slack : -0.529 +From Node : counter[13] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.479 + +Slack : -0.489 +From Node : counter[6] +To Node : address[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.439 + +Slack : -0.489 +From Node : counter[6] +To Node : address[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.439 + +Slack : -0.489 +From Node : counter[6] +To Node : address[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.439 + +Slack : -0.489 +From Node : counter[6] +To Node : address[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.439 + +Slack : -0.489 +From Node : counter[6] +To Node : address[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.439 + +Slack : -0.489 +From Node : counter[6] +To Node : address[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.439 + +Slack : -0.489 +From Node : counter[6] +To Node : address[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.439 + +Slack : -0.489 +From Node : counter[6] +To Node : address[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.439 + +Slack : -0.489 +From Node : counter[6] +To Node : address[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.439 + +Slack : -0.489 +From Node : counter[6] +To Node : address[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.439 + +Slack : -0.489 +From Node : counter[6] +To Node : address[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.439 + +Slack : -0.489 +From Node : counter[6] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.439 + +Slack : -0.489 +From Node : counter[6] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.439 + +Slack : -0.489 +From Node : counter[7] +To Node : address[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.439 + +Slack : -0.489 +From Node : counter[7] +To Node : address[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.439 + +Slack : -0.489 +From Node : counter[7] +To Node : address[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.439 + +Slack : -0.489 +From Node : counter[7] +To Node : address[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.439 + +Slack : -0.489 +From Node : counter[7] +To Node : address[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.439 + +Slack : -0.489 +From Node : counter[7] +To Node : address[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.439 + +Slack : -0.489 +From Node : counter[7] +To Node : address[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.439 + +Slack : -0.489 +From Node : counter[7] +To Node : address[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.439 + +Slack : -0.489 +From Node : counter[7] +To Node : address[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.439 + +Slack : -0.489 +From Node : counter[7] +To Node : address[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.439 + +Slack : -0.489 +From Node : counter[7] +To Node : address[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.439 + +Slack : -0.489 +From Node : counter[7] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.439 + +Slack : -0.489 +From Node : counter[7] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.439 + +Slack : -0.486 +From Node : counter[1] +To Node : address[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.436 + +Slack : -0.486 +From Node : counter[1] +To Node : address[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.436 + +Slack : -0.486 +From Node : counter[1] +To Node : address[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.436 + +Slack : -0.486 +From Node : counter[1] +To Node : address[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.436 + +Slack : -0.486 +From Node : counter[1] +To Node : address[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.436 + +Slack : -0.486 +From Node : counter[1] +To Node : address[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.436 + +Slack : -0.486 +From Node : counter[1] +To Node : address[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.436 + +Slack : -0.486 +From Node : counter[1] +To Node : address[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.436 + +Slack : -0.486 +From Node : counter[1] +To Node : address[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.436 + +Slack : -0.486 +From Node : counter[1] +To Node : address[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.436 + +Slack : -0.486 +From Node : counter[1] +To Node : address[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.436 + +Slack : -0.486 +From Node : counter[1] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.436 + +Slack : -0.486 +From Node : counter[1] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.436 + +Slack : -0.486 +From Node : counter[0] +To Node : address[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.436 + +Slack : -0.486 +From Node : counter[0] +To Node : address[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.436 + +Slack : -0.486 +From Node : counter[0] +To Node : address[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.436 + +Slack : -0.486 +From Node : counter[0] +To Node : address[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.436 + +Slack : -0.486 +From Node : counter[0] +To Node : address[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.436 + +Slack : -0.486 +From Node : counter[0] +To Node : address[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.436 + +Slack : -0.486 +From Node : counter[0] +To Node : address[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.436 + +Slack : -0.486 +From Node : counter[0] +To Node : address[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.436 + +Slack : -0.486 +From Node : counter[0] +To Node : address[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.436 + +Slack : -0.486 +From Node : counter[0] +To Node : address[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.436 + +Slack : -0.486 +From Node : counter[0] +To Node : address[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.436 + +Slack : -0.486 +From Node : counter[0] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.436 + +Slack : -0.486 +From Node : counter[0] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.436 + +Slack : -0.479 +From Node : counter[5] +To Node : address[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.429 + +Slack : -0.479 +From Node : counter[5] +To Node : address[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.429 + +Slack : -0.479 +From Node : counter[5] +To Node : address[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.429 + +Slack : -0.479 +From Node : counter[5] +To Node : address[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.429 + +Slack : -0.479 +From Node : counter[5] +To Node : address[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.429 + +Slack : -0.479 +From Node : counter[5] +To Node : address[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.429 + +Slack : -0.479 +From Node : counter[5] +To Node : address[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.429 + +Slack : -0.479 +From Node : counter[5] +To Node : address[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.429 + +Slack : -0.479 +From Node : counter[5] +To Node : address[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.429 + +Slack : -0.479 +From Node : counter[5] +To Node : address[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.429 + +Slack : -0.479 +From Node : counter[5] +To Node : address[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.429 + +Slack : -0.479 +From Node : counter[5] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.429 + +Slack : -0.479 +From Node : counter[5] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.429 + +Slack : -0.446 +From Node : address[13] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.122 +Data Delay : 1.577 + +Slack : -0.443 From Node : counter[11] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.804 - -Slack : -0.651 -From Node : counter[17] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.791 - -Slack : -0.650 -From Node : counter[9] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.790 - -Slack : -0.635 -From Node : counter[8] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.775 - -Slack : -0.614 -From Node : counter[13] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.754 - -Slack : -0.610 -From Node : counter[16] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.750 - -Slack : -0.606 -From Node : counter[8] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.746 - -Slack : -0.596 -From Node : counter[13] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.736 - -Slack : -0.567 -From Node : counter[10] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.707 - -Slack : -0.566 -From Node : counter[12] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.706 - -Slack : -0.548 -From Node : counter[12] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.688 - -Slack : -0.546 -From Node : counter[15] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.686 - -Slack : -0.538 -From Node : counter[10] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.678 - -Slack : -0.528 -From Node : counter[15] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.668 - -Slack : -0.499 -From Node : counter[14] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.639 - -Slack : -0.485 -From Node : counter[1] -To Node : counter[20] +To Node : address[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.037 -Data Delay : 1.435 +Data Delay : 1.393 -Slack : -0.481 -From Node : counter[14] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.621 - -Slack : -0.474 -From Node : counter[17] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.614 - -Slack : -0.456 -From Node : counter[17] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.596 - -Slack : -0.435 -From Node : counter[0] -To Node : counter[20] +Slack : -0.443 +From Node : counter[11] +To Node : address[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.037 -Data Delay : 1.385 +Data Delay : 1.393 -Slack : -0.433 -From Node : counter[16] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.573 - -Slack : -0.427 -From Node : counter[5] -To Node : counter[20] +Slack : -0.443 +From Node : counter[11] +To Node : address[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.037 -Data Delay : 1.377 +Data Delay : 1.393 -Slack : -0.426 -From Node : counter[18] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.566 - -Slack : -0.421 -From Node : counter[1] -To Node : counter[19] +Slack : -0.443 +From Node : counter[11] +To Node : address[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.037 -Data Delay : 1.371 +Data Delay : 1.393 -Slack : -0.417 -From Node : counter[1] -To Node : counter[18] +Slack : -0.443 +From Node : counter[11] +To Node : address[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.037 -Data Delay : 1.367 +Data Delay : 1.393 -Slack : -0.417 -From Node : counter[3] -To Node : counter[20] +Slack : -0.443 +From Node : counter[11] +To Node : address[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.037 -Data Delay : 1.367 +Data Delay : 1.393 -Slack : -0.415 -From Node : counter[16] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.555 - -Slack : -0.410 -From Node : counter[19] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.550 - -Slack : -0.407 -From Node : counter[0] -To Node : counter[19] +Slack : -0.443 +From Node : counter[11] +To Node : address[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.037 -Data Delay : 1.357 +Data Delay : 1.393 -Slack : -0.377 -From Node : counter[4] -To Node : counter[20] +Slack : -0.443 +From Node : counter[11] +To Node : address[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.037 -Data Delay : 1.327 - -Slack : -0.369 -From Node : counter[19] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.509 - -Slack : -0.369 -From Node : counter[2] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.319 - -Slack : -0.367 -From Node : counter[0] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.317 - -Slack : -0.363 -From Node : counter[5] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.313 - -Slack : -0.361 -From Node : counter[18] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.501 - -Slack : -0.359 -From Node : counter[7] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.309 - -Slack : -0.359 -From Node : counter[5] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.309 - -Slack : -0.353 -From Node : counter[1] -To Node : counter[17] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.303 - -Slack : -0.353 -From Node : counter[3] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.303 - -Slack : -0.349 -From Node : counter[1] -To Node : counter[16] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.299 - -Slack : -0.349 -From Node : counter[3] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.299 - -Slack : -0.341 -From Node : counter[4] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.291 - -Slack : -0.339 -From Node : counter[2] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.289 - -Slack : -0.339 -From Node : counter[0] -To Node : counter[17] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.289 - -Slack : -0.324 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.047 -Data Delay : 1.232 - -Slack : -0.324 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.047 -Data Delay : 1.232 - -Slack : -0.324 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.047 -Data Delay : 1.232 - -Slack : -0.324 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[4] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.047 -Data Delay : 1.232 - -Slack : -0.324 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[3] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.047 -Data Delay : 1.232 - -Slack : -0.324 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.047 -Data Delay : 1.232 - -Slack : -0.324 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.047 -Data Delay : 1.232 - -Slack : -0.324 -From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 -To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.047 -Data Delay : 1.232 - -Slack : -0.309 -From Node : counter[6] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.259 - -Slack : -0.309 -From Node : counter[4] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.259 - -Slack : -0.301 -From Node : counter[2] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.251 - -Slack : -0.299 -From Node : counter[0] -To Node : counter[16] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.249 - -Slack : -0.295 -From Node : counter[7] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.245 - -Slack : -0.295 -From Node : counter[5] -To Node : counter[17] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.245 - -Slack : -0.291 -From Node : counter[7] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.241 - -Slack : -0.291 -From Node : counter[5] -To Node : counter[16] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.241 - -Slack : -0.286 -From Node : counter[19] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.153 -Data Delay : 1.426 - -Slack : -0.285 -From Node : counter[1] -To Node : counter[15] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.235 - -Slack : -0.285 -From Node : counter[3] -To Node : counter[17] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.235 - -Slack : -0.281 -From Node : counter[1] -To Node : counter[14] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.231 - -Slack : -0.281 -From Node : counter[3] -To Node : counter[16] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.231 - -Slack : -0.273 -From Node : counter[6] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.037 -Data Delay : 1.223 +Data Delay : 1.393 +--------------------------------------------------------------------------------+ @@ -6719,905 +6719,905 @@ Data Delay : 1.223 +--------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Hold: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ -Slack : 0.178 -From Node : address[2] -To Node : address[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.307 - -Slack : 0.178 +Slack : 0.123 From Node : address[1] -To Node : address[1] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.307 +Clock Skew : 0.219 +Data Delay : 0.446 -Slack : 0.178 +Slack : 0.124 +From Node : address[1] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.218 +Data Delay : 0.446 + +Slack : 0.128 +From Node : address[4] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.219 +Data Delay : 0.451 + +Slack : 0.159 +From Node : address[2] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.219 +Data Delay : 0.482 + +Slack : 0.173 +From Node : address[5] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.219 +Data Delay : 0.496 + +Slack : 0.177 +From Node : address[7] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.219 +Data Delay : 0.500 + +Slack : 0.177 +From Node : address[11] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.219 +Data Delay : 0.500 + +Slack : 0.179 From Node : address[0] To Node : address[0] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.045 +Clock Skew : 0.044 Data Delay : 0.307 +Slack : 0.180 +From Node : address[8] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.219 +Data Delay : 0.503 + +Slack : 0.182 +From Node : address[12] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.219 +Data Delay : 0.505 + +Slack : 0.184 +From Node : address[3] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.219 +Data Delay : 0.507 + +Slack : 0.185 +From Node : address[6] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.219 +Data Delay : 0.508 + +Slack : 0.188 +From Node : address[9] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.219 +Data Delay : 0.511 + Slack : 0.193 -From Node : counter[20] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.314 - -Slack : 0.291 -From Node : counter[9] -To Node : counter[9] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.412 - -Slack : 0.293 -From Node : counter[10] -To Node : counter[10] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.414 - -Slack : 0.293 -From Node : counter[8] -To Node : counter[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.414 - -Slack : 0.293 -From Node : counter[3] -To Node : counter[3] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.414 - -Slack : 0.293 -From Node : counter[1] -To Node : counter[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.414 - -Slack : 0.294 -From Node : counter[2] -To Node : counter[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.415 - -Slack : 0.302 From Node : counter[0] To Node : counter[0] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.423 +Data Delay : 0.314 -Slack : 0.359 +Slack : 0.196 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|out_address_reg_a[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.316 + +Slack : 0.197 +From Node : counter[21] +To Node : counter[21] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.044 +Data Delay : 0.325 + +Slack : 0.217 +From Node : address[13] +To Node : address[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.337 + +Slack : 0.261 From Node : counter[19] -To Node : counter[19] +To Node : counter[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.234 +Data Delay : 0.579 + +Slack : 0.264 +From Node : counter[19] +To Node : counter[21] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.234 +Data Delay : 0.582 + +Slack : 0.276 +From Node : address[7] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.223 +Data Delay : 0.603 + +Slack : 0.277 +From Node : address[4] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.218 +Data Delay : 0.599 + +Slack : 0.281 +From Node : address[11] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.223 +Data Delay : 0.608 + +Slack : 0.288 +From Node : address[4] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.219 +Data Delay : 0.611 + +Slack : 0.293 +From Node : address[10] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.223 +Data Delay : 0.620 + +Slack : 0.294 +From Node : address[12] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.223 +Data Delay : 0.621 + +Slack : 0.295 +From Node : counter[10] +To Node : counter[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.480 +Data Delay : 0.416 -Slack : 0.359 -From Node : counter[14] -To Node : counter[14] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.480 - -Slack : 0.359 -From Node : counter[7] -To Node : counter[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.480 - -Slack : 0.360 -From Node : counter[17] -To Node : counter[17] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.481 - -Slack : 0.360 -From Node : counter[6] -To Node : counter[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.481 - -Slack : 0.360 -From Node : counter[5] -To Node : counter[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.481 - -Slack : 0.360 -From Node : counter[4] -To Node : counter[4] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.481 - -Slack : 0.360 +Slack : 0.296 From Node : address[1] -To Node : address[2] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.489 +Clock Skew : 0.219 +Data Delay : 0.619 -Slack : 0.361 -From Node : counter[18] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.482 - -Slack : 0.361 -From Node : counter[16] -To Node : counter[16] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.482 - -Slack : 0.361 -From Node : counter[15] -To Node : counter[15] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.482 - -Slack : 0.361 -From Node : counter[13] -To Node : counter[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.482 - -Slack : 0.361 +Slack : 0.296 From Node : counter[12] To Node : counter[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.482 +Data Delay : 0.417 -Slack : 0.361 -From Node : counter[11] -To Node : counter[11] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.482 - -Slack : 0.440 -From Node : counter[9] -To Node : counter[10] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.561 - -Slack : 0.442 -From Node : counter[20] -To Node : address[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.235 -Data Delay : 0.761 - -Slack : 0.442 -From Node : counter[1] -To Node : counter[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.563 - -Slack : 0.442 -From Node : counter[3] -To Node : counter[4] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.563 - -Slack : 0.451 +Slack : 0.296 From Node : counter[8] +To Node : counter[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.417 + +Slack : 0.297 +From Node : address[13] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.417 + +Slack : 0.297 +From Node : counter[16] +To Node : counter[16] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.418 + +Slack : 0.297 +From Node : counter[14] +To Node : counter[14] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.418 + +Slack : 0.297 +From Node : counter[9] To Node : counter[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.572 +Data Delay : 0.418 -Slack : 0.451 +Slack : 0.297 +From Node : counter[6] +To Node : counter[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.418 + +Slack : 0.297 +From Node : counter[4] +To Node : counter[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.418 + +Slack : 0.298 +From Node : counter[13] +To Node : counter[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.419 + +Slack : 0.298 +From Node : counter[3] +To Node : counter[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.419 + +Slack : 0.298 +From Node : counter[2] +To Node : counter[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.419 + +Slack : 0.299 +From Node : address[4] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.230 +Data Delay : 0.633 + +Slack : 0.299 +From Node : counter[18] +To Node : counter[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.420 + +Slack : 0.299 +From Node : counter[17] +To Node : counter[17] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.420 + +Slack : 0.299 +From Node : counter[15] +To Node : counter[15] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.420 + +Slack : 0.299 +From Node : counter[7] +To Node : counter[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.420 + +Slack : 0.299 +From Node : counter[20] +To Node : counter[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.044 +Data Delay : 0.427 + +Slack : 0.300 +From Node : address[4] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.223 +Data Delay : 0.627 + +Slack : 0.300 +From Node : counter[19] +To Node : counter[19] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.421 + +Slack : 0.301 +From Node : address[6] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.223 +Data Delay : 0.628 + +Slack : 0.303 +From Node : address[9] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.223 +Data Delay : 0.630 + +Slack : 0.304 +From Node : counter[1] +To Node : counter[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.425 + +Slack : 0.305 +From Node : address[4] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.230 +Data Delay : 0.639 + +Slack : 0.305 +From Node : address[12] +To Node : address[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.425 + +Slack : 0.305 +From Node : address[6] +To Node : address[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.425 + +Slack : 0.305 +From Node : address[4] +To Node : address[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.425 + +Slack : 0.305 +From Node : address[2] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.425 + +Slack : 0.305 From Node : counter[0] To Node : counter[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.572 +Data Delay : 0.426 -Slack : 0.451 -From Node : counter[10] -To Node : counter[11] +Slack : 0.306 +From Node : address[1] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.229 +Data Delay : 0.639 + +Slack : 0.306 +From Node : address[8] +To Node : address[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.426 + +Slack : 0.306 +From Node : address[7] +To Node : address[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.036 +Data Delay : 0.426 + +Slack : 0.306 +From Node : counter[5] +To Node : counter[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.572 +Data Delay : 0.427 -Slack : 0.452 -From Node : counter[2] -To Node : counter[3] +Slack : 0.307 +From Node : address[3] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.573 +Clock Skew : 0.223 +Data Delay : 0.634 -Slack : 0.454 -From Node : counter[10] -To Node : counter[12] +Slack : 0.307 +From Node : address[10] +To Node : address[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.575 +Clock Skew : 0.036 +Data Delay : 0.427 -Slack : 0.454 -From Node : counter[8] -To Node : counter[10] +Slack : 0.307 +From Node : address[9] +To Node : address[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.575 +Clock Skew : 0.036 +Data Delay : 0.427 -Slack : 0.454 -From Node : counter[0] -To Node : counter[2] +Slack : 0.307 +From Node : address[5] +To Node : address[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.575 +Clock Skew : 0.036 +Data Delay : 0.427 -Slack : 0.455 -From Node : counter[2] -To Node : counter[4] +Slack : 0.308 +From Node : address[11] +To Node : address[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.576 +Clock Skew : 0.036 +Data Delay : 0.428 -Slack : 0.460 -From Node : address[0] +Slack : 0.311 +From Node : address[1] To Node : address[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.589 +Clock Skew : 0.036 +Data Delay : 0.431 -Slack : 0.503 -From Node : counter[9] -To Node : counter[11] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.624 - -Slack : 0.505 -From Node : counter[3] -To Node : counter[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.626 - -Slack : 0.505 -From Node : counter[1] -To Node : counter[3] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.626 - -Slack : 0.506 -From Node : counter[9] -To Node : counter[12] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.627 - -Slack : 0.508 -From Node : counter[19] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.629 - -Slack : 0.508 -From Node : counter[7] -To Node : counter[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.629 - -Slack : 0.508 -From Node : counter[3] -To Node : counter[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.629 - -Slack : 0.508 -From Node : counter[1] -To Node : counter[4] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.629 - -Slack : 0.509 -From Node : counter[17] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.630 - -Slack : 0.509 -From Node : counter[5] -To Node : counter[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.630 - -Slack : 0.510 -From Node : counter[13] -To Node : counter[14] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.631 - -Slack : 0.510 -From Node : counter[15] -To Node : counter[16] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.631 - -Slack : 0.510 -From Node : counter[11] -To Node : counter[12] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.631 - -Slack : 0.517 -From Node : counter[14] -To Node : counter[15] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.638 - -Slack : 0.517 -From Node : counter[10] -To Node : counter[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.638 - -Slack : 0.517 -From Node : counter[8] -To Node : counter[11] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.638 - -Slack : 0.517 -From Node : counter[0] -To Node : counter[3] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.638 - -Slack : 0.518 -From Node : counter[6] -To Node : counter[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.639 - -Slack : 0.518 -From Node : counter[4] -To Node : counter[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.639 - -Slack : 0.518 -From Node : counter[2] -To Node : counter[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.639 - -Slack : 0.519 -From Node : counter[18] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.640 - -Slack : 0.519 -From Node : counter[16] -To Node : counter[17] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.640 - -Slack : 0.519 -From Node : counter[12] -To Node : counter[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.640 - -Slack : 0.520 -From Node : counter[8] -To Node : counter[12] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.641 - -Slack : 0.520 -From Node : counter[0] -To Node : counter[4] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.641 - -Slack : 0.520 -From Node : counter[10] -To Node : counter[14] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.641 - -Slack : 0.520 -From Node : counter[14] -To Node : counter[16] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.641 - -Slack : 0.521 -From Node : counter[6] -To Node : counter[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.642 - -Slack : 0.521 -From Node : counter[4] -To Node : counter[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.642 - -Slack : 0.521 -From Node : counter[2] -To Node : counter[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.642 - -Slack : 0.522 +Slack : 0.314 From Node : counter[18] To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.643 +Clock Skew : 0.234 +Data Delay : 0.632 -Slack : 0.522 -From Node : counter[16] -To Node : counter[18] +Slack : 0.317 +From Node : counter[18] +To Node : counter[21] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.643 +Clock Skew : 0.234 +Data Delay : 0.635 -Slack : 0.522 -From Node : counter[12] -To Node : counter[14] +Slack : 0.318 +From Node : address[3] +To Node : address[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.643 +Clock Skew : 0.036 +Data Delay : 0.438 -Slack : 0.569 -From Node : counter[20] -To Node : address[2] +Slack : 0.319 +From Node : address[5] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.235 -Data Delay : 0.888 +Clock Skew : 0.219 +Data Delay : 0.642 -Slack : 0.569 -From Node : counter[9] -To Node : counter[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.690 - -Slack : 0.571 -From Node : counter[19] -To Node : address[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.235 -Data Delay : 0.890 - -Slack : 0.571 -From Node : counter[7] -To Node : counter[9] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.692 - -Slack : 0.571 -From Node : counter[3] -To Node : counter[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.692 - -Slack : 0.571 -From Node : counter[1] -To Node : counter[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.692 - -Slack : 0.572 -From Node : counter[17] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.693 - -Slack : 0.572 -From Node : counter[9] -To Node : counter[14] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.693 - -Slack : 0.572 -From Node : counter[5] -To Node : counter[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.693 - -Slack : 0.573 -From Node : counter[13] -To Node : counter[15] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.694 - -Slack : 0.573 -From Node : counter[11] -To Node : counter[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.694 - -Slack : 0.573 -From Node : counter[15] -To Node : counter[17] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.694 - -Slack : 0.574 -From Node : counter[7] -To Node : counter[10] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.695 - -Slack : 0.574 -From Node : counter[3] -To Node : counter[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.695 - -Slack : 0.574 -From Node : counter[1] -To Node : counter[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.695 - -Slack : 0.575 +Slack : 0.326 From Node : counter[17] To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.696 +Clock Skew : 0.234 +Data Delay : 0.644 -Slack : 0.575 -From Node : counter[5] -To Node : counter[8] +Slack : 0.327 +From Node : address[10] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.696 +Clock Skew : 0.230 +Data Delay : 0.661 -Slack : 0.576 -From Node : counter[11] -To Node : counter[14] +Slack : 0.329 +From Node : counter[17] +To Node : counter[21] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.697 +Clock Skew : 0.234 +Data Delay : 0.647 -Slack : 0.576 -From Node : counter[13] -To Node : counter[16] +Slack : 0.334 +From Node : address[10] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.697 +Clock Skew : 0.219 +Data Delay : 0.657 -Slack : 0.576 -From Node : counter[15] -To Node : counter[18] +Slack : 0.338 +From Node : address[10] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.697 +Clock Skew : 0.218 +Data Delay : 0.660 -Slack : 0.583 -From Node : counter[8] -To Node : counter[13] +Slack : 0.340 +From Node : address[9] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.704 +Clock Skew : 0.218 +Data Delay : 0.662 -Slack : 0.583 -From Node : counter[0] -To Node : counter[5] +Slack : 0.341 +From Node : address[3] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.704 +Clock Skew : 0.219 +Data Delay : 0.664 -Slack : 0.583 -From Node : counter[10] -To Node : counter[15] +Slack : 0.342 +From Node : address[5] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.704 +Clock Skew : 0.218 +Data Delay : 0.664 -Slack : 0.583 -From Node : counter[14] -To Node : counter[17] +Slack : 0.342 +From Node : address[2] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.704 +Clock Skew : 0.229 +Data Delay : 0.675 -Slack : 0.584 -From Node : counter[6] -To Node : counter[9] +Slack : 0.344 +From Node : address[8] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.037 +Clock Skew : 0.230 +Data Delay : 0.678 + +Slack : 0.346 +From Node : address[2] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.230 +Data Delay : 0.680 + +Slack : 0.346 +From Node : address[5] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.230 +Data Delay : 0.680 + +Slack : 0.346 +From Node : address[8] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.230 +Data Delay : 0.680 + +Slack : 0.348 +From Node : address[9] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.230 +Data Delay : 0.682 + +Slack : 0.348 +From Node : address[2] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.230 +Data Delay : 0.682 + +Slack : 0.353 +From Node : address[2] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.219 +Data Delay : 0.676 + +Slack : 0.354 +From Node : address[3] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.230 +Data Delay : 0.688 + +Slack : 0.355 +From Node : address[3] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.230 +Data Delay : 0.689 + +Slack : 0.355 +From Node : address[9] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.219 +Data Delay : 0.678 + +Slack : 0.371 +From Node : address[9] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.230 Data Delay : 0.705 -Slack : 0.584 -From Node : counter[4] -To Node : counter[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.705 - -Slack : 0.584 -From Node : counter[2] -To Node : counter[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.705 - -Slack : 0.585 +Slack : 0.378 From Node : counter[16] -To Node : counter[19] +To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.706 +Clock Skew : 0.234 +Data Delay : 0.696 -Slack : 0.585 -From Node : counter[12] -To Node : counter[15] +Slack : 0.381 +From Node : counter[16] +To Node : counter[21] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.706 +Clock Skew : 0.234 +Data Delay : 0.699 + +Slack : 0.392 +From Node : counter[15] +To Node : counter[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.234 +Data Delay : 0.710 + +Slack : 0.395 +From Node : counter[15] +To Node : counter[21] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.234 +Data Delay : 0.713 + +Slack : 0.414 +From Node : address[10] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.219 +Data Delay : 0.737 + +Slack : 0.417 +From Node : address[11] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.218 +Data Delay : 0.739 + +Slack : 0.417 +From Node : address[11] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.223 +Data Delay : 0.744 + +Slack : 0.428 +From Node : address[9] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.223 +Data Delay : 0.755 + +Slack : 0.434 +From Node : address[12] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.223 +Data Delay : 0.761 + +Slack : 0.435 +From Node : address[5] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.230 +Data Delay : 0.769 + +Slack : 0.437 +From Node : address[7] +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.218 +Data Delay : 0.759 +--------------------------------------------------------------------------------+ @@ -7641,6 +7641,38 @@ Clock : CLOCK_50 Clock Edge : Rise Target : address[0] +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : address[10] + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : address[11] + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : address[12] + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : address[13] + Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 @@ -7657,6 +7689,62 @@ Clock : CLOCK_50 Clock Edge : Rise Target : address[2] +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : address[3] + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : address[4] + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : address[5] + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : address[6] + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : address[7] + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : address[8] + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : address[9] + Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 @@ -7761,6 +7849,14 @@ Clock : CLOCK_50 Clock Edge : Rise Target : counter[20] +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[21] + Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 @@ -7831,7 +7927,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[0] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|address_reg_a[0] Slack : -1.000 Actual Width : 1.000 @@ -7839,7 +7935,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[1] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|out_address_reg_a[0] Slack : -1.000 Actual Width : 1.000 @@ -7847,7 +7943,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[2] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0 Slack : -1.000 Actual Width : 1.000 @@ -7855,7 +7951,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[3] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 Slack : -1.000 Actual Width : 1.000 @@ -7863,7 +7959,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[4] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 Slack : -1.000 Actual Width : 1.000 @@ -7871,7 +7967,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[5] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 Slack : -1.000 Actual Width : 1.000 @@ -7879,7 +7975,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[6] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 Slack : -1.000 Actual Width : 1.000 @@ -7887,7 +7983,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[7] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 Slack : -1.000 Actual Width : 1.000 @@ -7895,7 +7991,207 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9 + +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0 Slack : -0.291 Actual Width : -0.061 @@ -7903,7 +8199,111 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0 + +Slack : -0.291 +Actual Width : -0.061 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0 + +Slack : -0.291 +Actual Width : -0.061 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0 + +Slack : -0.291 +Actual Width : -0.061 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0 + +Slack : -0.291 +Actual Width : -0.061 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0 + +Slack : -0.291 +Actual Width : -0.061 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15~porta_address_reg0 + +Slack : -0.291 +Actual Width : -0.061 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1~porta_address_reg0 + +Slack : -0.291 +Actual Width : -0.061 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0 + +Slack : -0.291 +Actual Width : -0.061 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0 + +Slack : -0.291 +Actual Width : -0.061 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0 + +Slack : -0.291 +Actual Width : -0.061 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0 + +Slack : -0.291 +Actual Width : -0.061 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0 + +Slack : -0.291 +Actual Width : -0.061 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0 + +Slack : -0.291 +Actual Width : -0.061 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0 Slack : -0.290 Actual Width : -0.060 @@ -7911,7 +8311,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[0] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0 Slack : -0.290 Actual Width : -0.060 @@ -7919,7 +8319,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[1] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1 Slack : -0.290 Actual Width : -0.060 @@ -7927,7 +8327,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[2] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10 Slack : -0.290 Actual Width : -0.060 @@ -7935,7 +8335,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[3] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11 Slack : -0.290 Actual Width : -0.060 @@ -7943,7 +8343,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[4] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12 Slack : -0.290 Actual Width : -0.060 @@ -7951,7 +8351,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[5] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13 Slack : -0.290 Actual Width : -0.060 @@ -7959,7 +8359,7 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[6] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14 Slack : -0.290 Actual Width : -0.060 @@ -7967,463 +8367,63 @@ Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[7] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15 -Slack : -0.250 -Actual Width : -0.066 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : address[0] - -Slack : -0.250 -Actual Width : -0.066 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : address[1] - -Slack : -0.250 -Actual Width : -0.066 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : address[2] - -Slack : -0.226 -Actual Width : -0.042 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[0] - -Slack : -0.226 -Actual Width : -0.042 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[10] - -Slack : -0.226 -Actual Width : -0.042 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[11] - -Slack : -0.226 -Actual Width : -0.042 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[12] - -Slack : -0.226 -Actual Width : -0.042 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[13] - -Slack : -0.226 -Actual Width : -0.042 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[14] - -Slack : -0.226 -Actual Width : -0.042 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[15] - -Slack : -0.226 -Actual Width : -0.042 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[16] - -Slack : -0.226 -Actual Width : -0.042 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[17] - -Slack : -0.226 -Actual Width : -0.042 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[18] - -Slack : -0.226 -Actual Width : -0.042 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[19] - -Slack : -0.226 -Actual Width : -0.042 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[1] - -Slack : -0.226 -Actual Width : -0.042 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[20] - -Slack : -0.226 -Actual Width : -0.042 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[2] - -Slack : -0.226 -Actual Width : -0.042 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[3] - -Slack : -0.226 -Actual Width : -0.042 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[4] - -Slack : -0.226 -Actual Width : -0.042 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[5] - -Slack : -0.226 -Actual Width : -0.042 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[6] - -Slack : -0.226 -Actual Width : -0.042 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[7] - -Slack : -0.226 -Actual Width : -0.042 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[8] - -Slack : -0.226 -Actual Width : -0.042 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[9] - -Slack : -0.070 -Actual Width : -0.070 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : address[0]|clk - -Slack : -0.070 -Actual Width : -0.070 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : address[1]|clk - -Slack : -0.070 -Actual Width : -0.070 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : address[2]|clk - -Slack : -0.051 -Actual Width : -0.051 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : CLOCK_50~input|o - -Slack : -0.047 -Actual Width : -0.047 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[0]|clk - -Slack : -0.047 -Actual Width : -0.047 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[10]|clk - -Slack : -0.047 -Actual Width : -0.047 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[11]|clk - -Slack : -0.047 -Actual Width : -0.047 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[12]|clk - -Slack : -0.047 -Actual Width : -0.047 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[13]|clk - -Slack : -0.047 -Actual Width : -0.047 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[14]|clk - -Slack : -0.047 -Actual Width : -0.047 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[15]|clk - -Slack : -0.047 -Actual Width : -0.047 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[16]|clk - -Slack : -0.047 -Actual Width : -0.047 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[17]|clk - -Slack : -0.047 -Actual Width : -0.047 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[18]|clk - -Slack : -0.047 -Actual Width : -0.047 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[19]|clk - -Slack : -0.047 -Actual Width : -0.047 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[1]|clk - -Slack : -0.047 -Actual Width : -0.047 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[20]|clk - -Slack : -0.047 -Actual Width : -0.047 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[2]|clk - -Slack : -0.047 -Actual Width : -0.047 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[3]|clk - -Slack : -0.047 -Actual Width : -0.047 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[4]|clk - -Slack : -0.047 -Actual Width : -0.047 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[5]|clk - -Slack : -0.047 -Actual Width : -0.047 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[6]|clk - -Slack : -0.047 -Actual Width : -0.047 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[7]|clk - -Slack : -0.047 -Actual Width : -0.047 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[8]|clk - -Slack : -0.047 -Actual Width : -0.047 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[9]|clk - -Slack : -0.047 -Actual Width : -0.047 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : rom|altsyncram_component|auto_generated|ram_block1a0|clk0 - -Slack : -0.039 -Actual Width : -0.039 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : CLOCK_50~inputclkctrl|inclk[0] - -Slack : -0.039 -Actual Width : -0.039 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : CLOCK_50~inputclkctrl|outclk - -Slack : 0.500 -Actual Width : 0.500 -Required Width : 0.000 -Type : High Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : CLOCK_50~input|i - -Slack : 0.500 -Actual Width : 0.500 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : CLOCK_50~input|i - -Slack : 0.824 -Actual Width : 1.054 +Slack : -0.290 +Actual Width : -0.060 Required Width : 0.230 -Type : High Pulse Width +Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[0] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2 -Slack : 0.824 -Actual Width : 1.054 +Slack : -0.290 +Actual Width : -0.060 Required Width : 0.230 -Type : High Pulse Width +Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[1] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3 -Slack : 0.824 -Actual Width : 1.054 +Slack : -0.290 +Actual Width : -0.060 Required Width : 0.230 -Type : High Pulse Width +Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[2] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4 + +Slack : -0.290 +Actual Width : -0.060 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0 + +Slack : -0.290 +Actual Width : -0.060 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6 + +Slack : -0.290 +Actual Width : -0.060 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7 + +Slack : -0.290 +Actual Width : -0.060 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8 +--------------------------------------------------------------------------------+ @@ -8433,64 +8433,64 @@ Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_g +--------------------------------------------------------------------------------+ Data Port : LED[*] Clock Port : CLOCK_50 -Rise : 5.428 -Fall : 5.282 +Rise : 6.420 +Fall : 6.381 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[0] Clock Port : CLOCK_50 -Rise : 3.889 -Fall : 3.919 +Rise : 4.683 +Fall : 4.845 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[1] Clock Port : CLOCK_50 -Rise : 3.916 -Fall : 3.960 +Rise : 4.677 +Fall : 4.744 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[2] Clock Port : CLOCK_50 -Rise : 4.151 -Fall : 4.211 +Rise : 4.731 +Fall : 4.868 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[3] Clock Port : CLOCK_50 -Rise : 3.921 -Fall : 3.944 +Rise : 4.431 +Fall : 4.553 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[4] Clock Port : CLOCK_50 -Rise : 4.131 -Fall : 4.186 +Rise : 4.571 +Fall : 4.688 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[5] Clock Port : CLOCK_50 -Rise : 5.330 -Fall : 5.170 +Rise : 6.420 +Fall : 6.381 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[6] Clock Port : CLOCK_50 -Rise : 4.099 -Fall : 4.184 +Rise : 5.002 +Fall : 5.185 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[7] Clock Port : CLOCK_50 -Rise : 5.428 -Fall : 5.282 +Rise : 5.766 +Fall : 5.661 Clock Edge : Rise Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ @@ -8502,64 +8502,64 @@ Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ Data Port : LED[*] Clock Port : CLOCK_50 -Rise : 3.755 -Fall : 3.781 +Rise : 3.865 +Fall : 3.891 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[0] Clock Port : CLOCK_50 -Rise : 3.755 -Fall : 3.781 +Rise : 4.313 +Fall : 4.443 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[1] Clock Port : CLOCK_50 -Rise : 3.780 -Fall : 3.821 +Rise : 4.345 +Fall : 4.444 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[2] Clock Port : CLOCK_50 -Rise : 4.006 -Fall : 4.062 +Rise : 4.324 +Fall : 4.427 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[3] Clock Port : CLOCK_50 -Rise : 3.785 -Fall : 3.805 +Rise : 3.865 +Fall : 3.891 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[4] Clock Port : CLOCK_50 -Rise : 3.991 -Fall : 4.041 +Rise : 4.100 +Fall : 4.147 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[5] Clock Port : CLOCK_50 -Rise : 5.199 -Fall : 5.036 +Rise : 6.088 +Fall : 5.971 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[6] Clock Port : CLOCK_50 -Rise : 3.957 -Fall : 4.036 +Rise : 4.510 +Fall : 4.644 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[7] Clock Port : CLOCK_50 -Rise : 5.294 -Fall : 5.143 +Rise : 5.471 +Fall : 5.290 Clock Edge : Rise Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ @@ -8576,32 +8576,32 @@ No synchronizer chains to report. ; Multicorner Timing Analysis Summary ; +--------------------------------------------------------------------------------+ Clock : Worst-case Slack -Setup : -2.763 -Hold : 0.178 +Setup : -1.788 +Hold : 0.123 Recovery : N/A Removal : N/A Minimum Pulse Width : -3.000 Clock : CLOCK_50 -Setup : -2.763 -Hold : 0.178 +Setup : -1.788 +Hold : 0.123 Recovery : N/A Removal : N/A Minimum Pulse Width : -3.000 Clock : Design-wide TNS -Setup : -43.394 +Setup : -88.557 Hold : 0.0 Recovery : 0.0 Removal : 0.0 -Minimum Pulse Width : -46.633 +Minimum Pulse Width : -110.836 Clock : CLOCK_50 -Setup : -43.394 +Setup : -88.557 Hold : 0.000 Recovery : N/A Removal : N/A -Minimum Pulse Width : -46.633 +Minimum Pulse Width : -110.836 +--------------------------------------------------------------------------------+ @@ -8611,64 +8611,64 @@ Minimum Pulse Width : -46.633 +--------------------------------------------------------------------------------+ Data Port : LED[*] Clock Port : CLOCK_50 -Rise : 8.682 -Fall : 8.416 +Rise : 10.470 +Fall : 10.183 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[0] Clock Port : CLOCK_50 -Rise : 6.626 -Fall : 6.525 +Rise : 8.036 +Fall : 8.004 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[1] Clock Port : CLOCK_50 -Rise : 6.680 -Fall : 6.629 +Rise : 7.982 +Fall : 7.929 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[2] Clock Port : CLOCK_50 -Rise : 7.094 -Fall : 7.015 +Rise : 8.151 +Fall : 8.115 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[3] Clock Port : CLOCK_50 -Rise : 6.726 -Fall : 6.609 +Rise : 7.654 +Fall : 7.638 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[4] Clock Port : CLOCK_50 -Rise : 7.077 -Fall : 7.019 +Rise : 7.866 +Fall : 7.844 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[5] Clock Port : CLOCK_50 -Rise : 8.550 -Fall : 8.235 +Rise : 10.470 +Fall : 10.183 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[6] Clock Port : CLOCK_50 -Rise : 7.046 -Fall : 6.990 +Rise : 8.654 +Fall : 8.642 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[7] Clock Port : CLOCK_50 -Rise : 8.682 -Fall : 8.416 +Rise : 9.306 +Fall : 9.035 Clock Edge : Rise Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ @@ -8680,64 +8680,64 @@ Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ Data Port : LED[*] Clock Port : CLOCK_50 -Rise : 3.755 -Fall : 3.781 +Rise : 3.865 +Fall : 3.891 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[0] Clock Port : CLOCK_50 -Rise : 3.755 -Fall : 3.781 +Rise : 4.313 +Fall : 4.443 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[1] Clock Port : CLOCK_50 -Rise : 3.780 -Fall : 3.821 +Rise : 4.345 +Fall : 4.444 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[2] Clock Port : CLOCK_50 -Rise : 4.006 -Fall : 4.062 +Rise : 4.324 +Fall : 4.427 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[3] Clock Port : CLOCK_50 -Rise : 3.785 -Fall : 3.805 +Rise : 3.865 +Fall : 3.891 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[4] Clock Port : CLOCK_50 -Rise : 3.991 -Fall : 4.041 +Rise : 4.100 +Fall : 4.147 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[5] Clock Port : CLOCK_50 -Rise : 5.199 -Fall : 5.036 +Rise : 6.088 +Fall : 5.971 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[6] Clock Port : CLOCK_50 -Rise : 3.957 -Fall : 4.036 +Rise : 4.510 +Fall : 4.644 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[7] Clock Port : CLOCK_50 -Rise : 5.294 -Fall : 5.143 +Rise : 5.471 +Fall : 5.290 Clock Edge : Rise Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ @@ -9779,7 +9779,7 @@ Monotonic Fall at Far-end : Yes +--------------------------------------------------------------------------------+ From Clock : CLOCK_50 To Clock : CLOCK_50 -RR Paths : 941 +RR Paths : 908 FR Paths : 0 RF Paths : 0 FF Paths : 0 @@ -9793,7 +9793,7 @@ Entries labeled "false path" only account for clock-to-clock false paths and not +--------------------------------------------------------------------------------+ From Clock : CLOCK_50 To Clock : CLOCK_50 -RR Paths : 941 +RR Paths : 908 FR Paths : 0 RF Paths : 0 FF Paths : 0 @@ -9838,8 +9838,8 @@ Setup : 8 Hold : 8 Property : Unconstrained Output Port Paths -Setup : 8 -Hold : 8 +Setup : 24 +Hold : 24 +--------------------------------------------------------------------------------+ @@ -9850,7 +9850,7 @@ Hold : 8 Info: ******************************************************************* Info: Running Quartus II 32-bit TimeQuest Timing Analyzer Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition - Info: Processing started: Wed Mar 30 12:38:38 2022 + Info: Processing started: Wed Mar 30 13:12:24 2022 Info: Command: quartus_sta spectrum -c spectrum Info: qsta_default_script.tcl version: #1 Warning (20028): Parallel compilation is not licensed and has been disabled @@ -9867,63 +9867,63 @@ Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Info: Analyzing Slow 1200mV 85C Model Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. -Info (332146): Worst-case setup slack is -2.763 +Info (332146): Worst-case setup slack is -1.788 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -2.763 -43.394 CLOCK_50 -Info (332146): Worst-case hold slack is 0.343 + Info (332119): -1.788 -88.557 CLOCK_50 +Info (332146): Worst-case hold slack is 0.260 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 0.343 0.000 CLOCK_50 + Info (332119): 0.260 0.000 CLOCK_50 Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is -3.000 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -3.000 -46.633 CLOCK_50 + Info (332119): -3.000 -110.836 CLOCK_50 Info: Analyzing Slow 1200mV 0C Model Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. -Info (332146): Worst-case setup slack is -2.331 +Info (332146): Worst-case setup slack is -1.527 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -2.331 -34.994 CLOCK_50 -Info (332146): Worst-case hold slack is 0.299 + Info (332119): -1.527 -72.611 CLOCK_50 +Info (332146): Worst-case hold slack is 0.255 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 0.299 0.000 CLOCK_50 + Info (332119): 0.255 0.000 CLOCK_50 Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is -3.000 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -3.000 -46.624 CLOCK_50 + Info (332119): -3.000 -110.824 CLOCK_50 Info: Analyzing Fast 1200mV 0C Model Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. -Info (332146): Worst-case setup slack is -1.122 +Info (332146): Worst-case setup slack is -0.529 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -1.122 -9.363 CLOCK_50 -Info (332146): Worst-case hold slack is 0.178 + Info (332119): -0.529 -18.538 CLOCK_50 +Info (332146): Worst-case hold slack is 0.123 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 0.178 0.000 CLOCK_50 + Info (332119): 0.123 0.000 CLOCK_50 Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is -3.000 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -3.000 -45.480 CLOCK_50 + Info (332119): -3.000 -93.684 CLOCK_50 Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings - Info: Peak virtual memory: 415 megabytes - Info: Processing ended: Wed Mar 30 12:38:40 2022 + Info: Peak virtual memory: 407 megabytes + Info: Processing ended: Wed Mar 30 13:12:26 2022 Info: Elapsed time: 00:00:02 Info: Total CPU time (on all processors): 00:00:02 diff --git a/output_files/spectrum.sta.summary b/output_files/spectrum.sta.summary index 97ccdb9..25a9c18 100644 --- a/output_files/spectrum.sta.summary +++ b/output_files/spectrum.sta.summary @@ -3,39 +3,39 @@ TimeQuest Timing Analyzer Summary ------------------------------------------------------------ Type : Slow 1200mV 85C Model Setup 'CLOCK_50' -Slack : -2.763 -TNS : -43.394 +Slack : -1.788 +TNS : -88.557 Type : Slow 1200mV 85C Model Hold 'CLOCK_50' -Slack : 0.343 +Slack : 0.260 TNS : 0.000 Type : Slow 1200mV 85C Model Minimum Pulse Width 'CLOCK_50' Slack : -3.000 -TNS : -46.633 +TNS : -110.836 Type : Slow 1200mV 0C Model Setup 'CLOCK_50' -Slack : -2.331 -TNS : -34.994 +Slack : -1.527 +TNS : -72.611 Type : Slow 1200mV 0C Model Hold 'CLOCK_50' -Slack : 0.299 +Slack : 0.255 TNS : 0.000 Type : Slow 1200mV 0C Model Minimum Pulse Width 'CLOCK_50' Slack : -3.000 -TNS : -46.624 +TNS : -110.824 Type : Fast 1200mV 0C Model Setup 'CLOCK_50' -Slack : -1.122 -TNS : -9.363 +Slack : -0.529 +TNS : -18.538 Type : Fast 1200mV 0C Model Hold 'CLOCK_50' -Slack : 0.178 +Slack : 0.123 TNS : 0.000 Type : Fast 1200mV 0C Model Minimum Pulse Width 'CLOCK_50' Slack : -3.000 -TNS : -45.480 +TNS : -93.684 ------------------------------------------------------------ diff --git a/rom/gw03.hex b/rom/gw03.hex new file mode 100644 index 0000000..b6cdd6c --- /dev/null +++ b/rom/gw03.hex @@ -0,0 +1,514 @@ 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+:203F40000040407844444400001000301010380000040004040424180020283030282400C5 +:203F60000010101010100C0000006854545454000000784444444400000038444444380069 +:203F8000000078444478404000003C44443C040600001C2020202000000038403804780057 +:203FA0000010381010100C00000044444444380000004444282810000000445454542800E5 +:203FC000000044281028440000004444443C043800007C0810207C00000E083008080E0021 +:203FE00000080808080808000070100C1010700000142800000000003C4299A1A199423CC9 +:00000001FF diff --git a/rom/gw03.rom b/rom/gw03.rom new file mode 100644 index 0000000..1f95f9f Binary files /dev/null and b/rom/gw03.rom differ diff --git a/rom0.cnx b/rom0.cnx deleted file mode 100644 index f793609..0000000 --- a/rom0.cnx +++ /dev/null @@ -1,98 +0,0 @@ -VERSION: WM1.0 -MODULE: altsyncram -PRIVATE: ADDRESSSTALL_A NUMERIC "0" -PRIVATE: AclrAddr NUMERIC "0" -PRIVATE: AclrByte NUMERIC "0" -PRIVATE: AclrOutput NUMERIC "0" -PRIVATE: BYTE_ENABLE NUMERIC "0" -PRIVATE: BYTE_SIZE NUMERIC "8" -PRIVATE: BlankMemory NUMERIC "0" -PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" -PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" -PRIVATE: Clken NUMERIC "0" -PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" -PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" -PRIVATE: INIT_TO_SIM_X NUMERIC "0" -PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" -PRIVATE: JTAG_ENABLED NUMERIC "0" -PRIVATE: JTAG_ID STRING "NONE" -PRIVATE: MAXIMUM_DEPTH NUMERIC "0" -PRIVATE: MIFfilename STRING "led_patterns.mif" -PRIVATE: NUMWORDS_A NUMERIC "8" -PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -PRIVATE: RegAddr NUMERIC "1" -PRIVATE: RegOutput NUMERIC "1" -PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -PRIVATE: SingleClock NUMERIC "1" -PRIVATE: UseDQRAM NUMERIC "0" -PRIVATE: WidthAddr NUMERIC "3" -PRIVATE: WidthData NUMERIC "8" -PRIVATE: rden NUMERIC "0" -LIBRARY: altera_mf altera_mf.altera_mf_components.all -CONSTANT: ADDRESS_ACLR_A STRING "NONE" -CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" -CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" -CONSTANT: INIT_FILE STRING "led_patterns.mif" -CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" -CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" -CONSTANT: LPM_TYPE STRING "altsyncram" -CONSTANT: NUMWORDS_A NUMERIC "8" -CONSTANT: OPERATION_MODE STRING "ROM" -CONSTANT: OUTDATA_ACLR_A STRING "NONE" -CONSTANT: OUTDATA_REG_A STRING "CLOCK0" -CONSTANT: WIDTHAD_A NUMERIC "3" -CONSTANT: WIDTH_A NUMERIC "8" -CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" -USED_PORT: address 0 0 3 0 INPUT NODEFVAL "address[2..0]" -USED_PORT: clock 0 0 0 0 INPUT VCC "clock" -USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" -CONNECT: @address_a 0 0 3 0 address 0 0 3 0 -CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 -CONNECT: q 0 0 8 0 @q_a 0 0 8 0 -GEN_FILE: TYPE_NORMAL rom0.v TRUE -GEN_FILE: TYPE_NORMAL rom0.inc FALSE -GEN_FILE: TYPE_NORMAL rom0.cmp FALSE -GEN_FILE: TYPE_NORMAL rom0.bsf FALSE -GEN_FILE: TYPE_NORMAL rom0_inst.v FALSE -GEN_FILE: TYPE_NORMAL rom0_bb.v TRUE -LIB_FILE: altera_mf - -LICENSE_ID: "DEVICE_FAMILY_Cyclone III" 30229803K6032210322T -LICENSE_ID: "DEVICE_FAMILY_Cyclone IV E" 30229803A6032210322A -LICENSE_ID: "DEVICE_FAMILY_Cyclone V" 30229803A6032210322B -LICENSE_ID: "DEVICE_FAMILY_Cyclone IV GX" 30229803A6032210322B -LICENSE_ID: "DEVICE_FAMILY_Cyclone III LS" 30229803A6032210322B -LICENSE_ID: "FEATURE_STRATIXGX_DPA" 30229803M6032210322T -LICENSE_ID: "FEATURE_STRATIXGX_BASIC" 30229803A6032210322B - - -SUPPORTED_DEVICE_FAMILY: "Cyclone III" -SUPPORTED_DEVICE_FAMILY: "Cyclone IV E" -SUPPORTED_DEVICE_FAMILY: "Cyclone V" -SUPPORTED_DEVICE_FAMILY: "Cyclone IV GX" -SUPPORTED_DEVICE_FAMILY: "Cyclone III LS" -SUPPORTED_DEVICE_FAMILY: "Cyclone IV E" - -WIZARD_TITLE: "ROM: 1-PORT" -QUARTUS_VERSION: "Version 13.1" -QUARTUS_SVERSION: "13.1.0 Build 162 10/23/2013 SJ Web Edition:10/23/2013" -QUARTUS_BUILD_DATE: "10/23/2013" -ALTERA_COPYRIGHT: "Copyright (C) 1991-2013 Altera Corporation" -RESC_INFO: ON - - -HELP_MENU_ITEM: FALSE "IUG_ALIAS$STRATIX_WEB_LINK$http://www.altera.com/literature/hb/stx/ch_3_vol_2.pdf" -HELP_MENU_ITEM: FALSE "ALIAS$STRATIX_WEB_MENU_LABEL$TriMatrix Memory Blocks in Stratix (GX)" -HELP_MENU_ITEM: FALSE "IUG_ALIAS$CYCLONE_IV_WEB_LINK$http://www.altera.com/literature/hb/cyclone-iv/cyiv-51003.pdf" -HELP_MENU_ITEM: FALSE "ALIAS$CYCLONE_IV_WEB_MENU_LABEL$Cyclone IV Memory Blocks" -HELP_MENU_ITEM: FALSE "IUG_ALIAS$CYCLONEII_WEB_LINK$http://www.altera.com/literature/hb/cyc2/cyc2_cii51008.pdf" -HELP_MENU_ITEM: FALSE "ALIAS$CYCLONEII_WEB_MENU_LABEL$Cyclone II Memory Blocks" -HELP_MENU_ITEM: FALSE "IUG_ALIAS$CYCLONE_WEB_LINK$http://www.altera.com/literature/hb/cyc/cyc_c51007.pdf" -HELP_MENU_ITEM: FALSE "ALIAS$CYCLONE_WEB_MENU_LABEL$Memory Implementations Using Cyclone Memory Blocks" -HELP_MENU_ITEM: FALSE "IUG_ALIAS$STRATIXII_WEB_LINK$http://www.altera.com/literature/hb/stx2/stx2_sii52002.pdf" -HELP_MENU_ITEM: FALSE "ALIAS$STRATIXII_WEB_MENU_LABEL$TriMatrix Memory Blocks in Stratix II" -HELP_MENU_ITEM: FALSE "IUG_ALIAS$STRATIXIII_WEB_LINK$http://www.altera.com/literature/hb/stx3/stx3_siii51004.pdf" -HELP_MENU_ITEM: FALSE "ALIAS$STRATIXIII_WEB_MENU_LABEL$TriMatrix Embedded Memory Blocks in Stratix III" -HELP_MENU_ITEM: FALSE "IUG_ALIAS$APEX_WEB_LINK$http://www.altera.com/literature/an/an179.pdf" -HELP_MENU_ITEM: FALSE "ALIAS$APEX_WEB_MENU_LABEL$Designing with ESBs" -HELP_MENU_ITEM: FALSE "IUG$ROM Megafunction User Guide$http://www.altera.com/literature/ug/ug_memrom.pdf" diff --git a/rom0.v b/rom0.v index 1e74bb4..69d769c 100644 --- a/rom0.v +++ b/rom0.v @@ -41,7 +41,7 @@ module rom0 ( clock, q); - input [2:0] address; + input [13:0] address; input clock; output [7:0] q; `ifndef ALTERA_RESERVED_QIS @@ -83,15 +83,20 @@ module rom0 ( altsyncram_component.address_aclr_a = "NONE", altsyncram_component.clock_enable_input_a = "BYPASS", altsyncram_component.clock_enable_output_a = "BYPASS", - altsyncram_component.init_file = "led_patterns.mif", +`ifdef NO_PLI + altsyncram_component.init_file = "./rom/gw03.rif" +`else + altsyncram_component.init_file = "./rom/gw03.hex" +`endif +, altsyncram_component.intended_device_family = "Cyclone IV E", altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", altsyncram_component.lpm_type = "altsyncram", - altsyncram_component.numwords_a = 8, + altsyncram_component.numwords_a = 16384, altsyncram_component.operation_mode = "ROM", altsyncram_component.outdata_aclr_a = "NONE", altsyncram_component.outdata_reg_a = "CLOCK0", - altsyncram_component.widthad_a = 3, + altsyncram_component.widthad_a = 14, altsyncram_component.width_a = 8, altsyncram_component.width_byteena_a = 1; @@ -118,36 +123,36 @@ endmodule // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" -// Retrieval info: PRIVATE: MIFfilename STRING "led_patterns.mif" -// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8" +// Retrieval info: PRIVATE: MIFfilename STRING "./rom/gw03.hex" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "16384" // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" // Retrieval info: PRIVATE: RegAddr NUMERIC "1" // Retrieval info: PRIVATE: RegOutput NUMERIC "1" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: SingleClock NUMERIC "1" // Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" -// Retrieval info: PRIVATE: WidthAddr NUMERIC "3" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "14" // Retrieval info: PRIVATE: WidthData NUMERIC "8" // Retrieval info: PRIVATE: rden NUMERIC "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" -// Retrieval info: CONSTANT: INIT_FILE STRING "led_patterns.mif" +// Retrieval info: CONSTANT: INIT_FILE STRING "./rom/gw03.hex" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384" // Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" -// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "3" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14" // Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" -// Retrieval info: USED_PORT: address 0 0 3 0 INPUT NODEFVAL "address[2..0]" +// Retrieval info: USED_PORT: address 0 0 14 0 INPUT NODEFVAL "address[13..0]" // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" // Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" -// Retrieval info: CONNECT: @address_a 0 0 3 0 address 0 0 3 0 +// Retrieval info: CONNECT: @address_a 0 0 14 0 address 0 0 14 0 // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 // Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 // Retrieval info: GEN_FILE: TYPE_NORMAL rom0.v TRUE diff --git a/rom0_bb.v b/rom0_bb.v index a5d4866..a150391 100644 --- a/rom0_bb.v +++ b/rom0_bb.v @@ -36,7 +36,7 @@ module rom0 ( clock, q); - input [2:0] address; + input [13:0] address; input clock; output [7:0] q; `ifndef ALTERA_RESERVED_QIS @@ -69,36 +69,36 @@ endmodule // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" -// Retrieval info: PRIVATE: MIFfilename STRING "led_patterns.mif" -// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8" +// Retrieval info: PRIVATE: MIFfilename STRING "./rom/gw03.hex" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "16384" // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" // Retrieval info: PRIVATE: RegAddr NUMERIC "1" // Retrieval info: PRIVATE: RegOutput NUMERIC "1" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: SingleClock NUMERIC "1" // Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" -// Retrieval info: PRIVATE: WidthAddr NUMERIC "3" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "14" // Retrieval info: PRIVATE: WidthData NUMERIC "8" // Retrieval info: PRIVATE: rden NUMERIC "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" -// Retrieval info: CONSTANT: INIT_FILE STRING "led_patterns.mif" +// Retrieval info: CONSTANT: INIT_FILE STRING "./rom/gw03.hex" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384" // Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" -// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "3" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14" // Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" -// Retrieval info: USED_PORT: address 0 0 3 0 INPUT NODEFVAL "address[2..0]" +// Retrieval info: USED_PORT: address 0 0 14 0 INPUT NODEFVAL "address[13..0]" // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" // Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" -// Retrieval info: CONNECT: @address_a 0 0 3 0 address 0 0 3 0 +// Retrieval info: CONNECT: @address_a 0 0 14 0 address 0 0 14 0 // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 // Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 // Retrieval info: GEN_FILE: TYPE_NORMAL rom0.v TRUE diff --git a/simulation/modelsim/spectrum.vo b/simulation/modelsim/spectrum.vo index 59e758e..87e1f0e 100644 --- a/simulation/modelsim/spectrum.vo +++ b/simulation/modelsim/spectrum.vo @@ -16,7 +16,7 @@ // PROGRAM "Quartus II 32-bit" // VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" -// DATE "03/30/2022 12:38:42" +// DATE "03/30/2022 13:12:28" // // Device: Altera EP4CE22F17C6 Package FBGA256 @@ -71,77 +71,166 @@ wire \LED[6]~output_o ; wire \LED[7]~output_o ; wire \CLOCK_50~input_o ; wire \CLOCK_50~inputclkctrl_outclk ; -wire \Add0~0_combout ; -wire \Add0~1 ; -wire \Add0~2_combout ; -wire \Add0~3 ; -wire \Add0~4_combout ; -wire \Add0~5 ; -wire \Add0~6_combout ; -wire \Add0~7 ; -wire \Add0~8_combout ; -wire \Add0~9 ; -wire \Add0~10_combout ; -wire \Add0~11 ; -wire \Add0~12_combout ; -wire \Add0~13 ; -wire \Add0~14_combout ; -wire \Add0~15 ; -wire \Add0~16_combout ; -wire \Add0~17 ; -wire \Add0~18_combout ; -wire \Add0~19 ; -wire \Add0~20_combout ; -wire \Add0~21 ; -wire \Add0~22_combout ; -wire \Add0~23 ; -wire \Add0~24_combout ; -wire \Add0~25 ; -wire \Add0~26_combout ; -wire \Add0~27 ; -wire \Add0~28_combout ; -wire \Add0~29 ; -wire \Add0~30_combout ; -wire \Add0~31 ; -wire \Add0~32_combout ; -wire \Add0~33 ; -wire \Add0~34_combout ; -wire \Add0~35 ; -wire \Add0~36_combout ; -wire \Add0~37 ; -wire \Add0~38_combout ; -wire \Add0~39 ; -wire \Add0~40_combout ; +wire \counter[0]~63_combout ; +wire \counter[1]~21_combout ; +wire \counter[1]~22 ; +wire \counter[2]~23_combout ; +wire \counter[2]~24 ; +wire \counter[3]~25_combout ; +wire \counter[3]~26 ; +wire \counter[4]~27_combout ; +wire \counter[4]~28 ; +wire \counter[5]~29_combout ; +wire \counter[5]~30 ; +wire \counter[6]~31_combout ; +wire \counter[6]~32 ; +wire \counter[7]~33_combout ; +wire \counter[7]~34 ; +wire \counter[8]~35_combout ; +wire \counter[8]~36 ; +wire \counter[9]~37_combout ; +wire \counter[9]~38 ; +wire \counter[10]~39_combout ; +wire \counter[10]~40 ; +wire \counter[11]~41_combout ; +wire \counter[11]~feeder_combout ; +wire \counter[11]~42 ; +wire \counter[12]~43_combout ; +wire \counter[12]~44 ; +wire \counter[13]~45_combout ; +wire \counter[13]~46 ; +wire \counter[14]~47_combout ; +wire \counter[14]~48 ; +wire \counter[15]~49_combout ; +wire \counter[15]~50 ; +wire \counter[16]~51_combout ; +wire \counter[16]~52 ; +wire \counter[17]~53_combout ; +wire \counter[17]~54 ; +wire \counter[18]~55_combout ; +wire \counter[18]~56 ; +wire \counter[19]~57_combout ; wire \Equal0~5_combout ; -wire \Equal0~1_combout ; wire \Equal0~0_combout ; +wire \Equal0~1_combout ; wire \Equal0~2_combout ; wire \Equal0~3_combout ; wire \Equal0~4_combout ; -wire \address[0]~0_combout ; -wire \Equal0~6_combout ; +wire \counter[19]~58 ; +wire \counter[20]~59_combout ; +wire \counter[20]~60 ; +wire \counter[21]~61_combout ; wire \Equal0~7_combout ; -wire \address[1]~1_combout ; -wire \address[1]~2_combout ; -wire \address[2]~3_combout ; -wire [20:0] counter; -wire [2:0] address; -wire [7:0] \rom|altsyncram_component|auto_generated|q_a ; +wire \address[0]~39_combout ; +wire \address[1]~13_combout ; +wire \Equal0~6_combout ; +wire \address[1]~14 ; +wire \address[2]~15_combout ; +wire \address[2]~16 ; +wire \address[3]~17_combout ; +wire \address[3]~18 ; +wire \address[4]~19_combout ; +wire \address[4]~20 ; +wire \address[5]~21_combout ; +wire \address[5]~22 ; +wire \address[6]~23_combout ; +wire \address[6]~24 ; +wire \address[7]~25_combout ; +wire \address[7]~26 ; +wire \address[8]~27_combout ; +wire \address[8]~28 ; +wire \address[9]~29_combout ; +wire \address[9]~30 ; +wire \address[10]~31_combout ; +wire \address[10]~32 ; +wire \address[11]~33_combout ; +wire \address[11]~34 ; +wire \address[12]~35_combout ; +wire \address[12]~36 ; +wire \address[13]~37_combout ; +wire \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; +wire \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ; +wire [21:0] counter; +wire [13:0] address; +wire [0:0] \rom|altsyncram_component|auto_generated|out_address_reg_a ; +wire [0:0] \rom|altsyncram_component|auto_generated|address_reg_a ; -wire [17:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; -assign \rom|altsyncram_component|auto_generated|q_a [0] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|q_a [1] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [1]; -assign \rom|altsyncram_component|auto_generated|q_a [2] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [2]; -assign \rom|altsyncram_component|auto_generated|q_a [3] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [3]; -assign \rom|altsyncram_component|auto_generated|q_a [4] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [4]; -assign \rom|altsyncram_component|auto_generated|q_a [5] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [5]; -assign \rom|altsyncram_component|auto_generated|q_a [6] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [6]; -assign \rom|altsyncram_component|auto_generated|q_a [7] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [7]; +assign \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; // Location: IOOBUF_X38_Y34_N16 cycloneive_io_obuf \LED[0]~output ( - .i(\rom|altsyncram_component|auto_generated|q_a [0]), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -154,7 +243,7 @@ defparam \LED[0]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y34_N2 cycloneive_io_obuf \LED[1]~output ( - .i(\rom|altsyncram_component|auto_generated|q_a [1]), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -167,7 +256,7 @@ defparam \LED[1]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y34_N9 cycloneive_io_obuf \LED[2]~output ( - .i(\rom|altsyncram_component|auto_generated|q_a [2]), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -180,7 +269,7 @@ defparam \LED[2]~output .open_drain_output = "false"; // Location: IOOBUF_X40_Y34_N2 cycloneive_io_obuf \LED[3]~output ( - .i(\rom|altsyncram_component|auto_generated|q_a [3]), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -193,7 +282,7 @@ defparam \LED[3]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y25_N9 cycloneive_io_obuf \LED[4]~output ( - .i(\rom|altsyncram_component|auto_generated|q_a [4]), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -206,7 +295,7 @@ defparam \LED[4]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y26_N16 cycloneive_io_obuf \LED[5]~output ( - .i(\rom|altsyncram_component|auto_generated|q_a [5]), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -219,7 +308,7 @@ defparam \LED[5]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y28_N9 cycloneive_io_obuf \LED[6]~output ( - .i(\rom|altsyncram_component|auto_generated|q_a [6]), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -232,7 +321,7 @@ defparam \LED[6]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y10_N23 cycloneive_io_obuf \LED[7]~output ( - .i(\rom|altsyncram_component|auto_generated|q_a [7]), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -266,47 +355,27 @@ defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: FF_X31_Y17_N21 -dffeas \counter[20] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~40_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[20]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[20] .is_wysiwyg = "true"; -defparam \counter[20] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N12 -cycloneive_lcell_comb \Add0~0 ( +// Location: LCCOMB_X28_Y18_N2 +cycloneive_lcell_comb \counter[0]~63 ( // Equation(s): -// \Add0~0_combout = counter[0] $ (VCC) -// \Add0~1 = CARRY(counter[0]) +// \counter[0]~63_combout = !counter[0] - .dataa(counter[0]), + .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(vcc), + .datac(counter[0]), + .datad(gnd), .cin(gnd), - .combout(\Add0~0_combout ), - .cout(\Add0~1 )); + .combout(\counter[0]~63_combout ), + .cout()); // synopsys translate_off -defparam \Add0~0 .lut_mask = 16'h55AA; -defparam \Add0~0 .sum_lutc_input = "datac"; +defparam \counter[0]~63 .lut_mask = 16'h0F0F; +defparam \counter[0]~63 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y18_N13 +// Location: FF_X28_Y18_N3 dffeas \counter[0] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~0_combout ), + .d(\counter[0]~63_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -322,28 +391,28 @@ defparam \counter[0] .is_wysiwyg = "true"; defparam \counter[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y18_N14 -cycloneive_lcell_comb \Add0~2 ( +// Location: LCCOMB_X28_Y18_N12 +cycloneive_lcell_comb \counter[1]~21 ( // Equation(s): -// \Add0~2_combout = (counter[1] & (!\Add0~1 )) # (!counter[1] & ((\Add0~1 ) # (GND))) -// \Add0~3 = CARRY((!\Add0~1 ) # (!counter[1])) +// \counter[1]~21_combout = (counter[1] & (counter[0] $ (VCC))) # (!counter[1] & (counter[0] & VCC)) +// \counter[1]~22 = CARRY((counter[1] & counter[0])) - .dataa(gnd), - .datab(counter[1]), + .dataa(counter[1]), + .datab(counter[0]), .datac(gnd), .datad(vcc), - .cin(\Add0~1 ), - .combout(\Add0~2_combout ), - .cout(\Add0~3 )); + .cin(gnd), + .combout(\counter[1]~21_combout ), + .cout(\counter[1]~22 )); // synopsys translate_off -defparam \Add0~2 .lut_mask = 16'h3C3F; -defparam \Add0~2 .sum_lutc_input = "cin"; +defparam \counter[1]~21 .lut_mask = 16'h6688; +defparam \counter[1]~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y18_N15 +// Location: FF_X28_Y18_N13 dffeas \counter[1] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~2_combout ), + .d(\counter[1]~21_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -359,28 +428,28 @@ defparam \counter[1] .is_wysiwyg = "true"; defparam \counter[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y18_N16 -cycloneive_lcell_comb \Add0~4 ( +// Location: LCCOMB_X28_Y18_N14 +cycloneive_lcell_comb \counter[2]~23 ( // Equation(s): -// \Add0~4_combout = (counter[2] & (\Add0~3 $ (GND))) # (!counter[2] & (!\Add0~3 & VCC)) -// \Add0~5 = CARRY((counter[2] & !\Add0~3 )) +// \counter[2]~23_combout = (counter[2] & (!\counter[1]~22 )) # (!counter[2] & ((\counter[1]~22 ) # (GND))) +// \counter[2]~24 = CARRY((!\counter[1]~22 ) # (!counter[2])) .dataa(gnd), .datab(counter[2]), .datac(gnd), .datad(vcc), - .cin(\Add0~3 ), - .combout(\Add0~4_combout ), - .cout(\Add0~5 )); + .cin(\counter[1]~22 ), + .combout(\counter[2]~23_combout ), + .cout(\counter[2]~24 )); // synopsys translate_off -defparam \Add0~4 .lut_mask = 16'hC30C; -defparam \Add0~4 .sum_lutc_input = "cin"; +defparam \counter[2]~23 .lut_mask = 16'h3C3F; +defparam \counter[2]~23 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y18_N17 +// Location: FF_X28_Y18_N15 dffeas \counter[2] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~4_combout ), + .d(\counter[2]~23_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -396,28 +465,28 @@ defparam \counter[2] .is_wysiwyg = "true"; defparam \counter[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y18_N18 -cycloneive_lcell_comb \Add0~6 ( +// Location: LCCOMB_X28_Y18_N16 +cycloneive_lcell_comb \counter[3]~25 ( // Equation(s): -// \Add0~6_combout = (counter[3] & (!\Add0~5 )) # (!counter[3] & ((\Add0~5 ) # (GND))) -// \Add0~7 = CARRY((!\Add0~5 ) # (!counter[3])) +// \counter[3]~25_combout = (counter[3] & (\counter[2]~24 $ (GND))) # (!counter[3] & (!\counter[2]~24 & VCC)) +// \counter[3]~26 = CARRY((counter[3] & !\counter[2]~24 )) .dataa(gnd), .datab(counter[3]), .datac(gnd), .datad(vcc), - .cin(\Add0~5 ), - .combout(\Add0~6_combout ), - .cout(\Add0~7 )); + .cin(\counter[2]~24 ), + .combout(\counter[3]~25_combout ), + .cout(\counter[3]~26 )); // synopsys translate_off -defparam \Add0~6 .lut_mask = 16'h3C3F; -defparam \Add0~6 .sum_lutc_input = "cin"; +defparam \counter[3]~25 .lut_mask = 16'hC30C; +defparam \counter[3]~25 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y18_N19 +// Location: FF_X28_Y18_N17 dffeas \counter[3] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~6_combout ), + .d(\counter[3]~25_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -433,28 +502,28 @@ defparam \counter[3] .is_wysiwyg = "true"; defparam \counter[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y18_N20 -cycloneive_lcell_comb \Add0~8 ( +// Location: LCCOMB_X28_Y18_N18 +cycloneive_lcell_comb \counter[4]~27 ( // Equation(s): -// \Add0~8_combout = (counter[4] & (\Add0~7 $ (GND))) # (!counter[4] & (!\Add0~7 & VCC)) -// \Add0~9 = CARRY((counter[4] & !\Add0~7 )) +// \counter[4]~27_combout = (counter[4] & (!\counter[3]~26 )) # (!counter[4] & ((\counter[3]~26 ) # (GND))) +// \counter[4]~28 = CARRY((!\counter[3]~26 ) # (!counter[4])) - .dataa(counter[4]), - .datab(gnd), + .dataa(gnd), + .datab(counter[4]), .datac(gnd), .datad(vcc), - .cin(\Add0~7 ), - .combout(\Add0~8_combout ), - .cout(\Add0~9 )); + .cin(\counter[3]~26 ), + .combout(\counter[4]~27_combout ), + .cout(\counter[4]~28 )); // synopsys translate_off -defparam \Add0~8 .lut_mask = 16'hA50A; -defparam \Add0~8 .sum_lutc_input = "cin"; +defparam \counter[4]~27 .lut_mask = 16'h3C3F; +defparam \counter[4]~27 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y18_N21 +// Location: FF_X28_Y18_N19 dffeas \counter[4] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~8_combout ), + .d(\counter[4]~27_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -470,28 +539,28 @@ defparam \counter[4] .is_wysiwyg = "true"; defparam \counter[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y18_N22 -cycloneive_lcell_comb \Add0~10 ( +// Location: LCCOMB_X28_Y18_N20 +cycloneive_lcell_comb \counter[5]~29 ( // Equation(s): -// \Add0~10_combout = (counter[5] & (!\Add0~9 )) # (!counter[5] & ((\Add0~9 ) # (GND))) -// \Add0~11 = CARRY((!\Add0~9 ) # (!counter[5])) +// \counter[5]~29_combout = (counter[5] & (\counter[4]~28 $ (GND))) # (!counter[5] & (!\counter[4]~28 & VCC)) +// \counter[5]~30 = CARRY((counter[5] & !\counter[4]~28 )) .dataa(gnd), .datab(counter[5]), .datac(gnd), .datad(vcc), - .cin(\Add0~9 ), - .combout(\Add0~10_combout ), - .cout(\Add0~11 )); + .cin(\counter[4]~28 ), + .combout(\counter[5]~29_combout ), + .cout(\counter[5]~30 )); // synopsys translate_off -defparam \Add0~10 .lut_mask = 16'h3C3F; -defparam \Add0~10 .sum_lutc_input = "cin"; +defparam \counter[5]~29 .lut_mask = 16'hC30C; +defparam \counter[5]~29 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y18_N23 +// Location: FF_X28_Y18_N21 dffeas \counter[5] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~10_combout ), + .d(\counter[5]~29_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -507,28 +576,28 @@ defparam \counter[5] .is_wysiwyg = "true"; defparam \counter[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y18_N24 -cycloneive_lcell_comb \Add0~12 ( +// Location: LCCOMB_X28_Y18_N22 +cycloneive_lcell_comb \counter[6]~31 ( // Equation(s): -// \Add0~12_combout = (counter[6] & (\Add0~11 $ (GND))) # (!counter[6] & (!\Add0~11 & VCC)) -// \Add0~13 = CARRY((counter[6] & !\Add0~11 )) +// \counter[6]~31_combout = (counter[6] & (!\counter[5]~30 )) # (!counter[6] & ((\counter[5]~30 ) # (GND))) +// \counter[6]~32 = CARRY((!\counter[5]~30 ) # (!counter[6])) .dataa(counter[6]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\Add0~11 ), - .combout(\Add0~12_combout ), - .cout(\Add0~13 )); + .cin(\counter[5]~30 ), + .combout(\counter[6]~31_combout ), + .cout(\counter[6]~32 )); // synopsys translate_off -defparam \Add0~12 .lut_mask = 16'hA50A; -defparam \Add0~12 .sum_lutc_input = "cin"; +defparam \counter[6]~31 .lut_mask = 16'h5A5F; +defparam \counter[6]~31 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y18_N25 +// Location: FF_X28_Y18_N23 dffeas \counter[6] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~12_combout ), + .d(\counter[6]~31_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -544,28 +613,28 @@ defparam \counter[6] .is_wysiwyg = "true"; defparam \counter[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y18_N26 -cycloneive_lcell_comb \Add0~14 ( +// Location: LCCOMB_X28_Y18_N24 +cycloneive_lcell_comb \counter[7]~33 ( // Equation(s): -// \Add0~14_combout = (counter[7] & (!\Add0~13 )) # (!counter[7] & ((\Add0~13 ) # (GND))) -// \Add0~15 = CARRY((!\Add0~13 ) # (!counter[7])) +// \counter[7]~33_combout = (counter[7] & (\counter[6]~32 $ (GND))) # (!counter[7] & (!\counter[6]~32 & VCC)) +// \counter[7]~34 = CARRY((counter[7] & !\counter[6]~32 )) .dataa(gnd), .datab(counter[7]), .datac(gnd), .datad(vcc), - .cin(\Add0~13 ), - .combout(\Add0~14_combout ), - .cout(\Add0~15 )); + .cin(\counter[6]~32 ), + .combout(\counter[7]~33_combout ), + .cout(\counter[7]~34 )); // synopsys translate_off -defparam \Add0~14 .lut_mask = 16'h3C3F; -defparam \Add0~14 .sum_lutc_input = "cin"; +defparam \counter[7]~33 .lut_mask = 16'hC30C; +defparam \counter[7]~33 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y18_N27 +// Location: FF_X28_Y18_N25 dffeas \counter[7] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~14_combout ), + .d(\counter[7]~33_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -581,28 +650,28 @@ defparam \counter[7] .is_wysiwyg = "true"; defparam \counter[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y18_N28 -cycloneive_lcell_comb \Add0~16 ( +// Location: LCCOMB_X28_Y18_N26 +cycloneive_lcell_comb \counter[8]~35 ( // Equation(s): -// \Add0~16_combout = (counter[8] & (\Add0~15 $ (GND))) # (!counter[8] & (!\Add0~15 & VCC)) -// \Add0~17 = CARRY((counter[8] & !\Add0~15 )) +// \counter[8]~35_combout = (counter[8] & (!\counter[7]~34 )) # (!counter[8] & ((\counter[7]~34 ) # (GND))) +// \counter[8]~36 = CARRY((!\counter[7]~34 ) # (!counter[8])) - .dataa(gnd), - .datab(counter[8]), + .dataa(counter[8]), + .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\Add0~15 ), - .combout(\Add0~16_combout ), - .cout(\Add0~17 )); + .cin(\counter[7]~34 ), + .combout(\counter[8]~35_combout ), + .cout(\counter[8]~36 )); // synopsys translate_off -defparam \Add0~16 .lut_mask = 16'hC30C; -defparam \Add0~16 .sum_lutc_input = "cin"; +defparam \counter[8]~35 .lut_mask = 16'h5A5F; +defparam \counter[8]~35 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y18_N29 +// Location: FF_X28_Y18_N27 dffeas \counter[8] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~16_combout ), + .d(\counter[8]~35_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -618,28 +687,28 @@ defparam \counter[8] .is_wysiwyg = "true"; defparam \counter[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y18_N30 -cycloneive_lcell_comb \Add0~18 ( +// Location: LCCOMB_X28_Y18_N28 +cycloneive_lcell_comb \counter[9]~37 ( // Equation(s): -// \Add0~18_combout = (counter[9] & (!\Add0~17 )) # (!counter[9] & ((\Add0~17 ) # (GND))) -// \Add0~19 = CARRY((!\Add0~17 ) # (!counter[9])) +// \counter[9]~37_combout = (counter[9] & (\counter[8]~36 $ (GND))) # (!counter[9] & (!\counter[8]~36 & VCC)) +// \counter[9]~38 = CARRY((counter[9] & !\counter[8]~36 )) - .dataa(counter[9]), - .datab(gnd), + .dataa(gnd), + .datab(counter[9]), .datac(gnd), .datad(vcc), - .cin(\Add0~17 ), - .combout(\Add0~18_combout ), - .cout(\Add0~19 )); + .cin(\counter[8]~36 ), + .combout(\counter[9]~37_combout ), + .cout(\counter[9]~38 )); // synopsys translate_off -defparam \Add0~18 .lut_mask = 16'h5A5F; -defparam \Add0~18 .sum_lutc_input = "cin"; +defparam \counter[9]~37 .lut_mask = 16'hC30C; +defparam \counter[9]~37 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y18_N31 +// Location: FF_X28_Y18_N29 dffeas \counter[9] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~18_combout ), + .d(\counter[9]~37_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -655,28 +724,28 @@ defparam \counter[9] .is_wysiwyg = "true"; defparam \counter[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N0 -cycloneive_lcell_comb \Add0~20 ( +// Location: LCCOMB_X28_Y18_N30 +cycloneive_lcell_comb \counter[10]~39 ( // Equation(s): -// \Add0~20_combout = (counter[10] & (\Add0~19 $ (GND))) # (!counter[10] & (!\Add0~19 & VCC)) -// \Add0~21 = CARRY((counter[10] & !\Add0~19 )) +// \counter[10]~39_combout = (counter[10] & (!\counter[9]~38 )) # (!counter[10] & ((\counter[9]~38 ) # (GND))) +// \counter[10]~40 = CARRY((!\counter[9]~38 ) # (!counter[10])) - .dataa(gnd), - .datab(counter[10]), + .dataa(counter[10]), + .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\Add0~19 ), - .combout(\Add0~20_combout ), - .cout(\Add0~21 )); + .cin(\counter[9]~38 ), + .combout(\counter[10]~39_combout ), + .cout(\counter[10]~40 )); // synopsys translate_off -defparam \Add0~20 .lut_mask = 16'hC30C; -defparam \Add0~20 .sum_lutc_input = "cin"; +defparam \counter[10]~39 .lut_mask = 16'h5A5F; +defparam \counter[10]~39 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y17_N1 +// Location: FF_X28_Y18_N31 dffeas \counter[10] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~20_combout ), + .d(\counter[10]~39_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -692,28 +761,45 @@ defparam \counter[10] .is_wysiwyg = "true"; defparam \counter[10] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N2 -cycloneive_lcell_comb \Add0~22 ( +// Location: LCCOMB_X28_Y17_N0 +cycloneive_lcell_comb \counter[11]~41 ( // Equation(s): -// \Add0~22_combout = (counter[11] & (!\Add0~21 )) # (!counter[11] & ((\Add0~21 ) # (GND))) -// \Add0~23 = CARRY((!\Add0~21 ) # (!counter[11])) +// \counter[11]~41_combout = (counter[11] & (\counter[10]~40 $ (GND))) # (!counter[11] & (!\counter[10]~40 & VCC)) +// \counter[11]~42 = CARRY((counter[11] & !\counter[10]~40 )) - .dataa(gnd), - .datab(counter[11]), + .dataa(counter[11]), + .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\Add0~21 ), - .combout(\Add0~22_combout ), - .cout(\Add0~23 )); + .cin(\counter[10]~40 ), + .combout(\counter[11]~41_combout ), + .cout(\counter[11]~42 )); // synopsys translate_off -defparam \Add0~22 .lut_mask = 16'h3C3F; -defparam \Add0~22 .sum_lutc_input = "cin"; +defparam \counter[11]~41 .lut_mask = 16'hA50A; +defparam \counter[11]~41 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y17_N3 +// Location: LCCOMB_X28_Y18_N4 +cycloneive_lcell_comb \counter[11]~feeder ( +// Equation(s): +// \counter[11]~feeder_combout = \counter[11]~41_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\counter[11]~41_combout ), + .cin(gnd), + .combout(\counter[11]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \counter[11]~feeder .lut_mask = 16'hFF00; +defparam \counter[11]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N5 dffeas \counter[11] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~22_combout ), + .d(\counter[11]~feeder_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -729,28 +815,28 @@ defparam \counter[11] .is_wysiwyg = "true"; defparam \counter[11] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N4 -cycloneive_lcell_comb \Add0~24 ( +// Location: LCCOMB_X28_Y17_N2 +cycloneive_lcell_comb \counter[12]~43 ( // Equation(s): -// \Add0~24_combout = (counter[12] & (\Add0~23 $ (GND))) # (!counter[12] & (!\Add0~23 & VCC)) -// \Add0~25 = CARRY((counter[12] & !\Add0~23 )) +// \counter[12]~43_combout = (counter[12] & (!\counter[11]~42 )) # (!counter[12] & ((\counter[11]~42 ) # (GND))) +// \counter[12]~44 = CARRY((!\counter[11]~42 ) # (!counter[12])) .dataa(gnd), .datab(counter[12]), .datac(gnd), .datad(vcc), - .cin(\Add0~23 ), - .combout(\Add0~24_combout ), - .cout(\Add0~25 )); + .cin(\counter[11]~42 ), + .combout(\counter[12]~43_combout ), + .cout(\counter[12]~44 )); // synopsys translate_off -defparam \Add0~24 .lut_mask = 16'hC30C; -defparam \Add0~24 .sum_lutc_input = "cin"; +defparam \counter[12]~43 .lut_mask = 16'h3C3F; +defparam \counter[12]~43 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y17_N5 +// Location: FF_X28_Y17_N3 dffeas \counter[12] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~24_combout ), + .d(\counter[12]~43_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -766,28 +852,28 @@ defparam \counter[12] .is_wysiwyg = "true"; defparam \counter[12] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N6 -cycloneive_lcell_comb \Add0~26 ( +// Location: LCCOMB_X28_Y17_N4 +cycloneive_lcell_comb \counter[13]~45 ( // Equation(s): -// \Add0~26_combout = (counter[13] & (!\Add0~25 )) # (!counter[13] & ((\Add0~25 ) # (GND))) -// \Add0~27 = CARRY((!\Add0~25 ) # (!counter[13])) +// \counter[13]~45_combout = (counter[13] & (\counter[12]~44 $ (GND))) # (!counter[13] & (!\counter[12]~44 & VCC)) +// \counter[13]~46 = CARRY((counter[13] & !\counter[12]~44 )) .dataa(gnd), .datab(counter[13]), .datac(gnd), .datad(vcc), - .cin(\Add0~25 ), - .combout(\Add0~26_combout ), - .cout(\Add0~27 )); + .cin(\counter[12]~44 ), + .combout(\counter[13]~45_combout ), + .cout(\counter[13]~46 )); // synopsys translate_off -defparam \Add0~26 .lut_mask = 16'h3C3F; -defparam \Add0~26 .sum_lutc_input = "cin"; +defparam \counter[13]~45 .lut_mask = 16'hC30C; +defparam \counter[13]~45 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y17_N7 +// Location: FF_X28_Y17_N5 dffeas \counter[13] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~26_combout ), + .d(\counter[13]~45_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -803,28 +889,28 @@ defparam \counter[13] .is_wysiwyg = "true"; defparam \counter[13] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N8 -cycloneive_lcell_comb \Add0~28 ( +// Location: LCCOMB_X28_Y17_N6 +cycloneive_lcell_comb \counter[14]~47 ( // Equation(s): -// \Add0~28_combout = (counter[14] & (\Add0~27 $ (GND))) # (!counter[14] & (!\Add0~27 & VCC)) -// \Add0~29 = CARRY((counter[14] & !\Add0~27 )) +// \counter[14]~47_combout = (counter[14] & (!\counter[13]~46 )) # (!counter[14] & ((\counter[13]~46 ) # (GND))) +// \counter[14]~48 = CARRY((!\counter[13]~46 ) # (!counter[14])) .dataa(counter[14]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\Add0~27 ), - .combout(\Add0~28_combout ), - .cout(\Add0~29 )); + .cin(\counter[13]~46 ), + .combout(\counter[14]~47_combout ), + .cout(\counter[14]~48 )); // synopsys translate_off -defparam \Add0~28 .lut_mask = 16'hA50A; -defparam \Add0~28 .sum_lutc_input = "cin"; +defparam \counter[14]~47 .lut_mask = 16'h5A5F; +defparam \counter[14]~47 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y17_N9 +// Location: FF_X28_Y17_N7 dffeas \counter[14] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~28_combout ), + .d(\counter[14]~47_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -840,28 +926,28 @@ defparam \counter[14] .is_wysiwyg = "true"; defparam \counter[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N10 -cycloneive_lcell_comb \Add0~30 ( +// Location: LCCOMB_X28_Y17_N8 +cycloneive_lcell_comb \counter[15]~49 ( // Equation(s): -// \Add0~30_combout = (counter[15] & (!\Add0~29 )) # (!counter[15] & ((\Add0~29 ) # (GND))) -// \Add0~31 = CARRY((!\Add0~29 ) # (!counter[15])) +// \counter[15]~49_combout = (counter[15] & (\counter[14]~48 $ (GND))) # (!counter[15] & (!\counter[14]~48 & VCC)) +// \counter[15]~50 = CARRY((counter[15] & !\counter[14]~48 )) .dataa(gnd), .datab(counter[15]), .datac(gnd), .datad(vcc), - .cin(\Add0~29 ), - .combout(\Add0~30_combout ), - .cout(\Add0~31 )); + .cin(\counter[14]~48 ), + .combout(\counter[15]~49_combout ), + .cout(\counter[15]~50 )); // synopsys translate_off -defparam \Add0~30 .lut_mask = 16'h3C3F; -defparam \Add0~30 .sum_lutc_input = "cin"; +defparam \counter[15]~49 .lut_mask = 16'hC30C; +defparam \counter[15]~49 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y17_N11 +// Location: FF_X28_Y17_N9 dffeas \counter[15] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~30_combout ), + .d(\counter[15]~49_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -877,28 +963,28 @@ defparam \counter[15] .is_wysiwyg = "true"; defparam \counter[15] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N12 -cycloneive_lcell_comb \Add0~32 ( +// Location: LCCOMB_X28_Y17_N10 +cycloneive_lcell_comb \counter[16]~51 ( // Equation(s): -// \Add0~32_combout = (counter[16] & (\Add0~31 $ (GND))) # (!counter[16] & (!\Add0~31 & VCC)) -// \Add0~33 = CARRY((counter[16] & !\Add0~31 )) +// \counter[16]~51_combout = (counter[16] & (!\counter[15]~50 )) # (!counter[16] & ((\counter[15]~50 ) # (GND))) +// \counter[16]~52 = CARRY((!\counter[15]~50 ) # (!counter[16])) - .dataa(gnd), - .datab(counter[16]), + .dataa(counter[16]), + .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\Add0~31 ), - .combout(\Add0~32_combout ), - .cout(\Add0~33 )); + .cin(\counter[15]~50 ), + .combout(\counter[16]~51_combout ), + .cout(\counter[16]~52 )); // synopsys translate_off -defparam \Add0~32 .lut_mask = 16'hC30C; -defparam \Add0~32 .sum_lutc_input = "cin"; +defparam \counter[16]~51 .lut_mask = 16'h5A5F; +defparam \counter[16]~51 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y17_N13 +// Location: FF_X28_Y17_N11 dffeas \counter[16] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~32_combout ), + .d(\counter[16]~51_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -914,28 +1000,28 @@ defparam \counter[16] .is_wysiwyg = "true"; defparam \counter[16] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N14 -cycloneive_lcell_comb \Add0~34 ( +// Location: LCCOMB_X28_Y17_N12 +cycloneive_lcell_comb \counter[17]~53 ( // Equation(s): -// \Add0~34_combout = (counter[17] & (!\Add0~33 )) # (!counter[17] & ((\Add0~33 ) # (GND))) -// \Add0~35 = CARRY((!\Add0~33 ) # (!counter[17])) +// \counter[17]~53_combout = (counter[17] & (\counter[16]~52 $ (GND))) # (!counter[17] & (!\counter[16]~52 & VCC)) +// \counter[17]~54 = CARRY((counter[17] & !\counter[16]~52 )) .dataa(counter[17]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\Add0~33 ), - .combout(\Add0~34_combout ), - .cout(\Add0~35 )); + .cin(\counter[16]~52 ), + .combout(\counter[17]~53_combout ), + .cout(\counter[17]~54 )); // synopsys translate_off -defparam \Add0~34 .lut_mask = 16'h5A5F; -defparam \Add0~34 .sum_lutc_input = "cin"; +defparam \counter[17]~53 .lut_mask = 16'hA50A; +defparam \counter[17]~53 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y17_N15 +// Location: FF_X28_Y17_N13 dffeas \counter[17] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~34_combout ), + .d(\counter[17]~53_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -951,28 +1037,28 @@ defparam \counter[17] .is_wysiwyg = "true"; defparam \counter[17] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N16 -cycloneive_lcell_comb \Add0~36 ( +// Location: LCCOMB_X28_Y17_N14 +cycloneive_lcell_comb \counter[18]~55 ( // Equation(s): -// \Add0~36_combout = (counter[18] & (\Add0~35 $ (GND))) # (!counter[18] & (!\Add0~35 & VCC)) -// \Add0~37 = CARRY((counter[18] & !\Add0~35 )) +// \counter[18]~55_combout = (counter[18] & (!\counter[17]~54 )) # (!counter[18] & ((\counter[17]~54 ) # (GND))) +// \counter[18]~56 = CARRY((!\counter[17]~54 ) # (!counter[18])) - .dataa(counter[18]), - .datab(gnd), + .dataa(gnd), + .datab(counter[18]), .datac(gnd), .datad(vcc), - .cin(\Add0~35 ), - .combout(\Add0~36_combout ), - .cout(\Add0~37 )); + .cin(\counter[17]~54 ), + .combout(\counter[18]~55_combout ), + .cout(\counter[18]~56 )); // synopsys translate_off -defparam \Add0~36 .lut_mask = 16'hA50A; -defparam \Add0~36 .sum_lutc_input = "cin"; +defparam \counter[18]~55 .lut_mask = 16'h3C3F; +defparam \counter[18]~55 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y17_N17 +// Location: FF_X28_Y17_N15 dffeas \counter[18] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~36_combout ), + .d(\counter[18]~55_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -988,28 +1074,28 @@ defparam \counter[18] .is_wysiwyg = "true"; defparam \counter[18] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N18 -cycloneive_lcell_comb \Add0~38 ( +// Location: LCCOMB_X28_Y17_N16 +cycloneive_lcell_comb \counter[19]~57 ( // Equation(s): -// \Add0~38_combout = (counter[19] & (!\Add0~37 )) # (!counter[19] & ((\Add0~37 ) # (GND))) -// \Add0~39 = CARRY((!\Add0~37 ) # (!counter[19])) +// \counter[19]~57_combout = (counter[19] & (\counter[18]~56 $ (GND))) # (!counter[19] & (!\counter[18]~56 & VCC)) +// \counter[19]~58 = CARRY((counter[19] & !\counter[18]~56 )) - .dataa(counter[19]), - .datab(gnd), + .dataa(gnd), + .datab(counter[19]), .datac(gnd), .datad(vcc), - .cin(\Add0~37 ), - .combout(\Add0~38_combout ), - .cout(\Add0~39 )); + .cin(\counter[18]~56 ), + .combout(\counter[19]~57_combout ), + .cout(\counter[19]~58 )); // synopsys translate_off -defparam \Add0~38 .lut_mask = 16'h5A5F; -defparam \Add0~38 .sum_lutc_input = "cin"; +defparam \counter[19]~57 .lut_mask = 16'hC30C; +defparam \counter[19]~57 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y17_N19 +// Location: FF_X28_Y17_N17 dffeas \counter[19] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~38_combout ), + .d(\counter[19]~57_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1025,32 +1111,15 @@ defparam \counter[19] .is_wysiwyg = "true"; defparam \counter[19] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N20 -cycloneive_lcell_comb \Add0~40 ( -// Equation(s): -// \Add0~40_combout = \Add0~39 $ (!counter[20]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(counter[20]), - .cin(\Add0~39 ), - .combout(\Add0~40_combout ), - .cout()); -// synopsys translate_off -defparam \Add0~40 .lut_mask = 16'hF00F; -defparam \Add0~40 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N28 +// Location: LCCOMB_X28_Y17_N28 cycloneive_lcell_comb \Equal0~5 ( // Equation(s): -// \Equal0~5_combout = (!\Add0~32_combout & (!\Add0~36_combout & (!\Add0~34_combout & !\Add0~38_combout ))) +// \Equal0~5_combout = (!counter[17] & (!counter[19] & (!counter[18] & !counter[16]))) - .dataa(\Add0~32_combout ), - .datab(\Add0~36_combout ), - .datac(\Add0~34_combout ), - .datad(\Add0~38_combout ), + .dataa(counter[17]), + .datab(counter[19]), + .datac(counter[18]), + .datad(counter[16]), .cin(gnd), .combout(\Equal0~5_combout ), .cout()); @@ -1059,32 +1128,15 @@ defparam \Equal0~5 .lut_mask = 16'h0001; defparam \Equal0~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y18_N6 -cycloneive_lcell_comb \Equal0~1 ( -// Equation(s): -// \Equal0~1_combout = (!\Add0~10_combout & (!\Add0~8_combout & (!\Add0~14_combout & !\Add0~12_combout ))) - - .dataa(\Add0~10_combout ), - .datab(\Add0~8_combout ), - .datac(\Add0~14_combout ), - .datad(\Add0~12_combout ), - .cin(gnd), - .combout(\Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \Equal0~1 .lut_mask = 16'h0001; -defparam \Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N4 +// Location: LCCOMB_X28_Y18_N8 cycloneive_lcell_comb \Equal0~0 ( // Equation(s): -// \Equal0~0_combout = (!\Add0~4_combout & (!\Add0~0_combout & (!\Add0~6_combout & !\Add0~2_combout ))) +// \Equal0~0_combout = (!counter[1] & (!counter[0] & (!counter[2] & !counter[3]))) - .dataa(\Add0~4_combout ), - .datab(\Add0~0_combout ), - .datac(\Add0~6_combout ), - .datad(\Add0~2_combout ), + .dataa(counter[1]), + .datab(counter[0]), + .datac(counter[2]), + .datad(counter[3]), .cin(gnd), .combout(\Equal0~0_combout ), .cout()); @@ -1093,15 +1145,32 @@ defparam \Equal0~0 .lut_mask = 16'h0001; defparam \Equal0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N30 +// Location: LCCOMB_X28_Y18_N6 +cycloneive_lcell_comb \Equal0~1 ( +// Equation(s): +// \Equal0~1_combout = (!counter[6] & (!counter[7] & (!counter[5] & !counter[4]))) + + .dataa(counter[6]), + .datab(counter[7]), + .datac(counter[5]), + .datad(counter[4]), + .cin(gnd), + .combout(\Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~1 .lut_mask = 16'h0001; +defparam \Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N0 cycloneive_lcell_comb \Equal0~2 ( // Equation(s): -// \Equal0~2_combout = (!\Add0~22_combout & (!\Add0~16_combout & (!\Add0~20_combout & !\Add0~18_combout ))) +// \Equal0~2_combout = (!counter[8] & (!counter[11] & (!counter[10] & !counter[9]))) - .dataa(\Add0~22_combout ), - .datab(\Add0~16_combout ), - .datac(\Add0~20_combout ), - .datad(\Add0~18_combout ), + .dataa(counter[8]), + .datab(counter[11]), + .datac(counter[10]), + .datad(counter[9]), .cin(gnd), .combout(\Equal0~2_combout ), .cout()); @@ -1110,15 +1179,15 @@ defparam \Equal0~2 .lut_mask = 16'h0001; defparam \Equal0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N30 +// Location: LCCOMB_X28_Y17_N26 cycloneive_lcell_comb \Equal0~3 ( // Equation(s): -// \Equal0~3_combout = (!\Add0~26_combout & (!\Add0~24_combout & (!\Add0~28_combout & !\Add0~30_combout ))) +// \Equal0~3_combout = (!counter[14] & (!counter[13] & (!counter[15] & !counter[12]))) - .dataa(\Add0~26_combout ), - .datab(\Add0~24_combout ), - .datac(\Add0~28_combout ), - .datad(\Add0~30_combout ), + .dataa(counter[14]), + .datab(counter[13]), + .datac(counter[15]), + .datad(counter[12]), .cin(gnd), .combout(\Equal0~3_combout ), .cout()); @@ -1127,13 +1196,13 @@ defparam \Equal0~3 .lut_mask = 16'h0001; defparam \Equal0~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N28 +// Location: LCCOMB_X29_Y18_N28 cycloneive_lcell_comb \Equal0~4 ( // Equation(s): -// \Equal0~4_combout = (\Equal0~1_combout & (\Equal0~0_combout & (\Equal0~2_combout & \Equal0~3_combout ))) +// \Equal0~4_combout = (\Equal0~0_combout & (\Equal0~1_combout & (\Equal0~2_combout & \Equal0~3_combout ))) - .dataa(\Equal0~1_combout ), - .datab(\Equal0~0_combout ), + .dataa(\Equal0~0_combout ), + .datab(\Equal0~1_combout ), .datac(\Equal0~2_combout ), .datad(\Equal0~3_combout ), .cin(gnd), @@ -1144,27 +1213,117 @@ defparam \Equal0~4 .lut_mask = 16'h8000; defparam \Equal0~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N20 -cycloneive_lcell_comb \address[0]~0 ( +// Location: LCCOMB_X28_Y17_N18 +cycloneive_lcell_comb \counter[20]~59 ( // Equation(s): -// \address[0]~0_combout = address[0] $ (((!\Add0~40_combout & (\Equal0~5_combout & \Equal0~4_combout )))) +// \counter[20]~59_combout = (counter[20] & (!\counter[19]~58 )) # (!counter[20] & ((\counter[19]~58 ) # (GND))) +// \counter[20]~60 = CARRY((!\counter[19]~58 ) # (!counter[20])) - .dataa(\Add0~40_combout ), - .datab(\Equal0~5_combout ), - .datac(address[0]), - .datad(\Equal0~4_combout ), - .cin(gnd), - .combout(\address[0]~0_combout ), - .cout()); + .dataa(gnd), + .datab(counter[20]), + .datac(gnd), + .datad(vcc), + .cin(\counter[19]~58 ), + .combout(\counter[20]~59_combout ), + .cout(\counter[20]~60 )); // synopsys translate_off -defparam \address[0]~0 .lut_mask = 16'hB4F0; -defparam \address[0]~0 .sum_lutc_input = "datac"; +defparam \counter[20]~59 .lut_mask = 16'h3C3F; +defparam \counter[20]~59 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X32_Y17_N21 +// Location: FF_X28_Y17_N19 +dffeas \counter[20] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\counter[20]~59_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[20]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[20] .is_wysiwyg = "true"; +defparam \counter[20] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N20 +cycloneive_lcell_comb \counter[21]~61 ( +// Equation(s): +// \counter[21]~61_combout = \counter[20]~60 $ (!counter[21]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(counter[21]), + .cin(\counter[20]~60 ), + .combout(\counter[21]~61_combout ), + .cout()); +// synopsys translate_off +defparam \counter[21]~61 .lut_mask = 16'hF00F; +defparam \counter[21]~61 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X28_Y17_N21 +dffeas \counter[21] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\counter[21]~61_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[21]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[21] .is_wysiwyg = "true"; +defparam \counter[21] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N10 +cycloneive_lcell_comb \Equal0~7 ( +// Equation(s): +// \Equal0~7_combout = (!counter[21] & !counter[20]) + + .dataa(gnd), + .datab(gnd), + .datac(counter[21]), + .datad(counter[20]), + .cin(gnd), + .combout(\Equal0~7_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~7 .lut_mask = 16'h000F; +defparam \Equal0~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N30 +cycloneive_lcell_comb \address[0]~39 ( +// Equation(s): +// \address[0]~39_combout = address[0] $ (((\Equal0~5_combout & (\Equal0~4_combout & \Equal0~7_combout )))) + + .dataa(\Equal0~5_combout ), + .datab(\Equal0~4_combout ), + .datac(address[0]), + .datad(\Equal0~7_combout ), + .cin(gnd), + .combout(\address[0]~39_combout ), + .cout()); +// synopsys translate_off +defparam \address[0]~39 .lut_mask = 16'h78F0; +defparam \address[0]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y18_N31 dffeas \address[0] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[0]~0_combout ), + .d(\address[0]~39_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1180,67 +1339,51 @@ defparam \address[0] .is_wysiwyg = "true"; defparam \address[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N26 +// Location: LCCOMB_X29_Y18_N0 +cycloneive_lcell_comb \address[1]~13 ( +// Equation(s): +// \address[1]~13_combout = (address[0] & (address[1] $ (VCC))) # (!address[0] & (address[1] & VCC)) +// \address[1]~14 = CARRY((address[0] & address[1])) + + .dataa(address[0]), + .datab(address[1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\address[1]~13_combout ), + .cout(\address[1]~14 )); +// synopsys translate_off +defparam \address[1]~13 .lut_mask = 16'h6688; +defparam \address[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N26 cycloneive_lcell_comb \Equal0~6 ( // Equation(s): -// \Equal0~6_combout = (!\Add0~34_combout & !\Add0~32_combout ) +// \Equal0~6_combout = (!counter[20] & (!counter[21] & (\Equal0~5_combout & \Equal0~4_combout ))) - .dataa(gnd), - .datab(gnd), - .datac(\Add0~34_combout ), - .datad(\Add0~32_combout ), + .dataa(counter[20]), + .datab(counter[21]), + .datac(\Equal0~5_combout ), + .datad(\Equal0~4_combout ), .cin(gnd), .combout(\Equal0~6_combout ), .cout()); // synopsys translate_off -defparam \Equal0~6 .lut_mask = 16'h000F; +defparam \Equal0~6 .lut_mask = 16'h1000; defparam \Equal0~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N24 -cycloneive_lcell_comb \Equal0~7 ( -// Equation(s): -// \Equal0~7_combout = (!\Add0~40_combout & (!\Add0~36_combout & (\Equal0~6_combout & !\Add0~38_combout ))) - - .dataa(\Add0~40_combout ), - .datab(\Add0~36_combout ), - .datac(\Equal0~6_combout ), - .datad(\Add0~38_combout ), - .cin(gnd), - .combout(\Equal0~7_combout ), - .cout()); -// synopsys translate_off -defparam \Equal0~7 .lut_mask = 16'h0010; -defparam \Equal0~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N10 -cycloneive_lcell_comb \address[1]~1 ( -// Equation(s): -// \address[1]~1_combout = address[1] $ (((address[0] & (\Equal0~4_combout & \Equal0~7_combout )))) - - .dataa(address[0]), - .datab(\Equal0~4_combout ), - .datac(address[1]), - .datad(\Equal0~7_combout ), - .cin(gnd), - .combout(\address[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \address[1]~1 .lut_mask = 16'h78F0; -defparam \address[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N11 +// Location: FF_X29_Y18_N1 dffeas \address[1] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[1]~1_combout ), + .d(\address[1]~13_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(vcc), + .ena(\Equal0~6_combout ), .devclrn(devclrn), .devpor(devpor), .q(address[1]), @@ -1250,50 +1393,34 @@ defparam \address[1] .is_wysiwyg = "true"; defparam \address[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N2 -cycloneive_lcell_comb \address[1]~2 ( +// Location: LCCOMB_X29_Y18_N2 +cycloneive_lcell_comb \address[2]~15 ( // Equation(s): -// \address[1]~2_combout = (address[0] & (\Equal0~5_combout & (!\Add0~40_combout & \Equal0~4_combout ))) - - .dataa(address[0]), - .datab(\Equal0~5_combout ), - .datac(\Add0~40_combout ), - .datad(\Equal0~4_combout ), - .cin(gnd), - .combout(\address[1]~2_combout ), - .cout()); -// synopsys translate_off -defparam \address[1]~2 .lut_mask = 16'h0800; -defparam \address[1]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N16 -cycloneive_lcell_comb \address[2]~3 ( -// Equation(s): -// \address[2]~3_combout = address[2] $ (((address[1] & \address[1]~2_combout ))) +// \address[2]~15_combout = (address[2] & (!\address[1]~14 )) # (!address[2] & ((\address[1]~14 ) # (GND))) +// \address[2]~16 = CARRY((!\address[1]~14 ) # (!address[2])) .dataa(gnd), - .datab(address[1]), - .datac(address[2]), - .datad(\address[1]~2_combout ), - .cin(gnd), - .combout(\address[2]~3_combout ), - .cout()); + .datab(address[2]), + .datac(gnd), + .datad(vcc), + .cin(\address[1]~14 ), + .combout(\address[2]~15_combout ), + .cout(\address[2]~16 )); // synopsys translate_off -defparam \address[2]~3 .lut_mask = 16'h3CF0; -defparam \address[2]~3 .sum_lutc_input = "datac"; +defparam \address[2]~15 .lut_mask = 16'h3C3F; +defparam \address[2]~15 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X32_Y17_N17 +// Location: FF_X29_Y18_N3 dffeas \address[2] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[2]~3_combout ), + .d(\address[2]~15_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(vcc), + .ena(\Equal0~6_combout ), .devclrn(devclrn), .devpor(devpor), .q(address[2]), @@ -1303,7 +1430,541 @@ defparam \address[2] .is_wysiwyg = "true"; defparam \address[2] .power_up = "low"; // synopsys translate_on -// Location: M9K_X33_Y26_N0 +// Location: LCCOMB_X29_Y18_N4 +cycloneive_lcell_comb \address[3]~17 ( +// Equation(s): +// \address[3]~17_combout = (address[3] & (\address[2]~16 $ (GND))) # (!address[3] & (!\address[2]~16 & VCC)) +// \address[3]~18 = CARRY((address[3] & !\address[2]~16 )) + + .dataa(gnd), + .datab(address[3]), + .datac(gnd), + .datad(vcc), + .cin(\address[2]~16 ), + .combout(\address[3]~17_combout ), + .cout(\address[3]~18 )); +// synopsys translate_off +defparam \address[3]~17 .lut_mask = 16'hC30C; +defparam \address[3]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y18_N5 +dffeas \address[3] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[3]~17_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(address[3]), + .prn(vcc)); +// synopsys translate_off +defparam \address[3] .is_wysiwyg = "true"; +defparam \address[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N6 +cycloneive_lcell_comb \address[4]~19 ( +// Equation(s): +// \address[4]~19_combout = (address[4] & (!\address[3]~18 )) # (!address[4] & ((\address[3]~18 ) # (GND))) +// \address[4]~20 = CARRY((!\address[3]~18 ) # (!address[4])) + + .dataa(address[4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\address[3]~18 ), + .combout(\address[4]~19_combout ), + .cout(\address[4]~20 )); +// synopsys translate_off +defparam \address[4]~19 .lut_mask = 16'h5A5F; +defparam \address[4]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y18_N7 +dffeas \address[4] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[4]~19_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(address[4]), + .prn(vcc)); +// synopsys translate_off +defparam \address[4] .is_wysiwyg = "true"; +defparam \address[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N8 +cycloneive_lcell_comb \address[5]~21 ( +// Equation(s): +// \address[5]~21_combout = (address[5] & (\address[4]~20 $ (GND))) # (!address[5] & (!\address[4]~20 & VCC)) +// \address[5]~22 = CARRY((address[5] & !\address[4]~20 )) + + .dataa(gnd), + .datab(address[5]), + .datac(gnd), + .datad(vcc), + .cin(\address[4]~20 ), + .combout(\address[5]~21_combout ), + .cout(\address[5]~22 )); +// synopsys translate_off +defparam \address[5]~21 .lut_mask = 16'hC30C; +defparam \address[5]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y18_N9 +dffeas \address[5] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[5]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(address[5]), + .prn(vcc)); +// synopsys translate_off +defparam \address[5] .is_wysiwyg = "true"; +defparam \address[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N10 +cycloneive_lcell_comb \address[6]~23 ( +// Equation(s): +// \address[6]~23_combout = (address[6] & (!\address[5]~22 )) # (!address[6] & ((\address[5]~22 ) # (GND))) +// \address[6]~24 = CARRY((!\address[5]~22 ) # (!address[6])) + + .dataa(address[6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\address[5]~22 ), + .combout(\address[6]~23_combout ), + .cout(\address[6]~24 )); +// synopsys translate_off +defparam \address[6]~23 .lut_mask = 16'h5A5F; +defparam \address[6]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y18_N11 +dffeas \address[6] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[6]~23_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(address[6]), + .prn(vcc)); +// synopsys translate_off +defparam \address[6] .is_wysiwyg = "true"; +defparam \address[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N12 +cycloneive_lcell_comb \address[7]~25 ( +// Equation(s): +// \address[7]~25_combout = (address[7] & (\address[6]~24 $ (GND))) # (!address[7] & (!\address[6]~24 & VCC)) +// \address[7]~26 = CARRY((address[7] & !\address[6]~24 )) + + .dataa(address[7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\address[6]~24 ), + .combout(\address[7]~25_combout ), + .cout(\address[7]~26 )); +// synopsys translate_off +defparam \address[7]~25 .lut_mask = 16'hA50A; +defparam \address[7]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y18_N13 +dffeas \address[7] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[7]~25_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(address[7]), + .prn(vcc)); +// synopsys translate_off +defparam \address[7] .is_wysiwyg = "true"; +defparam \address[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N14 +cycloneive_lcell_comb \address[8]~27 ( +// Equation(s): +// \address[8]~27_combout = (address[8] & (!\address[7]~26 )) # (!address[8] & ((\address[7]~26 ) # (GND))) +// \address[8]~28 = CARRY((!\address[7]~26 ) # (!address[8])) + + .dataa(gnd), + .datab(address[8]), + .datac(gnd), + .datad(vcc), + .cin(\address[7]~26 ), + .combout(\address[8]~27_combout ), + .cout(\address[8]~28 )); +// synopsys translate_off +defparam \address[8]~27 .lut_mask = 16'h3C3F; +defparam \address[8]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y18_N15 +dffeas \address[8] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[8]~27_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(address[8]), + .prn(vcc)); +// synopsys translate_off +defparam \address[8] .is_wysiwyg = "true"; +defparam \address[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N16 +cycloneive_lcell_comb \address[9]~29 ( +// Equation(s): +// \address[9]~29_combout = (address[9] & (\address[8]~28 $ (GND))) # (!address[9] & (!\address[8]~28 & VCC)) +// \address[9]~30 = CARRY((address[9] & !\address[8]~28 )) + + .dataa(gnd), + .datab(address[9]), + .datac(gnd), + .datad(vcc), + .cin(\address[8]~28 ), + .combout(\address[9]~29_combout ), + .cout(\address[9]~30 )); +// synopsys translate_off +defparam \address[9]~29 .lut_mask = 16'hC30C; +defparam \address[9]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y18_N17 +dffeas \address[9] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[9]~29_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(address[9]), + .prn(vcc)); +// synopsys translate_off +defparam \address[9] .is_wysiwyg = "true"; +defparam \address[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N18 +cycloneive_lcell_comb \address[10]~31 ( +// Equation(s): +// \address[10]~31_combout = (address[10] & (!\address[9]~30 )) # (!address[10] & ((\address[9]~30 ) # (GND))) +// \address[10]~32 = CARRY((!\address[9]~30 ) # (!address[10])) + + .dataa(gnd), + .datab(address[10]), + .datac(gnd), + .datad(vcc), + .cin(\address[9]~30 ), + .combout(\address[10]~31_combout ), + .cout(\address[10]~32 )); +// synopsys translate_off +defparam \address[10]~31 .lut_mask = 16'h3C3F; +defparam \address[10]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y18_N19 +dffeas \address[10] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[10]~31_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(address[10]), + .prn(vcc)); +// synopsys translate_off +defparam \address[10] .is_wysiwyg = "true"; +defparam \address[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N20 +cycloneive_lcell_comb \address[11]~33 ( +// Equation(s): +// \address[11]~33_combout = (address[11] & (\address[10]~32 $ (GND))) # (!address[11] & (!\address[10]~32 & VCC)) +// \address[11]~34 = CARRY((address[11] & !\address[10]~32 )) + + .dataa(gnd), + .datab(address[11]), + .datac(gnd), + .datad(vcc), + .cin(\address[10]~32 ), + .combout(\address[11]~33_combout ), + .cout(\address[11]~34 )); +// synopsys translate_off +defparam \address[11]~33 .lut_mask = 16'hC30C; +defparam \address[11]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y18_N21 +dffeas \address[11] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[11]~33_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(address[11]), + .prn(vcc)); +// synopsys translate_off +defparam \address[11] .is_wysiwyg = "true"; +defparam \address[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N22 +cycloneive_lcell_comb \address[12]~35 ( +// Equation(s): +// \address[12]~35_combout = (address[12] & (!\address[11]~34 )) # (!address[12] & ((\address[11]~34 ) # (GND))) +// \address[12]~36 = CARRY((!\address[11]~34 ) # (!address[12])) + + .dataa(address[12]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\address[11]~34 ), + .combout(\address[12]~35_combout ), + .cout(\address[12]~36 )); +// synopsys translate_off +defparam \address[12]~35 .lut_mask = 16'h5A5F; +defparam \address[12]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y18_N23 +dffeas \address[12] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[12]~35_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(address[12]), + .prn(vcc)); +// synopsys translate_off +defparam \address[12] .is_wysiwyg = "true"; +defparam \address[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N24 +cycloneive_lcell_comb \address[13]~37 ( +// Equation(s): +// \address[13]~37_combout = \address[12]~36 $ (!address[13]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(address[13]), + .cin(\address[12]~36 ), + .combout(\address[13]~37_combout ), + .cout()); +// synopsys translate_off +defparam \address[13]~37 .lut_mask = 16'hF00F; +defparam \address[13]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y18_N25 +dffeas \address[13] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[13]~37_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(address[13]), + .prn(vcc)); +// synopsys translate_off +defparam \address[13] .is_wysiwyg = "true"; +defparam \address[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N2 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = address[13] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(address[13]), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hFF00; +defparam \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y18_N3 +dffeas \rom|altsyncram_component|auto_generated|address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\rom|altsyncram_component|auto_generated|address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; +defparam \rom|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N24 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout = \rom|altsyncram_component|auto_generated|address_reg_a [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\rom|altsyncram_component|auto_generated|address_reg_a [0]), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .lut_mask = 16'hFF00; +defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y18_N25 +dffeas \rom|altsyncram_component|auto_generated|out_address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; +defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: M9K_X33_Y13_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h3C00000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005DB824E17CAAE881C1908A79F24B7D1B4857A981A6AF39DFF5A2FEE9141EB33592D8E9B82471FDDA6791810A1C29D415CC1A8FA03444DF0083F83506BA93E8D1A1856A768D73A08418BFB25A40001DD4833DAF33BD311BB45F39667627407EF59ED569C483EB3BE1B10551B1428A6169579293ED063CAA9C6ADB0433CFC15C33AFF04C710408C20AC28B5909A229CD7D1DB4EB9A44CE0EEDBBBD391D3128AAA3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'hDDE6FC8EBE3F9F3C3DFC6E8F07BFD31D50660B1E0B2506A533CE0E340C7C745CAEC4837C2A5FECBB94C1C969FFDDFF79BFFAAFDCA8D748399ABF75558ADD02F56F6DFFF29CB70FFD25A59DFFFED7B3F7E8B4CE6FFF3EF9CEC6BAE57ABFFFCEE647B2AFF5B87AA26AFFDD317DEDCFBDFFE1A0CAD3B58877DD2F647F7DF748E7CF4693FD3C1238FFAFBD7FDF567FA8FEF024F33AFD3AABC6B105EA80272D64895FFF9FFF6E3881C81AFDCF2257FD4F8ED5257D0E9B800726B6564D2B05012F76DF636CDEB4BDFCAEEFC61DFFEFB7E26262DEF2CB9F71565824FEBF3F7BDDEABB593F1BF746FBFFC353E37263FF38A796EF39E3FD7DFEBA7FFEFFBD97ABAF09E909; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'hE629BDF93D7F5B5BAF92FBAB477E9B315DB5A310CFACC7408DF9A544B1E57AF6EFEF92C2FA4D8D4E4AC86C277338FA37BCDD9D47782DB75EFF80781BCD23D0AFCAE30B9FE6AA29FFF6F72DA73DFE4F7ACD39687B9E69C5359E9B991F0246EFFBC5595561AC64787878F5CE14C664CF9EB0CDAFFBABEF1E83358371B9ED96E5069555AFBBD3AEBFCABFBBED7A5C5FE9BD0E6A91C6E7610042695EEB08D8881B1D735AF87DAE59FABBD7DEAF8717F2B72F428F5E37E5D6E13157B99CBD2D73B9C73C563C8B02C8CC39C64DDCEA1BEEB5E7353F93786145598FE634EF1000179B345725EA43CE18F187A1DE4DAABEA97963E3A7A96B8B7CBC095BEB7CE46274D9AF; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h4ED4AE2B1650D21EAFE01E7099EFCA3094FD4D705CF6B84AE21583E13385F8650004406BD60A023AB063D4E5966EA41AA997F5A49BFCB0657A9732D28EB8217E65F627A15E1057ADEE7B9E27122A58FB2B98B1EA560390C7E87715861814E04DCB76FAB179E9619BC7E7E9C9FD801CF87DBA1EA496E829D4E62861E1AF436A7585287860729C77B6C68CAEA3033A6E84D67249B594C407B39C68B4C1C97FDEFC6BAD12FDBB525EF4F87F4A23EC13CBC0262D8899A3A290F04F41C1324045B9FCEEC890579E95D5A0A546CCCDD48577558ABE7CA36EF67A70F6A8758BDA052D5B95DE707778B17C2379847A23AE5D4BB01F36F3F44A8162566D9FB15DE7CC83F7; +// synopsys translate_on + +// Location: M9K_X33_Y14_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( .portawe(vcc), .portare(vcc), @@ -1313,46 +1974,978 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(vcc), + .ena0(!address[13]), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain(18'b000000000000000000), - .portaaddr({address[2],address[1],address[0]}), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), .portabyteenamasks(1'b1), - .portbdatain(18'b000000000000000000), - .portbaddr(3'b000), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "./rom/gw03.hex"; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom"; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 18; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 18; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 144'h002040042000900018000600024001080081; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h1EEA3633EFEA856D05BA968C1B3C30CA1788DD95D16B8F914DDDFC3EE5C69945DF7D7BF31C6072BFA7993996AB7DD2F3EE4009844CC9D6CF9E583AEC48A52F2904B57D8E0D755851232838F9B5348838530D7AF95411555D263B8CA86A5D29D7CE4B65409D6F04C5709A56C241C3BCEF07459A416EB4E8F3D73CC714F4333AFE605D53A5C955D5D1412F8361617A54446971FD187442A60FB04457857BECC3120A01FDC7FE2CBF038A61DEE5FCE2D10C8F35FBF80C05ABFF4B6935287B125E8D56F9FDFE7D64C1F4E1F5641845CD17E836B97780400C702523FA8E7C7BBD6F0666591A35ADD26B6B7E33CA56E9AB329EFA7E68F98AE7CE9507755C74C430286A; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h88537A811D4EF6CD9668CCD3E2E7A8041788DCA5F7E08AF52AF5276078304DEB75B74BB9AC3C1A492952F7EEAA0E7CF9FBEDD0FB47EEFDCC3734B816F355C913CD2E1AF14C30545297A91BED3AEAEFF8F696B5F4FC80BC6B1A2559492E9198E4A5875745B625C6CA7A7292332492D139728A689DA1AE78B6B44CE4F4A4EA5A22F331598B364EF27516CC49A4662C5E5C92ED140D96373678F833AE434698237599716B8CBAE2D3D061F2C3D6337AB435B5C2144AB6FA2F8BB51357801066B6589467DA6C480E6D19CEEA8451CEFA88FD70E7925B0302F877F87FA833FBD147E937309C08305A10187707E3D57DDE4931F1D9E97A8F378981ABBF8D7B6B7539C3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h763DD7AA7EED3F4AD4EA7491ADE6F14E6DBADD0F090A8DF34D7BAD35DD2275F0BCCF19EEF299751C919C9C13C6FB9ED711AC4DA7D947CC79E9B6323EF6CE62638CEBCB187AE5D44ECA689C9BD4E5AE544DEA7E90D186B9F335F3323877AAD54196CE81973CB555904419599375501366EC343561BCF83357F8823671393B278C1C387A7970C7F3E688673CF5975EE3E5FF105CFCCFAB725D698FB088B063063C7833830C7B2C7AFB8A8D203C312306DA0E72641FFB93D59B5EC84F44AD55F4B884735325ACC969B2EAE10A1478D866F667DDEF7BBF75E6958B6D02DC6D0F807660A229B98541E6FE734DE2280A9B57FCD5A9BEFEF7CDA5ABEB44FD73D2794D56; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hD0734B461A36980411EB2A6C1BE76029258777EF227A8F6E84F74C4436098F67BA611013110188547995B108BB2DAE76F423A0D98845F9248BDFA45E10CA403A5E2B1A3E16869E1D37BCE906B82F401CBD467617DB34D9E0C80B5E6E10063EC4BD52921D249E377D95CFAAA309EEDAA57DA85F55DBB7048A69A4C801013948B617F7F5724D40707E6FF30002982023020449B4680C45D1CE6D8EB30A061DB8FEDD6E630C15271E48CA801988654FB501D5393392EE765C1EC95C1E4D86F18A965372B72B484E2F2664B735B69A5AB532B086BA4C62AD6D56EECBDB6984B251454845BD5B243DAED2B2489B313A35C50252AFD3E0B76FEF342335C7F1321D92FF; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N24 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout )) # +// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ))) + + .dataa(gnd), + .datab(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0 .lut_mask = 16'hF3C0; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y19_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h35C65240B61076066A23CE4CFC5E76063A1C2AE07DF555007338BDC080EA0C23082C891C76A4845096304A0D8502080C1198911998821D09C29CA830C337499236E0548D65FF9125A765F0220F6EB9D1B318244CC6CA2CBC9CEC6979C14EB28DE2E0440C6CBD61341FC178649A852D4A2A0627C688D905B882524E191E7951EAEF30312A73337CBAD4838F42A3293859CD169240D8E652F6D72D8D19D56DD7675939FC47C933E1B0AEF12A484454C247B00A6BEC5402AA08B5106E3065602454C80CEC08A7F5F85CE65326632B4C4F3920019A35AE2AEB321131046EE45B81D4EFD5995634050D4CFEC166B032B6415553AF0358304080D9DD0A2E5948593830; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h376E511217E00B624A46BA2E4CC10B729C326F710F24CFE78C5E63F3024B17CC5E1380C938A0A16C9B696272DE7A2948BE8AFE81310146B8AAE5E549FA27EFBE27929938B8E10530250877A4998D0DF0004852125C20CA8D4279881E41208B14198817644F293AC1946061117122A39D8841818C1389D51BDAC549181902516571163594CEC5863F0F56625E221D6B8180848C6B2BE24AA0AEEE5D187201CAAE6AA394A8644314895565192AE415630A42894D6EF21343903B348EED8642F2310644C9567C0BF9911B870B989C59330089AA4C8065AB1B11132213EE0FD830817DE6C2ED45D76325CA2A8E198859334553AB02945CAB1F17C142288008073004; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h20721F982534A8179F13E2C6328CDE7D2A73087D3A9314419022103DFF7677769FE2D1F27443253D58403577C801AE23371F00290A17E1C4A40258BFD204230EE9969472A81B83113144528F831AA6C3221E137C1E9C670E26809A894013828D9E2DBCBF62498A769893D7218899245CD18AE49F0146517422EE475D520029ED39BCEF6BF4D23532957455F1C80115524179D59C4C4534DF7296991146CE24508366123AA809AB30B47977571C5D70397A93C723106D0A2C254714359DC7C9E13AE624C94932927924D20024CD638A05C8620023319662D80E05805625BC4A4006C78011F78D8B82E59F0CD4B32D6801669BE3EB0B96960DFF152005EC7C16CB; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h9C8CA06AA05B63C89A59A3E4E80807B27A70B0006624C4AC4A0595CCD8CA20824CA272352720BCD900A6D79BFD9D0595EC0D044ABC8CC28E9AE946E3D2000A4EFA4F91915C6AC9D8570C292F10848189906127BCBE06FFE92DAFB4AAFB240D88DDBB7B207EFA1709B05E1C4801BD45625A36BB62220506E171891964A31BED2215408676F600F490FAA59B488C7998CC8CCC28922AC62644EEBB432EEECB51B16CDEE7468681D6C31E4991CA3736E9ACB7531EC6D8BBCD453718101EA25D79278C6AC955A8A6140421573E413CF5A80AA1436D8B4C31A2AB26D2A61CE834248BAD5751BD429B4F61318427560CE39D49299002165212181064E24FF0093B997B; +// synopsys translate_on + +// Location: M9K_X22_Y16_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h420000004200000000000000000080000000000000000000000000000030004480000000424202423E1E3E02304C3C0C3C7E7E40403E427E3402421824347C1C0400280000003C3406303220344C403C0400100010100000005062742400000091991809FB3BD9084A1241F5015988B3C506031934089E0E1FA8043DDAF2CC07D94A6F2B1D133C211222B22C787D430E45D4C53282288077DFC0F704AAD55127A2BEAEA114958D2817AB1213183A4E1A15E3690A08A33B429284A202011A1243D49CACA1C0A441405A720D21A0921294045F746229E287B95E956AA3DE0CA3B7A019C8039C4DDA6BC99371248CC6008A54CB84503442C4F91309238ECB252072; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h81F3167814687CBD683E54D44555E6C95B5F2A72C0C193C6110C0221A448D0C9A0D8E36A84D5C61285128845215F8F8821C308E368283D8E2B42989C04A8B51354E09A38775020189010680840800297C31282442326D008D1F2351A89FFD7C16087F8B130F04418C0A1C082FC005843F5B42CADD9455ADBD328C13219110DE100D988737BBB44C414210118C673B0C1BDF76C499226F78FF41A0AF7AFD3308AAA0AAA22B1C70003F542A66FD1F1CF9D4578315F8C1C6FEC3EDB9B322CB204821A94A248414CE030020F207BF040A06A3DF993DEA3823423F405294A52014565100E0A7211342DF02958046899EEBE6E491299A09312778193FEBD7FFABA8000; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h2C05EF54A3C0F7F5F017E03F5800377CCF6E493C84E8F56441831087370A084801DEC1A54696B9912E8B0705C8587D4F7D36C8638947A620554CC77819B55B7A12D552A8A0496EFE3AAC6F34739A94E798101823148D811212E9A349CC219049527CCD419525AD29AB7D372C0B56AA0A065F8BDC905346478059EC82801920687FF29C990C9E66273CC78041192D03081CC62A8A0D8CB4D9CF2F2558131A78B8A807C3A1110211AFCA2A142F0BA928156D142250438143D339E4E2079F298493C08C4847914664518E27EF7EB9C870A226AFC35BEDB651840466400D4B3C0F877740114D6B08228BCC693FB12CECCCD2461586069445ACFC910B1241434622B6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h5FFE6AD3343986C4103935236B6E6E11B940EF46A8FC06E6872A6929D50DCDB75621E625522D34519BF2C353F8AA030B9109C2F9686AD3AF57AF3016D9160354C0BED5FBD379F904A41BAFB6BE4EE9F208058229DD0C354F034A6C4D8B6C16A29F0120108829220B230F44550832C1022530CC13C4C30D8254ECA5200A1941266EE48A1CA6430860DE613153615CAF4C8D191004CE9C6105D8C6795B6484467D21D9DC46029B8376E97F2C7BF8C3A218EE79DDBCF886B2BBDE702F71B38AEC6914E5DCCAFE50CC13922A5B149C598A621F80C24D215291228844E7F33F9763C6639303AE5376F664C7125632C1A280CECD5740C77849D937472B202579964F60; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N0 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))) # +// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout )) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datab(gnd), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1 .lut_mask = 16'hF0AA; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y12_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h77A47C739FF6A22B8B5CDC49E748E9C739BDE6756DB4D22437E74183E12400CBF7D3C6CC8C7841AB49CC538E8A72F2E73C64D3DF3662B19C07D7D299CBEDEF3E7DA5F4A8458A9451315B681ADA9AB0D63218DFB77D3353C32837E954604B9D98144A4566F47B71715BE6CDB8BA64D536762E9224D70F9A5C374B4D1CAB8DF527027170C5DBCC2B6AD72B8E4CCC94DAA139D8BA64E3384337426E7F274CC88A373AB1F9007B8A7F2936D16274F9BF8B6BABD48FCE74047C1E738C5B303E815BA720C76D6362915156A7671331CE657011862E594E46A6D99392E2D640D766869389A4D43867379AB880C1ACE279E451CB3A9063A0B320F65E536B8EEF9CBB9C76; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h9A2921ED6AA0CC8387B267B9E7A182720833CEE061E6450C8E4A72E3C043F21A0AD007E832124E92429C091D167806C10041AF32DDE13A669990457D098CC2FE3AC884B1E69101135CD080022451F20884CCB9CD203C141402A5AD293C3BABA95ADFAF6726384795A7656B753D2369B9EB5595BAA722012DF8DCFBF15BF46D6EB755D1CBF0DCF6FD40BEEC16EAB4A6D16839C98CBE9DBB437C69FB709F8E79993B9DDFE4F823D6E124B75BCE9B29F799F926619184B6C1178389F07349210436293A130C900FBA4EA70D2BA25B343C5B026D8E8766A4E4267CDAEC99E830D2307D94E6ED80D6722F3989B91E31C63B64C363DCE71A861C14382E270FC02868C7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h386BA04E797A3F8551DAD9D24A8D259A03ECFF5AB81B1C31DFDAE10100544F8CF1A8CCFC0C7A15BD9E7C2557CB00BF2584E16AAD13D7EDB525A85ABF90C0136DD195D748900C29DF7F381280A9738CDC3BF5BBF937D3A4D99CE2BCCD97CEF2C7F00030AFDB7F22E68CBAA4D9BE7633D3B53E90E4B124422A2A4454BACA5A8DC9352CD1DAFC910CC504334DF9E6F1F4F30161A36293CC5CCF1CA13994ED29D34A5699692496359B8E67A7E74D9A0FC504C8465638CF74A0AF9185921A7D2629893091900604017933442359491FBAB63F346F0C5EC8E3A531984B09E605A30A0627271C28420E47B8DEC74738FC3EDF9FBD40EC09FC7B4D3A1475BE433705FB5F; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h973FED2E9BEDBA474B70B121A8D60F3B4EE3F1A238FB3B730EDEEE74EC632DB4D7779D7B79D1C75DF87378E98719C1AF38B1B801C71D180CE86370AE9C2BF38CF84DBBB9878C55457324E92D3DAE91D729AC76BBAD4C6EECA74DAB5EE9A175EE34ABEB9DFAA48538A57E3E5C158947081CA41402E8E65478737F73BB629AAE2EE51D405CAF70F622DD4599602D7910DCAC8214B2A42025110593202C8B164C8DF6369572C3BB8AA1984A8D12F776E224ECEEB21F97FCD6C0CF17A044EC2BBF0571A553CCDD8ABA79BD27B7AF735ED2D34F1EF3A81A160C9ECB1B1FAE6EDEEFF99E28CC30C7C2553DED3378D655AD194B2E6C1BCBED700F6713D960F33E4C361A; +// synopsys translate_on + +// Location: M9K_X33_Y15_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h8102080042447C443C0C3C402004FC1838787840407A00707C02487E444878428008004042460424402040024A3242124220044022404208520A4A24424A125A0A1028440000524A0A4A4A204A5240460800100010540042002064547E0600001FA9BE02B828694B8A82CB8C8158226808198E9EC6B021F07A2098D5E0ECB639D2B1908129B6A2D646516192D87593189D8B2B26CD6E16234C1CC90AD9831EBD89EAD271ECC39A80507716BB49626B743DFFCF99576C3FAC889860E46618ACB79EC30EEDE42EB1E31F3976CA23243179FAA96DCD66D51535351770D410DC8531866136E6184518410368288C446EC63A4FEE425019C244097049C2B2DC8D93C4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'hA111466C9493A2A7CA2204102414CC798BF0EEC2995A4814580BD07585585ED92E5172E82E845070000A846100500E84EA1803B8B07B99E1DC75BE6419674597B38F54EB9091AE3320201EE395AD63902282A031CE3E87CC902954AA515D5D6B6A855EC94CFEC4E0172C59A7D054F8F9F4356C312C204E40B05E2059407C8DC84683814663FB910969D1D631A952B381B7F635A33FD38D5CF15DF47D057F7FF555B555C2278100000A24804D7D98EB98602733818A12094F281287422CB40002464C92242004E0AE8518E001D124A7628010115D23C30462FC00A014A12133582A191E00538FC8A5004036A959ACB7A463D23E419EA06B744005385455A71250; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h6C60009CA281AEACDC1762945981B869F93D683EAF4AC7EE52412E85B60B91CD03AD0025F0D509F63202D877ECD8BF8005451F7BD346CF9E17B36F1850A7D80A8CF14A288EAE3BFE00FB2DB45080D4A50C58263A3B398DD51AB9CB554ECAA7B2E73D9D6D2C265859DB844C2C1952AD10241100174FE0444E6707D80A098D8585AAAC4802B74190FB007C0C0206186AFC1B3A2A46864F26118ED1D03ACB1062B7315502751655F60070E6B2C50609369611365AD1E3352327320331A51818030C7D8C4C59396600DC0C420495A0D987501490002BAD38012E20620D556A230B1796450B74E95A860FF3E434C65F1308F16F92395816B914F0CE870C1323347A4E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h7FC8531A7A319F3EBFC1383FFCDB0E09BD288288B078B4AD220B6FA934CF6187D972662C0D31E34E63B31CFC6EB4B35A69B67D85489E62EA99899A94F6800FDBA5D31B86A0288D29CE2EAAFF86A6A9F7000082293E6BB54F06E98ECCB199973EDA00FADB1D3A630BA18050635DE7DCB13B9B86E0CE6E08DC46331A352F716E3C441A0CC068A0823F8668A00621B779DE35FEC004050469F34866AEE766743D8C00FDF3B9F8DE7B76E97F8D32F0F39E4CAC68D9BBB68EA3915F6225F932CAAFDAD6E60DC661155EC9E80F8CEE659F19CC554B2C67C33EDCDA63BAD91B7D1842A7177AF49DF118FE47ACE3344964EBCADCFBB543F7729CCB340866D1157B6CCDDB; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N28 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ))) # +// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout )) + + .dataa(gnd), + .datab(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2 .lut_mask = 16'hFC30; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y17_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'hA504087E764CA02840304044540424244404044024804008A40A54484448544A800400207E4A0818204040024A1262124210084014407E08520A4A42424A1256522828280000524A124A4A7E4A527E4A106010607C38003C025408FE2400000087857B4051593F8FEF8A4F84E99E6FCC30DBEF9DDB582A41325A97B1EEE4166FF390FF8420BD829D1679F5F18B57EAB9C5CFBE75ECF7F3730C105ADF74BA7D7F9159D64BD7F217C1803F5B1169B463FF6C6EC899D6482FBA8E6B53DCF12F3BFFBE72266D55B4E9E5887FAF8840007C50220105C908100BAF6FBA7BF97E6E020792ADFDFBD96CFD77B36CF30CC5DE43A85FB6F0020203478F160F42F9A061FE44; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h812017671773A9EE08641F818054455F0BABE232D2AA00081423C0BCCE1E642C4B7AE34419240F3C0170E001D6CE75F0475D5A8A9012B9BD97153AB038EF6187776B42A5FE80BB5AAA2A550A58904A1C6DC992952AB4532C6CB2F975BC101356F70811E17D8C73F1D9BEF7F7E82EFAE6C2D2DB2126004D81CA67DACC344F6458C165510222E12BABC9B940EB70182EDBEEF007365AA980A2002829A05282A2AAAA8AAA32A2C38012BFEB492278CD27651FD91BDE452EEF054801275AA0D49D9A896B7EB5FD69B679669CBA00AA9A431956A3CE676A9D7B50D84F3FFFFFC4AAF735995E3ADF9E07EB861E3035B1EF3EF935DAFFFA1F94FDCA5B803F14101BE318; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'hCE21FFE0D222852612C7A87E8DFE961BD8CF052D4757559DF3ED2417472384AF04FF86DDFE9FCBD3DC2A4967F492CDD5A8FFBD9857306D8B07F3AD96A6138C0360BE688D11B16D7936F4B55E0E301BAD6A96802B5719271D55D5E93FED5335EF86E8AEC1EE37F6F5FFD77F204F5EBFDA614C41C1F85C32FFB05F2881BF7EB1D73DDBF48E39F1AE9FC0A7CAC2B4515882877D84D415C7A00D91E87F57E95B60EFEB9963425C951C00298F26A884C3AEF0DBF539D04E867EB6FB957E817C230DFEE3BE607B3FAC5DD39FB436C5BB7926D7FFF03EF787FF563C3FEF787919A8383DEF3142B9927BEAF99BCFB066319F5BDF2EFFB11686607A73BE9CB85CF6EC52D0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h420539B476E305B8200E47DFAAE8D5D1D0724DCC3FD72C4F8DE54622A1DD1BA78CA3CE9F24BEFA9E2BB9D89B423C327C8E050114401A62FDCD2054E166C0005F7941B61372AC884EE60A372057B59CFF30A6020B875C06E7C5FBDF9A91F8F0588ED67F67AA66B0674CD240410F613700B8DFE7F8837F88FF4520002E4BFD7FA2768008002000002624793100811F43BC315A6004052671392B47FEB7F5DC90E62175C7B8FC48FCC916D46F9315DFDECBE43E5F03D7D27F97E09E4700AA694552A1FF3BE5E159FFDDEB2FBECAEB87BBCC5FCF6E23D77E4DD4C9DEBC93C10F636326FAFE3BE30DFAF7B9E7A5FFE44BF314DAA1C1529CDBFFE9D94EB11A9F68D4DF; +// synopsys translate_on + +// Location: M9K_X33_Y18_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h7BBD7F79FFE0AB8FC33758D1C1145DDD6311CF69FFFDF62EDD236FC6A0358FA2B4B15EB89456517DFF58F68BDADB95B5F764CAE7E7C7E7D70CADB8FFD8F9A72BFBB9EB400590D7F939FF5A70A29817DC2CC29B679B2D7146BD21D47EF06F7D5EAF72F66DC666B0726D66FD941AD9BC6D758D5EC24DFEBA64871D6B86D37DF1DFBFF05FBD6AD8CA62C6CBE43BDBFD99E9EB6DD724D235FBEA9FE7D6767D811C40681A00AF8D864D8BB6D2A0916C8A93250A76B8A977F82E8FDFBE68F8E0F8DF237CA976FE488D1069D687A6F1D68A70F37CAAA367A74CBB75D3A6FFB4B1E8D4B7F7F22D2FE1509BDF80E6DD7B717D7E9C6531C3A86BE9F1D7A6AFD5BFB7A37A60; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h8AB3B7FDEE7B9CC735FCCE93E3AC1AAAA691AD6350E57F1F5773302B6F36F63D130E0574D6BB44B2C0D7A907702A748D0BA50F8FA5437ACD3B343C35039F44D19CD4E55E6CB00410842B02A7FD105706DF9E2A1FA025005632A0CC080400D280CCCA0665222D038CC873351A21B23939A98CC08803282189C8440D40CD40462421A40982C046D22C10146484345CAF7BC828BFE79DFBE3C631CBF660C487EBB759BD7F8DE9E0F27A65DE5245BEB8F7829C36F0D136168F97C2BD77D649A39EB4DDB3A42AC80797FDEF4DE3EEF7ED8C7307E4CE6A6317F7BF25D077BBF03AEA3363B065F7D671322D6BFB2B8759433929CEC27E3FD7741292A4A5AF02703CC4E3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'hFD5CB07B6C729B510A78BEC5F7C7A1E7809F1976D0DD3615C1D27D2DF596BFE7A8BCDC2E6655185CC45008B39EFD1FA6E9F5E816114F93E1E7A2A27C72C7349F3497229CB9044B6E7A7861A04A712AAF29EFBD393727F1F3FC2AA1E6CF571457F0A09C47F23F20FE2AABF5FD3ABE6167E5FD36E1D9735BBD5375C1F79BD0424ECF133BF47B9D3DA46DD6DBF3A8ADCDD3DF1176D2FE23447DFC65E1DD7BF3BE5E1C9DCD8EBB9D36AF570CF25CDD16F645D1DE9F9EE575E3A2B91D5659FC131CE3DCD4560015805B13AC0290001EF8261B7E4EB867C828D9777FFF47B6903008DDD7D77EF5E2C6D7220BE64B3C6E9EF22AFDFCC8005C2FFFFA3AB9AD1ADFC0AFE7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h06ABC52D5DBEF57EEB3311A9D85D253B44E250E1566BED57C6DBEB2ABFD1ADF6FF4DEBFBDEB376DF68D5EEDB5EB4D5AB5B79745D76CD8ADC59CB30C8AA33E1551D2FCA8DCB43C5356BAE638588C302868CE1161CACADFEF7696F8C3AA82EC16F47A8EA413A2DCF09B996582318DBF3C4711871B3BC0404EC45252A485234A663C1FFFB3487617BE24FD79501DE05F1A341B89EC82FD5702497FD866639C0DE08B383E6E7C3B310E1F7FF595C5DF6F0E9A9FFFBE16D3FFBE82C1E0051F1E060D500812F408CC6501331852531B04480021D9220D4903A41404312032840153FE9CC8070206B8245AC240020752EBC2BEF3E74AB288F360C239C4AFAE93F68775A; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N0 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout )) # +// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datab(gnd), + .datac(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3 .lut_mask = 16'hAFA0; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y18_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h35861A00A6112A1481AF1A50A6004A05291627227FF08229B87389E08119A28A7888672DC999B7046A61E60810A7434450E3D33E330F321A18E8A120D1EDC8623DA2C64840C2CCE811522B42008095E5A456C98F4B25EAEA410610545024640CF10410AC463BF9349074917E9A74A12830EFA280EBD3131E484A255D0191C6852730A263DBCCAAA88712242B3BE49AA5338990229B391158C726BC7EB4ECC32308980020680249882691A680488292310B4313CE87FFCD5329A64B708CAC8533316412C4900F646A36630261DA093053D98F19D2C5B653165D4A71AA5682B29B89B6054CC727D292805705A93268676A31111371390B240EC3CC85D331813EB1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h1AA1C248D293110CB951445117D9B6AA500F65068B8CC508BD00184F8705B010A0CC46CC9302649242CE08191634113154562B149100204551178DE805D98EC8A2E5A64B241400267194CD524499BC01D31058CD18684A817A5800B65143281C1310B00A49902C0104004C654E0582040001103654011012021912281216B000C653A0510A1B00C36AC88058CAC126E14E198DFB07E81C3F41510BB08F8F851C3B9AF0147BC1F730B4E91D9D11C3A8F1B82DF19988ACC44072FDB17B4D81882E9DD952B29003D7767BA581A68BC41C2B16AD6EB57F1D048CD4E464190D25ADF2C194E3598360AFB031A1690F4625BB628363B4C90A400E3A04DAA70DA0CC4776; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'hC82B30671933680037A65978674DDEC2D30EEEDA78F5F2A1DEE660FFEA11B175DCB42E9277212A58842051A078007109A0D820166B881042600284403143048295D23A0E191EBC2134B833D53D37E42B05018289A10300A188E315CE98640F548A370D60A0AA3E7288A0B0869FA5E703D1AE17C0EC276B2AFB747B550A8B41021620D1A60A901095D12A0973B95E20838001330138951361967847D42901910A3488480610A91A851E84FF08783F81AEA52D2FDC2200BD2FE81C0357FBEC1D875686C6CA41B2224C88D8456C1DBF20D820A6649774CB11B69933246E9739C998470542C2E3C783A4C24767084C52DC209D60E95DBC096D9A0171A12D5AB99BAB; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h17A24D2C636ED2478B5AE1C99D40761B1E7AA6A89DDD1BBD8DBD223E70531BCDE90C8E38C8E0478AD8B388F94891C9673A50BC32478E083074657E8E0EA53BEE861F8BC1993560946D92D1C0C7F046A245B5849CB751FF15B97FCD50BC7B8524C13E7C640F3645082248D1CC14296E30DEA3057B35C641762CD00D40DABC27472251A60725008AAA056591C4000BB48C0BC29B8034A03400027B84769B520D9196968460CA3388A03ECB45F2C4B70F1829221000FFFC7FEC346F079F13079798EC2A08157331C6CC0E30884244916A0DE26D4D22454091290404A492016887E2111F830F9851184101370588A06D3BF9AE621A5F4E632A6799C83EFAAE06769D; +// synopsys translate_on + +// Location: M9K_X22_Y17_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'hA50276000854A0103840403E540424244404783E18807A08A47C54484448544A807E7E10005270182040407E4A1252124208084008404208420A4A42424A125A024428106448524A624A4A24425242522060108010543C00044A105424005E0031ED1E0529E507AE2F6FF1CD51D4C772A648E65F6532C28022061303F06C36CDBD319B55CB8E626C20E46C93C1463A0B1CE594F0ED3B62330C104DECE46CA6CD966B1386612C7B43980349408F36FB64C14342DAE26CE4D8D5E791388729D743B09A27AB81D71A14AB3D24E385B602248476D00249239514B58D3098504ACD119B99E9021B650A69494C22600667473128DA5010D2195982823226DED0ADFCB8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h5861917919344A4685CC0990862A11324792E761B6D41C0FCC0838C1C27211A2453FDC2219C225E421B320085A8FBFD0C42135B16448DFC226E09B3438A740C352979565817114DE46462844A57F7958873FC4B255C8AE549BDD1A87415D5018F88D5002628FFD13203066C850F10649F21319109208387641120B362124803F0678522BA2812C1454A502ED1A59CBD76A034756F5765DF7555F57575F7F57FFFF7FFF7D5712524D4A30723514B2B3064A84B4742D48415281863DDFAA9D9B7E7BB16DDB96B7845371C30B55DB96C8F6EB4B453242FF6A4DF84A76B5AEDC88A68DC6A06905054C8C36E4199E74638E6532965218A965909BA456000451343351; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'hE2975A2686A7AE0288F140141B698E2A82A835F478453A1D722CFCED12859FD735188757AC5A42DEB501FE010586249AC1EA60D08F74CFA5086EC78FC9190C056059E332C311521E6522901852D484B423A98816C9B26A08C92368E9FF05524502288A804612A2A0A102A418CBDFBA554499541660F8124640110101263142892A086B442661015380041594608092D9CB919250100A37DDA3919A1427F660963C251301FB2CA45562245308885131119115C652B2493252340201101942D26000CC60799124A8520C08050122171281808058018C38A645D07931896B39ED259A22242CB58413089465B246231330D806105010035100B08761A08506094160; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N20 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ))) # +// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout )) + + .dataa(gnd), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4 .lut_mask = 16'hF0CC; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y15_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h990442000864A0284030400454782424440404007E404808A4005448387E547C8004420800620824402040024A1242124204044008404208420A4A42424A1242020028008000524A024A4A284252446240001000101042000054265C7E0600007FAF5CA001C181BE0C02418447B1D88BAA85409896BC7C0E5FAC2529CB69A4038E2564731F88FE730045956C357C5ECF7EF8591DF2A8ACFFBFEEF268CD9B51238594AF691A9B8640983B7F76AAB97209EA6257389992FFE684926E0B19FA338B8489D73811171D5C9FF3DCFFFFFF8002000780101F3F4035A0CDED99F79A4775854F179F7D7DBBCF81B2F6421FF684CA6AF85894D29B9D3ACCBA3F27D9DC9911; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h5B438D714D4E3DD115E8BD1286EAB5FA1D71BD8F4508BD4BDC8838F9D27B552259BCEFFBB68A6FF529B3B0D92970010BBB6C7D872421210E190E1CCC47A485EAD2F8735647315839EF6F683C64773FC73464D5FE354936D50823A5DAEBEBDBCC6CAFF2622B8D518F63C6030424188FD357718970D25A30CD0731E532DB23002D02C12B12378356DE2C52041CA7A320C51E0D7CA9F5D575775D57FD75DDFDF75FFFDFFFD75F145247F03A0AE7F1E1EB2D5A99D2444108C6A5979B7CC26ABCC241EA4C912568003BB493CE04FF086C188980052BF6ABAAA2FD5D658000011277EB924C10EFAF3CB9B62486512344C61ADE6F15AB67F335A52513FF05AFAEEE8400; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h0C840083AD485153ACD3C035591630199B8C096CE4DC557D6D55FCCD738573D6E0948817C496E9DE8EA1F88F627B7460106691CC452DB9799E59A5D003733C4EA1BCE33AD2D8BE40A4E5BB7D7BBEC2CEADBBC8B6F87A4A56FBE0B891DE57E4C64EF9AD87727C49CFE7C5DE942B72AC7F6D97DE18920777FDDEE9EB11122A4E18F5569FDE08906765428FB9E6F89FBF0DEAA6064637BCA63FD02E273E5557F0548662C97BC2E8D3FFDB26D23E87BFD97E635A6560CFD93F8EED26E30C70DE8633D6B97C86DF7D9BEDFB99E36B6658F16C6DEFBDD5DF728D6209C852C37FE67CFF32EE4CCCECC64F7E6225FC99EC64C3B6DD7DED0FD7CCEA3BF09A006ECDD1009E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'hA9C9CE3AECF7BE27C000000A8ABA95251B309A60B9DDC19EC3E391458CBB53CA00A85E3C5AAE2C49DDC2F6C7B013DACB319A769818A1081A7389F711D76A09BCBED23D9A99FF9B77183697955D76BF0E0008822742DA45B883C9193DAF09424501859565800698515E10A8189EE9B323E35CE7388D73C6E7A50D0DE6739C73AC538D134115D860ADA57B5B868E54393B1E31E762062577697D57E8464340420E9434CCA34CC9A1CB1FAACC56168071EAC113F5265D5F6A45A098D604A820508C4EA47F9A7E46083716911B0D585CE937B530218E8D2AD3777EE7D3B4BC56C29ADB46809D15D185F8809229B150C29C8081174CA6173B99703DA466629005C604; +// synopsys translate_on + +// Location: M9K_X22_Y13_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'hE10F8B8C100323720BEBBDEBB81DF13FF97B252E2CB4F27BA091FBD0002D1A611E1EDBBC716D44D2912B80041C44558060CFCF15955C0D780DD5E71393920844F25E16C87C5D0308EEC52C011514BBC13AFA1028924D0C7CE738105BD47A10AA5B5C1D9D4193E4339F492B0E1A64E13AE35BE6B67AC8057BDACC155F14E906A017A1841358335450D4B26CD2A21B3D8F2211080B81EC040D7FA0B51CD48008112508062020A02490900092D2040259108806A328F4006D2AA514B42FB006ECCCCB9A360865678449975A8AE72B5C0F7BA800C1B5DC55D7D6FE2EF4EED85D00AB111821321BA426A4FE4956B43595832C271E83E060341AE5F2023FC808177383; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h1A2955372D510AC266A5445146E27000020C320FAE1557E37154040A13202DC6F40B840FB9A59B6DBB296562CB6220EFBE99D2776A202044D9101006FD221D305519198C859000004012AFF4FB060307C92BB732203BFDFEFFFFFFDFFF87FCFFFBFFEFF03FFE0FFFBFAFE0FF80787FFF7FFF83F7F87003FFBFFFFBFFFBFF0FFC0FF81FFF7FFBFFDFFFBFFFE1FF0086F3141AAB6005810A0621595A893F9D85983B9254954341968BAC8C141C90938C05B2C9CD267E11650407375FEDD6A2FEB346AAF6CFDC0791AA97B741995A3B3981E06D1A44D3711955197BB9910FCA20744915C84D6C24BAF53929814CA8A4697E8F4201145AE7415DC122A5F010436107; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h02E84F969E3C800AC610D276182020227809001A50DDDBA3487BB6AE802BA06509312DA0E620656EAF24D57C08FFB14D289613DC32083803B84DC6415FD5EDC000300A8D128FA20030ACCBAFA237B7024504D36A4BA26081137F059E78991154FE2AC2A884A8CC7FBBB21C851CC92B12E15593C0C020FFEE066558590E882D5B67459F1A8C3240FE4E6A8D028C0C088FCF471D400A19B38211004DD122212288B111114514CB11840E04828849C621392041163C00808C67223422F00110201DD18FCFFFF3FFE7F9FFFFFFF82C0B422D214711E08904524A069491774E663F48F665955B4E2C63DAC0078652D10120900298F7EE380092442AFD400BEC43C003; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'hB5D49EA9D7036A45AA9E870B8E8016720C7C3102AE925262492C84584942D209042216E0216C85B8912250B7157D5955AD406CB685BBF071B47D5193363C1CECAFE59E91BF11498940A0944996D47EE8D7E3A4EAE611AE19A965D01BA86B55E9C52A6A379A382C6C265FB0DA01396D0800C0046405C06F466DD18C4DD7655CD4E7622EC485808C841D64B737041FF68813B149A41531A0A692FB14AE2E5B49D49CDCADCF90E7BD88125BCE706BF6D04AABFC1C001163DC6EFF7FD3230303030000000000000000000008400000000000000000000000000030600000100007E00220000000000000080040004023AD496997B8C0077B886EEF161CF2298A091B; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N20 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # +// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ))) + + .dataa(gnd), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5 .lut_mask = 16'hCCF0; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y16_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h4200420000441C443C0C3C00480018FC387C7C000000007E180038300000204880084204004204423E1E3E02247E3C7E3C7E7E7E7E30007E3C7E7E7E3C7E7C3C0400000000000C34023C2E302464003C00000000000000000020460024000000FF991E65536D2D8D9C9B4DB081C83A5A881B0DFDE2D72DF0FA08FCD6F664173D989098D02025E0F6043B4B9080F4923880C3A3B02D269E730C3DCC423386DCB98B4AD0C5C8D6119602E5121008325B7457090E914F4876EC8A18C664210A4C2392C7658400073421047C75FBE7BE73FDFFF05FEE07BF8AEF7F1378B359E8C61F8F692C2218C98A4A8748531986E7C770D984E0000C02060C000C0DF50F68A580; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h0100046606572583002086010800054C0F2DE8371AC0000A9003E024840C7C0806F6612D770080980A40D293FEC069F16CB2164CA033C539F69B37741AEF1CE3662FF5DF9CB107BB23A39EF7B95E7372200448DBDC18F9C0DE0EF379BF49480657781E91788044213E091339886F337D0612CA646CD48FC58EE77EDD7ECEC466C744FD00E1A7F9E9FBFE4777FD50ABD11F0E57FF4808802282200888A20AA88000000008800AC11D556264251ECFA68C056FBCCB040C614A6850222300D2F6FF59F878FCF5689FCFEF34BFD52FA2422A56A3C113409F7813007F8D6B5F80FE9D7FB1E62675F7C2CBE01032DCA16BADC570C1CBF7ECBC4E7E6C54A5D4550BE1A8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'hE33CB578DEBFAFAEDFD530DE8FA1992072F31B116644B18C72F9F44116C79ADF2F3982C7BE09AD4A32196807648A2495ADF98FD2B16CC096A5E25F5BC811C953CEC3000F432029B3FE3F211712944CA54D1940F193204C199C9F49666CC11B38C23B9D130CA49818913D3A2C1FBF71C5B0C774336F903C677D976189D98CA127AAAD6B6AF36195DA637C6EFA3E36E8FE97FA02EC26EB46198AD8DAD8C11260AF499D7BD86619EE5574CD27C80D39F71E653FDCF1B366737233CBB98D1E7B330F7DCCFC5939C4EC79CF0E1CD43BA7AFC716900A21BDB9DD0FCC7ECE1063238407C7E1B221EA10E38F64EF31CEBF3368E1C712BB1B33781134CFE54C2123349A6E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6; +// synopsys translate_on + +// Location: M9K_X33_Y19_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h3C766E63DB6481CB39BC8C68831C724633186CC1BAE9D608A5DEF0FF219C28C1EFF4FDE394D0E19B6FD89186C23CF071E6F1CC8F7FC4F1E48756B0DCD8ED6D0C3DA139003D7A86B2F878DD99DAFB70DE1A19F3FB7DB3B8EF2633007664CB19992E43664448EFF06072648DBA32EDB76E26439BCCEF2DFBF664594B04FBAE72A84A3E508B49DC6BEAAB4F3F0CCCF6D8F568F2DA00EB384A7F53249323198000100408002024010408824080002008011482ED5615E40012EE630C3B2CDB2C13A736DB5B7BD2850018CF936621C6863095A73F7BE7442CB13110B9C0BBB96EEF16CE618EEDCFB393738178C476C367909F71307F6803F677575763DB2D8C3118E4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h881331ED7AC4EFD38DFACDBB236790005719AEA2FAECCF0D126A30A27222D61BBA428334561F4EDB60C6BF8DB6E267BC56CB69BBCE636CCCB3B2B4B103CC46D5CEEC06DAECB0001569589D5F267AFE086C8FED5DE41DFEFF027DFDFF7FFBFBFDFFDFFF6FFFBDFFDFFF57FF7F7FB7FBBDFBDFFDBFF78FFDBFFEDDFFFDFFFEFF6FF7F7FDDFFEDFF6FF7FFEEFFEFEFC4E51EC0888848E1F2044B47B66608D8A3B3919B9466E6D60D27565964244B218B48AD83430D996068EC908D9E112096996041D77401A0C0CCF5DEEE561F7F7E68CBE72E48E570B047C772CBACC33753080E32EB0B348C0B62337739B1BC73192392592C84E37B7AC141CFE65EE76D83C9083; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h1C5CF062CA6F13854A59BDEEEA07E3C6559EBB3618111895CBBACCBCD512B5F07D361CCE72B925658DBE1F7C4707E195C5C665B8118C3C31B196C261DA85A5E11889D25CB816ACC6627802052C61A4099B7B0EC923971DB3B9F9204BDBCCFA457EE296E8986E64C6DC99E59436641567648CB84DEB7D7937F974F038D838274F3D3CF1BE8C84DDB000565880A776E5C0E13166E49F47119A4CA1311CF97B965E7CBBCB2CB384BD0D92ED105D0617856E80441124B31DE58B8C001607FEE668899693E3EFF8FBF1FCEEFBCF7CF9BA6C37640DDF7FFE6187B19ACF089D4C038F6607B78D38001FE67E56CCE399DE36D7DDBD699D5CFC5B6D7A1421CE06FE40DB6E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h0776C62C316FF94B0BC3A0288DE6A62B14D6C1A2DADF9BDF85B2CCB02CE1DB2D96632C3232C3974CDC1172E1779D8C6738251819975DB8146067301E0C0277B6B657485DCD62AC0662C8C005DDE7494C9CA13AAE3234BB0EE1B708A23A2F48AC4C3838641E940620F9CDDCCA14BCC07104C112BCC9032C48E925594CB886A604C9F7627EB100872A52FB5141D65111E6C8DA0ADB6CEC6004461D0E366B20DCCDB607E624499300E4DF6D95CB62F62FB75403E400EFBC3BD34080FC9CDCFCFCFFFFFFFFFFFFFFFFFFFFF7BFFFFFFFFFFFFFFFFFFFFFFFFFFFCF9FFFFFEFFFF81FFDDFFFFFFFFFFFFFF7FFBFFFBFDC0A6DBE6F8BE5BB7FE7A39B3DA3F3BE13B679; +// synopsys translate_on + +// Location: LCCOMB_X32_Y19_N0 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout )) # +// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datab(gnd), + .datac(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6 .lut_mask = 16'hAFA0; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y14_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; +// synopsys translate_on + +// Location: M9K_X22_Y12_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N12 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ))) # +// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout )) + + .dataa(gnd), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7 .lut_mask = 16'hF0CC; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7 .sum_lutc_input = "datac"; // synopsys translate_on assign LED[0] = \LED[0]~output_o ; diff --git a/simulation/modelsim/spectrum_6_1200mv_0c_slow.vo b/simulation/modelsim/spectrum_6_1200mv_0c_slow.vo index dbe4927..681ffbf 100644 --- a/simulation/modelsim/spectrum_6_1200mv_0c_slow.vo +++ b/simulation/modelsim/spectrum_6_1200mv_0c_slow.vo @@ -16,7 +16,7 @@ // PROGRAM "Quartus II 32-bit" // VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" -// DATE "03/30/2022 12:38:42" +// DATE "03/30/2022 13:12:28" // // Device: Altera EP4CE22F17C6 Package FBGA256 @@ -71,77 +71,166 @@ wire \LED[6]~output_o ; wire \LED[7]~output_o ; wire \CLOCK_50~input_o ; wire \CLOCK_50~inputclkctrl_outclk ; -wire \Add0~0_combout ; -wire \Add0~1 ; -wire \Add0~2_combout ; -wire \Add0~3 ; -wire \Add0~4_combout ; -wire \Add0~5 ; -wire \Add0~6_combout ; -wire \Add0~7 ; -wire \Add0~8_combout ; -wire \Add0~9 ; -wire \Add0~10_combout ; -wire \Add0~11 ; -wire \Add0~12_combout ; -wire \Add0~13 ; -wire \Add0~14_combout ; -wire \Add0~15 ; -wire \Add0~16_combout ; -wire \Add0~17 ; -wire \Add0~18_combout ; -wire \Add0~19 ; -wire \Add0~20_combout ; -wire \Add0~21 ; -wire \Add0~22_combout ; -wire \Add0~23 ; -wire \Add0~24_combout ; -wire \Add0~25 ; -wire \Add0~26_combout ; -wire \Add0~27 ; -wire \Add0~28_combout ; -wire \Add0~29 ; -wire \Add0~30_combout ; -wire \Add0~31 ; -wire \Add0~32_combout ; -wire \Add0~33 ; -wire \Add0~34_combout ; -wire \Add0~35 ; -wire \Add0~36_combout ; -wire \Add0~37 ; -wire \Add0~38_combout ; -wire \Add0~39 ; -wire \Add0~40_combout ; +wire \counter[0]~63_combout ; +wire \counter[1]~21_combout ; +wire \counter[1]~22 ; +wire \counter[2]~23_combout ; +wire \counter[2]~24 ; +wire \counter[3]~25_combout ; +wire \counter[3]~26 ; +wire \counter[4]~27_combout ; +wire \counter[4]~28 ; +wire \counter[5]~29_combout ; +wire \counter[5]~30 ; +wire \counter[6]~31_combout ; +wire \counter[6]~32 ; +wire \counter[7]~33_combout ; +wire \counter[7]~34 ; +wire \counter[8]~35_combout ; +wire \counter[8]~36 ; +wire \counter[9]~37_combout ; +wire \counter[9]~38 ; +wire \counter[10]~39_combout ; +wire \counter[10]~40 ; +wire \counter[11]~41_combout ; +wire \counter[11]~feeder_combout ; +wire \counter[11]~42 ; +wire \counter[12]~43_combout ; +wire \counter[12]~44 ; +wire \counter[13]~45_combout ; +wire \counter[13]~46 ; +wire \counter[14]~47_combout ; +wire \counter[14]~48 ; +wire \counter[15]~49_combout ; +wire \counter[15]~50 ; +wire \counter[16]~51_combout ; +wire \counter[16]~52 ; +wire \counter[17]~53_combout ; +wire \counter[17]~54 ; +wire \counter[18]~55_combout ; +wire \counter[18]~56 ; +wire \counter[19]~57_combout ; wire \Equal0~5_combout ; -wire \Equal0~1_combout ; wire \Equal0~0_combout ; +wire \Equal0~1_combout ; wire \Equal0~2_combout ; wire \Equal0~3_combout ; wire \Equal0~4_combout ; -wire \address[0]~0_combout ; -wire \Equal0~6_combout ; +wire \counter[19]~58 ; +wire \counter[20]~59_combout ; +wire \counter[20]~60 ; +wire \counter[21]~61_combout ; wire \Equal0~7_combout ; -wire \address[1]~1_combout ; -wire \address[1]~2_combout ; -wire \address[2]~3_combout ; -wire [20:0] counter; -wire [2:0] address; -wire [7:0] \rom|altsyncram_component|auto_generated|q_a ; +wire \address[0]~39_combout ; +wire \address[1]~13_combout ; +wire \Equal0~6_combout ; +wire \address[1]~14 ; +wire \address[2]~15_combout ; +wire \address[2]~16 ; +wire \address[3]~17_combout ; +wire \address[3]~18 ; +wire \address[4]~19_combout ; +wire \address[4]~20 ; +wire \address[5]~21_combout ; +wire \address[5]~22 ; +wire \address[6]~23_combout ; +wire \address[6]~24 ; +wire \address[7]~25_combout ; +wire \address[7]~26 ; +wire \address[8]~27_combout ; +wire \address[8]~28 ; +wire \address[9]~29_combout ; +wire \address[9]~30 ; +wire \address[10]~31_combout ; +wire \address[10]~32 ; +wire \address[11]~33_combout ; +wire \address[11]~34 ; +wire \address[12]~35_combout ; +wire \address[12]~36 ; +wire \address[13]~37_combout ; +wire \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; +wire \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ; +wire [21:0] counter; +wire [13:0] address; +wire [0:0] \rom|altsyncram_component|auto_generated|out_address_reg_a ; +wire [0:0] \rom|altsyncram_component|auto_generated|address_reg_a ; -wire [17:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; -assign \rom|altsyncram_component|auto_generated|q_a [0] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|q_a [1] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [1]; -assign \rom|altsyncram_component|auto_generated|q_a [2] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [2]; -assign \rom|altsyncram_component|auto_generated|q_a [3] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [3]; -assign \rom|altsyncram_component|auto_generated|q_a [4] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [4]; -assign \rom|altsyncram_component|auto_generated|q_a [5] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [5]; -assign \rom|altsyncram_component|auto_generated|q_a [6] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [6]; -assign \rom|altsyncram_component|auto_generated|q_a [7] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [7]; +assign \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; // Location: IOOBUF_X38_Y34_N16 cycloneive_io_obuf \LED[0]~output ( - .i(\rom|altsyncram_component|auto_generated|q_a [0]), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -154,7 +243,7 @@ defparam \LED[0]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y34_N2 cycloneive_io_obuf \LED[1]~output ( - .i(\rom|altsyncram_component|auto_generated|q_a [1]), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -167,7 +256,7 @@ defparam \LED[1]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y34_N9 cycloneive_io_obuf \LED[2]~output ( - .i(\rom|altsyncram_component|auto_generated|q_a [2]), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -180,7 +269,7 @@ defparam \LED[2]~output .open_drain_output = "false"; // Location: IOOBUF_X40_Y34_N2 cycloneive_io_obuf \LED[3]~output ( - .i(\rom|altsyncram_component|auto_generated|q_a [3]), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -193,7 +282,7 @@ defparam \LED[3]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y25_N9 cycloneive_io_obuf \LED[4]~output ( - .i(\rom|altsyncram_component|auto_generated|q_a [4]), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -206,7 +295,7 @@ defparam \LED[4]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y26_N16 cycloneive_io_obuf \LED[5]~output ( - .i(\rom|altsyncram_component|auto_generated|q_a [5]), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -219,7 +308,7 @@ defparam \LED[5]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y28_N9 cycloneive_io_obuf \LED[6]~output ( - .i(\rom|altsyncram_component|auto_generated|q_a [6]), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -232,7 +321,7 @@ defparam \LED[6]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y10_N23 cycloneive_io_obuf \LED[7]~output ( - .i(\rom|altsyncram_component|auto_generated|q_a [7]), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -266,47 +355,27 @@ defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: FF_X31_Y17_N21 -dffeas \counter[20] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~40_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[20]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[20] .is_wysiwyg = "true"; -defparam \counter[20] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N12 -cycloneive_lcell_comb \Add0~0 ( +// Location: LCCOMB_X28_Y18_N2 +cycloneive_lcell_comb \counter[0]~63 ( // Equation(s): -// \Add0~0_combout = counter[0] $ (VCC) -// \Add0~1 = CARRY(counter[0]) +// \counter[0]~63_combout = !counter[0] - .dataa(counter[0]), + .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(vcc), + .datac(counter[0]), + .datad(gnd), .cin(gnd), - .combout(\Add0~0_combout ), - .cout(\Add0~1 )); + .combout(\counter[0]~63_combout ), + .cout()); // synopsys translate_off -defparam \Add0~0 .lut_mask = 16'h55AA; -defparam \Add0~0 .sum_lutc_input = "datac"; +defparam \counter[0]~63 .lut_mask = 16'h0F0F; +defparam \counter[0]~63 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y18_N13 +// Location: FF_X28_Y18_N3 dffeas \counter[0] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~0_combout ), + .d(\counter[0]~63_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -322,28 +391,28 @@ defparam \counter[0] .is_wysiwyg = "true"; defparam \counter[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y18_N14 -cycloneive_lcell_comb \Add0~2 ( +// Location: LCCOMB_X28_Y18_N12 +cycloneive_lcell_comb \counter[1]~21 ( // Equation(s): -// \Add0~2_combout = (counter[1] & (!\Add0~1 )) # (!counter[1] & ((\Add0~1 ) # (GND))) -// \Add0~3 = CARRY((!\Add0~1 ) # (!counter[1])) +// \counter[1]~21_combout = (counter[1] & (counter[0] $ (VCC))) # (!counter[1] & (counter[0] & VCC)) +// \counter[1]~22 = CARRY((counter[1] & counter[0])) - .dataa(gnd), - .datab(counter[1]), + .dataa(counter[1]), + .datab(counter[0]), .datac(gnd), .datad(vcc), - .cin(\Add0~1 ), - .combout(\Add0~2_combout ), - .cout(\Add0~3 )); + .cin(gnd), + .combout(\counter[1]~21_combout ), + .cout(\counter[1]~22 )); // synopsys translate_off -defparam \Add0~2 .lut_mask = 16'h3C3F; -defparam \Add0~2 .sum_lutc_input = "cin"; +defparam \counter[1]~21 .lut_mask = 16'h6688; +defparam \counter[1]~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y18_N15 +// Location: FF_X28_Y18_N13 dffeas \counter[1] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~2_combout ), + .d(\counter[1]~21_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -359,28 +428,28 @@ defparam \counter[1] .is_wysiwyg = "true"; defparam \counter[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y18_N16 -cycloneive_lcell_comb \Add0~4 ( +// Location: LCCOMB_X28_Y18_N14 +cycloneive_lcell_comb \counter[2]~23 ( // Equation(s): -// \Add0~4_combout = (counter[2] & (\Add0~3 $ (GND))) # (!counter[2] & (!\Add0~3 & VCC)) -// \Add0~5 = CARRY((counter[2] & !\Add0~3 )) +// \counter[2]~23_combout = (counter[2] & (!\counter[1]~22 )) # (!counter[2] & ((\counter[1]~22 ) # (GND))) +// \counter[2]~24 = CARRY((!\counter[1]~22 ) # (!counter[2])) .dataa(gnd), .datab(counter[2]), .datac(gnd), .datad(vcc), - .cin(\Add0~3 ), - .combout(\Add0~4_combout ), - .cout(\Add0~5 )); + .cin(\counter[1]~22 ), + .combout(\counter[2]~23_combout ), + .cout(\counter[2]~24 )); // synopsys translate_off -defparam \Add0~4 .lut_mask = 16'hC30C; -defparam \Add0~4 .sum_lutc_input = "cin"; +defparam \counter[2]~23 .lut_mask = 16'h3C3F; +defparam \counter[2]~23 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y18_N17 +// Location: FF_X28_Y18_N15 dffeas \counter[2] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~4_combout ), + .d(\counter[2]~23_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -396,28 +465,28 @@ defparam \counter[2] .is_wysiwyg = "true"; defparam \counter[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y18_N18 -cycloneive_lcell_comb \Add0~6 ( +// Location: LCCOMB_X28_Y18_N16 +cycloneive_lcell_comb \counter[3]~25 ( // Equation(s): -// \Add0~6_combout = (counter[3] & (!\Add0~5 )) # (!counter[3] & ((\Add0~5 ) # (GND))) -// \Add0~7 = CARRY((!\Add0~5 ) # (!counter[3])) +// \counter[3]~25_combout = (counter[3] & (\counter[2]~24 $ (GND))) # (!counter[3] & (!\counter[2]~24 & VCC)) +// \counter[3]~26 = CARRY((counter[3] & !\counter[2]~24 )) .dataa(gnd), .datab(counter[3]), .datac(gnd), .datad(vcc), - .cin(\Add0~5 ), - .combout(\Add0~6_combout ), - .cout(\Add0~7 )); + .cin(\counter[2]~24 ), + .combout(\counter[3]~25_combout ), + .cout(\counter[3]~26 )); // synopsys translate_off -defparam \Add0~6 .lut_mask = 16'h3C3F; -defparam \Add0~6 .sum_lutc_input = "cin"; +defparam \counter[3]~25 .lut_mask = 16'hC30C; +defparam \counter[3]~25 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y18_N19 +// Location: FF_X28_Y18_N17 dffeas \counter[3] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~6_combout ), + .d(\counter[3]~25_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -433,28 +502,28 @@ defparam \counter[3] .is_wysiwyg = "true"; defparam \counter[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y18_N20 -cycloneive_lcell_comb \Add0~8 ( +// Location: LCCOMB_X28_Y18_N18 +cycloneive_lcell_comb \counter[4]~27 ( // Equation(s): -// \Add0~8_combout = (counter[4] & (\Add0~7 $ (GND))) # (!counter[4] & (!\Add0~7 & VCC)) -// \Add0~9 = CARRY((counter[4] & !\Add0~7 )) +// \counter[4]~27_combout = (counter[4] & (!\counter[3]~26 )) # (!counter[4] & ((\counter[3]~26 ) # (GND))) +// \counter[4]~28 = CARRY((!\counter[3]~26 ) # (!counter[4])) - .dataa(counter[4]), - .datab(gnd), + .dataa(gnd), + .datab(counter[4]), .datac(gnd), .datad(vcc), - .cin(\Add0~7 ), - .combout(\Add0~8_combout ), - .cout(\Add0~9 )); + .cin(\counter[3]~26 ), + .combout(\counter[4]~27_combout ), + .cout(\counter[4]~28 )); // synopsys translate_off -defparam \Add0~8 .lut_mask = 16'hA50A; -defparam \Add0~8 .sum_lutc_input = "cin"; +defparam \counter[4]~27 .lut_mask = 16'h3C3F; +defparam \counter[4]~27 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y18_N21 +// Location: FF_X28_Y18_N19 dffeas \counter[4] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~8_combout ), + .d(\counter[4]~27_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -470,28 +539,28 @@ defparam \counter[4] .is_wysiwyg = "true"; defparam \counter[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y18_N22 -cycloneive_lcell_comb \Add0~10 ( +// Location: LCCOMB_X28_Y18_N20 +cycloneive_lcell_comb \counter[5]~29 ( // Equation(s): -// \Add0~10_combout = (counter[5] & (!\Add0~9 )) # (!counter[5] & ((\Add0~9 ) # (GND))) -// \Add0~11 = CARRY((!\Add0~9 ) # (!counter[5])) +// \counter[5]~29_combout = (counter[5] & (\counter[4]~28 $ (GND))) # (!counter[5] & (!\counter[4]~28 & VCC)) +// \counter[5]~30 = CARRY((counter[5] & !\counter[4]~28 )) .dataa(gnd), .datab(counter[5]), .datac(gnd), .datad(vcc), - .cin(\Add0~9 ), - .combout(\Add0~10_combout ), - .cout(\Add0~11 )); + .cin(\counter[4]~28 ), + .combout(\counter[5]~29_combout ), + .cout(\counter[5]~30 )); // synopsys translate_off -defparam \Add0~10 .lut_mask = 16'h3C3F; -defparam \Add0~10 .sum_lutc_input = "cin"; +defparam \counter[5]~29 .lut_mask = 16'hC30C; +defparam \counter[5]~29 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y18_N23 +// Location: FF_X28_Y18_N21 dffeas \counter[5] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~10_combout ), + .d(\counter[5]~29_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -507,28 +576,28 @@ defparam \counter[5] .is_wysiwyg = "true"; defparam \counter[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y18_N24 -cycloneive_lcell_comb \Add0~12 ( +// Location: LCCOMB_X28_Y18_N22 +cycloneive_lcell_comb \counter[6]~31 ( // Equation(s): -// \Add0~12_combout = (counter[6] & (\Add0~11 $ (GND))) # (!counter[6] & (!\Add0~11 & VCC)) -// \Add0~13 = CARRY((counter[6] & !\Add0~11 )) +// \counter[6]~31_combout = (counter[6] & (!\counter[5]~30 )) # (!counter[6] & ((\counter[5]~30 ) # (GND))) +// \counter[6]~32 = CARRY((!\counter[5]~30 ) # (!counter[6])) .dataa(counter[6]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\Add0~11 ), - .combout(\Add0~12_combout ), - .cout(\Add0~13 )); + .cin(\counter[5]~30 ), + .combout(\counter[6]~31_combout ), + .cout(\counter[6]~32 )); // synopsys translate_off -defparam \Add0~12 .lut_mask = 16'hA50A; -defparam \Add0~12 .sum_lutc_input = "cin"; +defparam \counter[6]~31 .lut_mask = 16'h5A5F; +defparam \counter[6]~31 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y18_N25 +// Location: FF_X28_Y18_N23 dffeas \counter[6] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~12_combout ), + .d(\counter[6]~31_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -544,28 +613,28 @@ defparam \counter[6] .is_wysiwyg = "true"; defparam \counter[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y18_N26 -cycloneive_lcell_comb \Add0~14 ( +// Location: LCCOMB_X28_Y18_N24 +cycloneive_lcell_comb \counter[7]~33 ( // Equation(s): -// \Add0~14_combout = (counter[7] & (!\Add0~13 )) # (!counter[7] & ((\Add0~13 ) # (GND))) -// \Add0~15 = CARRY((!\Add0~13 ) # (!counter[7])) +// \counter[7]~33_combout = (counter[7] & (\counter[6]~32 $ (GND))) # (!counter[7] & (!\counter[6]~32 & VCC)) +// \counter[7]~34 = CARRY((counter[7] & !\counter[6]~32 )) .dataa(gnd), .datab(counter[7]), .datac(gnd), .datad(vcc), - .cin(\Add0~13 ), - .combout(\Add0~14_combout ), - .cout(\Add0~15 )); + .cin(\counter[6]~32 ), + .combout(\counter[7]~33_combout ), + .cout(\counter[7]~34 )); // synopsys translate_off -defparam \Add0~14 .lut_mask = 16'h3C3F; -defparam \Add0~14 .sum_lutc_input = "cin"; +defparam \counter[7]~33 .lut_mask = 16'hC30C; +defparam \counter[7]~33 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y18_N27 +// Location: FF_X28_Y18_N25 dffeas \counter[7] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~14_combout ), + .d(\counter[7]~33_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -581,28 +650,28 @@ defparam \counter[7] .is_wysiwyg = "true"; defparam \counter[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y18_N28 -cycloneive_lcell_comb \Add0~16 ( +// Location: LCCOMB_X28_Y18_N26 +cycloneive_lcell_comb \counter[8]~35 ( // Equation(s): -// \Add0~16_combout = (counter[8] & (\Add0~15 $ (GND))) # (!counter[8] & (!\Add0~15 & VCC)) -// \Add0~17 = CARRY((counter[8] & !\Add0~15 )) +// \counter[8]~35_combout = (counter[8] & (!\counter[7]~34 )) # (!counter[8] & ((\counter[7]~34 ) # (GND))) +// \counter[8]~36 = CARRY((!\counter[7]~34 ) # (!counter[8])) - .dataa(gnd), - .datab(counter[8]), + .dataa(counter[8]), + .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\Add0~15 ), - .combout(\Add0~16_combout ), - .cout(\Add0~17 )); + .cin(\counter[7]~34 ), + .combout(\counter[8]~35_combout ), + .cout(\counter[8]~36 )); // synopsys translate_off -defparam \Add0~16 .lut_mask = 16'hC30C; -defparam \Add0~16 .sum_lutc_input = "cin"; +defparam \counter[8]~35 .lut_mask = 16'h5A5F; +defparam \counter[8]~35 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y18_N29 +// Location: FF_X28_Y18_N27 dffeas \counter[8] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~16_combout ), + .d(\counter[8]~35_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -618,28 +687,28 @@ defparam \counter[8] .is_wysiwyg = "true"; defparam \counter[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y18_N30 -cycloneive_lcell_comb \Add0~18 ( +// Location: LCCOMB_X28_Y18_N28 +cycloneive_lcell_comb \counter[9]~37 ( // Equation(s): -// \Add0~18_combout = (counter[9] & (!\Add0~17 )) # (!counter[9] & ((\Add0~17 ) # (GND))) -// \Add0~19 = CARRY((!\Add0~17 ) # (!counter[9])) +// \counter[9]~37_combout = (counter[9] & (\counter[8]~36 $ (GND))) # (!counter[9] & (!\counter[8]~36 & VCC)) +// \counter[9]~38 = CARRY((counter[9] & !\counter[8]~36 )) - .dataa(counter[9]), - .datab(gnd), + .dataa(gnd), + .datab(counter[9]), .datac(gnd), .datad(vcc), - .cin(\Add0~17 ), - .combout(\Add0~18_combout ), - .cout(\Add0~19 )); + .cin(\counter[8]~36 ), + .combout(\counter[9]~37_combout ), + .cout(\counter[9]~38 )); // synopsys translate_off -defparam \Add0~18 .lut_mask = 16'h5A5F; -defparam \Add0~18 .sum_lutc_input = "cin"; +defparam \counter[9]~37 .lut_mask = 16'hC30C; +defparam \counter[9]~37 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y18_N31 +// Location: FF_X28_Y18_N29 dffeas \counter[9] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~18_combout ), + .d(\counter[9]~37_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -655,28 +724,28 @@ defparam \counter[9] .is_wysiwyg = "true"; defparam \counter[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N0 -cycloneive_lcell_comb \Add0~20 ( +// Location: LCCOMB_X28_Y18_N30 +cycloneive_lcell_comb \counter[10]~39 ( // Equation(s): -// \Add0~20_combout = (counter[10] & (\Add0~19 $ (GND))) # (!counter[10] & (!\Add0~19 & VCC)) -// \Add0~21 = CARRY((counter[10] & !\Add0~19 )) +// \counter[10]~39_combout = (counter[10] & (!\counter[9]~38 )) # (!counter[10] & ((\counter[9]~38 ) # (GND))) +// \counter[10]~40 = CARRY((!\counter[9]~38 ) # (!counter[10])) - .dataa(gnd), - .datab(counter[10]), + .dataa(counter[10]), + .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\Add0~19 ), - .combout(\Add0~20_combout ), - .cout(\Add0~21 )); + .cin(\counter[9]~38 ), + .combout(\counter[10]~39_combout ), + .cout(\counter[10]~40 )); // synopsys translate_off -defparam \Add0~20 .lut_mask = 16'hC30C; -defparam \Add0~20 .sum_lutc_input = "cin"; +defparam \counter[10]~39 .lut_mask = 16'h5A5F; +defparam \counter[10]~39 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y17_N1 +// Location: FF_X28_Y18_N31 dffeas \counter[10] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~20_combout ), + .d(\counter[10]~39_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -692,28 +761,45 @@ defparam \counter[10] .is_wysiwyg = "true"; defparam \counter[10] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N2 -cycloneive_lcell_comb \Add0~22 ( +// Location: LCCOMB_X28_Y17_N0 +cycloneive_lcell_comb \counter[11]~41 ( // Equation(s): -// \Add0~22_combout = (counter[11] & (!\Add0~21 )) # (!counter[11] & ((\Add0~21 ) # (GND))) -// \Add0~23 = CARRY((!\Add0~21 ) # (!counter[11])) +// \counter[11]~41_combout = (counter[11] & (\counter[10]~40 $ (GND))) # (!counter[11] & (!\counter[10]~40 & VCC)) +// \counter[11]~42 = CARRY((counter[11] & !\counter[10]~40 )) - .dataa(gnd), - .datab(counter[11]), + .dataa(counter[11]), + .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\Add0~21 ), - .combout(\Add0~22_combout ), - .cout(\Add0~23 )); + .cin(\counter[10]~40 ), + .combout(\counter[11]~41_combout ), + .cout(\counter[11]~42 )); // synopsys translate_off -defparam \Add0~22 .lut_mask = 16'h3C3F; -defparam \Add0~22 .sum_lutc_input = "cin"; +defparam \counter[11]~41 .lut_mask = 16'hA50A; +defparam \counter[11]~41 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y17_N3 +// Location: LCCOMB_X28_Y18_N4 +cycloneive_lcell_comb \counter[11]~feeder ( +// Equation(s): +// \counter[11]~feeder_combout = \counter[11]~41_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\counter[11]~41_combout ), + .cin(gnd), + .combout(\counter[11]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \counter[11]~feeder .lut_mask = 16'hFF00; +defparam \counter[11]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N5 dffeas \counter[11] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~22_combout ), + .d(\counter[11]~feeder_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -729,28 +815,28 @@ defparam \counter[11] .is_wysiwyg = "true"; defparam \counter[11] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N4 -cycloneive_lcell_comb \Add0~24 ( +// Location: LCCOMB_X28_Y17_N2 +cycloneive_lcell_comb \counter[12]~43 ( // Equation(s): -// \Add0~24_combout = (counter[12] & (\Add0~23 $ (GND))) # (!counter[12] & (!\Add0~23 & VCC)) -// \Add0~25 = CARRY((counter[12] & !\Add0~23 )) +// \counter[12]~43_combout = (counter[12] & (!\counter[11]~42 )) # (!counter[12] & ((\counter[11]~42 ) # (GND))) +// \counter[12]~44 = CARRY((!\counter[11]~42 ) # (!counter[12])) .dataa(gnd), .datab(counter[12]), .datac(gnd), .datad(vcc), - .cin(\Add0~23 ), - .combout(\Add0~24_combout ), - .cout(\Add0~25 )); + .cin(\counter[11]~42 ), + .combout(\counter[12]~43_combout ), + .cout(\counter[12]~44 )); // synopsys translate_off -defparam \Add0~24 .lut_mask = 16'hC30C; -defparam \Add0~24 .sum_lutc_input = "cin"; +defparam \counter[12]~43 .lut_mask = 16'h3C3F; +defparam \counter[12]~43 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y17_N5 +// Location: FF_X28_Y17_N3 dffeas \counter[12] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~24_combout ), + .d(\counter[12]~43_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -766,28 +852,28 @@ defparam \counter[12] .is_wysiwyg = "true"; defparam \counter[12] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N6 -cycloneive_lcell_comb \Add0~26 ( +// Location: LCCOMB_X28_Y17_N4 +cycloneive_lcell_comb \counter[13]~45 ( // Equation(s): -// \Add0~26_combout = (counter[13] & (!\Add0~25 )) # (!counter[13] & ((\Add0~25 ) # (GND))) -// \Add0~27 = CARRY((!\Add0~25 ) # (!counter[13])) +// \counter[13]~45_combout = (counter[13] & (\counter[12]~44 $ (GND))) # (!counter[13] & (!\counter[12]~44 & VCC)) +// \counter[13]~46 = CARRY((counter[13] & !\counter[12]~44 )) .dataa(gnd), .datab(counter[13]), .datac(gnd), .datad(vcc), - .cin(\Add0~25 ), - .combout(\Add0~26_combout ), - .cout(\Add0~27 )); + .cin(\counter[12]~44 ), + .combout(\counter[13]~45_combout ), + .cout(\counter[13]~46 )); // synopsys translate_off -defparam \Add0~26 .lut_mask = 16'h3C3F; -defparam \Add0~26 .sum_lutc_input = "cin"; +defparam \counter[13]~45 .lut_mask = 16'hC30C; +defparam \counter[13]~45 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y17_N7 +// Location: FF_X28_Y17_N5 dffeas \counter[13] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~26_combout ), + .d(\counter[13]~45_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -803,28 +889,28 @@ defparam \counter[13] .is_wysiwyg = "true"; defparam \counter[13] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N8 -cycloneive_lcell_comb \Add0~28 ( +// Location: LCCOMB_X28_Y17_N6 +cycloneive_lcell_comb \counter[14]~47 ( // Equation(s): -// \Add0~28_combout = (counter[14] & (\Add0~27 $ (GND))) # (!counter[14] & (!\Add0~27 & VCC)) -// \Add0~29 = CARRY((counter[14] & !\Add0~27 )) +// \counter[14]~47_combout = (counter[14] & (!\counter[13]~46 )) # (!counter[14] & ((\counter[13]~46 ) # (GND))) +// \counter[14]~48 = CARRY((!\counter[13]~46 ) # (!counter[14])) .dataa(counter[14]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\Add0~27 ), - .combout(\Add0~28_combout ), - .cout(\Add0~29 )); + .cin(\counter[13]~46 ), + .combout(\counter[14]~47_combout ), + .cout(\counter[14]~48 )); // synopsys translate_off -defparam \Add0~28 .lut_mask = 16'hA50A; -defparam \Add0~28 .sum_lutc_input = "cin"; +defparam \counter[14]~47 .lut_mask = 16'h5A5F; +defparam \counter[14]~47 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y17_N9 +// Location: FF_X28_Y17_N7 dffeas \counter[14] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~28_combout ), + .d(\counter[14]~47_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -840,28 +926,28 @@ defparam \counter[14] .is_wysiwyg = "true"; defparam \counter[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N10 -cycloneive_lcell_comb \Add0~30 ( +// Location: LCCOMB_X28_Y17_N8 +cycloneive_lcell_comb \counter[15]~49 ( // Equation(s): -// \Add0~30_combout = (counter[15] & (!\Add0~29 )) # (!counter[15] & ((\Add0~29 ) # (GND))) -// \Add0~31 = CARRY((!\Add0~29 ) # (!counter[15])) +// \counter[15]~49_combout = (counter[15] & (\counter[14]~48 $ (GND))) # (!counter[15] & (!\counter[14]~48 & VCC)) +// \counter[15]~50 = CARRY((counter[15] & !\counter[14]~48 )) .dataa(gnd), .datab(counter[15]), .datac(gnd), .datad(vcc), - .cin(\Add0~29 ), - .combout(\Add0~30_combout ), - .cout(\Add0~31 )); + .cin(\counter[14]~48 ), + .combout(\counter[15]~49_combout ), + .cout(\counter[15]~50 )); // synopsys translate_off -defparam \Add0~30 .lut_mask = 16'h3C3F; -defparam \Add0~30 .sum_lutc_input = "cin"; +defparam \counter[15]~49 .lut_mask = 16'hC30C; +defparam \counter[15]~49 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y17_N11 +// Location: FF_X28_Y17_N9 dffeas \counter[15] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~30_combout ), + .d(\counter[15]~49_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -877,28 +963,28 @@ defparam \counter[15] .is_wysiwyg = "true"; defparam \counter[15] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N12 -cycloneive_lcell_comb \Add0~32 ( +// Location: LCCOMB_X28_Y17_N10 +cycloneive_lcell_comb \counter[16]~51 ( // Equation(s): -// \Add0~32_combout = (counter[16] & (\Add0~31 $ (GND))) # (!counter[16] & (!\Add0~31 & VCC)) -// \Add0~33 = CARRY((counter[16] & !\Add0~31 )) +// \counter[16]~51_combout = (counter[16] & (!\counter[15]~50 )) # (!counter[16] & ((\counter[15]~50 ) # (GND))) +// \counter[16]~52 = CARRY((!\counter[15]~50 ) # (!counter[16])) - .dataa(gnd), - .datab(counter[16]), + .dataa(counter[16]), + .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\Add0~31 ), - .combout(\Add0~32_combout ), - .cout(\Add0~33 )); + .cin(\counter[15]~50 ), + .combout(\counter[16]~51_combout ), + .cout(\counter[16]~52 )); // synopsys translate_off -defparam \Add0~32 .lut_mask = 16'hC30C; -defparam \Add0~32 .sum_lutc_input = "cin"; +defparam \counter[16]~51 .lut_mask = 16'h5A5F; +defparam \counter[16]~51 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y17_N13 +// Location: FF_X28_Y17_N11 dffeas \counter[16] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~32_combout ), + .d(\counter[16]~51_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -914,28 +1000,28 @@ defparam \counter[16] .is_wysiwyg = "true"; defparam \counter[16] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N14 -cycloneive_lcell_comb \Add0~34 ( +// Location: LCCOMB_X28_Y17_N12 +cycloneive_lcell_comb \counter[17]~53 ( // Equation(s): -// \Add0~34_combout = (counter[17] & (!\Add0~33 )) # (!counter[17] & ((\Add0~33 ) # (GND))) -// \Add0~35 = CARRY((!\Add0~33 ) # (!counter[17])) +// \counter[17]~53_combout = (counter[17] & (\counter[16]~52 $ (GND))) # (!counter[17] & (!\counter[16]~52 & VCC)) +// \counter[17]~54 = CARRY((counter[17] & !\counter[16]~52 )) .dataa(counter[17]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\Add0~33 ), - .combout(\Add0~34_combout ), - .cout(\Add0~35 )); + .cin(\counter[16]~52 ), + .combout(\counter[17]~53_combout ), + .cout(\counter[17]~54 )); // synopsys translate_off -defparam \Add0~34 .lut_mask = 16'h5A5F; -defparam \Add0~34 .sum_lutc_input = "cin"; +defparam \counter[17]~53 .lut_mask = 16'hA50A; +defparam \counter[17]~53 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y17_N15 +// Location: FF_X28_Y17_N13 dffeas \counter[17] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~34_combout ), + .d(\counter[17]~53_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -951,28 +1037,28 @@ defparam \counter[17] .is_wysiwyg = "true"; defparam \counter[17] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N16 -cycloneive_lcell_comb \Add0~36 ( +// Location: LCCOMB_X28_Y17_N14 +cycloneive_lcell_comb \counter[18]~55 ( // Equation(s): -// \Add0~36_combout = (counter[18] & (\Add0~35 $ (GND))) # (!counter[18] & (!\Add0~35 & VCC)) -// \Add0~37 = CARRY((counter[18] & !\Add0~35 )) +// \counter[18]~55_combout = (counter[18] & (!\counter[17]~54 )) # (!counter[18] & ((\counter[17]~54 ) # (GND))) +// \counter[18]~56 = CARRY((!\counter[17]~54 ) # (!counter[18])) - .dataa(counter[18]), - .datab(gnd), + .dataa(gnd), + .datab(counter[18]), .datac(gnd), .datad(vcc), - .cin(\Add0~35 ), - .combout(\Add0~36_combout ), - .cout(\Add0~37 )); + .cin(\counter[17]~54 ), + .combout(\counter[18]~55_combout ), + .cout(\counter[18]~56 )); // synopsys translate_off -defparam \Add0~36 .lut_mask = 16'hA50A; -defparam \Add0~36 .sum_lutc_input = "cin"; +defparam \counter[18]~55 .lut_mask = 16'h3C3F; +defparam \counter[18]~55 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y17_N17 +// Location: FF_X28_Y17_N15 dffeas \counter[18] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~36_combout ), + .d(\counter[18]~55_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -988,28 +1074,28 @@ defparam \counter[18] .is_wysiwyg = "true"; defparam \counter[18] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N18 -cycloneive_lcell_comb \Add0~38 ( +// Location: LCCOMB_X28_Y17_N16 +cycloneive_lcell_comb \counter[19]~57 ( // Equation(s): -// \Add0~38_combout = (counter[19] & (!\Add0~37 )) # (!counter[19] & ((\Add0~37 ) # (GND))) -// \Add0~39 = CARRY((!\Add0~37 ) # (!counter[19])) +// \counter[19]~57_combout = (counter[19] & (\counter[18]~56 $ (GND))) # (!counter[19] & (!\counter[18]~56 & VCC)) +// \counter[19]~58 = CARRY((counter[19] & !\counter[18]~56 )) - .dataa(counter[19]), - .datab(gnd), + .dataa(gnd), + .datab(counter[19]), .datac(gnd), .datad(vcc), - .cin(\Add0~37 ), - .combout(\Add0~38_combout ), - .cout(\Add0~39 )); + .cin(\counter[18]~56 ), + .combout(\counter[19]~57_combout ), + .cout(\counter[19]~58 )); // synopsys translate_off -defparam \Add0~38 .lut_mask = 16'h5A5F; -defparam \Add0~38 .sum_lutc_input = "cin"; +defparam \counter[19]~57 .lut_mask = 16'hC30C; +defparam \counter[19]~57 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y17_N19 +// Location: FF_X28_Y17_N17 dffeas \counter[19] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~38_combout ), + .d(\counter[19]~57_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1025,32 +1111,15 @@ defparam \counter[19] .is_wysiwyg = "true"; defparam \counter[19] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N20 -cycloneive_lcell_comb \Add0~40 ( -// Equation(s): -// \Add0~40_combout = \Add0~39 $ (!counter[20]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(counter[20]), - .cin(\Add0~39 ), - .combout(\Add0~40_combout ), - .cout()); -// synopsys translate_off -defparam \Add0~40 .lut_mask = 16'hF00F; -defparam \Add0~40 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N28 +// Location: LCCOMB_X28_Y17_N28 cycloneive_lcell_comb \Equal0~5 ( // Equation(s): -// \Equal0~5_combout = (!\Add0~32_combout & (!\Add0~36_combout & (!\Add0~34_combout & !\Add0~38_combout ))) +// \Equal0~5_combout = (!counter[17] & (!counter[19] & (!counter[18] & !counter[16]))) - .dataa(\Add0~32_combout ), - .datab(\Add0~36_combout ), - .datac(\Add0~34_combout ), - .datad(\Add0~38_combout ), + .dataa(counter[17]), + .datab(counter[19]), + .datac(counter[18]), + .datad(counter[16]), .cin(gnd), .combout(\Equal0~5_combout ), .cout()); @@ -1059,32 +1128,15 @@ defparam \Equal0~5 .lut_mask = 16'h0001; defparam \Equal0~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y18_N6 -cycloneive_lcell_comb \Equal0~1 ( -// Equation(s): -// \Equal0~1_combout = (!\Add0~10_combout & (!\Add0~8_combout & (!\Add0~14_combout & !\Add0~12_combout ))) - - .dataa(\Add0~10_combout ), - .datab(\Add0~8_combout ), - .datac(\Add0~14_combout ), - .datad(\Add0~12_combout ), - .cin(gnd), - .combout(\Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \Equal0~1 .lut_mask = 16'h0001; -defparam \Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N4 +// Location: LCCOMB_X28_Y18_N8 cycloneive_lcell_comb \Equal0~0 ( // Equation(s): -// \Equal0~0_combout = (!\Add0~4_combout & (!\Add0~0_combout & (!\Add0~6_combout & !\Add0~2_combout ))) +// \Equal0~0_combout = (!counter[1] & (!counter[0] & (!counter[2] & !counter[3]))) - .dataa(\Add0~4_combout ), - .datab(\Add0~0_combout ), - .datac(\Add0~6_combout ), - .datad(\Add0~2_combout ), + .dataa(counter[1]), + .datab(counter[0]), + .datac(counter[2]), + .datad(counter[3]), .cin(gnd), .combout(\Equal0~0_combout ), .cout()); @@ -1093,15 +1145,32 @@ defparam \Equal0~0 .lut_mask = 16'h0001; defparam \Equal0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N30 +// Location: LCCOMB_X28_Y18_N6 +cycloneive_lcell_comb \Equal0~1 ( +// Equation(s): +// \Equal0~1_combout = (!counter[6] & (!counter[7] & (!counter[5] & !counter[4]))) + + .dataa(counter[6]), + .datab(counter[7]), + .datac(counter[5]), + .datad(counter[4]), + .cin(gnd), + .combout(\Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~1 .lut_mask = 16'h0001; +defparam \Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N0 cycloneive_lcell_comb \Equal0~2 ( // Equation(s): -// \Equal0~2_combout = (!\Add0~22_combout & (!\Add0~16_combout & (!\Add0~20_combout & !\Add0~18_combout ))) +// \Equal0~2_combout = (!counter[8] & (!counter[11] & (!counter[10] & !counter[9]))) - .dataa(\Add0~22_combout ), - .datab(\Add0~16_combout ), - .datac(\Add0~20_combout ), - .datad(\Add0~18_combout ), + .dataa(counter[8]), + .datab(counter[11]), + .datac(counter[10]), + .datad(counter[9]), .cin(gnd), .combout(\Equal0~2_combout ), .cout()); @@ -1110,15 +1179,15 @@ defparam \Equal0~2 .lut_mask = 16'h0001; defparam \Equal0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N30 +// Location: LCCOMB_X28_Y17_N26 cycloneive_lcell_comb \Equal0~3 ( // Equation(s): -// \Equal0~3_combout = (!\Add0~26_combout & (!\Add0~24_combout & (!\Add0~28_combout & !\Add0~30_combout ))) +// \Equal0~3_combout = (!counter[14] & (!counter[13] & (!counter[15] & !counter[12]))) - .dataa(\Add0~26_combout ), - .datab(\Add0~24_combout ), - .datac(\Add0~28_combout ), - .datad(\Add0~30_combout ), + .dataa(counter[14]), + .datab(counter[13]), + .datac(counter[15]), + .datad(counter[12]), .cin(gnd), .combout(\Equal0~3_combout ), .cout()); @@ -1127,13 +1196,13 @@ defparam \Equal0~3 .lut_mask = 16'h0001; defparam \Equal0~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N28 +// Location: LCCOMB_X29_Y18_N28 cycloneive_lcell_comb \Equal0~4 ( // Equation(s): -// \Equal0~4_combout = (\Equal0~1_combout & (\Equal0~0_combout & (\Equal0~2_combout & \Equal0~3_combout ))) +// \Equal0~4_combout = (\Equal0~0_combout & (\Equal0~1_combout & (\Equal0~2_combout & \Equal0~3_combout ))) - .dataa(\Equal0~1_combout ), - .datab(\Equal0~0_combout ), + .dataa(\Equal0~0_combout ), + .datab(\Equal0~1_combout ), .datac(\Equal0~2_combout ), .datad(\Equal0~3_combout ), .cin(gnd), @@ -1144,27 +1213,117 @@ defparam \Equal0~4 .lut_mask = 16'h8000; defparam \Equal0~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N20 -cycloneive_lcell_comb \address[0]~0 ( +// Location: LCCOMB_X28_Y17_N18 +cycloneive_lcell_comb \counter[20]~59 ( // Equation(s): -// \address[0]~0_combout = address[0] $ (((!\Add0~40_combout & (\Equal0~5_combout & \Equal0~4_combout )))) +// \counter[20]~59_combout = (counter[20] & (!\counter[19]~58 )) # (!counter[20] & ((\counter[19]~58 ) # (GND))) +// \counter[20]~60 = CARRY((!\counter[19]~58 ) # (!counter[20])) - .dataa(\Add0~40_combout ), - .datab(\Equal0~5_combout ), - .datac(address[0]), - .datad(\Equal0~4_combout ), - .cin(gnd), - .combout(\address[0]~0_combout ), - .cout()); + .dataa(gnd), + .datab(counter[20]), + .datac(gnd), + .datad(vcc), + .cin(\counter[19]~58 ), + .combout(\counter[20]~59_combout ), + .cout(\counter[20]~60 )); // synopsys translate_off -defparam \address[0]~0 .lut_mask = 16'hB4F0; -defparam \address[0]~0 .sum_lutc_input = "datac"; +defparam \counter[20]~59 .lut_mask = 16'h3C3F; +defparam \counter[20]~59 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X32_Y17_N21 +// Location: FF_X28_Y17_N19 +dffeas \counter[20] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\counter[20]~59_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[20]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[20] .is_wysiwyg = "true"; +defparam \counter[20] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N20 +cycloneive_lcell_comb \counter[21]~61 ( +// Equation(s): +// \counter[21]~61_combout = \counter[20]~60 $ (!counter[21]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(counter[21]), + .cin(\counter[20]~60 ), + .combout(\counter[21]~61_combout ), + .cout()); +// synopsys translate_off +defparam \counter[21]~61 .lut_mask = 16'hF00F; +defparam \counter[21]~61 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X28_Y17_N21 +dffeas \counter[21] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\counter[21]~61_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[21]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[21] .is_wysiwyg = "true"; +defparam \counter[21] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N10 +cycloneive_lcell_comb \Equal0~7 ( +// Equation(s): +// \Equal0~7_combout = (!counter[21] & !counter[20]) + + .dataa(gnd), + .datab(gnd), + .datac(counter[21]), + .datad(counter[20]), + .cin(gnd), + .combout(\Equal0~7_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~7 .lut_mask = 16'h000F; +defparam \Equal0~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N30 +cycloneive_lcell_comb \address[0]~39 ( +// Equation(s): +// \address[0]~39_combout = address[0] $ (((\Equal0~5_combout & (\Equal0~4_combout & \Equal0~7_combout )))) + + .dataa(\Equal0~5_combout ), + .datab(\Equal0~4_combout ), + .datac(address[0]), + .datad(\Equal0~7_combout ), + .cin(gnd), + .combout(\address[0]~39_combout ), + .cout()); +// synopsys translate_off +defparam \address[0]~39 .lut_mask = 16'h78F0; +defparam \address[0]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y18_N31 dffeas \address[0] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[0]~0_combout ), + .d(\address[0]~39_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1180,67 +1339,51 @@ defparam \address[0] .is_wysiwyg = "true"; defparam \address[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N26 +// Location: LCCOMB_X29_Y18_N0 +cycloneive_lcell_comb \address[1]~13 ( +// Equation(s): +// \address[1]~13_combout = (address[0] & (address[1] $ (VCC))) # (!address[0] & (address[1] & VCC)) +// \address[1]~14 = CARRY((address[0] & address[1])) + + .dataa(address[0]), + .datab(address[1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\address[1]~13_combout ), + .cout(\address[1]~14 )); +// synopsys translate_off +defparam \address[1]~13 .lut_mask = 16'h6688; +defparam \address[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N26 cycloneive_lcell_comb \Equal0~6 ( // Equation(s): -// \Equal0~6_combout = (!\Add0~34_combout & !\Add0~32_combout ) +// \Equal0~6_combout = (!counter[20] & (!counter[21] & (\Equal0~5_combout & \Equal0~4_combout ))) - .dataa(gnd), - .datab(gnd), - .datac(\Add0~34_combout ), - .datad(\Add0~32_combout ), + .dataa(counter[20]), + .datab(counter[21]), + .datac(\Equal0~5_combout ), + .datad(\Equal0~4_combout ), .cin(gnd), .combout(\Equal0~6_combout ), .cout()); // synopsys translate_off -defparam \Equal0~6 .lut_mask = 16'h000F; +defparam \Equal0~6 .lut_mask = 16'h1000; defparam \Equal0~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N24 -cycloneive_lcell_comb \Equal0~7 ( -// Equation(s): -// \Equal0~7_combout = (!\Add0~40_combout & (!\Add0~36_combout & (\Equal0~6_combout & !\Add0~38_combout ))) - - .dataa(\Add0~40_combout ), - .datab(\Add0~36_combout ), - .datac(\Equal0~6_combout ), - .datad(\Add0~38_combout ), - .cin(gnd), - .combout(\Equal0~7_combout ), - .cout()); -// synopsys translate_off -defparam \Equal0~7 .lut_mask = 16'h0010; -defparam \Equal0~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N10 -cycloneive_lcell_comb \address[1]~1 ( -// Equation(s): -// \address[1]~1_combout = address[1] $ (((address[0] & (\Equal0~4_combout & \Equal0~7_combout )))) - - .dataa(address[0]), - .datab(\Equal0~4_combout ), - .datac(address[1]), - .datad(\Equal0~7_combout ), - .cin(gnd), - .combout(\address[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \address[1]~1 .lut_mask = 16'h78F0; -defparam \address[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N11 +// Location: FF_X29_Y18_N1 dffeas \address[1] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[1]~1_combout ), + .d(\address[1]~13_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(vcc), + .ena(\Equal0~6_combout ), .devclrn(devclrn), .devpor(devpor), .q(address[1]), @@ -1250,50 +1393,34 @@ defparam \address[1] .is_wysiwyg = "true"; defparam \address[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N2 -cycloneive_lcell_comb \address[1]~2 ( +// Location: LCCOMB_X29_Y18_N2 +cycloneive_lcell_comb \address[2]~15 ( // Equation(s): -// \address[1]~2_combout = (address[0] & (\Equal0~5_combout & (!\Add0~40_combout & \Equal0~4_combout ))) - - .dataa(address[0]), - .datab(\Equal0~5_combout ), - .datac(\Add0~40_combout ), - .datad(\Equal0~4_combout ), - .cin(gnd), - .combout(\address[1]~2_combout ), - .cout()); -// synopsys translate_off -defparam \address[1]~2 .lut_mask = 16'h0800; -defparam \address[1]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N16 -cycloneive_lcell_comb \address[2]~3 ( -// Equation(s): -// \address[2]~3_combout = address[2] $ (((address[1] & \address[1]~2_combout ))) +// \address[2]~15_combout = (address[2] & (!\address[1]~14 )) # (!address[2] & ((\address[1]~14 ) # (GND))) +// \address[2]~16 = CARRY((!\address[1]~14 ) # (!address[2])) .dataa(gnd), - .datab(address[1]), - .datac(address[2]), - .datad(\address[1]~2_combout ), - .cin(gnd), - .combout(\address[2]~3_combout ), - .cout()); + .datab(address[2]), + .datac(gnd), + .datad(vcc), + .cin(\address[1]~14 ), + .combout(\address[2]~15_combout ), + .cout(\address[2]~16 )); // synopsys translate_off -defparam \address[2]~3 .lut_mask = 16'h3CF0; -defparam \address[2]~3 .sum_lutc_input = "datac"; +defparam \address[2]~15 .lut_mask = 16'h3C3F; +defparam \address[2]~15 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X32_Y17_N17 +// Location: FF_X29_Y18_N3 dffeas \address[2] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[2]~3_combout ), + .d(\address[2]~15_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(vcc), + .ena(\Equal0~6_combout ), .devclrn(devclrn), .devpor(devpor), .q(address[2]), @@ -1303,7 +1430,541 @@ defparam \address[2] .is_wysiwyg = "true"; defparam \address[2] .power_up = "low"; // synopsys translate_on -// Location: M9K_X33_Y26_N0 +// Location: LCCOMB_X29_Y18_N4 +cycloneive_lcell_comb \address[3]~17 ( +// Equation(s): +// \address[3]~17_combout = (address[3] & (\address[2]~16 $ (GND))) # (!address[3] & (!\address[2]~16 & VCC)) +// \address[3]~18 = CARRY((address[3] & !\address[2]~16 )) + + .dataa(gnd), + .datab(address[3]), + .datac(gnd), + .datad(vcc), + .cin(\address[2]~16 ), + .combout(\address[3]~17_combout ), + .cout(\address[3]~18 )); +// synopsys translate_off +defparam \address[3]~17 .lut_mask = 16'hC30C; +defparam \address[3]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y18_N5 +dffeas \address[3] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[3]~17_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(address[3]), + .prn(vcc)); +// synopsys translate_off +defparam \address[3] .is_wysiwyg = "true"; +defparam \address[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N6 +cycloneive_lcell_comb \address[4]~19 ( +// Equation(s): +// \address[4]~19_combout = (address[4] & (!\address[3]~18 )) # (!address[4] & ((\address[3]~18 ) # (GND))) +// \address[4]~20 = CARRY((!\address[3]~18 ) # (!address[4])) + + .dataa(address[4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\address[3]~18 ), + .combout(\address[4]~19_combout ), + .cout(\address[4]~20 )); +// synopsys translate_off +defparam \address[4]~19 .lut_mask = 16'h5A5F; +defparam \address[4]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y18_N7 +dffeas \address[4] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[4]~19_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(address[4]), + .prn(vcc)); +// synopsys translate_off +defparam \address[4] .is_wysiwyg = "true"; +defparam \address[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N8 +cycloneive_lcell_comb \address[5]~21 ( +// Equation(s): +// \address[5]~21_combout = (address[5] & (\address[4]~20 $ (GND))) # (!address[5] & (!\address[4]~20 & VCC)) +// \address[5]~22 = CARRY((address[5] & !\address[4]~20 )) + + .dataa(gnd), + .datab(address[5]), + .datac(gnd), + .datad(vcc), + .cin(\address[4]~20 ), + .combout(\address[5]~21_combout ), + .cout(\address[5]~22 )); +// synopsys translate_off +defparam \address[5]~21 .lut_mask = 16'hC30C; +defparam \address[5]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y18_N9 +dffeas \address[5] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[5]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(address[5]), + .prn(vcc)); +// synopsys translate_off +defparam \address[5] .is_wysiwyg = "true"; +defparam \address[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N10 +cycloneive_lcell_comb \address[6]~23 ( +// Equation(s): +// \address[6]~23_combout = (address[6] & (!\address[5]~22 )) # (!address[6] & ((\address[5]~22 ) # (GND))) +// \address[6]~24 = CARRY((!\address[5]~22 ) # (!address[6])) + + .dataa(address[6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\address[5]~22 ), + .combout(\address[6]~23_combout ), + .cout(\address[6]~24 )); +// synopsys translate_off +defparam \address[6]~23 .lut_mask = 16'h5A5F; +defparam \address[6]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y18_N11 +dffeas \address[6] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[6]~23_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(address[6]), + .prn(vcc)); +// synopsys translate_off +defparam \address[6] .is_wysiwyg = "true"; +defparam \address[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N12 +cycloneive_lcell_comb \address[7]~25 ( +// Equation(s): +// \address[7]~25_combout = (address[7] & (\address[6]~24 $ (GND))) # (!address[7] & (!\address[6]~24 & VCC)) +// \address[7]~26 = CARRY((address[7] & !\address[6]~24 )) + + .dataa(address[7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\address[6]~24 ), + .combout(\address[7]~25_combout ), + .cout(\address[7]~26 )); +// synopsys translate_off +defparam \address[7]~25 .lut_mask = 16'hA50A; +defparam \address[7]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y18_N13 +dffeas \address[7] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[7]~25_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(address[7]), + .prn(vcc)); +// synopsys translate_off +defparam \address[7] .is_wysiwyg = "true"; +defparam \address[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N14 +cycloneive_lcell_comb \address[8]~27 ( +// Equation(s): +// \address[8]~27_combout = (address[8] & (!\address[7]~26 )) # (!address[8] & ((\address[7]~26 ) # (GND))) +// \address[8]~28 = CARRY((!\address[7]~26 ) # (!address[8])) + + .dataa(gnd), + .datab(address[8]), + .datac(gnd), + .datad(vcc), + .cin(\address[7]~26 ), + .combout(\address[8]~27_combout ), + .cout(\address[8]~28 )); +// synopsys translate_off +defparam \address[8]~27 .lut_mask = 16'h3C3F; +defparam \address[8]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y18_N15 +dffeas \address[8] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[8]~27_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(address[8]), + .prn(vcc)); +// synopsys translate_off +defparam \address[8] .is_wysiwyg = "true"; +defparam \address[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N16 +cycloneive_lcell_comb \address[9]~29 ( +// Equation(s): +// \address[9]~29_combout = (address[9] & (\address[8]~28 $ (GND))) # (!address[9] & (!\address[8]~28 & VCC)) +// \address[9]~30 = CARRY((address[9] & !\address[8]~28 )) + + .dataa(gnd), + .datab(address[9]), + .datac(gnd), + .datad(vcc), + .cin(\address[8]~28 ), + .combout(\address[9]~29_combout ), + .cout(\address[9]~30 )); +// synopsys translate_off +defparam \address[9]~29 .lut_mask = 16'hC30C; +defparam \address[9]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y18_N17 +dffeas \address[9] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[9]~29_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(address[9]), + .prn(vcc)); +// synopsys translate_off +defparam \address[9] .is_wysiwyg = "true"; +defparam \address[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N18 +cycloneive_lcell_comb \address[10]~31 ( +// Equation(s): +// \address[10]~31_combout = (address[10] & (!\address[9]~30 )) # (!address[10] & ((\address[9]~30 ) # (GND))) +// \address[10]~32 = CARRY((!\address[9]~30 ) # (!address[10])) + + .dataa(gnd), + .datab(address[10]), + .datac(gnd), + .datad(vcc), + .cin(\address[9]~30 ), + .combout(\address[10]~31_combout ), + .cout(\address[10]~32 )); +// synopsys translate_off +defparam \address[10]~31 .lut_mask = 16'h3C3F; +defparam \address[10]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y18_N19 +dffeas \address[10] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[10]~31_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(address[10]), + .prn(vcc)); +// synopsys translate_off +defparam \address[10] .is_wysiwyg = "true"; +defparam \address[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N20 +cycloneive_lcell_comb \address[11]~33 ( +// Equation(s): +// \address[11]~33_combout = (address[11] & (\address[10]~32 $ (GND))) # (!address[11] & (!\address[10]~32 & VCC)) +// \address[11]~34 = CARRY((address[11] & !\address[10]~32 )) + + .dataa(gnd), + .datab(address[11]), + .datac(gnd), + .datad(vcc), + .cin(\address[10]~32 ), + .combout(\address[11]~33_combout ), + .cout(\address[11]~34 )); +// synopsys translate_off +defparam \address[11]~33 .lut_mask = 16'hC30C; +defparam \address[11]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y18_N21 +dffeas \address[11] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[11]~33_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(address[11]), + .prn(vcc)); +// synopsys translate_off +defparam \address[11] .is_wysiwyg = "true"; +defparam \address[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N22 +cycloneive_lcell_comb \address[12]~35 ( +// Equation(s): +// \address[12]~35_combout = (address[12] & (!\address[11]~34 )) # (!address[12] & ((\address[11]~34 ) # (GND))) +// \address[12]~36 = CARRY((!\address[11]~34 ) # (!address[12])) + + .dataa(address[12]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\address[11]~34 ), + .combout(\address[12]~35_combout ), + .cout(\address[12]~36 )); +// synopsys translate_off +defparam \address[12]~35 .lut_mask = 16'h5A5F; +defparam \address[12]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y18_N23 +dffeas \address[12] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[12]~35_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(address[12]), + .prn(vcc)); +// synopsys translate_off +defparam \address[12] .is_wysiwyg = "true"; +defparam \address[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N24 +cycloneive_lcell_comb \address[13]~37 ( +// Equation(s): +// \address[13]~37_combout = \address[12]~36 $ (!address[13]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(address[13]), + .cin(\address[12]~36 ), + .combout(\address[13]~37_combout ), + .cout()); +// synopsys translate_off +defparam \address[13]~37 .lut_mask = 16'hF00F; +defparam \address[13]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y18_N25 +dffeas \address[13] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[13]~37_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(address[13]), + .prn(vcc)); +// synopsys translate_off +defparam \address[13] .is_wysiwyg = "true"; +defparam \address[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N2 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = address[13] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(address[13]), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hFF00; +defparam \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y18_N3 +dffeas \rom|altsyncram_component|auto_generated|address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\rom|altsyncram_component|auto_generated|address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; +defparam \rom|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N24 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout = \rom|altsyncram_component|auto_generated|address_reg_a [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\rom|altsyncram_component|auto_generated|address_reg_a [0]), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .lut_mask = 16'hFF00; +defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y18_N25 +dffeas \rom|altsyncram_component|auto_generated|out_address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; +defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: M9K_X33_Y13_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h3C00000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005DB824E17CAAE881C1908A79F24B7D1B4857A981A6AF39DFF5A2FEE9141EB33592D8E9B82471FDDA6791810A1C29D415CC1A8FA03444DF0083F83506BA93E8D1A1856A768D73A08418BFB25A40001DD4833DAF33BD311BB45F39667627407EF59ED569C483EB3BE1B10551B1428A6169579293ED063CAA9C6ADB0433CFC15C33AFF04C710408C20AC28B5909A229CD7D1DB4EB9A44CE0EEDBBBD391D3128AAA3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'hDDE6FC8EBE3F9F3C3DFC6E8F07BFD31D50660B1E0B2506A533CE0E340C7C745CAEC4837C2A5FECBB94C1C969FFDDFF79BFFAAFDCA8D748399ABF75558ADD02F56F6DFFF29CB70FFD25A59DFFFED7B3F7E8B4CE6FFF3EF9CEC6BAE57ABFFFCEE647B2AFF5B87AA26AFFDD317DEDCFBDFFE1A0CAD3B58877DD2F647F7DF748E7CF4693FD3C1238FFAFBD7FDF567FA8FEF024F33AFD3AABC6B105EA80272D64895FFF9FFF6E3881C81AFDCF2257FD4F8ED5257D0E9B800726B6564D2B05012F76DF636CDEB4BDFCAEEFC61DFFEFB7E26262DEF2CB9F71565824FEBF3F7BDDEABB593F1BF746FBFFC353E37263FF38A796EF39E3FD7DFEBA7FFEFFBD97ABAF09E909; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'hE629BDF93D7F5B5BAF92FBAB477E9B315DB5A310CFACC7408DF9A544B1E57AF6EFEF92C2FA4D8D4E4AC86C277338FA37BCDD9D47782DB75EFF80781BCD23D0AFCAE30B9FE6AA29FFF6F72DA73DFE4F7ACD39687B9E69C5359E9B991F0246EFFBC5595561AC64787878F5CE14C664CF9EB0CDAFFBABEF1E83358371B9ED96E5069555AFBBD3AEBFCABFBBED7A5C5FE9BD0E6A91C6E7610042695EEB08D8881B1D735AF87DAE59FABBD7DEAF8717F2B72F428F5E37E5D6E13157B99CBD2D73B9C73C563C8B02C8CC39C64DDCEA1BEEB5E7353F93786145598FE634EF1000179B345725EA43CE18F187A1DE4DAABEA97963E3A7A96B8B7CBC095BEB7CE46274D9AF; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h4ED4AE2B1650D21EAFE01E7099EFCA3094FD4D705CF6B84AE21583E13385F8650004406BD60A023AB063D4E5966EA41AA997F5A49BFCB0657A9732D28EB8217E65F627A15E1057ADEE7B9E27122A58FB2B98B1EA560390C7E87715861814E04DCB76FAB179E9619BC7E7E9C9FD801CF87DBA1EA496E829D4E62861E1AF436A7585287860729C77B6C68CAEA3033A6E84D67249B594C407B39C68B4C1C97FDEFC6BAD12FDBB525EF4F87F4A23EC13CBC0262D8899A3A290F04F41C1324045B9FCEEC890579E95D5A0A546CCCDD48577558ABE7CA36EF67A70F6A8758BDA052D5B95DE707778B17C2379847A23AE5D4BB01F36F3F44A8162566D9FB15DE7CC83F7; +// synopsys translate_on + +// Location: M9K_X33_Y14_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( .portawe(vcc), .portare(vcc), @@ -1313,46 +1974,978 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(vcc), + .ena0(!address[13]), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain(18'b000000000000000000), - .portaaddr({address[2],address[1],address[0]}), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), .portabyteenamasks(1'b1), - .portbdatain(18'b000000000000000000), - .portbaddr(3'b000), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "./rom/gw03.hex"; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom"; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 18; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 18; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 144'h002040042000900018000600024001080081; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h1EEA3633EFEA856D05BA968C1B3C30CA1788DD95D16B8F914DDDFC3EE5C69945DF7D7BF31C6072BFA7993996AB7DD2F3EE4009844CC9D6CF9E583AEC48A52F2904B57D8E0D755851232838F9B5348838530D7AF95411555D263B8CA86A5D29D7CE4B65409D6F04C5709A56C241C3BCEF07459A416EB4E8F3D73CC714F4333AFE605D53A5C955D5D1412F8361617A54446971FD187442A60FB04457857BECC3120A01FDC7FE2CBF038A61DEE5FCE2D10C8F35FBF80C05ABFF4B6935287B125E8D56F9FDFE7D64C1F4E1F5641845CD17E836B97780400C702523FA8E7C7BBD6F0666591A35ADD26B6B7E33CA56E9AB329EFA7E68F98AE7CE9507755C74C430286A; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h88537A811D4EF6CD9668CCD3E2E7A8041788DCA5F7E08AF52AF5276078304DEB75B74BB9AC3C1A492952F7EEAA0E7CF9FBEDD0FB47EEFDCC3734B816F355C913CD2E1AF14C30545297A91BED3AEAEFF8F696B5F4FC80BC6B1A2559492E9198E4A5875745B625C6CA7A7292332492D139728A689DA1AE78B6B44CE4F4A4EA5A22F331598B364EF27516CC49A4662C5E5C92ED140D96373678F833AE434698237599716B8CBAE2D3D061F2C3D6337AB435B5C2144AB6FA2F8BB51357801066B6589467DA6C480E6D19CEEA8451CEFA88FD70E7925B0302F877F87FA833FBD147E937309C08305A10187707E3D57DDE4931F1D9E97A8F378981ABBF8D7B6B7539C3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h763DD7AA7EED3F4AD4EA7491ADE6F14E6DBADD0F090A8DF34D7BAD35DD2275F0BCCF19EEF299751C919C9C13C6FB9ED711AC4DA7D947CC79E9B6323EF6CE62638CEBCB187AE5D44ECA689C9BD4E5AE544DEA7E90D186B9F335F3323877AAD54196CE81973CB555904419599375501366EC343561BCF83357F8823671393B278C1C387A7970C7F3E688673CF5975EE3E5FF105CFCCFAB725D698FB088B063063C7833830C7B2C7AFB8A8D203C312306DA0E72641FFB93D59B5EC84F44AD55F4B884735325ACC969B2EAE10A1478D866F667DDEF7BBF75E6958B6D02DC6D0F807660A229B98541E6FE734DE2280A9B57FCD5A9BEFEF7CDA5ABEB44FD73D2794D56; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hD0734B461A36980411EB2A6C1BE76029258777EF227A8F6E84F74C4436098F67BA611013110188547995B108BB2DAE76F423A0D98845F9248BDFA45E10CA403A5E2B1A3E16869E1D37BCE906B82F401CBD467617DB34D9E0C80B5E6E10063EC4BD52921D249E377D95CFAAA309EEDAA57DA85F55DBB7048A69A4C801013948B617F7F5724D40707E6FF30002982023020449B4680C45D1CE6D8EB30A061DB8FEDD6E630C15271E48CA801988654FB501D5393392EE765C1EC95C1E4D86F18A965372B72B484E2F2664B735B69A5AB532B086BA4C62AD6D56EECBDB6984B251454845BD5B243DAED2B2489B313A35C50252AFD3E0B76FEF342335C7F1321D92FF; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N24 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout )) # +// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ))) + + .dataa(gnd), + .datab(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0 .lut_mask = 16'hF3C0; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y19_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h35C65240B61076066A23CE4CFC5E76063A1C2AE07DF555007338BDC080EA0C23082C891C76A4845096304A0D8502080C1198911998821D09C29CA830C337499236E0548D65FF9125A765F0220F6EB9D1B318244CC6CA2CBC9CEC6979C14EB28DE2E0440C6CBD61341FC178649A852D4A2A0627C688D905B882524E191E7951EAEF30312A73337CBAD4838F42A3293859CD169240D8E652F6D72D8D19D56DD7675939FC47C933E1B0AEF12A484454C247B00A6BEC5402AA08B5106E3065602454C80CEC08A7F5F85CE65326632B4C4F3920019A35AE2AEB321131046EE45B81D4EFD5995634050D4CFEC166B032B6415553AF0358304080D9DD0A2E5948593830; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h376E511217E00B624A46BA2E4CC10B729C326F710F24CFE78C5E63F3024B17CC5E1380C938A0A16C9B696272DE7A2948BE8AFE81310146B8AAE5E549FA27EFBE27929938B8E10530250877A4998D0DF0004852125C20CA8D4279881E41208B14198817644F293AC1946061117122A39D8841818C1389D51BDAC549181902516571163594CEC5863F0F56625E221D6B8180848C6B2BE24AA0AEEE5D187201CAAE6AA394A8644314895565192AE415630A42894D6EF21343903B348EED8642F2310644C9567C0BF9911B870B989C59330089AA4C8065AB1B11132213EE0FD830817DE6C2ED45D76325CA2A8E198859334553AB02945CAB1F17C142288008073004; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h20721F982534A8179F13E2C6328CDE7D2A73087D3A9314419022103DFF7677769FE2D1F27443253D58403577C801AE23371F00290A17E1C4A40258BFD204230EE9969472A81B83113144528F831AA6C3221E137C1E9C670E26809A894013828D9E2DBCBF62498A769893D7218899245CD18AE49F0146517422EE475D520029ED39BCEF6BF4D23532957455F1C80115524179D59C4C4534DF7296991146CE24508366123AA809AB30B47977571C5D70397A93C723106D0A2C254714359DC7C9E13AE624C94932927924D20024CD638A05C8620023319662D80E05805625BC4A4006C78011F78D8B82E59F0CD4B32D6801669BE3EB0B96960DFF152005EC7C16CB; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h9C8CA06AA05B63C89A59A3E4E80807B27A70B0006624C4AC4A0595CCD8CA20824CA272352720BCD900A6D79BFD9D0595EC0D044ABC8CC28E9AE946E3D2000A4EFA4F91915C6AC9D8570C292F10848189906127BCBE06FFE92DAFB4AAFB240D88DDBB7B207EFA1709B05E1C4801BD45625A36BB62220506E171891964A31BED2215408676F600F490FAA59B488C7998CC8CCC28922AC62644EEBB432EEECB51B16CDEE7468681D6C31E4991CA3736E9ACB7531EC6D8BBCD453718101EA25D79278C6AC955A8A6140421573E413CF5A80AA1436D8B4C31A2AB26D2A61CE834248BAD5751BD429B4F61318427560CE39D49299002165212181064E24FF0093B997B; +// synopsys translate_on + +// Location: M9K_X22_Y16_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h420000004200000000000000000080000000000000000000000000000030004480000000424202423E1E3E02304C3C0C3C7E7E40403E427E3402421824347C1C0400280000003C3406303220344C403C0400100010100000005062742400000091991809FB3BD9084A1241F5015988B3C506031934089E0E1FA8043DDAF2CC07D94A6F2B1D133C211222B22C787D430E45D4C53282288077DFC0F704AAD55127A2BEAEA114958D2817AB1213183A4E1A15E3690A08A33B429284A202011A1243D49CACA1C0A441405A720D21A0921294045F746229E287B95E956AA3DE0CA3B7A019C8039C4DDA6BC99371248CC6008A54CB84503442C4F91309238ECB252072; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h81F3167814687CBD683E54D44555E6C95B5F2A72C0C193C6110C0221A448D0C9A0D8E36A84D5C61285128845215F8F8821C308E368283D8E2B42989C04A8B51354E09A38775020189010680840800297C31282442326D008D1F2351A89FFD7C16087F8B130F04418C0A1C082FC005843F5B42CADD9455ADBD328C13219110DE100D988737BBB44C414210118C673B0C1BDF76C499226F78FF41A0AF7AFD3308AAA0AAA22B1C70003F542A66FD1F1CF9D4578315F8C1C6FEC3EDB9B322CB204821A94A248414CE030020F207BF040A06A3DF993DEA3823423F405294A52014565100E0A7211342DF02958046899EEBE6E491299A09312778193FEBD7FFABA8000; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h2C05EF54A3C0F7F5F017E03F5800377CCF6E493C84E8F56441831087370A084801DEC1A54696B9912E8B0705C8587D4F7D36C8638947A620554CC77819B55B7A12D552A8A0496EFE3AAC6F34739A94E798101823148D811212E9A349CC219049527CCD419525AD29AB7D372C0B56AA0A065F8BDC905346478059EC82801920687FF29C990C9E66273CC78041192D03081CC62A8A0D8CB4D9CF2F2558131A78B8A807C3A1110211AFCA2A142F0BA928156D142250438143D339E4E2079F298493C08C4847914664518E27EF7EB9C870A226AFC35BEDB651840466400D4B3C0F877740114D6B08228BCC693FB12CECCCD2461586069445ACFC910B1241434622B6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h5FFE6AD3343986C4103935236B6E6E11B940EF46A8FC06E6872A6929D50DCDB75621E625522D34519BF2C353F8AA030B9109C2F9686AD3AF57AF3016D9160354C0BED5FBD379F904A41BAFB6BE4EE9F208058229DD0C354F034A6C4D8B6C16A29F0120108829220B230F44550832C1022530CC13C4C30D8254ECA5200A1941266EE48A1CA6430860DE613153615CAF4C8D191004CE9C6105D8C6795B6484467D21D9DC46029B8376E97F2C7BF8C3A218EE79DDBCF886B2BBDE702F71B38AEC6914E5DCCAFE50CC13922A5B149C598A621F80C24D215291228844E7F33F9763C6639303AE5376F664C7125632C1A280CECD5740C77849D937472B202579964F60; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N0 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))) # +// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout )) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datab(gnd), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1 .lut_mask = 16'hF0AA; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y12_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h77A47C739FF6A22B8B5CDC49E748E9C739BDE6756DB4D22437E74183E12400CBF7D3C6CC8C7841AB49CC538E8A72F2E73C64D3DF3662B19C07D7D299CBEDEF3E7DA5F4A8458A9451315B681ADA9AB0D63218DFB77D3353C32837E954604B9D98144A4566F47B71715BE6CDB8BA64D536762E9224D70F9A5C374B4D1CAB8DF527027170C5DBCC2B6AD72B8E4CCC94DAA139D8BA64E3384337426E7F274CC88A373AB1F9007B8A7F2936D16274F9BF8B6BABD48FCE74047C1E738C5B303E815BA720C76D6362915156A7671331CE657011862E594E46A6D99392E2D640D766869389A4D43867379AB880C1ACE279E451CB3A9063A0B320F65E536B8EEF9CBB9C76; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h9A2921ED6AA0CC8387B267B9E7A182720833CEE061E6450C8E4A72E3C043F21A0AD007E832124E92429C091D167806C10041AF32DDE13A669990457D098CC2FE3AC884B1E69101135CD080022451F20884CCB9CD203C141402A5AD293C3BABA95ADFAF6726384795A7656B753D2369B9EB5595BAA722012DF8DCFBF15BF46D6EB755D1CBF0DCF6FD40BEEC16EAB4A6D16839C98CBE9DBB437C69FB709F8E79993B9DDFE4F823D6E124B75BCE9B29F799F926619184B6C1178389F07349210436293A130C900FBA4EA70D2BA25B343C5B026D8E8766A4E4267CDAEC99E830D2307D94E6ED80D6722F3989B91E31C63B64C363DCE71A861C14382E270FC02868C7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h386BA04E797A3F8551DAD9D24A8D259A03ECFF5AB81B1C31DFDAE10100544F8CF1A8CCFC0C7A15BD9E7C2557CB00BF2584E16AAD13D7EDB525A85ABF90C0136DD195D748900C29DF7F381280A9738CDC3BF5BBF937D3A4D99CE2BCCD97CEF2C7F00030AFDB7F22E68CBAA4D9BE7633D3B53E90E4B124422A2A4454BACA5A8DC9352CD1DAFC910CC504334DF9E6F1F4F30161A36293CC5CCF1CA13994ED29D34A5699692496359B8E67A7E74D9A0FC504C8465638CF74A0AF9185921A7D2629893091900604017933442359491FBAB63F346F0C5EC8E3A531984B09E605A30A0627271C28420E47B8DEC74738FC3EDF9FBD40EC09FC7B4D3A1475BE433705FB5F; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h973FED2E9BEDBA474B70B121A8D60F3B4EE3F1A238FB3B730EDEEE74EC632DB4D7779D7B79D1C75DF87378E98719C1AF38B1B801C71D180CE86370AE9C2BF38CF84DBBB9878C55457324E92D3DAE91D729AC76BBAD4C6EECA74DAB5EE9A175EE34ABEB9DFAA48538A57E3E5C158947081CA41402E8E65478737F73BB629AAE2EE51D405CAF70F622DD4599602D7910DCAC8214B2A42025110593202C8B164C8DF6369572C3BB8AA1984A8D12F776E224ECEEB21F97FCD6C0CF17A044EC2BBF0571A553CCDD8ABA79BD27B7AF735ED2D34F1EF3A81A160C9ECB1B1FAE6EDEEFF99E28CC30C7C2553DED3378D655AD194B2E6C1BCBED700F6713D960F33E4C361A; +// synopsys translate_on + +// Location: M9K_X33_Y15_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h8102080042447C443C0C3C402004FC1838787840407A00707C02487E444878428008004042460424402040024A3242124220044022404208520A4A24424A125A0A1028440000524A0A4A4A204A5240460800100010540042002064547E0600001FA9BE02B828694B8A82CB8C8158226808198E9EC6B021F07A2098D5E0ECB639D2B1908129B6A2D646516192D87593189D8B2B26CD6E16234C1CC90AD9831EBD89EAD271ECC39A80507716BB49626B743DFFCF99576C3FAC889860E46618ACB79EC30EEDE42EB1E31F3976CA23243179FAA96DCD66D51535351770D410DC8531866136E6184518410368288C446EC63A4FEE425019C244097049C2B2DC8D93C4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'hA111466C9493A2A7CA2204102414CC798BF0EEC2995A4814580BD07585585ED92E5172E82E845070000A846100500E84EA1803B8B07B99E1DC75BE6419674597B38F54EB9091AE3320201EE395AD63902282A031CE3E87CC902954AA515D5D6B6A855EC94CFEC4E0172C59A7D054F8F9F4356C312C204E40B05E2059407C8DC84683814663FB910969D1D631A952B381B7F635A33FD38D5CF15DF47D057F7FF555B555C2278100000A24804D7D98EB98602733818A12094F281287422CB40002464C92242004E0AE8518E001D124A7628010115D23C30462FC00A014A12133582A191E00538FC8A5004036A959ACB7A463D23E419EA06B744005385455A71250; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h6C60009CA281AEACDC1762945981B869F93D683EAF4AC7EE52412E85B60B91CD03AD0025F0D509F63202D877ECD8BF8005451F7BD346CF9E17B36F1850A7D80A8CF14A288EAE3BFE00FB2DB45080D4A50C58263A3B398DD51AB9CB554ECAA7B2E73D9D6D2C265859DB844C2C1952AD10241100174FE0444E6707D80A098D8585AAAC4802B74190FB007C0C0206186AFC1B3A2A46864F26118ED1D03ACB1062B7315502751655F60070E6B2C50609369611365AD1E3352327320331A51818030C7D8C4C59396600DC0C420495A0D987501490002BAD38012E20620D556A230B1796450B74E95A860FF3E434C65F1308F16F92395816B914F0CE870C1323347A4E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h7FC8531A7A319F3EBFC1383FFCDB0E09BD288288B078B4AD220B6FA934CF6187D972662C0D31E34E63B31CFC6EB4B35A69B67D85489E62EA99899A94F6800FDBA5D31B86A0288D29CE2EAAFF86A6A9F7000082293E6BB54F06E98ECCB199973EDA00FADB1D3A630BA18050635DE7DCB13B9B86E0CE6E08DC46331A352F716E3C441A0CC068A0823F8668A00621B779DE35FEC004050469F34866AEE766743D8C00FDF3B9F8DE7B76E97F8D32F0F39E4CAC68D9BBB68EA3915F6225F932CAAFDAD6E60DC661155EC9E80F8CEE659F19CC554B2C67C33EDCDA63BAD91B7D1842A7177AF49DF118FE47ACE3344964EBCADCFBB543F7729CCB340866D1157B6CCDDB; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N28 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ))) # +// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout )) + + .dataa(gnd), + .datab(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2 .lut_mask = 16'hFC30; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y17_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'hA504087E764CA02840304044540424244404044024804008A40A54484448544A800400207E4A0818204040024A1262124210084014407E08520A4A42424A1256522828280000524A124A4A7E4A527E4A106010607C38003C025408FE2400000087857B4051593F8FEF8A4F84E99E6FCC30DBEF9DDB582A41325A97B1EEE4166FF390FF8420BD829D1679F5F18B57EAB9C5CFBE75ECF7F3730C105ADF74BA7D7F9159D64BD7F217C1803F5B1169B463FF6C6EC899D6482FBA8E6B53DCF12F3BFFBE72266D55B4E9E5887FAF8840007C50220105C908100BAF6FBA7BF97E6E020792ADFDFBD96CFD77B36CF30CC5DE43A85FB6F0020203478F160F42F9A061FE44; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h812017671773A9EE08641F818054455F0BABE232D2AA00081423C0BCCE1E642C4B7AE34419240F3C0170E001D6CE75F0475D5A8A9012B9BD97153AB038EF6187776B42A5FE80BB5AAA2A550A58904A1C6DC992952AB4532C6CB2F975BC101356F70811E17D8C73F1D9BEF7F7E82EFAE6C2D2DB2126004D81CA67DACC344F6458C165510222E12BABC9B940EB70182EDBEEF007365AA980A2002829A05282A2AAAA8AAA32A2C38012BFEB492278CD27651FD91BDE452EEF054801275AA0D49D9A896B7EB5FD69B679669CBA00AA9A431956A3CE676A9D7B50D84F3FFFFFC4AAF735995E3ADF9E07EB861E3035B1EF3EF935DAFFFA1F94FDCA5B803F14101BE318; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'hCE21FFE0D222852612C7A87E8DFE961BD8CF052D4757559DF3ED2417472384AF04FF86DDFE9FCBD3DC2A4967F492CDD5A8FFBD9857306D8B07F3AD96A6138C0360BE688D11B16D7936F4B55E0E301BAD6A96802B5719271D55D5E93FED5335EF86E8AEC1EE37F6F5FFD77F204F5EBFDA614C41C1F85C32FFB05F2881BF7EB1D73DDBF48E39F1AE9FC0A7CAC2B4515882877D84D415C7A00D91E87F57E95B60EFEB9963425C951C00298F26A884C3AEF0DBF539D04E867EB6FB957E817C230DFEE3BE607B3FAC5DD39FB436C5BB7926D7FFF03EF787FF563C3FEF787919A8383DEF3142B9927BEAF99BCFB066319F5BDF2EFFB11686607A73BE9CB85CF6EC52D0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h420539B476E305B8200E47DFAAE8D5D1D0724DCC3FD72C4F8DE54622A1DD1BA78CA3CE9F24BEFA9E2BB9D89B423C327C8E050114401A62FDCD2054E166C0005F7941B61372AC884EE60A372057B59CFF30A6020B875C06E7C5FBDF9A91F8F0588ED67F67AA66B0674CD240410F613700B8DFE7F8837F88FF4520002E4BFD7FA2768008002000002624793100811F43BC315A6004052671392B47FEB7F5DC90E62175C7B8FC48FCC916D46F9315DFDECBE43E5F03D7D27F97E09E4700AA694552A1FF3BE5E159FFDDEB2FBECAEB87BBCC5FCF6E23D77E4DD4C9DEBC93C10F636326FAFE3BE30DFAF7B9E7A5FFE44BF314DAA1C1529CDBFFE9D94EB11A9F68D4DF; +// synopsys translate_on + +// Location: M9K_X33_Y18_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h7BBD7F79FFE0AB8FC33758D1C1145DDD6311CF69FFFDF62EDD236FC6A0358FA2B4B15EB89456517DFF58F68BDADB95B5F764CAE7E7C7E7D70CADB8FFD8F9A72BFBB9EB400590D7F939FF5A70A29817DC2CC29B679B2D7146BD21D47EF06F7D5EAF72F66DC666B0726D66FD941AD9BC6D758D5EC24DFEBA64871D6B86D37DF1DFBFF05FBD6AD8CA62C6CBE43BDBFD99E9EB6DD724D235FBEA9FE7D6767D811C40681A00AF8D864D8BB6D2A0916C8A93250A76B8A977F82E8FDFBE68F8E0F8DF237CA976FE488D1069D687A6F1D68A70F37CAAA367A74CBB75D3A6FFB4B1E8D4B7F7F22D2FE1509BDF80E6DD7B717D7E9C6531C3A86BE9F1D7A6AFD5BFB7A37A60; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h8AB3B7FDEE7B9CC735FCCE93E3AC1AAAA691AD6350E57F1F5773302B6F36F63D130E0574D6BB44B2C0D7A907702A748D0BA50F8FA5437ACD3B343C35039F44D19CD4E55E6CB00410842B02A7FD105706DF9E2A1FA025005632A0CC080400D280CCCA0665222D038CC873351A21B23939A98CC08803282189C8440D40CD40462421A40982C046D22C10146484345CAF7BC828BFE79DFBE3C631CBF660C487EBB759BD7F8DE9E0F27A65DE5245BEB8F7829C36F0D136168F97C2BD77D649A39EB4DDB3A42AC80797FDEF4DE3EEF7ED8C7307E4CE6A6317F7BF25D077BBF03AEA3363B065F7D671322D6BFB2B8759433929CEC27E3FD7741292A4A5AF02703CC4E3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'hFD5CB07B6C729B510A78BEC5F7C7A1E7809F1976D0DD3615C1D27D2DF596BFE7A8BCDC2E6655185CC45008B39EFD1FA6E9F5E816114F93E1E7A2A27C72C7349F3497229CB9044B6E7A7861A04A712AAF29EFBD393727F1F3FC2AA1E6CF571457F0A09C47F23F20FE2AABF5FD3ABE6167E5FD36E1D9735BBD5375C1F79BD0424ECF133BF47B9D3DA46DD6DBF3A8ADCDD3DF1176D2FE23447DFC65E1DD7BF3BE5E1C9DCD8EBB9D36AF570CF25CDD16F645D1DE9F9EE575E3A2B91D5659FC131CE3DCD4560015805B13AC0290001EF8261B7E4EB867C828D9777FFF47B6903008DDD7D77EF5E2C6D7220BE64B3C6E9EF22AFDFCC8005C2FFFFA3AB9AD1ADFC0AFE7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h06ABC52D5DBEF57EEB3311A9D85D253B44E250E1566BED57C6DBEB2ABFD1ADF6FF4DEBFBDEB376DF68D5EEDB5EB4D5AB5B79745D76CD8ADC59CB30C8AA33E1551D2FCA8DCB43C5356BAE638588C302868CE1161CACADFEF7696F8C3AA82EC16F47A8EA413A2DCF09B996582318DBF3C4711871B3BC0404EC45252A485234A663C1FFFB3487617BE24FD79501DE05F1A341B89EC82FD5702497FD866639C0DE08B383E6E7C3B310E1F7FF595C5DF6F0E9A9FFFBE16D3FFBE82C1E0051F1E060D500812F408CC6501331852531B04480021D9220D4903A41404312032840153FE9CC8070206B8245AC240020752EBC2BEF3E74AB288F360C239C4AFAE93F68775A; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N0 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout )) # +// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datab(gnd), + .datac(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3 .lut_mask = 16'hAFA0; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y18_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h35861A00A6112A1481AF1A50A6004A05291627227FF08229B87389E08119A28A7888672DC999B7046A61E60810A7434450E3D33E330F321A18E8A120D1EDC8623DA2C64840C2CCE811522B42008095E5A456C98F4B25EAEA410610545024640CF10410AC463BF9349074917E9A74A12830EFA280EBD3131E484A255D0191C6852730A263DBCCAAA88712242B3BE49AA5338990229B391158C726BC7EB4ECC32308980020680249882691A680488292310B4313CE87FFCD5329A64B708CAC8533316412C4900F646A36630261DA093053D98F19D2C5B653165D4A71AA5682B29B89B6054CC727D292805705A93268676A31111371390B240EC3CC85D331813EB1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h1AA1C248D293110CB951445117D9B6AA500F65068B8CC508BD00184F8705B010A0CC46CC9302649242CE08191634113154562B149100204551178DE805D98EC8A2E5A64B241400267194CD524499BC01D31058CD18684A817A5800B65143281C1310B00A49902C0104004C654E0582040001103654011012021912281216B000C653A0510A1B00C36AC88058CAC126E14E198DFB07E81C3F41510BB08F8F851C3B9AF0147BC1F730B4E91D9D11C3A8F1B82DF19988ACC44072FDB17B4D81882E9DD952B29003D7767BA581A68BC41C2B16AD6EB57F1D048CD4E464190D25ADF2C194E3598360AFB031A1690F4625BB628363B4C90A400E3A04DAA70DA0CC4776; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'hC82B30671933680037A65978674DDEC2D30EEEDA78F5F2A1DEE660FFEA11B175DCB42E9277212A58842051A078007109A0D820166B881042600284403143048295D23A0E191EBC2134B833D53D37E42B05018289A10300A188E315CE98640F548A370D60A0AA3E7288A0B0869FA5E703D1AE17C0EC276B2AFB747B550A8B41021620D1A60A901095D12A0973B95E20838001330138951361967847D42901910A3488480610A91A851E84FF08783F81AEA52D2FDC2200BD2FE81C0357FBEC1D875686C6CA41B2224C88D8456C1DBF20D820A6649774CB11B69933246E9739C998470542C2E3C783A4C24767084C52DC209D60E95DBC096D9A0171A12D5AB99BAB; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h17A24D2C636ED2478B5AE1C99D40761B1E7AA6A89DDD1BBD8DBD223E70531BCDE90C8E38C8E0478AD8B388F94891C9673A50BC32478E083074657E8E0EA53BEE861F8BC1993560946D92D1C0C7F046A245B5849CB751FF15B97FCD50BC7B8524C13E7C640F3645082248D1CC14296E30DEA3057B35C641762CD00D40DABC27472251A60725008AAA056591C4000BB48C0BC29B8034A03400027B84769B520D9196968460CA3388A03ECB45F2C4B70F1829221000FFFC7FEC346F079F13079798EC2A08157331C6CC0E30884244916A0DE26D4D22454091290404A492016887E2111F830F9851184101370588A06D3BF9AE621A5F4E632A6799C83EFAAE06769D; +// synopsys translate_on + +// Location: M9K_X22_Y17_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'hA50276000854A0103840403E540424244404783E18807A08A47C54484448544A807E7E10005270182040407E4A1252124208084008404208420A4A42424A125A024428106448524A624A4A24425242522060108010543C00044A105424005E0031ED1E0529E507AE2F6FF1CD51D4C772A648E65F6532C28022061303F06C36CDBD319B55CB8E626C20E46C93C1463A0B1CE594F0ED3B62330C104DECE46CA6CD966B1386612C7B43980349408F36FB64C14342DAE26CE4D8D5E791388729D743B09A27AB81D71A14AB3D24E385B602248476D00249239514B58D3098504ACD119B99E9021B650A69494C22600667473128DA5010D2195982823226DED0ADFCB8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h5861917919344A4685CC0990862A11324792E761B6D41C0FCC0838C1C27211A2453FDC2219C225E421B320085A8FBFD0C42135B16448DFC226E09B3438A740C352979565817114DE46462844A57F7958873FC4B255C8AE549BDD1A87415D5018F88D5002628FFD13203066C850F10649F21319109208387641120B362124803F0678522BA2812C1454A502ED1A59CBD76A034756F5765DF7555F57575F7F57FFFF7FFF7D5712524D4A30723514B2B3064A84B4742D48415281863DDFAA9D9B7E7BB16DDB96B7845371C30B55DB96C8F6EB4B453242FF6A4DF84A76B5AEDC88A68DC6A06905054C8C36E4199E74638E6532965218A965909BA456000451343351; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'hE2975A2686A7AE0288F140141B698E2A82A835F478453A1D722CFCED12859FD735188757AC5A42DEB501FE010586249AC1EA60D08F74CFA5086EC78FC9190C056059E332C311521E6522901852D484B423A98816C9B26A08C92368E9FF05524502288A804612A2A0A102A418CBDFBA554499541660F8124640110101263142892A086B442661015380041594608092D9CB919250100A37DDA3919A1427F660963C251301FB2CA45562245308885131119115C652B2493252340201101942D26000CC60799124A8520C08050122171281808058018C38A645D07931896B39ED259A22242CB58413089465B246231330D806105010035100B08761A08506094160; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N20 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ))) # +// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout )) + + .dataa(gnd), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4 .lut_mask = 16'hF0CC; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y15_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h990442000864A0284030400454782424440404007E404808A4005448387E547C8004420800620824402040024A1242124204044008404208420A4A42424A1242020028008000524A024A4A284252446240001000101042000054265C7E0600007FAF5CA001C181BE0C02418447B1D88BAA85409896BC7C0E5FAC2529CB69A4038E2564731F88FE730045956C357C5ECF7EF8591DF2A8ACFFBFEEF268CD9B51238594AF691A9B8640983B7F76AAB97209EA6257389992FFE684926E0B19FA338B8489D73811171D5C9FF3DCFFFFFF8002000780101F3F4035A0CDED99F79A4775854F179F7D7DBBCF81B2F6421FF684CA6AF85894D29B9D3ACCBA3F27D9DC9911; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h5B438D714D4E3DD115E8BD1286EAB5FA1D71BD8F4508BD4BDC8838F9D27B552259BCEFFBB68A6FF529B3B0D92970010BBB6C7D872421210E190E1CCC47A485EAD2F8735647315839EF6F683C64773FC73464D5FE354936D50823A5DAEBEBDBCC6CAFF2622B8D518F63C6030424188FD357718970D25A30CD0731E532DB23002D02C12B12378356DE2C52041CA7A320C51E0D7CA9F5D575775D57FD75DDFDF75FFFDFFFD75F145247F03A0AE7F1E1EB2D5A99D2444108C6A5979B7CC26ABCC241EA4C912568003BB493CE04FF086C188980052BF6ABAAA2FD5D658000011277EB924C10EFAF3CB9B62486512344C61ADE6F15AB67F335A52513FF05AFAEEE8400; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h0C840083AD485153ACD3C035591630199B8C096CE4DC557D6D55FCCD738573D6E0948817C496E9DE8EA1F88F627B7460106691CC452DB9799E59A5D003733C4EA1BCE33AD2D8BE40A4E5BB7D7BBEC2CEADBBC8B6F87A4A56FBE0B891DE57E4C64EF9AD87727C49CFE7C5DE942B72AC7F6D97DE18920777FDDEE9EB11122A4E18F5569FDE08906765428FB9E6F89FBF0DEAA6064637BCA63FD02E273E5557F0548662C97BC2E8D3FFDB26D23E87BFD97E635A6560CFD93F8EED26E30C70DE8633D6B97C86DF7D9BEDFB99E36B6658F16C6DEFBDD5DF728D6209C852C37FE67CFF32EE4CCCECC64F7E6225FC99EC64C3B6DD7DED0FD7CCEA3BF09A006ECDD1009E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'hA9C9CE3AECF7BE27C000000A8ABA95251B309A60B9DDC19EC3E391458CBB53CA00A85E3C5AAE2C49DDC2F6C7B013DACB319A769818A1081A7389F711D76A09BCBED23D9A99FF9B77183697955D76BF0E0008822742DA45B883C9193DAF09424501859565800698515E10A8189EE9B323E35CE7388D73C6E7A50D0DE6739C73AC538D134115D860ADA57B5B868E54393B1E31E762062577697D57E8464340420E9434CCA34CC9A1CB1FAACC56168071EAC113F5265D5F6A45A098D604A820508C4EA47F9A7E46083716911B0D585CE937B530218E8D2AD3777EE7D3B4BC56C29ADB46809D15D185F8809229B150C29C8081174CA6173B99703DA466629005C604; +// synopsys translate_on + +// Location: M9K_X22_Y13_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'hE10F8B8C100323720BEBBDEBB81DF13FF97B252E2CB4F27BA091FBD0002D1A611E1EDBBC716D44D2912B80041C44558060CFCF15955C0D780DD5E71393920844F25E16C87C5D0308EEC52C011514BBC13AFA1028924D0C7CE738105BD47A10AA5B5C1D9D4193E4339F492B0E1A64E13AE35BE6B67AC8057BDACC155F14E906A017A1841358335450D4B26CD2A21B3D8F2211080B81EC040D7FA0B51CD48008112508062020A02490900092D2040259108806A328F4006D2AA514B42FB006ECCCCB9A360865678449975A8AE72B5C0F7BA800C1B5DC55D7D6FE2EF4EED85D00AB111821321BA426A4FE4956B43595832C271E83E060341AE5F2023FC808177383; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h1A2955372D510AC266A5445146E27000020C320FAE1557E37154040A13202DC6F40B840FB9A59B6DBB296562CB6220EFBE99D2776A202044D9101006FD221D305519198C859000004012AFF4FB060307C92BB732203BFDFEFFFFFFDFFF87FCFFFBFFEFF03FFE0FFFBFAFE0FF80787FFF7FFF83F7F87003FFBFFFFBFFFBFF0FFC0FF81FFF7FFBFFDFFFBFFFE1FF0086F3141AAB6005810A0621595A893F9D85983B9254954341968BAC8C141C90938C05B2C9CD267E11650407375FEDD6A2FEB346AAF6CFDC0791AA97B741995A3B3981E06D1A44D3711955197BB9910FCA20744915C84D6C24BAF53929814CA8A4697E8F4201145AE7415DC122A5F010436107; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h02E84F969E3C800AC610D276182020227809001A50DDDBA3487BB6AE802BA06509312DA0E620656EAF24D57C08FFB14D289613DC32083803B84DC6415FD5EDC000300A8D128FA20030ACCBAFA237B7024504D36A4BA26081137F059E78991154FE2AC2A884A8CC7FBBB21C851CC92B12E15593C0C020FFEE066558590E882D5B67459F1A8C3240FE4E6A8D028C0C088FCF471D400A19B38211004DD122212288B111114514CB11840E04828849C621392041163C00808C67223422F00110201DD18FCFFFF3FFE7F9FFFFFFF82C0B422D214711E08904524A069491774E663F48F665955B4E2C63DAC0078652D10120900298F7EE380092442AFD400BEC43C003; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'hB5D49EA9D7036A45AA9E870B8E8016720C7C3102AE925262492C84584942D209042216E0216C85B8912250B7157D5955AD406CB685BBF071B47D5193363C1CECAFE59E91BF11498940A0944996D47EE8D7E3A4EAE611AE19A965D01BA86B55E9C52A6A379A382C6C265FB0DA01396D0800C0046405C06F466DD18C4DD7655CD4E7622EC485808C841D64B737041FF68813B149A41531A0A692FB14AE2E5B49D49CDCADCF90E7BD88125BCE706BF6D04AABFC1C001163DC6EFF7FD3230303030000000000000000000008400000000000000000000000000030600000100007E00220000000000000080040004023AD496997B8C0077B886EEF161CF2298A091B; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N20 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # +// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ))) + + .dataa(gnd), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5 .lut_mask = 16'hCCF0; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y16_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h4200420000441C443C0C3C00480018FC387C7C000000007E180038300000204880084204004204423E1E3E02247E3C7E3C7E7E7E7E30007E3C7E7E7E3C7E7C3C0400000000000C34023C2E302464003C00000000000000000020460024000000FF991E65536D2D8D9C9B4DB081C83A5A881B0DFDE2D72DF0FA08FCD6F664173D989098D02025E0F6043B4B9080F4923880C3A3B02D269E730C3DCC423386DCB98B4AD0C5C8D6119602E5121008325B7457090E914F4876EC8A18C664210A4C2392C7658400073421047C75FBE7BE73FDFFF05FEE07BF8AEF7F1378B359E8C61F8F692C2218C98A4A8748531986E7C770D984E0000C02060C000C0DF50F68A580; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h0100046606572583002086010800054C0F2DE8371AC0000A9003E024840C7C0806F6612D770080980A40D293FEC069F16CB2164CA033C539F69B37741AEF1CE3662FF5DF9CB107BB23A39EF7B95E7372200448DBDC18F9C0DE0EF379BF49480657781E91788044213E091339886F337D0612CA646CD48FC58EE77EDD7ECEC466C744FD00E1A7F9E9FBFE4777FD50ABD11F0E57FF4808802282200888A20AA88000000008800AC11D556264251ECFA68C056FBCCB040C614A6850222300D2F6FF59F878FCF5689FCFEF34BFD52FA2422A56A3C113409F7813007F8D6B5F80FE9D7FB1E62675F7C2CBE01032DCA16BADC570C1CBF7ECBC4E7E6C54A5D4550BE1A8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'hE33CB578DEBFAFAEDFD530DE8FA1992072F31B116644B18C72F9F44116C79ADF2F3982C7BE09AD4A32196807648A2495ADF98FD2B16CC096A5E25F5BC811C953CEC3000F432029B3FE3F211712944CA54D1940F193204C199C9F49666CC11B38C23B9D130CA49818913D3A2C1FBF71C5B0C774336F903C677D976189D98CA127AAAD6B6AF36195DA637C6EFA3E36E8FE97FA02EC26EB46198AD8DAD8C11260AF499D7BD86619EE5574CD27C80D39F71E653FDCF1B366737233CBB98D1E7B330F7DCCFC5939C4EC79CF0E1CD43BA7AFC716900A21BDB9DD0FCC7ECE1063238407C7E1B221EA10E38F64EF31CEBF3368E1C712BB1B33781134CFE54C2123349A6E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6; +// synopsys translate_on + +// Location: M9K_X33_Y19_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h3C766E63DB6481CB39BC8C68831C724633186CC1BAE9D608A5DEF0FF219C28C1EFF4FDE394D0E19B6FD89186C23CF071E6F1CC8F7FC4F1E48756B0DCD8ED6D0C3DA139003D7A86B2F878DD99DAFB70DE1A19F3FB7DB3B8EF2633007664CB19992E43664448EFF06072648DBA32EDB76E26439BCCEF2DFBF664594B04FBAE72A84A3E508B49DC6BEAAB4F3F0CCCF6D8F568F2DA00EB384A7F53249323198000100408002024010408824080002008011482ED5615E40012EE630C3B2CDB2C13A736DB5B7BD2850018CF936621C6863095A73F7BE7442CB13110B9C0BBB96EEF16CE618EEDCFB393738178C476C367909F71307F6803F677575763DB2D8C3118E4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h881331ED7AC4EFD38DFACDBB236790005719AEA2FAECCF0D126A30A27222D61BBA428334561F4EDB60C6BF8DB6E267BC56CB69BBCE636CCCB3B2B4B103CC46D5CEEC06DAECB0001569589D5F267AFE086C8FED5DE41DFEFF027DFDFF7FFBFBFDFFDFFF6FFFBDFFDFFF57FF7F7FB7FBBDFBDFFDBFF78FFDBFFEDDFFFDFFFEFF6FF7F7FDDFFEDFF6FF7FFEEFFEFEFC4E51EC0888848E1F2044B47B66608D8A3B3919B9466E6D60D27565964244B218B48AD83430D996068EC908D9E112096996041D77401A0C0CCF5DEEE561F7F7E68CBE72E48E570B047C772CBACC33753080E32EB0B348C0B62337739B1BC73192392592C84E37B7AC141CFE65EE76D83C9083; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h1C5CF062CA6F13854A59BDEEEA07E3C6559EBB3618111895CBBACCBCD512B5F07D361CCE72B925658DBE1F7C4707E195C5C665B8118C3C31B196C261DA85A5E11889D25CB816ACC6627802052C61A4099B7B0EC923971DB3B9F9204BDBCCFA457EE296E8986E64C6DC99E59436641567648CB84DEB7D7937F974F038D838274F3D3CF1BE8C84DDB000565880A776E5C0E13166E49F47119A4CA1311CF97B965E7CBBCB2CB384BD0D92ED105D0617856E80441124B31DE58B8C001607FEE668899693E3EFF8FBF1FCEEFBCF7CF9BA6C37640DDF7FFE6187B19ACF089D4C038F6607B78D38001FE67E56CCE399DE36D7DDBD699D5CFC5B6D7A1421CE06FE40DB6E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h0776C62C316FF94B0BC3A0288DE6A62B14D6C1A2DADF9BDF85B2CCB02CE1DB2D96632C3232C3974CDC1172E1779D8C6738251819975DB8146067301E0C0277B6B657485DCD62AC0662C8C005DDE7494C9CA13AAE3234BB0EE1B708A23A2F48AC4C3838641E940620F9CDDCCA14BCC07104C112BCC9032C48E925594CB886A604C9F7627EB100872A52FB5141D65111E6C8DA0ADB6CEC6004461D0E366B20DCCDB607E624499300E4DF6D95CB62F62FB75403E400EFBC3BD34080FC9CDCFCFCFFFFFFFFFFFFFFFFFFFFF7BFFFFFFFFFFFFFFFFFFFFFFFFFFFCF9FFFFFEFFFF81FFDDFFFFFFFFFFFFFF7FFBFFFBFDC0A6DBE6F8BE5BB7FE7A39B3DA3F3BE13B679; +// synopsys translate_on + +// Location: LCCOMB_X32_Y19_N0 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout )) # +// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datab(gnd), + .datac(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6 .lut_mask = 16'hAFA0; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y14_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; +// synopsys translate_on + +// Location: M9K_X22_Y12_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N12 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ))) # +// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout )) + + .dataa(gnd), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7 .lut_mask = 16'hF0CC; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7 .sum_lutc_input = "datac"; // synopsys translate_on assign LED[0] = \LED[0]~output_o ; diff --git a/simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo b/simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo index ce4aabf..77d78f8 100644 --- a/simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo +++ b/simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo @@ -29,7 +29,7 @@ (DELAYFILE (SDFVERSION "2.1") (DESIGN "spectrum") - (DATE "03/30/2022 12:38:42") + (DATE "03/30/2022 13:12:28") (VENDOR "Altera") (PROGRAM "Quartus II 32-bit") (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") @@ -41,7 +41,7 @@ (INSTANCE LED\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1253:1253:1253) (1226:1226:1226)) + (PORT i (1517:1517:1517) (1544:1544:1544)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -51,7 +51,7 @@ (INSTANCE LED\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (1304:1304:1304) (1267:1267:1267)) + (PORT i (1454:1454:1454) (1428:1428:1428)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -61,7 +61,7 @@ (INSTANCE LED\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (1684:1684:1684) (1627:1627:1627)) + (PORT i (1610:1610:1610) (1575:1575:1575)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -71,7 +71,7 @@ (INSTANCE LED\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1346:1346:1346) (1276:1276:1276)) + (PORT i (1039:1039:1039) (1034:1034:1034)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -81,7 +81,7 @@ (INSTANCE LED\[4\]\~output) (DELAY (ABSOLUTE - (PORT i (1648:1648:1648) (1591:1591:1591)) + (PORT i (1347:1347:1347) (1342:1342:1342)) (IOPATH i o (2277:2277:2277) (2180:2180:2180)) ) ) @@ -91,7 +91,7 @@ (INSTANCE LED\[5\]\~output) (DELAY (ABSOLUTE - (PORT i (1253:1253:1253) (1210:1210:1210)) + (PORT i (1969:1969:1969) (1936:1936:1936)) (IOPATH i o (3961:3961:3961) (3539:3539:3539)) ) ) @@ -101,7 +101,7 @@ (INSTANCE LED\[6\]\~output) (DELAY (ABSOLUTE - (PORT i (1728:1728:1728) (1679:1679:1679)) + (PORT i (2280:2280:2280) (2169:2169:2169)) (IOPATH i o (2194:2194:2194) (2119:2119:2119)) ) ) @@ -111,7 +111,7 @@ (INSTANCE LED\[7\]\~output) (DELAY (ABSOLUTE - (PORT i (1370:1370:1370) (1374:1374:1374)) + (PORT i (886:886:886) (919:919:919)) (IOPATH i o (3961:3961:3961) (3539:3539:3539)) ) ) @@ -134,29 +134,12 @@ ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[20\]) - (DELAY - (ABSOLUTE - (PORT clk (1352:1352:1352) (1368:1368:1368)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~0) + (INSTANCE counter\[0\]\~63) (DELAY (ABSOLUTE - (PORT dataa (222:222:222) (295:295:295)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH dataa cout (376:376:376) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH datac combout (312:312:312) (325:325:325)) ) ) ) @@ -165,7 +148,7 @@ (INSTANCE counter\[0\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1368:1368:1368)) + (PORT clk (1353:1353:1353) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -176,15 +159,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~2) + (INSTANCE counter\[1\]\~21) (DELAY (ABSOLUTE - (PORT datab (221:221:221) (289:289:289)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT dataa (230:230:230) (309:309:309)) + (PORT datab (227:227:227) (300:300:300)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datab combout (306:306:306) (324:324:324)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) ) ) ) @@ -193,7 +177,7 @@ (INSTANCE counter\[1\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1368:1368:1368)) + (PORT clk (1353:1353:1353) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -204,11 +188,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~4) + (INSTANCE counter\[2\]\~23) (DELAY (ABSOLUTE - (PORT datab (221:221:221) (289:289:289)) - (IOPATH datab combout (319:319:319) (324:324:324)) + (PORT datab (228:228:228) (300:300:300)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) @@ -221,7 +205,7 @@ (INSTANCE counter\[2\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1368:1368:1368)) + (PORT clk (1353:1353:1353) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -232,11 +216,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~6) + (INSTANCE counter\[3\]\~25) (DELAY (ABSOLUTE - (PORT datab (220:220:220) (289:289:289)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT datab (228:228:228) (300:300:300)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) @@ -249,7 +233,7 @@ (INSTANCE counter\[3\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1368:1368:1368)) + (PORT clk (1353:1353:1353) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -260,12 +244,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~8) + (INSTANCE counter\[4\]\~27) (DELAY (ABSOLUTE - (PORT dataa (359:359:359) (404:404:404)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH dataa cout (376:376:376) (275:275:275)) + (PORT datab (228:228:228) (299:299:299)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -277,7 +261,7 @@ (INSTANCE counter\[4\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1368:1368:1368)) + (PORT clk (1353:1353:1353) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -288,11 +272,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~10) + (INSTANCE counter\[5\]\~29) (DELAY (ABSOLUTE - (PORT datab (348:348:348) (401:401:401)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT datab (240:240:240) (309:309:309)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) @@ -305,7 +289,7 @@ (INSTANCE counter\[5\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1368:1368:1368)) + (PORT clk (1353:1353:1353) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -316,11 +300,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~12) + (INSTANCE counter\[6\]\~31) (DELAY (ABSOLUTE - (PORT dataa (359:359:359) (403:403:403)) - (IOPATH dataa combout (318:318:318) (323:323:323)) + (PORT dataa (229:229:229) (306:306:306)) + (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) @@ -333,7 +317,7 @@ (INSTANCE counter\[6\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1368:1368:1368)) + (PORT clk (1353:1353:1353) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -344,11 +328,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~14) + (INSTANCE counter\[7\]\~33) (DELAY (ABSOLUTE - (PORT datab (358:358:358) (400:400:400)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT datab (226:226:226) (299:299:299)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) @@ -361,7 +345,7 @@ (INSTANCE counter\[7\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1368:1368:1368)) + (PORT clk (1353:1353:1353) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -372,12 +356,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~16) + (INSTANCE counter\[8\]\~35) (DELAY (ABSOLUTE - (PORT datab (219:219:219) (287:287:287)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datab cout (385:385:385) (280:280:280)) + (PORT dataa (229:229:229) (305:305:305)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -389,7 +373,7 @@ (INSTANCE counter\[8\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1368:1368:1368)) + (PORT clk (1353:1353:1353) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -400,12 +384,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~18) + (INSTANCE counter\[9\]\~37) (DELAY (ABSOLUTE - (PORT dataa (220:220:220) (292:292:292)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH dataa cout (376:376:376) (275:275:275)) + (PORT datab (227:227:227) (297:297:297)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -417,7 +401,7 @@ (INSTANCE counter\[9\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1368:1368:1368)) + (PORT clk (1353:1353:1353) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -428,12 +412,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~20) + (INSTANCE counter\[10\]\~39) (DELAY (ABSOLUTE - (PORT datab (218:218:218) (286:286:286)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datab cout (385:385:385) (280:280:280)) + (PORT dataa (228:228:228) (302:302:302)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -445,7 +429,7 @@ (INSTANCE counter\[10\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1368:1368:1368)) + (PORT clk (1353:1353:1353) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -456,24 +440,34 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~22) + (INSTANCE counter\[11\]\~41) (DELAY (ABSOLUTE - (PORT datab (360:360:360) (398:398:398)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datab cout (385:385:385) (280:280:280)) + (PORT dataa (658:658:658) (680:680:680)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE counter\[11\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (294:294:294) (300:300:300)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE counter\[11\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1368:1368:1368)) + (PORT clk (1353:1353:1353) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -484,11 +478,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~24) + (INSTANCE counter\[12\]\~43) (DELAY (ABSOLUTE - (PORT datab (350:350:350) (399:399:399)) - (IOPATH datab combout (319:319:319) (324:324:324)) + (PORT datab (226:226:226) (297:297:297)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) @@ -501,7 +495,7 @@ (INSTANCE counter\[12\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1368:1368:1368)) + (PORT clk (1353:1353:1353) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -512,11 +506,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~26) + (INSTANCE counter\[13\]\~45) (DELAY (ABSOLUTE - (PORT datab (359:359:359) (398:398:398)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT datab (226:226:226) (299:299:299)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) @@ -529,7 +523,7 @@ (INSTANCE counter\[13\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1368:1368:1368)) + (PORT clk (1353:1353:1353) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -540,11 +534,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~28) + (INSTANCE counter\[14\]\~47) (DELAY (ABSOLUTE - (PORT dataa (358:358:358) (407:407:407)) - (IOPATH dataa combout (318:318:318) (323:323:323)) + (PORT dataa (229:229:229) (306:306:306)) + (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) @@ -557,7 +551,7 @@ (INSTANCE counter\[14\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1368:1368:1368)) + (PORT clk (1353:1353:1353) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -568,11 +562,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~30) + (INSTANCE counter\[15\]\~49) (DELAY (ABSOLUTE - (PORT datab (358:358:358) (399:399:399)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (PORT datab (228:228:228) (299:299:299)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) @@ -585,7 +579,7 @@ (INSTANCE counter\[15\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1368:1368:1368)) + (PORT clk (1353:1353:1353) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -596,12 +590,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~32) + (INSTANCE counter\[16\]\~51) (DELAY (ABSOLUTE - (PORT datab (357:357:357) (404:404:404)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datab cout (385:385:385) (280:280:280)) + (PORT dataa (230:230:230) (306:306:306)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -613,7 +607,7 @@ (INSTANCE counter\[16\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1368:1368:1368)) + (PORT clk (1353:1353:1353) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -624,11 +618,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~34) + (INSTANCE counter\[17\]\~53) (DELAY (ABSOLUTE - (PORT dataa (359:359:359) (404:404:404)) - (IOPATH dataa combout (318:318:318) (327:327:327)) + (PORT dataa (231:231:231) (309:309:309)) + (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) @@ -641,7 +635,7 @@ (INSTANCE counter\[17\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1368:1368:1368)) + (PORT clk (1353:1353:1353) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -652,12 +646,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~36) + (INSTANCE counter\[18\]\~55) (DELAY (ABSOLUTE - (PORT dataa (359:359:359) (404:404:404)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH dataa cout (376:376:376) (275:275:275)) + (PORT datab (229:229:229) (301:301:301)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -669,7 +663,7 @@ (INSTANCE counter\[18\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1368:1368:1368)) + (PORT clk (1353:1353:1353) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -680,12 +674,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~38) + (INSTANCE counter\[19\]\~57) (DELAY (ABSOLUTE - (PORT dataa (361:361:361) (408:408:408)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH dataa cout (376:376:376) (275:275:275)) + (PORT datab (229:229:229) (302:302:302)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -697,7 +691,7 @@ (INSTANCE counter\[19\]) (DELAY (ABSOLUTE - (PORT clk (1352:1352:1352) (1368:1368:1368)) + (PORT clk (1353:1353:1353) (1369:1369:1369)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -706,42 +700,15 @@ (HOLD d (posedge clk) (144:144:144)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~40) - (DELAY - (ABSOLUTE - (PORT datad (199:199:199) (256:256:256)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE Equal0\~5) (DELAY (ABSOLUTE - (PORT dataa (192:192:192) (232:232:232)) - (PORT datab (189:189:189) (225:225:225)) - (PORT datac (164:164:164) (198:198:198)) - (PORT datad (166:166:166) (188:188:188)) - (IOPATH dataa combout (309:309:309) (326:326:326)) - (IOPATH datab combout (309:309:309) (328:328:328)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (184:184:184) (221:221:221)) - (PORT datab (183:183:183) (215:215:215)) - (PORT datac (157:157:157) (188:188:188)) - (PORT datad (160:160:160) (181:181:181)) + (PORT dataa (232:232:232) (310:310:310)) + (PORT datab (228:228:228) (300:300:300)) + (PORT datac (202:202:202) (274:274:274)) + (PORT datad (207:207:207) (269:269:269)) (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -754,10 +721,26 @@ (INSTANCE Equal0\~0) (DELAY (ABSOLUTE - (PORT dataa (319:319:319) (328:328:328)) - (PORT datab (319:319:319) (327:327:327)) - (PORT datac (296:296:296) (304:304:304)) - (PORT datad (297:297:297) (291:291:291)) + (PORT dataa (230:230:230) (306:306:306)) + (PORT datab (227:227:227) (300:300:300)) + (PORT datac (201:201:201) (271:271:271)) + (PORT datad (204:204:204) (265:265:265)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (307:307:307)) + (PORT datab (228:228:228) (301:301:301)) + (PORT datac (354:354:354) (389:389:389)) + (PORT datad (204:204:204) (265:265:265)) (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -770,10 +753,10 @@ (INSTANCE Equal0\~2) (DELAY (ABSOLUTE - (PORT dataa (351:351:351) (356:356:356)) - (PORT datab (587:587:587) (585:585:585)) - (PORT datac (312:312:312) (319:319:319)) - (PORT datad (522:522:522) (503:503:503)) + (PORT dataa (233:233:233) (311:311:311)) + (PORT datab (239:239:239) (308:308:308)) + (PORT datac (205:205:205) (277:277:277)) + (PORT datad (206:206:206) (268:268:268)) (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -786,10 +769,10 @@ (INSTANCE Equal0\~3) (DELAY (ABSOLUTE - (PORT dataa (185:185:185) (223:223:223)) - (PORT datab (184:184:184) (218:218:218)) - (PORT datac (158:158:158) (189:189:189)) - (PORT datad (161:161:161) (182:182:182)) + (PORT dataa (232:232:232) (310:310:310)) + (PORT datab (229:229:229) (303:303:303)) + (PORT datac (202:202:202) (274:274:274)) + (PORT datad (206:206:206) (268:268:268)) (IOPATH dataa combout (309:309:309) (326:326:326)) (IOPATH datab combout (309:309:309) (328:328:328)) (IOPATH datac combout (218:218:218) (215:215:215)) @@ -802,10 +785,10 @@ (INSTANCE Equal0\~4) (DELAY (ABSOLUTE - (PORT dataa (570:570:570) (572:572:572)) - (PORT datab (762:762:762) (749:749:749)) - (PORT datac (155:155:155) (185:185:185)) - (PORT datad (285:285:285) (290:290:290)) + (PORT dataa (314:314:314) (333:333:333)) + (PORT datab (325:325:325) (332:332:332)) + (PORT datac (313:313:313) (319:319:319)) + (PORT datad (544:544:544) (539:539:539)) (IOPATH dataa combout (265:265:265) (269:269:269)) (IOPATH datab combout (265:265:265) (275:275:275)) (IOPATH datac combout (218:218:218) (216:216:216)) @@ -815,14 +798,79 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[0\]\~0) + (INSTANCE counter\[20\]\~59) (DELAY (ABSOLUTE - (PORT dataa (556:556:556) (552:552:552)) - (PORT datab (351:351:351) (360:360:360)) - (PORT datad (171:171:171) (199:199:199)) - (IOPATH dataa combout (287:287:287) (280:280:280)) - (IOPATH datab combout (273:273:273) (275:275:275)) + (PORT datab (241:241:241) (311:311:311)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE counter\[20\]) + (DELAY + (ABSOLUTE + (PORT clk (1681:1681:1681) (1700:1700:1700)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE counter\[21\]\~61) + (DELAY + (ABSOLUTE + (PORT datad (218:218:218) (276:276:276)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE counter\[21\]) + (DELAY + (ABSOLUTE + (PORT clk (1681:1681:1681) (1700:1700:1700)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~7) + (DELAY + (ABSOLUTE + (PORT datac (624:624:624) (648:648:648)) + (PORT datad (603:603:603) (623:623:623)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[0\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (592:592:592) (593:593:593)) + (PORT datab (189:189:189) (224:224:224)) + (PORT datad (306:306:306) (313:313:313)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) @@ -833,7 +881,7 @@ (INSTANCE address\[0\]) (DELAY (ABSOLUTE - (PORT clk (1680:1680:1680) (1698:1698:1698)) + (PORT clk (1652:1652:1652) (1662:1662:1662)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -842,45 +890,33 @@ (HOLD d (posedge clk) (144:144:144)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (318:318:318)) + (PORT datab (237:237:237) (306:306:306)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE Equal0\~6) (DELAY (ABSOLUTE - (PORT datac (164:164:164) (198:198:198)) - (PORT datad (168:168:168) (195:195:195)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal0\~7) - (DELAY - (ABSOLUTE - (PORT dataa (340:340:340) (346:346:346)) - (PORT datab (188:188:188) (224:224:224)) - (PORT datac (156:156:156) (186:186:186)) - (PORT datad (166:166:166) (188:188:188)) - (IOPATH dataa combout (299:299:299) (304:304:304)) - (IOPATH datab combout (300:300:300) (312:312:312)) - (IOPATH datac combout (220:220:220) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (560:560:560) (594:594:594)) - (PORT datab (198:198:198) (236:236:236)) - (PORT datad (307:307:307) (316:316:316)) - (IOPATH dataa combout (287:287:287) (289:289:289)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (PORT dataa (656:656:656) (681:681:681)) + (PORT datab (627:627:627) (652:652:652)) + (PORT datac (564:564:564) (562:562:562)) + (PORT datad (164:164:164) (189:189:189)) + (IOPATH dataa combout (267:267:267) (269:269:269)) + (IOPATH datab combout (267:267:267) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) @@ -890,7 +926,390 @@ (INSTANCE address\[1\]) (DELAY (ABSOLUTE - (PORT clk (1680:1680:1680) (1698:1698:1698)) + (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (721:721:721) (723:723:723)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[2\]\~15) + (DELAY + (ABSOLUTE + (PORT datab (238:238:238) (307:307:307)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (721:721:721) (723:723:723)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[3\]\~17) + (DELAY + (ABSOLUTE + (PORT datab (257:257:257) (326:326:326)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (721:721:721) (723:723:723)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[4\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (241:241:241) (313:313:313)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (721:721:721) (723:723:723)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[5\]\~21) + (DELAY + (ABSOLUTE + (PORT datab (240:240:240) (308:308:308)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (721:721:721) (723:723:723)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[6\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (242:242:242) (315:315:315)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (721:721:721) (723:723:723)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[7\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (242:242:242) (315:315:315)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (721:721:721) (723:723:723)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[8\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (241:241:241) (310:310:310)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (721:721:721) (723:723:723)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[9\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (241:241:241) (310:310:310)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (721:721:721) (723:723:723)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[10\]\~31) + (DELAY + (ABSOLUTE + (PORT datab (241:241:241) (310:310:310)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (721:721:721) (723:723:723)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[11\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (241:241:241) (311:311:311)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (721:721:721) (723:723:723)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[12\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (242:242:242) (314:314:314)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (721:721:721) (723:723:723)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[13\]\~37) + (DELAY + (ABSOLUTE + (PORT datad (235:235:235) (292:292:292)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1352:1352:1352) (1369:1369:1369)) + (PORT d (67:67:67) (78:78:78)) + (PORT ena (721:721:721) (723:723:723)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + (HOLD ena (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (395:395:395) (436:436:436)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE rom\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1352:1352:1352) (1368:1368:1368)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -901,39 +1320,20 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[1\]\~2) + (INSTANCE rom\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (562:562:562) (595:595:595)) - (PORT datab (354:354:354) (363:363:363)) - (PORT datac (531:531:531) (524:524:524)) - (PORT datad (174:174:174) (203:203:203)) - (IOPATH dataa combout (265:265:265) (269:269:269)) - (IOPATH datab combout (265:265:265) (275:275:275)) - (IOPATH datac combout (218:218:218) (215:215:215)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[2\]\~3) - (DELAY - (ABSOLUTE - (PORT datab (369:369:369) (413:413:413)) - (PORT datad (160:160:160) (182:182:182)) - (IOPATH datab combout (295:295:295) (294:294:294)) - (IOPATH datac combout (312:312:312) (325:325:325)) + (PORT datad (201:201:201) (259:259:259)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[2\]) + (INSTANCE rom\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) (DELAY (ABSOLUTE - (PORT clk (1680:1680:1680) (1698:1698:1698)) + (PORT clk (1352:1352:1352) (1368:1368:1368)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -942,14 +1342,121 @@ (HOLD d (posedge clk) (144:144:144)) ) ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1137:1137:1137) (1173:1173:1173)) + (PORT d[1] (1176:1176:1176) (1232:1232:1232)) + (PORT d[2] (1242:1242:1242) (1303:1303:1303)) + (PORT d[3] (1221:1221:1221) (1276:1276:1276)) + (PORT d[4] (1152:1152:1152) (1201:1201:1201)) + (PORT d[5] (1260:1260:1260) (1308:1308:1308)) + (PORT d[6] (1591:1591:1591) (1705:1705:1705)) + (PORT d[7] (1212:1212:1212) (1268:1268:1268)) + (PORT d[8] (1218:1218:1218) (1274:1274:1274)) + (PORT d[9] (1254:1254:1254) (1299:1299:1299)) + (PORT d[10] (1220:1220:1220) (1267:1267:1267)) + (PORT d[11] (1449:1449:1449) (1466:1466:1466)) + (PORT d[12] (1195:1195:1195) (1234:1234:1234)) + (PORT clk (1642:1642:1642) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1642:1642:1642) (1670:1670:1670)) + (PORT d[0] (1070:1070:1070) (1057:1057:1057)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1636:1636:1636)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (883:883:883)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1170:1170:1170) (1206:1206:1206)) - (PORT d[1] (1424:1424:1424) (1458:1458:1458)) - (PORT d[2] (1417:1417:1417) (1451:1451:1451)) + (PORT d[0] (1066:1066:1066) (1108:1108:1108)) + (PORT d[1] (903:903:903) (960:960:960)) + (PORT d[2] (960:960:960) (1018:1018:1018)) + (PORT d[3] (1239:1239:1239) (1281:1281:1281)) + (PORT d[4] (1152:1152:1152) (1192:1192:1192)) + (PORT d[5] (1224:1224:1224) (1264:1264:1264)) + (PORT d[6] (1390:1390:1390) (1523:1523:1523)) + (PORT d[7] (1170:1170:1170) (1209:1209:1209)) + (PORT d[8] (1226:1226:1226) (1271:1271:1271)) + (PORT d[9] (1281:1281:1281) (1333:1333:1333)) + (PORT d[10] (1209:1209:1209) (1251:1251:1251)) + (PORT d[11] (1182:1182:1182) (1215:1215:1215)) + (PORT d[12] (1240:1240:1240) (1281:1281:1281)) (PORT clk (1643:1643:1643) (1671:1671:1671)) ) ) @@ -963,6 +1470,7 @@ (DELAY (ABSOLUTE (PORT clk (1643:1643:1643) (1671:1671:1671)) + (PORT d[0] (859:859:859) (849:849:849)) ) ) ) @@ -1028,4 +1536,1474 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (885:885:885) (944:944:944)) + (PORT datac (813:813:813) (791:791:791)) + (PORT datad (568:568:568) (546:546:546)) + (IOPATH datab combout (308:308:308) (300:300:300)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1358:1358:1358) (1390:1390:1390)) + (PORT d[1] (1429:1429:1429) (1457:1457:1457)) + (PORT d[2] (1457:1457:1457) (1497:1497:1497)) + (PORT d[3] (1164:1164:1164) (1188:1188:1188)) + (PORT d[4] (1495:1495:1495) (1557:1557:1557)) + (PORT d[5] (1763:1763:1763) (1849:1849:1849)) + (PORT d[6] (1169:1169:1169) (1188:1188:1188)) + (PORT d[7] (1246:1246:1246) (1305:1305:1305)) + (PORT d[8] (1752:1752:1752) (1825:1825:1825)) + (PORT d[9] (1142:1142:1142) (1172:1172:1172)) + (PORT d[10] (1313:1313:1313) (1369:1369:1369)) + (PORT d[11] (1131:1131:1131) (1139:1139:1139)) + (PORT d[12] (1168:1168:1168) (1195:1195:1195)) + (PORT clk (1635:1635:1635) (1662:1662:1662)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1662:1662:1662)) + (PORT d[0] (1021:1021:1021) (1044:1044:1044)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1663:1663:1663)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1628:1628:1628)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (875:875:875)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (876:876:876)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (876:876:876)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1395:1395:1395) (1437:1437:1437)) + (PORT d[1] (1255:1255:1255) (1322:1322:1322)) + (PORT d[2] (1479:1479:1479) (1521:1521:1521)) + (PORT d[3] (1244:1244:1244) (1292:1292:1292)) + (PORT d[4] (1222:1222:1222) (1273:1273:1273)) + (PORT d[5] (1476:1476:1476) (1561:1561:1561)) + (PORT d[6] (1179:1179:1179) (1243:1243:1243)) + (PORT d[7] (1164:1164:1164) (1224:1224:1224)) + (PORT d[8] (1495:1495:1495) (1577:1577:1577)) + (PORT d[9] (1230:1230:1230) (1283:1283:1283)) + (PORT d[10] (1677:1677:1677) (1744:1744:1744)) + (PORT d[11] (1203:1203:1203) (1262:1262:1262)) + (PORT d[12] (1455:1455:1455) (1512:1512:1512)) + (PORT clk (1635:1635:1635) (1664:1664:1664)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1664:1664:1664)) + (PORT d[0] (1111:1111:1111) (1127:1127:1127)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1665:1665:1665)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1630:1630:1630)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (587:587:587) (581:581:581)) + (PORT datac (815:815:815) (815:815:815)) + (PORT datad (1247:1247:1247) (1247:1247:1247)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1143:1143:1143) (1193:1193:1193)) + (PORT d[1] (1186:1186:1186) (1252:1252:1252)) + (PORT d[2] (1471:1471:1471) (1533:1533:1533)) + (PORT d[3] (1278:1278:1278) (1335:1335:1335)) + (PORT d[4] (1183:1183:1183) (1244:1244:1244)) + (PORT d[5] (1185:1185:1185) (1237:1237:1237)) + (PORT d[6] (1596:1596:1596) (1726:1726:1726)) + (PORT d[7] (1243:1243:1243) (1300:1300:1300)) + (PORT d[8] (1232:1232:1232) (1284:1284:1284)) + (PORT d[9] (1304:1304:1304) (1372:1372:1372)) + (PORT d[10] (1636:1636:1636) (1650:1650:1650)) + (PORT d[11] (1457:1457:1457) (1491:1491:1491)) + (PORT d[12] (1228:1228:1228) (1274:1274:1274)) + (PORT clk (1641:1641:1641) (1668:1668:1668)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1668:1668:1668)) + (PORT d[0] (1114:1114:1114) (1098:1098:1098)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1642:1642:1642) (1669:1669:1669)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1634:1634:1634)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (881:881:881)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (882:882:882)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (882:882:882)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (882:882:882)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (890:890:890) (939:939:939)) + (PORT d[1] (1164:1164:1164) (1202:1202:1202)) + (PORT d[2] (971:971:971) (1014:1014:1014)) + (PORT d[3] (996:996:996) (1048:1048:1048)) + (PORT d[4] (894:894:894) (953:953:953)) + (PORT d[5] (1145:1145:1145) (1182:1182:1182)) + (PORT d[6] (1364:1364:1364) (1494:1494:1494)) + (PORT d[7] (1170:1170:1170) (1208:1208:1208)) + (PORT d[8] (975:975:975) (1038:1038:1038)) + (PORT d[9] (1019:1019:1019) (1085:1085:1085)) + (PORT d[10] (1404:1404:1404) (1421:1421:1421)) + (PORT d[11] (1181:1181:1181) (1214:1214:1214)) + (PORT d[12] (1214:1214:1214) (1252:1252:1252)) + (PORT clk (1643:1643:1643) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1672:1672:1672)) + (PORT d[0] (848:848:848) (858:858:858)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1638:1638:1638)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (885:885:885)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (886:886:886)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (886:886:886)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT datab (905:905:905) (961:961:961)) + (PORT datac (835:835:835) (824:824:824)) + (PORT datad (554:554:554) (539:539:539)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (864:864:864) (888:888:888)) + (PORT d[1] (904:904:904) (943:943:943)) + (PORT d[2] (999:999:999) (1044:1044:1044)) + (PORT d[3] (981:981:981) (1012:1012:1012)) + (PORT d[4] (883:883:883) (924:924:924)) + (PORT d[5] (931:931:931) (967:967:967)) + (PORT d[6] (1325:1325:1325) (1435:1435:1435)) + (PORT d[7] (1147:1147:1147) (1173:1173:1173)) + (PORT d[8] (1501:1501:1501) (1549:1549:1549)) + (PORT d[9] (1001:1001:1001) (1049:1049:1049)) + (PORT d[10] (963:963:963) (1003:1003:1003)) + (PORT d[11] (1202:1202:1202) (1209:1209:1209)) + (PORT d[12] (1200:1200:1200) (1222:1222:1222)) + (PORT clk (1643:1643:1643) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1670:1670:1670)) + (PORT d[0] (832:832:832) (824:824:824)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1636:1636:1636)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (883:883:883)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (884:884:884)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1113:1113:1113) (1125:1125:1125)) + (PORT d[1] (606:606:606) (637:637:637)) + (PORT d[2] (665:665:665) (695:695:695)) + (PORT d[3] (709:709:709) (741:741:741)) + (PORT d[4] (612:612:612) (647:647:647)) + (PORT d[5] (683:683:683) (724:724:724)) + (PORT d[6] (708:708:708) (738:738:738)) + (PORT d[7] (688:688:688) (727:727:727)) + (PORT d[8] (700:700:700) (736:736:736)) + (PORT d[9] (712:712:712) (753:753:753)) + (PORT d[10] (1139:1139:1139) (1140:1140:1140)) + (PORT d[11] (689:689:689) (724:724:724)) + (PORT d[12] (698:698:698) (736:736:736)) + (PORT clk (1643:1643:1643) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1670:1670:1670)) + (PORT d[0] (568:568:568) (578:578:578)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1636:1636:1636)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (883:883:883)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (884:884:884)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (852:852:852) (853:853:853)) + (PORT datac (604:604:604) (635:635:635)) + (PORT datad (566:566:566) (544:544:544)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1371:1371:1371) (1392:1392:1392)) + (PORT d[1] (1421:1421:1421) (1436:1436:1436)) + (PORT d[2] (1449:1449:1449) (1476:1476:1476)) + (PORT d[3] (924:924:924) (961:961:961)) + (PORT d[4] (913:913:913) (957:957:957)) + (PORT d[5] (1485:1485:1485) (1575:1575:1575)) + (PORT d[6] (929:929:929) (974:974:974)) + (PORT d[7] (882:882:882) (925:925:925)) + (PORT d[8] (1483:1483:1483) (1569:1569:1569)) + (PORT d[9] (928:928:928) (958:958:958)) + (PORT d[10] (913:913:913) (949:949:949)) + (PORT d[11] (894:894:894) (932:932:932)) + (PORT d[12] (911:911:911) (944:944:944)) + (PORT clk (1635:1635:1635) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1663:1663:1663)) + (PORT d[0] (793:793:793) (817:817:817)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1664:1664:1664)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1629:1629:1629)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1140:1140:1140) (1174:1174:1174)) + (PORT d[1] (1169:1169:1169) (1198:1198:1198)) + (PORT d[2] (1194:1194:1194) (1234:1234:1234)) + (PORT d[3] (1189:1189:1189) (1216:1216:1216)) + (PORT d[4] (1491:1491:1491) (1548:1548:1548)) + (PORT d[5] (1484:1484:1484) (1574:1574:1574)) + (PORT d[6] (1190:1190:1190) (1239:1239:1239)) + (PORT d[7] (1154:1154:1154) (1198:1198:1198)) + (PORT d[8] (1482:1482:1482) (1568:1568:1568)) + (PORT d[9] (1174:1174:1174) (1206:1206:1206)) + (PORT d[10] (1702:1702:1702) (1770:1770:1770)) + (PORT d[11] (1193:1193:1193) (1235:1235:1235)) + (PORT d[12] (1156:1156:1156) (1189:1189:1189)) + (PORT clk (1635:1635:1635) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1663:1663:1663)) + (PORT d[0] (1064:1064:1064) (1056:1056:1056)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1664:1664:1664)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1629:1629:1629)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~4) + (DELAY + (ABSOLUTE + (PORT datab (597:597:597) (583:583:583)) + (PORT datac (797:797:797) (769:769:769)) + (PORT datad (747:747:747) (756:756:756)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1404:1404:1404) (1451:1451:1451)) + (PORT d[1] (1754:1754:1754) (1846:1846:1846)) + (PORT d[2] (1170:1170:1170) (1226:1226:1226)) + (PORT d[3] (1230:1230:1230) (1270:1270:1270)) + (PORT d[4] (1206:1206:1206) (1267:1267:1267)) + (PORT d[5] (1157:1157:1157) (1221:1221:1221)) + (PORT d[6] (1207:1207:1207) (1273:1273:1273)) + (PORT d[7] (1170:1170:1170) (1232:1232:1232)) + (PORT d[8] (1488:1488:1488) (1556:1556:1556)) + (PORT d[9] (1215:1215:1215) (1269:1269:1269)) + (PORT d[10] (1722:1722:1722) (1787:1787:1787)) + (PORT d[11] (1184:1184:1184) (1241:1241:1241)) + (PORT d[12] (1422:1422:1422) (1464:1464:1464)) + (PORT clk (1635:1635:1635) (1664:1664:1664)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1664:1664:1664)) + (PORT d[0] (1100:1100:1100) (1091:1091:1091)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1665:1665:1665)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1630:1630:1630)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1448:1448:1448) (1498:1498:1498)) + (PORT d[1] (1506:1506:1506) (1592:1592:1592)) + (PORT d[2] (1452:1452:1452) (1509:1509:1509)) + (PORT d[3] (1528:1528:1528) (1576:1576:1576)) + (PORT d[4] (1475:1475:1475) (1541:1541:1541)) + (PORT d[5] (1462:1462:1462) (1522:1522:1522)) + (PORT d[6] (1454:1454:1454) (1503:1503:1503)) + (PORT d[7] (1420:1420:1420) (1469:1469:1469)) + (PORT d[8] (1442:1442:1442) (1487:1487:1487)) + (PORT d[9] (1473:1473:1473) (1520:1520:1520)) + (PORT d[10] (1421:1421:1421) (1470:1470:1470)) + (PORT d[11] (1448:1448:1448) (1508:1508:1508)) + (PORT d[12] (1420:1420:1420) (1464:1464:1464)) + (PORT clk (1634:1634:1634) (1663:1663:1663)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1634:1634:1634) (1663:1663:1663)) + (PORT d[0] (1331:1331:1331) (1332:1332:1332)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1664:1664:1664)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1601:1601:1601) (1629:1629:1629)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (584:584:584) (569:569:569)) + (PORT datac (839:839:839) (835:835:835)) + (PORT datad (1050:1050:1050) (1093:1093:1093)) + (IOPATH datab combout (275:275:275) (275:275:275)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (891:891:891) (939:939:939)) + (PORT d[1] (1151:1151:1151) (1192:1192:1192)) + (PORT d[2] (982:982:982) (1034:1034:1034)) + (PORT d[3] (1008:1008:1008) (1057:1057:1057)) + (PORT d[4] (914:914:914) (974:974:974)) + (PORT d[5] (988:988:988) (1039:1039:1039)) + (PORT d[6] (1336:1336:1336) (1464:1464:1464)) + (PORT d[7] (1184:1184:1184) (1228:1228:1228)) + (PORT d[8] (977:977:977) (1032:1032:1032)) + (PORT d[9] (982:982:982) (1046:1046:1046)) + (PORT d[10] (949:949:949) (1003:1003:1003)) + (PORT d[11] (1165:1165:1165) (1197:1197:1197)) + (PORT d[12] (1210:1210:1210) (1246:1246:1246)) + (PORT clk (1643:1643:1643) (1672:1672:1672)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1672:1672:1672)) + (PORT d[0] (842:842:842) (851:851:851)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1673:1673:1673)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1638:1638:1638)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (885:885:885)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (886:886:886)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (886:886:886)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (886:886:886)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (853:853:853) (884:884:884)) + (PORT d[1] (606:606:606) (638:638:638)) + (PORT d[2] (1214:1214:1214) (1272:1272:1272)) + (PORT d[3] (1231:1231:1231) (1305:1305:1305)) + (PORT d[4] (860:860:860) (887:887:887)) + (PORT d[5] (973:973:973) (1005:1005:1005)) + (PORT d[6] (1300:1300:1300) (1396:1396:1396)) + (PORT d[7] (1150:1150:1150) (1164:1164:1164)) + (PORT d[8] (1515:1515:1515) (1564:1564:1564)) + (PORT d[9] (972:972:972) (1000:1000:1000)) + (PORT d[10] (968:968:968) (992:992:992)) + (PORT d[11] (1116:1116:1116) (1120:1120:1120)) + (PORT d[12] (1163:1163:1163) (1171:1171:1171)) + (PORT clk (1643:1643:1643) (1670:1670:1670)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1670:1670:1670)) + (PORT d[0] (798:798:798) (816:816:816)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1671:1671:1671)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1636:1636:1636)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (883:883:883)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (884:884:884)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (884:884:884)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (649:649:649) (659:659:659)) + (PORT datac (837:837:837) (850:850:850)) + (PORT datad (328:328:328) (320:320:320)) + (IOPATH dataa combout (307:307:307) (306:306:306)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1373:1373:1373) (1418:1418:1418)) + (PORT d[1] (1747:1747:1747) (1825:1825:1825)) + (PORT d[2] (1746:1746:1746) (1807:1807:1807)) + (PORT d[3] (1277:1277:1277) (1330:1330:1330)) + (PORT d[4] (1743:1743:1743) (1797:1797:1797)) + (PORT d[5] (1224:1224:1224) (1295:1295:1295)) + (PORT d[6] (1233:1233:1233) (1302:1302:1302)) + (PORT d[7] (1171:1171:1171) (1233:1233:1233)) + (PORT d[8] (1217:1217:1217) (1283:1283:1283)) + (PORT d[9] (1191:1191:1191) (1242:1242:1242)) + (PORT d[10] (1667:1667:1667) (1716:1716:1716)) + (PORT d[11] (1184:1184:1184) (1242:1242:1242)) + (PORT d[12] (1175:1175:1175) (1226:1226:1226)) + (PORT clk (1635:1635:1635) (1664:1664:1664)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1635:1635:1635) (1664:1664:1664)) + (PORT d[0] (1135:1135:1135) (1114:1114:1114)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1636:1636:1636) (1665:1665:1665)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1602:1602:1602) (1630:1630:1630)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1688:1688:1688) (1727:1727:1727)) + (PORT d[1] (1489:1489:1489) (1529:1529:1529)) + (PORT d[2] (1466:1466:1466) (1541:1541:1541)) + (PORT d[3] (1503:1503:1503) (1555:1555:1555)) + (PORT d[4] (1477:1477:1477) (1556:1556:1556)) + (PORT d[5] (1450:1450:1450) (1516:1516:1516)) + (PORT d[6] (1438:1438:1438) (1502:1502:1502)) + (PORT d[7] (1428:1428:1428) (1489:1489:1489)) + (PORT d[8] (1421:1421:1421) (1476:1476:1476)) + (PORT d[9] (1475:1475:1475) (1533:1533:1533)) + (PORT d[10] (1392:1392:1392) (1448:1448:1448)) + (PORT d[11] (1450:1450:1450) (1514:1514:1514)) + (PORT d[12] (1424:1424:1424) (1479:1479:1479)) + (PORT clk (1633:1633:1633) (1660:1660:1660)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (169:169:169)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1633:1633:1633) (1660:1660:1660)) + (PORT d[0] (1376:1376:1376) (1394:1394:1394)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1634:1634:1634) (1661:1661:1661)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1600:1600:1600) (1626:1626:1626)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (873:873:873)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (874:874:874)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (874:874:874)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (874:874:874)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT datab (593:593:593) (577:577:577)) + (PORT datac (833:833:833) (822:822:822)) + (PORT datad (1052:1052:1052) (1094:1094:1094)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) ) diff --git a/simulation/modelsim/spectrum_6_1200mv_85c_slow.vo b/simulation/modelsim/spectrum_6_1200mv_85c_slow.vo index 8896dc4..1499b6d 100644 --- a/simulation/modelsim/spectrum_6_1200mv_85c_slow.vo +++ b/simulation/modelsim/spectrum_6_1200mv_85c_slow.vo @@ -16,7 +16,7 @@ // PROGRAM "Quartus II 32-bit" // VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" -// DATE "03/30/2022 12:38:42" +// DATE "03/30/2022 13:12:28" // // Device: Altera EP4CE22F17C6 Package FBGA256 @@ -71,77 +71,166 @@ wire \LED[6]~output_o ; wire \LED[7]~output_o ; wire \CLOCK_50~input_o ; wire \CLOCK_50~inputclkctrl_outclk ; -wire \Add0~0_combout ; -wire \Add0~1 ; -wire \Add0~2_combout ; -wire \Add0~3 ; -wire \Add0~4_combout ; -wire \Add0~5 ; -wire \Add0~6_combout ; -wire \Add0~7 ; -wire \Add0~8_combout ; -wire \Add0~9 ; -wire \Add0~10_combout ; -wire \Add0~11 ; -wire \Add0~12_combout ; -wire \Add0~13 ; -wire \Add0~14_combout ; -wire \Add0~15 ; -wire \Add0~16_combout ; -wire \Add0~17 ; -wire \Add0~18_combout ; -wire \Add0~19 ; -wire \Add0~20_combout ; -wire \Add0~21 ; -wire \Add0~22_combout ; -wire \Add0~23 ; -wire \Add0~24_combout ; -wire \Add0~25 ; -wire \Add0~26_combout ; -wire \Add0~27 ; -wire \Add0~28_combout ; -wire \Add0~29 ; -wire \Add0~30_combout ; -wire \Add0~31 ; -wire \Add0~32_combout ; -wire \Add0~33 ; -wire \Add0~34_combout ; -wire \Add0~35 ; -wire \Add0~36_combout ; -wire \Add0~37 ; -wire \Add0~38_combout ; -wire \Add0~39 ; -wire \Add0~40_combout ; +wire \counter[0]~63_combout ; +wire \counter[1]~21_combout ; +wire \counter[1]~22 ; +wire \counter[2]~23_combout ; +wire \counter[2]~24 ; +wire \counter[3]~25_combout ; +wire \counter[3]~26 ; +wire \counter[4]~27_combout ; +wire \counter[4]~28 ; +wire \counter[5]~29_combout ; +wire \counter[5]~30 ; +wire \counter[6]~31_combout ; +wire \counter[6]~32 ; +wire \counter[7]~33_combout ; +wire \counter[7]~34 ; +wire \counter[8]~35_combout ; +wire \counter[8]~36 ; +wire \counter[9]~37_combout ; +wire \counter[9]~38 ; +wire \counter[10]~39_combout ; +wire \counter[10]~40 ; +wire \counter[11]~41_combout ; +wire \counter[11]~feeder_combout ; +wire \counter[11]~42 ; +wire \counter[12]~43_combout ; +wire \counter[12]~44 ; +wire \counter[13]~45_combout ; +wire \counter[13]~46 ; +wire \counter[14]~47_combout ; +wire \counter[14]~48 ; +wire \counter[15]~49_combout ; +wire \counter[15]~50 ; +wire \counter[16]~51_combout ; +wire \counter[16]~52 ; +wire \counter[17]~53_combout ; +wire \counter[17]~54 ; +wire \counter[18]~55_combout ; +wire \counter[18]~56 ; +wire \counter[19]~57_combout ; wire \Equal0~5_combout ; -wire \Equal0~1_combout ; wire \Equal0~0_combout ; +wire \Equal0~1_combout ; wire \Equal0~2_combout ; wire \Equal0~3_combout ; wire \Equal0~4_combout ; -wire \address[0]~0_combout ; -wire \Equal0~6_combout ; +wire \counter[19]~58 ; +wire \counter[20]~59_combout ; +wire \counter[20]~60 ; +wire \counter[21]~61_combout ; wire \Equal0~7_combout ; -wire \address[1]~1_combout ; -wire \address[1]~2_combout ; -wire \address[2]~3_combout ; -wire [20:0] counter; -wire [2:0] address; -wire [7:0] \rom|altsyncram_component|auto_generated|q_a ; +wire \address[0]~39_combout ; +wire \address[1]~13_combout ; +wire \Equal0~6_combout ; +wire \address[1]~14 ; +wire \address[2]~15_combout ; +wire \address[2]~16 ; +wire \address[3]~17_combout ; +wire \address[3]~18 ; +wire \address[4]~19_combout ; +wire \address[4]~20 ; +wire \address[5]~21_combout ; +wire \address[5]~22 ; +wire \address[6]~23_combout ; +wire \address[6]~24 ; +wire \address[7]~25_combout ; +wire \address[7]~26 ; +wire \address[8]~27_combout ; +wire \address[8]~28 ; +wire \address[9]~29_combout ; +wire \address[9]~30 ; +wire \address[10]~31_combout ; +wire \address[10]~32 ; +wire \address[11]~33_combout ; +wire \address[11]~34 ; +wire \address[12]~35_combout ; +wire \address[12]~36 ; +wire \address[13]~37_combout ; +wire \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; +wire \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ; +wire [21:0] counter; +wire [13:0] address; +wire [0:0] \rom|altsyncram_component|auto_generated|out_address_reg_a ; +wire [0:0] \rom|altsyncram_component|auto_generated|address_reg_a ; -wire [17:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; -assign \rom|altsyncram_component|auto_generated|q_a [0] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|q_a [1] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [1]; -assign \rom|altsyncram_component|auto_generated|q_a [2] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [2]; -assign \rom|altsyncram_component|auto_generated|q_a [3] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [3]; -assign \rom|altsyncram_component|auto_generated|q_a [4] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [4]; -assign \rom|altsyncram_component|auto_generated|q_a [5] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [5]; -assign \rom|altsyncram_component|auto_generated|q_a [6] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [6]; -assign \rom|altsyncram_component|auto_generated|q_a [7] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [7]; +assign \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; // Location: IOOBUF_X38_Y34_N16 cycloneive_io_obuf \LED[0]~output ( - .i(\rom|altsyncram_component|auto_generated|q_a [0]), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -154,7 +243,7 @@ defparam \LED[0]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y34_N2 cycloneive_io_obuf \LED[1]~output ( - .i(\rom|altsyncram_component|auto_generated|q_a [1]), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -167,7 +256,7 @@ defparam \LED[1]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y34_N9 cycloneive_io_obuf \LED[2]~output ( - .i(\rom|altsyncram_component|auto_generated|q_a [2]), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -180,7 +269,7 @@ defparam \LED[2]~output .open_drain_output = "false"; // Location: IOOBUF_X40_Y34_N2 cycloneive_io_obuf \LED[3]~output ( - .i(\rom|altsyncram_component|auto_generated|q_a [3]), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -193,7 +282,7 @@ defparam \LED[3]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y25_N9 cycloneive_io_obuf \LED[4]~output ( - .i(\rom|altsyncram_component|auto_generated|q_a [4]), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -206,7 +295,7 @@ defparam \LED[4]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y26_N16 cycloneive_io_obuf \LED[5]~output ( - .i(\rom|altsyncram_component|auto_generated|q_a [5]), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -219,7 +308,7 @@ defparam \LED[5]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y28_N9 cycloneive_io_obuf \LED[6]~output ( - .i(\rom|altsyncram_component|auto_generated|q_a [6]), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -232,7 +321,7 @@ defparam \LED[6]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y10_N23 cycloneive_io_obuf \LED[7]~output ( - .i(\rom|altsyncram_component|auto_generated|q_a [7]), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -266,47 +355,27 @@ defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: FF_X31_Y17_N21 -dffeas \counter[20] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~40_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[20]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[20] .is_wysiwyg = "true"; -defparam \counter[20] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N12 -cycloneive_lcell_comb \Add0~0 ( +// Location: LCCOMB_X28_Y18_N2 +cycloneive_lcell_comb \counter[0]~63 ( // Equation(s): -// \Add0~0_combout = counter[0] $ (VCC) -// \Add0~1 = CARRY(counter[0]) +// \counter[0]~63_combout = !counter[0] - .dataa(counter[0]), + .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(vcc), + .datac(counter[0]), + .datad(gnd), .cin(gnd), - .combout(\Add0~0_combout ), - .cout(\Add0~1 )); + .combout(\counter[0]~63_combout ), + .cout()); // synopsys translate_off -defparam \Add0~0 .lut_mask = 16'h55AA; -defparam \Add0~0 .sum_lutc_input = "datac"; +defparam \counter[0]~63 .lut_mask = 16'h0F0F; +defparam \counter[0]~63 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y18_N13 +// Location: FF_X28_Y18_N3 dffeas \counter[0] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~0_combout ), + .d(\counter[0]~63_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -322,28 +391,28 @@ defparam \counter[0] .is_wysiwyg = "true"; defparam \counter[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y18_N14 -cycloneive_lcell_comb \Add0~2 ( +// Location: LCCOMB_X28_Y18_N12 +cycloneive_lcell_comb \counter[1]~21 ( // Equation(s): -// \Add0~2_combout = (counter[1] & (!\Add0~1 )) # (!counter[1] & ((\Add0~1 ) # (GND))) -// \Add0~3 = CARRY((!\Add0~1 ) # (!counter[1])) +// \counter[1]~21_combout = (counter[1] & (counter[0] $ (VCC))) # (!counter[1] & (counter[0] & VCC)) +// \counter[1]~22 = CARRY((counter[1] & counter[0])) - .dataa(gnd), - .datab(counter[1]), + .dataa(counter[1]), + .datab(counter[0]), .datac(gnd), .datad(vcc), - .cin(\Add0~1 ), - .combout(\Add0~2_combout ), - .cout(\Add0~3 )); + .cin(gnd), + .combout(\counter[1]~21_combout ), + .cout(\counter[1]~22 )); // synopsys translate_off -defparam \Add0~2 .lut_mask = 16'h3C3F; -defparam \Add0~2 .sum_lutc_input = "cin"; +defparam \counter[1]~21 .lut_mask = 16'h6688; +defparam \counter[1]~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y18_N15 +// Location: FF_X28_Y18_N13 dffeas \counter[1] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~2_combout ), + .d(\counter[1]~21_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -359,28 +428,28 @@ defparam \counter[1] .is_wysiwyg = "true"; defparam \counter[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y18_N16 -cycloneive_lcell_comb \Add0~4 ( +// Location: LCCOMB_X28_Y18_N14 +cycloneive_lcell_comb \counter[2]~23 ( // Equation(s): -// \Add0~4_combout = (counter[2] & (\Add0~3 $ (GND))) # (!counter[2] & (!\Add0~3 & VCC)) -// \Add0~5 = CARRY((counter[2] & !\Add0~3 )) +// \counter[2]~23_combout = (counter[2] & (!\counter[1]~22 )) # (!counter[2] & ((\counter[1]~22 ) # (GND))) +// \counter[2]~24 = CARRY((!\counter[1]~22 ) # (!counter[2])) .dataa(gnd), .datab(counter[2]), .datac(gnd), .datad(vcc), - .cin(\Add0~3 ), - .combout(\Add0~4_combout ), - .cout(\Add0~5 )); + .cin(\counter[1]~22 ), + .combout(\counter[2]~23_combout ), + .cout(\counter[2]~24 )); // synopsys translate_off -defparam \Add0~4 .lut_mask = 16'hC30C; -defparam \Add0~4 .sum_lutc_input = "cin"; +defparam \counter[2]~23 .lut_mask = 16'h3C3F; +defparam \counter[2]~23 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y18_N17 +// Location: FF_X28_Y18_N15 dffeas \counter[2] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~4_combout ), + .d(\counter[2]~23_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -396,28 +465,28 @@ defparam \counter[2] .is_wysiwyg = "true"; defparam \counter[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y18_N18 -cycloneive_lcell_comb \Add0~6 ( +// Location: LCCOMB_X28_Y18_N16 +cycloneive_lcell_comb \counter[3]~25 ( // Equation(s): -// \Add0~6_combout = (counter[3] & (!\Add0~5 )) # (!counter[3] & ((\Add0~5 ) # (GND))) -// \Add0~7 = CARRY((!\Add0~5 ) # (!counter[3])) +// \counter[3]~25_combout = (counter[3] & (\counter[2]~24 $ (GND))) # (!counter[3] & (!\counter[2]~24 & VCC)) +// \counter[3]~26 = CARRY((counter[3] & !\counter[2]~24 )) .dataa(gnd), .datab(counter[3]), .datac(gnd), .datad(vcc), - .cin(\Add0~5 ), - .combout(\Add0~6_combout ), - .cout(\Add0~7 )); + .cin(\counter[2]~24 ), + .combout(\counter[3]~25_combout ), + .cout(\counter[3]~26 )); // synopsys translate_off -defparam \Add0~6 .lut_mask = 16'h3C3F; -defparam \Add0~6 .sum_lutc_input = "cin"; +defparam \counter[3]~25 .lut_mask = 16'hC30C; +defparam \counter[3]~25 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y18_N19 +// Location: FF_X28_Y18_N17 dffeas \counter[3] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~6_combout ), + .d(\counter[3]~25_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -433,28 +502,28 @@ defparam \counter[3] .is_wysiwyg = "true"; defparam \counter[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y18_N20 -cycloneive_lcell_comb \Add0~8 ( +// Location: LCCOMB_X28_Y18_N18 +cycloneive_lcell_comb \counter[4]~27 ( // Equation(s): -// \Add0~8_combout = (counter[4] & (\Add0~7 $ (GND))) # (!counter[4] & (!\Add0~7 & VCC)) -// \Add0~9 = CARRY((counter[4] & !\Add0~7 )) +// \counter[4]~27_combout = (counter[4] & (!\counter[3]~26 )) # (!counter[4] & ((\counter[3]~26 ) # (GND))) +// \counter[4]~28 = CARRY((!\counter[3]~26 ) # (!counter[4])) - .dataa(counter[4]), - .datab(gnd), + .dataa(gnd), + .datab(counter[4]), .datac(gnd), .datad(vcc), - .cin(\Add0~7 ), - .combout(\Add0~8_combout ), - .cout(\Add0~9 )); + .cin(\counter[3]~26 ), + .combout(\counter[4]~27_combout ), + .cout(\counter[4]~28 )); // synopsys translate_off -defparam \Add0~8 .lut_mask = 16'hA50A; -defparam \Add0~8 .sum_lutc_input = "cin"; +defparam \counter[4]~27 .lut_mask = 16'h3C3F; +defparam \counter[4]~27 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y18_N21 +// Location: FF_X28_Y18_N19 dffeas \counter[4] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~8_combout ), + .d(\counter[4]~27_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -470,28 +539,28 @@ defparam \counter[4] .is_wysiwyg = "true"; defparam \counter[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y18_N22 -cycloneive_lcell_comb \Add0~10 ( +// Location: LCCOMB_X28_Y18_N20 +cycloneive_lcell_comb \counter[5]~29 ( // Equation(s): -// \Add0~10_combout = (counter[5] & (!\Add0~9 )) # (!counter[5] & ((\Add0~9 ) # (GND))) -// \Add0~11 = CARRY((!\Add0~9 ) # (!counter[5])) +// \counter[5]~29_combout = (counter[5] & (\counter[4]~28 $ (GND))) # (!counter[5] & (!\counter[4]~28 & VCC)) +// \counter[5]~30 = CARRY((counter[5] & !\counter[4]~28 )) .dataa(gnd), .datab(counter[5]), .datac(gnd), .datad(vcc), - .cin(\Add0~9 ), - .combout(\Add0~10_combout ), - .cout(\Add0~11 )); + .cin(\counter[4]~28 ), + .combout(\counter[5]~29_combout ), + .cout(\counter[5]~30 )); // synopsys translate_off -defparam \Add0~10 .lut_mask = 16'h3C3F; -defparam \Add0~10 .sum_lutc_input = "cin"; +defparam \counter[5]~29 .lut_mask = 16'hC30C; +defparam \counter[5]~29 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y18_N23 +// Location: FF_X28_Y18_N21 dffeas \counter[5] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~10_combout ), + .d(\counter[5]~29_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -507,28 +576,28 @@ defparam \counter[5] .is_wysiwyg = "true"; defparam \counter[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y18_N24 -cycloneive_lcell_comb \Add0~12 ( +// Location: LCCOMB_X28_Y18_N22 +cycloneive_lcell_comb \counter[6]~31 ( // Equation(s): -// \Add0~12_combout = (counter[6] & (\Add0~11 $ (GND))) # (!counter[6] & (!\Add0~11 & VCC)) -// \Add0~13 = CARRY((counter[6] & !\Add0~11 )) +// \counter[6]~31_combout = (counter[6] & (!\counter[5]~30 )) # (!counter[6] & ((\counter[5]~30 ) # (GND))) +// \counter[6]~32 = CARRY((!\counter[5]~30 ) # (!counter[6])) .dataa(counter[6]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\Add0~11 ), - .combout(\Add0~12_combout ), - .cout(\Add0~13 )); + .cin(\counter[5]~30 ), + .combout(\counter[6]~31_combout ), + .cout(\counter[6]~32 )); // synopsys translate_off -defparam \Add0~12 .lut_mask = 16'hA50A; -defparam \Add0~12 .sum_lutc_input = "cin"; +defparam \counter[6]~31 .lut_mask = 16'h5A5F; +defparam \counter[6]~31 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y18_N25 +// Location: FF_X28_Y18_N23 dffeas \counter[6] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~12_combout ), + .d(\counter[6]~31_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -544,28 +613,28 @@ defparam \counter[6] .is_wysiwyg = "true"; defparam \counter[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y18_N26 -cycloneive_lcell_comb \Add0~14 ( +// Location: LCCOMB_X28_Y18_N24 +cycloneive_lcell_comb \counter[7]~33 ( // Equation(s): -// \Add0~14_combout = (counter[7] & (!\Add0~13 )) # (!counter[7] & ((\Add0~13 ) # (GND))) -// \Add0~15 = CARRY((!\Add0~13 ) # (!counter[7])) +// \counter[7]~33_combout = (counter[7] & (\counter[6]~32 $ (GND))) # (!counter[7] & (!\counter[6]~32 & VCC)) +// \counter[7]~34 = CARRY((counter[7] & !\counter[6]~32 )) .dataa(gnd), .datab(counter[7]), .datac(gnd), .datad(vcc), - .cin(\Add0~13 ), - .combout(\Add0~14_combout ), - .cout(\Add0~15 )); + .cin(\counter[6]~32 ), + .combout(\counter[7]~33_combout ), + .cout(\counter[7]~34 )); // synopsys translate_off -defparam \Add0~14 .lut_mask = 16'h3C3F; -defparam \Add0~14 .sum_lutc_input = "cin"; +defparam \counter[7]~33 .lut_mask = 16'hC30C; +defparam \counter[7]~33 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y18_N27 +// Location: FF_X28_Y18_N25 dffeas \counter[7] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~14_combout ), + .d(\counter[7]~33_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -581,28 +650,28 @@ defparam \counter[7] .is_wysiwyg = "true"; defparam \counter[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y18_N28 -cycloneive_lcell_comb \Add0~16 ( +// Location: LCCOMB_X28_Y18_N26 +cycloneive_lcell_comb \counter[8]~35 ( // Equation(s): -// \Add0~16_combout = (counter[8] & (\Add0~15 $ (GND))) # (!counter[8] & (!\Add0~15 & VCC)) -// \Add0~17 = CARRY((counter[8] & !\Add0~15 )) +// \counter[8]~35_combout = (counter[8] & (!\counter[7]~34 )) # (!counter[8] & ((\counter[7]~34 ) # (GND))) +// \counter[8]~36 = CARRY((!\counter[7]~34 ) # (!counter[8])) - .dataa(gnd), - .datab(counter[8]), + .dataa(counter[8]), + .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\Add0~15 ), - .combout(\Add0~16_combout ), - .cout(\Add0~17 )); + .cin(\counter[7]~34 ), + .combout(\counter[8]~35_combout ), + .cout(\counter[8]~36 )); // synopsys translate_off -defparam \Add0~16 .lut_mask = 16'hC30C; -defparam \Add0~16 .sum_lutc_input = "cin"; +defparam \counter[8]~35 .lut_mask = 16'h5A5F; +defparam \counter[8]~35 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y18_N29 +// Location: FF_X28_Y18_N27 dffeas \counter[8] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~16_combout ), + .d(\counter[8]~35_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -618,28 +687,28 @@ defparam \counter[8] .is_wysiwyg = "true"; defparam \counter[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y18_N30 -cycloneive_lcell_comb \Add0~18 ( +// Location: LCCOMB_X28_Y18_N28 +cycloneive_lcell_comb \counter[9]~37 ( // Equation(s): -// \Add0~18_combout = (counter[9] & (!\Add0~17 )) # (!counter[9] & ((\Add0~17 ) # (GND))) -// \Add0~19 = CARRY((!\Add0~17 ) # (!counter[9])) +// \counter[9]~37_combout = (counter[9] & (\counter[8]~36 $ (GND))) # (!counter[9] & (!\counter[8]~36 & VCC)) +// \counter[9]~38 = CARRY((counter[9] & !\counter[8]~36 )) - .dataa(counter[9]), - .datab(gnd), + .dataa(gnd), + .datab(counter[9]), .datac(gnd), .datad(vcc), - .cin(\Add0~17 ), - .combout(\Add0~18_combout ), - .cout(\Add0~19 )); + .cin(\counter[8]~36 ), + .combout(\counter[9]~37_combout ), + .cout(\counter[9]~38 )); // synopsys translate_off -defparam \Add0~18 .lut_mask = 16'h5A5F; -defparam \Add0~18 .sum_lutc_input = "cin"; +defparam \counter[9]~37 .lut_mask = 16'hC30C; +defparam \counter[9]~37 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y18_N31 +// Location: FF_X28_Y18_N29 dffeas \counter[9] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~18_combout ), + .d(\counter[9]~37_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -655,28 +724,28 @@ defparam \counter[9] .is_wysiwyg = "true"; defparam \counter[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N0 -cycloneive_lcell_comb \Add0~20 ( +// Location: LCCOMB_X28_Y18_N30 +cycloneive_lcell_comb \counter[10]~39 ( // Equation(s): -// \Add0~20_combout = (counter[10] & (\Add0~19 $ (GND))) # (!counter[10] & (!\Add0~19 & VCC)) -// \Add0~21 = CARRY((counter[10] & !\Add0~19 )) +// \counter[10]~39_combout = (counter[10] & (!\counter[9]~38 )) # (!counter[10] & ((\counter[9]~38 ) # (GND))) +// \counter[10]~40 = CARRY((!\counter[9]~38 ) # (!counter[10])) - .dataa(gnd), - .datab(counter[10]), + .dataa(counter[10]), + .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\Add0~19 ), - .combout(\Add0~20_combout ), - .cout(\Add0~21 )); + .cin(\counter[9]~38 ), + .combout(\counter[10]~39_combout ), + .cout(\counter[10]~40 )); // synopsys translate_off -defparam \Add0~20 .lut_mask = 16'hC30C; -defparam \Add0~20 .sum_lutc_input = "cin"; +defparam \counter[10]~39 .lut_mask = 16'h5A5F; +defparam \counter[10]~39 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y17_N1 +// Location: FF_X28_Y18_N31 dffeas \counter[10] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~20_combout ), + .d(\counter[10]~39_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -692,28 +761,45 @@ defparam \counter[10] .is_wysiwyg = "true"; defparam \counter[10] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N2 -cycloneive_lcell_comb \Add0~22 ( +// Location: LCCOMB_X28_Y17_N0 +cycloneive_lcell_comb \counter[11]~41 ( // Equation(s): -// \Add0~22_combout = (counter[11] & (!\Add0~21 )) # (!counter[11] & ((\Add0~21 ) # (GND))) -// \Add0~23 = CARRY((!\Add0~21 ) # (!counter[11])) +// \counter[11]~41_combout = (counter[11] & (\counter[10]~40 $ (GND))) # (!counter[11] & (!\counter[10]~40 & VCC)) +// \counter[11]~42 = CARRY((counter[11] & !\counter[10]~40 )) - .dataa(gnd), - .datab(counter[11]), + .dataa(counter[11]), + .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\Add0~21 ), - .combout(\Add0~22_combout ), - .cout(\Add0~23 )); + .cin(\counter[10]~40 ), + .combout(\counter[11]~41_combout ), + .cout(\counter[11]~42 )); // synopsys translate_off -defparam \Add0~22 .lut_mask = 16'h3C3F; -defparam \Add0~22 .sum_lutc_input = "cin"; +defparam \counter[11]~41 .lut_mask = 16'hA50A; +defparam \counter[11]~41 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y17_N3 +// Location: LCCOMB_X28_Y18_N4 +cycloneive_lcell_comb \counter[11]~feeder ( +// Equation(s): +// \counter[11]~feeder_combout = \counter[11]~41_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\counter[11]~41_combout ), + .cin(gnd), + .combout(\counter[11]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \counter[11]~feeder .lut_mask = 16'hFF00; +defparam \counter[11]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N5 dffeas \counter[11] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~22_combout ), + .d(\counter[11]~feeder_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -729,28 +815,28 @@ defparam \counter[11] .is_wysiwyg = "true"; defparam \counter[11] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N4 -cycloneive_lcell_comb \Add0~24 ( +// Location: LCCOMB_X28_Y17_N2 +cycloneive_lcell_comb \counter[12]~43 ( // Equation(s): -// \Add0~24_combout = (counter[12] & (\Add0~23 $ (GND))) # (!counter[12] & (!\Add0~23 & VCC)) -// \Add0~25 = CARRY((counter[12] & !\Add0~23 )) +// \counter[12]~43_combout = (counter[12] & (!\counter[11]~42 )) # (!counter[12] & ((\counter[11]~42 ) # (GND))) +// \counter[12]~44 = CARRY((!\counter[11]~42 ) # (!counter[12])) .dataa(gnd), .datab(counter[12]), .datac(gnd), .datad(vcc), - .cin(\Add0~23 ), - .combout(\Add0~24_combout ), - .cout(\Add0~25 )); + .cin(\counter[11]~42 ), + .combout(\counter[12]~43_combout ), + .cout(\counter[12]~44 )); // synopsys translate_off -defparam \Add0~24 .lut_mask = 16'hC30C; -defparam \Add0~24 .sum_lutc_input = "cin"; +defparam \counter[12]~43 .lut_mask = 16'h3C3F; +defparam \counter[12]~43 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y17_N5 +// Location: FF_X28_Y17_N3 dffeas \counter[12] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~24_combout ), + .d(\counter[12]~43_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -766,28 +852,28 @@ defparam \counter[12] .is_wysiwyg = "true"; defparam \counter[12] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N6 -cycloneive_lcell_comb \Add0~26 ( +// Location: LCCOMB_X28_Y17_N4 +cycloneive_lcell_comb \counter[13]~45 ( // Equation(s): -// \Add0~26_combout = (counter[13] & (!\Add0~25 )) # (!counter[13] & ((\Add0~25 ) # (GND))) -// \Add0~27 = CARRY((!\Add0~25 ) # (!counter[13])) +// \counter[13]~45_combout = (counter[13] & (\counter[12]~44 $ (GND))) # (!counter[13] & (!\counter[12]~44 & VCC)) +// \counter[13]~46 = CARRY((counter[13] & !\counter[12]~44 )) .dataa(gnd), .datab(counter[13]), .datac(gnd), .datad(vcc), - .cin(\Add0~25 ), - .combout(\Add0~26_combout ), - .cout(\Add0~27 )); + .cin(\counter[12]~44 ), + .combout(\counter[13]~45_combout ), + .cout(\counter[13]~46 )); // synopsys translate_off -defparam \Add0~26 .lut_mask = 16'h3C3F; -defparam \Add0~26 .sum_lutc_input = "cin"; +defparam \counter[13]~45 .lut_mask = 16'hC30C; +defparam \counter[13]~45 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y17_N7 +// Location: FF_X28_Y17_N5 dffeas \counter[13] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~26_combout ), + .d(\counter[13]~45_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -803,28 +889,28 @@ defparam \counter[13] .is_wysiwyg = "true"; defparam \counter[13] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N8 -cycloneive_lcell_comb \Add0~28 ( +// Location: LCCOMB_X28_Y17_N6 +cycloneive_lcell_comb \counter[14]~47 ( // Equation(s): -// \Add0~28_combout = (counter[14] & (\Add0~27 $ (GND))) # (!counter[14] & (!\Add0~27 & VCC)) -// \Add0~29 = CARRY((counter[14] & !\Add0~27 )) +// \counter[14]~47_combout = (counter[14] & (!\counter[13]~46 )) # (!counter[14] & ((\counter[13]~46 ) # (GND))) +// \counter[14]~48 = CARRY((!\counter[13]~46 ) # (!counter[14])) .dataa(counter[14]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\Add0~27 ), - .combout(\Add0~28_combout ), - .cout(\Add0~29 )); + .cin(\counter[13]~46 ), + .combout(\counter[14]~47_combout ), + .cout(\counter[14]~48 )); // synopsys translate_off -defparam \Add0~28 .lut_mask = 16'hA50A; -defparam \Add0~28 .sum_lutc_input = "cin"; +defparam \counter[14]~47 .lut_mask = 16'h5A5F; +defparam \counter[14]~47 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y17_N9 +// Location: FF_X28_Y17_N7 dffeas \counter[14] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~28_combout ), + .d(\counter[14]~47_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -840,28 +926,28 @@ defparam \counter[14] .is_wysiwyg = "true"; defparam \counter[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N10 -cycloneive_lcell_comb \Add0~30 ( +// Location: LCCOMB_X28_Y17_N8 +cycloneive_lcell_comb \counter[15]~49 ( // Equation(s): -// \Add0~30_combout = (counter[15] & (!\Add0~29 )) # (!counter[15] & ((\Add0~29 ) # (GND))) -// \Add0~31 = CARRY((!\Add0~29 ) # (!counter[15])) +// \counter[15]~49_combout = (counter[15] & (\counter[14]~48 $ (GND))) # (!counter[15] & (!\counter[14]~48 & VCC)) +// \counter[15]~50 = CARRY((counter[15] & !\counter[14]~48 )) .dataa(gnd), .datab(counter[15]), .datac(gnd), .datad(vcc), - .cin(\Add0~29 ), - .combout(\Add0~30_combout ), - .cout(\Add0~31 )); + .cin(\counter[14]~48 ), + .combout(\counter[15]~49_combout ), + .cout(\counter[15]~50 )); // synopsys translate_off -defparam \Add0~30 .lut_mask = 16'h3C3F; -defparam \Add0~30 .sum_lutc_input = "cin"; +defparam \counter[15]~49 .lut_mask = 16'hC30C; +defparam \counter[15]~49 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y17_N11 +// Location: FF_X28_Y17_N9 dffeas \counter[15] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~30_combout ), + .d(\counter[15]~49_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -877,28 +963,28 @@ defparam \counter[15] .is_wysiwyg = "true"; defparam \counter[15] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N12 -cycloneive_lcell_comb \Add0~32 ( +// Location: LCCOMB_X28_Y17_N10 +cycloneive_lcell_comb \counter[16]~51 ( // Equation(s): -// \Add0~32_combout = (counter[16] & (\Add0~31 $ (GND))) # (!counter[16] & (!\Add0~31 & VCC)) -// \Add0~33 = CARRY((counter[16] & !\Add0~31 )) +// \counter[16]~51_combout = (counter[16] & (!\counter[15]~50 )) # (!counter[16] & ((\counter[15]~50 ) # (GND))) +// \counter[16]~52 = CARRY((!\counter[15]~50 ) # (!counter[16])) - .dataa(gnd), - .datab(counter[16]), + .dataa(counter[16]), + .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\Add0~31 ), - .combout(\Add0~32_combout ), - .cout(\Add0~33 )); + .cin(\counter[15]~50 ), + .combout(\counter[16]~51_combout ), + .cout(\counter[16]~52 )); // synopsys translate_off -defparam \Add0~32 .lut_mask = 16'hC30C; -defparam \Add0~32 .sum_lutc_input = "cin"; +defparam \counter[16]~51 .lut_mask = 16'h5A5F; +defparam \counter[16]~51 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y17_N13 +// Location: FF_X28_Y17_N11 dffeas \counter[16] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~32_combout ), + .d(\counter[16]~51_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -914,28 +1000,28 @@ defparam \counter[16] .is_wysiwyg = "true"; defparam \counter[16] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N14 -cycloneive_lcell_comb \Add0~34 ( +// Location: LCCOMB_X28_Y17_N12 +cycloneive_lcell_comb \counter[17]~53 ( // Equation(s): -// \Add0~34_combout = (counter[17] & (!\Add0~33 )) # (!counter[17] & ((\Add0~33 ) # (GND))) -// \Add0~35 = CARRY((!\Add0~33 ) # (!counter[17])) +// \counter[17]~53_combout = (counter[17] & (\counter[16]~52 $ (GND))) # (!counter[17] & (!\counter[16]~52 & VCC)) +// \counter[17]~54 = CARRY((counter[17] & !\counter[16]~52 )) .dataa(counter[17]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\Add0~33 ), - .combout(\Add0~34_combout ), - .cout(\Add0~35 )); + .cin(\counter[16]~52 ), + .combout(\counter[17]~53_combout ), + .cout(\counter[17]~54 )); // synopsys translate_off -defparam \Add0~34 .lut_mask = 16'h5A5F; -defparam \Add0~34 .sum_lutc_input = "cin"; +defparam \counter[17]~53 .lut_mask = 16'hA50A; +defparam \counter[17]~53 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y17_N15 +// Location: FF_X28_Y17_N13 dffeas \counter[17] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~34_combout ), + .d(\counter[17]~53_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -951,28 +1037,28 @@ defparam \counter[17] .is_wysiwyg = "true"; defparam \counter[17] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N16 -cycloneive_lcell_comb \Add0~36 ( +// Location: LCCOMB_X28_Y17_N14 +cycloneive_lcell_comb \counter[18]~55 ( // Equation(s): -// \Add0~36_combout = (counter[18] & (\Add0~35 $ (GND))) # (!counter[18] & (!\Add0~35 & VCC)) -// \Add0~37 = CARRY((counter[18] & !\Add0~35 )) +// \counter[18]~55_combout = (counter[18] & (!\counter[17]~54 )) # (!counter[18] & ((\counter[17]~54 ) # (GND))) +// \counter[18]~56 = CARRY((!\counter[17]~54 ) # (!counter[18])) - .dataa(counter[18]), - .datab(gnd), + .dataa(gnd), + .datab(counter[18]), .datac(gnd), .datad(vcc), - .cin(\Add0~35 ), - .combout(\Add0~36_combout ), - .cout(\Add0~37 )); + .cin(\counter[17]~54 ), + .combout(\counter[18]~55_combout ), + .cout(\counter[18]~56 )); // synopsys translate_off -defparam \Add0~36 .lut_mask = 16'hA50A; -defparam \Add0~36 .sum_lutc_input = "cin"; +defparam \counter[18]~55 .lut_mask = 16'h3C3F; +defparam \counter[18]~55 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y17_N17 +// Location: FF_X28_Y17_N15 dffeas \counter[18] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~36_combout ), + .d(\counter[18]~55_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -988,28 +1074,28 @@ defparam \counter[18] .is_wysiwyg = "true"; defparam \counter[18] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N18 -cycloneive_lcell_comb \Add0~38 ( +// Location: LCCOMB_X28_Y17_N16 +cycloneive_lcell_comb \counter[19]~57 ( // Equation(s): -// \Add0~38_combout = (counter[19] & (!\Add0~37 )) # (!counter[19] & ((\Add0~37 ) # (GND))) -// \Add0~39 = CARRY((!\Add0~37 ) # (!counter[19])) +// \counter[19]~57_combout = (counter[19] & (\counter[18]~56 $ (GND))) # (!counter[19] & (!\counter[18]~56 & VCC)) +// \counter[19]~58 = CARRY((counter[19] & !\counter[18]~56 )) - .dataa(counter[19]), - .datab(gnd), + .dataa(gnd), + .datab(counter[19]), .datac(gnd), .datad(vcc), - .cin(\Add0~37 ), - .combout(\Add0~38_combout ), - .cout(\Add0~39 )); + .cin(\counter[18]~56 ), + .combout(\counter[19]~57_combout ), + .cout(\counter[19]~58 )); // synopsys translate_off -defparam \Add0~38 .lut_mask = 16'h5A5F; -defparam \Add0~38 .sum_lutc_input = "cin"; +defparam \counter[19]~57 .lut_mask = 16'hC30C; +defparam \counter[19]~57 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y17_N19 +// Location: FF_X28_Y17_N17 dffeas \counter[19] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~38_combout ), + .d(\counter[19]~57_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1025,32 +1111,15 @@ defparam \counter[19] .is_wysiwyg = "true"; defparam \counter[19] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N20 -cycloneive_lcell_comb \Add0~40 ( -// Equation(s): -// \Add0~40_combout = \Add0~39 $ (!counter[20]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(counter[20]), - .cin(\Add0~39 ), - .combout(\Add0~40_combout ), - .cout()); -// synopsys translate_off -defparam \Add0~40 .lut_mask = 16'hF00F; -defparam \Add0~40 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N28 +// Location: LCCOMB_X28_Y17_N28 cycloneive_lcell_comb \Equal0~5 ( // Equation(s): -// \Equal0~5_combout = (!\Add0~32_combout & (!\Add0~36_combout & (!\Add0~34_combout & !\Add0~38_combout ))) +// \Equal0~5_combout = (!counter[17] & (!counter[19] & (!counter[18] & !counter[16]))) - .dataa(\Add0~32_combout ), - .datab(\Add0~36_combout ), - .datac(\Add0~34_combout ), - .datad(\Add0~38_combout ), + .dataa(counter[17]), + .datab(counter[19]), + .datac(counter[18]), + .datad(counter[16]), .cin(gnd), .combout(\Equal0~5_combout ), .cout()); @@ -1059,32 +1128,15 @@ defparam \Equal0~5 .lut_mask = 16'h0001; defparam \Equal0~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y18_N6 -cycloneive_lcell_comb \Equal0~1 ( -// Equation(s): -// \Equal0~1_combout = (!\Add0~10_combout & (!\Add0~8_combout & (!\Add0~14_combout & !\Add0~12_combout ))) - - .dataa(\Add0~10_combout ), - .datab(\Add0~8_combout ), - .datac(\Add0~14_combout ), - .datad(\Add0~12_combout ), - .cin(gnd), - .combout(\Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \Equal0~1 .lut_mask = 16'h0001; -defparam \Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N4 +// Location: LCCOMB_X28_Y18_N8 cycloneive_lcell_comb \Equal0~0 ( // Equation(s): -// \Equal0~0_combout = (!\Add0~4_combout & (!\Add0~0_combout & (!\Add0~6_combout & !\Add0~2_combout ))) +// \Equal0~0_combout = (!counter[1] & (!counter[0] & (!counter[2] & !counter[3]))) - .dataa(\Add0~4_combout ), - .datab(\Add0~0_combout ), - .datac(\Add0~6_combout ), - .datad(\Add0~2_combout ), + .dataa(counter[1]), + .datab(counter[0]), + .datac(counter[2]), + .datad(counter[3]), .cin(gnd), .combout(\Equal0~0_combout ), .cout()); @@ -1093,15 +1145,32 @@ defparam \Equal0~0 .lut_mask = 16'h0001; defparam \Equal0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N30 +// Location: LCCOMB_X28_Y18_N6 +cycloneive_lcell_comb \Equal0~1 ( +// Equation(s): +// \Equal0~1_combout = (!counter[6] & (!counter[7] & (!counter[5] & !counter[4]))) + + .dataa(counter[6]), + .datab(counter[7]), + .datac(counter[5]), + .datad(counter[4]), + .cin(gnd), + .combout(\Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~1 .lut_mask = 16'h0001; +defparam \Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N0 cycloneive_lcell_comb \Equal0~2 ( // Equation(s): -// \Equal0~2_combout = (!\Add0~22_combout & (!\Add0~16_combout & (!\Add0~20_combout & !\Add0~18_combout ))) +// \Equal0~2_combout = (!counter[8] & (!counter[11] & (!counter[10] & !counter[9]))) - .dataa(\Add0~22_combout ), - .datab(\Add0~16_combout ), - .datac(\Add0~20_combout ), - .datad(\Add0~18_combout ), + .dataa(counter[8]), + .datab(counter[11]), + .datac(counter[10]), + .datad(counter[9]), .cin(gnd), .combout(\Equal0~2_combout ), .cout()); @@ -1110,15 +1179,15 @@ defparam \Equal0~2 .lut_mask = 16'h0001; defparam \Equal0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N30 +// Location: LCCOMB_X28_Y17_N26 cycloneive_lcell_comb \Equal0~3 ( // Equation(s): -// \Equal0~3_combout = (!\Add0~26_combout & (!\Add0~24_combout & (!\Add0~28_combout & !\Add0~30_combout ))) +// \Equal0~3_combout = (!counter[14] & (!counter[13] & (!counter[15] & !counter[12]))) - .dataa(\Add0~26_combout ), - .datab(\Add0~24_combout ), - .datac(\Add0~28_combout ), - .datad(\Add0~30_combout ), + .dataa(counter[14]), + .datab(counter[13]), + .datac(counter[15]), + .datad(counter[12]), .cin(gnd), .combout(\Equal0~3_combout ), .cout()); @@ -1127,13 +1196,13 @@ defparam \Equal0~3 .lut_mask = 16'h0001; defparam \Equal0~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N28 +// Location: LCCOMB_X29_Y18_N28 cycloneive_lcell_comb \Equal0~4 ( // Equation(s): -// \Equal0~4_combout = (\Equal0~1_combout & (\Equal0~0_combout & (\Equal0~2_combout & \Equal0~3_combout ))) +// \Equal0~4_combout = (\Equal0~0_combout & (\Equal0~1_combout & (\Equal0~2_combout & \Equal0~3_combout ))) - .dataa(\Equal0~1_combout ), - .datab(\Equal0~0_combout ), + .dataa(\Equal0~0_combout ), + .datab(\Equal0~1_combout ), .datac(\Equal0~2_combout ), .datad(\Equal0~3_combout ), .cin(gnd), @@ -1144,27 +1213,117 @@ defparam \Equal0~4 .lut_mask = 16'h8000; defparam \Equal0~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N20 -cycloneive_lcell_comb \address[0]~0 ( +// Location: LCCOMB_X28_Y17_N18 +cycloneive_lcell_comb \counter[20]~59 ( // Equation(s): -// \address[0]~0_combout = address[0] $ (((!\Add0~40_combout & (\Equal0~5_combout & \Equal0~4_combout )))) +// \counter[20]~59_combout = (counter[20] & (!\counter[19]~58 )) # (!counter[20] & ((\counter[19]~58 ) # (GND))) +// \counter[20]~60 = CARRY((!\counter[19]~58 ) # (!counter[20])) - .dataa(\Add0~40_combout ), - .datab(\Equal0~5_combout ), - .datac(address[0]), - .datad(\Equal0~4_combout ), - .cin(gnd), - .combout(\address[0]~0_combout ), - .cout()); + .dataa(gnd), + .datab(counter[20]), + .datac(gnd), + .datad(vcc), + .cin(\counter[19]~58 ), + .combout(\counter[20]~59_combout ), + .cout(\counter[20]~60 )); // synopsys translate_off -defparam \address[0]~0 .lut_mask = 16'hB4F0; -defparam \address[0]~0 .sum_lutc_input = "datac"; +defparam \counter[20]~59 .lut_mask = 16'h3C3F; +defparam \counter[20]~59 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X32_Y17_N21 +// Location: FF_X28_Y17_N19 +dffeas \counter[20] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\counter[20]~59_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[20]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[20] .is_wysiwyg = "true"; +defparam \counter[20] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N20 +cycloneive_lcell_comb \counter[21]~61 ( +// Equation(s): +// \counter[21]~61_combout = \counter[20]~60 $ (!counter[21]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(counter[21]), + .cin(\counter[20]~60 ), + .combout(\counter[21]~61_combout ), + .cout()); +// synopsys translate_off +defparam \counter[21]~61 .lut_mask = 16'hF00F; +defparam \counter[21]~61 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X28_Y17_N21 +dffeas \counter[21] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\counter[21]~61_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[21]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[21] .is_wysiwyg = "true"; +defparam \counter[21] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N10 +cycloneive_lcell_comb \Equal0~7 ( +// Equation(s): +// \Equal0~7_combout = (!counter[21] & !counter[20]) + + .dataa(gnd), + .datab(gnd), + .datac(counter[21]), + .datad(counter[20]), + .cin(gnd), + .combout(\Equal0~7_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~7 .lut_mask = 16'h000F; +defparam \Equal0~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N30 +cycloneive_lcell_comb \address[0]~39 ( +// Equation(s): +// \address[0]~39_combout = address[0] $ (((\Equal0~5_combout & (\Equal0~4_combout & \Equal0~7_combout )))) + + .dataa(\Equal0~5_combout ), + .datab(\Equal0~4_combout ), + .datac(address[0]), + .datad(\Equal0~7_combout ), + .cin(gnd), + .combout(\address[0]~39_combout ), + .cout()); +// synopsys translate_off +defparam \address[0]~39 .lut_mask = 16'h78F0; +defparam \address[0]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y18_N31 dffeas \address[0] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[0]~0_combout ), + .d(\address[0]~39_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1180,67 +1339,51 @@ defparam \address[0] .is_wysiwyg = "true"; defparam \address[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N26 +// Location: LCCOMB_X29_Y18_N0 +cycloneive_lcell_comb \address[1]~13 ( +// Equation(s): +// \address[1]~13_combout = (address[0] & (address[1] $ (VCC))) # (!address[0] & (address[1] & VCC)) +// \address[1]~14 = CARRY((address[0] & address[1])) + + .dataa(address[0]), + .datab(address[1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\address[1]~13_combout ), + .cout(\address[1]~14 )); +// synopsys translate_off +defparam \address[1]~13 .lut_mask = 16'h6688; +defparam \address[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N26 cycloneive_lcell_comb \Equal0~6 ( // Equation(s): -// \Equal0~6_combout = (!\Add0~34_combout & !\Add0~32_combout ) +// \Equal0~6_combout = (!counter[20] & (!counter[21] & (\Equal0~5_combout & \Equal0~4_combout ))) - .dataa(gnd), - .datab(gnd), - .datac(\Add0~34_combout ), - .datad(\Add0~32_combout ), + .dataa(counter[20]), + .datab(counter[21]), + .datac(\Equal0~5_combout ), + .datad(\Equal0~4_combout ), .cin(gnd), .combout(\Equal0~6_combout ), .cout()); // synopsys translate_off -defparam \Equal0~6 .lut_mask = 16'h000F; +defparam \Equal0~6 .lut_mask = 16'h1000; defparam \Equal0~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N24 -cycloneive_lcell_comb \Equal0~7 ( -// Equation(s): -// \Equal0~7_combout = (!\Add0~40_combout & (!\Add0~36_combout & (\Equal0~6_combout & !\Add0~38_combout ))) - - .dataa(\Add0~40_combout ), - .datab(\Add0~36_combout ), - .datac(\Equal0~6_combout ), - .datad(\Add0~38_combout ), - .cin(gnd), - .combout(\Equal0~7_combout ), - .cout()); -// synopsys translate_off -defparam \Equal0~7 .lut_mask = 16'h0010; -defparam \Equal0~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N10 -cycloneive_lcell_comb \address[1]~1 ( -// Equation(s): -// \address[1]~1_combout = address[1] $ (((address[0] & (\Equal0~4_combout & \Equal0~7_combout )))) - - .dataa(address[0]), - .datab(\Equal0~4_combout ), - .datac(address[1]), - .datad(\Equal0~7_combout ), - .cin(gnd), - .combout(\address[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \address[1]~1 .lut_mask = 16'h78F0; -defparam \address[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N11 +// Location: FF_X29_Y18_N1 dffeas \address[1] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[1]~1_combout ), + .d(\address[1]~13_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(vcc), + .ena(\Equal0~6_combout ), .devclrn(devclrn), .devpor(devpor), .q(address[1]), @@ -1250,50 +1393,34 @@ defparam \address[1] .is_wysiwyg = "true"; defparam \address[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N2 -cycloneive_lcell_comb \address[1]~2 ( +// Location: LCCOMB_X29_Y18_N2 +cycloneive_lcell_comb \address[2]~15 ( // Equation(s): -// \address[1]~2_combout = (address[0] & (\Equal0~5_combout & (!\Add0~40_combout & \Equal0~4_combout ))) - - .dataa(address[0]), - .datab(\Equal0~5_combout ), - .datac(\Add0~40_combout ), - .datad(\Equal0~4_combout ), - .cin(gnd), - .combout(\address[1]~2_combout ), - .cout()); -// synopsys translate_off -defparam \address[1]~2 .lut_mask = 16'h0800; -defparam \address[1]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N16 -cycloneive_lcell_comb \address[2]~3 ( -// Equation(s): -// \address[2]~3_combout = address[2] $ (((address[1] & \address[1]~2_combout ))) +// \address[2]~15_combout = (address[2] & (!\address[1]~14 )) # (!address[2] & ((\address[1]~14 ) # (GND))) +// \address[2]~16 = CARRY((!\address[1]~14 ) # (!address[2])) .dataa(gnd), - .datab(address[1]), - .datac(address[2]), - .datad(\address[1]~2_combout ), - .cin(gnd), - .combout(\address[2]~3_combout ), - .cout()); + .datab(address[2]), + .datac(gnd), + .datad(vcc), + .cin(\address[1]~14 ), + .combout(\address[2]~15_combout ), + .cout(\address[2]~16 )); // synopsys translate_off -defparam \address[2]~3 .lut_mask = 16'h3CF0; -defparam \address[2]~3 .sum_lutc_input = "datac"; +defparam \address[2]~15 .lut_mask = 16'h3C3F; +defparam \address[2]~15 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X32_Y17_N17 +// Location: FF_X29_Y18_N3 dffeas \address[2] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[2]~3_combout ), + .d(\address[2]~15_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(vcc), + .ena(\Equal0~6_combout ), .devclrn(devclrn), .devpor(devpor), .q(address[2]), @@ -1303,7 +1430,541 @@ defparam \address[2] .is_wysiwyg = "true"; defparam \address[2] .power_up = "low"; // synopsys translate_on -// Location: M9K_X33_Y26_N0 +// Location: LCCOMB_X29_Y18_N4 +cycloneive_lcell_comb \address[3]~17 ( +// Equation(s): +// \address[3]~17_combout = (address[3] & (\address[2]~16 $ (GND))) # (!address[3] & (!\address[2]~16 & VCC)) +// \address[3]~18 = CARRY((address[3] & !\address[2]~16 )) + + .dataa(gnd), + .datab(address[3]), + .datac(gnd), + .datad(vcc), + .cin(\address[2]~16 ), + .combout(\address[3]~17_combout ), + .cout(\address[3]~18 )); +// synopsys translate_off +defparam \address[3]~17 .lut_mask = 16'hC30C; +defparam \address[3]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y18_N5 +dffeas \address[3] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[3]~17_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(address[3]), + .prn(vcc)); +// synopsys translate_off +defparam \address[3] .is_wysiwyg = "true"; +defparam \address[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N6 +cycloneive_lcell_comb \address[4]~19 ( +// Equation(s): +// \address[4]~19_combout = (address[4] & (!\address[3]~18 )) # (!address[4] & ((\address[3]~18 ) # (GND))) +// \address[4]~20 = CARRY((!\address[3]~18 ) # (!address[4])) + + .dataa(address[4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\address[3]~18 ), + .combout(\address[4]~19_combout ), + .cout(\address[4]~20 )); +// synopsys translate_off +defparam \address[4]~19 .lut_mask = 16'h5A5F; +defparam \address[4]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y18_N7 +dffeas \address[4] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[4]~19_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(address[4]), + .prn(vcc)); +// synopsys translate_off +defparam \address[4] .is_wysiwyg = "true"; +defparam \address[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N8 +cycloneive_lcell_comb \address[5]~21 ( +// Equation(s): +// \address[5]~21_combout = (address[5] & (\address[4]~20 $ (GND))) # (!address[5] & (!\address[4]~20 & VCC)) +// \address[5]~22 = CARRY((address[5] & !\address[4]~20 )) + + .dataa(gnd), + .datab(address[5]), + .datac(gnd), + .datad(vcc), + .cin(\address[4]~20 ), + .combout(\address[5]~21_combout ), + .cout(\address[5]~22 )); +// synopsys translate_off +defparam \address[5]~21 .lut_mask = 16'hC30C; +defparam \address[5]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y18_N9 +dffeas \address[5] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[5]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(address[5]), + .prn(vcc)); +// synopsys translate_off +defparam \address[5] .is_wysiwyg = "true"; +defparam \address[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N10 +cycloneive_lcell_comb \address[6]~23 ( +// Equation(s): +// \address[6]~23_combout = (address[6] & (!\address[5]~22 )) # (!address[6] & ((\address[5]~22 ) # (GND))) +// \address[6]~24 = CARRY((!\address[5]~22 ) # (!address[6])) + + .dataa(address[6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\address[5]~22 ), + .combout(\address[6]~23_combout ), + .cout(\address[6]~24 )); +// synopsys translate_off +defparam \address[6]~23 .lut_mask = 16'h5A5F; +defparam \address[6]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y18_N11 +dffeas \address[6] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[6]~23_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(address[6]), + .prn(vcc)); +// synopsys translate_off +defparam \address[6] .is_wysiwyg = "true"; +defparam \address[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N12 +cycloneive_lcell_comb \address[7]~25 ( +// Equation(s): +// \address[7]~25_combout = (address[7] & (\address[6]~24 $ (GND))) # (!address[7] & (!\address[6]~24 & VCC)) +// \address[7]~26 = CARRY((address[7] & !\address[6]~24 )) + + .dataa(address[7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\address[6]~24 ), + .combout(\address[7]~25_combout ), + .cout(\address[7]~26 )); +// synopsys translate_off +defparam \address[7]~25 .lut_mask = 16'hA50A; +defparam \address[7]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y18_N13 +dffeas \address[7] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[7]~25_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(address[7]), + .prn(vcc)); +// synopsys translate_off +defparam \address[7] .is_wysiwyg = "true"; +defparam \address[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N14 +cycloneive_lcell_comb \address[8]~27 ( +// Equation(s): +// \address[8]~27_combout = (address[8] & (!\address[7]~26 )) # (!address[8] & ((\address[7]~26 ) # (GND))) +// \address[8]~28 = CARRY((!\address[7]~26 ) # (!address[8])) + + .dataa(gnd), + .datab(address[8]), + .datac(gnd), + .datad(vcc), + .cin(\address[7]~26 ), + .combout(\address[8]~27_combout ), + .cout(\address[8]~28 )); +// synopsys translate_off +defparam \address[8]~27 .lut_mask = 16'h3C3F; +defparam \address[8]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y18_N15 +dffeas \address[8] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[8]~27_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(address[8]), + .prn(vcc)); +// synopsys translate_off +defparam \address[8] .is_wysiwyg = "true"; +defparam \address[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N16 +cycloneive_lcell_comb \address[9]~29 ( +// Equation(s): +// \address[9]~29_combout = (address[9] & (\address[8]~28 $ (GND))) # (!address[9] & (!\address[8]~28 & VCC)) +// \address[9]~30 = CARRY((address[9] & !\address[8]~28 )) + + .dataa(gnd), + .datab(address[9]), + .datac(gnd), + .datad(vcc), + .cin(\address[8]~28 ), + .combout(\address[9]~29_combout ), + .cout(\address[9]~30 )); +// synopsys translate_off +defparam \address[9]~29 .lut_mask = 16'hC30C; +defparam \address[9]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y18_N17 +dffeas \address[9] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[9]~29_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(address[9]), + .prn(vcc)); +// synopsys translate_off +defparam \address[9] .is_wysiwyg = "true"; +defparam \address[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N18 +cycloneive_lcell_comb \address[10]~31 ( +// Equation(s): +// \address[10]~31_combout = (address[10] & (!\address[9]~30 )) # (!address[10] & ((\address[9]~30 ) # (GND))) +// \address[10]~32 = CARRY((!\address[9]~30 ) # (!address[10])) + + .dataa(gnd), + .datab(address[10]), + .datac(gnd), + .datad(vcc), + .cin(\address[9]~30 ), + .combout(\address[10]~31_combout ), + .cout(\address[10]~32 )); +// synopsys translate_off +defparam \address[10]~31 .lut_mask = 16'h3C3F; +defparam \address[10]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y18_N19 +dffeas \address[10] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[10]~31_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(address[10]), + .prn(vcc)); +// synopsys translate_off +defparam \address[10] .is_wysiwyg = "true"; +defparam \address[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N20 +cycloneive_lcell_comb \address[11]~33 ( +// Equation(s): +// \address[11]~33_combout = (address[11] & (\address[10]~32 $ (GND))) # (!address[11] & (!\address[10]~32 & VCC)) +// \address[11]~34 = CARRY((address[11] & !\address[10]~32 )) + + .dataa(gnd), + .datab(address[11]), + .datac(gnd), + .datad(vcc), + .cin(\address[10]~32 ), + .combout(\address[11]~33_combout ), + .cout(\address[11]~34 )); +// synopsys translate_off +defparam \address[11]~33 .lut_mask = 16'hC30C; +defparam \address[11]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y18_N21 +dffeas \address[11] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[11]~33_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(address[11]), + .prn(vcc)); +// synopsys translate_off +defparam \address[11] .is_wysiwyg = "true"; +defparam \address[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N22 +cycloneive_lcell_comb \address[12]~35 ( +// Equation(s): +// \address[12]~35_combout = (address[12] & (!\address[11]~34 )) # (!address[12] & ((\address[11]~34 ) # (GND))) +// \address[12]~36 = CARRY((!\address[11]~34 ) # (!address[12])) + + .dataa(address[12]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\address[11]~34 ), + .combout(\address[12]~35_combout ), + .cout(\address[12]~36 )); +// synopsys translate_off +defparam \address[12]~35 .lut_mask = 16'h5A5F; +defparam \address[12]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y18_N23 +dffeas \address[12] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[12]~35_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(address[12]), + .prn(vcc)); +// synopsys translate_off +defparam \address[12] .is_wysiwyg = "true"; +defparam \address[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N24 +cycloneive_lcell_comb \address[13]~37 ( +// Equation(s): +// \address[13]~37_combout = \address[12]~36 $ (!address[13]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(address[13]), + .cin(\address[12]~36 ), + .combout(\address[13]~37_combout ), + .cout()); +// synopsys translate_off +defparam \address[13]~37 .lut_mask = 16'hF00F; +defparam \address[13]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y18_N25 +dffeas \address[13] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[13]~37_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(address[13]), + .prn(vcc)); +// synopsys translate_off +defparam \address[13] .is_wysiwyg = "true"; +defparam \address[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N2 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = address[13] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(address[13]), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hFF00; +defparam \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y18_N3 +dffeas \rom|altsyncram_component|auto_generated|address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\rom|altsyncram_component|auto_generated|address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; +defparam \rom|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N24 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout = \rom|altsyncram_component|auto_generated|address_reg_a [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\rom|altsyncram_component|auto_generated|address_reg_a [0]), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .lut_mask = 16'hFF00; +defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y18_N25 +dffeas \rom|altsyncram_component|auto_generated|out_address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; +defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: M9K_X33_Y13_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h3C00000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005DB824E17CAAE881C1908A79F24B7D1B4857A981A6AF39DFF5A2FEE9141EB33592D8E9B82471FDDA6791810A1C29D415CC1A8FA03444DF0083F83506BA93E8D1A1856A768D73A08418BFB25A40001DD4833DAF33BD311BB45F39667627407EF59ED569C483EB3BE1B10551B1428A6169579293ED063CAA9C6ADB0433CFC15C33AFF04C710408C20AC28B5909A229CD7D1DB4EB9A44CE0EEDBBBD391D3128AAA3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'hDDE6FC8EBE3F9F3C3DFC6E8F07BFD31D50660B1E0B2506A533CE0E340C7C745CAEC4837C2A5FECBB94C1C969FFDDFF79BFFAAFDCA8D748399ABF75558ADD02F56F6DFFF29CB70FFD25A59DFFFED7B3F7E8B4CE6FFF3EF9CEC6BAE57ABFFFCEE647B2AFF5B87AA26AFFDD317DEDCFBDFFE1A0CAD3B58877DD2F647F7DF748E7CF4693FD3C1238FFAFBD7FDF567FA8FEF024F33AFD3AABC6B105EA80272D64895FFF9FFF6E3881C81AFDCF2257FD4F8ED5257D0E9B800726B6564D2B05012F76DF636CDEB4BDFCAEEFC61DFFEFB7E26262DEF2CB9F71565824FEBF3F7BDDEABB593F1BF746FBFFC353E37263FF38A796EF39E3FD7DFEBA7FFEFFBD97ABAF09E909; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'hE629BDF93D7F5B5BAF92FBAB477E9B315DB5A310CFACC7408DF9A544B1E57AF6EFEF92C2FA4D8D4E4AC86C277338FA37BCDD9D47782DB75EFF80781BCD23D0AFCAE30B9FE6AA29FFF6F72DA73DFE4F7ACD39687B9E69C5359E9B991F0246EFFBC5595561AC64787878F5CE14C664CF9EB0CDAFFBABEF1E83358371B9ED96E5069555AFBBD3AEBFCABFBBED7A5C5FE9BD0E6A91C6E7610042695EEB08D8881B1D735AF87DAE59FABBD7DEAF8717F2B72F428F5E37E5D6E13157B99CBD2D73B9C73C563C8B02C8CC39C64DDCEA1BEEB5E7353F93786145598FE634EF1000179B345725EA43CE18F187A1DE4DAABEA97963E3A7A96B8B7CBC095BEB7CE46274D9AF; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h4ED4AE2B1650D21EAFE01E7099EFCA3094FD4D705CF6B84AE21583E13385F8650004406BD60A023AB063D4E5966EA41AA997F5A49BFCB0657A9732D28EB8217E65F627A15E1057ADEE7B9E27122A58FB2B98B1EA560390C7E87715861814E04DCB76FAB179E9619BC7E7E9C9FD801CF87DBA1EA496E829D4E62861E1AF436A7585287860729C77B6C68CAEA3033A6E84D67249B594C407B39C68B4C1C97FDEFC6BAD12FDBB525EF4F87F4A23EC13CBC0262D8899A3A290F04F41C1324045B9FCEEC890579E95D5A0A546CCCDD48577558ABE7CA36EF67A70F6A8758BDA052D5B95DE707778B17C2379847A23AE5D4BB01F36F3F44A8162566D9FB15DE7CC83F7; +// synopsys translate_on + +// Location: M9K_X33_Y14_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( .portawe(vcc), .portare(vcc), @@ -1313,46 +1974,978 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(vcc), + .ena0(!address[13]), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain(18'b000000000000000000), - .portaaddr({address[2],address[1],address[0]}), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), .portabyteenamasks(1'b1), - .portbdatain(18'b000000000000000000), - .portbaddr(3'b000), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "./rom/gw03.hex"; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom"; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 18; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 18; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 144'h002040042000900018000600024001080081; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h1EEA3633EFEA856D05BA968C1B3C30CA1788DD95D16B8F914DDDFC3EE5C69945DF7D7BF31C6072BFA7993996AB7DD2F3EE4009844CC9D6CF9E583AEC48A52F2904B57D8E0D755851232838F9B5348838530D7AF95411555D263B8CA86A5D29D7CE4B65409D6F04C5709A56C241C3BCEF07459A416EB4E8F3D73CC714F4333AFE605D53A5C955D5D1412F8361617A54446971FD187442A60FB04457857BECC3120A01FDC7FE2CBF038A61DEE5FCE2D10C8F35FBF80C05ABFF4B6935287B125E8D56F9FDFE7D64C1F4E1F5641845CD17E836B97780400C702523FA8E7C7BBD6F0666591A35ADD26B6B7E33CA56E9AB329EFA7E68F98AE7CE9507755C74C430286A; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h88537A811D4EF6CD9668CCD3E2E7A8041788DCA5F7E08AF52AF5276078304DEB75B74BB9AC3C1A492952F7EEAA0E7CF9FBEDD0FB47EEFDCC3734B816F355C913CD2E1AF14C30545297A91BED3AEAEFF8F696B5F4FC80BC6B1A2559492E9198E4A5875745B625C6CA7A7292332492D139728A689DA1AE78B6B44CE4F4A4EA5A22F331598B364EF27516CC49A4662C5E5C92ED140D96373678F833AE434698237599716B8CBAE2D3D061F2C3D6337AB435B5C2144AB6FA2F8BB51357801066B6589467DA6C480E6D19CEEA8451CEFA88FD70E7925B0302F877F87FA833FBD147E937309C08305A10187707E3D57DDE4931F1D9E97A8F378981ABBF8D7B6B7539C3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h763DD7AA7EED3F4AD4EA7491ADE6F14E6DBADD0F090A8DF34D7BAD35DD2275F0BCCF19EEF299751C919C9C13C6FB9ED711AC4DA7D947CC79E9B6323EF6CE62638CEBCB187AE5D44ECA689C9BD4E5AE544DEA7E90D186B9F335F3323877AAD54196CE81973CB555904419599375501366EC343561BCF83357F8823671393B278C1C387A7970C7F3E688673CF5975EE3E5FF105CFCCFAB725D698FB088B063063C7833830C7B2C7AFB8A8D203C312306DA0E72641FFB93D59B5EC84F44AD55F4B884735325ACC969B2EAE10A1478D866F667DDEF7BBF75E6958B6D02DC6D0F807660A229B98541E6FE734DE2280A9B57FCD5A9BEFEF7CDA5ABEB44FD73D2794D56; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hD0734B461A36980411EB2A6C1BE76029258777EF227A8F6E84F74C4436098F67BA611013110188547995B108BB2DAE76F423A0D98845F9248BDFA45E10CA403A5E2B1A3E16869E1D37BCE906B82F401CBD467617DB34D9E0C80B5E6E10063EC4BD52921D249E377D95CFAAA309EEDAA57DA85F55DBB7048A69A4C801013948B617F7F5724D40707E6FF30002982023020449B4680C45D1CE6D8EB30A061DB8FEDD6E630C15271E48CA801988654FB501D5393392EE765C1EC95C1E4D86F18A965372B72B484E2F2664B735B69A5AB532B086BA4C62AD6D56EECBDB6984B251454845BD5B243DAED2B2489B313A35C50252AFD3E0B76FEF342335C7F1321D92FF; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N24 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout )) # +// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ))) + + .dataa(gnd), + .datab(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0 .lut_mask = 16'hF3C0; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y19_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h35C65240B61076066A23CE4CFC5E76063A1C2AE07DF555007338BDC080EA0C23082C891C76A4845096304A0D8502080C1198911998821D09C29CA830C337499236E0548D65FF9125A765F0220F6EB9D1B318244CC6CA2CBC9CEC6979C14EB28DE2E0440C6CBD61341FC178649A852D4A2A0627C688D905B882524E191E7951EAEF30312A73337CBAD4838F42A3293859CD169240D8E652F6D72D8D19D56DD7675939FC47C933E1B0AEF12A484454C247B00A6BEC5402AA08B5106E3065602454C80CEC08A7F5F85CE65326632B4C4F3920019A35AE2AEB321131046EE45B81D4EFD5995634050D4CFEC166B032B6415553AF0358304080D9DD0A2E5948593830; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h376E511217E00B624A46BA2E4CC10B729C326F710F24CFE78C5E63F3024B17CC5E1380C938A0A16C9B696272DE7A2948BE8AFE81310146B8AAE5E549FA27EFBE27929938B8E10530250877A4998D0DF0004852125C20CA8D4279881E41208B14198817644F293AC1946061117122A39D8841818C1389D51BDAC549181902516571163594CEC5863F0F56625E221D6B8180848C6B2BE24AA0AEEE5D187201CAAE6AA394A8644314895565192AE415630A42894D6EF21343903B348EED8642F2310644C9567C0BF9911B870B989C59330089AA4C8065AB1B11132213EE0FD830817DE6C2ED45D76325CA2A8E198859334553AB02945CAB1F17C142288008073004; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h20721F982534A8179F13E2C6328CDE7D2A73087D3A9314419022103DFF7677769FE2D1F27443253D58403577C801AE23371F00290A17E1C4A40258BFD204230EE9969472A81B83113144528F831AA6C3221E137C1E9C670E26809A894013828D9E2DBCBF62498A769893D7218899245CD18AE49F0146517422EE475D520029ED39BCEF6BF4D23532957455F1C80115524179D59C4C4534DF7296991146CE24508366123AA809AB30B47977571C5D70397A93C723106D0A2C254714359DC7C9E13AE624C94932927924D20024CD638A05C8620023319662D80E05805625BC4A4006C78011F78D8B82E59F0CD4B32D6801669BE3EB0B96960DFF152005EC7C16CB; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h9C8CA06AA05B63C89A59A3E4E80807B27A70B0006624C4AC4A0595CCD8CA20824CA272352720BCD900A6D79BFD9D0595EC0D044ABC8CC28E9AE946E3D2000A4EFA4F91915C6AC9D8570C292F10848189906127BCBE06FFE92DAFB4AAFB240D88DDBB7B207EFA1709B05E1C4801BD45625A36BB62220506E171891964A31BED2215408676F600F490FAA59B488C7998CC8CCC28922AC62644EEBB432EEECB51B16CDEE7468681D6C31E4991CA3736E9ACB7531EC6D8BBCD453718101EA25D79278C6AC955A8A6140421573E413CF5A80AA1436D8B4C31A2AB26D2A61CE834248BAD5751BD429B4F61318427560CE39D49299002165212181064E24FF0093B997B; +// synopsys translate_on + +// Location: M9K_X22_Y16_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h420000004200000000000000000080000000000000000000000000000030004480000000424202423E1E3E02304C3C0C3C7E7E40403E427E3402421824347C1C0400280000003C3406303220344C403C0400100010100000005062742400000091991809FB3BD9084A1241F5015988B3C506031934089E0E1FA8043DDAF2CC07D94A6F2B1D133C211222B22C787D430E45D4C53282288077DFC0F704AAD55127A2BEAEA114958D2817AB1213183A4E1A15E3690A08A33B429284A202011A1243D49CACA1C0A441405A720D21A0921294045F746229E287B95E956AA3DE0CA3B7A019C8039C4DDA6BC99371248CC6008A54CB84503442C4F91309238ECB252072; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h81F3167814687CBD683E54D44555E6C95B5F2A72C0C193C6110C0221A448D0C9A0D8E36A84D5C61285128845215F8F8821C308E368283D8E2B42989C04A8B51354E09A38775020189010680840800297C31282442326D008D1F2351A89FFD7C16087F8B130F04418C0A1C082FC005843F5B42CADD9455ADBD328C13219110DE100D988737BBB44C414210118C673B0C1BDF76C499226F78FF41A0AF7AFD3308AAA0AAA22B1C70003F542A66FD1F1CF9D4578315F8C1C6FEC3EDB9B322CB204821A94A248414CE030020F207BF040A06A3DF993DEA3823423F405294A52014565100E0A7211342DF02958046899EEBE6E491299A09312778193FEBD7FFABA8000; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h2C05EF54A3C0F7F5F017E03F5800377CCF6E493C84E8F56441831087370A084801DEC1A54696B9912E8B0705C8587D4F7D36C8638947A620554CC77819B55B7A12D552A8A0496EFE3AAC6F34739A94E798101823148D811212E9A349CC219049527CCD419525AD29AB7D372C0B56AA0A065F8BDC905346478059EC82801920687FF29C990C9E66273CC78041192D03081CC62A8A0D8CB4D9CF2F2558131A78B8A807C3A1110211AFCA2A142F0BA928156D142250438143D339E4E2079F298493C08C4847914664518E27EF7EB9C870A226AFC35BEDB651840466400D4B3C0F877740114D6B08228BCC693FB12CECCCD2461586069445ACFC910B1241434622B6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h5FFE6AD3343986C4103935236B6E6E11B940EF46A8FC06E6872A6929D50DCDB75621E625522D34519BF2C353F8AA030B9109C2F9686AD3AF57AF3016D9160354C0BED5FBD379F904A41BAFB6BE4EE9F208058229DD0C354F034A6C4D8B6C16A29F0120108829220B230F44550832C1022530CC13C4C30D8254ECA5200A1941266EE48A1CA6430860DE613153615CAF4C8D191004CE9C6105D8C6795B6484467D21D9DC46029B8376E97F2C7BF8C3A218EE79DDBCF886B2BBDE702F71B38AEC6914E5DCCAFE50CC13922A5B149C598A621F80C24D215291228844E7F33F9763C6639303AE5376F664C7125632C1A280CECD5740C77849D937472B202579964F60; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N0 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))) # +// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout )) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datab(gnd), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1 .lut_mask = 16'hF0AA; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y12_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h77A47C739FF6A22B8B5CDC49E748E9C739BDE6756DB4D22437E74183E12400CBF7D3C6CC8C7841AB49CC538E8A72F2E73C64D3DF3662B19C07D7D299CBEDEF3E7DA5F4A8458A9451315B681ADA9AB0D63218DFB77D3353C32837E954604B9D98144A4566F47B71715BE6CDB8BA64D536762E9224D70F9A5C374B4D1CAB8DF527027170C5DBCC2B6AD72B8E4CCC94DAA139D8BA64E3384337426E7F274CC88A373AB1F9007B8A7F2936D16274F9BF8B6BABD48FCE74047C1E738C5B303E815BA720C76D6362915156A7671331CE657011862E594E46A6D99392E2D640D766869389A4D43867379AB880C1ACE279E451CB3A9063A0B320F65E536B8EEF9CBB9C76; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h9A2921ED6AA0CC8387B267B9E7A182720833CEE061E6450C8E4A72E3C043F21A0AD007E832124E92429C091D167806C10041AF32DDE13A669990457D098CC2FE3AC884B1E69101135CD080022451F20884CCB9CD203C141402A5AD293C3BABA95ADFAF6726384795A7656B753D2369B9EB5595BAA722012DF8DCFBF15BF46D6EB755D1CBF0DCF6FD40BEEC16EAB4A6D16839C98CBE9DBB437C69FB709F8E79993B9DDFE4F823D6E124B75BCE9B29F799F926619184B6C1178389F07349210436293A130C900FBA4EA70D2BA25B343C5B026D8E8766A4E4267CDAEC99E830D2307D94E6ED80D6722F3989B91E31C63B64C363DCE71A861C14382E270FC02868C7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h386BA04E797A3F8551DAD9D24A8D259A03ECFF5AB81B1C31DFDAE10100544F8CF1A8CCFC0C7A15BD9E7C2557CB00BF2584E16AAD13D7EDB525A85ABF90C0136DD195D748900C29DF7F381280A9738CDC3BF5BBF937D3A4D99CE2BCCD97CEF2C7F00030AFDB7F22E68CBAA4D9BE7633D3B53E90E4B124422A2A4454BACA5A8DC9352CD1DAFC910CC504334DF9E6F1F4F30161A36293CC5CCF1CA13994ED29D34A5699692496359B8E67A7E74D9A0FC504C8465638CF74A0AF9185921A7D2629893091900604017933442359491FBAB63F346F0C5EC8E3A531984B09E605A30A0627271C28420E47B8DEC74738FC3EDF9FBD40EC09FC7B4D3A1475BE433705FB5F; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h973FED2E9BEDBA474B70B121A8D60F3B4EE3F1A238FB3B730EDEEE74EC632DB4D7779D7B79D1C75DF87378E98719C1AF38B1B801C71D180CE86370AE9C2BF38CF84DBBB9878C55457324E92D3DAE91D729AC76BBAD4C6EECA74DAB5EE9A175EE34ABEB9DFAA48538A57E3E5C158947081CA41402E8E65478737F73BB629AAE2EE51D405CAF70F622DD4599602D7910DCAC8214B2A42025110593202C8B164C8DF6369572C3BB8AA1984A8D12F776E224ECEEB21F97FCD6C0CF17A044EC2BBF0571A553CCDD8ABA79BD27B7AF735ED2D34F1EF3A81A160C9ECB1B1FAE6EDEEFF99E28CC30C7C2553DED3378D655AD194B2E6C1BCBED700F6713D960F33E4C361A; +// synopsys translate_on + +// Location: M9K_X33_Y15_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h8102080042447C443C0C3C402004FC1838787840407A00707C02487E444878428008004042460424402040024A3242124220044022404208520A4A24424A125A0A1028440000524A0A4A4A204A5240460800100010540042002064547E0600001FA9BE02B828694B8A82CB8C8158226808198E9EC6B021F07A2098D5E0ECB639D2B1908129B6A2D646516192D87593189D8B2B26CD6E16234C1CC90AD9831EBD89EAD271ECC39A80507716BB49626B743DFFCF99576C3FAC889860E46618ACB79EC30EEDE42EB1E31F3976CA23243179FAA96DCD66D51535351770D410DC8531866136E6184518410368288C446EC63A4FEE425019C244097049C2B2DC8D93C4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'hA111466C9493A2A7CA2204102414CC798BF0EEC2995A4814580BD07585585ED92E5172E82E845070000A846100500E84EA1803B8B07B99E1DC75BE6419674597B38F54EB9091AE3320201EE395AD63902282A031CE3E87CC902954AA515D5D6B6A855EC94CFEC4E0172C59A7D054F8F9F4356C312C204E40B05E2059407C8DC84683814663FB910969D1D631A952B381B7F635A33FD38D5CF15DF47D057F7FF555B555C2278100000A24804D7D98EB98602733818A12094F281287422CB40002464C92242004E0AE8518E001D124A7628010115D23C30462FC00A014A12133582A191E00538FC8A5004036A959ACB7A463D23E419EA06B744005385455A71250; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h6C60009CA281AEACDC1762945981B869F93D683EAF4AC7EE52412E85B60B91CD03AD0025F0D509F63202D877ECD8BF8005451F7BD346CF9E17B36F1850A7D80A8CF14A288EAE3BFE00FB2DB45080D4A50C58263A3B398DD51AB9CB554ECAA7B2E73D9D6D2C265859DB844C2C1952AD10241100174FE0444E6707D80A098D8585AAAC4802B74190FB007C0C0206186AFC1B3A2A46864F26118ED1D03ACB1062B7315502751655F60070E6B2C50609369611365AD1E3352327320331A51818030C7D8C4C59396600DC0C420495A0D987501490002BAD38012E20620D556A230B1796450B74E95A860FF3E434C65F1308F16F92395816B914F0CE870C1323347A4E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h7FC8531A7A319F3EBFC1383FFCDB0E09BD288288B078B4AD220B6FA934CF6187D972662C0D31E34E63B31CFC6EB4B35A69B67D85489E62EA99899A94F6800FDBA5D31B86A0288D29CE2EAAFF86A6A9F7000082293E6BB54F06E98ECCB199973EDA00FADB1D3A630BA18050635DE7DCB13B9B86E0CE6E08DC46331A352F716E3C441A0CC068A0823F8668A00621B779DE35FEC004050469F34866AEE766743D8C00FDF3B9F8DE7B76E97F8D32F0F39E4CAC68D9BBB68EA3915F6225F932CAAFDAD6E60DC661155EC9E80F8CEE659F19CC554B2C67C33EDCDA63BAD91B7D1842A7177AF49DF118FE47ACE3344964EBCADCFBB543F7729CCB340866D1157B6CCDDB; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N28 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ))) # +// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout )) + + .dataa(gnd), + .datab(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2 .lut_mask = 16'hFC30; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y17_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'hA504087E764CA02840304044540424244404044024804008A40A54484448544A800400207E4A0818204040024A1262124210084014407E08520A4A42424A1256522828280000524A124A4A7E4A527E4A106010607C38003C025408FE2400000087857B4051593F8FEF8A4F84E99E6FCC30DBEF9DDB582A41325A97B1EEE4166FF390FF8420BD829D1679F5F18B57EAB9C5CFBE75ECF7F3730C105ADF74BA7D7F9159D64BD7F217C1803F5B1169B463FF6C6EC899D6482FBA8E6B53DCF12F3BFFBE72266D55B4E9E5887FAF8840007C50220105C908100BAF6FBA7BF97E6E020792ADFDFBD96CFD77B36CF30CC5DE43A85FB6F0020203478F160F42F9A061FE44; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h812017671773A9EE08641F818054455F0BABE232D2AA00081423C0BCCE1E642C4B7AE34419240F3C0170E001D6CE75F0475D5A8A9012B9BD97153AB038EF6187776B42A5FE80BB5AAA2A550A58904A1C6DC992952AB4532C6CB2F975BC101356F70811E17D8C73F1D9BEF7F7E82EFAE6C2D2DB2126004D81CA67DACC344F6458C165510222E12BABC9B940EB70182EDBEEF007365AA980A2002829A05282A2AAAA8AAA32A2C38012BFEB492278CD27651FD91BDE452EEF054801275AA0D49D9A896B7EB5FD69B679669CBA00AA9A431956A3CE676A9D7B50D84F3FFFFFC4AAF735995E3ADF9E07EB861E3035B1EF3EF935DAFFFA1F94FDCA5B803F14101BE318; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'hCE21FFE0D222852612C7A87E8DFE961BD8CF052D4757559DF3ED2417472384AF04FF86DDFE9FCBD3DC2A4967F492CDD5A8FFBD9857306D8B07F3AD96A6138C0360BE688D11B16D7936F4B55E0E301BAD6A96802B5719271D55D5E93FED5335EF86E8AEC1EE37F6F5FFD77F204F5EBFDA614C41C1F85C32FFB05F2881BF7EB1D73DDBF48E39F1AE9FC0A7CAC2B4515882877D84D415C7A00D91E87F57E95B60EFEB9963425C951C00298F26A884C3AEF0DBF539D04E867EB6FB957E817C230DFEE3BE607B3FAC5DD39FB436C5BB7926D7FFF03EF787FF563C3FEF787919A8383DEF3142B9927BEAF99BCFB066319F5BDF2EFFB11686607A73BE9CB85CF6EC52D0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h420539B476E305B8200E47DFAAE8D5D1D0724DCC3FD72C4F8DE54622A1DD1BA78CA3CE9F24BEFA9E2BB9D89B423C327C8E050114401A62FDCD2054E166C0005F7941B61372AC884EE60A372057B59CFF30A6020B875C06E7C5FBDF9A91F8F0588ED67F67AA66B0674CD240410F613700B8DFE7F8837F88FF4520002E4BFD7FA2768008002000002624793100811F43BC315A6004052671392B47FEB7F5DC90E62175C7B8FC48FCC916D46F9315DFDECBE43E5F03D7D27F97E09E4700AA694552A1FF3BE5E159FFDDEB2FBECAEB87BBCC5FCF6E23D77E4DD4C9DEBC93C10F636326FAFE3BE30DFAF7B9E7A5FFE44BF314DAA1C1529CDBFFE9D94EB11A9F68D4DF; +// synopsys translate_on + +// Location: M9K_X33_Y18_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h7BBD7F79FFE0AB8FC33758D1C1145DDD6311CF69FFFDF62EDD236FC6A0358FA2B4B15EB89456517DFF58F68BDADB95B5F764CAE7E7C7E7D70CADB8FFD8F9A72BFBB9EB400590D7F939FF5A70A29817DC2CC29B679B2D7146BD21D47EF06F7D5EAF72F66DC666B0726D66FD941AD9BC6D758D5EC24DFEBA64871D6B86D37DF1DFBFF05FBD6AD8CA62C6CBE43BDBFD99E9EB6DD724D235FBEA9FE7D6767D811C40681A00AF8D864D8BB6D2A0916C8A93250A76B8A977F82E8FDFBE68F8E0F8DF237CA976FE488D1069D687A6F1D68A70F37CAAA367A74CBB75D3A6FFB4B1E8D4B7F7F22D2FE1509BDF80E6DD7B717D7E9C6531C3A86BE9F1D7A6AFD5BFB7A37A60; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h8AB3B7FDEE7B9CC735FCCE93E3AC1AAAA691AD6350E57F1F5773302B6F36F63D130E0574D6BB44B2C0D7A907702A748D0BA50F8FA5437ACD3B343C35039F44D19CD4E55E6CB00410842B02A7FD105706DF9E2A1FA025005632A0CC080400D280CCCA0665222D038CC873351A21B23939A98CC08803282189C8440D40CD40462421A40982C046D22C10146484345CAF7BC828BFE79DFBE3C631CBF660C487EBB759BD7F8DE9E0F27A65DE5245BEB8F7829C36F0D136168F97C2BD77D649A39EB4DDB3A42AC80797FDEF4DE3EEF7ED8C7307E4CE6A6317F7BF25D077BBF03AEA3363B065F7D671322D6BFB2B8759433929CEC27E3FD7741292A4A5AF02703CC4E3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'hFD5CB07B6C729B510A78BEC5F7C7A1E7809F1976D0DD3615C1D27D2DF596BFE7A8BCDC2E6655185CC45008B39EFD1FA6E9F5E816114F93E1E7A2A27C72C7349F3497229CB9044B6E7A7861A04A712AAF29EFBD393727F1F3FC2AA1E6CF571457F0A09C47F23F20FE2AABF5FD3ABE6167E5FD36E1D9735BBD5375C1F79BD0424ECF133BF47B9D3DA46DD6DBF3A8ADCDD3DF1176D2FE23447DFC65E1DD7BF3BE5E1C9DCD8EBB9D36AF570CF25CDD16F645D1DE9F9EE575E3A2B91D5659FC131CE3DCD4560015805B13AC0290001EF8261B7E4EB867C828D9777FFF47B6903008DDD7D77EF5E2C6D7220BE64B3C6E9EF22AFDFCC8005C2FFFFA3AB9AD1ADFC0AFE7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h06ABC52D5DBEF57EEB3311A9D85D253B44E250E1566BED57C6DBEB2ABFD1ADF6FF4DEBFBDEB376DF68D5EEDB5EB4D5AB5B79745D76CD8ADC59CB30C8AA33E1551D2FCA8DCB43C5356BAE638588C302868CE1161CACADFEF7696F8C3AA82EC16F47A8EA413A2DCF09B996582318DBF3C4711871B3BC0404EC45252A485234A663C1FFFB3487617BE24FD79501DE05F1A341B89EC82FD5702497FD866639C0DE08B383E6E7C3B310E1F7FF595C5DF6F0E9A9FFFBE16D3FFBE82C1E0051F1E060D500812F408CC6501331852531B04480021D9220D4903A41404312032840153FE9CC8070206B8245AC240020752EBC2BEF3E74AB288F360C239C4AFAE93F68775A; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N0 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout )) # +// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datab(gnd), + .datac(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3 .lut_mask = 16'hAFA0; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y18_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h35861A00A6112A1481AF1A50A6004A05291627227FF08229B87389E08119A28A7888672DC999B7046A61E60810A7434450E3D33E330F321A18E8A120D1EDC8623DA2C64840C2CCE811522B42008095E5A456C98F4B25EAEA410610545024640CF10410AC463BF9349074917E9A74A12830EFA280EBD3131E484A255D0191C6852730A263DBCCAAA88712242B3BE49AA5338990229B391158C726BC7EB4ECC32308980020680249882691A680488292310B4313CE87FFCD5329A64B708CAC8533316412C4900F646A36630261DA093053D98F19D2C5B653165D4A71AA5682B29B89B6054CC727D292805705A93268676A31111371390B240EC3CC85D331813EB1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h1AA1C248D293110CB951445117D9B6AA500F65068B8CC508BD00184F8705B010A0CC46CC9302649242CE08191634113154562B149100204551178DE805D98EC8A2E5A64B241400267194CD524499BC01D31058CD18684A817A5800B65143281C1310B00A49902C0104004C654E0582040001103654011012021912281216B000C653A0510A1B00C36AC88058CAC126E14E198DFB07E81C3F41510BB08F8F851C3B9AF0147BC1F730B4E91D9D11C3A8F1B82DF19988ACC44072FDB17B4D81882E9DD952B29003D7767BA581A68BC41C2B16AD6EB57F1D048CD4E464190D25ADF2C194E3598360AFB031A1690F4625BB628363B4C90A400E3A04DAA70DA0CC4776; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'hC82B30671933680037A65978674DDEC2D30EEEDA78F5F2A1DEE660FFEA11B175DCB42E9277212A58842051A078007109A0D820166B881042600284403143048295D23A0E191EBC2134B833D53D37E42B05018289A10300A188E315CE98640F548A370D60A0AA3E7288A0B0869FA5E703D1AE17C0EC276B2AFB747B550A8B41021620D1A60A901095D12A0973B95E20838001330138951361967847D42901910A3488480610A91A851E84FF08783F81AEA52D2FDC2200BD2FE81C0357FBEC1D875686C6CA41B2224C88D8456C1DBF20D820A6649774CB11B69933246E9739C998470542C2E3C783A4C24767084C52DC209D60E95DBC096D9A0171A12D5AB99BAB; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h17A24D2C636ED2478B5AE1C99D40761B1E7AA6A89DDD1BBD8DBD223E70531BCDE90C8E38C8E0478AD8B388F94891C9673A50BC32478E083074657E8E0EA53BEE861F8BC1993560946D92D1C0C7F046A245B5849CB751FF15B97FCD50BC7B8524C13E7C640F3645082248D1CC14296E30DEA3057B35C641762CD00D40DABC27472251A60725008AAA056591C4000BB48C0BC29B8034A03400027B84769B520D9196968460CA3388A03ECB45F2C4B70F1829221000FFFC7FEC346F079F13079798EC2A08157331C6CC0E30884244916A0DE26D4D22454091290404A492016887E2111F830F9851184101370588A06D3BF9AE621A5F4E632A6799C83EFAAE06769D; +// synopsys translate_on + +// Location: M9K_X22_Y17_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'hA50276000854A0103840403E540424244404783E18807A08A47C54484448544A807E7E10005270182040407E4A1252124208084008404208420A4A42424A125A024428106448524A624A4A24425242522060108010543C00044A105424005E0031ED1E0529E507AE2F6FF1CD51D4C772A648E65F6532C28022061303F06C36CDBD319B55CB8E626C20E46C93C1463A0B1CE594F0ED3B62330C104DECE46CA6CD966B1386612C7B43980349408F36FB64C14342DAE26CE4D8D5E791388729D743B09A27AB81D71A14AB3D24E385B602248476D00249239514B58D3098504ACD119B99E9021B650A69494C22600667473128DA5010D2195982823226DED0ADFCB8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h5861917919344A4685CC0990862A11324792E761B6D41C0FCC0838C1C27211A2453FDC2219C225E421B320085A8FBFD0C42135B16448DFC226E09B3438A740C352979565817114DE46462844A57F7958873FC4B255C8AE549BDD1A87415D5018F88D5002628FFD13203066C850F10649F21319109208387641120B362124803F0678522BA2812C1454A502ED1A59CBD76A034756F5765DF7555F57575F7F57FFFF7FFF7D5712524D4A30723514B2B3064A84B4742D48415281863DDFAA9D9B7E7BB16DDB96B7845371C30B55DB96C8F6EB4B453242FF6A4DF84A76B5AEDC88A68DC6A06905054C8C36E4199E74638E6532965218A965909BA456000451343351; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'hE2975A2686A7AE0288F140141B698E2A82A835F478453A1D722CFCED12859FD735188757AC5A42DEB501FE010586249AC1EA60D08F74CFA5086EC78FC9190C056059E332C311521E6522901852D484B423A98816C9B26A08C92368E9FF05524502288A804612A2A0A102A418CBDFBA554499541660F8124640110101263142892A086B442661015380041594608092D9CB919250100A37DDA3919A1427F660963C251301FB2CA45562245308885131119115C652B2493252340201101942D26000CC60799124A8520C08050122171281808058018C38A645D07931896B39ED259A22242CB58413089465B246231330D806105010035100B08761A08506094160; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N20 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ))) # +// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout )) + + .dataa(gnd), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4 .lut_mask = 16'hF0CC; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y15_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h990442000864A0284030400454782424440404007E404808A4005448387E547C8004420800620824402040024A1242124204044008404208420A4A42424A1242020028008000524A024A4A284252446240001000101042000054265C7E0600007FAF5CA001C181BE0C02418447B1D88BAA85409896BC7C0E5FAC2529CB69A4038E2564731F88FE730045956C357C5ECF7EF8591DF2A8ACFFBFEEF268CD9B51238594AF691A9B8640983B7F76AAB97209EA6257389992FFE684926E0B19FA338B8489D73811171D5C9FF3DCFFFFFF8002000780101F3F4035A0CDED99F79A4775854F179F7D7DBBCF81B2F6421FF684CA6AF85894D29B9D3ACCBA3F27D9DC9911; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h5B438D714D4E3DD115E8BD1286EAB5FA1D71BD8F4508BD4BDC8838F9D27B552259BCEFFBB68A6FF529B3B0D92970010BBB6C7D872421210E190E1CCC47A485EAD2F8735647315839EF6F683C64773FC73464D5FE354936D50823A5DAEBEBDBCC6CAFF2622B8D518F63C6030424188FD357718970D25A30CD0731E532DB23002D02C12B12378356DE2C52041CA7A320C51E0D7CA9F5D575775D57FD75DDFDF75FFFDFFFD75F145247F03A0AE7F1E1EB2D5A99D2444108C6A5979B7CC26ABCC241EA4C912568003BB493CE04FF086C188980052BF6ABAAA2FD5D658000011277EB924C10EFAF3CB9B62486512344C61ADE6F15AB67F335A52513FF05AFAEEE8400; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h0C840083AD485153ACD3C035591630199B8C096CE4DC557D6D55FCCD738573D6E0948817C496E9DE8EA1F88F627B7460106691CC452DB9799E59A5D003733C4EA1BCE33AD2D8BE40A4E5BB7D7BBEC2CEADBBC8B6F87A4A56FBE0B891DE57E4C64EF9AD87727C49CFE7C5DE942B72AC7F6D97DE18920777FDDEE9EB11122A4E18F5569FDE08906765428FB9E6F89FBF0DEAA6064637BCA63FD02E273E5557F0548662C97BC2E8D3FFDB26D23E87BFD97E635A6560CFD93F8EED26E30C70DE8633D6B97C86DF7D9BEDFB99E36B6658F16C6DEFBDD5DF728D6209C852C37FE67CFF32EE4CCCECC64F7E6225FC99EC64C3B6DD7DED0FD7CCEA3BF09A006ECDD1009E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'hA9C9CE3AECF7BE27C000000A8ABA95251B309A60B9DDC19EC3E391458CBB53CA00A85E3C5AAE2C49DDC2F6C7B013DACB319A769818A1081A7389F711D76A09BCBED23D9A99FF9B77183697955D76BF0E0008822742DA45B883C9193DAF09424501859565800698515E10A8189EE9B323E35CE7388D73C6E7A50D0DE6739C73AC538D134115D860ADA57B5B868E54393B1E31E762062577697D57E8464340420E9434CCA34CC9A1CB1FAACC56168071EAC113F5265D5F6A45A098D604A820508C4EA47F9A7E46083716911B0D585CE937B530218E8D2AD3777EE7D3B4BC56C29ADB46809D15D185F8809229B150C29C8081174CA6173B99703DA466629005C604; +// synopsys translate_on + +// Location: M9K_X22_Y13_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'hE10F8B8C100323720BEBBDEBB81DF13FF97B252E2CB4F27BA091FBD0002D1A611E1EDBBC716D44D2912B80041C44558060CFCF15955C0D780DD5E71393920844F25E16C87C5D0308EEC52C011514BBC13AFA1028924D0C7CE738105BD47A10AA5B5C1D9D4193E4339F492B0E1A64E13AE35BE6B67AC8057BDACC155F14E906A017A1841358335450D4B26CD2A21B3D8F2211080B81EC040D7FA0B51CD48008112508062020A02490900092D2040259108806A328F4006D2AA514B42FB006ECCCCB9A360865678449975A8AE72B5C0F7BA800C1B5DC55D7D6FE2EF4EED85D00AB111821321BA426A4FE4956B43595832C271E83E060341AE5F2023FC808177383; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h1A2955372D510AC266A5445146E27000020C320FAE1557E37154040A13202DC6F40B840FB9A59B6DBB296562CB6220EFBE99D2776A202044D9101006FD221D305519198C859000004012AFF4FB060307C92BB732203BFDFEFFFFFFDFFF87FCFFFBFFEFF03FFE0FFFBFAFE0FF80787FFF7FFF83F7F87003FFBFFFFBFFFBFF0FFC0FF81FFF7FFBFFDFFFBFFFE1FF0086F3141AAB6005810A0621595A893F9D85983B9254954341968BAC8C141C90938C05B2C9CD267E11650407375FEDD6A2FEB346AAF6CFDC0791AA97B741995A3B3981E06D1A44D3711955197BB9910FCA20744915C84D6C24BAF53929814CA8A4697E8F4201145AE7415DC122A5F010436107; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h02E84F969E3C800AC610D276182020227809001A50DDDBA3487BB6AE802BA06509312DA0E620656EAF24D57C08FFB14D289613DC32083803B84DC6415FD5EDC000300A8D128FA20030ACCBAFA237B7024504D36A4BA26081137F059E78991154FE2AC2A884A8CC7FBBB21C851CC92B12E15593C0C020FFEE066558590E882D5B67459F1A8C3240FE4E6A8D028C0C088FCF471D400A19B38211004DD122212288B111114514CB11840E04828849C621392041163C00808C67223422F00110201DD18FCFFFF3FFE7F9FFFFFFF82C0B422D214711E08904524A069491774E663F48F665955B4E2C63DAC0078652D10120900298F7EE380092442AFD400BEC43C003; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'hB5D49EA9D7036A45AA9E870B8E8016720C7C3102AE925262492C84584942D209042216E0216C85B8912250B7157D5955AD406CB685BBF071B47D5193363C1CECAFE59E91BF11498940A0944996D47EE8D7E3A4EAE611AE19A965D01BA86B55E9C52A6A379A382C6C265FB0DA01396D0800C0046405C06F466DD18C4DD7655CD4E7622EC485808C841D64B737041FF68813B149A41531A0A692FB14AE2E5B49D49CDCADCF90E7BD88125BCE706BF6D04AABFC1C001163DC6EFF7FD3230303030000000000000000000008400000000000000000000000000030600000100007E00220000000000000080040004023AD496997B8C0077B886EEF161CF2298A091B; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N20 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # +// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ))) + + .dataa(gnd), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5 .lut_mask = 16'hCCF0; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y16_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h4200420000441C443C0C3C00480018FC387C7C000000007E180038300000204880084204004204423E1E3E02247E3C7E3C7E7E7E7E30007E3C7E7E7E3C7E7C3C0400000000000C34023C2E302464003C00000000000000000020460024000000FF991E65536D2D8D9C9B4DB081C83A5A881B0DFDE2D72DF0FA08FCD6F664173D989098D02025E0F6043B4B9080F4923880C3A3B02D269E730C3DCC423386DCB98B4AD0C5C8D6119602E5121008325B7457090E914F4876EC8A18C664210A4C2392C7658400073421047C75FBE7BE73FDFFF05FEE07BF8AEF7F1378B359E8C61F8F692C2218C98A4A8748531986E7C770D984E0000C02060C000C0DF50F68A580; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h0100046606572583002086010800054C0F2DE8371AC0000A9003E024840C7C0806F6612D770080980A40D293FEC069F16CB2164CA033C539F69B37741AEF1CE3662FF5DF9CB107BB23A39EF7B95E7372200448DBDC18F9C0DE0EF379BF49480657781E91788044213E091339886F337D0612CA646CD48FC58EE77EDD7ECEC466C744FD00E1A7F9E9FBFE4777FD50ABD11F0E57FF4808802282200888A20AA88000000008800AC11D556264251ECFA68C056FBCCB040C614A6850222300D2F6FF59F878FCF5689FCFEF34BFD52FA2422A56A3C113409F7813007F8D6B5F80FE9D7FB1E62675F7C2CBE01032DCA16BADC570C1CBF7ECBC4E7E6C54A5D4550BE1A8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'hE33CB578DEBFAFAEDFD530DE8FA1992072F31B116644B18C72F9F44116C79ADF2F3982C7BE09AD4A32196807648A2495ADF98FD2B16CC096A5E25F5BC811C953CEC3000F432029B3FE3F211712944CA54D1940F193204C199C9F49666CC11B38C23B9D130CA49818913D3A2C1FBF71C5B0C774336F903C677D976189D98CA127AAAD6B6AF36195DA637C6EFA3E36E8FE97FA02EC26EB46198AD8DAD8C11260AF499D7BD86619EE5574CD27C80D39F71E653FDCF1B366737233CBB98D1E7B330F7DCCFC5939C4EC79CF0E1CD43BA7AFC716900A21BDB9DD0FCC7ECE1063238407C7E1B221EA10E38F64EF31CEBF3368E1C712BB1B33781134CFE54C2123349A6E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6; +// synopsys translate_on + +// Location: M9K_X33_Y19_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h3C766E63DB6481CB39BC8C68831C724633186CC1BAE9D608A5DEF0FF219C28C1EFF4FDE394D0E19B6FD89186C23CF071E6F1CC8F7FC4F1E48756B0DCD8ED6D0C3DA139003D7A86B2F878DD99DAFB70DE1A19F3FB7DB3B8EF2633007664CB19992E43664448EFF06072648DBA32EDB76E26439BCCEF2DFBF664594B04FBAE72A84A3E508B49DC6BEAAB4F3F0CCCF6D8F568F2DA00EB384A7F53249323198000100408002024010408824080002008011482ED5615E40012EE630C3B2CDB2C13A736DB5B7BD2850018CF936621C6863095A73F7BE7442CB13110B9C0BBB96EEF16CE618EEDCFB393738178C476C367909F71307F6803F677575763DB2D8C3118E4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h881331ED7AC4EFD38DFACDBB236790005719AEA2FAECCF0D126A30A27222D61BBA428334561F4EDB60C6BF8DB6E267BC56CB69BBCE636CCCB3B2B4B103CC46D5CEEC06DAECB0001569589D5F267AFE086C8FED5DE41DFEFF027DFDFF7FFBFBFDFFDFFF6FFFBDFFDFFF57FF7F7FB7FBBDFBDFFDBFF78FFDBFFEDDFFFDFFFEFF6FF7F7FDDFFEDFF6FF7FFEEFFEFEFC4E51EC0888848E1F2044B47B66608D8A3B3919B9466E6D60D27565964244B218B48AD83430D996068EC908D9E112096996041D77401A0C0CCF5DEEE561F7F7E68CBE72E48E570B047C772CBACC33753080E32EB0B348C0B62337739B1BC73192392592C84E37B7AC141CFE65EE76D83C9083; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h1C5CF062CA6F13854A59BDEEEA07E3C6559EBB3618111895CBBACCBCD512B5F07D361CCE72B925658DBE1F7C4707E195C5C665B8118C3C31B196C261DA85A5E11889D25CB816ACC6627802052C61A4099B7B0EC923971DB3B9F9204BDBCCFA457EE296E8986E64C6DC99E59436641567648CB84DEB7D7937F974F038D838274F3D3CF1BE8C84DDB000565880A776E5C0E13166E49F47119A4CA1311CF97B965E7CBBCB2CB384BD0D92ED105D0617856E80441124B31DE58B8C001607FEE668899693E3EFF8FBF1FCEEFBCF7CF9BA6C37640DDF7FFE6187B19ACF089D4C038F6607B78D38001FE67E56CCE399DE36D7DDBD699D5CFC5B6D7A1421CE06FE40DB6E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h0776C62C316FF94B0BC3A0288DE6A62B14D6C1A2DADF9BDF85B2CCB02CE1DB2D96632C3232C3974CDC1172E1779D8C6738251819975DB8146067301E0C0277B6B657485DCD62AC0662C8C005DDE7494C9CA13AAE3234BB0EE1B708A23A2F48AC4C3838641E940620F9CDDCCA14BCC07104C112BCC9032C48E925594CB886A604C9F7627EB100872A52FB5141D65111E6C8DA0ADB6CEC6004461D0E366B20DCCDB607E624499300E4DF6D95CB62F62FB75403E400EFBC3BD34080FC9CDCFCFCFFFFFFFFFFFFFFFFFFFFF7BFFFFFFFFFFFFFFFFFFFFFFFFFFFCF9FFFFFEFFFF81FFDDFFFFFFFFFFFFFF7FFBFFFBFDC0A6DBE6F8BE5BB7FE7A39B3DA3F3BE13B679; +// synopsys translate_on + +// Location: LCCOMB_X32_Y19_N0 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout )) # +// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datab(gnd), + .datac(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6 .lut_mask = 16'hAFA0; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y14_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; +// synopsys translate_on + +// Location: M9K_X22_Y12_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N12 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ))) # +// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout )) + + .dataa(gnd), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7 .lut_mask = 16'hF0CC; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7 .sum_lutc_input = "datac"; // synopsys translate_on assign LED[0] = \LED[0]~output_o ; diff --git a/simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo b/simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo index 7414a00..9b80f0c 100644 --- a/simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo +++ b/simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo @@ -29,7 +29,7 @@ (DELAYFILE (SDFVERSION "2.1") (DESIGN "spectrum") - (DATE "03/30/2022 12:38:42") + (DATE "03/30/2022 13:12:28") (VENDOR "Altera") (PROGRAM "Quartus II 32-bit") (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") @@ -41,7 +41,7 @@ (INSTANCE LED\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1355:1355:1355) (1339:1339:1339)) + (PORT i (1643:1643:1643) (1694:1694:1694)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -51,7 +51,7 @@ (INSTANCE LED\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (1409:1409:1409) (1443:1443:1443)) + (PORT i (1565:1565:1565) (1603:1603:1603)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -61,7 +61,7 @@ (INSTANCE LED\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (1823:1823:1823) (1829:1829:1829)) + (PORT i (1737:1737:1737) (1749:1749:1749)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -71,7 +71,7 @@ (INSTANCE LED\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1455:1455:1455) (1423:1423:1423)) + (PORT i (1124:1124:1124) (1166:1166:1166)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -81,7 +81,7 @@ (INSTANCE LED\[4\]\~output) (DELAY (ABSOLUTE - (PORT i (1759:1759:1759) (1776:1776:1776)) + (PORT i (1456:1456:1456) (1512:1512:1512)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) ) ) @@ -91,7 +91,7 @@ (INSTANCE LED\[5\]\~output) (DELAY (ABSOLUTE - (PORT i (1337:1337:1337) (1367:1367:1367)) + (PORT i (2115:2115:2115) (2173:2173:2173)) (IOPATH i o (4477:4477:4477) (4127:4127:4127)) ) ) @@ -101,7 +101,7 @@ (INSTANCE LED\[6\]\~output) (DELAY (ABSOLUTE - (PORT i (1855:1855:1855) (1871:1871:1871)) + (PORT i (2428:2428:2428) (2433:2433:2433)) (IOPATH i o (2455:2455:2455) (2378:2378:2378)) ) ) @@ -111,7 +111,7 @@ (INSTANCE LED\[7\]\~output) (DELAY (ABSOLUTE - (PORT i (1469:1469:1469) (1548:1548:1548)) + (PORT i (957:957:957) (1031:1031:1031)) (IOPATH i o (4477:4477:4477) (4127:4127:4127)) ) ) @@ -134,29 +134,12 @@ ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[20\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~0) + (INSTANCE counter\[0\]\~63) (DELAY (ABSOLUTE - (PORT dataa (243:243:243) (330:330:330)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH datac combout (353:353:353) (369:369:369)) ) ) ) @@ -165,7 +148,7 @@ (INSTANCE counter\[0\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -176,15 +159,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~2) + (INSTANCE counter\[1\]\~21) (DELAY (ABSOLUTE - (PORT datab (242:242:242) (324:324:324)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (253:253:253) (345:345:345)) + (PORT datab (251:251:251) (336:336:336)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) ) ) ) @@ -193,7 +177,7 @@ (INSTANCE counter\[1\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -204,11 +188,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~4) + (INSTANCE counter\[2\]\~23) (DELAY (ABSOLUTE - (PORT datab (242:242:242) (324:324:324)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT datab (251:251:251) (336:336:336)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) @@ -221,7 +205,7 @@ (INSTANCE counter\[2\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -232,11 +216,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~6) + (INSTANCE counter\[3\]\~25) (DELAY (ABSOLUTE - (PORT datab (242:242:242) (324:324:324)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT datab (250:250:250) (335:335:335)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) @@ -249,7 +233,7 @@ (INSTANCE counter\[3\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -260,12 +244,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~8) + (INSTANCE counter\[4\]\~27) (DELAY (ABSOLUTE - (PORT dataa (386:386:386) (458:458:458)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (250:250:250) (335:335:335)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -277,7 +261,7 @@ (INSTANCE counter\[4\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -288,11 +272,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~10) + (INSTANCE counter\[5\]\~29) (DELAY (ABSOLUTE - (PORT datab (380:380:380) (452:452:452)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT datab (263:263:263) (346:346:346)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) @@ -305,7 +289,7 @@ (INSTANCE counter\[5\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -316,11 +300,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~12) + (INSTANCE counter\[6\]\~31) (DELAY (ABSOLUTE - (PORT dataa (386:386:386) (458:458:458)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (PORT dataa (252:252:252) (342:342:342)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) @@ -333,7 +317,7 @@ (INSTANCE counter\[6\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -344,11 +328,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~14) + (INSTANCE counter\[7\]\~33) (DELAY (ABSOLUTE - (PORT datab (380:380:380) (450:450:450)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT datab (250:250:250) (335:335:335)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) @@ -361,7 +345,7 @@ (INSTANCE counter\[7\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -372,12 +356,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~16) + (INSTANCE counter\[8\]\~35) (DELAY (ABSOLUTE - (PORT datab (240:240:240) (322:322:322)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (251:251:251) (341:341:341)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -389,7 +373,7 @@ (INSTANCE counter\[8\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -400,12 +384,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~18) + (INSTANCE counter\[9\]\~37) (DELAY (ABSOLUTE - (PORT dataa (242:242:242) (328:328:328)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (249:249:249) (333:333:333)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -417,7 +401,7 @@ (INSTANCE counter\[9\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -428,12 +412,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~20) + (INSTANCE counter\[10\]\~39) (DELAY (ABSOLUTE - (PORT datab (239:239:239) (321:321:321)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (252:252:252) (340:340:340)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -445,7 +429,7 @@ (INSTANCE counter\[10\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -456,24 +440,34 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~22) + (INSTANCE counter\[11\]\~41) (DELAY (ABSOLUTE - (PORT datab (388:388:388) (452:452:452)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (704:704:704) (765:765:765)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE counter\[11\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (318:318:318) (335:335:335)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE counter\[11\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -484,11 +478,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~24) + (INSTANCE counter\[12\]\~43) (DELAY (ABSOLUTE - (PORT datab (382:382:382) (451:451:451)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT datab (248:248:248) (333:333:333)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) @@ -501,7 +495,7 @@ (INSTANCE counter\[12\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -512,11 +506,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~26) + (INSTANCE counter\[13\]\~45) (DELAY (ABSOLUTE - (PORT datab (387:387:387) (451:451:451)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT datab (249:249:249) (335:335:335)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) @@ -529,7 +523,7 @@ (INSTANCE counter\[13\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -540,11 +534,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~28) + (INSTANCE counter\[14\]\~47) (DELAY (ABSOLUTE - (PORT dataa (380:380:380) (458:458:458)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (PORT dataa (251:251:251) (342:342:342)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) @@ -557,7 +551,7 @@ (INSTANCE counter\[14\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -568,11 +562,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~30) + (INSTANCE counter\[15\]\~49) (DELAY (ABSOLUTE - (PORT datab (387:387:387) (452:452:452)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT datab (251:251:251) (335:335:335)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) @@ -585,7 +579,7 @@ (INSTANCE counter\[15\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -596,12 +590,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~32) + (INSTANCE counter\[16\]\~51) (DELAY (ABSOLUTE - (PORT datab (379:379:379) (454:454:454)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (253:253:253) (343:343:343)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -613,7 +607,7 @@ (INSTANCE counter\[16\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -624,11 +618,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~34) + (INSTANCE counter\[17\]\~53) (DELAY (ABSOLUTE - (PORT dataa (388:388:388) (458:458:458)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT dataa (253:253:253) (345:345:345)) + (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) @@ -641,7 +635,7 @@ (INSTANCE counter\[17\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -652,12 +646,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~36) + (INSTANCE counter\[18\]\~55) (DELAY (ABSOLUTE - (PORT dataa (386:386:386) (458:458:458)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (252:252:252) (338:338:338)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -669,7 +663,7 @@ (INSTANCE counter\[18\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -680,12 +674,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~38) + (INSTANCE counter\[19\]\~57) (DELAY (ABSOLUTE - (PORT dataa (383:383:383) (460:460:460)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (252:252:252) (338:338:338)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -697,7 +691,7 @@ (INSTANCE counter\[19\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -706,42 +700,15 @@ (HOLD d (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~40) - (DELAY - (ABSOLUTE - (PORT datad (218:218:218) (287:287:287)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE Equal0\~5) (DELAY (ABSOLUTE - (PORT dataa (210:210:210) (257:257:257)) - (PORT datab (208:208:208) (249:249:249)) - (PORT datac (181:181:181) (219:219:219)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (174:174:174) (200:200:200)) + (PORT dataa (254:254:254) (346:346:346)) + (PORT datab (252:252:252) (336:336:336)) + (PORT datac (225:225:225) (305:305:305)) + (PORT datad (226:226:226) (300:300:300)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -754,10 +721,26 @@ (INSTANCE Equal0\~0) (DELAY (ABSOLUTE - (PORT dataa (343:343:343) (371:371:371)) - (PORT datab (336:336:336) (366:366:366)) - (PORT datac (312:312:312) (338:338:338)) - (PORT datad (318:318:318) (328:328:328)) + (PORT dataa (253:253:253) (343:343:343)) + (PORT datab (250:250:250) (336:336:336)) + (PORT datac (224:224:224) (302:302:302)) + (PORT datad (225:225:225) (296:296:296)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (344:344:344)) + (PORT datab (251:251:251) (337:337:337)) + (PORT datac (381:381:381) (440:440:440)) + (PORT datad (225:225:225) (297:297:297)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -770,10 +753,10 @@ (INSTANCE Equal0\~2) (DELAY (ABSOLUTE - (PORT dataa (375:375:375) (396:396:396)) - (PORT datab (637:637:637) (652:652:652)) - (PORT datac (334:334:334) (353:353:353)) - (PORT datad (562:562:562) (570:570:570)) + (PORT dataa (255:255:255) (347:347:347)) + (PORT datab (262:262:262) (344:344:344)) + (PORT datac (226:226:226) (308:308:308)) + (PORT datad (228:228:228) (300:300:300)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -786,10 +769,10 @@ (INSTANCE Equal0\~3) (DELAY (ABSOLUTE - (PORT dataa (203:203:203) (247:247:247)) - (PORT datab (201:201:201) (241:241:241)) - (PORT datac (174:174:174) (208:208:208)) - (PORT datad (175:175:175) (201:201:201)) + (PORT dataa (254:254:254) (346:346:346)) + (PORT datab (253:253:253) (339:339:339)) + (PORT datac (225:225:225) (305:305:305)) + (PORT datad (227:227:227) (300:300:300)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -802,10 +785,10 @@ (INSTANCE Equal0\~4) (DELAY (ABSOLUTE - (PORT dataa (612:612:612) (640:640:640)) - (PORT datab (820:820:820) (843:843:843)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (305:305:305) (321:321:321)) + (PORT dataa (337:337:337) (370:370:370)) + (PORT datab (345:345:345) (370:370:370)) + (PORT datac (335:335:335) (354:354:354)) + (PORT datad (589:589:589) (601:601:601)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -815,14 +798,79 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[0\]\~0) + (INSTANCE counter\[20\]\~59) (DELAY (ABSOLUTE - (PORT dataa (601:601:601) (619:619:619)) - (PORT datab (378:378:378) (401:401:401)) - (PORT datad (189:189:189) (221:221:221)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) + (PORT datab (264:264:264) (347:347:347)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE counter\[20\]) + (DELAY + (ABSOLUTE + (PORT clk (1898:1898:1898) (1920:1920:1920)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE counter\[21\]\~61) + (DELAY + (ABSOLUTE + (PORT datad (239:239:239) (309:309:309)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE counter\[21\]) + (DELAY + (ABSOLUTE + (PORT clk (1898:1898:1898) (1920:1920:1920)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~7) + (DELAY + (ABSOLUTE + (PORT datac (669:669:669) (728:728:728)) + (PORT datad (646:646:646) (700:700:700)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[0\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (663:663:663)) + (PORT datab (207:207:207) (248:248:248)) + (PORT datad (330:330:330) (347:347:347)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -833,7 +881,7 @@ (INSTANCE address\[0\]) (DELAY (ABSOLUTE - (PORT clk (1897:1897:1897) (1919:1919:1919)) + (PORT clk (1868:1868:1868) (1877:1877:1877)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -842,45 +890,33 @@ (HOLD d (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (268:268:268) (356:356:356)) + (PORT datab (261:261:261) (343:343:343)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE Equal0\~6) (DELAY (ABSOLUTE - (PORT datac (181:181:181) (219:219:219)) - (PORT datad (183:183:183) (214:214:214)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal0\~7) - (DELAY - (ABSOLUTE - (PORT dataa (364:364:364) (391:391:391)) - (PORT datab (207:207:207) (248:248:248)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (181:181:181) (208:208:208)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (595:595:595) (669:669:669)) - (PORT datab (216:216:216) (261:261:261)) - (PORT datad (332:332:332) (350:350:350)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (707:707:707) (763:763:763)) + (PORT datab (674:674:674) (730:730:730)) + (PORT datac (613:613:613) (625:625:625)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -890,7 +926,390 @@ (INSTANCE address\[1\]) (DELAY (ABSOLUTE - (PORT clk (1897:1897:1897) (1919:1919:1919)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (795:795:795) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[2\]\~15) + (DELAY + (ABSOLUTE + (PORT datab (261:261:261) (343:343:343)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (795:795:795) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[3\]\~17) + (DELAY + (ABSOLUTE + (PORT datab (282:282:282) (364:364:364)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (795:795:795) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[4\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (265:265:265) (351:351:351)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (795:795:795) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[5\]\~21) + (DELAY + (ABSOLUTE + (PORT datab (263:263:263) (345:345:345)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (795:795:795) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[6\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (266:266:266) (353:353:353)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (795:795:795) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[7\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (266:266:266) (353:353:353)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (795:795:795) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[8\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (264:264:264) (347:347:347)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (795:795:795) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[9\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (264:264:264) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (795:795:795) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[10\]\~31) + (DELAY + (ABSOLUTE + (PORT datab (264:264:264) (347:347:347)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (795:795:795) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[11\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (264:264:264) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (795:795:795) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[12\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (266:266:266) (352:352:352)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (795:795:795) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[13\]\~37) + (DELAY + (ABSOLUTE + (PORT datad (258:258:258) (327:327:327)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (795:795:795) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (428:428:428) (485:485:485)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE rom\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -901,39 +1320,20 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[1\]\~2) + (INSTANCE rom\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (597:597:597) (670:670:670)) - (PORT datab (381:381:381) (404:404:404)) - (PORT datac (574:574:574) (583:583:583)) - (PORT datad (191:191:191) (224:224:224)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[2\]\~3) - (DELAY - (ABSOLUTE - (PORT datab (398:398:398) (468:468:468)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT datad (220:220:220) (290:290:290)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[2\]) + (INSTANCE rom\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) (DELAY (ABSOLUTE - (PORT clk (1897:1897:1897) (1919:1919:1919)) + (PORT clk (1531:1531:1531) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -942,15 +1342,122 @@ (HOLD d (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1232:1232:1232) (1314:1314:1314)) + (PORT d[1] (1273:1273:1273) (1381:1381:1381)) + (PORT d[2] (1342:1342:1342) (1456:1456:1456)) + (PORT d[3] (1317:1317:1317) (1435:1435:1435)) + (PORT d[4] (1249:1249:1249) (1341:1341:1341)) + (PORT d[5] (1362:1362:1362) (1458:1458:1458)) + (PORT d[6] (1704:1704:1704) (1869:1869:1869)) + (PORT d[7] (1310:1310:1310) (1434:1434:1434)) + (PORT d[8] (1316:1316:1316) (1419:1419:1419)) + (PORT d[9] (1359:1359:1359) (1447:1447:1447)) + (PORT d[10] (1320:1320:1320) (1425:1425:1425)) + (PORT d[11] (1570:1570:1570) (1654:1654:1654)) + (PORT d[12] (1289:1289:1289) (1390:1390:1390)) + (PORT clk (1856:1856:1856) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1882:1882:1882)) + (PORT d[0] (1167:1167:1167) (1189:1189:1189)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1883:1883:1883)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1845:1845:1845)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1008:1008:1008)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1263:1263:1263) (1361:1361:1361)) - (PORT d[1] (1538:1538:1538) (1608:1608:1608)) - (PORT d[2] (1534:1534:1534) (1635:1635:1635)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) + (PORT d[0] (1152:1152:1152) (1246:1246:1246)) + (PORT d[1] (973:973:973) (1069:1069:1069)) + (PORT d[2] (1034:1034:1034) (1138:1138:1138)) + (PORT d[3] (1341:1341:1341) (1439:1439:1439)) + (PORT d[4] (1248:1248:1248) (1333:1333:1333)) + (PORT d[5] (1325:1325:1325) (1408:1408:1408)) + (PORT d[6] (1491:1491:1491) (1664:1664:1664)) + (PORT d[7] (1263:1263:1263) (1339:1339:1339)) + (PORT d[8] (1326:1326:1326) (1417:1417:1417)) + (PORT d[9] (1388:1388:1388) (1482:1482:1482)) + (PORT d[10] (1305:1305:1305) (1406:1406:1406)) + (PORT d[11] (1274:1274:1274) (1349:1349:1349)) + (PORT d[12] (1340:1340:1340) (1438:1438:1438)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) ) ) (TIMINGCHECK @@ -962,7 +1469,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + (PORT d[0] (954:954:954) (925:925:925)) ) ) ) @@ -971,7 +1479,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1858:1858:1858) (1885:1885:1885)) + (PORT clk (1858:1858:1858) (1884:1884:1884)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -981,7 +1489,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1820:1820:1820) (1847:1847:1847)) + (PORT clk (1820:1820:1820) (1846:1846:1846)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -995,7 +1503,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1005:1005:1005) (1010:1010:1010)) + (PORT clk (1005:1005:1005) (1009:1009:1009)) ) ) ) @@ -1004,7 +1512,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1006:1006:1006) (1011:1011:1011)) + (PORT clk (1006:1006:1006) (1010:1010:1010)) ) ) ) @@ -1013,7 +1521,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1006:1006:1006) (1011:1011:1011)) + (PORT clk (1006:1006:1006) (1010:1010:1010)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -1021,6 +1529,523 @@ (CELL (CELLTYPE "cycloneive_ram_pulse_generator") (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (956:956:956) (1072:1072:1072)) + (PORT datac (880:880:880) (883:883:883)) + (PORT datad (605:605:605) (612:612:612)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1457:1457:1457) (1535:1535:1535)) + (PORT d[1] (1538:1538:1538) (1599:1599:1599)) + (PORT d[2] (1565:1565:1565) (1669:1669:1669)) + (PORT d[3] (1248:1248:1248) (1294:1294:1294)) + (PORT d[4] (1607:1607:1607) (1738:1738:1738)) + (PORT d[5] (1904:1904:1904) (2043:2043:2043)) + (PORT d[6] (1250:1250:1250) (1306:1306:1306)) + (PORT d[7] (1340:1340:1340) (1441:1441:1441)) + (PORT d[8] (1887:1887:1887) (2029:2029:2029)) + (PORT d[9] (1230:1230:1230) (1303:1303:1303)) + (PORT d[10] (1415:1415:1415) (1517:1517:1517)) + (PORT d[11] (1208:1208:1208) (1273:1273:1273)) + (PORT d[12] (1256:1256:1256) (1338:1338:1338)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1875:1875:1875)) + (PORT d[0] (1141:1141:1141) (1128:1128:1128)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1500:1500:1500) (1594:1594:1594)) + (PORT d[1] (1355:1355:1355) (1470:1470:1470)) + (PORT d[2] (1591:1591:1591) (1703:1703:1703)) + (PORT d[3] (1336:1336:1336) (1417:1417:1417)) + (PORT d[4] (1313:1313:1313) (1422:1422:1422)) + (PORT d[5] (1595:1595:1595) (1733:1733:1733)) + (PORT d[6] (1268:1268:1268) (1373:1373:1373)) + (PORT d[7] (1255:1255:1255) (1355:1355:1355)) + (PORT d[8] (1615:1615:1615) (1750:1750:1750)) + (PORT d[9] (1326:1326:1326) (1421:1421:1421)) + (PORT d[10] (1812:1812:1812) (1937:1937:1937)) + (PORT d[11] (1293:1293:1293) (1402:1402:1402)) + (PORT d[12] (1561:1561:1561) (1676:1676:1676)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1875:1875:1875)) + (PORT d[0] (1207:1207:1207) (1256:1256:1256)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (626:626:626) (652:652:652)) + (PORT datac (877:877:877) (907:907:907)) + (PORT datad (1342:1342:1342) (1396:1396:1396)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1238:1238:1238) (1323:1323:1323)) + (PORT d[1] (1282:1282:1282) (1374:1374:1374)) + (PORT d[2] (1603:1603:1603) (1716:1716:1716)) + (PORT d[3] (1381:1381:1381) (1467:1467:1467)) + (PORT d[4] (1282:1282:1282) (1376:1376:1376)) + (PORT d[5] (1277:1277:1277) (1395:1395:1395)) + (PORT d[6] (1716:1716:1716) (1879:1879:1879)) + (PORT d[7] (1344:1344:1344) (1433:1433:1433)) + (PORT d[8] (1329:1329:1329) (1433:1433:1433)) + (PORT d[9] (1412:1412:1412) (1507:1507:1507)) + (PORT d[10] (1764:1764:1764) (1843:1843:1843)) + (PORT d[11] (1578:1578:1578) (1656:1656:1656)) + (PORT d[12] (1322:1322:1322) (1422:1422:1422)) + (PORT clk (1855:1855:1855) (1880:1880:1880)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1880:1880:1880)) + (PORT d[0] (1242:1242:1242) (1194:1194:1194)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1881:1881:1881)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1843:1843:1843)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1003:1003:1003) (1006:1006:1006)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (963:963:963) (1054:1054:1054)) + (PORT d[1] (1258:1258:1258) (1343:1343:1343)) + (PORT d[2] (1047:1047:1047) (1135:1135:1135)) + (PORT d[3] (1074:1074:1074) (1167:1167:1167)) + (PORT d[4] (966:966:966) (1059:1059:1059)) + (PORT d[5] (1239:1239:1239) (1332:1332:1332)) + (PORT d[6] (1463:1463:1463) (1631:1631:1631)) + (PORT d[7] (1262:1262:1262) (1338:1338:1338)) + (PORT d[8] (1053:1053:1053) (1156:1156:1156)) + (PORT d[9] (1100:1100:1100) (1206:1206:1206)) + (PORT d[10] (1512:1512:1512) (1581:1581:1581)) + (PORT d[11] (1273:1273:1273) (1348:1348:1348)) + (PORT d[12] (1313:1313:1313) (1405:1405:1405)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1883:1883:1883)) + (PORT d[0] (924:924:924) (953:953:953)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT datab (980:980:980) (1094:1094:1094)) + (PORT datac (902:902:902) (940:940:940)) + (PORT datad (596:596:596) (601:601:601)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (930:930:930) (988:988:988)) + (PORT d[1] (979:979:979) (1053:1053:1053)) + (PORT d[2] (1080:1080:1080) (1156:1156:1156)) + (PORT d[3] (1058:1058:1058) (1130:1130:1130)) + (PORT d[4] (956:956:956) (1028:1028:1028)) + (PORT d[5] (1006:1006:1006) (1083:1083:1083)) + (PORT d[6] (1424:1424:1424) (1563:1563:1563)) + (PORT d[7] (1240:1240:1240) (1316:1316:1316)) + (PORT d[8] (1625:1625:1625) (1738:1738:1738)) + (PORT d[9] (1086:1086:1086) (1162:1162:1162)) + (PORT d[10] (1042:1042:1042) (1125:1125:1125)) + (PORT d[11] (1300:1300:1300) (1361:1361:1361)) + (PORT d[12] (1299:1299:1299) (1370:1370:1370)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (PORT d[0] (908:908:908) (912:912:912)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1847:1847:1847)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (1006:1006:1006) (1011:1011:1011)) @@ -1028,4 +2053,957 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1205:1205:1205) (1260:1260:1260)) + (PORT d[1] (651:651:651) (711:711:711)) + (PORT d[2] (713:713:713) (781:781:781)) + (PORT d[3] (760:760:760) (830:830:830)) + (PORT d[4] (659:659:659) (721:721:721)) + (PORT d[5] (734:734:734) (814:814:814)) + (PORT d[6] (761:761:761) (832:832:832)) + (PORT d[7] (740:740:740) (819:819:819)) + (PORT d[8] (756:756:756) (828:828:828)) + (PORT d[9] (769:769:769) (847:847:847)) + (PORT d[10] (1226:1226:1226) (1292:1292:1292)) + (PORT d[11] (741:741:741) (813:813:813)) + (PORT d[12] (751:751:751) (826:826:826)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (PORT d[0] (642:642:642) (628:628:628)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1847:1847:1847)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (918:918:918) (939:939:939)) + (PORT datac (648:648:648) (723:723:723)) + (PORT datad (603:603:603) (610:610:610)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1471:1471:1471) (1551:1551:1551)) + (PORT d[1] (1529:1529:1529) (1590:1590:1590)) + (PORT d[2] (1557:1557:1557) (1660:1660:1660)) + (PORT d[3] (988:988:988) (1045:1045:1045)) + (PORT d[4] (976:976:976) (1062:1062:1062)) + (PORT d[5] (1604:1604:1604) (1749:1749:1749)) + (PORT d[6] (996:996:996) (1079:1079:1079)) + (PORT d[7] (948:948:948) (1026:1026:1026)) + (PORT d[8] (1601:1601:1601) (1742:1742:1742)) + (PORT d[9] (998:998:998) (1064:1064:1064)) + (PORT d[10] (979:979:979) (1057:1057:1057)) + (PORT d[11] (958:958:958) (1040:1040:1040)) + (PORT d[12] (969:969:969) (1047:1047:1047)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1875:1875:1875)) + (PORT d[0] (904:904:904) (885:885:885)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1219:1219:1219) (1307:1307:1307)) + (PORT d[1] (1255:1255:1255) (1323:1323:1323)) + (PORT d[2] (1279:1279:1279) (1381:1381:1381)) + (PORT d[3] (1279:1279:1279) (1328:1328:1328)) + (PORT d[4] (1603:1603:1603) (1733:1733:1733)) + (PORT d[5] (1603:1603:1603) (1748:1748:1748)) + (PORT d[6] (1281:1281:1281) (1369:1369:1369)) + (PORT d[7] (1245:1245:1245) (1325:1325:1325)) + (PORT d[8] (1600:1600:1600) (1741:1741:1741)) + (PORT d[9] (1266:1266:1266) (1335:1335:1335)) + (PORT d[10] (1838:1838:1838) (1967:1967:1967)) + (PORT d[11] (1283:1283:1283) (1373:1373:1373)) + (PORT d[12] (1245:1245:1245) (1330:1330:1330)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1875:1875:1875)) + (PORT d[0] (1151:1151:1151) (1179:1179:1179)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~4) + (DELAY + (ABSOLUTE + (PORT datab (640:640:640) (651:651:651)) + (PORT datac (859:859:859) (855:855:855)) + (PORT datad (794:794:794) (853:853:853)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1508:1508:1508) (1612:1612:1612)) + (PORT d[1] (1896:1896:1896) (2041:2041:2041)) + (PORT d[2] (1251:1251:1251) (1359:1359:1359)) + (PORT d[3] (1319:1319:1319) (1368:1368:1368)) + (PORT d[4] (1294:1294:1294) (1407:1407:1407)) + (PORT d[5] (1248:1248:1248) (1360:1360:1360)) + (PORT d[6] (1297:1297:1297) (1411:1411:1411)) + (PORT d[7] (1260:1260:1260) (1366:1366:1366)) + (PORT d[8] (1608:1608:1608) (1726:1726:1726)) + (PORT d[9] (1309:1309:1309) (1408:1408:1408)) + (PORT d[10] (1860:1860:1860) (1990:1990:1990)) + (PORT d[11] (1271:1271:1271) (1381:1381:1381)) + (PORT d[12] (1527:1527:1527) (1637:1637:1637)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1875:1875:1875)) + (PORT d[0] (1193:1193:1193) (1239:1239:1239)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1555:1555:1555) (1667:1667:1667)) + (PORT d[1] (1626:1626:1626) (1776:1776:1776)) + (PORT d[2] (1557:1557:1557) (1668:1668:1668)) + (PORT d[3] (1644:1644:1644) (1709:1709:1709)) + (PORT d[4] (1593:1593:1593) (1715:1715:1715)) + (PORT d[5] (1575:1575:1575) (1680:1680:1680)) + (PORT d[6] (1565:1565:1565) (1670:1670:1670)) + (PORT d[7] (1531:1531:1531) (1632:1632:1632)) + (PORT d[8] (1555:1555:1555) (1659:1659:1659)) + (PORT d[9] (1587:1587:1587) (1682:1682:1682)) + (PORT d[10] (1533:1533:1533) (1638:1638:1638)) + (PORT d[11] (1559:1559:1559) (1667:1667:1667)) + (PORT d[12] (1527:1527:1527) (1639:1639:1639)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1874:1874:1874)) + (PORT d[0] (1489:1489:1489) (1442:1442:1442)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1875:1875:1875)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1837:1837:1837)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (1000:1000:1000)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (626:626:626) (635:635:635)) + (PORT datac (909:909:909) (911:911:911)) + (PORT datad (1120:1120:1120) (1222:1222:1222)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (965:965:965) (1030:1030:1030)) + (PORT d[1] (1241:1241:1241) (1329:1329:1329)) + (PORT d[2] (1056:1056:1056) (1157:1157:1157)) + (PORT d[3] (1088:1088:1088) (1177:1177:1177)) + (PORT d[4] (990:990:990) (1084:1084:1084)) + (PORT d[5] (1067:1067:1067) (1137:1137:1137)) + (PORT d[6] (1434:1434:1434) (1593:1593:1593)) + (PORT d[7] (1278:1278:1278) (1382:1382:1382)) + (PORT d[8] (1052:1052:1052) (1156:1156:1156)) + (PORT d[9] (1060:1060:1060) (1159:1159:1159)) + (PORT d[10] (1022:1022:1022) (1126:1126:1126)) + (PORT d[11] (1256:1256:1256) (1351:1351:1351)) + (PORT d[12] (1309:1309:1309) (1400:1400:1400)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1883:1883:1883)) + (PORT d[0] (918:918:918) (941:941:941)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (921:921:921) (982:982:982)) + (PORT d[1] (652:652:652) (711:711:711)) + (PORT d[2] (1323:1323:1323) (1400:1400:1400)) + (PORT d[3] (1338:1338:1338) (1452:1452:1452)) + (PORT d[4] (929:929:929) (988:988:988)) + (PORT d[5] (1048:1048:1048) (1131:1131:1131)) + (PORT d[6] (1394:1394:1394) (1522:1522:1522)) + (PORT d[7] (1240:1240:1240) (1309:1309:1309)) + (PORT d[8] (1638:1638:1638) (1740:1740:1740)) + (PORT d[9] (1048:1048:1048) (1110:1110:1110)) + (PORT d[10] (1044:1044:1044) (1103:1103:1103)) + (PORT d[11] (1204:1204:1204) (1263:1263:1263)) + (PORT d[12] (1258:1258:1258) (1304:1304:1304)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1883:1883:1883)) + (PORT d[0] (887:887:887) (888:888:888)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (694:694:694) (743:743:743)) + (PORT datac (917:917:917) (955:955:955)) + (PORT datad (347:347:347) (362:362:362)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1471:1471:1471) (1578:1578:1578)) + (PORT d[1] (1888:1888:1888) (2030:2030:2030)) + (PORT d[2] (1880:1880:1880) (2006:2006:2006)) + (PORT d[3] (1371:1371:1371) (1434:1434:1434)) + (PORT d[4] (1886:1886:1886) (2001:2001:2001)) + (PORT d[5] (1321:1321:1321) (1439:1439:1439)) + (PORT d[6] (1325:1325:1325) (1443:1443:1443)) + (PORT d[7] (1261:1261:1261) (1367:1367:1367)) + (PORT d[8] (1312:1312:1312) (1427:1427:1427)) + (PORT d[9] (1283:1283:1283) (1377:1377:1377)) + (PORT d[10] (1803:1803:1803) (1907:1907:1907)) + (PORT d[11] (1272:1272:1272) (1382:1382:1382)) + (PORT d[12] (1256:1256:1256) (1366:1366:1366)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1875:1875:1875)) + (PORT d[0] (1266:1266:1266) (1210:1210:1210)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1817:1817:1817) (1923:1923:1923)) + (PORT d[1] (1607:1607:1607) (1705:1705:1705)) + (PORT d[2] (1576:1576:1576) (1716:1716:1716)) + (PORT d[3] (1616:1616:1616) (1679:1679:1679)) + (PORT d[4] (1594:1594:1594) (1718:1718:1718)) + (PORT d[5] (1563:1563:1563) (1701:1701:1701)) + (PORT d[6] (1548:1548:1548) (1655:1655:1655)) + (PORT d[7] (1539:1539:1539) (1642:1642:1642)) + (PORT d[8] (1532:1532:1532) (1634:1634:1634)) + (PORT d[9] (1589:1589:1589) (1705:1705:1705)) + (PORT d[10] (1503:1503:1503) (1601:1601:1601)) + (PORT d[11] (1561:1561:1561) (1686:1686:1686)) + (PORT d[12] (1531:1531:1531) (1649:1649:1649)) + (PORT clk (1846:1846:1846) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1872:1872:1872)) + (PORT d[0] (1495:1495:1495) (1543:1543:1543)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1873:1873:1873)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1809:1809:1809) (1835:1835:1835)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (994:994:994) (998:998:998)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT datab (636:636:636) (645:645:645)) + (PORT datac (906:906:906) (905:905:905)) + (PORT datad (1123:1123:1123) (1224:1224:1224)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) ) diff --git a/simulation/modelsim/spectrum_min_1200mv_0c_fast.vo b/simulation/modelsim/spectrum_min_1200mv_0c_fast.vo index 59ddc72..03b41ff 100644 --- a/simulation/modelsim/spectrum_min_1200mv_0c_fast.vo +++ b/simulation/modelsim/spectrum_min_1200mv_0c_fast.vo @@ -16,7 +16,7 @@ // PROGRAM "Quartus II 32-bit" // VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" -// DATE "03/30/2022 12:38:42" +// DATE "03/30/2022 13:12:28" // // Device: Altera EP4CE22F17C6 Package FBGA256 @@ -71,77 +71,166 @@ wire \LED[6]~output_o ; wire \LED[7]~output_o ; wire \CLOCK_50~input_o ; wire \CLOCK_50~inputclkctrl_outclk ; -wire \Add0~0_combout ; -wire \Add0~1 ; -wire \Add0~2_combout ; -wire \Add0~3 ; -wire \Add0~4_combout ; -wire \Add0~5 ; -wire \Add0~6_combout ; -wire \Add0~7 ; -wire \Add0~8_combout ; -wire \Add0~9 ; -wire \Add0~10_combout ; -wire \Add0~11 ; -wire \Add0~12_combout ; -wire \Add0~13 ; -wire \Add0~14_combout ; -wire \Add0~15 ; -wire \Add0~16_combout ; -wire \Add0~17 ; -wire \Add0~18_combout ; -wire \Add0~19 ; -wire \Add0~20_combout ; -wire \Add0~21 ; -wire \Add0~22_combout ; -wire \Add0~23 ; -wire \Add0~24_combout ; -wire \Add0~25 ; -wire \Add0~26_combout ; -wire \Add0~27 ; -wire \Add0~28_combout ; -wire \Add0~29 ; -wire \Add0~30_combout ; -wire \Add0~31 ; -wire \Add0~32_combout ; -wire \Add0~33 ; -wire \Add0~34_combout ; -wire \Add0~35 ; -wire \Add0~36_combout ; -wire \Add0~37 ; -wire \Add0~38_combout ; -wire \Add0~39 ; -wire \Add0~40_combout ; +wire \counter[0]~63_combout ; +wire \counter[1]~21_combout ; +wire \counter[1]~22 ; +wire \counter[2]~23_combout ; +wire \counter[2]~24 ; +wire \counter[3]~25_combout ; +wire \counter[3]~26 ; +wire \counter[4]~27_combout ; +wire \counter[4]~28 ; +wire \counter[5]~29_combout ; +wire \counter[5]~30 ; +wire \counter[6]~31_combout ; +wire \counter[6]~32 ; +wire \counter[7]~33_combout ; +wire \counter[7]~34 ; +wire \counter[8]~35_combout ; +wire \counter[8]~36 ; +wire \counter[9]~37_combout ; +wire \counter[9]~38 ; +wire \counter[10]~39_combout ; +wire \counter[10]~40 ; +wire \counter[11]~41_combout ; +wire \counter[11]~feeder_combout ; +wire \counter[11]~42 ; +wire \counter[12]~43_combout ; +wire \counter[12]~44 ; +wire \counter[13]~45_combout ; +wire \counter[13]~46 ; +wire \counter[14]~47_combout ; +wire \counter[14]~48 ; +wire \counter[15]~49_combout ; +wire \counter[15]~50 ; +wire \counter[16]~51_combout ; +wire \counter[16]~52 ; +wire \counter[17]~53_combout ; +wire \counter[17]~54 ; +wire \counter[18]~55_combout ; +wire \counter[18]~56 ; +wire \counter[19]~57_combout ; wire \Equal0~5_combout ; -wire \Equal0~1_combout ; wire \Equal0~0_combout ; +wire \Equal0~1_combout ; wire \Equal0~2_combout ; wire \Equal0~3_combout ; wire \Equal0~4_combout ; -wire \address[0]~0_combout ; -wire \Equal0~6_combout ; +wire \counter[19]~58 ; +wire \counter[20]~59_combout ; +wire \counter[20]~60 ; +wire \counter[21]~61_combout ; wire \Equal0~7_combout ; -wire \address[1]~1_combout ; -wire \address[1]~2_combout ; -wire \address[2]~3_combout ; -wire [20:0] counter; -wire [2:0] address; -wire [7:0] \rom|altsyncram_component|auto_generated|q_a ; +wire \address[0]~39_combout ; +wire \address[1]~13_combout ; +wire \Equal0~6_combout ; +wire \address[1]~14 ; +wire \address[2]~15_combout ; +wire \address[2]~16 ; +wire \address[3]~17_combout ; +wire \address[3]~18 ; +wire \address[4]~19_combout ; +wire \address[4]~20 ; +wire \address[5]~21_combout ; +wire \address[5]~22 ; +wire \address[6]~23_combout ; +wire \address[6]~24 ; +wire \address[7]~25_combout ; +wire \address[7]~26 ; +wire \address[8]~27_combout ; +wire \address[8]~28 ; +wire \address[9]~29_combout ; +wire \address[9]~30 ; +wire \address[10]~31_combout ; +wire \address[10]~32 ; +wire \address[11]~33_combout ; +wire \address[11]~34 ; +wire \address[12]~35_combout ; +wire \address[12]~36 ; +wire \address[13]~37_combout ; +wire \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ; +wire \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ; +wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ; +wire \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ; +wire [21:0] counter; +wire [13:0] address; +wire [0:0] \rom|altsyncram_component|auto_generated|out_address_reg_a ; +wire [0:0] \rom|altsyncram_component|auto_generated|address_reg_a ; -wire [17:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ; +wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ; -assign \rom|altsyncram_component|auto_generated|q_a [0] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; -assign \rom|altsyncram_component|auto_generated|q_a [1] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [1]; -assign \rom|altsyncram_component|auto_generated|q_a [2] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [2]; -assign \rom|altsyncram_component|auto_generated|q_a [3] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [3]; -assign \rom|altsyncram_component|auto_generated|q_a [4] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [4]; -assign \rom|altsyncram_component|auto_generated|q_a [5] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [5]; -assign \rom|altsyncram_component|auto_generated|q_a [6] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [6]; -assign \rom|altsyncram_component|auto_generated|q_a [7] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [7]; +assign \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0]; + +assign \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0]; // Location: IOOBUF_X38_Y34_N16 cycloneive_io_obuf \LED[0]~output ( - .i(\rom|altsyncram_component|auto_generated|q_a [0]), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -154,7 +243,7 @@ defparam \LED[0]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y34_N2 cycloneive_io_obuf \LED[1]~output ( - .i(\rom|altsyncram_component|auto_generated|q_a [1]), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -167,7 +256,7 @@ defparam \LED[1]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y34_N9 cycloneive_io_obuf \LED[2]~output ( - .i(\rom|altsyncram_component|auto_generated|q_a [2]), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -180,7 +269,7 @@ defparam \LED[2]~output .open_drain_output = "false"; // Location: IOOBUF_X40_Y34_N2 cycloneive_io_obuf \LED[3]~output ( - .i(\rom|altsyncram_component|auto_generated|q_a [3]), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -193,7 +282,7 @@ defparam \LED[3]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y25_N9 cycloneive_io_obuf \LED[4]~output ( - .i(\rom|altsyncram_component|auto_generated|q_a [4]), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -206,7 +295,7 @@ defparam \LED[4]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y26_N16 cycloneive_io_obuf \LED[5]~output ( - .i(\rom|altsyncram_component|auto_generated|q_a [5]), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -219,7 +308,7 @@ defparam \LED[5]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y28_N9 cycloneive_io_obuf \LED[6]~output ( - .i(\rom|altsyncram_component|auto_generated|q_a [6]), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -232,7 +321,7 @@ defparam \LED[6]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y10_N23 cycloneive_io_obuf \LED[7]~output ( - .i(\rom|altsyncram_component|auto_generated|q_a [7]), + .i(\rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -266,47 +355,27 @@ defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: FF_X31_Y17_N21 -dffeas \counter[20] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~40_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[20]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[20] .is_wysiwyg = "true"; -defparam \counter[20] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N12 -cycloneive_lcell_comb \Add0~0 ( +// Location: LCCOMB_X28_Y18_N2 +cycloneive_lcell_comb \counter[0]~63 ( // Equation(s): -// \Add0~0_combout = counter[0] $ (VCC) -// \Add0~1 = CARRY(counter[0]) +// \counter[0]~63_combout = !counter[0] - .dataa(counter[0]), + .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(vcc), + .datac(counter[0]), + .datad(gnd), .cin(gnd), - .combout(\Add0~0_combout ), - .cout(\Add0~1 )); + .combout(\counter[0]~63_combout ), + .cout()); // synopsys translate_off -defparam \Add0~0 .lut_mask = 16'h55AA; -defparam \Add0~0 .sum_lutc_input = "datac"; +defparam \counter[0]~63 .lut_mask = 16'h0F0F; +defparam \counter[0]~63 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y18_N13 +// Location: FF_X28_Y18_N3 dffeas \counter[0] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~0_combout ), + .d(\counter[0]~63_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -322,28 +391,28 @@ defparam \counter[0] .is_wysiwyg = "true"; defparam \counter[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y18_N14 -cycloneive_lcell_comb \Add0~2 ( +// Location: LCCOMB_X28_Y18_N12 +cycloneive_lcell_comb \counter[1]~21 ( // Equation(s): -// \Add0~2_combout = (counter[1] & (!\Add0~1 )) # (!counter[1] & ((\Add0~1 ) # (GND))) -// \Add0~3 = CARRY((!\Add0~1 ) # (!counter[1])) +// \counter[1]~21_combout = (counter[1] & (counter[0] $ (VCC))) # (!counter[1] & (counter[0] & VCC)) +// \counter[1]~22 = CARRY((counter[1] & counter[0])) - .dataa(gnd), - .datab(counter[1]), + .dataa(counter[1]), + .datab(counter[0]), .datac(gnd), .datad(vcc), - .cin(\Add0~1 ), - .combout(\Add0~2_combout ), - .cout(\Add0~3 )); + .cin(gnd), + .combout(\counter[1]~21_combout ), + .cout(\counter[1]~22 )); // synopsys translate_off -defparam \Add0~2 .lut_mask = 16'h3C3F; -defparam \Add0~2 .sum_lutc_input = "cin"; +defparam \counter[1]~21 .lut_mask = 16'h6688; +defparam \counter[1]~21 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X31_Y18_N15 +// Location: FF_X28_Y18_N13 dffeas \counter[1] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~2_combout ), + .d(\counter[1]~21_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -359,28 +428,28 @@ defparam \counter[1] .is_wysiwyg = "true"; defparam \counter[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y18_N16 -cycloneive_lcell_comb \Add0~4 ( +// Location: LCCOMB_X28_Y18_N14 +cycloneive_lcell_comb \counter[2]~23 ( // Equation(s): -// \Add0~4_combout = (counter[2] & (\Add0~3 $ (GND))) # (!counter[2] & (!\Add0~3 & VCC)) -// \Add0~5 = CARRY((counter[2] & !\Add0~3 )) +// \counter[2]~23_combout = (counter[2] & (!\counter[1]~22 )) # (!counter[2] & ((\counter[1]~22 ) # (GND))) +// \counter[2]~24 = CARRY((!\counter[1]~22 ) # (!counter[2])) .dataa(gnd), .datab(counter[2]), .datac(gnd), .datad(vcc), - .cin(\Add0~3 ), - .combout(\Add0~4_combout ), - .cout(\Add0~5 )); + .cin(\counter[1]~22 ), + .combout(\counter[2]~23_combout ), + .cout(\counter[2]~24 )); // synopsys translate_off -defparam \Add0~4 .lut_mask = 16'hC30C; -defparam \Add0~4 .sum_lutc_input = "cin"; +defparam \counter[2]~23 .lut_mask = 16'h3C3F; +defparam \counter[2]~23 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y18_N17 +// Location: FF_X28_Y18_N15 dffeas \counter[2] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~4_combout ), + .d(\counter[2]~23_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -396,28 +465,28 @@ defparam \counter[2] .is_wysiwyg = "true"; defparam \counter[2] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y18_N18 -cycloneive_lcell_comb \Add0~6 ( +// Location: LCCOMB_X28_Y18_N16 +cycloneive_lcell_comb \counter[3]~25 ( // Equation(s): -// \Add0~6_combout = (counter[3] & (!\Add0~5 )) # (!counter[3] & ((\Add0~5 ) # (GND))) -// \Add0~7 = CARRY((!\Add0~5 ) # (!counter[3])) +// \counter[3]~25_combout = (counter[3] & (\counter[2]~24 $ (GND))) # (!counter[3] & (!\counter[2]~24 & VCC)) +// \counter[3]~26 = CARRY((counter[3] & !\counter[2]~24 )) .dataa(gnd), .datab(counter[3]), .datac(gnd), .datad(vcc), - .cin(\Add0~5 ), - .combout(\Add0~6_combout ), - .cout(\Add0~7 )); + .cin(\counter[2]~24 ), + .combout(\counter[3]~25_combout ), + .cout(\counter[3]~26 )); // synopsys translate_off -defparam \Add0~6 .lut_mask = 16'h3C3F; -defparam \Add0~6 .sum_lutc_input = "cin"; +defparam \counter[3]~25 .lut_mask = 16'hC30C; +defparam \counter[3]~25 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y18_N19 +// Location: FF_X28_Y18_N17 dffeas \counter[3] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~6_combout ), + .d(\counter[3]~25_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -433,28 +502,28 @@ defparam \counter[3] .is_wysiwyg = "true"; defparam \counter[3] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y18_N20 -cycloneive_lcell_comb \Add0~8 ( +// Location: LCCOMB_X28_Y18_N18 +cycloneive_lcell_comb \counter[4]~27 ( // Equation(s): -// \Add0~8_combout = (counter[4] & (\Add0~7 $ (GND))) # (!counter[4] & (!\Add0~7 & VCC)) -// \Add0~9 = CARRY((counter[4] & !\Add0~7 )) +// \counter[4]~27_combout = (counter[4] & (!\counter[3]~26 )) # (!counter[4] & ((\counter[3]~26 ) # (GND))) +// \counter[4]~28 = CARRY((!\counter[3]~26 ) # (!counter[4])) - .dataa(counter[4]), - .datab(gnd), + .dataa(gnd), + .datab(counter[4]), .datac(gnd), .datad(vcc), - .cin(\Add0~7 ), - .combout(\Add0~8_combout ), - .cout(\Add0~9 )); + .cin(\counter[3]~26 ), + .combout(\counter[4]~27_combout ), + .cout(\counter[4]~28 )); // synopsys translate_off -defparam \Add0~8 .lut_mask = 16'hA50A; -defparam \Add0~8 .sum_lutc_input = "cin"; +defparam \counter[4]~27 .lut_mask = 16'h3C3F; +defparam \counter[4]~27 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y18_N21 +// Location: FF_X28_Y18_N19 dffeas \counter[4] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~8_combout ), + .d(\counter[4]~27_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -470,28 +539,28 @@ defparam \counter[4] .is_wysiwyg = "true"; defparam \counter[4] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y18_N22 -cycloneive_lcell_comb \Add0~10 ( +// Location: LCCOMB_X28_Y18_N20 +cycloneive_lcell_comb \counter[5]~29 ( // Equation(s): -// \Add0~10_combout = (counter[5] & (!\Add0~9 )) # (!counter[5] & ((\Add0~9 ) # (GND))) -// \Add0~11 = CARRY((!\Add0~9 ) # (!counter[5])) +// \counter[5]~29_combout = (counter[5] & (\counter[4]~28 $ (GND))) # (!counter[5] & (!\counter[4]~28 & VCC)) +// \counter[5]~30 = CARRY((counter[5] & !\counter[4]~28 )) .dataa(gnd), .datab(counter[5]), .datac(gnd), .datad(vcc), - .cin(\Add0~9 ), - .combout(\Add0~10_combout ), - .cout(\Add0~11 )); + .cin(\counter[4]~28 ), + .combout(\counter[5]~29_combout ), + .cout(\counter[5]~30 )); // synopsys translate_off -defparam \Add0~10 .lut_mask = 16'h3C3F; -defparam \Add0~10 .sum_lutc_input = "cin"; +defparam \counter[5]~29 .lut_mask = 16'hC30C; +defparam \counter[5]~29 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y18_N23 +// Location: FF_X28_Y18_N21 dffeas \counter[5] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~10_combout ), + .d(\counter[5]~29_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -507,28 +576,28 @@ defparam \counter[5] .is_wysiwyg = "true"; defparam \counter[5] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y18_N24 -cycloneive_lcell_comb \Add0~12 ( +// Location: LCCOMB_X28_Y18_N22 +cycloneive_lcell_comb \counter[6]~31 ( // Equation(s): -// \Add0~12_combout = (counter[6] & (\Add0~11 $ (GND))) # (!counter[6] & (!\Add0~11 & VCC)) -// \Add0~13 = CARRY((counter[6] & !\Add0~11 )) +// \counter[6]~31_combout = (counter[6] & (!\counter[5]~30 )) # (!counter[6] & ((\counter[5]~30 ) # (GND))) +// \counter[6]~32 = CARRY((!\counter[5]~30 ) # (!counter[6])) .dataa(counter[6]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\Add0~11 ), - .combout(\Add0~12_combout ), - .cout(\Add0~13 )); + .cin(\counter[5]~30 ), + .combout(\counter[6]~31_combout ), + .cout(\counter[6]~32 )); // synopsys translate_off -defparam \Add0~12 .lut_mask = 16'hA50A; -defparam \Add0~12 .sum_lutc_input = "cin"; +defparam \counter[6]~31 .lut_mask = 16'h5A5F; +defparam \counter[6]~31 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y18_N25 +// Location: FF_X28_Y18_N23 dffeas \counter[6] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~12_combout ), + .d(\counter[6]~31_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -544,28 +613,28 @@ defparam \counter[6] .is_wysiwyg = "true"; defparam \counter[6] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y18_N26 -cycloneive_lcell_comb \Add0~14 ( +// Location: LCCOMB_X28_Y18_N24 +cycloneive_lcell_comb \counter[7]~33 ( // Equation(s): -// \Add0~14_combout = (counter[7] & (!\Add0~13 )) # (!counter[7] & ((\Add0~13 ) # (GND))) -// \Add0~15 = CARRY((!\Add0~13 ) # (!counter[7])) +// \counter[7]~33_combout = (counter[7] & (\counter[6]~32 $ (GND))) # (!counter[7] & (!\counter[6]~32 & VCC)) +// \counter[7]~34 = CARRY((counter[7] & !\counter[6]~32 )) .dataa(gnd), .datab(counter[7]), .datac(gnd), .datad(vcc), - .cin(\Add0~13 ), - .combout(\Add0~14_combout ), - .cout(\Add0~15 )); + .cin(\counter[6]~32 ), + .combout(\counter[7]~33_combout ), + .cout(\counter[7]~34 )); // synopsys translate_off -defparam \Add0~14 .lut_mask = 16'h3C3F; -defparam \Add0~14 .sum_lutc_input = "cin"; +defparam \counter[7]~33 .lut_mask = 16'hC30C; +defparam \counter[7]~33 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y18_N27 +// Location: FF_X28_Y18_N25 dffeas \counter[7] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~14_combout ), + .d(\counter[7]~33_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -581,28 +650,28 @@ defparam \counter[7] .is_wysiwyg = "true"; defparam \counter[7] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y18_N28 -cycloneive_lcell_comb \Add0~16 ( +// Location: LCCOMB_X28_Y18_N26 +cycloneive_lcell_comb \counter[8]~35 ( // Equation(s): -// \Add0~16_combout = (counter[8] & (\Add0~15 $ (GND))) # (!counter[8] & (!\Add0~15 & VCC)) -// \Add0~17 = CARRY((counter[8] & !\Add0~15 )) +// \counter[8]~35_combout = (counter[8] & (!\counter[7]~34 )) # (!counter[8] & ((\counter[7]~34 ) # (GND))) +// \counter[8]~36 = CARRY((!\counter[7]~34 ) # (!counter[8])) - .dataa(gnd), - .datab(counter[8]), + .dataa(counter[8]), + .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\Add0~15 ), - .combout(\Add0~16_combout ), - .cout(\Add0~17 )); + .cin(\counter[7]~34 ), + .combout(\counter[8]~35_combout ), + .cout(\counter[8]~36 )); // synopsys translate_off -defparam \Add0~16 .lut_mask = 16'hC30C; -defparam \Add0~16 .sum_lutc_input = "cin"; +defparam \counter[8]~35 .lut_mask = 16'h5A5F; +defparam \counter[8]~35 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y18_N29 +// Location: FF_X28_Y18_N27 dffeas \counter[8] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~16_combout ), + .d(\counter[8]~35_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -618,28 +687,28 @@ defparam \counter[8] .is_wysiwyg = "true"; defparam \counter[8] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y18_N30 -cycloneive_lcell_comb \Add0~18 ( +// Location: LCCOMB_X28_Y18_N28 +cycloneive_lcell_comb \counter[9]~37 ( // Equation(s): -// \Add0~18_combout = (counter[9] & (!\Add0~17 )) # (!counter[9] & ((\Add0~17 ) # (GND))) -// \Add0~19 = CARRY((!\Add0~17 ) # (!counter[9])) +// \counter[9]~37_combout = (counter[9] & (\counter[8]~36 $ (GND))) # (!counter[9] & (!\counter[8]~36 & VCC)) +// \counter[9]~38 = CARRY((counter[9] & !\counter[8]~36 )) - .dataa(counter[9]), - .datab(gnd), + .dataa(gnd), + .datab(counter[9]), .datac(gnd), .datad(vcc), - .cin(\Add0~17 ), - .combout(\Add0~18_combout ), - .cout(\Add0~19 )); + .cin(\counter[8]~36 ), + .combout(\counter[9]~37_combout ), + .cout(\counter[9]~38 )); // synopsys translate_off -defparam \Add0~18 .lut_mask = 16'h5A5F; -defparam \Add0~18 .sum_lutc_input = "cin"; +defparam \counter[9]~37 .lut_mask = 16'hC30C; +defparam \counter[9]~37 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y18_N31 +// Location: FF_X28_Y18_N29 dffeas \counter[9] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~18_combout ), + .d(\counter[9]~37_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -655,28 +724,28 @@ defparam \counter[9] .is_wysiwyg = "true"; defparam \counter[9] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N0 -cycloneive_lcell_comb \Add0~20 ( +// Location: LCCOMB_X28_Y18_N30 +cycloneive_lcell_comb \counter[10]~39 ( // Equation(s): -// \Add0~20_combout = (counter[10] & (\Add0~19 $ (GND))) # (!counter[10] & (!\Add0~19 & VCC)) -// \Add0~21 = CARRY((counter[10] & !\Add0~19 )) +// \counter[10]~39_combout = (counter[10] & (!\counter[9]~38 )) # (!counter[10] & ((\counter[9]~38 ) # (GND))) +// \counter[10]~40 = CARRY((!\counter[9]~38 ) # (!counter[10])) - .dataa(gnd), - .datab(counter[10]), + .dataa(counter[10]), + .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\Add0~19 ), - .combout(\Add0~20_combout ), - .cout(\Add0~21 )); + .cin(\counter[9]~38 ), + .combout(\counter[10]~39_combout ), + .cout(\counter[10]~40 )); // synopsys translate_off -defparam \Add0~20 .lut_mask = 16'hC30C; -defparam \Add0~20 .sum_lutc_input = "cin"; +defparam \counter[10]~39 .lut_mask = 16'h5A5F; +defparam \counter[10]~39 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y17_N1 +// Location: FF_X28_Y18_N31 dffeas \counter[10] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~20_combout ), + .d(\counter[10]~39_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -692,28 +761,45 @@ defparam \counter[10] .is_wysiwyg = "true"; defparam \counter[10] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N2 -cycloneive_lcell_comb \Add0~22 ( +// Location: LCCOMB_X28_Y17_N0 +cycloneive_lcell_comb \counter[11]~41 ( // Equation(s): -// \Add0~22_combout = (counter[11] & (!\Add0~21 )) # (!counter[11] & ((\Add0~21 ) # (GND))) -// \Add0~23 = CARRY((!\Add0~21 ) # (!counter[11])) +// \counter[11]~41_combout = (counter[11] & (\counter[10]~40 $ (GND))) # (!counter[11] & (!\counter[10]~40 & VCC)) +// \counter[11]~42 = CARRY((counter[11] & !\counter[10]~40 )) - .dataa(gnd), - .datab(counter[11]), + .dataa(counter[11]), + .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\Add0~21 ), - .combout(\Add0~22_combout ), - .cout(\Add0~23 )); + .cin(\counter[10]~40 ), + .combout(\counter[11]~41_combout ), + .cout(\counter[11]~42 )); // synopsys translate_off -defparam \Add0~22 .lut_mask = 16'h3C3F; -defparam \Add0~22 .sum_lutc_input = "cin"; +defparam \counter[11]~41 .lut_mask = 16'hA50A; +defparam \counter[11]~41 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y17_N3 +// Location: LCCOMB_X28_Y18_N4 +cycloneive_lcell_comb \counter[11]~feeder ( +// Equation(s): +// \counter[11]~feeder_combout = \counter[11]~41_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\counter[11]~41_combout ), + .cin(gnd), + .combout(\counter[11]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \counter[11]~feeder .lut_mask = 16'hFF00; +defparam \counter[11]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N5 dffeas \counter[11] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~22_combout ), + .d(\counter[11]~feeder_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -729,28 +815,28 @@ defparam \counter[11] .is_wysiwyg = "true"; defparam \counter[11] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N4 -cycloneive_lcell_comb \Add0~24 ( +// Location: LCCOMB_X28_Y17_N2 +cycloneive_lcell_comb \counter[12]~43 ( // Equation(s): -// \Add0~24_combout = (counter[12] & (\Add0~23 $ (GND))) # (!counter[12] & (!\Add0~23 & VCC)) -// \Add0~25 = CARRY((counter[12] & !\Add0~23 )) +// \counter[12]~43_combout = (counter[12] & (!\counter[11]~42 )) # (!counter[12] & ((\counter[11]~42 ) # (GND))) +// \counter[12]~44 = CARRY((!\counter[11]~42 ) # (!counter[12])) .dataa(gnd), .datab(counter[12]), .datac(gnd), .datad(vcc), - .cin(\Add0~23 ), - .combout(\Add0~24_combout ), - .cout(\Add0~25 )); + .cin(\counter[11]~42 ), + .combout(\counter[12]~43_combout ), + .cout(\counter[12]~44 )); // synopsys translate_off -defparam \Add0~24 .lut_mask = 16'hC30C; -defparam \Add0~24 .sum_lutc_input = "cin"; +defparam \counter[12]~43 .lut_mask = 16'h3C3F; +defparam \counter[12]~43 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y17_N5 +// Location: FF_X28_Y17_N3 dffeas \counter[12] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~24_combout ), + .d(\counter[12]~43_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -766,28 +852,28 @@ defparam \counter[12] .is_wysiwyg = "true"; defparam \counter[12] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N6 -cycloneive_lcell_comb \Add0~26 ( +// Location: LCCOMB_X28_Y17_N4 +cycloneive_lcell_comb \counter[13]~45 ( // Equation(s): -// \Add0~26_combout = (counter[13] & (!\Add0~25 )) # (!counter[13] & ((\Add0~25 ) # (GND))) -// \Add0~27 = CARRY((!\Add0~25 ) # (!counter[13])) +// \counter[13]~45_combout = (counter[13] & (\counter[12]~44 $ (GND))) # (!counter[13] & (!\counter[12]~44 & VCC)) +// \counter[13]~46 = CARRY((counter[13] & !\counter[12]~44 )) .dataa(gnd), .datab(counter[13]), .datac(gnd), .datad(vcc), - .cin(\Add0~25 ), - .combout(\Add0~26_combout ), - .cout(\Add0~27 )); + .cin(\counter[12]~44 ), + .combout(\counter[13]~45_combout ), + .cout(\counter[13]~46 )); // synopsys translate_off -defparam \Add0~26 .lut_mask = 16'h3C3F; -defparam \Add0~26 .sum_lutc_input = "cin"; +defparam \counter[13]~45 .lut_mask = 16'hC30C; +defparam \counter[13]~45 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y17_N7 +// Location: FF_X28_Y17_N5 dffeas \counter[13] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~26_combout ), + .d(\counter[13]~45_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -803,28 +889,28 @@ defparam \counter[13] .is_wysiwyg = "true"; defparam \counter[13] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N8 -cycloneive_lcell_comb \Add0~28 ( +// Location: LCCOMB_X28_Y17_N6 +cycloneive_lcell_comb \counter[14]~47 ( // Equation(s): -// \Add0~28_combout = (counter[14] & (\Add0~27 $ (GND))) # (!counter[14] & (!\Add0~27 & VCC)) -// \Add0~29 = CARRY((counter[14] & !\Add0~27 )) +// \counter[14]~47_combout = (counter[14] & (!\counter[13]~46 )) # (!counter[14] & ((\counter[13]~46 ) # (GND))) +// \counter[14]~48 = CARRY((!\counter[13]~46 ) # (!counter[14])) .dataa(counter[14]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\Add0~27 ), - .combout(\Add0~28_combout ), - .cout(\Add0~29 )); + .cin(\counter[13]~46 ), + .combout(\counter[14]~47_combout ), + .cout(\counter[14]~48 )); // synopsys translate_off -defparam \Add0~28 .lut_mask = 16'hA50A; -defparam \Add0~28 .sum_lutc_input = "cin"; +defparam \counter[14]~47 .lut_mask = 16'h5A5F; +defparam \counter[14]~47 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y17_N9 +// Location: FF_X28_Y17_N7 dffeas \counter[14] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~28_combout ), + .d(\counter[14]~47_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -840,28 +926,28 @@ defparam \counter[14] .is_wysiwyg = "true"; defparam \counter[14] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N10 -cycloneive_lcell_comb \Add0~30 ( +// Location: LCCOMB_X28_Y17_N8 +cycloneive_lcell_comb \counter[15]~49 ( // Equation(s): -// \Add0~30_combout = (counter[15] & (!\Add0~29 )) # (!counter[15] & ((\Add0~29 ) # (GND))) -// \Add0~31 = CARRY((!\Add0~29 ) # (!counter[15])) +// \counter[15]~49_combout = (counter[15] & (\counter[14]~48 $ (GND))) # (!counter[15] & (!\counter[14]~48 & VCC)) +// \counter[15]~50 = CARRY((counter[15] & !\counter[14]~48 )) .dataa(gnd), .datab(counter[15]), .datac(gnd), .datad(vcc), - .cin(\Add0~29 ), - .combout(\Add0~30_combout ), - .cout(\Add0~31 )); + .cin(\counter[14]~48 ), + .combout(\counter[15]~49_combout ), + .cout(\counter[15]~50 )); // synopsys translate_off -defparam \Add0~30 .lut_mask = 16'h3C3F; -defparam \Add0~30 .sum_lutc_input = "cin"; +defparam \counter[15]~49 .lut_mask = 16'hC30C; +defparam \counter[15]~49 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y17_N11 +// Location: FF_X28_Y17_N9 dffeas \counter[15] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~30_combout ), + .d(\counter[15]~49_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -877,28 +963,28 @@ defparam \counter[15] .is_wysiwyg = "true"; defparam \counter[15] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N12 -cycloneive_lcell_comb \Add0~32 ( +// Location: LCCOMB_X28_Y17_N10 +cycloneive_lcell_comb \counter[16]~51 ( // Equation(s): -// \Add0~32_combout = (counter[16] & (\Add0~31 $ (GND))) # (!counter[16] & (!\Add0~31 & VCC)) -// \Add0~33 = CARRY((counter[16] & !\Add0~31 )) +// \counter[16]~51_combout = (counter[16] & (!\counter[15]~50 )) # (!counter[16] & ((\counter[15]~50 ) # (GND))) +// \counter[16]~52 = CARRY((!\counter[15]~50 ) # (!counter[16])) - .dataa(gnd), - .datab(counter[16]), + .dataa(counter[16]), + .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\Add0~31 ), - .combout(\Add0~32_combout ), - .cout(\Add0~33 )); + .cin(\counter[15]~50 ), + .combout(\counter[16]~51_combout ), + .cout(\counter[16]~52 )); // synopsys translate_off -defparam \Add0~32 .lut_mask = 16'hC30C; -defparam \Add0~32 .sum_lutc_input = "cin"; +defparam \counter[16]~51 .lut_mask = 16'h5A5F; +defparam \counter[16]~51 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y17_N13 +// Location: FF_X28_Y17_N11 dffeas \counter[16] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~32_combout ), + .d(\counter[16]~51_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -914,28 +1000,28 @@ defparam \counter[16] .is_wysiwyg = "true"; defparam \counter[16] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N14 -cycloneive_lcell_comb \Add0~34 ( +// Location: LCCOMB_X28_Y17_N12 +cycloneive_lcell_comb \counter[17]~53 ( // Equation(s): -// \Add0~34_combout = (counter[17] & (!\Add0~33 )) # (!counter[17] & ((\Add0~33 ) # (GND))) -// \Add0~35 = CARRY((!\Add0~33 ) # (!counter[17])) +// \counter[17]~53_combout = (counter[17] & (\counter[16]~52 $ (GND))) # (!counter[17] & (!\counter[16]~52 & VCC)) +// \counter[17]~54 = CARRY((counter[17] & !\counter[16]~52 )) .dataa(counter[17]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\Add0~33 ), - .combout(\Add0~34_combout ), - .cout(\Add0~35 )); + .cin(\counter[16]~52 ), + .combout(\counter[17]~53_combout ), + .cout(\counter[17]~54 )); // synopsys translate_off -defparam \Add0~34 .lut_mask = 16'h5A5F; -defparam \Add0~34 .sum_lutc_input = "cin"; +defparam \counter[17]~53 .lut_mask = 16'hA50A; +defparam \counter[17]~53 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y17_N15 +// Location: FF_X28_Y17_N13 dffeas \counter[17] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~34_combout ), + .d(\counter[17]~53_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -951,28 +1037,28 @@ defparam \counter[17] .is_wysiwyg = "true"; defparam \counter[17] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N16 -cycloneive_lcell_comb \Add0~36 ( +// Location: LCCOMB_X28_Y17_N14 +cycloneive_lcell_comb \counter[18]~55 ( // Equation(s): -// \Add0~36_combout = (counter[18] & (\Add0~35 $ (GND))) # (!counter[18] & (!\Add0~35 & VCC)) -// \Add0~37 = CARRY((counter[18] & !\Add0~35 )) +// \counter[18]~55_combout = (counter[18] & (!\counter[17]~54 )) # (!counter[18] & ((\counter[17]~54 ) # (GND))) +// \counter[18]~56 = CARRY((!\counter[17]~54 ) # (!counter[18])) - .dataa(counter[18]), - .datab(gnd), + .dataa(gnd), + .datab(counter[18]), .datac(gnd), .datad(vcc), - .cin(\Add0~35 ), - .combout(\Add0~36_combout ), - .cout(\Add0~37 )); + .cin(\counter[17]~54 ), + .combout(\counter[18]~55_combout ), + .cout(\counter[18]~56 )); // synopsys translate_off -defparam \Add0~36 .lut_mask = 16'hA50A; -defparam \Add0~36 .sum_lutc_input = "cin"; +defparam \counter[18]~55 .lut_mask = 16'h3C3F; +defparam \counter[18]~55 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y17_N17 +// Location: FF_X28_Y17_N15 dffeas \counter[18] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~36_combout ), + .d(\counter[18]~55_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -988,28 +1074,28 @@ defparam \counter[18] .is_wysiwyg = "true"; defparam \counter[18] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N18 -cycloneive_lcell_comb \Add0~38 ( +// Location: LCCOMB_X28_Y17_N16 +cycloneive_lcell_comb \counter[19]~57 ( // Equation(s): -// \Add0~38_combout = (counter[19] & (!\Add0~37 )) # (!counter[19] & ((\Add0~37 ) # (GND))) -// \Add0~39 = CARRY((!\Add0~37 ) # (!counter[19])) +// \counter[19]~57_combout = (counter[19] & (\counter[18]~56 $ (GND))) # (!counter[19] & (!\counter[18]~56 & VCC)) +// \counter[19]~58 = CARRY((counter[19] & !\counter[18]~56 )) - .dataa(counter[19]), - .datab(gnd), + .dataa(gnd), + .datab(counter[19]), .datac(gnd), .datad(vcc), - .cin(\Add0~37 ), - .combout(\Add0~38_combout ), - .cout(\Add0~39 )); + .cin(\counter[18]~56 ), + .combout(\counter[19]~57_combout ), + .cout(\counter[19]~58 )); // synopsys translate_off -defparam \Add0~38 .lut_mask = 16'h5A5F; -defparam \Add0~38 .sum_lutc_input = "cin"; +defparam \counter[19]~57 .lut_mask = 16'hC30C; +defparam \counter[19]~57 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X31_Y17_N19 +// Location: FF_X28_Y17_N17 dffeas \counter[19] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\Add0~38_combout ), + .d(\counter[19]~57_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1025,32 +1111,15 @@ defparam \counter[19] .is_wysiwyg = "true"; defparam \counter[19] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N20 -cycloneive_lcell_comb \Add0~40 ( -// Equation(s): -// \Add0~40_combout = \Add0~39 $ (!counter[20]) - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(counter[20]), - .cin(\Add0~39 ), - .combout(\Add0~40_combout ), - .cout()); -// synopsys translate_off -defparam \Add0~40 .lut_mask = 16'hF00F; -defparam \Add0~40 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y17_N28 +// Location: LCCOMB_X28_Y17_N28 cycloneive_lcell_comb \Equal0~5 ( // Equation(s): -// \Equal0~5_combout = (!\Add0~32_combout & (!\Add0~36_combout & (!\Add0~34_combout & !\Add0~38_combout ))) +// \Equal0~5_combout = (!counter[17] & (!counter[19] & (!counter[18] & !counter[16]))) - .dataa(\Add0~32_combout ), - .datab(\Add0~36_combout ), - .datac(\Add0~34_combout ), - .datad(\Add0~38_combout ), + .dataa(counter[17]), + .datab(counter[19]), + .datac(counter[18]), + .datad(counter[16]), .cin(gnd), .combout(\Equal0~5_combout ), .cout()); @@ -1059,32 +1128,15 @@ defparam \Equal0~5 .lut_mask = 16'h0001; defparam \Equal0~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y18_N6 -cycloneive_lcell_comb \Equal0~1 ( -// Equation(s): -// \Equal0~1_combout = (!\Add0~10_combout & (!\Add0~8_combout & (!\Add0~14_combout & !\Add0~12_combout ))) - - .dataa(\Add0~10_combout ), - .datab(\Add0~8_combout ), - .datac(\Add0~14_combout ), - .datad(\Add0~12_combout ), - .cin(gnd), - .combout(\Equal0~1_combout ), - .cout()); -// synopsys translate_off -defparam \Equal0~1 .lut_mask = 16'h0001; -defparam \Equal0~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X31_Y18_N4 +// Location: LCCOMB_X28_Y18_N8 cycloneive_lcell_comb \Equal0~0 ( // Equation(s): -// \Equal0~0_combout = (!\Add0~4_combout & (!\Add0~0_combout & (!\Add0~6_combout & !\Add0~2_combout ))) +// \Equal0~0_combout = (!counter[1] & (!counter[0] & (!counter[2] & !counter[3]))) - .dataa(\Add0~4_combout ), - .datab(\Add0~0_combout ), - .datac(\Add0~6_combout ), - .datad(\Add0~2_combout ), + .dataa(counter[1]), + .datab(counter[0]), + .datac(counter[2]), + .datad(counter[3]), .cin(gnd), .combout(\Equal0~0_combout ), .cout()); @@ -1093,15 +1145,32 @@ defparam \Equal0~0 .lut_mask = 16'h0001; defparam \Equal0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N30 +// Location: LCCOMB_X28_Y18_N6 +cycloneive_lcell_comb \Equal0~1 ( +// Equation(s): +// \Equal0~1_combout = (!counter[6] & (!counter[7] & (!counter[5] & !counter[4]))) + + .dataa(counter[6]), + .datab(counter[7]), + .datac(counter[5]), + .datad(counter[4]), + .cin(gnd), + .combout(\Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~1 .lut_mask = 16'h0001; +defparam \Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N0 cycloneive_lcell_comb \Equal0~2 ( // Equation(s): -// \Equal0~2_combout = (!\Add0~22_combout & (!\Add0~16_combout & (!\Add0~20_combout & !\Add0~18_combout ))) +// \Equal0~2_combout = (!counter[8] & (!counter[11] & (!counter[10] & !counter[9]))) - .dataa(\Add0~22_combout ), - .datab(\Add0~16_combout ), - .datac(\Add0~20_combout ), - .datad(\Add0~18_combout ), + .dataa(counter[8]), + .datab(counter[11]), + .datac(counter[10]), + .datad(counter[9]), .cin(gnd), .combout(\Equal0~2_combout ), .cout()); @@ -1110,15 +1179,15 @@ defparam \Equal0~2 .lut_mask = 16'h0001; defparam \Equal0~2 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N30 +// Location: LCCOMB_X28_Y17_N26 cycloneive_lcell_comb \Equal0~3 ( // Equation(s): -// \Equal0~3_combout = (!\Add0~26_combout & (!\Add0~24_combout & (!\Add0~28_combout & !\Add0~30_combout ))) +// \Equal0~3_combout = (!counter[14] & (!counter[13] & (!counter[15] & !counter[12]))) - .dataa(\Add0~26_combout ), - .datab(\Add0~24_combout ), - .datac(\Add0~28_combout ), - .datad(\Add0~30_combout ), + .dataa(counter[14]), + .datab(counter[13]), + .datac(counter[15]), + .datad(counter[12]), .cin(gnd), .combout(\Equal0~3_combout ), .cout()); @@ -1127,13 +1196,13 @@ defparam \Equal0~3 .lut_mask = 16'h0001; defparam \Equal0~3 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N28 +// Location: LCCOMB_X29_Y18_N28 cycloneive_lcell_comb \Equal0~4 ( // Equation(s): -// \Equal0~4_combout = (\Equal0~1_combout & (\Equal0~0_combout & (\Equal0~2_combout & \Equal0~3_combout ))) +// \Equal0~4_combout = (\Equal0~0_combout & (\Equal0~1_combout & (\Equal0~2_combout & \Equal0~3_combout ))) - .dataa(\Equal0~1_combout ), - .datab(\Equal0~0_combout ), + .dataa(\Equal0~0_combout ), + .datab(\Equal0~1_combout ), .datac(\Equal0~2_combout ), .datad(\Equal0~3_combout ), .cin(gnd), @@ -1144,27 +1213,117 @@ defparam \Equal0~4 .lut_mask = 16'h8000; defparam \Equal0~4 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N20 -cycloneive_lcell_comb \address[0]~0 ( +// Location: LCCOMB_X28_Y17_N18 +cycloneive_lcell_comb \counter[20]~59 ( // Equation(s): -// \address[0]~0_combout = address[0] $ (((!\Add0~40_combout & (\Equal0~5_combout & \Equal0~4_combout )))) +// \counter[20]~59_combout = (counter[20] & (!\counter[19]~58 )) # (!counter[20] & ((\counter[19]~58 ) # (GND))) +// \counter[20]~60 = CARRY((!\counter[19]~58 ) # (!counter[20])) - .dataa(\Add0~40_combout ), - .datab(\Equal0~5_combout ), - .datac(address[0]), - .datad(\Equal0~4_combout ), - .cin(gnd), - .combout(\address[0]~0_combout ), - .cout()); + .dataa(gnd), + .datab(counter[20]), + .datac(gnd), + .datad(vcc), + .cin(\counter[19]~58 ), + .combout(\counter[20]~59_combout ), + .cout(\counter[20]~60 )); // synopsys translate_off -defparam \address[0]~0 .lut_mask = 16'hB4F0; -defparam \address[0]~0 .sum_lutc_input = "datac"; +defparam \counter[20]~59 .lut_mask = 16'h3C3F; +defparam \counter[20]~59 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X32_Y17_N21 +// Location: FF_X28_Y17_N19 +dffeas \counter[20] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\counter[20]~59_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[20]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[20] .is_wysiwyg = "true"; +defparam \counter[20] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y17_N20 +cycloneive_lcell_comb \counter[21]~61 ( +// Equation(s): +// \counter[21]~61_combout = \counter[20]~60 $ (!counter[21]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(counter[21]), + .cin(\counter[20]~60 ), + .combout(\counter[21]~61_combout ), + .cout()); +// synopsys translate_off +defparam \counter[21]~61 .lut_mask = 16'hF00F; +defparam \counter[21]~61 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X28_Y17_N21 +dffeas \counter[21] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\counter[21]~61_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[21]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[21] .is_wysiwyg = "true"; +defparam \counter[21] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N10 +cycloneive_lcell_comb \Equal0~7 ( +// Equation(s): +// \Equal0~7_combout = (!counter[21] & !counter[20]) + + .dataa(gnd), + .datab(gnd), + .datac(counter[21]), + .datad(counter[20]), + .cin(gnd), + .combout(\Equal0~7_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~7 .lut_mask = 16'h000F; +defparam \Equal0~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N30 +cycloneive_lcell_comb \address[0]~39 ( +// Equation(s): +// \address[0]~39_combout = address[0] $ (((\Equal0~5_combout & (\Equal0~4_combout & \Equal0~7_combout )))) + + .dataa(\Equal0~5_combout ), + .datab(\Equal0~4_combout ), + .datac(address[0]), + .datad(\Equal0~7_combout ), + .cin(gnd), + .combout(\address[0]~39_combout ), + .cout()); +// synopsys translate_off +defparam \address[0]~39 .lut_mask = 16'h78F0; +defparam \address[0]~39 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y18_N31 dffeas \address[0] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[0]~0_combout ), + .d(\address[0]~39_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1180,67 +1339,51 @@ defparam \address[0] .is_wysiwyg = "true"; defparam \address[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N26 +// Location: LCCOMB_X29_Y18_N0 +cycloneive_lcell_comb \address[1]~13 ( +// Equation(s): +// \address[1]~13_combout = (address[0] & (address[1] $ (VCC))) # (!address[0] & (address[1] & VCC)) +// \address[1]~14 = CARRY((address[0] & address[1])) + + .dataa(address[0]), + .datab(address[1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\address[1]~13_combout ), + .cout(\address[1]~14 )); +// synopsys translate_off +defparam \address[1]~13 .lut_mask = 16'h6688; +defparam \address[1]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N26 cycloneive_lcell_comb \Equal0~6 ( // Equation(s): -// \Equal0~6_combout = (!\Add0~34_combout & !\Add0~32_combout ) +// \Equal0~6_combout = (!counter[20] & (!counter[21] & (\Equal0~5_combout & \Equal0~4_combout ))) - .dataa(gnd), - .datab(gnd), - .datac(\Add0~34_combout ), - .datad(\Add0~32_combout ), + .dataa(counter[20]), + .datab(counter[21]), + .datac(\Equal0~5_combout ), + .datad(\Equal0~4_combout ), .cin(gnd), .combout(\Equal0~6_combout ), .cout()); // synopsys translate_off -defparam \Equal0~6 .lut_mask = 16'h000F; +defparam \Equal0~6 .lut_mask = 16'h1000; defparam \Equal0~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: LCCOMB_X31_Y17_N24 -cycloneive_lcell_comb \Equal0~7 ( -// Equation(s): -// \Equal0~7_combout = (!\Add0~40_combout & (!\Add0~36_combout & (\Equal0~6_combout & !\Add0~38_combout ))) - - .dataa(\Add0~40_combout ), - .datab(\Add0~36_combout ), - .datac(\Equal0~6_combout ), - .datad(\Add0~38_combout ), - .cin(gnd), - .combout(\Equal0~7_combout ), - .cout()); -// synopsys translate_off -defparam \Equal0~7 .lut_mask = 16'h0010; -defparam \Equal0~7 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N10 -cycloneive_lcell_comb \address[1]~1 ( -// Equation(s): -// \address[1]~1_combout = address[1] $ (((address[0] & (\Equal0~4_combout & \Equal0~7_combout )))) - - .dataa(address[0]), - .datab(\Equal0~4_combout ), - .datac(address[1]), - .datad(\Equal0~7_combout ), - .cin(gnd), - .combout(\address[1]~1_combout ), - .cout()); -// synopsys translate_off -defparam \address[1]~1 .lut_mask = 16'h78F0; -defparam \address[1]~1 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X32_Y17_N11 +// Location: FF_X29_Y18_N1 dffeas \address[1] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[1]~1_combout ), + .d(\address[1]~13_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(vcc), + .ena(\Equal0~6_combout ), .devclrn(devclrn), .devpor(devpor), .q(address[1]), @@ -1250,50 +1393,34 @@ defparam \address[1] .is_wysiwyg = "true"; defparam \address[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X32_Y17_N2 -cycloneive_lcell_comb \address[1]~2 ( +// Location: LCCOMB_X29_Y18_N2 +cycloneive_lcell_comb \address[2]~15 ( // Equation(s): -// \address[1]~2_combout = (address[0] & (\Equal0~5_combout & (!\Add0~40_combout & \Equal0~4_combout ))) - - .dataa(address[0]), - .datab(\Equal0~5_combout ), - .datac(\Add0~40_combout ), - .datad(\Equal0~4_combout ), - .cin(gnd), - .combout(\address[1]~2_combout ), - .cout()); -// synopsys translate_off -defparam \address[1]~2 .lut_mask = 16'h0800; -defparam \address[1]~2 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: LCCOMB_X32_Y17_N16 -cycloneive_lcell_comb \address[2]~3 ( -// Equation(s): -// \address[2]~3_combout = address[2] $ (((address[1] & \address[1]~2_combout ))) +// \address[2]~15_combout = (address[2] & (!\address[1]~14 )) # (!address[2] & ((\address[1]~14 ) # (GND))) +// \address[2]~16 = CARRY((!\address[1]~14 ) # (!address[2])) .dataa(gnd), - .datab(address[1]), - .datac(address[2]), - .datad(\address[1]~2_combout ), - .cin(gnd), - .combout(\address[2]~3_combout ), - .cout()); + .datab(address[2]), + .datac(gnd), + .datad(vcc), + .cin(\address[1]~14 ), + .combout(\address[2]~15_combout ), + .cout(\address[2]~16 )); // synopsys translate_off -defparam \address[2]~3 .lut_mask = 16'h3CF0; -defparam \address[2]~3 .sum_lutc_input = "datac"; +defparam \address[2]~15 .lut_mask = 16'h3C3F; +defparam \address[2]~15 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X32_Y17_N17 +// Location: FF_X29_Y18_N3 dffeas \address[2] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\address[2]~3_combout ), + .d(\address[2]~15_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), .sclr(gnd), .sload(gnd), - .ena(vcc), + .ena(\Equal0~6_combout ), .devclrn(devclrn), .devpor(devpor), .q(address[2]), @@ -1303,7 +1430,541 @@ defparam \address[2] .is_wysiwyg = "true"; defparam \address[2] .power_up = "low"; // synopsys translate_on -// Location: M9K_X33_Y26_N0 +// Location: LCCOMB_X29_Y18_N4 +cycloneive_lcell_comb \address[3]~17 ( +// Equation(s): +// \address[3]~17_combout = (address[3] & (\address[2]~16 $ (GND))) # (!address[3] & (!\address[2]~16 & VCC)) +// \address[3]~18 = CARRY((address[3] & !\address[2]~16 )) + + .dataa(gnd), + .datab(address[3]), + .datac(gnd), + .datad(vcc), + .cin(\address[2]~16 ), + .combout(\address[3]~17_combout ), + .cout(\address[3]~18 )); +// synopsys translate_off +defparam \address[3]~17 .lut_mask = 16'hC30C; +defparam \address[3]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y18_N5 +dffeas \address[3] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[3]~17_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(address[3]), + .prn(vcc)); +// synopsys translate_off +defparam \address[3] .is_wysiwyg = "true"; +defparam \address[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N6 +cycloneive_lcell_comb \address[4]~19 ( +// Equation(s): +// \address[4]~19_combout = (address[4] & (!\address[3]~18 )) # (!address[4] & ((\address[3]~18 ) # (GND))) +// \address[4]~20 = CARRY((!\address[3]~18 ) # (!address[4])) + + .dataa(address[4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\address[3]~18 ), + .combout(\address[4]~19_combout ), + .cout(\address[4]~20 )); +// synopsys translate_off +defparam \address[4]~19 .lut_mask = 16'h5A5F; +defparam \address[4]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y18_N7 +dffeas \address[4] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[4]~19_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(address[4]), + .prn(vcc)); +// synopsys translate_off +defparam \address[4] .is_wysiwyg = "true"; +defparam \address[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N8 +cycloneive_lcell_comb \address[5]~21 ( +// Equation(s): +// \address[5]~21_combout = (address[5] & (\address[4]~20 $ (GND))) # (!address[5] & (!\address[4]~20 & VCC)) +// \address[5]~22 = CARRY((address[5] & !\address[4]~20 )) + + .dataa(gnd), + .datab(address[5]), + .datac(gnd), + .datad(vcc), + .cin(\address[4]~20 ), + .combout(\address[5]~21_combout ), + .cout(\address[5]~22 )); +// synopsys translate_off +defparam \address[5]~21 .lut_mask = 16'hC30C; +defparam \address[5]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y18_N9 +dffeas \address[5] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[5]~21_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(address[5]), + .prn(vcc)); +// synopsys translate_off +defparam \address[5] .is_wysiwyg = "true"; +defparam \address[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N10 +cycloneive_lcell_comb \address[6]~23 ( +// Equation(s): +// \address[6]~23_combout = (address[6] & (!\address[5]~22 )) # (!address[6] & ((\address[5]~22 ) # (GND))) +// \address[6]~24 = CARRY((!\address[5]~22 ) # (!address[6])) + + .dataa(address[6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\address[5]~22 ), + .combout(\address[6]~23_combout ), + .cout(\address[6]~24 )); +// synopsys translate_off +defparam \address[6]~23 .lut_mask = 16'h5A5F; +defparam \address[6]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y18_N11 +dffeas \address[6] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[6]~23_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(address[6]), + .prn(vcc)); +// synopsys translate_off +defparam \address[6] .is_wysiwyg = "true"; +defparam \address[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N12 +cycloneive_lcell_comb \address[7]~25 ( +// Equation(s): +// \address[7]~25_combout = (address[7] & (\address[6]~24 $ (GND))) # (!address[7] & (!\address[6]~24 & VCC)) +// \address[7]~26 = CARRY((address[7] & !\address[6]~24 )) + + .dataa(address[7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\address[6]~24 ), + .combout(\address[7]~25_combout ), + .cout(\address[7]~26 )); +// synopsys translate_off +defparam \address[7]~25 .lut_mask = 16'hA50A; +defparam \address[7]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y18_N13 +dffeas \address[7] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[7]~25_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(address[7]), + .prn(vcc)); +// synopsys translate_off +defparam \address[7] .is_wysiwyg = "true"; +defparam \address[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N14 +cycloneive_lcell_comb \address[8]~27 ( +// Equation(s): +// \address[8]~27_combout = (address[8] & (!\address[7]~26 )) # (!address[8] & ((\address[7]~26 ) # (GND))) +// \address[8]~28 = CARRY((!\address[7]~26 ) # (!address[8])) + + .dataa(gnd), + .datab(address[8]), + .datac(gnd), + .datad(vcc), + .cin(\address[7]~26 ), + .combout(\address[8]~27_combout ), + .cout(\address[8]~28 )); +// synopsys translate_off +defparam \address[8]~27 .lut_mask = 16'h3C3F; +defparam \address[8]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y18_N15 +dffeas \address[8] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[8]~27_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(address[8]), + .prn(vcc)); +// synopsys translate_off +defparam \address[8] .is_wysiwyg = "true"; +defparam \address[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N16 +cycloneive_lcell_comb \address[9]~29 ( +// Equation(s): +// \address[9]~29_combout = (address[9] & (\address[8]~28 $ (GND))) # (!address[9] & (!\address[8]~28 & VCC)) +// \address[9]~30 = CARRY((address[9] & !\address[8]~28 )) + + .dataa(gnd), + .datab(address[9]), + .datac(gnd), + .datad(vcc), + .cin(\address[8]~28 ), + .combout(\address[9]~29_combout ), + .cout(\address[9]~30 )); +// synopsys translate_off +defparam \address[9]~29 .lut_mask = 16'hC30C; +defparam \address[9]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y18_N17 +dffeas \address[9] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[9]~29_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(address[9]), + .prn(vcc)); +// synopsys translate_off +defparam \address[9] .is_wysiwyg = "true"; +defparam \address[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N18 +cycloneive_lcell_comb \address[10]~31 ( +// Equation(s): +// \address[10]~31_combout = (address[10] & (!\address[9]~30 )) # (!address[10] & ((\address[9]~30 ) # (GND))) +// \address[10]~32 = CARRY((!\address[9]~30 ) # (!address[10])) + + .dataa(gnd), + .datab(address[10]), + .datac(gnd), + .datad(vcc), + .cin(\address[9]~30 ), + .combout(\address[10]~31_combout ), + .cout(\address[10]~32 )); +// synopsys translate_off +defparam \address[10]~31 .lut_mask = 16'h3C3F; +defparam \address[10]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y18_N19 +dffeas \address[10] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[10]~31_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(address[10]), + .prn(vcc)); +// synopsys translate_off +defparam \address[10] .is_wysiwyg = "true"; +defparam \address[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N20 +cycloneive_lcell_comb \address[11]~33 ( +// Equation(s): +// \address[11]~33_combout = (address[11] & (\address[10]~32 $ (GND))) # (!address[11] & (!\address[10]~32 & VCC)) +// \address[11]~34 = CARRY((address[11] & !\address[10]~32 )) + + .dataa(gnd), + .datab(address[11]), + .datac(gnd), + .datad(vcc), + .cin(\address[10]~32 ), + .combout(\address[11]~33_combout ), + .cout(\address[11]~34 )); +// synopsys translate_off +defparam \address[11]~33 .lut_mask = 16'hC30C; +defparam \address[11]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y18_N21 +dffeas \address[11] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[11]~33_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(address[11]), + .prn(vcc)); +// synopsys translate_off +defparam \address[11] .is_wysiwyg = "true"; +defparam \address[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N22 +cycloneive_lcell_comb \address[12]~35 ( +// Equation(s): +// \address[12]~35_combout = (address[12] & (!\address[11]~34 )) # (!address[12] & ((\address[11]~34 ) # (GND))) +// \address[12]~36 = CARRY((!\address[11]~34 ) # (!address[12])) + + .dataa(address[12]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\address[11]~34 ), + .combout(\address[12]~35_combout ), + .cout(\address[12]~36 )); +// synopsys translate_off +defparam \address[12]~35 .lut_mask = 16'h5A5F; +defparam \address[12]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y18_N23 +dffeas \address[12] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[12]~35_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(address[12]), + .prn(vcc)); +// synopsys translate_off +defparam \address[12] .is_wysiwyg = "true"; +defparam \address[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y18_N24 +cycloneive_lcell_comb \address[13]~37 ( +// Equation(s): +// \address[13]~37_combout = \address[12]~36 $ (!address[13]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(address[13]), + .cin(\address[12]~36 ), + .combout(\address[13]~37_combout ), + .cout()); +// synopsys translate_off +defparam \address[13]~37 .lut_mask = 16'hF00F; +defparam \address[13]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y18_N25 +dffeas \address[13] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[13]~37_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Equal0~6_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(address[13]), + .prn(vcc)); +// synopsys translate_off +defparam \address[13] .is_wysiwyg = "true"; +defparam \address[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N2 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = address[13] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(address[13]), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hFF00; +defparam \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y18_N3 +dffeas \rom|altsyncram_component|auto_generated|address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\rom|altsyncram_component|auto_generated|address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true"; +defparam \rom|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y18_N24 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout = \rom|altsyncram_component|auto_generated|address_reg_a [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\rom|altsyncram_component|auto_generated|address_reg_a [0]), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .lut_mask = 16'hFF00; +defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y18_N25 +dffeas \rom|altsyncram_component|auto_generated|out_address_reg_a[0] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true"; +defparam \rom|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low"; +// synopsys translate_on + +// Location: M9K_X33_Y13_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a8 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h3C00000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005DB824E17CAAE881C1908A79F24B7D1B4857A981A6AF39DFF5A2FEE9141EB33592D8E9B82471FDDA6791810A1C29D415CC1A8FA03444DF0083F83506BA93E8D1A1856A768D73A08418BFB25A40001DD4833DAF33BD311BB45F39667627407EF59ED569C483EB3BE1B10551B1428A6169579293ED063CAA9C6ADB0433CFC15C33AFF04C710408C20AC28B5909A229CD7D1DB4EB9A44CE0EEDBBBD391D3128AAA3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'hDDE6FC8EBE3F9F3C3DFC6E8F07BFD31D50660B1E0B2506A533CE0E340C7C745CAEC4837C2A5FECBB94C1C969FFDDFF79BFFAAFDCA8D748399ABF75558ADD02F56F6DFFF29CB70FFD25A59DFFFED7B3F7E8B4CE6FFF3EF9CEC6BAE57ABFFFCEE647B2AFF5B87AA26AFFDD317DEDCFBDFFE1A0CAD3B58877DD2F647F7DF748E7CF4693FD3C1238FFAFBD7FDF567FA8FEF024F33AFD3AABC6B105EA80272D64895FFF9FFF6E3881C81AFDCF2257FD4F8ED5257D0E9B800726B6564D2B05012F76DF636CDEB4BDFCAEEFC61DFFEFB7E26262DEF2CB9F71565824FEBF3F7BDDEABB593F1BF746FBFFC353E37263FF38A796EF39E3FD7DFEBA7FFEFFBD97ABAF09E909; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'hE629BDF93D7F5B5BAF92FBAB477E9B315DB5A310CFACC7408DF9A544B1E57AF6EFEF92C2FA4D8D4E4AC86C277338FA37BCDD9D47782DB75EFF80781BCD23D0AFCAE30B9FE6AA29FFF6F72DA73DFE4F7ACD39687B9E69C5359E9B991F0246EFFBC5595561AC64787878F5CE14C664CF9EB0CDAFFBABEF1E83358371B9ED96E5069555AFBBD3AEBFCABFBBED7A5C5FE9BD0E6A91C6E7610042695EEB08D8881B1D735AF87DAE59FABBD7DEAF8717F2B72F428F5E37E5D6E13157B99CBD2D73B9C73C563C8B02C8CC39C64DDCEA1BEEB5E7353F93786145598FE634EF1000179B345725EA43CE18F187A1DE4DAABEA97963E3A7A96B8B7CBC095BEB7CE46274D9AF; +defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h4ED4AE2B1650D21EAFE01E7099EFCA3094FD4D705CF6B84AE21583E13385F8650004406BD60A023AB063D4E5966EA41AA997F5A49BFCB0657A9732D28EB8217E65F627A15E1057ADEE7B9E27122A58FB2B98B1EA560390C7E87715861814E04DCB76FAB179E9619BC7E7E9C9FD801CF87DBA1EA496E829D4E62861E1AF436A7585287860729C77B6C68CAEA3033A6E84D67249B594C407B39C68B4C1C97FDEFC6BAD12FDBB525EF4F87F4A23EC13CBC0262D8899A3A290F04F41C1324045B9FCEEC890579E95D5A0A546CCCDD48577558ABE7CA36EF67A70F6A8758BDA052D5B95DE707778B17C2379847A23AE5D4BB01F36F3F44A8162566D9FB15DE7CC83F7; +// synopsys translate_on + +// Location: M9K_X33_Y14_N0 cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( .portawe(vcc), .portare(vcc), @@ -1313,46 +1974,978 @@ cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( .portbaddrstall(gnd), .clk0(\CLOCK_50~inputclkctrl_outclk ), .clk1(gnd), - .ena0(vcc), + .ena0(!address[13]), .ena1(vcc), .ena2(vcc), .ena3(vcc), .clr0(gnd), .clr1(gnd), - .portadatain(18'b000000000000000000), - .portaaddr({address[2],address[1],address[0]}), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), .portabyteenamasks(1'b1), - .portbdatain(18'b000000000000000000), - .portbaddr(3'b000), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), .portbbyteenamasks(1'b1), .devclrn(devclrn), .devpor(devpor), .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), .portbdataout()); // synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0"; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "./rom/gw03.hex"; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom"; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 18; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 7; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 3; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 18; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1; defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; -defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 144'h002040042000900018000600024001080081; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h1EEA3633EFEA856D05BA968C1B3C30CA1788DD95D16B8F914DDDFC3EE5C69945DF7D7BF31C6072BFA7993996AB7DD2F3EE4009844CC9D6CF9E583AEC48A52F2904B57D8E0D755851232838F9B5348838530D7AF95411555D263B8CA86A5D29D7CE4B65409D6F04C5709A56C241C3BCEF07459A416EB4E8F3D73CC714F4333AFE605D53A5C955D5D1412F8361617A54446971FD187442A60FB04457857BECC3120A01FDC7FE2CBF038A61DEE5FCE2D10C8F35FBF80C05ABFF4B6935287B125E8D56F9FDFE7D64C1F4E1F5641845CD17E836B97780400C702523FA8E7C7BBD6F0666591A35ADD26B6B7E33CA56E9AB329EFA7E68F98AE7CE9507755C74C430286A; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h88537A811D4EF6CD9668CCD3E2E7A8041788DCA5F7E08AF52AF5276078304DEB75B74BB9AC3C1A492952F7EEAA0E7CF9FBEDD0FB47EEFDCC3734B816F355C913CD2E1AF14C30545297A91BED3AEAEFF8F696B5F4FC80BC6B1A2559492E9198E4A5875745B625C6CA7A7292332492D139728A689DA1AE78B6B44CE4F4A4EA5A22F331598B364EF27516CC49A4662C5E5C92ED140D96373678F833AE434698237599716B8CBAE2D3D061F2C3D6337AB435B5C2144AB6FA2F8BB51357801066B6589467DA6C480E6D19CEEA8451CEFA88FD70E7925B0302F877F87FA833FBD147E937309C08305A10187707E3D57DDE4931F1D9E97A8F378981ABBF8D7B6B7539C3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h763DD7AA7EED3F4AD4EA7491ADE6F14E6DBADD0F090A8DF34D7BAD35DD2275F0BCCF19EEF299751C919C9C13C6FB9ED711AC4DA7D947CC79E9B6323EF6CE62638CEBCB187AE5D44ECA689C9BD4E5AE544DEA7E90D186B9F335F3323877AAD54196CE81973CB555904419599375501366EC343561BCF83357F8823671393B278C1C387A7970C7F3E688673CF5975EE3E5FF105CFCCFAB725D698FB088B063063C7833830C7B2C7AFB8A8D203C312306DA0E72641FFB93D59B5EC84F44AD55F4B884735325ACC969B2EAE10A1478D866F667DDEF7BBF75E6958B6D02DC6D0F807660A229B98541E6FE734DE2280A9B57FCD5A9BEFEF7CDA5ABEB44FD73D2794D56; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hD0734B461A36980411EB2A6C1BE76029258777EF227A8F6E84F74C4436098F67BA611013110188547995B108BB2DAE76F423A0D98845F9248BDFA45E10CA403A5E2B1A3E16869E1D37BCE906B82F401CBD467617DB34D9E0C80B5E6E10063EC4BD52921D249E377D95CFAAA309EEDAA57DA85F55DBB7048A69A4C801013948B617F7F5724D40707E6FF30002982023020449B4680C45D1CE6D8EB30A061DB8FEDD6E630C15271E48CA801988654FB501D5393392EE765C1EC95C1E4D86F18A965372B72B484E2F2664B735B69A5AB532B086BA4C62AD6D56EECBDB6984B251454845BD5B243DAED2B2489B313A35C50252AFD3E0B76FEF342335C7F1321D92FF; +// synopsys translate_on + +// Location: LCCOMB_X34_Y14_N24 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout )) # +// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ))) + + .dataa(gnd), + .datab(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0 .lut_mask = 16'hF3C0; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y19_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a1 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h35C65240B61076066A23CE4CFC5E76063A1C2AE07DF555007338BDC080EA0C23082C891C76A4845096304A0D8502080C1198911998821D09C29CA830C337499236E0548D65FF9125A765F0220F6EB9D1B318244CC6CA2CBC9CEC6979C14EB28DE2E0440C6CBD61341FC178649A852D4A2A0627C688D905B882524E191E7951EAEF30312A73337CBAD4838F42A3293859CD169240D8E652F6D72D8D19D56DD7675939FC47C933E1B0AEF12A484454C247B00A6BEC5402AA08B5106E3065602454C80CEC08A7F5F85CE65326632B4C4F3920019A35AE2AEB321131046EE45B81D4EFD5995634050D4CFEC166B032B6415553AF0358304080D9DD0A2E5948593830; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h376E511217E00B624A46BA2E4CC10B729C326F710F24CFE78C5E63F3024B17CC5E1380C938A0A16C9B696272DE7A2948BE8AFE81310146B8AAE5E549FA27EFBE27929938B8E10530250877A4998D0DF0004852125C20CA8D4279881E41208B14198817644F293AC1946061117122A39D8841818C1389D51BDAC549181902516571163594CEC5863F0F56625E221D6B8180848C6B2BE24AA0AEEE5D187201CAAE6AA394A8644314895565192AE415630A42894D6EF21343903B348EED8642F2310644C9567C0BF9911B870B989C59330089AA4C8065AB1B11132213EE0FD830817DE6C2ED45D76325CA2A8E198859334553AB02945CAB1F17C142288008073004; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h20721F982534A8179F13E2C6328CDE7D2A73087D3A9314419022103DFF7677769FE2D1F27443253D58403577C801AE23371F00290A17E1C4A40258BFD204230EE9969472A81B83113144528F831AA6C3221E137C1E9C670E26809A894013828D9E2DBCBF62498A769893D7218899245CD18AE49F0146517422EE475D520029ED39BCEF6BF4D23532957455F1C80115524179D59C4C4534DF7296991146CE24508366123AA809AB30B47977571C5D70397A93C723106D0A2C254714359DC7C9E13AE624C94932927924D20024CD638A05C8620023319662D80E05805625BC4A4006C78011F78D8B82E59F0CD4B32D6801669BE3EB0B96960DFF152005EC7C16CB; +defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h9C8CA06AA05B63C89A59A3E4E80807B27A70B0006624C4AC4A0595CCD8CA20824CA272352720BCD900A6D79BFD9D0595EC0D044ABC8CC28E9AE946E3D2000A4EFA4F91915C6AC9D8570C292F10848189906127BCBE06FFE92DAFB4AAFB240D88DDBB7B207EFA1709B05E1C4801BD45625A36BB62220506E171891964A31BED2215408676F600F490FAA59B488C7998CC8CCC28922AC62644EEBB432EEECB51B16CDEE7468681D6C31E4991CA3736E9ACB7531EC6D8BBCD453718101EA25D79278C6AC955A8A6140421573E413CF5A80AA1436D8B4C31A2AB26D2A61CE834248BAD5751BD429B4F61318427560CE39D49299002165212181064E24FF0093B997B; +// synopsys translate_on + +// Location: M9K_X22_Y16_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a9 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h420000004200000000000000000080000000000000000000000000000030004480000000424202423E1E3E02304C3C0C3C7E7E40403E427E3402421824347C1C0400280000003C3406303220344C403C0400100010100000005062742400000091991809FB3BD9084A1241F5015988B3C506031934089E0E1FA8043DDAF2CC07D94A6F2B1D133C211222B22C787D430E45D4C53282288077DFC0F704AAD55127A2BEAEA114958D2817AB1213183A4E1A15E3690A08A33B429284A202011A1243D49CACA1C0A441405A720D21A0921294045F746229E287B95E956AA3DE0CA3B7A019C8039C4DDA6BC99371248CC6008A54CB84503442C4F91309238ECB252072; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h81F3167814687CBD683E54D44555E6C95B5F2A72C0C193C6110C0221A448D0C9A0D8E36A84D5C61285128845215F8F8821C308E368283D8E2B42989C04A8B51354E09A38775020189010680840800297C31282442326D008D1F2351A89FFD7C16087F8B130F04418C0A1C082FC005843F5B42CADD9455ADBD328C13219110DE100D988737BBB44C414210118C673B0C1BDF76C499226F78FF41A0AF7AFD3308AAA0AAA22B1C70003F542A66FD1F1CF9D4578315F8C1C6FEC3EDB9B322CB204821A94A248414CE030020F207BF040A06A3DF993DEA3823423F405294A52014565100E0A7211342DF02958046899EEBE6E491299A09312778193FEBD7FFABA8000; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h2C05EF54A3C0F7F5F017E03F5800377CCF6E493C84E8F56441831087370A084801DEC1A54696B9912E8B0705C8587D4F7D36C8638947A620554CC77819B55B7A12D552A8A0496EFE3AAC6F34739A94E798101823148D811212E9A349CC219049527CCD419525AD29AB7D372C0B56AA0A065F8BDC905346478059EC82801920687FF29C990C9E66273CC78041192D03081CC62A8A0D8CB4D9CF2F2558131A78B8A807C3A1110211AFCA2A142F0BA928156D142250438143D339E4E2079F298493C08C4847914664518E27EF7EB9C870A226AFC35BEDB651840466400D4B3C0F877740114D6B08228BCC693FB12CECCCD2461586069445ACFC910B1241434622B6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h5FFE6AD3343986C4103935236B6E6E11B940EF46A8FC06E6872A6929D50DCDB75621E625522D34519BF2C353F8AA030B9109C2F9686AD3AF57AF3016D9160354C0BED5FBD379F904A41BAFB6BE4EE9F208058229DD0C354F034A6C4D8B6C16A29F0120108829220B230F44550832C1022530CC13C4C30D8254ECA5200A1941266EE48A1CA6430860DE613153615CAF4C8D191004CE9C6105D8C6795B6484467D21D9DC46029B8376E97F2C7BF8C3A218EE79DDBCF886B2BBDE702F71B38AEC6914E5DCCAFE50CC13922A5B149C598A621F80C24D215291228844E7F33F9763C6639303AE5376F664C7125632C1A280CECD5740C77849D937472B202579964F60; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N0 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))) # +// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout )) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ), + .datab(gnd), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1 .lut_mask = 16'hF0AA; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y12_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a2 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h77A47C739FF6A22B8B5CDC49E748E9C739BDE6756DB4D22437E74183E12400CBF7D3C6CC8C7841AB49CC538E8A72F2E73C64D3DF3662B19C07D7D299CBEDEF3E7DA5F4A8458A9451315B681ADA9AB0D63218DFB77D3353C32837E954604B9D98144A4566F47B71715BE6CDB8BA64D536762E9224D70F9A5C374B4D1CAB8DF527027170C5DBCC2B6AD72B8E4CCC94DAA139D8BA64E3384337426E7F274CC88A373AB1F9007B8A7F2936D16274F9BF8B6BABD48FCE74047C1E738C5B303E815BA720C76D6362915156A7671331CE657011862E594E46A6D99392E2D640D766869389A4D43867379AB880C1ACE279E451CB3A9063A0B320F65E536B8EEF9CBB9C76; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h9A2921ED6AA0CC8387B267B9E7A182720833CEE061E6450C8E4A72E3C043F21A0AD007E832124E92429C091D167806C10041AF32DDE13A669990457D098CC2FE3AC884B1E69101135CD080022451F20884CCB9CD203C141402A5AD293C3BABA95ADFAF6726384795A7656B753D2369B9EB5595BAA722012DF8DCFBF15BF46D6EB755D1CBF0DCF6FD40BEEC16EAB4A6D16839C98CBE9DBB437C69FB709F8E79993B9DDFE4F823D6E124B75BCE9B29F799F926619184B6C1178389F07349210436293A130C900FBA4EA70D2BA25B343C5B026D8E8766A4E4267CDAEC99E830D2307D94E6ED80D6722F3989B91E31C63B64C363DCE71A861C14382E270FC02868C7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h386BA04E797A3F8551DAD9D24A8D259A03ECFF5AB81B1C31DFDAE10100544F8CF1A8CCFC0C7A15BD9E7C2557CB00BF2584E16AAD13D7EDB525A85ABF90C0136DD195D748900C29DF7F381280A9738CDC3BF5BBF937D3A4D99CE2BCCD97CEF2C7F00030AFDB7F22E68CBAA4D9BE7633D3B53E90E4B124422A2A4454BACA5A8DC9352CD1DAFC910CC504334DF9E6F1F4F30161A36293CC5CCF1CA13994ED29D34A5699692496359B8E67A7E74D9A0FC504C8465638CF74A0AF9185921A7D2629893091900604017933442359491FBAB63F346F0C5EC8E3A531984B09E605A30A0627271C28420E47B8DEC74738FC3EDF9FBD40EC09FC7B4D3A1475BE433705FB5F; +defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h973FED2E9BEDBA474B70B121A8D60F3B4EE3F1A238FB3B730EDEEE74EC632DB4D7779D7B79D1C75DF87378E98719C1AF38B1B801C71D180CE86370AE9C2BF38CF84DBBB9878C55457324E92D3DAE91D729AC76BBAD4C6EECA74DAB5EE9A175EE34ABEB9DFAA48538A57E3E5C158947081CA41402E8E65478737F73BB629AAE2EE51D405CAF70F622DD4599602D7910DCAC8214B2A42025110593202C8B164C8DF6369572C3BB8AA1984A8D12F776E224ECEEB21F97FCD6C0CF17A044EC2BBF0571A553CCDD8ABA79BD27B7AF735ED2D34F1EF3A81A160C9ECB1B1FAE6EDEEFF99E28CC30C7C2553DED3378D655AD194B2E6C1BCBED700F6713D960F33E4C361A; +// synopsys translate_on + +// Location: M9K_X33_Y15_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h8102080042447C443C0C3C402004FC1838787840407A00707C02487E444878428008004042460424402040024A3242124220044022404208520A4A24424A125A0A1028440000524A0A4A4A204A5240460800100010540042002064547E0600001FA9BE02B828694B8A82CB8C8158226808198E9EC6B021F07A2098D5E0ECB639D2B1908129B6A2D646516192D87593189D8B2B26CD6E16234C1CC90AD9831EBD89EAD271ECC39A80507716BB49626B743DFFCF99576C3FAC889860E46618ACB79EC30EEDE42EB1E31F3976CA23243179FAA96DCD66D51535351770D410DC8531866136E6184518410368288C446EC63A4FEE425019C244097049C2B2DC8D93C4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'hA111466C9493A2A7CA2204102414CC798BF0EEC2995A4814580BD07585585ED92E5172E82E845070000A846100500E84EA1803B8B07B99E1DC75BE6419674597B38F54EB9091AE3320201EE395AD63902282A031CE3E87CC902954AA515D5D6B6A855EC94CFEC4E0172C59A7D054F8F9F4356C312C204E40B05E2059407C8DC84683814663FB910969D1D631A952B381B7F635A33FD38D5CF15DF47D057F7FF555B555C2278100000A24804D7D98EB98602733818A12094F281287422CB40002464C92242004E0AE8518E001D124A7628010115D23C30462FC00A014A12133582A191E00538FC8A5004036A959ACB7A463D23E419EA06B744005385455A71250; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h6C60009CA281AEACDC1762945981B869F93D683EAF4AC7EE52412E85B60B91CD03AD0025F0D509F63202D877ECD8BF8005451F7BD346CF9E17B36F1850A7D80A8CF14A288EAE3BFE00FB2DB45080D4A50C58263A3B398DD51AB9CB554ECAA7B2E73D9D6D2C265859DB844C2C1952AD10241100174FE0444E6707D80A098D8585AAAC4802B74190FB007C0C0206186AFC1B3A2A46864F26118ED1D03ACB1062B7315502751655F60070E6B2C50609369611365AD1E3352327320331A51818030C7D8C4C59396600DC0C420495A0D987501490002BAD38012E20620D556A230B1796450B74E95A860FF3E434C65F1308F16F92395816B914F0CE870C1323347A4E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h7FC8531A7A319F3EBFC1383FFCDB0E09BD288288B078B4AD220B6FA934CF6187D972662C0D31E34E63B31CFC6EB4B35A69B67D85489E62EA99899A94F6800FDBA5D31B86A0288D29CE2EAAFF86A6A9F7000082293E6BB54F06E98ECCB199973EDA00FADB1D3A630BA18050635DE7DCB13B9B86E0CE6E08DC46331A352F716E3C441A0CC068A0823F8668A00621B779DE35FEC004050469F34866AEE766743D8C00FDF3B9F8DE7B76E97F8D32F0F39E4CAC68D9BBB68EA3915F6225F932CAAFDAD6E60DC661155EC9E80F8CEE659F19CC554B2C67C33EDCDA63BAD91B7D1842A7177AF49DF118FE47ACE3344964EBCADCFBB543F7729CCB340866D1157B6CCDDB; +// synopsys translate_on + +// Location: LCCOMB_X34_Y15_N28 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ))) # +// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout )) + + .dataa(gnd), + .datab(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2 .lut_mask = 16'hFC30; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y17_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'hA504087E764CA02840304044540424244404044024804008A40A54484448544A800400207E4A0818204040024A1262124210084014407E08520A4A42424A1256522828280000524A124A4A7E4A527E4A106010607C38003C025408FE2400000087857B4051593F8FEF8A4F84E99E6FCC30DBEF9DDB582A41325A97B1EEE4166FF390FF8420BD829D1679F5F18B57EAB9C5CFBE75ECF7F3730C105ADF74BA7D7F9159D64BD7F217C1803F5B1169B463FF6C6EC899D6482FBA8E6B53DCF12F3BFFBE72266D55B4E9E5887FAF8840007C50220105C908100BAF6FBA7BF97E6E020792ADFDFBD96CFD77B36CF30CC5DE43A85FB6F0020203478F160F42F9A061FE44; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h812017671773A9EE08641F818054455F0BABE232D2AA00081423C0BCCE1E642C4B7AE34419240F3C0170E001D6CE75F0475D5A8A9012B9BD97153AB038EF6187776B42A5FE80BB5AAA2A550A58904A1C6DC992952AB4532C6CB2F975BC101356F70811E17D8C73F1D9BEF7F7E82EFAE6C2D2DB2126004D81CA67DACC344F6458C165510222E12BABC9B940EB70182EDBEEF007365AA980A2002829A05282A2AAAA8AAA32A2C38012BFEB492278CD27651FD91BDE452EEF054801275AA0D49D9A896B7EB5FD69B679669CBA00AA9A431956A3CE676A9D7B50D84F3FFFFFC4AAF735995E3ADF9E07EB861E3035B1EF3EF935DAFFFA1F94FDCA5B803F14101BE318; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'hCE21FFE0D222852612C7A87E8DFE961BD8CF052D4757559DF3ED2417472384AF04FF86DDFE9FCBD3DC2A4967F492CDD5A8FFBD9857306D8B07F3AD96A6138C0360BE688D11B16D7936F4B55E0E301BAD6A96802B5719271D55D5E93FED5335EF86E8AEC1EE37F6F5FFD77F204F5EBFDA614C41C1F85C32FFB05F2881BF7EB1D73DDBF48E39F1AE9FC0A7CAC2B4515882877D84D415C7A00D91E87F57E95B60EFEB9963425C951C00298F26A884C3AEF0DBF539D04E867EB6FB957E817C230DFEE3BE607B3FAC5DD39FB436C5BB7926D7FFF03EF787FF563C3FEF787919A8383DEF3142B9927BEAF99BCFB066319F5BDF2EFFB11686607A73BE9CB85CF6EC52D0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h420539B476E305B8200E47DFAAE8D5D1D0724DCC3FD72C4F8DE54622A1DD1BA78CA3CE9F24BEFA9E2BB9D89B423C327C8E050114401A62FDCD2054E166C0005F7941B61372AC884EE60A372057B59CFF30A6020B875C06E7C5FBDF9A91F8F0588ED67F67AA66B0674CD240410F613700B8DFE7F8837F88FF4520002E4BFD7FA2768008002000002624793100811F43BC315A6004052671392B47FEB7F5DC90E62175C7B8FC48FCC916D46F9315DFDECBE43E5F03D7D27F97E09E4700AA694552A1FF3BE5E159FFDDEB2FBECAEB87BBCC5FCF6E23D77E4DD4C9DEBC93C10F636326FAFE3BE30DFAF7B9E7A5FFE44BF314DAA1C1529CDBFFE9D94EB11A9F68D4DF; +// synopsys translate_on + +// Location: M9K_X33_Y18_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h7BBD7F79FFE0AB8FC33758D1C1145DDD6311CF69FFFDF62EDD236FC6A0358FA2B4B15EB89456517DFF58F68BDADB95B5F764CAE7E7C7E7D70CADB8FFD8F9A72BFBB9EB400590D7F939FF5A70A29817DC2CC29B679B2D7146BD21D47EF06F7D5EAF72F66DC666B0726D66FD941AD9BC6D758D5EC24DFEBA64871D6B86D37DF1DFBFF05FBD6AD8CA62C6CBE43BDBFD99E9EB6DD724D235FBEA9FE7D6767D811C40681A00AF8D864D8BB6D2A0916C8A93250A76B8A977F82E8FDFBE68F8E0F8DF237CA976FE488D1069D687A6F1D68A70F37CAAA367A74CBB75D3A6FFB4B1E8D4B7F7F22D2FE1509BDF80E6DD7B717D7E9C6531C3A86BE9F1D7A6AFD5BFB7A37A60; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h8AB3B7FDEE7B9CC735FCCE93E3AC1AAAA691AD6350E57F1F5773302B6F36F63D130E0574D6BB44B2C0D7A907702A748D0BA50F8FA5437ACD3B343C35039F44D19CD4E55E6CB00410842B02A7FD105706DF9E2A1FA025005632A0CC080400D280CCCA0665222D038CC873351A21B23939A98CC08803282189C8440D40CD40462421A40982C046D22C10146484345CAF7BC828BFE79DFBE3C631CBF660C487EBB759BD7F8DE9E0F27A65DE5245BEB8F7829C36F0D136168F97C2BD77D649A39EB4DDB3A42AC80797FDEF4DE3EEF7ED8C7307E4CE6A6317F7BF25D077BBF03AEA3363B065F7D671322D6BFB2B8759433929CEC27E3FD7741292A4A5AF02703CC4E3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'hFD5CB07B6C729B510A78BEC5F7C7A1E7809F1976D0DD3615C1D27D2DF596BFE7A8BCDC2E6655185CC45008B39EFD1FA6E9F5E816114F93E1E7A2A27C72C7349F3497229CB9044B6E7A7861A04A712AAF29EFBD393727F1F3FC2AA1E6CF571457F0A09C47F23F20FE2AABF5FD3ABE6167E5FD36E1D9735BBD5375C1F79BD0424ECF133BF47B9D3DA46DD6DBF3A8ADCDD3DF1176D2FE23447DFC65E1DD7BF3BE5E1C9DCD8EBB9D36AF570CF25CDD16F645D1DE9F9EE575E3A2B91D5659FC131CE3DCD4560015805B13AC0290001EF8261B7E4EB867C828D9777FFF47B6903008DDD7D77EF5E2C6D7220BE64B3C6E9EF22AFDFCC8005C2FFFFA3AB9AD1ADFC0AFE7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h06ABC52D5DBEF57EEB3311A9D85D253B44E250E1566BED57C6DBEB2ABFD1ADF6FF4DEBFBDEB376DF68D5EEDB5EB4D5AB5B79745D76CD8ADC59CB30C8AA33E1551D2FCA8DCB43C5356BAE638588C302868CE1161CACADFEF7696F8C3AA82EC16F47A8EA413A2DCF09B996582318DBF3C4711871B3BC0404EC45252A485234A663C1FFFB3487617BE24FD79501DE05F1A341B89EC82FD5702497FD866639C0DE08B383E6E7C3B310E1F7FF595C5DF6F0E9A9FFFBE16D3FFBE82C1E0051F1E060D500812F408CC6501331852531B04480021D9220D4903A41404312032840153FE9CC8070206B8245AC240020752EBC2BEF3E74AB288F360C239C4AFAE93F68775A; +// synopsys translate_on + +// Location: LCCOMB_X34_Y18_N0 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout )) # +// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ), + .datab(gnd), + .datac(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3 .lut_mask = 16'hAFA0; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y18_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h35861A00A6112A1481AF1A50A6004A05291627227FF08229B87389E08119A28A7888672DC999B7046A61E60810A7434450E3D33E330F321A18E8A120D1EDC8623DA2C64840C2CCE811522B42008095E5A456C98F4B25EAEA410610545024640CF10410AC463BF9349074917E9A74A12830EFA280EBD3131E484A255D0191C6852730A263DBCCAAA88712242B3BE49AA5338990229B391158C726BC7EB4ECC32308980020680249882691A680488292310B4313CE87FFCD5329A64B708CAC8533316412C4900F646A36630261DA093053D98F19D2C5B653165D4A71AA5682B29B89B6054CC727D292805705A93268676A31111371390B240EC3CC85D331813EB1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h1AA1C248D293110CB951445117D9B6AA500F65068B8CC508BD00184F8705B010A0CC46CC9302649242CE08191634113154562B149100204551178DE805D98EC8A2E5A64B241400267194CD524499BC01D31058CD18684A817A5800B65143281C1310B00A49902C0104004C654E0582040001103654011012021912281216B000C653A0510A1B00C36AC88058CAC126E14E198DFB07E81C3F41510BB08F8F851C3B9AF0147BC1F730B4E91D9D11C3A8F1B82DF19988ACC44072FDB17B4D81882E9DD952B29003D7767BA581A68BC41C2B16AD6EB57F1D048CD4E464190D25ADF2C194E3598360AFB031A1690F4625BB628363B4C90A400E3A04DAA70DA0CC4776; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'hC82B30671933680037A65978674DDEC2D30EEEDA78F5F2A1DEE660FFEA11B175DCB42E9277212A58842051A078007109A0D820166B881042600284403143048295D23A0E191EBC2134B833D53D37E42B05018289A10300A188E315CE98640F548A370D60A0AA3E7288A0B0869FA5E703D1AE17C0EC276B2AFB747B550A8B41021620D1A60A901095D12A0973B95E20838001330138951361967847D42901910A3488480610A91A851E84FF08783F81AEA52D2FDC2200BD2FE81C0357FBEC1D875686C6CA41B2224C88D8456C1DBF20D820A6649774CB11B69933246E9739C998470542C2E3C783A4C24767084C52DC209D60E95DBC096D9A0171A12D5AB99BAB; +defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h17A24D2C636ED2478B5AE1C99D40761B1E7AA6A89DDD1BBD8DBD223E70531BCDE90C8E38C8E0478AD8B388F94891C9673A50BC32478E083074657E8E0EA53BEE861F8BC1993560946D92D1C0C7F046A245B5849CB751FF15B97FCD50BC7B8524C13E7C640F3645082248D1CC14296E30DEA3057B35C641762CD00D40DABC27472251A60725008AAA056591C4000BB48C0BC29B8034A03400027B84769B520D9196968460CA3388A03ECB45F2C4B70F1829221000FFFC7FEC346F079F13079798EC2A08157331C6CC0E30884244916A0DE26D4D22454091290404A492016887E2111F830F9851184101370588A06D3BF9AE621A5F4E632A6799C83EFAAE06769D; +// synopsys translate_on + +// Location: M9K_X22_Y17_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'hA50276000854A0103840403E540424244404783E18807A08A47C54484448544A807E7E10005270182040407E4A1252124208084008404208420A4A42424A125A024428106448524A624A4A24425242522060108010543C00044A105424005E0031ED1E0529E507AE2F6FF1CD51D4C772A648E65F6532C28022061303F06C36CDBD319B55CB8E626C20E46C93C1463A0B1CE594F0ED3B62330C104DECE46CA6CD966B1386612C7B43980349408F36FB64C14342DAE26CE4D8D5E791388729D743B09A27AB81D71A14AB3D24E385B602248476D00249239514B58D3098504ACD119B99E9021B650A69494C22600667473128DA5010D2195982823226DED0ADFCB8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h5861917919344A4685CC0990862A11324792E761B6D41C0FCC0838C1C27211A2453FDC2219C225E421B320085A8FBFD0C42135B16448DFC226E09B3438A740C352979565817114DE46462844A57F7958873FC4B255C8AE549BDD1A87415D5018F88D5002628FFD13203066C850F10649F21319109208387641120B362124803F0678522BA2812C1454A502ED1A59CBD76A034756F5765DF7555F57575F7F57FFFF7FFF7D5712524D4A30723514B2B3064A84B4742D48415281863DDFAA9D9B7E7BB16DDB96B7845371C30B55DB96C8F6EB4B453242FF6A4DF84A76B5AEDC88A68DC6A06905054C8C36E4199E74638E6532965218A965909BA456000451343351; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'hE2975A2686A7AE0288F140141B698E2A82A835F478453A1D722CFCED12859FD735188757AC5A42DEB501FE010586249AC1EA60D08F74CFA5086EC78FC9190C056059E332C311521E6522901852D484B423A98816C9B26A08C92368E9FF05524502288A804612A2A0A102A418CBDFBA554499541660F8124640110101263142892A086B442661015380041594608092D9CB919250100A37DDA3919A1427F660963C251301FB2CA45562245308885131119115C652B2493252340201101942D26000CC60799124A8520C08050122171281808058018C38A645D07931896B39ED259A22242CB58413089465B246231330D806105010035100B08761A08506094160; +defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N20 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ))) # +// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout )) + + .dataa(gnd), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[4]~4_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4 .lut_mask = 16'hF0CC; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y15_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h990442000864A0284030400454782424440404007E404808A4005448387E547C8004420800620824402040024A1242124204044008404208420A4A42424A1242020028008000524A024A4A284252446240001000101042000054265C7E0600007FAF5CA001C181BE0C02418447B1D88BAA85409896BC7C0E5FAC2529CB69A4038E2564731F88FE730045956C357C5ECF7EF8591DF2A8ACFFBFEEF268CD9B51238594AF691A9B8640983B7F76AAB97209EA6257389992FFE684926E0B19FA338B8489D73811171D5C9FF3DCFFFFFF8002000780101F3F4035A0CDED99F79A4775854F179F7D7DBBCF81B2F6421FF684CA6AF85894D29B9D3ACCBA3F27D9DC9911; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h5B438D714D4E3DD115E8BD1286EAB5FA1D71BD8F4508BD4BDC8838F9D27B552259BCEFFBB68A6FF529B3B0D92970010BBB6C7D872421210E190E1CCC47A485EAD2F8735647315839EF6F683C64773FC73464D5FE354936D50823A5DAEBEBDBCC6CAFF2622B8D518F63C6030424188FD357718970D25A30CD0731E532DB23002D02C12B12378356DE2C52041CA7A320C51E0D7CA9F5D575775D57FD75DDFDF75FFFDFFFD75F145247F03A0AE7F1E1EB2D5A99D2444108C6A5979B7CC26ABCC241EA4C912568003BB493CE04FF086C188980052BF6ABAAA2FD5D658000011277EB924C10EFAF3CB9B62486512344C61ADE6F15AB67F335A52513FF05AFAEEE8400; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h0C840083AD485153ACD3C035591630199B8C096CE4DC557D6D55FCCD738573D6E0948817C496E9DE8EA1F88F627B7460106691CC452DB9799E59A5D003733C4EA1BCE33AD2D8BE40A4E5BB7D7BBEC2CEADBBC8B6F87A4A56FBE0B891DE57E4C64EF9AD87727C49CFE7C5DE942B72AC7F6D97DE18920777FDDEE9EB11122A4E18F5569FDE08906765428FB9E6F89FBF0DEAA6064637BCA63FD02E273E5557F0548662C97BC2E8D3FFDB26D23E87BFD97E635A6560CFD93F8EED26E30C70DE8633D6B97C86DF7D9BEDFB99E36B6658F16C6DEFBDD5DF728D6209C852C37FE67CFF32EE4CCCECC64F7E6225FC99EC64C3B6DD7DED0FD7CCEA3BF09A006ECDD1009E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'hA9C9CE3AECF7BE27C000000A8ABA95251B309A60B9DDC19EC3E391458CBB53CA00A85E3C5AAE2C49DDC2F6C7B013DACB319A769818A1081A7389F711D76A09BCBED23D9A99FF9B77183697955D76BF0E0008822742DA45B883C9193DAF09424501859565800698515E10A8189EE9B323E35CE7388D73C6E7A50D0DE6739C73AC538D134115D860ADA57B5B868E54393B1E31E762062577697D57E8464340420E9434CCA34CC9A1CB1FAACC56168071EAC113F5265D5F6A45A098D604A820508C4EA47F9A7E46083716911B0D585CE937B530218E8D2AD3777EE7D3B4BC56C29ADB46809D15D185F8809229B150C29C8081174CA6173B99703DA466629005C604; +// synopsys translate_on + +// Location: M9K_X22_Y13_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'hE10F8B8C100323720BEBBDEBB81DF13FF97B252E2CB4F27BA091FBD0002D1A611E1EDBBC716D44D2912B80041C44558060CFCF15955C0D780DD5E71393920844F25E16C87C5D0308EEC52C011514BBC13AFA1028924D0C7CE738105BD47A10AA5B5C1D9D4193E4339F492B0E1A64E13AE35BE6B67AC8057BDACC155F14E906A017A1841358335450D4B26CD2A21B3D8F2211080B81EC040D7FA0B51CD48008112508062020A02490900092D2040259108806A328F4006D2AA514B42FB006ECCCCB9A360865678449975A8AE72B5C0F7BA800C1B5DC55D7D6FE2EF4EED85D00AB111821321BA426A4FE4956B43595832C271E83E060341AE5F2023FC808177383; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h1A2955372D510AC266A5445146E27000020C320FAE1557E37154040A13202DC6F40B840FB9A59B6DBB296562CB6220EFBE99D2776A202044D9101006FD221D305519198C859000004012AFF4FB060307C92BB732203BFDFEFFFFFFDFFF87FCFFFBFFEFF03FFE0FFFBFAFE0FF80787FFF7FFF83F7F87003FFBFFFFBFFFBFF0FFC0FF81FFF7FFBFFDFFFBFFFE1FF0086F3141AAB6005810A0621595A893F9D85983B9254954341968BAC8C141C90938C05B2C9CD267E11650407375FEDD6A2FEB346AAF6CFDC0791AA97B741995A3B3981E06D1A44D3711955197BB9910FCA20744915C84D6C24BAF53929814CA8A4697E8F4201145AE7415DC122A5F010436107; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h02E84F969E3C800AC610D276182020227809001A50DDDBA3487BB6AE802BA06509312DA0E620656EAF24D57C08FFB14D289613DC32083803B84DC6415FD5EDC000300A8D128FA20030ACCBAFA237B7024504D36A4BA26081137F059E78991154FE2AC2A884A8CC7FBBB21C851CC92B12E15593C0C020FFEE066558590E882D5B67459F1A8C3240FE4E6A8D028C0C088FCF471D400A19B38211004DD122212288B111114514CB11840E04828849C621392041163C00808C67223422F00110201DD18FCFFFF3FFE7F9FFFFFFF82C0B422D214711E08904524A069491774E663F48F665955B4E2C63DAC0078652D10120900298F7EE380092442AFD400BEC43C003; +defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'hB5D49EA9D7036A45AA9E870B8E8016720C7C3102AE925262492C84584942D209042216E0216C85B8912250B7157D5955AD406CB685BBF071B47D5193363C1CECAFE59E91BF11498940A0944996D47EE8D7E3A4EAE611AE19A965D01BA86B55E9C52A6A379A382C6C265FB0DA01396D0800C0046405C06F466DD18C4DD7655CD4E7622EC485808C841D64B737041FF68813B149A41531A0A692FB14AE2E5B49D49CDCADCF90E7BD88125BCE706BF6D04AABFC1C001163DC6EFF7FD3230303030000000000000000000008400000000000000000000000000030600000100007E00220000000000000080040004023AD496997B8C0077B886EEF161CF2298A091B; +// synopsys translate_on + +// Location: LCCOMB_X23_Y15_N20 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # +// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ))) + + .dataa(gnd), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[5]~5_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5 .lut_mask = 16'hCCF0; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X33_Y16_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h4200420000441C443C0C3C00480018FC387C7C000000007E180038300000204880084204004204423E1E3E02247E3C7E3C7E7E7E7E30007E3C7E7E7E3C7E7C3C0400000000000C34023C2E302464003C00000000000000000020460024000000FF991E65536D2D8D9C9B4DB081C83A5A881B0DFDE2D72DF0FA08FCD6F664173D989098D02025E0F6043B4B9080F4923880C3A3B02D269E730C3DCC423386DCB98B4AD0C5C8D6119602E5121008325B7457090E914F4876EC8A18C664210A4C2392C7658400073421047C75FBE7BE73FDFFF05FEE07BF8AEF7F1378B359E8C61F8F692C2218C98A4A8748531986E7C770D984E0000C02060C000C0DF50F68A580; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h0100046606572583002086010800054C0F2DE8371AC0000A9003E024840C7C0806F6612D770080980A40D293FEC069F16CB2164CA033C539F69B37741AEF1CE3662FF5DF9CB107BB23A39EF7B95E7372200448DBDC18F9C0DE0EF379BF49480657781E91788044213E091339886F337D0612CA646CD48FC58EE77EDD7ECEC466C744FD00E1A7F9E9FBFE4777FD50ABD11F0E57FF4808802282200888A20AA88000000008800AC11D556264251ECFA68C056FBCCB040C614A6850222300D2F6FF59F878FCF5689FCFEF34BFD52FA2422A56A3C113409F7813007F8D6B5F80FE9D7FB1E62675F7C2CBE01032DCA16BADC570C1CBF7ECBC4E7E6C54A5D4550BE1A8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'hE33CB578DEBFAFAEDFD530DE8FA1992072F31B116644B18C72F9F44116C79ADF2F3982C7BE09AD4A32196807648A2495ADF98FD2B16CC096A5E25F5BC811C953CEC3000F432029B3FE3F211712944CA54D1940F193204C199C9F49666CC11B38C23B9D130CA49818913D3A2C1FBF71C5B0C774336F903C677D976189D98CA127AAAD6B6AF36195DA637C6EFA3E36E8FE97FA02EC26EB46198AD8DAD8C11260AF499D7BD86619EE5574CD27C80D39F71E653FDCF1B366737233CBB98D1E7B330F7DCCFC5939C4EC79CF0E1CD43BA7AFC716900A21BDB9DD0FCC7ECE1063238407C7E1B221EA10E38F64EF31CEBF3368E1C712BB1B33781134CFE54C2123349A6E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6; +// synopsys translate_on + +// Location: M9K_X33_Y19_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h3C766E63DB6481CB39BC8C68831C724633186CC1BAE9D608A5DEF0FF219C28C1EFF4FDE394D0E19B6FD89186C23CF071E6F1CC8F7FC4F1E48756B0DCD8ED6D0C3DA139003D7A86B2F878DD99DAFB70DE1A19F3FB7DB3B8EF2633007664CB19992E43664448EFF06072648DBA32EDB76E26439BCCEF2DFBF664594B04FBAE72A84A3E508B49DC6BEAAB4F3F0CCCF6D8F568F2DA00EB384A7F53249323198000100408002024010408824080002008011482ED5615E40012EE630C3B2CDB2C13A736DB5B7BD2850018CF936621C6863095A73F7BE7442CB13110B9C0BBB96EEF16CE618EEDCFB393738178C476C367909F71307F6803F677575763DB2D8C3118E4; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h881331ED7AC4EFD38DFACDBB236790005719AEA2FAECCF0D126A30A27222D61BBA428334561F4EDB60C6BF8DB6E267BC56CB69BBCE636CCCB3B2B4B103CC46D5CEEC06DAECB0001569589D5F267AFE086C8FED5DE41DFEFF027DFDFF7FFBFBFDFFDFFF6FFFBDFFDFFF57FF7F7FB7FBBDFBDFFDBFF78FFDBFFEDDFFFDFFFEFF6FF7F7FDDFFEDFF6FF7FFEEFFEFEFC4E51EC0888848E1F2044B47B66608D8A3B3919B9466E6D60D27565964244B218B48AD83430D996068EC908D9E112096996041D77401A0C0CCF5DEEE561F7F7E68CBE72E48E570B047C772CBACC33753080E32EB0B348C0B62337739B1BC73192392592C84E37B7AC141CFE65EE76D83C9083; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h1C5CF062CA6F13854A59BDEEEA07E3C6559EBB3618111895CBBACCBCD512B5F07D361CCE72B925658DBE1F7C4707E195C5C665B8118C3C31B196C261DA85A5E11889D25CB816ACC6627802052C61A4099B7B0EC923971DB3B9F9204BDBCCFA457EE296E8986E64C6DC99E59436641567648CB84DEB7D7937F974F038D838274F3D3CF1BE8C84DDB000565880A776E5C0E13166E49F47119A4CA1311CF97B965E7CBBCB2CB384BD0D92ED105D0617856E80441124B31DE58B8C001607FEE668899693E3EFF8FBF1FCEEFBCF7CF9BA6C37640DDF7FFE6187B19ACF089D4C038F6607B78D38001FE67E56CCE399DE36D7DDBD699D5CFC5B6D7A1421CE06FE40DB6E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h0776C62C316FF94B0BC3A0288DE6A62B14D6C1A2DADF9BDF85B2CCB02CE1DB2D96632C3232C3974CDC1172E1779D8C6738251819975DB8146067301E0C0277B6B657485DCD62AC0662C8C005DDE7494C9CA13AAE3234BB0EE1B708A23A2F48AC4C3838641E940620F9CDDCCA14BCC07104C112BCC9032C48E925594CB886A604C9F7627EB100872A52FB5141D65111E6C8DA0ADB6CEC6004461D0E366B20DCCDB607E624499300E4DF6D95CB62F62FB75403E400EFBC3BD34080FC9CDCFCFCFFFFFFFFFFFFFFFFFFFFF7BFFFFFFFFFFFFFFFFFFFFFFFFFFFCF9FFFFFEFFFF81FFDDFFFFFFFFFFFFFF7FFBFFFBFDC0A6DBE6F8BE5BB7FE7A39B3DA3F3BE13B679; +// synopsys translate_on + +// Location: LCCOMB_X32_Y19_N0 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout )) # +// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ))) + + .dataa(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ), + .datab(gnd), + .datac(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .datad(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[6]~6_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6 .lut_mask = 16'hAFA0; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X22_Y14_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(!address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966; +defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B; +// synopsys translate_on + +// Location: M9K_X22_Y12_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(address[13]), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(1'b0), + .portaaddr({address[12],address[11],address[10],address[9],address[8],address[7],address[6],address[5],address[4],address[3],address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(1'b0), + .portbaddr(13'b0000000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E; +defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2; +// synopsys translate_on + +// Location: LCCOMB_X23_Y14_N12 +cycloneive_lcell_comb \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7 ( +// Equation(s): +// \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout = (\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ))) # +// (!\rom|altsyncram_component|auto_generated|out_address_reg_a [0] & (\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout )) + + .dataa(gnd), + .datab(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ), + .datac(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ), + .datad(\rom|altsyncram_component|auto_generated|out_address_reg_a [0]), + .cin(gnd), + .combout(\rom|altsyncram_component|auto_generated|mux2|result_node[7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7 .lut_mask = 16'hF0CC; +defparam \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7 .sum_lutc_input = "datac"; // synopsys translate_on assign LED[0] = \LED[0]~output_o ; diff --git a/simulation/modelsim/spectrum_min_1200mv_0c_v_fast.sdo b/simulation/modelsim/spectrum_min_1200mv_0c_v_fast.sdo index 5ca5f65..e0f98d2 100644 --- a/simulation/modelsim/spectrum_min_1200mv_0c_v_fast.sdo +++ b/simulation/modelsim/spectrum_min_1200mv_0c_v_fast.sdo @@ -29,7 +29,7 @@ (DELAYFILE (SDFVERSION "2.1") (DESIGN "spectrum") - (DATE "03/30/2022 12:38:42") + (DATE "03/30/2022 13:12:28") (VENDOR "Altera") (PROGRAM "Quartus II 32-bit") (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") @@ -41,7 +41,7 @@ (INSTANCE LED\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (761:761:761) (843:843:843)) + (PORT i (941:941:941) (1090:1090:1090)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -51,7 +51,7 @@ (INSTANCE LED\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (788:788:788) (884:884:884)) + (PORT i (858:858:858) (973:973:973)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -61,7 +61,7 @@ (INSTANCE LED\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (1023:1023:1023) (1135:1135:1135)) + (PORT i (957:957:957) (1082:1082:1082)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -71,7 +71,7 @@ (INSTANCE LED\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (793:793:793) (868:868:868)) + (PORT i (611:611:611) (701:701:701)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -81,7 +81,7 @@ (INSTANCE LED\[4\]\~output) (DELAY (ABSOLUTE - (PORT i (980:980:980) (1098:1098:1098)) + (PORT i (821:821:821) (940:940:940)) (IOPATH i o (1666:1666:1666) (1600:1600:1600)) ) ) @@ -91,7 +91,7 @@ (INSTANCE LED\[5\]\~output) (DELAY (ABSOLUTE - (PORT i (739:739:739) (841:841:841)) + (PORT i (1195:1195:1195) (1350:1350:1350)) (IOPATH i o (3106:3106:3106) (2841:2841:2841)) ) ) @@ -101,7 +101,7 @@ (INSTANCE LED\[6\]\~output) (DELAY (ABSOLUTE - (PORT i (1028:1028:1028) (1155:1155:1155)) + (PORT i (1351:1351:1351) (1507:1507:1507)) (IOPATH i o (1586:1586:1586) (1541:1541:1541)) ) ) @@ -111,7 +111,7 @@ (INSTANCE LED\[7\]\~output) (DELAY (ABSOLUTE - (PORT i (837:837:837) (953:953:953)) + (PORT i (550:550:550) (639:639:639)) (IOPATH i o (3106:3106:3106) (2841:2841:2841)) ) ) @@ -134,29 +134,12 @@ ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[20\]) - (DELAY - (ABSOLUTE - (PORT clk (912:912:912) (916:916:916)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~0) + (INSTANCE counter\[0\]\~63) (DELAY (ABSOLUTE - (PORT dataa (130:130:130) (179:179:179)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH dataa cout (226:226:226) (171:171:171)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH datac combout (190:190:190) (195:195:195)) ) ) ) @@ -165,7 +148,7 @@ (INSTANCE counter\[0\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (916:916:916)) + (PORT clk (913:913:913) (917:917:917)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -176,15 +159,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~2) + (INSTANCE counter\[1\]\~21) (DELAY (ABSOLUTE - (PORT datab (129:129:129) (177:177:177)) - (IOPATH datab combout (166:166:166) (176:176:176)) + (PORT dataa (136:136:136) (187:187:187)) + (PORT datab (135:135:135) (186:186:186)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) ) ) ) @@ -193,7 +177,7 @@ (INSTANCE counter\[1\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (916:916:916)) + (PORT clk (913:913:913) (917:917:917)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -204,11 +188,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~4) + (INSTANCE counter\[2\]\~23) (DELAY (ABSOLUTE - (PORT datab (129:129:129) (177:177:177)) - (IOPATH datab combout (192:192:192) (177:177:177)) + (PORT datab (134:134:134) (184:184:184)) + (IOPATH datab combout (166:166:166) (176:176:176)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) @@ -221,7 +205,7 @@ (INSTANCE counter\[2\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (916:916:916)) + (PORT clk (913:913:913) (917:917:917)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -232,11 +216,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~6) + (INSTANCE counter\[3\]\~25) (DELAY (ABSOLUTE - (PORT datab (129:129:129) (177:177:177)) - (IOPATH datab combout (166:166:166) (176:176:176)) + (PORT datab (133:133:133) (183:183:183)) + (IOPATH datab combout (192:192:192) (177:177:177)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) @@ -249,7 +233,7 @@ (INSTANCE counter\[3\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (916:916:916)) + (PORT clk (913:913:913) (917:917:917)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -260,12 +244,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~8) + (INSTANCE counter\[4\]\~27) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (257:257:257)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH dataa cout (226:226:226) (171:171:171)) + (PORT datab (134:134:134) (183:183:183)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -277,7 +261,7 @@ (INSTANCE counter\[4\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (916:916:916)) + (PORT clk (913:913:913) (917:917:917)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -288,11 +272,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~10) + (INSTANCE counter\[5\]\~29) (DELAY (ABSOLUTE - (PORT datab (199:199:199) (255:255:255)) - (IOPATH datab combout (166:166:166) (176:176:176)) + (PORT datab (142:142:142) (189:189:189)) + (IOPATH datab combout (192:192:192) (177:177:177)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) @@ -305,7 +289,7 @@ (INSTANCE counter\[5\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (916:916:916)) + (PORT clk (913:913:913) (917:917:917)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -316,11 +300,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~12) + (INSTANCE counter\[6\]\~31) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (257:257:257)) - (IOPATH dataa combout (186:186:186) (175:175:175)) + (PORT dataa (136:136:136) (187:187:187)) + (IOPATH dataa combout (165:165:165) (173:173:173)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) @@ -333,7 +317,7 @@ (INSTANCE counter\[6\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (916:916:916)) + (PORT clk (913:913:913) (917:917:917)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -344,11 +328,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~14) + (INSTANCE counter\[7\]\~33) (DELAY (ABSOLUTE - (PORT datab (198:198:198) (255:255:255)) - (IOPATH datab combout (166:166:166) (176:176:176)) + (PORT datab (134:134:134) (183:183:183)) + (IOPATH datab combout (192:192:192) (177:177:177)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) @@ -361,7 +345,7 @@ (INSTANCE counter\[7\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (916:916:916)) + (PORT clk (913:913:913) (917:917:917)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -372,12 +356,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~16) + (INSTANCE counter\[8\]\~35) (DELAY (ABSOLUTE - (PORT datab (128:128:128) (176:176:176)) - (IOPATH datab combout (192:192:192) (177:177:177)) - (IOPATH datab cout (227:227:227) (175:175:175)) + (PORT dataa (135:135:135) (188:188:188)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -389,7 +373,7 @@ (INSTANCE counter\[8\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (916:916:916)) + (PORT clk (913:913:913) (917:917:917)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -400,12 +384,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~18) + (INSTANCE counter\[9\]\~37) (DELAY (ABSOLUTE - (PORT dataa (129:129:129) (179:179:179)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH dataa cout (226:226:226) (171:171:171)) + (PORT datab (133:133:133) (182:182:182)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -417,7 +401,7 @@ (INSTANCE counter\[9\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (916:916:916)) + (PORT clk (913:913:913) (917:917:917)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -428,12 +412,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~20) + (INSTANCE counter\[10\]\~39) (DELAY (ABSOLUTE - (PORT datab (128:128:128) (176:176:176)) - (IOPATH datab combout (192:192:192) (177:177:177)) - (IOPATH datab cout (227:227:227) (175:175:175)) + (PORT dataa (133:133:133) (187:187:187)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -445,7 +429,7 @@ (INSTANCE counter\[10\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (916:916:916)) + (PORT clk (913:913:913) (917:917:917)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -456,24 +440,34 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~22) + (INSTANCE counter\[11\]\~41) (DELAY (ABSOLUTE - (PORT datab (200:200:200) (254:254:254)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datab cout (227:227:227) (175:175:175)) + (PORT dataa (376:376:376) (454:454:454)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE counter\[11\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (164:164:164) (192:192:192)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE counter\[11\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (916:916:916)) + (PORT clk (913:913:913) (917:917:917)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -484,11 +478,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~24) + (INSTANCE counter\[12\]\~43) (DELAY (ABSOLUTE - (PORT datab (199:199:199) (254:254:254)) - (IOPATH datab combout (192:192:192) (177:177:177)) + (PORT datab (133:133:133) (182:182:182)) + (IOPATH datab combout (166:166:166) (176:176:176)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) @@ -501,7 +495,7 @@ (INSTANCE counter\[12\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (916:916:916)) + (PORT clk (913:913:913) (917:917:917)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -512,11 +506,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~26) + (INSTANCE counter\[13\]\~45) (DELAY (ABSOLUTE - (PORT datab (200:200:200) (254:254:254)) - (IOPATH datab combout (166:166:166) (176:176:176)) + (PORT datab (134:134:134) (184:184:184)) + (IOPATH datab combout (192:192:192) (177:177:177)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) @@ -529,7 +523,7 @@ (INSTANCE counter\[13\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (916:916:916)) + (PORT clk (913:913:913) (917:917:917)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -540,11 +534,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~28) + (INSTANCE counter\[14\]\~47) (DELAY (ABSOLUTE - (PORT dataa (199:199:199) (259:259:259)) - (IOPATH dataa combout (186:186:186) (175:175:175)) + (PORT dataa (136:136:136) (189:189:189)) + (IOPATH dataa combout (165:165:165) (173:173:173)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) @@ -557,7 +551,7 @@ (INSTANCE counter\[14\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (916:916:916)) + (PORT clk (913:913:913) (917:917:917)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -568,11 +562,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~30) + (INSTANCE counter\[15\]\~49) (DELAY (ABSOLUTE - (PORT datab (200:200:200) (254:254:254)) - (IOPATH datab combout (166:166:166) (176:176:176)) + (PORT datab (135:135:135) (185:185:185)) + (IOPATH datab combout (192:192:192) (177:177:177)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) @@ -585,7 +579,7 @@ (INSTANCE counter\[15\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (916:916:916)) + (PORT clk (913:913:913) (917:917:917)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -596,12 +590,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~32) + (INSTANCE counter\[16\]\~51) (DELAY (ABSOLUTE - (PORT datab (199:199:199) (257:257:257)) - (IOPATH datab combout (192:192:192) (177:177:177)) - (IOPATH datab cout (227:227:227) (175:175:175)) + (PORT dataa (135:135:135) (187:187:187)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -613,7 +607,7 @@ (INSTANCE counter\[16\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (916:916:916)) + (PORT clk (913:913:913) (917:917:917)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -624,11 +618,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~34) + (INSTANCE counter\[17\]\~53) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (257:257:257)) - (IOPATH dataa combout (165:165:165) (173:173:173)) + (PORT dataa (136:136:136) (188:188:188)) + (IOPATH dataa combout (186:186:186) (175:175:175)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) @@ -641,7 +635,7 @@ (INSTANCE counter\[17\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (916:916:916)) + (PORT clk (913:913:913) (917:917:917)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -652,12 +646,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~36) + (INSTANCE counter\[18\]\~55) (DELAY (ABSOLUTE - (PORT dataa (201:201:201) (257:257:257)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH dataa cout (226:226:226) (171:171:171)) + (PORT datab (135:135:135) (186:186:186)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -669,7 +663,7 @@ (INSTANCE counter\[18\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (916:916:916)) + (PORT clk (913:913:913) (917:917:917)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -680,12 +674,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~38) + (INSTANCE counter\[19\]\~57) (DELAY (ABSOLUTE - (PORT dataa (200:200:200) (261:261:261)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH dataa cout (226:226:226) (171:171:171)) + (PORT datab (135:135:135) (185:185:185)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -697,7 +691,7 @@ (INSTANCE counter\[19\]) (DELAY (ABSOLUTE - (PORT clk (912:912:912) (916:916:916)) + (PORT clk (913:913:913) (917:917:917)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -706,42 +700,15 @@ (HOLD d (posedge clk) (84:84:84)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~40) - (DELAY - (ABSOLUTE - (PORT datad (118:118:118) (154:154:154)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE Equal0\~5) (DELAY (ABSOLUTE - (PORT dataa (110:110:110) (143:143:143)) - (PORT datab (109:109:109) (139:139:139)) - (PORT datac (96:96:96) (120:120:120)) - (PORT datad (95:95:95) (114:114:114)) - (IOPATH dataa combout (158:158:158) (157:157:157)) - (IOPATH datab combout (160:160:160) (156:156:156)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (105:105:105) (137:137:137)) - (PORT datab (104:104:104) (133:133:133)) - (PORT datac (91:91:91) (114:114:114)) - (PORT datad (92:92:92) (110:110:110)) + (PORT dataa (138:138:138) (191:191:191)) + (PORT datab (136:136:136) (186:186:186)) + (PORT datac (122:122:122) (165:165:165)) + (PORT datad (124:124:124) (164:164:164)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -754,10 +721,26 @@ (INSTANCE Equal0\~0) (DELAY (ABSOLUTE - (PORT dataa (175:175:175) (212:212:212)) - (PORT datab (173:173:173) (211:211:211)) - (PORT datac (160:160:160) (194:194:194)) - (PORT datad (162:162:162) (186:186:186)) + (PORT dataa (136:136:136) (188:188:188)) + (PORT datab (135:135:135) (185:185:185)) + (PORT datac (121:121:121) (164:164:164)) + (PORT datad (122:122:122) (162:162:162)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (138:138:138) (191:191:191)) + (PORT datab (137:137:137) (188:188:188)) + (PORT datac (200:200:200) (245:245:245)) + (PORT datad (123:123:123) (162:162:162)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -770,10 +753,10 @@ (INSTANCE Equal0\~2) (DELAY (ABSOLUTE - (PORT dataa (191:191:191) (228:228:228)) - (PORT datab (336:336:336) (394:394:394)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (293:293:293) (332:332:332)) + (PORT dataa (140:140:140) (194:194:194)) + (PORT datab (141:141:141) (190:190:190)) + (PORT datac (125:125:125) (170:170:170)) + (PORT datad (125:125:125) (165:165:165)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -786,10 +769,10 @@ (INSTANCE Equal0\~3) (DELAY (ABSOLUTE - (PORT dataa (107:107:107) (139:139:139)) - (PORT datab (106:106:106) (135:135:135)) - (PORT datac (92:92:92) (114:114:114)) - (PORT datad (92:92:92) (110:110:110)) + (PORT dataa (138:138:138) (192:192:192)) + (PORT datab (137:137:137) (188:188:188)) + (PORT datac (123:123:123) (166:166:166)) + (PORT datad (124:124:124) (164:164:164)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (120:120:120) (124:124:124)) @@ -802,10 +785,10 @@ (INSTANCE Equal0\~4) (DELAY (ABSOLUTE - (PORT dataa (329:329:329) (387:387:387)) - (PORT datab (430:430:430) (498:498:498)) - (PORT datac (88:88:88) (110:110:110)) - (PORT datad (156:156:156) (182:182:182)) + (PORT dataa (174:174:174) (213:213:213)) + (PORT datab (177:177:177) (213:213:213)) + (PORT datac (172:172:172) (204:204:204)) + (PORT datad (314:314:314) (364:364:364)) (IOPATH dataa combout (159:159:159) (163:163:163)) (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -815,14 +798,79 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[0\]\~0) + (INSTANCE counter\[20\]\~59) (DELAY (ABSOLUTE - (PORT dataa (306:306:306) (353:353:353)) - (PORT datab (190:190:190) (228:228:228)) - (PORT datad (98:98:98) (120:120:120)) - (IOPATH dataa combout (159:159:159) (173:173:173)) - (IOPATH datab combout (166:166:166) (158:158:158)) + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE counter\[20\]) + (DELAY + (ABSOLUTE + (PORT clk (1110:1110:1110) (1139:1139:1139)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE counter\[21\]\~61) + (DELAY + (ABSOLUTE + (PORT datad (129:129:129) (166:166:166)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE counter\[21\]) + (DELAY + (ABSOLUTE + (PORT clk (1110:1110:1110) (1139:1139:1139)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~7) + (DELAY + (ABSOLUTE + (PORT datac (359:359:359) (433:433:433)) + (PORT datad (350:350:350) (417:417:417)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[0\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (401:401:401)) + (PORT datab (107:107:107) (137:137:137)) + (PORT datad (170:170:170) (199:199:199)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (160:160:160) (176:176:176)) (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) @@ -833,7 +881,7 @@ (INSTANCE address\[0\]) (DELAY (ABSOLUTE - (PORT clk (1110:1110:1110) (1138:1138:1138)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -842,27 +890,30 @@ (HOLD d (posedge clk) (84:84:84)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (146:146:146) (199:199:199)) + (PORT datab (140:140:140) (189:189:189)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE Equal0\~6) (DELAY (ABSOLUTE - (PORT datac (95:95:95) (120:120:120)) - (PORT datad (97:97:97) (118:118:118)) - (IOPATH datac combout (120:120:120) (124:124:124)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal0\~7) - (DELAY - (ABSOLUTE - (PORT dataa (187:187:187) (223:223:223)) - (PORT datab (109:109:109) (139:139:139)) - (PORT datac (89:89:89) (110:110:110)) - (PORT datad (95:95:95) (113:113:113)) + (PORT dataa (378:378:378) (454:454:454)) + (PORT datab (364:364:364) (436:436:436)) + (PORT datac (325:325:325) (377:377:377)) + (PORT datad (95:95:95) (115:115:115)) (IOPATH dataa combout (158:158:158) (157:157:157)) (IOPATH datab combout (160:160:160) (156:156:156)) (IOPATH datac combout (119:119:119) (124:124:124)) @@ -870,27 +921,395 @@ ) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (314:314:314) (385:385:385)) - (PORT datab (114:114:114) (147:147:147)) - (PORT datad (169:169:169) (198:198:198)) - (IOPATH dataa combout (158:158:158) (173:173:173)) - (IOPATH datab combout (160:160:160) (176:176:176)) - (IOPATH datac combout (190:190:190) (195:195:195)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) (CELL (CELLTYPE "dffeas") (INSTANCE address\[1\]) (DELAY (ABSOLUTE - (PORT clk (1110:1110:1110) (1138:1138:1138)) + (PORT clk (912:912:912) (917:917:917)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (409:409:409) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[2\]\~15) + (DELAY + (ABSOLUTE + (PORT datab (141:141:141) (189:189:189)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (917:917:917)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (409:409:409) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[3\]\~17) + (DELAY + (ABSOLUTE + (PORT datab (154:154:154) (201:201:201)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (917:917:917)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (409:409:409) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[4\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (917:917:917)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (409:409:409) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[5\]\~21) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (917:917:917)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (409:409:409) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[6\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (917:917:917)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (409:409:409) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[7\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (917:917:917)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (409:409:409) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[8\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (917:917:917)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (409:409:409) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[9\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (917:917:917)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (409:409:409) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[10\]\~31) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (917:917:917)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (409:409:409) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[11\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (917:917:917)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (409:409:409) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[12\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (917:917:917)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (409:409:409) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[13\]\~37) + (DELAY + (ABSOLUTE + (PORT datad (141:141:141) (177:177:177)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (917:917:917)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (409:409:409) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (225:225:225) (275:275:275)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE rom\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (912:912:912) (917:917:917)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -901,39 +1320,20 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[1\]\~2) + (INSTANCE rom\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (315:315:315) (387:387:387)) - (PORT datab (194:194:194) (233:233:233)) - (PORT datac (295:295:295) (332:332:332)) - (PORT datad (102:102:102) (125:125:125)) - (IOPATH dataa combout (158:158:158) (163:163:163)) - (IOPATH datab combout (160:160:160) (167:167:167)) - (IOPATH datac combout (119:119:119) (125:125:125)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[2\]\~3) - (DELAY - (ABSOLUTE - (PORT datab (207:207:207) (264:264:264)) - (PORT datad (92:92:92) (109:109:109)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datac combout (190:190:190) (195:195:195)) + (PORT datad (120:120:120) (157:157:157)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[2\]) + (INSTANCE rom\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) (DELAY (ABSOLUTE - (PORT clk (1110:1110:1110) (1138:1138:1138)) + (PORT clk (912:912:912) (917:917:917)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -942,14 +1342,121 @@ (HOLD d (posedge clk) (84:84:84)) ) ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (696:696:696) (809:809:809)) + (PORT d[1] (727:727:727) (854:854:854)) + (PORT d[2] (770:770:770) (905:905:905)) + (PORT d[3] (752:752:752) (874:874:874)) + (PORT d[4] (709:709:709) (827:827:827)) + (PORT d[5] (774:774:774) (910:910:910)) + (PORT d[6] (1002:1002:1002) (1193:1193:1193)) + (PORT d[7] (749:749:749) (870:870:870)) + (PORT d[8] (756:756:756) (884:884:884)) + (PORT d[9] (769:769:769) (904:904:904)) + (PORT d[10] (751:751:751) (876:876:876)) + (PORT d[11] (880:880:880) (1014:1014:1014)) + (PORT d[12] (737:737:737) (853:853:853)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (PORT d[0] (659:659:659) (736:736:736)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1077:1077:1077) (1093:1093:1093)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (720:720:720) (839:839:839)) - (PORT d[1] (870:870:870) (1010:1010:1010)) - (PORT d[2] (873:873:873) (1012:1012:1012)) + (PORT d[0] (643:643:643) (747:747:747)) + (PORT d[1] (556:556:556) (658:658:658)) + (PORT d[2] (593:593:593) (701:701:701)) + (PORT d[3] (758:758:758) (882:882:882)) + (PORT d[4] (705:705:705) (826:826:826)) + (PORT d[5] (749:749:749) (874:874:874)) + (PORT d[6] (874:874:874) (1055:1055:1055)) + (PORT d[7] (708:708:708) (817:817:817)) + (PORT d[8] (753:753:753) (886:886:886)) + (PORT d[9] (784:784:784) (927:927:927)) + (PORT d[10] (741:741:741) (864:864:864)) + (PORT d[11] (709:709:709) (823:823:823)) + (PORT d[12] (755:755:755) (877:877:877)) (PORT clk (1095:1095:1095) (1112:1112:1112)) ) ) @@ -963,6 +1470,7 @@ (DELAY (ABSOLUTE (PORT clk (1095:1095:1095) (1112:1112:1112)) + (PORT d[0] (582:582:582) (526:526:526)) ) ) ) @@ -1028,4 +1536,1474 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (545:545:545) (645:645:645)) + (PORT datac (484:484:484) (546:546:546)) + (PORT datad (333:333:333) (377:377:377)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (813:813:813) (941:941:941)) + (PORT d[1] (863:863:863) (1008:1008:1008)) + (PORT d[2] (881:881:881) (1027:1027:1027)) + (PORT d[3] (699:699:699) (808:808:808)) + (PORT d[4] (926:926:926) (1077:1077:1077)) + (PORT d[5] (1093:1093:1093) (1290:1290:1290)) + (PORT d[6] (695:695:695) (813:813:813)) + (PORT d[7] (761:761:761) (903:903:903)) + (PORT d[8] (1083:1083:1083) (1274:1274:1274)) + (PORT d[9] (677:677:677) (796:796:796)) + (PORT d[10] (799:799:799) (948:948:948)) + (PORT d[11] (665:665:665) (771:771:771)) + (PORT d[12] (687:687:687) (813:813:813)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1089:1089:1089) (1106:1106:1106)) + (PORT d[0] (695:695:695) (626:626:626)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1071:1071:1071) (1087:1087:1087)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (826:826:826) (972:972:972)) + (PORT d[1] (756:756:756) (903:903:903)) + (PORT d[2] (889:889:889) (1041:1041:1041)) + (PORT d[3] (752:752:752) (884:884:884)) + (PORT d[4] (736:736:736) (866:866:866)) + (PORT d[5] (908:908:908) (1078:1078:1078)) + (PORT d[6] (715:715:715) (845:845:845)) + (PORT d[7] (708:708:708) (834:834:834)) + (PORT d[8] (917:917:917) (1088:1088:1088)) + (PORT d[9] (746:746:746) (884:884:884)) + (PORT d[10] (1042:1042:1042) (1212:1212:1212)) + (PORT d[11] (728:728:728) (859:859:859)) + (PORT d[12] (886:886:886) (1034:1034:1034)) + (PORT clk (1090:1090:1090) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1108:1108:1108)) + (PORT d[0] (672:672:672) (765:765:765)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1072:1072:1072) (1089:1089:1089)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (621:621:621)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (399:399:399)) + (PORT datac (502:502:502) (567:567:567)) + (PORT datad (721:721:721) (843:843:843)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (705:705:705) (819:819:819)) + (PORT d[1] (732:732:732) (860:860:860)) + (PORT d[2] (910:910:910) (1062:1062:1062)) + (PORT d[3] (784:784:784) (916:916:916)) + (PORT d[4] (732:732:732) (858:858:858)) + (PORT d[5] (737:737:737) (856:856:856)) + (PORT d[6] (1011:1011:1011) (1205:1205:1205)) + (PORT d[7] (765:765:765) (893:893:893)) + (PORT d[8] (760:760:760) (891:891:891)) + (PORT d[9] (803:803:803) (947:947:947)) + (PORT d[10] (982:982:982) (1126:1126:1126)) + (PORT d[11] (885:885:885) (1020:1020:1020)) + (PORT d[12] (758:758:758) (879:879:879)) + (PORT clk (1094:1094:1094) (1111:1111:1111)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1094:1094:1094) (1111:1111:1111)) + (PORT d[0] (765:765:765) (689:689:689)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1076:1076:1076) (1092:1092:1092)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (616:616:616) (624:624:624)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (541:541:541) (637:637:637)) + (PORT d[1] (708:708:708) (828:828:828)) + (PORT d[2] (601:601:601) (702:702:702)) + (PORT d[3] (607:607:607) (715:715:715)) + (PORT d[4] (549:549:549) (647:647:647)) + (PORT d[5] (691:691:691) (797:797:797)) + (PORT d[6] (860:860:860) (1033:1033:1033)) + (PORT d[7] (707:707:707) (817:817:817)) + (PORT d[8] (599:599:599) (713:713:713)) + (PORT d[9] (625:625:625) (746:746:746)) + (PORT d[10] (828:828:828) (957:957:957)) + (PORT d[11] (709:709:709) (822:822:822)) + (PORT d[12] (742:742:742) (856:856:856)) + (PORT clk (1096:1096:1096) (1113:1113:1113)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1113:1113:1113)) + (PORT d[0] (525:525:525) (581:581:581)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1078:1078:1078) (1094:1094:1094)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (627:627:627)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (627:627:627)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (627:627:627)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT datab (551:551:551) (659:659:659)) + (PORT datac (509:509:509) (578:578:578)) + (PORT datad (328:328:328) (369:369:369)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (513:513:513) (599:599:599)) + (PORT d[1] (535:535:535) (638:638:638)) + (PORT d[2] (594:594:594) (707:707:707)) + (PORT d[3] (582:582:582) (682:682:682)) + (PORT d[4] (527:527:527) (618:618:618)) + (PORT d[5] (558:558:558) (656:656:656)) + (PORT d[6] (819:819:819) (985:985:985)) + (PORT d[7] (682:682:682) (790:790:790)) + (PORT d[8] (911:911:911) (1067:1067:1067)) + (PORT d[9] (597:597:597) (712:712:712)) + (PORT d[10] (575:575:575) (678:678:678)) + (PORT d[11] (710:710:710) (823:823:823)) + (PORT d[12] (716:716:716) (828:828:828)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (PORT d[0] (497:497:497) (548:548:548)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1077:1077:1077) (1093:1093:1093)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (648:648:648) (753:753:753)) + (PORT d[1] (354:354:354) (417:417:417)) + (PORT d[2] (392:392:392) (461:461:461)) + (PORT d[3] (418:418:418) (491:491:491)) + (PORT d[4] (359:359:359) (424:424:424)) + (PORT d[5] (407:407:407) (482:482:482)) + (PORT d[6] (419:419:419) (492:492:492)) + (PORT d[7] (411:411:411) (485:485:485)) + (PORT d[8] (414:414:414) (490:490:490)) + (PORT d[9] (422:422:422) (503:503:503)) + (PORT d[10] (658:658:658) (769:769:769)) + (PORT d[11] (411:411:411) (482:482:482)) + (PORT d[12] (416:416:416) (490:490:490)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1112:1112:1112)) + (PORT d[0] (376:376:376) (347:347:347)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1077:1077:1077) (1093:1093:1093)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (625:625:625)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (504:504:504) (583:583:583)) + (PORT datac (358:358:358) (424:424:424)) + (PORT datad (331:331:331) (374:374:374)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (813:813:813) (944:944:944)) + (PORT d[1] (852:852:852) (996:996:996)) + (PORT d[2] (870:870:870) (1016:1016:1016)) + (PORT d[3] (550:550:550) (646:646:646)) + (PORT d[4] (543:543:543) (639:639:639)) + (PORT d[5] (921:921:921) (1093:1093:1093)) + (PORT d[6] (544:544:544) (650:650:650)) + (PORT d[7] (519:519:519) (618:618:618)) + (PORT d[8] (920:920:920) (1089:1089:1089)) + (PORT d[9] (546:546:546) (652:652:652)) + (PORT d[10] (536:536:536) (637:637:637)) + (PORT d[11] (524:524:524) (622:622:622)) + (PORT d[12] (537:537:537) (631:631:631)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1089:1089:1089) (1106:1106:1106)) + (PORT d[0] (540:540:540) (486:486:486)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1071:1071:1071) (1087:1087:1087)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (667:667:667) (784:784:784)) + (PORT d[1] (696:696:696) (823:823:823)) + (PORT d[2] (712:712:712) (840:840:840)) + (PORT d[3] (708:708:708) (823:823:823)) + (PORT d[4] (919:919:919) (1070:1070:1070)) + (PORT d[5] (920:920:920) (1092:1092:1092)) + (PORT d[6] (704:704:704) (834:834:834)) + (PORT d[7] (688:688:688) (810:810:810)) + (PORT d[8] (919:919:919) (1088:1088:1088)) + (PORT d[9] (701:701:701) (826:826:826)) + (PORT d[10] (1057:1057:1057) (1230:1230:1230)) + (PORT d[11] (708:708:708) (835:835:835)) + (PORT d[12] (683:683:683) (805:805:805)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1089:1089:1089) (1106:1106:1106)) + (PORT d[0] (637:637:637) (713:713:713)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1071:1071:1071) (1087:1087:1087)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~4) + (DELAY + (ABSOLUTE + (PORT datab (349:349:349) (398:398:398)) + (PORT datac (475:475:475) (533:533:533)) + (PORT datad (428:428:428) (504:504:504)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (840:840:840) (987:987:987)) + (PORT d[1] (1090:1090:1090) (1276:1276:1276)) + (PORT d[2] (713:713:713) (840:840:840)) + (PORT d[3] (739:739:739) (859:859:859)) + (PORT d[4] (736:736:736) (862:862:862)) + (PORT d[5] (706:706:706) (838:838:838)) + (PORT d[6] (733:733:733) (868:868:868)) + (PORT d[7] (716:716:716) (843:843:843)) + (PORT d[8] (901:901:901) (1069:1069:1069)) + (PORT d[9] (744:744:744) (880:880:880)) + (PORT d[10] (1059:1059:1059) (1238:1238:1238)) + (PORT d[11] (722:722:722) (847:847:847)) + (PORT d[12] (859:859:859) (1000:1000:1000)) + (PORT clk (1090:1090:1090) (1108:1108:1108)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1108:1108:1108)) + (PORT d[0] (672:672:672) (759:759:759)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1109:1109:1109)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1072:1072:1072) (1089:1089:1089)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (621:621:621)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (622:622:622)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (867:867:867) (1022:1022:1022)) + (PORT d[1] (928:928:928) (1097:1097:1097)) + (PORT d[2] (889:889:889) (1039:1039:1039)) + (PORT d[3] (932:932:932) (1088:1088:1088)) + (PORT d[4] (904:904:904) (1065:1065:1065)) + (PORT d[5] (892:892:892) (1048:1048:1048)) + (PORT d[6] (883:883:883) (1038:1038:1038)) + (PORT d[7] (871:871:871) (1018:1018:1018)) + (PORT d[8] (871:871:871) (1029:1029:1029)) + (PORT d[9] (908:908:908) (1064:1064:1064)) + (PORT d[10] (863:863:863) (1012:1012:1012)) + (PORT d[11] (892:892:892) (1039:1039:1039)) + (PORT d[12] (860:860:860) (1009:1009:1009)) + (PORT clk (1089:1089:1089) (1106:1106:1106)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1089:1089:1089) (1106:1106:1106)) + (PORT d[0] (920:920:920) (819:819:819)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1071:1071:1071) (1087:1087:1087)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (389:389:389)) + (PORT datac (510:510:510) (575:575:575)) + (PORT datad (626:626:626) (741:741:741)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (539:539:539) (637:637:637)) + (PORT d[1] (697:697:697) (818:818:818)) + (PORT d[2] (599:599:599) (708:708:708)) + (PORT d[3] (608:608:608) (718:718:718)) + (PORT d[4] (555:555:555) (660:660:660)) + (PORT d[5] (599:599:599) (709:709:709)) + (PORT d[6] (841:841:841) (1010:1010:1010)) + (PORT d[7] (714:714:714) (829:829:829)) + (PORT d[8] (596:596:596) (706:706:706)) + (PORT d[9] (600:600:600) (716:716:716)) + (PORT d[10] (579:579:579) (682:682:682)) + (PORT d[11] (699:699:699) (809:809:809)) + (PORT d[12] (735:735:735) (849:849:849)) + (PORT clk (1096:1096:1096) (1113:1113:1113)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1096:1096:1096) (1113:1113:1113)) + (PORT d[0] (517:517:517) (572:572:572)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1097:1097:1097) (1114:1114:1114)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1078:1078:1078) (1094:1094:1094)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (618:618:618) (626:626:626)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (627:627:627)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (627:627:627)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (619:619:619) (627:627:627)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (509:509:509) (594:594:594)) + (PORT d[1] (355:355:355) (418:418:418)) + (PORT d[2] (733:733:733) (863:863:863)) + (PORT d[3] (766:766:766) (895:895:895)) + (PORT d[4] (514:514:514) (597:597:597)) + (PORT d[5] (582:582:582) (683:683:683)) + (PORT d[6] (805:805:805) (963:963:963)) + (PORT d[7] (681:681:681) (788:788:788)) + (PORT d[8] (925:925:925) (1079:1079:1079)) + (PORT d[9] (580:580:580) (683:683:683)) + (PORT d[10] (577:577:577) (677:677:677)) + (PORT d[11] (660:660:660) (761:761:761)) + (PORT d[12] (686:686:686) (789:789:789)) + (PORT clk (1094:1094:1094) (1112:1112:1112)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1094:1094:1094) (1112:1112:1112)) + (PORT d[0] (534:534:534) (487:487:487)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1095:1095:1095) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1076:1076:1076) (1093:1093:1093)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (616:616:616) (625:625:625)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (626:626:626)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (617:617:617) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (391:391:391) (455:455:455)) + (PORT datac (481:481:481) (561:561:561)) + (PORT datad (186:186:186) (218:218:218)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (830:830:830) (970:970:970)) + (PORT d[1] (1078:1078:1078) (1262:1262:1262)) + (PORT d[2] (1085:1085:1085) (1259:1259:1259)) + (PORT d[3] (772:772:772) (909:909:909)) + (PORT d[4] (1067:1067:1067) (1250:1250:1250)) + (PORT d[5] (739:739:739) (887:887:887)) + (PORT d[6] (747:747:747) (889:889:889)) + (PORT d[7] (717:717:717) (844:844:844)) + (PORT d[8] (733:733:733) (878:878:878)) + (PORT d[9] (731:731:731) (861:861:861)) + (PORT d[10] (1020:1020:1020) (1186:1186:1186)) + (PORT d[11] (723:723:723) (848:848:848)) + (PORT d[12] (713:713:713) (836:836:836)) + (PORT clk (1090:1090:1090) (1107:1107:1107)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1090:1090:1090) (1107:1107:1107)) + (PORT d[0] (776:776:776) (683:683:683)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1091:1091:1091) (1108:1108:1108)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1072:1072:1072) (1088:1088:1088)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (612:612:612) (620:620:620)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (621:621:621)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (621:621:621)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (613:613:613) (621:621:621)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1017:1017:1017) (1190:1190:1190)) + (PORT d[1] (910:910:910) (1072:1072:1072)) + (PORT d[2] (907:907:907) (1065:1065:1065)) + (PORT d[3] (918:918:918) (1070:1070:1070)) + (PORT d[4] (910:910:910) (1068:1068:1068)) + (PORT d[5] (891:891:891) (1047:1047:1047)) + (PORT d[6] (884:884:884) (1036:1036:1036)) + (PORT d[7] (880:880:880) (1029:1029:1029)) + (PORT d[8] (867:867:867) (1020:1020:1020)) + (PORT d[9] (913:913:913) (1070:1070:1070)) + (PORT d[10] (853:853:853) (997:997:997)) + (PORT d[11] (898:898:898) (1045:1045:1045)) + (PORT d[12] (870:870:870) (1019:1019:1019)) + (PORT clk (1088:1088:1088) (1105:1105:1105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1088:1088:1088) (1105:1105:1105)) + (PORT d[0] (846:846:846) (959:959:959)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1089:1089:1089) (1106:1106:1106)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1070:1070:1070) (1086:1086:1086)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (610:610:610) (618:618:618)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (611:611:611) (619:619:619)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT datab (346:346:346) (394:394:394)) + (PORT datac (502:502:502) (567:567:567)) + (PORT datad (628:628:628) (743:743:743)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) ) diff --git a/simulation/modelsim/spectrum_modelsim.xrf b/simulation/modelsim/spectrum_modelsim.xrf index 5aff091..2c6fa75 100644 --- a/simulation/modelsim/spectrum_modelsim.xrf +++ b/simulation/modelsim/spectrum_modelsim.xrf @@ -15,7 +15,10 @@ source_file = 1, /home/benny/altera/13.1/quartus/libraries/megafunctions/altrom. source_file = 1, /home/benny/altera/13.1/quartus/libraries/megafunctions/altram.inc source_file = 1, /home/benny/altera/13.1/quartus/libraries/megafunctions/altdpram.inc source_file = 1, /home/benny/altera/13.1/quartus/libraries/megafunctions/cbx.lst -source_file = 1, /home/benny/work/fpga/projects/db/altsyncram_ro91.tdf +source_file = 1, /home/benny/work/fpga/projects/db/altsyncram_qh91.tdf +source_file = 1, /home/benny/work/fpga/projects/rom/gw03.hex +source_file = 1, /home/benny/work/fpga/projects/db/decode_c8a.tdf +source_file = 1, /home/benny/work/fpga/projects/db/mux_3nb.tdf design_name = spectrum instance = comp, \LED[0]~output , LED[0]~output, spectrum, 1 instance = comp, \LED[1]~output , LED[1]~output, spectrum, 1 @@ -27,61 +30,112 @@ instance = comp, \LED[6]~output , LED[6]~output, spectrum, 1 instance = comp, \LED[7]~output , LED[7]~output, spectrum, 1 instance = comp, \CLOCK_50~input , CLOCK_50~input, spectrum, 1 instance = comp, \CLOCK_50~inputclkctrl , CLOCK_50~inputclkctrl, spectrum, 1 -instance = comp, \counter[20] , counter[20], spectrum, 1 -instance = comp, \Add0~0 , Add0~0, spectrum, 1 +instance = comp, \counter[0]~63 , counter[0]~63, spectrum, 1 instance = comp, \counter[0] , counter[0], spectrum, 1 -instance = comp, \Add0~2 , Add0~2, spectrum, 1 +instance = comp, \counter[1]~21 , counter[1]~21, spectrum, 1 instance = comp, \counter[1] , counter[1], spectrum, 1 -instance = comp, \Add0~4 , Add0~4, spectrum, 1 +instance = comp, \counter[2]~23 , counter[2]~23, spectrum, 1 instance = comp, \counter[2] , counter[2], spectrum, 1 -instance = comp, \Add0~6 , Add0~6, spectrum, 1 +instance = comp, \counter[3]~25 , counter[3]~25, spectrum, 1 instance = comp, \counter[3] , counter[3], spectrum, 1 -instance = comp, \Add0~8 , Add0~8, spectrum, 1 +instance = comp, \counter[4]~27 , counter[4]~27, spectrum, 1 instance = comp, \counter[4] , counter[4], spectrum, 1 -instance = comp, \Add0~10 , Add0~10, spectrum, 1 +instance = comp, \counter[5]~29 , counter[5]~29, spectrum, 1 instance = comp, \counter[5] , counter[5], spectrum, 1 -instance = comp, \Add0~12 , Add0~12, spectrum, 1 +instance = comp, \counter[6]~31 , counter[6]~31, spectrum, 1 instance = comp, \counter[6] , counter[6], spectrum, 1 -instance = comp, \Add0~14 , Add0~14, spectrum, 1 +instance = comp, \counter[7]~33 , counter[7]~33, spectrum, 1 instance = comp, \counter[7] , counter[7], spectrum, 1 -instance = comp, \Add0~16 , Add0~16, spectrum, 1 +instance = comp, \counter[8]~35 , counter[8]~35, spectrum, 1 instance = comp, \counter[8] , counter[8], spectrum, 1 -instance = comp, \Add0~18 , Add0~18, spectrum, 1 +instance = comp, \counter[9]~37 , counter[9]~37, spectrum, 1 instance = comp, \counter[9] , counter[9], spectrum, 1 -instance = comp, \Add0~20 , Add0~20, spectrum, 1 +instance = comp, \counter[10]~39 , counter[10]~39, spectrum, 1 instance = comp, \counter[10] , counter[10], spectrum, 1 -instance = comp, \Add0~22 , Add0~22, spectrum, 1 +instance = comp, \counter[11]~41 , counter[11]~41, spectrum, 1 +instance = comp, \counter[11]~feeder , counter[11]~feeder, spectrum, 1 instance = comp, \counter[11] , counter[11], spectrum, 1 -instance = comp, \Add0~24 , Add0~24, spectrum, 1 +instance = comp, \counter[12]~43 , counter[12]~43, spectrum, 1 instance = comp, \counter[12] , counter[12], spectrum, 1 -instance = comp, \Add0~26 , Add0~26, spectrum, 1 +instance = comp, \counter[13]~45 , counter[13]~45, spectrum, 1 instance = comp, \counter[13] , counter[13], spectrum, 1 -instance = comp, \Add0~28 , Add0~28, spectrum, 1 +instance = comp, \counter[14]~47 , counter[14]~47, spectrum, 1 instance = comp, \counter[14] , counter[14], spectrum, 1 -instance = comp, \Add0~30 , Add0~30, spectrum, 1 +instance = comp, \counter[15]~49 , counter[15]~49, spectrum, 1 instance = comp, \counter[15] , counter[15], spectrum, 1 -instance = comp, \Add0~32 , Add0~32, spectrum, 1 +instance = comp, \counter[16]~51 , counter[16]~51, spectrum, 1 instance = comp, \counter[16] , counter[16], spectrum, 1 -instance = comp, \Add0~34 , Add0~34, spectrum, 1 +instance = comp, \counter[17]~53 , counter[17]~53, spectrum, 1 instance = comp, \counter[17] , counter[17], spectrum, 1 -instance = comp, \Add0~36 , Add0~36, spectrum, 1 +instance = comp, \counter[18]~55 , counter[18]~55, spectrum, 1 instance = comp, \counter[18] , counter[18], spectrum, 1 -instance = comp, \Add0~38 , Add0~38, spectrum, 1 +instance = comp, \counter[19]~57 , counter[19]~57, spectrum, 1 instance = comp, \counter[19] , counter[19], spectrum, 1 -instance = comp, \Add0~40 , Add0~40, spectrum, 1 instance = comp, \Equal0~5 , Equal0~5, spectrum, 1 -instance = comp, \Equal0~1 , Equal0~1, spectrum, 1 instance = comp, \Equal0~0 , Equal0~0, spectrum, 1 +instance = comp, \Equal0~1 , Equal0~1, spectrum, 1 instance = comp, \Equal0~2 , Equal0~2, spectrum, 1 instance = comp, \Equal0~3 , Equal0~3, spectrum, 1 instance = comp, \Equal0~4 , Equal0~4, spectrum, 1 -instance = comp, \address[0]~0 , address[0]~0, spectrum, 1 -instance = comp, \address[0] , address[0], spectrum, 1 -instance = comp, \Equal0~6 , Equal0~6, spectrum, 1 +instance = comp, \counter[20]~59 , counter[20]~59, spectrum, 1 +instance = comp, \counter[20] , counter[20], spectrum, 1 +instance = comp, \counter[21]~61 , counter[21]~61, spectrum, 1 +instance = comp, \counter[21] , counter[21], spectrum, 1 instance = comp, \Equal0~7 , Equal0~7, spectrum, 1 -instance = comp, \address[1]~1 , address[1]~1, spectrum, 1 +instance = comp, \address[0]~39 , address[0]~39, spectrum, 1 +instance = comp, \address[0] , address[0], spectrum, 1 +instance = comp, \address[1]~13 , address[1]~13, spectrum, 1 +instance = comp, \Equal0~6 , Equal0~6, spectrum, 1 instance = comp, \address[1] , address[1], spectrum, 1 -instance = comp, \address[1]~2 , address[1]~2, spectrum, 1 -instance = comp, \address[2]~3 , address[2]~3, spectrum, 1 +instance = comp, \address[2]~15 , address[2]~15, spectrum, 1 instance = comp, \address[2] , address[2], spectrum, 1 +instance = comp, \address[3]~17 , address[3]~17, spectrum, 1 +instance = comp, \address[3] , address[3], spectrum, 1 +instance = comp, \address[4]~19 , address[4]~19, spectrum, 1 +instance = comp, \address[4] , address[4], spectrum, 1 +instance = comp, \address[5]~21 , address[5]~21, spectrum, 1 +instance = comp, \address[5] , address[5], spectrum, 1 +instance = comp, \address[6]~23 , address[6]~23, spectrum, 1 +instance = comp, \address[6] , address[6], spectrum, 1 +instance = comp, \address[7]~25 , address[7]~25, spectrum, 1 +instance = comp, \address[7] , address[7], spectrum, 1 +instance = comp, \address[8]~27 , address[8]~27, spectrum, 1 +instance = comp, \address[8] , address[8], spectrum, 1 +instance = comp, \address[9]~29 , address[9]~29, spectrum, 1 +instance = comp, \address[9] , address[9], spectrum, 1 +instance = comp, \address[10]~31 , address[10]~31, spectrum, 1 +instance = comp, \address[10] , address[10], spectrum, 1 +instance = comp, \address[11]~33 , address[11]~33, spectrum, 1 +instance = comp, \address[11] , address[11], spectrum, 1 +instance = comp, \address[12]~35 , address[12]~35, spectrum, 1 +instance = comp, \address[12] , address[12], spectrum, 1 +instance = comp, \address[13]~37 , address[13]~37, spectrum, 1 +instance = comp, \address[13] , address[13], spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder , rom|altsyncram_component|auto_generated|address_reg_a[0]~feeder, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|address_reg_a[0] , rom|altsyncram_component|auto_generated|address_reg_a[0], spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder , rom|altsyncram_component|auto_generated|out_address_reg_a[0]~feeder, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|out_address_reg_a[0] , rom|altsyncram_component|auto_generated|out_address_reg_a[0], spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a8 , rom|altsyncram_component|auto_generated|ram_block1a8, spectrum, 1 instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a0 , rom|altsyncram_component|auto_generated|ram_block1a0, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[0]~0 , rom|altsyncram_component|auto_generated|mux2|result_node[0]~0, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a1 , rom|altsyncram_component|auto_generated|ram_block1a1, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a9 , rom|altsyncram_component|auto_generated|ram_block1a9, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[1]~1 , rom|altsyncram_component|auto_generated|mux2|result_node[1]~1, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a2 , rom|altsyncram_component|auto_generated|ram_block1a2, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a10 , rom|altsyncram_component|auto_generated|ram_block1a10, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[2]~2 , rom|altsyncram_component|auto_generated|mux2|result_node[2]~2, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a11 , rom|altsyncram_component|auto_generated|ram_block1a11, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a3 , rom|altsyncram_component|auto_generated|ram_block1a3, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[3]~3 , rom|altsyncram_component|auto_generated|mux2|result_node[3]~3, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a4 , rom|altsyncram_component|auto_generated|ram_block1a4, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a12 , rom|altsyncram_component|auto_generated|ram_block1a12, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[4]~4 , rom|altsyncram_component|auto_generated|mux2|result_node[4]~4, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a13 , rom|altsyncram_component|auto_generated|ram_block1a13, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a5 , rom|altsyncram_component|auto_generated|ram_block1a5, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[5]~5 , rom|altsyncram_component|auto_generated|mux2|result_node[5]~5, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a14 , rom|altsyncram_component|auto_generated|ram_block1a14, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a6 , rom|altsyncram_component|auto_generated|ram_block1a6, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[6]~6 , rom|altsyncram_component|auto_generated|mux2|result_node[6]~6, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a7 , rom|altsyncram_component|auto_generated|ram_block1a7, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a15 , rom|altsyncram_component|auto_generated|ram_block1a15, spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|mux2|result_node[7]~7 , rom|altsyncram_component|auto_generated|mux2|result_node[7]~7, spectrum, 1 diff --git a/simulation/modelsim/spectrum_v.sdo b/simulation/modelsim/spectrum_v.sdo index 7414a00..9b80f0c 100644 --- a/simulation/modelsim/spectrum_v.sdo +++ b/simulation/modelsim/spectrum_v.sdo @@ -29,7 +29,7 @@ (DELAYFILE (SDFVERSION "2.1") (DESIGN "spectrum") - (DATE "03/30/2022 12:38:42") + (DATE "03/30/2022 13:12:28") (VENDOR "Altera") (PROGRAM "Quartus II 32-bit") (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") @@ -41,7 +41,7 @@ (INSTANCE LED\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (1355:1355:1355) (1339:1339:1339)) + (PORT i (1643:1643:1643) (1694:1694:1694)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -51,7 +51,7 @@ (INSTANCE LED\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (1409:1409:1409) (1443:1443:1443)) + (PORT i (1565:1565:1565) (1603:1603:1603)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -61,7 +61,7 @@ (INSTANCE LED\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (1823:1823:1823) (1829:1829:1829)) + (PORT i (1737:1737:1737) (1749:1749:1749)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -71,7 +71,7 @@ (INSTANCE LED\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (1455:1455:1455) (1423:1423:1423)) + (PORT i (1124:1124:1124) (1166:1166:1166)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -81,7 +81,7 @@ (INSTANCE LED\[4\]\~output) (DELAY (ABSOLUTE - (PORT i (1759:1759:1759) (1776:1776:1776)) + (PORT i (1456:1456:1456) (1512:1512:1512)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) ) ) @@ -91,7 +91,7 @@ (INSTANCE LED\[5\]\~output) (DELAY (ABSOLUTE - (PORT i (1337:1337:1337) (1367:1367:1367)) + (PORT i (2115:2115:2115) (2173:2173:2173)) (IOPATH i o (4477:4477:4477) (4127:4127:4127)) ) ) @@ -101,7 +101,7 @@ (INSTANCE LED\[6\]\~output) (DELAY (ABSOLUTE - (PORT i (1855:1855:1855) (1871:1871:1871)) + (PORT i (2428:2428:2428) (2433:2433:2433)) (IOPATH i o (2455:2455:2455) (2378:2378:2378)) ) ) @@ -111,7 +111,7 @@ (INSTANCE LED\[7\]\~output) (DELAY (ABSOLUTE - (PORT i (1469:1469:1469) (1548:1548:1548)) + (PORT i (957:957:957) (1031:1031:1031)) (IOPATH i o (4477:4477:4477) (4127:4127:4127)) ) ) @@ -134,29 +134,12 @@ ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[20\]) - (DELAY - (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~0) + (INSTANCE counter\[0\]\~63) (DELAY (ABSOLUTE - (PORT dataa (243:243:243) (330:330:330)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH datac combout (353:353:353) (369:369:369)) ) ) ) @@ -165,7 +148,7 @@ (INSTANCE counter\[0\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -176,15 +159,16 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~2) + (INSTANCE counter\[1\]\~21) (DELAY (ABSOLUTE - (PORT datab (242:242:242) (324:324:324)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT dataa (253:253:253) (345:345:345)) + (PORT datab (251:251:251) (336:336:336)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datab combout (344:344:344) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) ) ) ) @@ -193,7 +177,7 @@ (INSTANCE counter\[1\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -204,11 +188,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~4) + (INSTANCE counter\[2\]\~23) (DELAY (ABSOLUTE - (PORT datab (242:242:242) (324:324:324)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT datab (251:251:251) (336:336:336)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) @@ -221,7 +205,7 @@ (INSTANCE counter\[2\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -232,11 +216,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~6) + (INSTANCE counter\[3\]\~25) (DELAY (ABSOLUTE - (PORT datab (242:242:242) (324:324:324)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT datab (250:250:250) (335:335:335)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) @@ -249,7 +233,7 @@ (INSTANCE counter\[3\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -260,12 +244,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~8) + (INSTANCE counter\[4\]\~27) (DELAY (ABSOLUTE - (PORT dataa (386:386:386) (458:458:458)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (250:250:250) (335:335:335)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -277,7 +261,7 @@ (INSTANCE counter\[4\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -288,11 +272,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~10) + (INSTANCE counter\[5\]\~29) (DELAY (ABSOLUTE - (PORT datab (380:380:380) (452:452:452)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT datab (263:263:263) (346:346:346)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) @@ -305,7 +289,7 @@ (INSTANCE counter\[5\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -316,11 +300,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~12) + (INSTANCE counter\[6\]\~31) (DELAY (ABSOLUTE - (PORT dataa (386:386:386) (458:458:458)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (PORT dataa (252:252:252) (342:342:342)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) @@ -333,7 +317,7 @@ (INSTANCE counter\[6\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -344,11 +328,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~14) + (INSTANCE counter\[7\]\~33) (DELAY (ABSOLUTE - (PORT datab (380:380:380) (450:450:450)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT datab (250:250:250) (335:335:335)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) @@ -361,7 +345,7 @@ (INSTANCE counter\[7\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -372,12 +356,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~16) + (INSTANCE counter\[8\]\~35) (DELAY (ABSOLUTE - (PORT datab (240:240:240) (322:322:322)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (251:251:251) (341:341:341)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -389,7 +373,7 @@ (INSTANCE counter\[8\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -400,12 +384,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~18) + (INSTANCE counter\[9\]\~37) (DELAY (ABSOLUTE - (PORT dataa (242:242:242) (328:328:328)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (249:249:249) (333:333:333)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -417,7 +401,7 @@ (INSTANCE counter\[9\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -428,12 +412,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~20) + (INSTANCE counter\[10\]\~39) (DELAY (ABSOLUTE - (PORT datab (239:239:239) (321:321:321)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (252:252:252) (340:340:340)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -445,7 +429,7 @@ (INSTANCE counter\[10\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -456,24 +440,34 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~22) + (INSTANCE counter\[11\]\~41) (DELAY (ABSOLUTE - (PORT datab (388:388:388) (452:452:452)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (704:704:704) (765:765:765)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) ) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE counter\[11\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (318:318:318) (335:335:335)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE counter\[11\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -484,11 +478,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~24) + (INSTANCE counter\[12\]\~43) (DELAY (ABSOLUTE - (PORT datab (382:382:382) (451:451:451)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT datab (248:248:248) (333:333:333)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) @@ -501,7 +495,7 @@ (INSTANCE counter\[12\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -512,11 +506,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~26) + (INSTANCE counter\[13\]\~45) (DELAY (ABSOLUTE - (PORT datab (387:387:387) (451:451:451)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT datab (249:249:249) (335:335:335)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) @@ -529,7 +523,7 @@ (INSTANCE counter\[13\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -540,11 +534,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~28) + (INSTANCE counter\[14\]\~47) (DELAY (ABSOLUTE - (PORT dataa (380:380:380) (458:458:458)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (PORT dataa (251:251:251) (342:342:342)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) @@ -557,7 +551,7 @@ (INSTANCE counter\[14\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -568,11 +562,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~30) + (INSTANCE counter\[15\]\~49) (DELAY (ABSOLUTE - (PORT datab (387:387:387) (452:452:452)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT datab (251:251:251) (335:335:335)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) @@ -585,7 +579,7 @@ (INSTANCE counter\[15\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -596,12 +590,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~32) + (INSTANCE counter\[16\]\~51) (DELAY (ABSOLUTE - (PORT datab (379:379:379) (454:454:454)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (253:253:253) (343:343:343)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -613,7 +607,7 @@ (INSTANCE counter\[16\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -624,11 +618,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~34) + (INSTANCE counter\[17\]\~53) (DELAY (ABSOLUTE - (PORT dataa (388:388:388) (458:458:458)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT dataa (253:253:253) (345:345:345)) + (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) @@ -641,7 +635,7 @@ (INSTANCE counter\[17\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -652,12 +646,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~36) + (INSTANCE counter\[18\]\~55) (DELAY (ABSOLUTE - (PORT dataa (386:386:386) (458:458:458)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (252:252:252) (338:338:338)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -669,7 +663,7 @@ (INSTANCE counter\[18\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -680,12 +674,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~38) + (INSTANCE counter\[19\]\~57) (DELAY (ABSOLUTE - (PORT dataa (383:383:383) (460:460:460)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (252:252:252) (338:338:338)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -697,7 +691,7 @@ (INSTANCE counter\[19\]) (DELAY (ABSOLUTE - (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -706,42 +700,15 @@ (HOLD d (posedge clk) (157:157:157)) ) ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Add0\~40) - (DELAY - (ABSOLUTE - (PORT datad (218:218:218) (287:287:287)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - ) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE Equal0\~5) (DELAY (ABSOLUTE - (PORT dataa (210:210:210) (257:257:257)) - (PORT datab (208:208:208) (249:249:249)) - (PORT datac (181:181:181) (219:219:219)) - (PORT datad (181:181:181) (209:209:209)) - (IOPATH dataa combout (350:350:350) (366:366:366)) - (IOPATH datab combout (350:350:350) (368:368:368)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal0\~1) - (DELAY - (ABSOLUTE - (PORT dataa (201:201:201) (245:245:245)) - (PORT datab (199:199:199) (238:238:238)) - (PORT datac (173:173:173) (206:206:206)) - (PORT datad (174:174:174) (200:200:200)) + (PORT dataa (254:254:254) (346:346:346)) + (PORT datab (252:252:252) (336:336:336)) + (PORT datac (225:225:225) (305:305:305)) + (PORT datad (226:226:226) (300:300:300)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -754,10 +721,26 @@ (INSTANCE Equal0\~0) (DELAY (ABSOLUTE - (PORT dataa (343:343:343) (371:371:371)) - (PORT datab (336:336:336) (366:366:366)) - (PORT datac (312:312:312) (338:338:338)) - (PORT datad (318:318:318) (328:328:328)) + (PORT dataa (253:253:253) (343:343:343)) + (PORT datab (250:250:250) (336:336:336)) + (PORT datac (224:224:224) (302:302:302)) + (PORT datad (225:225:225) (296:296:296)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (253:253:253) (344:344:344)) + (PORT datab (251:251:251) (337:337:337)) + (PORT datac (381:381:381) (440:440:440)) + (PORT datad (225:225:225) (297:297:297)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -770,10 +753,10 @@ (INSTANCE Equal0\~2) (DELAY (ABSOLUTE - (PORT dataa (375:375:375) (396:396:396)) - (PORT datab (637:637:637) (652:652:652)) - (PORT datac (334:334:334) (353:353:353)) - (PORT datad (562:562:562) (570:570:570)) + (PORT dataa (255:255:255) (347:347:347)) + (PORT datab (262:262:262) (344:344:344)) + (PORT datac (226:226:226) (308:308:308)) + (PORT datad (228:228:228) (300:300:300)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -786,10 +769,10 @@ (INSTANCE Equal0\~3) (DELAY (ABSOLUTE - (PORT dataa (203:203:203) (247:247:247)) - (PORT datab (201:201:201) (241:241:241)) - (PORT datac (174:174:174) (208:208:208)) - (PORT datad (175:175:175) (201:201:201)) + (PORT dataa (254:254:254) (346:346:346)) + (PORT datab (253:253:253) (339:339:339)) + (PORT datac (225:225:225) (305:305:305)) + (PORT datad (227:227:227) (300:300:300)) (IOPATH dataa combout (350:350:350) (366:366:366)) (IOPATH datab combout (350:350:350) (368:368:368)) (IOPATH datac combout (241:241:241) (241:241:241)) @@ -802,10 +785,10 @@ (INSTANCE Equal0\~4) (DELAY (ABSOLUTE - (PORT dataa (612:612:612) (640:640:640)) - (PORT datab (820:820:820) (843:843:843)) - (PORT datac (170:170:170) (203:203:203)) - (PORT datad (305:305:305) (321:321:321)) + (PORT dataa (337:337:337) (370:370:370)) + (PORT datab (345:345:345) (370:370:370)) + (PORT datac (335:335:335) (354:354:354)) + (PORT datad (589:589:589) (601:601:601)) (IOPATH dataa combout (300:300:300) (307:307:307)) (IOPATH datab combout (300:300:300) (308:308:308)) (IOPATH datac combout (241:241:241) (242:242:242)) @@ -815,14 +798,79 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[0\]\~0) + (INSTANCE counter\[20\]\~59) (DELAY (ABSOLUTE - (PORT dataa (601:601:601) (619:619:619)) - (PORT datab (378:378:378) (401:401:401)) - (PORT datad (189:189:189) (221:221:221)) - (IOPATH dataa combout (325:325:325) (320:320:320)) - (IOPATH datab combout (304:304:304) (308:308:308)) + (PORT datab (264:264:264) (347:347:347)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE counter\[20\]) + (DELAY + (ABSOLUTE + (PORT clk (1898:1898:1898) (1920:1920:1920)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE counter\[21\]\~61) + (DELAY + (ABSOLUTE + (PORT datad (239:239:239) (309:309:309)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE counter\[21\]) + (DELAY + (ABSOLUTE + (PORT clk (1898:1898:1898) (1920:1920:1920)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~7) + (DELAY + (ABSOLUTE + (PORT datac (669:669:669) (728:728:728)) + (PORT datad (646:646:646) (700:700:700)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[0\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (663:663:663)) + (PORT datab (207:207:207) (248:248:248)) + (PORT datad (330:330:330) (347:347:347)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) @@ -833,7 +881,7 @@ (INSTANCE address\[0\]) (DELAY (ABSOLUTE - (PORT clk (1897:1897:1897) (1919:1919:1919)) + (PORT clk (1868:1868:1868) (1877:1877:1877)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -842,45 +890,33 @@ (HOLD d (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (268:268:268) (356:356:356)) + (PORT datab (261:261:261) (343:343:343)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_lcell_comb") (INSTANCE Equal0\~6) (DELAY (ABSOLUTE - (PORT datac (181:181:181) (219:219:219)) - (PORT datad (183:183:183) (214:214:214)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE Equal0\~7) - (DELAY - (ABSOLUTE - (PORT dataa (364:364:364) (391:391:391)) - (PORT datab (207:207:207) (248:248:248)) - (PORT datac (171:171:171) (204:204:204)) - (PORT datad (181:181:181) (208:208:208)) - (IOPATH dataa combout (337:337:337) (338:338:338)) - (IOPATH datab combout (337:337:337) (348:348:348)) - (IOPATH datac combout (243:243:243) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[1\]\~1) - (DELAY - (ABSOLUTE - (PORT dataa (595:595:595) (669:669:669)) - (PORT datab (216:216:216) (261:261:261)) - (PORT datad (332:332:332) (350:350:350)) - (IOPATH dataa combout (324:324:324) (328:328:328)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT dataa (707:707:707) (763:763:763)) + (PORT datab (674:674:674) (730:730:730)) + (PORT datac (613:613:613) (625:625:625)) + (PORT datad (181:181:181) (210:210:210)) + (IOPATH dataa combout (301:301:301) (299:299:299)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) @@ -890,7 +926,390 @@ (INSTANCE address\[1\]) (DELAY (ABSOLUTE - (PORT clk (1897:1897:1897) (1919:1919:1919)) + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (795:795:795) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[2\]\~15) + (DELAY + (ABSOLUTE + (PORT datab (261:261:261) (343:343:343)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (795:795:795) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[3\]\~17) + (DELAY + (ABSOLUTE + (PORT datab (282:282:282) (364:364:364)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (795:795:795) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[4\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (265:265:265) (351:351:351)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (795:795:795) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[5\]\~21) + (DELAY + (ABSOLUTE + (PORT datab (263:263:263) (345:345:345)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (795:795:795) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[6\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (266:266:266) (353:353:353)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (795:795:795) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[7\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (266:266:266) (353:353:353)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (795:795:795) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[8\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (264:264:264) (347:347:347)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (795:795:795) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[9\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (264:264:264) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (795:795:795) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[10\]\~31) + (DELAY + (ABSOLUTE + (PORT datab (264:264:264) (347:347:347)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (795:795:795) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[11\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (264:264:264) (347:347:347)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datab cout (446:446:446) (318:318:318)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (795:795:795) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[12\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (266:266:266) (352:352:352)) + (IOPATH dataa combout (356:356:356) (368:368:368)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (795:795:795) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[13\]\~37) + (DELAY + (ABSOLUTE + (PORT datad (258:258:258) (327:327:327)) + (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT d (74:74:74) (91:91:91)) + (PORT ena (795:795:795) (792:792:792)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + (HOLD ena (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (428:428:428) (485:485:485)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE rom\|altsyncram_component\|auto_generated\|address_reg_a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1531:1531:1531) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -901,39 +1320,20 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[1\]\~2) + (INSTANCE rom\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]\~feeder) (DELAY (ABSOLUTE - (PORT dataa (597:597:597) (670:670:670)) - (PORT datab (381:381:381) (404:404:404)) - (PORT datac (574:574:574) (583:583:583)) - (PORT datad (191:191:191) (224:224:224)) - (IOPATH dataa combout (300:300:300) (308:308:308)) - (IOPATH datab combout (300:300:300) (311:311:311)) - (IOPATH datac combout (241:241:241) (241:241:241)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE address\[2\]\~3) - (DELAY - (ABSOLUTE - (PORT datab (398:398:398) (468:468:468)) - (PORT datad (175:175:175) (201:201:201)) - (IOPATH datab combout (333:333:333) (332:332:332)) - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT datad (220:220:220) (290:290:290)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE address\[2\]) + (INSTANCE rom\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]) (DELAY (ABSOLUTE - (PORT clk (1897:1897:1897) (1919:1919:1919)) + (PORT clk (1531:1531:1531) (1545:1545:1545)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -942,15 +1342,122 @@ (HOLD d (posedge clk) (157:157:157)) ) ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1232:1232:1232) (1314:1314:1314)) + (PORT d[1] (1273:1273:1273) (1381:1381:1381)) + (PORT d[2] (1342:1342:1342) (1456:1456:1456)) + (PORT d[3] (1317:1317:1317) (1435:1435:1435)) + (PORT d[4] (1249:1249:1249) (1341:1341:1341)) + (PORT d[5] (1362:1362:1362) (1458:1458:1458)) + (PORT d[6] (1704:1704:1704) (1869:1869:1869)) + (PORT d[7] (1310:1310:1310) (1434:1434:1434)) + (PORT d[8] (1316:1316:1316) (1419:1419:1419)) + (PORT d[9] (1359:1359:1359) (1447:1447:1447)) + (PORT d[10] (1320:1320:1320) (1425:1425:1425)) + (PORT d[11] (1570:1570:1570) (1654:1654:1654)) + (PORT d[12] (1289:1289:1289) (1390:1390:1390)) + (PORT clk (1856:1856:1856) (1882:1882:1882)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1882:1882:1882)) + (PORT d[0] (1167:1167:1167) (1189:1189:1189)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1883:1883:1883)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1845:1845:1845)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1008:1008:1008)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_ram_register") (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) (DELAY (ABSOLUTE - (PORT d[0] (1263:1263:1263) (1361:1361:1361)) - (PORT d[1] (1538:1538:1538) (1608:1608:1608)) - (PORT d[2] (1534:1534:1534) (1635:1635:1635)) - (PORT clk (1857:1857:1857) (1884:1884:1884)) + (PORT d[0] (1152:1152:1152) (1246:1246:1246)) + (PORT d[1] (973:973:973) (1069:1069:1069)) + (PORT d[2] (1034:1034:1034) (1138:1138:1138)) + (PORT d[3] (1341:1341:1341) (1439:1439:1439)) + (PORT d[4] (1248:1248:1248) (1333:1333:1333)) + (PORT d[5] (1325:1325:1325) (1408:1408:1408)) + (PORT d[6] (1491:1491:1491) (1664:1664:1664)) + (PORT d[7] (1263:1263:1263) (1339:1339:1339)) + (PORT d[8] (1326:1326:1326) (1417:1417:1417)) + (PORT d[9] (1388:1388:1388) (1482:1482:1482)) + (PORT d[10] (1305:1305:1305) (1406:1406:1406)) + (PORT d[11] (1274:1274:1274) (1349:1349:1349)) + (PORT d[12] (1340:1340:1340) (1438:1438:1438)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) ) ) (TIMINGCHECK @@ -962,7 +1469,8 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) (DELAY (ABSOLUTE - (PORT clk (1857:1857:1857) (1884:1884:1884)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + (PORT d[0] (954:954:954) (925:925:925)) ) ) ) @@ -971,7 +1479,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1858:1858:1858) (1885:1885:1885)) + (PORT clk (1858:1858:1858) (1884:1884:1884)) (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) ) ) @@ -981,7 +1489,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) (DELAY (ABSOLUTE - (PORT clk (1820:1820:1820) (1847:1847:1847)) + (PORT clk (1820:1820:1820) (1846:1846:1846)) (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) @@ -995,7 +1503,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) (DELAY (ABSOLUTE - (PORT clk (1005:1005:1005) (1010:1010:1010)) + (PORT clk (1005:1005:1005) (1009:1009:1009)) ) ) ) @@ -1004,7 +1512,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1006:1006:1006) (1011:1011:1011)) + (PORT clk (1006:1006:1006) (1010:1010:1010)) ) ) ) @@ -1013,7 +1521,7 @@ (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1006:1006:1006) (1011:1011:1011)) + (PORT clk (1006:1006:1006) (1010:1010:1010)) (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) @@ -1021,6 +1529,523 @@ (CELL (CELLTYPE "cycloneive_ram_pulse_generator") (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (956:956:956) (1072:1072:1072)) + (PORT datac (880:880:880) (883:883:883)) + (PORT datad (605:605:605) (612:612:612)) + (IOPATH datab combout (342:342:342) (342:342:342)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1457:1457:1457) (1535:1535:1535)) + (PORT d[1] (1538:1538:1538) (1599:1599:1599)) + (PORT d[2] (1565:1565:1565) (1669:1669:1669)) + (PORT d[3] (1248:1248:1248) (1294:1294:1294)) + (PORT d[4] (1607:1607:1607) (1738:1738:1738)) + (PORT d[5] (1904:1904:1904) (2043:2043:2043)) + (PORT d[6] (1250:1250:1250) (1306:1306:1306)) + (PORT d[7] (1340:1340:1340) (1441:1441:1441)) + (PORT d[8] (1887:1887:1887) (2029:2029:2029)) + (PORT d[9] (1230:1230:1230) (1303:1303:1303)) + (PORT d[10] (1415:1415:1415) (1517:1517:1517)) + (PORT d[11] (1208:1208:1208) (1273:1273:1273)) + (PORT d[12] (1256:1256:1256) (1338:1338:1338)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1875:1875:1875)) + (PORT d[0] (1141:1141:1141) (1128:1128:1128)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1500:1500:1500) (1594:1594:1594)) + (PORT d[1] (1355:1355:1355) (1470:1470:1470)) + (PORT d[2] (1591:1591:1591) (1703:1703:1703)) + (PORT d[3] (1336:1336:1336) (1417:1417:1417)) + (PORT d[4] (1313:1313:1313) (1422:1422:1422)) + (PORT d[5] (1595:1595:1595) (1733:1733:1733)) + (PORT d[6] (1268:1268:1268) (1373:1373:1373)) + (PORT d[7] (1255:1255:1255) (1355:1355:1355)) + (PORT d[8] (1615:1615:1615) (1750:1750:1750)) + (PORT d[9] (1326:1326:1326) (1421:1421:1421)) + (PORT d[10] (1812:1812:1812) (1937:1937:1937)) + (PORT d[11] (1293:1293:1293) (1402:1402:1402)) + (PORT d[12] (1561:1561:1561) (1676:1676:1676)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1875:1875:1875)) + (PORT d[0] (1207:1207:1207) (1256:1256:1256)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (626:626:626) (652:652:652)) + (PORT datac (877:877:877) (907:907:907)) + (PORT datad (1342:1342:1342) (1396:1396:1396)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1238:1238:1238) (1323:1323:1323)) + (PORT d[1] (1282:1282:1282) (1374:1374:1374)) + (PORT d[2] (1603:1603:1603) (1716:1716:1716)) + (PORT d[3] (1381:1381:1381) (1467:1467:1467)) + (PORT d[4] (1282:1282:1282) (1376:1376:1376)) + (PORT d[5] (1277:1277:1277) (1395:1395:1395)) + (PORT d[6] (1716:1716:1716) (1879:1879:1879)) + (PORT d[7] (1344:1344:1344) (1433:1433:1433)) + (PORT d[8] (1329:1329:1329) (1433:1433:1433)) + (PORT d[9] (1412:1412:1412) (1507:1507:1507)) + (PORT d[10] (1764:1764:1764) (1843:1843:1843)) + (PORT d[11] (1578:1578:1578) (1656:1656:1656)) + (PORT d[12] (1322:1322:1322) (1422:1422:1422)) + (PORT clk (1855:1855:1855) (1880:1880:1880)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1855:1855:1855) (1880:1880:1880)) + (PORT d[0] (1242:1242:1242) (1194:1194:1194)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1881:1881:1881)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1843:1843:1843)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1003:1003:1003) (1006:1006:1006)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1004:1004:1004) (1007:1007:1007)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (963:963:963) (1054:1054:1054)) + (PORT d[1] (1258:1258:1258) (1343:1343:1343)) + (PORT d[2] (1047:1047:1047) (1135:1135:1135)) + (PORT d[3] (1074:1074:1074) (1167:1167:1167)) + (PORT d[4] (966:966:966) (1059:1059:1059)) + (PORT d[5] (1239:1239:1239) (1332:1332:1332)) + (PORT d[6] (1463:1463:1463) (1631:1631:1631)) + (PORT d[7] (1262:1262:1262) (1338:1338:1338)) + (PORT d[8] (1053:1053:1053) (1156:1156:1156)) + (PORT d[9] (1100:1100:1100) (1206:1206:1206)) + (PORT d[10] (1512:1512:1512) (1581:1581:1581)) + (PORT d[11] (1273:1273:1273) (1348:1348:1348)) + (PORT d[12] (1313:1313:1313) (1405:1405:1405)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1883:1883:1883)) + (PORT d[0] (924:924:924) (953:953:953)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT datab (980:980:980) (1094:1094:1094)) + (PORT datac (902:902:902) (940:940:940)) + (PORT datad (596:596:596) (601:601:601)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (930:930:930) (988:988:988)) + (PORT d[1] (979:979:979) (1053:1053:1053)) + (PORT d[2] (1080:1080:1080) (1156:1156:1156)) + (PORT d[3] (1058:1058:1058) (1130:1130:1130)) + (PORT d[4] (956:956:956) (1028:1028:1028)) + (PORT d[5] (1006:1006:1006) (1083:1083:1083)) + (PORT d[6] (1424:1424:1424) (1563:1563:1563)) + (PORT d[7] (1240:1240:1240) (1316:1316:1316)) + (PORT d[8] (1625:1625:1625) (1738:1738:1738)) + (PORT d[9] (1086:1086:1086) (1162:1162:1162)) + (PORT d[10] (1042:1042:1042) (1125:1125:1125)) + (PORT d[11] (1300:1300:1300) (1361:1361:1361)) + (PORT d[12] (1299:1299:1299) (1370:1370:1370)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (PORT d[0] (908:908:908) (912:912:912)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1847:1847:1847)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b) (DELAY (ABSOLUTE (PORT clk (1006:1006:1006) (1011:1011:1011)) @@ -1028,4 +2053,957 @@ ) ) ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1205:1205:1205) (1260:1260:1260)) + (PORT d[1] (651:651:651) (711:711:711)) + (PORT d[2] (713:713:713) (781:781:781)) + (PORT d[3] (760:760:760) (830:830:830)) + (PORT d[4] (659:659:659) (721:721:721)) + (PORT d[5] (734:734:734) (814:814:814)) + (PORT d[6] (761:761:761) (832:832:832)) + (PORT d[7] (740:740:740) (819:819:819)) + (PORT d[8] (756:756:756) (828:828:828)) + (PORT d[9] (769:769:769) (847:847:847)) + (PORT d[10] (1226:1226:1226) (1292:1292:1292)) + (PORT d[11] (741:741:741) (813:813:813)) + (PORT d[12] (751:751:751) (826:826:826)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1884:1884:1884)) + (PORT d[0] (642:642:642) (628:628:628)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1847:1847:1847)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (918:918:918) (939:939:939)) + (PORT datac (648:648:648) (723:723:723)) + (PORT datad (603:603:603) (610:610:610)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1471:1471:1471) (1551:1551:1551)) + (PORT d[1] (1529:1529:1529) (1590:1590:1590)) + (PORT d[2] (1557:1557:1557) (1660:1660:1660)) + (PORT d[3] (988:988:988) (1045:1045:1045)) + (PORT d[4] (976:976:976) (1062:1062:1062)) + (PORT d[5] (1604:1604:1604) (1749:1749:1749)) + (PORT d[6] (996:996:996) (1079:1079:1079)) + (PORT d[7] (948:948:948) (1026:1026:1026)) + (PORT d[8] (1601:1601:1601) (1742:1742:1742)) + (PORT d[9] (998:998:998) (1064:1064:1064)) + (PORT d[10] (979:979:979) (1057:1057:1057)) + (PORT d[11] (958:958:958) (1040:1040:1040)) + (PORT d[12] (969:969:969) (1047:1047:1047)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1875:1875:1875)) + (PORT d[0] (904:904:904) (885:885:885)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1219:1219:1219) (1307:1307:1307)) + (PORT d[1] (1255:1255:1255) (1323:1323:1323)) + (PORT d[2] (1279:1279:1279) (1381:1381:1381)) + (PORT d[3] (1279:1279:1279) (1328:1328:1328)) + (PORT d[4] (1603:1603:1603) (1733:1733:1733)) + (PORT d[5] (1603:1603:1603) (1748:1748:1748)) + (PORT d[6] (1281:1281:1281) (1369:1369:1369)) + (PORT d[7] (1245:1245:1245) (1325:1325:1325)) + (PORT d[8] (1600:1600:1600) (1741:1741:1741)) + (PORT d[9] (1266:1266:1266) (1335:1335:1335)) + (PORT d[10] (1838:1838:1838) (1967:1967:1967)) + (PORT d[11] (1283:1283:1283) (1373:1373:1373)) + (PORT d[12] (1245:1245:1245) (1330:1330:1330)) + (PORT clk (1849:1849:1849) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1875:1875:1875)) + (PORT d[0] (1151:1151:1151) (1179:1179:1179)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (998:998:998) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~4) + (DELAY + (ABSOLUTE + (PORT datab (640:640:640) (651:651:651)) + (PORT datac (859:859:859) (855:855:855)) + (PORT datad (794:794:794) (853:853:853)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1508:1508:1508) (1612:1612:1612)) + (PORT d[1] (1896:1896:1896) (2041:2041:2041)) + (PORT d[2] (1251:1251:1251) (1359:1359:1359)) + (PORT d[3] (1319:1319:1319) (1368:1368:1368)) + (PORT d[4] (1294:1294:1294) (1407:1407:1407)) + (PORT d[5] (1248:1248:1248) (1360:1360:1360)) + (PORT d[6] (1297:1297:1297) (1411:1411:1411)) + (PORT d[7] (1260:1260:1260) (1366:1366:1366)) + (PORT d[8] (1608:1608:1608) (1726:1726:1726)) + (PORT d[9] (1309:1309:1309) (1408:1408:1408)) + (PORT d[10] (1860:1860:1860) (1990:1990:1990)) + (PORT d[11] (1271:1271:1271) (1381:1381:1381)) + (PORT d[12] (1527:1527:1527) (1637:1637:1637)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1875:1875:1875)) + (PORT d[0] (1193:1193:1193) (1239:1239:1239)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1555:1555:1555) (1667:1667:1667)) + (PORT d[1] (1626:1626:1626) (1776:1776:1776)) + (PORT d[2] (1557:1557:1557) (1668:1668:1668)) + (PORT d[3] (1644:1644:1644) (1709:1709:1709)) + (PORT d[4] (1593:1593:1593) (1715:1715:1715)) + (PORT d[5] (1575:1575:1575) (1680:1680:1680)) + (PORT d[6] (1565:1565:1565) (1670:1670:1670)) + (PORT d[7] (1531:1531:1531) (1632:1632:1632)) + (PORT d[8] (1555:1555:1555) (1659:1659:1659)) + (PORT d[9] (1587:1587:1587) (1682:1682:1682)) + (PORT d[10] (1533:1533:1533) (1638:1638:1638)) + (PORT d[11] (1559:1559:1559) (1667:1667:1667)) + (PORT d[12] (1527:1527:1527) (1639:1639:1639)) + (PORT clk (1847:1847:1847) (1874:1874:1874)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1874:1874:1874)) + (PORT d[0] (1489:1489:1489) (1442:1442:1442)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1875:1875:1875)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1810:1810:1810) (1837:1837:1837)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (1000:1000:1000)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (626:626:626) (635:635:635)) + (PORT datac (909:909:909) (911:911:911)) + (PORT datad (1120:1120:1120) (1222:1222:1222)) + (IOPATH datab combout (306:306:306) (311:311:311)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (965:965:965) (1030:1030:1030)) + (PORT d[1] (1241:1241:1241) (1329:1329:1329)) + (PORT d[2] (1056:1056:1056) (1157:1157:1157)) + (PORT d[3] (1088:1088:1088) (1177:1177:1177)) + (PORT d[4] (990:990:990) (1084:1084:1084)) + (PORT d[5] (1067:1067:1067) (1137:1137:1137)) + (PORT d[6] (1434:1434:1434) (1593:1593:1593)) + (PORT d[7] (1278:1278:1278) (1382:1382:1382)) + (PORT d[8] (1052:1052:1052) (1156:1156:1156)) + (PORT d[9] (1060:1060:1060) (1159:1159:1159)) + (PORT d[10] (1022:1022:1022) (1126:1126:1126)) + (PORT d[11] (1256:1256:1256) (1351:1351:1351)) + (PORT d[12] (1309:1309:1309) (1400:1400:1400)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1883:1883:1883)) + (PORT d[0] (918:918:918) (941:941:941)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (921:921:921) (982:982:982)) + (PORT d[1] (652:652:652) (711:711:711)) + (PORT d[2] (1323:1323:1323) (1400:1400:1400)) + (PORT d[3] (1338:1338:1338) (1452:1452:1452)) + (PORT d[4] (929:929:929) (988:988:988)) + (PORT d[5] (1048:1048:1048) (1131:1131:1131)) + (PORT d[6] (1394:1394:1394) (1522:1522:1522)) + (PORT d[7] (1240:1240:1240) (1309:1309:1309)) + (PORT d[8] (1638:1638:1638) (1740:1740:1740)) + (PORT d[9] (1048:1048:1048) (1110:1110:1110)) + (PORT d[10] (1044:1044:1044) (1103:1103:1103)) + (PORT d[11] (1204:1204:1204) (1263:1263:1263)) + (PORT d[12] (1258:1258:1258) (1304:1304:1304)) + (PORT clk (1857:1857:1857) (1883:1883:1883)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1883:1883:1883)) + (PORT d[0] (887:887:887) (888:888:888)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1884:1884:1884)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1846:1846:1846)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1005:1005:1005) (1009:1009:1009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1006:1006:1006) (1010:1010:1010)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (694:694:694) (743:743:743)) + (PORT datac (917:917:917) (955:955:955)) + (PORT datad (347:347:347) (362:362:362)) + (IOPATH dataa combout (341:341:341) (347:347:347)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1471:1471:1471) (1578:1578:1578)) + (PORT d[1] (1888:1888:1888) (2030:2030:2030)) + (PORT d[2] (1880:1880:1880) (2006:2006:2006)) + (PORT d[3] (1371:1371:1371) (1434:1434:1434)) + (PORT d[4] (1886:1886:1886) (2001:2001:2001)) + (PORT d[5] (1321:1321:1321) (1439:1439:1439)) + (PORT d[6] (1325:1325:1325) (1443:1443:1443)) + (PORT d[7] (1261:1261:1261) (1367:1367:1367)) + (PORT d[8] (1312:1312:1312) (1427:1427:1427)) + (PORT d[9] (1283:1283:1283) (1377:1377:1377)) + (PORT d[10] (1803:1803:1803) (1907:1907:1907)) + (PORT d[11] (1272:1272:1272) (1382:1382:1382)) + (PORT d[12] (1256:1256:1256) (1366:1366:1366)) + (PORT clk (1848:1848:1848) (1875:1875:1875)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1875:1875:1875)) + (PORT d[0] (1266:1266:1266) (1210:1210:1210)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1876:1876:1876)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1811:1811:1811) (1838:1838:1838)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (996:996:996) (1001:1001:1001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (997:997:997) (1002:1002:1002)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1817:1817:1817) (1923:1923:1923)) + (PORT d[1] (1607:1607:1607) (1705:1705:1705)) + (PORT d[2] (1576:1576:1576) (1716:1716:1716)) + (PORT d[3] (1616:1616:1616) (1679:1679:1679)) + (PORT d[4] (1594:1594:1594) (1718:1718:1718)) + (PORT d[5] (1563:1563:1563) (1701:1701:1701)) + (PORT d[6] (1548:1548:1548) (1655:1655:1655)) + (PORT d[7] (1539:1539:1539) (1642:1642:1642)) + (PORT d[8] (1532:1532:1532) (1634:1634:1634)) + (PORT d[9] (1589:1589:1589) (1705:1705:1705)) + (PORT d[10] (1503:1503:1503) (1601:1601:1601)) + (PORT d[11] (1561:1561:1561) (1686:1686:1686)) + (PORT d[12] (1531:1531:1531) (1649:1649:1649)) + (PORT clk (1846:1846:1846) (1872:1872:1872)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (187:187:187)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1872:1872:1872)) + (PORT d[0] (1495:1495:1495) (1543:1543:1543)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1847:1847:1847) (1873:1873:1873)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1809:1809:1809) (1835:1835:1835)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (994:994:994) (998:998:998)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (995:995:995) (999:999:999)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT datab (636:636:636) (645:645:645)) + (PORT datac (906:906:906) (905:905:905)) + (PORT datad (1123:1123:1123) (1224:1224:1224)) + (IOPATH datab combout (355:355:355) (369:369:369)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) ) diff --git a/spectrum.v b/spectrum.v index 50dc56a..496dc28 100644 --- a/spectrum.v +++ b/spectrum.v @@ -3,7 +3,7 @@ module spectrum( output wire[7:0] LED ); -reg[2:0] address; +reg[13:0] address; wire[7:0] mem_data; rom0 rom( @@ -12,12 +12,12 @@ rom0 rom( .q(mem_data) ); -reg[20:0] counter; +reg[21:0] counter; always @(posedge CLOCK_50) begin - counter = counter + 1; + counter <= counter + 1; if (counter == 0) - address = address + 1; + address <= address + 1; end assign LED = mem_data;