3010 lines
87 KiB
Plaintext
3010 lines
87 KiB
Plaintext
// Copyright (C) 1991-2013 Altera Corporation
|
|
// Your use of Altera Corporation's design tools, logic functions
|
|
// and other software and tools, and its AMPP partner logic
|
|
// functions, and any output files from any of the foregoing
|
|
// (including device programming or simulation files), and any
|
|
// associated documentation or information are expressly subject
|
|
// to the terms and conditions of the Altera Program License
|
|
// Subscription Agreement, Altera MegaCore Function License
|
|
// Agreement, or other applicable license agreement, including,
|
|
// without limitation, that your use is for the sole purpose of
|
|
// programming logic devices manufactured by Altera and sold by
|
|
// Altera or its authorized distributors. Please refer to the
|
|
// applicable agreement for further details.
|
|
|
|
|
|
//
|
|
// Device: Altera EP4CE22F17C6 Package FBGA256
|
|
//
|
|
|
|
//
|
|
// This file contains Fast Corner delays for the design using part EP4CE22F17C6,
|
|
// with speed grade M, core voltage 1.2V, and temperature 0 Celsius
|
|
//
|
|
|
|
//
|
|
// This SDF file should be used for ModelSim-Altera (Verilog) only
|
|
//
|
|
|
|
(DELAYFILE
|
|
(SDFVERSION "2.1")
|
|
(DESIGN "spectrum")
|
|
(DATE "03/30/2022 13:12:28")
|
|
(VENDOR "Altera")
|
|
(PROGRAM "Quartus II 32-bit")
|
|
(VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
|
|
(DIVIDER .)
|
|
(TIMESCALE 1 ps)
|
|
|
|
(CELL
|
|
(CELLTYPE "cycloneive_io_obuf")
|
|
(INSTANCE LED\[0\]\~output)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT i (941:941:941) (1090:1090:1090))
|
|
(IOPATH i o (1643:1643:1643) (1588:1588:1588))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_io_obuf")
|
|
(INSTANCE LED\[1\]\~output)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT i (858:858:858) (973:973:973))
|
|
(IOPATH i o (1643:1643:1643) (1588:1588:1588))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_io_obuf")
|
|
(INSTANCE LED\[2\]\~output)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT i (957:957:957) (1082:1082:1082))
|
|
(IOPATH i o (1643:1643:1643) (1588:1588:1588))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_io_obuf")
|
|
(INSTANCE LED\[3\]\~output)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT i (611:611:611) (701:701:701))
|
|
(IOPATH i o (1643:1643:1643) (1588:1588:1588))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_io_obuf")
|
|
(INSTANCE LED\[4\]\~output)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT i (821:821:821) (940:940:940))
|
|
(IOPATH i o (1666:1666:1666) (1600:1600:1600))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_io_obuf")
|
|
(INSTANCE LED\[5\]\~output)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT i (1195:1195:1195) (1350:1350:1350))
|
|
(IOPATH i o (3106:3106:3106) (2841:2841:2841))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_io_obuf")
|
|
(INSTANCE LED\[6\]\~output)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT i (1351:1351:1351) (1507:1507:1507))
|
|
(IOPATH i o (1586:1586:1586) (1541:1541:1541))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_io_obuf")
|
|
(INSTANCE LED\[7\]\~output)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT i (550:550:550) (639:639:639))
|
|
(IOPATH i o (3106:3106:3106) (2841:2841:2841))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_io_ibuf")
|
|
(INSTANCE CLOCK_50\~input)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(IOPATH i o (153:153:153) (704:704:704))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_clkctrl")
|
|
(INSTANCE CLOCK_50\~inputclkctrl)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT inclk[0] (91:91:91) (78:78:78))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE counter\[0\]\~63)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(IOPATH datac combout (190:190:190) (195:195:195))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "dffeas")
|
|
(INSTANCE counter\[0\])
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (913:913:913) (917:917:917))
|
|
(PORT d (37:37:37) (50:50:50))
|
|
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (84:84:84))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE counter\[1\]\~21)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT dataa (136:136:136) (187:187:187))
|
|
(PORT datab (135:135:135) (186:186:186))
|
|
(IOPATH dataa combout (186:186:186) (180:180:180))
|
|
(IOPATH dataa cout (226:226:226) (171:171:171))
|
|
(IOPATH datab combout (190:190:190) (181:181:181))
|
|
(IOPATH datab cout (227:227:227) (175:175:175))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "dffeas")
|
|
(INSTANCE counter\[1\])
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (913:913:913) (917:917:917))
|
|
(PORT d (37:37:37) (50:50:50))
|
|
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (84:84:84))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE counter\[2\]\~23)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT datab (134:134:134) (184:184:184))
|
|
(IOPATH datab combout (166:166:166) (176:176:176))
|
|
(IOPATH datab cout (227:227:227) (175:175:175))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
(IOPATH cin combout (187:187:187) (204:204:204))
|
|
(IOPATH cin cout (34:34:34) (34:34:34))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "dffeas")
|
|
(INSTANCE counter\[2\])
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (913:913:913) (917:917:917))
|
|
(PORT d (37:37:37) (50:50:50))
|
|
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (84:84:84))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE counter\[3\]\~25)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT datab (133:133:133) (183:183:183))
|
|
(IOPATH datab combout (192:192:192) (177:177:177))
|
|
(IOPATH datab cout (227:227:227) (175:175:175))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
(IOPATH cin combout (187:187:187) (204:204:204))
|
|
(IOPATH cin cout (34:34:34) (34:34:34))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "dffeas")
|
|
(INSTANCE counter\[3\])
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (913:913:913) (917:917:917))
|
|
(PORT d (37:37:37) (50:50:50))
|
|
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (84:84:84))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE counter\[4\]\~27)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT datab (134:134:134) (183:183:183))
|
|
(IOPATH datab combout (166:166:166) (176:176:176))
|
|
(IOPATH datab cout (227:227:227) (175:175:175))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
(IOPATH cin combout (187:187:187) (204:204:204))
|
|
(IOPATH cin cout (34:34:34) (34:34:34))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "dffeas")
|
|
(INSTANCE counter\[4\])
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (913:913:913) (917:917:917))
|
|
(PORT d (37:37:37) (50:50:50))
|
|
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (84:84:84))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE counter\[5\]\~29)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT datab (142:142:142) (189:189:189))
|
|
(IOPATH datab combout (192:192:192) (177:177:177))
|
|
(IOPATH datab cout (227:227:227) (175:175:175))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
(IOPATH cin combout (187:187:187) (204:204:204))
|
|
(IOPATH cin cout (34:34:34) (34:34:34))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "dffeas")
|
|
(INSTANCE counter\[5\])
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (913:913:913) (917:917:917))
|
|
(PORT d (37:37:37) (50:50:50))
|
|
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (84:84:84))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE counter\[6\]\~31)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT dataa (136:136:136) (187:187:187))
|
|
(IOPATH dataa combout (165:165:165) (173:173:173))
|
|
(IOPATH dataa cout (226:226:226) (171:171:171))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
(IOPATH cin combout (187:187:187) (204:204:204))
|
|
(IOPATH cin cout (34:34:34) (34:34:34))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "dffeas")
|
|
(INSTANCE counter\[6\])
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (913:913:913) (917:917:917))
|
|
(PORT d (37:37:37) (50:50:50))
|
|
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (84:84:84))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE counter\[7\]\~33)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT datab (134:134:134) (183:183:183))
|
|
(IOPATH datab combout (192:192:192) (177:177:177))
|
|
(IOPATH datab cout (227:227:227) (175:175:175))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
(IOPATH cin combout (187:187:187) (204:204:204))
|
|
(IOPATH cin cout (34:34:34) (34:34:34))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "dffeas")
|
|
(INSTANCE counter\[7\])
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (913:913:913) (917:917:917))
|
|
(PORT d (37:37:37) (50:50:50))
|
|
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (84:84:84))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE counter\[8\]\~35)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT dataa (135:135:135) (188:188:188))
|
|
(IOPATH dataa combout (165:165:165) (173:173:173))
|
|
(IOPATH dataa cout (226:226:226) (171:171:171))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
(IOPATH cin combout (187:187:187) (204:204:204))
|
|
(IOPATH cin cout (34:34:34) (34:34:34))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "dffeas")
|
|
(INSTANCE counter\[8\])
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (913:913:913) (917:917:917))
|
|
(PORT d (37:37:37) (50:50:50))
|
|
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (84:84:84))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE counter\[9\]\~37)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT datab (133:133:133) (182:182:182))
|
|
(IOPATH datab combout (192:192:192) (177:177:177))
|
|
(IOPATH datab cout (227:227:227) (175:175:175))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
(IOPATH cin combout (187:187:187) (204:204:204))
|
|
(IOPATH cin cout (34:34:34) (34:34:34))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "dffeas")
|
|
(INSTANCE counter\[9\])
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (913:913:913) (917:917:917))
|
|
(PORT d (37:37:37) (50:50:50))
|
|
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (84:84:84))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE counter\[10\]\~39)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT dataa (133:133:133) (187:187:187))
|
|
(IOPATH dataa combout (165:165:165) (173:173:173))
|
|
(IOPATH dataa cout (226:226:226) (171:171:171))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
(IOPATH cin combout (187:187:187) (204:204:204))
|
|
(IOPATH cin cout (34:34:34) (34:34:34))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "dffeas")
|
|
(INSTANCE counter\[10\])
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (913:913:913) (917:917:917))
|
|
(PORT d (37:37:37) (50:50:50))
|
|
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (84:84:84))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE counter\[11\]\~41)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT dataa (376:376:376) (454:454:454))
|
|
(IOPATH dataa combout (186:186:186) (175:175:175))
|
|
(IOPATH dataa cout (226:226:226) (171:171:171))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
(IOPATH cin combout (187:187:187) (204:204:204))
|
|
(IOPATH cin cout (34:34:34) (34:34:34))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE counter\[11\]\~feeder)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT datad (164:164:164) (192:192:192))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "dffeas")
|
|
(INSTANCE counter\[11\])
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (913:913:913) (917:917:917))
|
|
(PORT d (37:37:37) (50:50:50))
|
|
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (84:84:84))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE counter\[12\]\~43)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT datab (133:133:133) (182:182:182))
|
|
(IOPATH datab combout (166:166:166) (176:176:176))
|
|
(IOPATH datab cout (227:227:227) (175:175:175))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
(IOPATH cin combout (187:187:187) (204:204:204))
|
|
(IOPATH cin cout (34:34:34) (34:34:34))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "dffeas")
|
|
(INSTANCE counter\[12\])
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (913:913:913) (917:917:917))
|
|
(PORT d (37:37:37) (50:50:50))
|
|
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (84:84:84))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE counter\[13\]\~45)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT datab (134:134:134) (184:184:184))
|
|
(IOPATH datab combout (192:192:192) (177:177:177))
|
|
(IOPATH datab cout (227:227:227) (175:175:175))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
(IOPATH cin combout (187:187:187) (204:204:204))
|
|
(IOPATH cin cout (34:34:34) (34:34:34))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "dffeas")
|
|
(INSTANCE counter\[13\])
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (913:913:913) (917:917:917))
|
|
(PORT d (37:37:37) (50:50:50))
|
|
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (84:84:84))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE counter\[14\]\~47)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT dataa (136:136:136) (189:189:189))
|
|
(IOPATH dataa combout (165:165:165) (173:173:173))
|
|
(IOPATH dataa cout (226:226:226) (171:171:171))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
(IOPATH cin combout (187:187:187) (204:204:204))
|
|
(IOPATH cin cout (34:34:34) (34:34:34))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "dffeas")
|
|
(INSTANCE counter\[14\])
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (913:913:913) (917:917:917))
|
|
(PORT d (37:37:37) (50:50:50))
|
|
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (84:84:84))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE counter\[15\]\~49)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT datab (135:135:135) (185:185:185))
|
|
(IOPATH datab combout (192:192:192) (177:177:177))
|
|
(IOPATH datab cout (227:227:227) (175:175:175))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
(IOPATH cin combout (187:187:187) (204:204:204))
|
|
(IOPATH cin cout (34:34:34) (34:34:34))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "dffeas")
|
|
(INSTANCE counter\[15\])
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (913:913:913) (917:917:917))
|
|
(PORT d (37:37:37) (50:50:50))
|
|
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (84:84:84))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE counter\[16\]\~51)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT dataa (135:135:135) (187:187:187))
|
|
(IOPATH dataa combout (165:165:165) (173:173:173))
|
|
(IOPATH dataa cout (226:226:226) (171:171:171))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
(IOPATH cin combout (187:187:187) (204:204:204))
|
|
(IOPATH cin cout (34:34:34) (34:34:34))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "dffeas")
|
|
(INSTANCE counter\[16\])
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (913:913:913) (917:917:917))
|
|
(PORT d (37:37:37) (50:50:50))
|
|
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (84:84:84))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE counter\[17\]\~53)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT dataa (136:136:136) (188:188:188))
|
|
(IOPATH dataa combout (186:186:186) (175:175:175))
|
|
(IOPATH dataa cout (226:226:226) (171:171:171))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
(IOPATH cin combout (187:187:187) (204:204:204))
|
|
(IOPATH cin cout (34:34:34) (34:34:34))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "dffeas")
|
|
(INSTANCE counter\[17\])
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (913:913:913) (917:917:917))
|
|
(PORT d (37:37:37) (50:50:50))
|
|
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (84:84:84))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE counter\[18\]\~55)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT datab (135:135:135) (186:186:186))
|
|
(IOPATH datab combout (166:166:166) (176:176:176))
|
|
(IOPATH datab cout (227:227:227) (175:175:175))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
(IOPATH cin combout (187:187:187) (204:204:204))
|
|
(IOPATH cin cout (34:34:34) (34:34:34))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "dffeas")
|
|
(INSTANCE counter\[18\])
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (913:913:913) (917:917:917))
|
|
(PORT d (37:37:37) (50:50:50))
|
|
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (84:84:84))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE counter\[19\]\~57)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT datab (135:135:135) (185:185:185))
|
|
(IOPATH datab combout (192:192:192) (177:177:177))
|
|
(IOPATH datab cout (227:227:227) (175:175:175))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
(IOPATH cin combout (187:187:187) (204:204:204))
|
|
(IOPATH cin cout (34:34:34) (34:34:34))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "dffeas")
|
|
(INSTANCE counter\[19\])
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (913:913:913) (917:917:917))
|
|
(PORT d (37:37:37) (50:50:50))
|
|
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (84:84:84))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE Equal0\~5)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT dataa (138:138:138) (191:191:191))
|
|
(PORT datab (136:136:136) (186:186:186))
|
|
(PORT datac (122:122:122) (165:165:165))
|
|
(PORT datad (124:124:124) (164:164:164))
|
|
(IOPATH dataa combout (158:158:158) (157:157:157))
|
|
(IOPATH datab combout (160:160:160) (156:156:156))
|
|
(IOPATH datac combout (120:120:120) (124:124:124))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE Equal0\~0)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT dataa (136:136:136) (188:188:188))
|
|
(PORT datab (135:135:135) (185:185:185))
|
|
(PORT datac (121:121:121) (164:164:164))
|
|
(PORT datad (122:122:122) (162:162:162))
|
|
(IOPATH dataa combout (158:158:158) (157:157:157))
|
|
(IOPATH datab combout (160:160:160) (156:156:156))
|
|
(IOPATH datac combout (120:120:120) (124:124:124))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE Equal0\~1)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT dataa (138:138:138) (191:191:191))
|
|
(PORT datab (137:137:137) (188:188:188))
|
|
(PORT datac (200:200:200) (245:245:245))
|
|
(PORT datad (123:123:123) (162:162:162))
|
|
(IOPATH dataa combout (158:158:158) (157:157:157))
|
|
(IOPATH datab combout (160:160:160) (156:156:156))
|
|
(IOPATH datac combout (120:120:120) (124:124:124))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE Equal0\~2)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT dataa (140:140:140) (194:194:194))
|
|
(PORT datab (141:141:141) (190:190:190))
|
|
(PORT datac (125:125:125) (170:170:170))
|
|
(PORT datad (125:125:125) (165:165:165))
|
|
(IOPATH dataa combout (158:158:158) (157:157:157))
|
|
(IOPATH datab combout (160:160:160) (156:156:156))
|
|
(IOPATH datac combout (120:120:120) (124:124:124))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE Equal0\~3)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT dataa (138:138:138) (192:192:192))
|
|
(PORT datab (137:137:137) (188:188:188))
|
|
(PORT datac (123:123:123) (166:166:166))
|
|
(PORT datad (124:124:124) (164:164:164))
|
|
(IOPATH dataa combout (158:158:158) (157:157:157))
|
|
(IOPATH datab combout (160:160:160) (156:156:156))
|
|
(IOPATH datac combout (120:120:120) (124:124:124))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE Equal0\~4)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT dataa (174:174:174) (213:213:213))
|
|
(PORT datab (177:177:177) (213:213:213))
|
|
(PORT datac (172:172:172) (204:204:204))
|
|
(PORT datad (314:314:314) (364:364:364))
|
|
(IOPATH dataa combout (159:159:159) (163:163:163))
|
|
(IOPATH datab combout (161:161:161) (167:167:167))
|
|
(IOPATH datac combout (119:119:119) (124:124:124))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE counter\[20\]\~59)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT datab (142:142:142) (190:190:190))
|
|
(IOPATH datab combout (166:166:166) (176:176:176))
|
|
(IOPATH datab cout (227:227:227) (175:175:175))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
(IOPATH cin combout (187:187:187) (204:204:204))
|
|
(IOPATH cin cout (34:34:34) (34:34:34))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "dffeas")
|
|
(INSTANCE counter\[20\])
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1110:1110:1110) (1139:1139:1139))
|
|
(PORT d (37:37:37) (50:50:50))
|
|
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (84:84:84))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE counter\[21\]\~61)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT datad (129:129:129) (166:166:166))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
(IOPATH cin combout (187:187:187) (204:204:204))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "dffeas")
|
|
(INSTANCE counter\[21\])
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1110:1110:1110) (1139:1139:1139))
|
|
(PORT d (37:37:37) (50:50:50))
|
|
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (84:84:84))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE Equal0\~7)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT datac (359:359:359) (433:433:433))
|
|
(PORT datad (350:350:350) (417:417:417))
|
|
(IOPATH datac combout (120:120:120) (124:124:124))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE address\[0\]\~39)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT dataa (340:340:340) (401:401:401))
|
|
(PORT datab (107:107:107) (137:137:137))
|
|
(PORT datad (170:170:170) (199:199:199))
|
|
(IOPATH dataa combout (158:158:158) (173:173:173))
|
|
(IOPATH datab combout (160:160:160) (176:176:176))
|
|
(IOPATH datac combout (190:190:190) (195:195:195))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "dffeas")
|
|
(INSTANCE address\[0\])
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1095:1095:1095) (1112:1112:1112))
|
|
(PORT d (37:37:37) (50:50:50))
|
|
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (84:84:84))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE address\[1\]\~13)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT dataa (146:146:146) (199:199:199))
|
|
(PORT datab (140:140:140) (189:189:189))
|
|
(IOPATH dataa combout (186:186:186) (180:180:180))
|
|
(IOPATH dataa cout (226:226:226) (171:171:171))
|
|
(IOPATH datab combout (190:190:190) (181:181:181))
|
|
(IOPATH datab cout (227:227:227) (175:175:175))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE Equal0\~6)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT dataa (378:378:378) (454:454:454))
|
|
(PORT datab (364:364:364) (436:436:436))
|
|
(PORT datac (325:325:325) (377:377:377))
|
|
(PORT datad (95:95:95) (115:115:115))
|
|
(IOPATH dataa combout (158:158:158) (157:157:157))
|
|
(IOPATH datab combout (160:160:160) (156:156:156))
|
|
(IOPATH datac combout (119:119:119) (124:124:124))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "dffeas")
|
|
(INSTANCE address\[1\])
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (912:912:912) (917:917:917))
|
|
(PORT d (37:37:37) (50:50:50))
|
|
(PORT ena (409:409:409) (429:429:429))
|
|
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (84:84:84))
|
|
(HOLD ena (posedge clk) (84:84:84))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE address\[2\]\~15)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT datab (141:141:141) (189:189:189))
|
|
(IOPATH datab combout (166:166:166) (176:176:176))
|
|
(IOPATH datab cout (227:227:227) (175:175:175))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
(IOPATH cin combout (187:187:187) (204:204:204))
|
|
(IOPATH cin cout (34:34:34) (34:34:34))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "dffeas")
|
|
(INSTANCE address\[2\])
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (912:912:912) (917:917:917))
|
|
(PORT d (37:37:37) (50:50:50))
|
|
(PORT ena (409:409:409) (429:429:429))
|
|
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (84:84:84))
|
|
(HOLD ena (posedge clk) (84:84:84))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE address\[3\]\~17)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT datab (154:154:154) (201:201:201))
|
|
(IOPATH datab combout (192:192:192) (177:177:177))
|
|
(IOPATH datab cout (227:227:227) (175:175:175))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
(IOPATH cin combout (187:187:187) (204:204:204))
|
|
(IOPATH cin cout (34:34:34) (34:34:34))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "dffeas")
|
|
(INSTANCE address\[3\])
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (912:912:912) (917:917:917))
|
|
(PORT d (37:37:37) (50:50:50))
|
|
(PORT ena (409:409:409) (429:429:429))
|
|
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (84:84:84))
|
|
(HOLD ena (posedge clk) (84:84:84))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE address\[4\]\~19)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT dataa (143:143:143) (193:193:193))
|
|
(IOPATH dataa combout (165:165:165) (173:173:173))
|
|
(IOPATH dataa cout (226:226:226) (171:171:171))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
(IOPATH cin combout (187:187:187) (204:204:204))
|
|
(IOPATH cin cout (34:34:34) (34:34:34))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "dffeas")
|
|
(INSTANCE address\[4\])
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (912:912:912) (917:917:917))
|
|
(PORT d (37:37:37) (50:50:50))
|
|
(PORT ena (409:409:409) (429:429:429))
|
|
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (84:84:84))
|
|
(HOLD ena (posedge clk) (84:84:84))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE address\[5\]\~21)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT datab (142:142:142) (190:190:190))
|
|
(IOPATH datab combout (192:192:192) (177:177:177))
|
|
(IOPATH datab cout (227:227:227) (175:175:175))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
(IOPATH cin combout (187:187:187) (204:204:204))
|
|
(IOPATH cin cout (34:34:34) (34:34:34))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "dffeas")
|
|
(INSTANCE address\[5\])
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (912:912:912) (917:917:917))
|
|
(PORT d (37:37:37) (50:50:50))
|
|
(PORT ena (409:409:409) (429:429:429))
|
|
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (84:84:84))
|
|
(HOLD ena (posedge clk) (84:84:84))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE address\[6\]\~23)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT dataa (143:143:143) (193:193:193))
|
|
(IOPATH dataa combout (165:165:165) (173:173:173))
|
|
(IOPATH dataa cout (226:226:226) (171:171:171))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
(IOPATH cin combout (187:187:187) (204:204:204))
|
|
(IOPATH cin cout (34:34:34) (34:34:34))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "dffeas")
|
|
(INSTANCE address\[6\])
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (912:912:912) (917:917:917))
|
|
(PORT d (37:37:37) (50:50:50))
|
|
(PORT ena (409:409:409) (429:429:429))
|
|
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (84:84:84))
|
|
(HOLD ena (posedge clk) (84:84:84))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE address\[7\]\~25)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT dataa (143:143:143) (193:193:193))
|
|
(IOPATH dataa combout (186:186:186) (175:175:175))
|
|
(IOPATH dataa cout (226:226:226) (171:171:171))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
(IOPATH cin combout (187:187:187) (204:204:204))
|
|
(IOPATH cin cout (34:34:34) (34:34:34))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "dffeas")
|
|
(INSTANCE address\[7\])
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (912:912:912) (917:917:917))
|
|
(PORT d (37:37:37) (50:50:50))
|
|
(PORT ena (409:409:409) (429:429:429))
|
|
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (84:84:84))
|
|
(HOLD ena (posedge clk) (84:84:84))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE address\[8\]\~27)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT datab (142:142:142) (190:190:190))
|
|
(IOPATH datab combout (166:166:166) (176:176:176))
|
|
(IOPATH datab cout (227:227:227) (175:175:175))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
(IOPATH cin combout (187:187:187) (204:204:204))
|
|
(IOPATH cin cout (34:34:34) (34:34:34))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "dffeas")
|
|
(INSTANCE address\[8\])
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (912:912:912) (917:917:917))
|
|
(PORT d (37:37:37) (50:50:50))
|
|
(PORT ena (409:409:409) (429:429:429))
|
|
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (84:84:84))
|
|
(HOLD ena (posedge clk) (84:84:84))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE address\[9\]\~29)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT datab (142:142:142) (190:190:190))
|
|
(IOPATH datab combout (192:192:192) (177:177:177))
|
|
(IOPATH datab cout (227:227:227) (175:175:175))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
(IOPATH cin combout (187:187:187) (204:204:204))
|
|
(IOPATH cin cout (34:34:34) (34:34:34))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "dffeas")
|
|
(INSTANCE address\[9\])
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (912:912:912) (917:917:917))
|
|
(PORT d (37:37:37) (50:50:50))
|
|
(PORT ena (409:409:409) (429:429:429))
|
|
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (84:84:84))
|
|
(HOLD ena (posedge clk) (84:84:84))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE address\[10\]\~31)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT datab (142:142:142) (190:190:190))
|
|
(IOPATH datab combout (166:166:166) (176:176:176))
|
|
(IOPATH datab cout (227:227:227) (175:175:175))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
(IOPATH cin combout (187:187:187) (204:204:204))
|
|
(IOPATH cin cout (34:34:34) (34:34:34))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "dffeas")
|
|
(INSTANCE address\[10\])
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (912:912:912) (917:917:917))
|
|
(PORT d (37:37:37) (50:50:50))
|
|
(PORT ena (409:409:409) (429:429:429))
|
|
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (84:84:84))
|
|
(HOLD ena (posedge clk) (84:84:84))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE address\[11\]\~33)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT datab (142:142:142) (190:190:190))
|
|
(IOPATH datab combout (192:192:192) (177:177:177))
|
|
(IOPATH datab cout (227:227:227) (175:175:175))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
(IOPATH cin combout (187:187:187) (204:204:204))
|
|
(IOPATH cin cout (34:34:34) (34:34:34))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "dffeas")
|
|
(INSTANCE address\[11\])
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (912:912:912) (917:917:917))
|
|
(PORT d (37:37:37) (50:50:50))
|
|
(PORT ena (409:409:409) (429:429:429))
|
|
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (84:84:84))
|
|
(HOLD ena (posedge clk) (84:84:84))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE address\[12\]\~35)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT dataa (143:143:143) (193:193:193))
|
|
(IOPATH dataa combout (165:165:165) (173:173:173))
|
|
(IOPATH dataa cout (226:226:226) (171:171:171))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
(IOPATH cin combout (187:187:187) (204:204:204))
|
|
(IOPATH cin cout (34:34:34) (34:34:34))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "dffeas")
|
|
(INSTANCE address\[12\])
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (912:912:912) (917:917:917))
|
|
(PORT d (37:37:37) (50:50:50))
|
|
(PORT ena (409:409:409) (429:429:429))
|
|
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (84:84:84))
|
|
(HOLD ena (posedge clk) (84:84:84))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE address\[13\]\~37)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT datad (141:141:141) (177:177:177))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
(IOPATH cin combout (187:187:187) (204:204:204))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "dffeas")
|
|
(INSTANCE address\[13\])
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (912:912:912) (917:917:917))
|
|
(PORT d (37:37:37) (50:50:50))
|
|
(PORT ena (409:409:409) (429:429:429))
|
|
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (84:84:84))
|
|
(HOLD ena (posedge clk) (84:84:84))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT datad (225:225:225) (275:275:275))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "dffeas")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|address_reg_a\[0\])
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (912:912:912) (917:917:917))
|
|
(PORT d (37:37:37) (50:50:50))
|
|
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (84:84:84))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]\~feeder)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT datad (120:120:120) (157:157:157))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "dffeas")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\])
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (912:912:912) (917:917:917))
|
|
(PORT d (37:37:37) (50:50:50))
|
|
(IOPATH (posedge clk) q (105:105:105) (105:105:105))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (84:84:84))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT d[0] (696:696:696) (809:809:809))
|
|
(PORT d[1] (727:727:727) (854:854:854))
|
|
(PORT d[2] (770:770:770) (905:905:905))
|
|
(PORT d[3] (752:752:752) (874:874:874))
|
|
(PORT d[4] (709:709:709) (827:827:827))
|
|
(PORT d[5] (774:774:774) (910:910:910))
|
|
(PORT d[6] (1002:1002:1002) (1193:1193:1193))
|
|
(PORT d[7] (749:749:749) (870:870:870))
|
|
(PORT d[8] (756:756:756) (884:884:884))
|
|
(PORT d[9] (769:769:769) (904:904:904))
|
|
(PORT d[10] (751:751:751) (876:876:876))
|
|
(PORT d[11] (880:880:880) (1014:1014:1014))
|
|
(PORT d[12] (737:737:737) (853:853:853))
|
|
(PORT clk (1095:1095:1095) (1112:1112:1112))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (104:104:104))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1095:1095:1095) (1112:1112:1112))
|
|
(PORT d[0] (659:659:659) (736:736:736))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1096:1096:1096) (1113:1113:1113))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1077:1077:1077) (1093:1093:1093))
|
|
(IOPATH (posedge clk) q (164:164:164) (167:167:167))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(SETUP d (posedge clk) (25:25:25))
|
|
(HOLD d (posedge clk) (90:90:90))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (617:617:617) (625:625:625))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (618:618:618) (626:626:626))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (618:618:618) (626:626:626))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (618:618:618) (626:626:626))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT d[0] (643:643:643) (747:747:747))
|
|
(PORT d[1] (556:556:556) (658:658:658))
|
|
(PORT d[2] (593:593:593) (701:701:701))
|
|
(PORT d[3] (758:758:758) (882:882:882))
|
|
(PORT d[4] (705:705:705) (826:826:826))
|
|
(PORT d[5] (749:749:749) (874:874:874))
|
|
(PORT d[6] (874:874:874) (1055:1055:1055))
|
|
(PORT d[7] (708:708:708) (817:817:817))
|
|
(PORT d[8] (753:753:753) (886:886:886))
|
|
(PORT d[9] (784:784:784) (927:927:927))
|
|
(PORT d[10] (741:741:741) (864:864:864))
|
|
(PORT d[11] (709:709:709) (823:823:823))
|
|
(PORT d[12] (755:755:755) (877:877:877))
|
|
(PORT clk (1095:1095:1095) (1112:1112:1112))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (104:104:104))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1095:1095:1095) (1112:1112:1112))
|
|
(PORT d[0] (582:582:582) (526:526:526))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1096:1096:1096) (1113:1113:1113))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1077:1077:1077) (1093:1093:1093))
|
|
(IOPATH (posedge clk) q (164:164:164) (167:167:167))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(SETUP d (posedge clk) (25:25:25))
|
|
(HOLD d (posedge clk) (90:90:90))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (617:617:617) (625:625:625))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (618:618:618) (626:626:626))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (618:618:618) (626:626:626))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (618:618:618) (626:626:626))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~0)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT datab (545:545:545) (645:645:645))
|
|
(PORT datac (484:484:484) (546:546:546))
|
|
(PORT datad (333:333:333) (377:377:377))
|
|
(IOPATH datab combout (188:188:188) (177:177:177))
|
|
(IOPATH datac combout (119:119:119) (124:124:124))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT d[0] (813:813:813) (941:941:941))
|
|
(PORT d[1] (863:863:863) (1008:1008:1008))
|
|
(PORT d[2] (881:881:881) (1027:1027:1027))
|
|
(PORT d[3] (699:699:699) (808:808:808))
|
|
(PORT d[4] (926:926:926) (1077:1077:1077))
|
|
(PORT d[5] (1093:1093:1093) (1290:1290:1290))
|
|
(PORT d[6] (695:695:695) (813:813:813))
|
|
(PORT d[7] (761:761:761) (903:903:903))
|
|
(PORT d[8] (1083:1083:1083) (1274:1274:1274))
|
|
(PORT d[9] (677:677:677) (796:796:796))
|
|
(PORT d[10] (799:799:799) (948:948:948))
|
|
(PORT d[11] (665:665:665) (771:771:771))
|
|
(PORT d[12] (687:687:687) (813:813:813))
|
|
(PORT clk (1089:1089:1089) (1106:1106:1106))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (104:104:104))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1089:1089:1089) (1106:1106:1106))
|
|
(PORT d[0] (695:695:695) (626:626:626))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1090:1090:1090) (1107:1107:1107))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1071:1071:1071) (1087:1087:1087))
|
|
(IOPATH (posedge clk) q (164:164:164) (167:167:167))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(SETUP d (posedge clk) (25:25:25))
|
|
(HOLD d (posedge clk) (90:90:90))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (611:611:611) (619:619:619))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (612:612:612) (620:620:620))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (612:612:612) (620:620:620))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (612:612:612) (620:620:620))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT d[0] (826:826:826) (972:972:972))
|
|
(PORT d[1] (756:756:756) (903:903:903))
|
|
(PORT d[2] (889:889:889) (1041:1041:1041))
|
|
(PORT d[3] (752:752:752) (884:884:884))
|
|
(PORT d[4] (736:736:736) (866:866:866))
|
|
(PORT d[5] (908:908:908) (1078:1078:1078))
|
|
(PORT d[6] (715:715:715) (845:845:845))
|
|
(PORT d[7] (708:708:708) (834:834:834))
|
|
(PORT d[8] (917:917:917) (1088:1088:1088))
|
|
(PORT d[9] (746:746:746) (884:884:884))
|
|
(PORT d[10] (1042:1042:1042) (1212:1212:1212))
|
|
(PORT d[11] (728:728:728) (859:859:859))
|
|
(PORT d[12] (886:886:886) (1034:1034:1034))
|
|
(PORT clk (1090:1090:1090) (1108:1108:1108))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (104:104:104))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1090:1090:1090) (1108:1108:1108))
|
|
(PORT d[0] (672:672:672) (765:765:765))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1091:1091:1091) (1109:1109:1109))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1072:1072:1072) (1089:1089:1089))
|
|
(IOPATH (posedge clk) q (164:164:164) (167:167:167))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(SETUP d (posedge clk) (25:25:25))
|
|
(HOLD d (posedge clk) (90:90:90))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (612:612:612) (621:621:621))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (613:613:613) (622:622:622))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (613:613:613) (622:622:622))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (613:613:613) (622:622:622))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~1)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT dataa (342:342:342) (399:399:399))
|
|
(PORT datac (502:502:502) (567:567:567))
|
|
(PORT datad (721:721:721) (843:843:843))
|
|
(IOPATH dataa combout (170:170:170) (163:163:163))
|
|
(IOPATH datac combout (119:119:119) (124:124:124))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT d[0] (705:705:705) (819:819:819))
|
|
(PORT d[1] (732:732:732) (860:860:860))
|
|
(PORT d[2] (910:910:910) (1062:1062:1062))
|
|
(PORT d[3] (784:784:784) (916:916:916))
|
|
(PORT d[4] (732:732:732) (858:858:858))
|
|
(PORT d[5] (737:737:737) (856:856:856))
|
|
(PORT d[6] (1011:1011:1011) (1205:1205:1205))
|
|
(PORT d[7] (765:765:765) (893:893:893))
|
|
(PORT d[8] (760:760:760) (891:891:891))
|
|
(PORT d[9] (803:803:803) (947:947:947))
|
|
(PORT d[10] (982:982:982) (1126:1126:1126))
|
|
(PORT d[11] (885:885:885) (1020:1020:1020))
|
|
(PORT d[12] (758:758:758) (879:879:879))
|
|
(PORT clk (1094:1094:1094) (1111:1111:1111))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (104:104:104))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1094:1094:1094) (1111:1111:1111))
|
|
(PORT d[0] (765:765:765) (689:689:689))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1095:1095:1095) (1112:1112:1112))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1076:1076:1076) (1092:1092:1092))
|
|
(IOPATH (posedge clk) q (164:164:164) (167:167:167))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(SETUP d (posedge clk) (25:25:25))
|
|
(HOLD d (posedge clk) (90:90:90))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (616:616:616) (624:624:624))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (617:617:617) (625:625:625))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (617:617:617) (625:625:625))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (617:617:617) (625:625:625))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT d[0] (541:541:541) (637:637:637))
|
|
(PORT d[1] (708:708:708) (828:828:828))
|
|
(PORT d[2] (601:601:601) (702:702:702))
|
|
(PORT d[3] (607:607:607) (715:715:715))
|
|
(PORT d[4] (549:549:549) (647:647:647))
|
|
(PORT d[5] (691:691:691) (797:797:797))
|
|
(PORT d[6] (860:860:860) (1033:1033:1033))
|
|
(PORT d[7] (707:707:707) (817:817:817))
|
|
(PORT d[8] (599:599:599) (713:713:713))
|
|
(PORT d[9] (625:625:625) (746:746:746))
|
|
(PORT d[10] (828:828:828) (957:957:957))
|
|
(PORT d[11] (709:709:709) (822:822:822))
|
|
(PORT d[12] (742:742:742) (856:856:856))
|
|
(PORT clk (1096:1096:1096) (1113:1113:1113))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (104:104:104))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1096:1096:1096) (1113:1113:1113))
|
|
(PORT d[0] (525:525:525) (581:581:581))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1097:1097:1097) (1114:1114:1114))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1078:1078:1078) (1094:1094:1094))
|
|
(IOPATH (posedge clk) q (164:164:164) (167:167:167))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(SETUP d (posedge clk) (25:25:25))
|
|
(HOLD d (posedge clk) (90:90:90))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (618:618:618) (626:626:626))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (619:619:619) (627:627:627))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (619:619:619) (627:627:627))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (619:619:619) (627:627:627))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~2)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT datab (551:551:551) (659:659:659))
|
|
(PORT datac (509:509:509) (578:578:578))
|
|
(PORT datad (328:328:328) (369:369:369))
|
|
(IOPATH datab combout (166:166:166) (176:176:176))
|
|
(IOPATH datac combout (119:119:119) (124:124:124))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT d[0] (513:513:513) (599:599:599))
|
|
(PORT d[1] (535:535:535) (638:638:638))
|
|
(PORT d[2] (594:594:594) (707:707:707))
|
|
(PORT d[3] (582:582:582) (682:682:682))
|
|
(PORT d[4] (527:527:527) (618:618:618))
|
|
(PORT d[5] (558:558:558) (656:656:656))
|
|
(PORT d[6] (819:819:819) (985:985:985))
|
|
(PORT d[7] (682:682:682) (790:790:790))
|
|
(PORT d[8] (911:911:911) (1067:1067:1067))
|
|
(PORT d[9] (597:597:597) (712:712:712))
|
|
(PORT d[10] (575:575:575) (678:678:678))
|
|
(PORT d[11] (710:710:710) (823:823:823))
|
|
(PORT d[12] (716:716:716) (828:828:828))
|
|
(PORT clk (1095:1095:1095) (1112:1112:1112))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (104:104:104))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1095:1095:1095) (1112:1112:1112))
|
|
(PORT d[0] (497:497:497) (548:548:548))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1096:1096:1096) (1113:1113:1113))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1077:1077:1077) (1093:1093:1093))
|
|
(IOPATH (posedge clk) q (164:164:164) (167:167:167))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(SETUP d (posedge clk) (25:25:25))
|
|
(HOLD d (posedge clk) (90:90:90))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (617:617:617) (625:625:625))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (618:618:618) (626:626:626))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (618:618:618) (626:626:626))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (618:618:618) (626:626:626))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT d[0] (648:648:648) (753:753:753))
|
|
(PORT d[1] (354:354:354) (417:417:417))
|
|
(PORT d[2] (392:392:392) (461:461:461))
|
|
(PORT d[3] (418:418:418) (491:491:491))
|
|
(PORT d[4] (359:359:359) (424:424:424))
|
|
(PORT d[5] (407:407:407) (482:482:482))
|
|
(PORT d[6] (419:419:419) (492:492:492))
|
|
(PORT d[7] (411:411:411) (485:485:485))
|
|
(PORT d[8] (414:414:414) (490:490:490))
|
|
(PORT d[9] (422:422:422) (503:503:503))
|
|
(PORT d[10] (658:658:658) (769:769:769))
|
|
(PORT d[11] (411:411:411) (482:482:482))
|
|
(PORT d[12] (416:416:416) (490:490:490))
|
|
(PORT clk (1095:1095:1095) (1112:1112:1112))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (104:104:104))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1095:1095:1095) (1112:1112:1112))
|
|
(PORT d[0] (376:376:376) (347:347:347))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1096:1096:1096) (1113:1113:1113))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1077:1077:1077) (1093:1093:1093))
|
|
(IOPATH (posedge clk) q (164:164:164) (167:167:167))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(SETUP d (posedge clk) (25:25:25))
|
|
(HOLD d (posedge clk) (90:90:90))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (617:617:617) (625:625:625))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (618:618:618) (626:626:626))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (618:618:618) (626:626:626))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (618:618:618) (626:626:626))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~3)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT dataa (504:504:504) (583:583:583))
|
|
(PORT datac (358:358:358) (424:424:424))
|
|
(PORT datad (331:331:331) (374:374:374))
|
|
(IOPATH dataa combout (170:170:170) (163:163:163))
|
|
(IOPATH datac combout (119:119:119) (125:125:125))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT d[0] (813:813:813) (944:944:944))
|
|
(PORT d[1] (852:852:852) (996:996:996))
|
|
(PORT d[2] (870:870:870) (1016:1016:1016))
|
|
(PORT d[3] (550:550:550) (646:646:646))
|
|
(PORT d[4] (543:543:543) (639:639:639))
|
|
(PORT d[5] (921:921:921) (1093:1093:1093))
|
|
(PORT d[6] (544:544:544) (650:650:650))
|
|
(PORT d[7] (519:519:519) (618:618:618))
|
|
(PORT d[8] (920:920:920) (1089:1089:1089))
|
|
(PORT d[9] (546:546:546) (652:652:652))
|
|
(PORT d[10] (536:536:536) (637:637:637))
|
|
(PORT d[11] (524:524:524) (622:622:622))
|
|
(PORT d[12] (537:537:537) (631:631:631))
|
|
(PORT clk (1089:1089:1089) (1106:1106:1106))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (104:104:104))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1089:1089:1089) (1106:1106:1106))
|
|
(PORT d[0] (540:540:540) (486:486:486))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1090:1090:1090) (1107:1107:1107))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1071:1071:1071) (1087:1087:1087))
|
|
(IOPATH (posedge clk) q (164:164:164) (167:167:167))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(SETUP d (posedge clk) (25:25:25))
|
|
(HOLD d (posedge clk) (90:90:90))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (611:611:611) (619:619:619))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (612:612:612) (620:620:620))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (612:612:612) (620:620:620))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (612:612:612) (620:620:620))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT d[0] (667:667:667) (784:784:784))
|
|
(PORT d[1] (696:696:696) (823:823:823))
|
|
(PORT d[2] (712:712:712) (840:840:840))
|
|
(PORT d[3] (708:708:708) (823:823:823))
|
|
(PORT d[4] (919:919:919) (1070:1070:1070))
|
|
(PORT d[5] (920:920:920) (1092:1092:1092))
|
|
(PORT d[6] (704:704:704) (834:834:834))
|
|
(PORT d[7] (688:688:688) (810:810:810))
|
|
(PORT d[8] (919:919:919) (1088:1088:1088))
|
|
(PORT d[9] (701:701:701) (826:826:826))
|
|
(PORT d[10] (1057:1057:1057) (1230:1230:1230))
|
|
(PORT d[11] (708:708:708) (835:835:835))
|
|
(PORT d[12] (683:683:683) (805:805:805))
|
|
(PORT clk (1089:1089:1089) (1106:1106:1106))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (104:104:104))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1089:1089:1089) (1106:1106:1106))
|
|
(PORT d[0] (637:637:637) (713:713:713))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1090:1090:1090) (1107:1107:1107))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1071:1071:1071) (1087:1087:1087))
|
|
(IOPATH (posedge clk) q (164:164:164) (167:167:167))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(SETUP d (posedge clk) (25:25:25))
|
|
(HOLD d (posedge clk) (90:90:90))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (611:611:611) (619:619:619))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (612:612:612) (620:620:620))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (612:612:612) (620:620:620))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (612:612:612) (620:620:620))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~4)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT datab (349:349:349) (398:398:398))
|
|
(PORT datac (475:475:475) (533:533:533))
|
|
(PORT datad (428:428:428) (504:504:504))
|
|
(IOPATH datab combout (168:168:168) (167:167:167))
|
|
(IOPATH datac combout (119:119:119) (124:124:124))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT d[0] (840:840:840) (987:987:987))
|
|
(PORT d[1] (1090:1090:1090) (1276:1276:1276))
|
|
(PORT d[2] (713:713:713) (840:840:840))
|
|
(PORT d[3] (739:739:739) (859:859:859))
|
|
(PORT d[4] (736:736:736) (862:862:862))
|
|
(PORT d[5] (706:706:706) (838:838:838))
|
|
(PORT d[6] (733:733:733) (868:868:868))
|
|
(PORT d[7] (716:716:716) (843:843:843))
|
|
(PORT d[8] (901:901:901) (1069:1069:1069))
|
|
(PORT d[9] (744:744:744) (880:880:880))
|
|
(PORT d[10] (1059:1059:1059) (1238:1238:1238))
|
|
(PORT d[11] (722:722:722) (847:847:847))
|
|
(PORT d[12] (859:859:859) (1000:1000:1000))
|
|
(PORT clk (1090:1090:1090) (1108:1108:1108))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (104:104:104))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1090:1090:1090) (1108:1108:1108))
|
|
(PORT d[0] (672:672:672) (759:759:759))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1091:1091:1091) (1109:1109:1109))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1072:1072:1072) (1089:1089:1089))
|
|
(IOPATH (posedge clk) q (164:164:164) (167:167:167))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(SETUP d (posedge clk) (25:25:25))
|
|
(HOLD d (posedge clk) (90:90:90))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (612:612:612) (621:621:621))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (613:613:613) (622:622:622))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (613:613:613) (622:622:622))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (613:613:613) (622:622:622))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT d[0] (867:867:867) (1022:1022:1022))
|
|
(PORT d[1] (928:928:928) (1097:1097:1097))
|
|
(PORT d[2] (889:889:889) (1039:1039:1039))
|
|
(PORT d[3] (932:932:932) (1088:1088:1088))
|
|
(PORT d[4] (904:904:904) (1065:1065:1065))
|
|
(PORT d[5] (892:892:892) (1048:1048:1048))
|
|
(PORT d[6] (883:883:883) (1038:1038:1038))
|
|
(PORT d[7] (871:871:871) (1018:1018:1018))
|
|
(PORT d[8] (871:871:871) (1029:1029:1029))
|
|
(PORT d[9] (908:908:908) (1064:1064:1064))
|
|
(PORT d[10] (863:863:863) (1012:1012:1012))
|
|
(PORT d[11] (892:892:892) (1039:1039:1039))
|
|
(PORT d[12] (860:860:860) (1009:1009:1009))
|
|
(PORT clk (1089:1089:1089) (1106:1106:1106))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (104:104:104))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1089:1089:1089) (1106:1106:1106))
|
|
(PORT d[0] (920:920:920) (819:819:819))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1090:1090:1090) (1107:1107:1107))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1071:1071:1071) (1087:1087:1087))
|
|
(IOPATH (posedge clk) q (164:164:164) (167:167:167))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(SETUP d (posedge clk) (25:25:25))
|
|
(HOLD d (posedge clk) (90:90:90))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (611:611:611) (619:619:619))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (612:612:612) (620:620:620))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (612:612:612) (620:620:620))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (612:612:612) (620:620:620))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~5)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT datab (341:341:341) (389:389:389))
|
|
(PORT datac (510:510:510) (575:575:575))
|
|
(PORT datad (626:626:626) (741:741:741))
|
|
(IOPATH datab combout (167:167:167) (167:167:167))
|
|
(IOPATH datac combout (119:119:119) (124:124:124))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT d[0] (539:539:539) (637:637:637))
|
|
(PORT d[1] (697:697:697) (818:818:818))
|
|
(PORT d[2] (599:599:599) (708:708:708))
|
|
(PORT d[3] (608:608:608) (718:718:718))
|
|
(PORT d[4] (555:555:555) (660:660:660))
|
|
(PORT d[5] (599:599:599) (709:709:709))
|
|
(PORT d[6] (841:841:841) (1010:1010:1010))
|
|
(PORT d[7] (714:714:714) (829:829:829))
|
|
(PORT d[8] (596:596:596) (706:706:706))
|
|
(PORT d[9] (600:600:600) (716:716:716))
|
|
(PORT d[10] (579:579:579) (682:682:682))
|
|
(PORT d[11] (699:699:699) (809:809:809))
|
|
(PORT d[12] (735:735:735) (849:849:849))
|
|
(PORT clk (1096:1096:1096) (1113:1113:1113))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (104:104:104))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1096:1096:1096) (1113:1113:1113))
|
|
(PORT d[0] (517:517:517) (572:572:572))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1097:1097:1097) (1114:1114:1114))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1078:1078:1078) (1094:1094:1094))
|
|
(IOPATH (posedge clk) q (164:164:164) (167:167:167))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(SETUP d (posedge clk) (25:25:25))
|
|
(HOLD d (posedge clk) (90:90:90))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (618:618:618) (626:626:626))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (619:619:619) (627:627:627))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (619:619:619) (627:627:627))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (619:619:619) (627:627:627))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT d[0] (509:509:509) (594:594:594))
|
|
(PORT d[1] (355:355:355) (418:418:418))
|
|
(PORT d[2] (733:733:733) (863:863:863))
|
|
(PORT d[3] (766:766:766) (895:895:895))
|
|
(PORT d[4] (514:514:514) (597:597:597))
|
|
(PORT d[5] (582:582:582) (683:683:683))
|
|
(PORT d[6] (805:805:805) (963:963:963))
|
|
(PORT d[7] (681:681:681) (788:788:788))
|
|
(PORT d[8] (925:925:925) (1079:1079:1079))
|
|
(PORT d[9] (580:580:580) (683:683:683))
|
|
(PORT d[10] (577:577:577) (677:677:677))
|
|
(PORT d[11] (660:660:660) (761:761:761))
|
|
(PORT d[12] (686:686:686) (789:789:789))
|
|
(PORT clk (1094:1094:1094) (1112:1112:1112))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (104:104:104))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1094:1094:1094) (1112:1112:1112))
|
|
(PORT d[0] (534:534:534) (487:487:487))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1095:1095:1095) (1113:1113:1113))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1076:1076:1076) (1093:1093:1093))
|
|
(IOPATH (posedge clk) q (164:164:164) (167:167:167))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(SETUP d (posedge clk) (25:25:25))
|
|
(HOLD d (posedge clk) (90:90:90))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (616:616:616) (625:625:625))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (617:617:617) (626:626:626))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (617:617:617) (626:626:626))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (617:617:617) (626:626:626))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~6)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT dataa (391:391:391) (455:455:455))
|
|
(PORT datac (481:481:481) (561:561:561))
|
|
(PORT datad (186:186:186) (218:218:218))
|
|
(IOPATH dataa combout (170:170:170) (163:163:163))
|
|
(IOPATH datac combout (119:119:119) (125:125:125))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT d[0] (830:830:830) (970:970:970))
|
|
(PORT d[1] (1078:1078:1078) (1262:1262:1262))
|
|
(PORT d[2] (1085:1085:1085) (1259:1259:1259))
|
|
(PORT d[3] (772:772:772) (909:909:909))
|
|
(PORT d[4] (1067:1067:1067) (1250:1250:1250))
|
|
(PORT d[5] (739:739:739) (887:887:887))
|
|
(PORT d[6] (747:747:747) (889:889:889))
|
|
(PORT d[7] (717:717:717) (844:844:844))
|
|
(PORT d[8] (733:733:733) (878:878:878))
|
|
(PORT d[9] (731:731:731) (861:861:861))
|
|
(PORT d[10] (1020:1020:1020) (1186:1186:1186))
|
|
(PORT d[11] (723:723:723) (848:848:848))
|
|
(PORT d[12] (713:713:713) (836:836:836))
|
|
(PORT clk (1090:1090:1090) (1107:1107:1107))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (104:104:104))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1090:1090:1090) (1107:1107:1107))
|
|
(PORT d[0] (776:776:776) (683:683:683))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1091:1091:1091) (1108:1108:1108))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1072:1072:1072) (1088:1088:1088))
|
|
(IOPATH (posedge clk) q (164:164:164) (167:167:167))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(SETUP d (posedge clk) (25:25:25))
|
|
(HOLD d (posedge clk) (90:90:90))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (612:612:612) (620:620:620))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (613:613:613) (621:621:621))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (613:613:613) (621:621:621))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (613:613:613) (621:621:621))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT d[0] (1017:1017:1017) (1190:1190:1190))
|
|
(PORT d[1] (910:910:910) (1072:1072:1072))
|
|
(PORT d[2] (907:907:907) (1065:1065:1065))
|
|
(PORT d[3] (918:918:918) (1070:1070:1070))
|
|
(PORT d[4] (910:910:910) (1068:1068:1068))
|
|
(PORT d[5] (891:891:891) (1047:1047:1047))
|
|
(PORT d[6] (884:884:884) (1036:1036:1036))
|
|
(PORT d[7] (880:880:880) (1029:1029:1029))
|
|
(PORT d[8] (867:867:867) (1020:1020:1020))
|
|
(PORT d[9] (913:913:913) (1070:1070:1070))
|
|
(PORT d[10] (853:853:853) (997:997:997))
|
|
(PORT d[11] (898:898:898) (1045:1045:1045))
|
|
(PORT d[12] (870:870:870) (1019:1019:1019))
|
|
(PORT clk (1088:1088:1088) (1105:1105:1105))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(HOLD d (posedge clk) (104:104:104))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1088:1088:1088) (1105:1105:1105))
|
|
(PORT d[0] (846:846:846) (959:959:959))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1089:1089:1089) (1106:1106:1106))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (1070:1070:1070) (1086:1086:1086))
|
|
(IOPATH (posedge clk) q (164:164:164) (167:167:167))
|
|
)
|
|
)
|
|
(TIMINGCHECK
|
|
(SETUP d (posedge clk) (25:25:25))
|
|
(HOLD d (posedge clk) (90:90:90))
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_register")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (610:610:610) (618:618:618))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (611:611:611) (619:619:619))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (611:611:611) (619:619:619))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_ram_pulse_generator")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT clk (611:611:611) (619:619:619))
|
|
(IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222))
|
|
)
|
|
)
|
|
)
|
|
(CELL
|
|
(CELLTYPE "cycloneive_lcell_comb")
|
|
(INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~7)
|
|
(DELAY
|
|
(ABSOLUTE
|
|
(PORT datab (346:346:346) (394:394:394))
|
|
(PORT datac (502:502:502) (567:567:567))
|
|
(PORT datad (628:628:628) (743:743:743))
|
|
(IOPATH datab combout (168:168:168) (167:167:167))
|
|
(IOPATH datac combout (119:119:119) (124:124:124))
|
|
(IOPATH datad combout (68:68:68) (63:63:63))
|
|
)
|
|
)
|
|
)
|
|
)
|