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9d6eb7a9faa86667827181dc7f534b5a360972fc
de0-zx-spectrum/simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo
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benny 9d6eb7a9fa ROM0 now has the spectrum rom
2022-03-30 13:18:06 +03:00

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// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//
// Device: Altera EP4CE22F17C6 Package FBGA256
//
//
// This file contains Slow Corner delays for the design using part EP4CE22F17C6,
// with speed grade 6, core voltage 1.2V, and temperature 0 Celsius
//
//
// This SDF file should be used for ModelSim-Altera (Verilog) only
//
(DELAYFILE
(SDFVERSION "2.1")
(DESIGN "spectrum")
(DATE "03/30/2022 13:12:28")
(VENDOR "Altera")
(PROGRAM "Quartus II 32-bit")
(VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
(DIVIDER .)
(TIMESCALE 1 ps)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE LED\[0\]\~output)
(DELAY
(ABSOLUTE
(PORT i (1517:1517:1517) (1544:1544:1544))
(IOPATH i o (2265:2265:2265) (2180:2180:2180))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE LED\[1\]\~output)
(DELAY
(ABSOLUTE
(PORT i (1454:1454:1454) (1428:1428:1428))
(IOPATH i o (2265:2265:2265) (2180:2180:2180))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE LED\[2\]\~output)
(DELAY
(ABSOLUTE
(PORT i (1610:1610:1610) (1575:1575:1575))
(IOPATH i o (2265:2265:2265) (2180:2180:2180))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE LED\[3\]\~output)
(DELAY
(ABSOLUTE
(PORT i (1039:1039:1039) (1034:1034:1034))
(IOPATH i o (2265:2265:2265) (2180:2180:2180))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE LED\[4\]\~output)
(DELAY
(ABSOLUTE
(PORT i (1347:1347:1347) (1342:1342:1342))
(IOPATH i o (2277:2277:2277) (2180:2180:2180))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE LED\[5\]\~output)
(DELAY
(ABSOLUTE
(PORT i (1969:1969:1969) (1936:1936:1936))
(IOPATH i o (3961:3961:3961) (3539:3539:3539))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE LED\[6\]\~output)
(DELAY
(ABSOLUTE
(PORT i (2280:2280:2280) (2169:2169:2169))
(IOPATH i o (2194:2194:2194) (2119:2119:2119))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_obuf")
(INSTANCE LED\[7\]\~output)
(DELAY
(ABSOLUTE
(PORT i (886:886:886) (919:919:919))
(IOPATH i o (3961:3961:3961) (3539:3539:3539))
)
)
)
(CELL
(CELLTYPE "cycloneive_io_ibuf")
(INSTANCE CLOCK_50\~input)
(DELAY
(ABSOLUTE
(IOPATH i o (459:459:459) (708:708:708))
)
)
)
(CELL
(CELLTYPE "cycloneive_clkctrl")
(INSTANCE CLOCK_50\~inputclkctrl)
(DELAY
(ABSOLUTE
(PORT inclk[0] (133:133:133) (124:124:124))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[0\]\~63)
(DELAY
(ABSOLUTE
(IOPATH datac combout (312:312:312) (325:325:325))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[0\])
(DELAY
(ABSOLUTE
(PORT clk (1353:1353:1353) (1369:1369:1369))
(PORT d (67:67:67) (78:78:78))
(IOPATH (posedge clk) q (180:180:180) (180:180:180))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (144:144:144))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[1\]\~21)
(DELAY
(ABSOLUTE
(PORT dataa (230:230:230) (309:309:309))
(PORT datab (227:227:227) (300:300:300))
(IOPATH dataa combout (300:300:300) (323:323:323))
(IOPATH dataa cout (376:376:376) (275:275:275))
(IOPATH datab combout (306:306:306) (324:324:324))
(IOPATH datab cout (385:385:385) (280:280:280))
(IOPATH datad combout (119:119:119) (106:106:106))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[1\])
(DELAY
(ABSOLUTE
(PORT clk (1353:1353:1353) (1369:1369:1369))
(PORT d (67:67:67) (78:78:78))
(IOPATH (posedge clk) q (180:180:180) (180:180:180))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (144:144:144))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[2\]\~23)
(DELAY
(ABSOLUTE
(PORT datab (228:228:228) (300:300:300))
(IOPATH datab combout (325:325:325) (332:332:332))
(IOPATH datab cout (385:385:385) (280:280:280))
(IOPATH datad combout (119:119:119) (106:106:106))
(IOPATH cin combout (408:408:408) (387:387:387))
(IOPATH cin cout (50:50:50) (50:50:50))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[2\])
(DELAY
(ABSOLUTE
(PORT clk (1353:1353:1353) (1369:1369:1369))
(PORT d (67:67:67) (78:78:78))
(IOPATH (posedge clk) q (180:180:180) (180:180:180))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (144:144:144))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[3\]\~25)
(DELAY
(ABSOLUTE
(PORT datab (228:228:228) (300:300:300))
(IOPATH datab combout (319:319:319) (324:324:324))
(IOPATH datab cout (385:385:385) (280:280:280))
(IOPATH datad combout (119:119:119) (106:106:106))
(IOPATH cin combout (408:408:408) (387:387:387))
(IOPATH cin cout (50:50:50) (50:50:50))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[3\])
(DELAY
(ABSOLUTE
(PORT clk (1353:1353:1353) (1369:1369:1369))
(PORT d (67:67:67) (78:78:78))
(IOPATH (posedge clk) q (180:180:180) (180:180:180))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (144:144:144))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[4\]\~27)
(DELAY
(ABSOLUTE
(PORT datab (228:228:228) (299:299:299))
(IOPATH datab combout (325:325:325) (332:332:332))
(IOPATH datab cout (385:385:385) (280:280:280))
(IOPATH datad combout (119:119:119) (106:106:106))
(IOPATH cin combout (408:408:408) (387:387:387))
(IOPATH cin cout (50:50:50) (50:50:50))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[4\])
(DELAY
(ABSOLUTE
(PORT clk (1353:1353:1353) (1369:1369:1369))
(PORT d (67:67:67) (78:78:78))
(IOPATH (posedge clk) q (180:180:180) (180:180:180))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (144:144:144))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[5\]\~29)
(DELAY
(ABSOLUTE
(PORT datab (240:240:240) (309:309:309))
(IOPATH datab combout (319:319:319) (324:324:324))
(IOPATH datab cout (385:385:385) (280:280:280))
(IOPATH datad combout (119:119:119) (106:106:106))
(IOPATH cin combout (408:408:408) (387:387:387))
(IOPATH cin cout (50:50:50) (50:50:50))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[5\])
(DELAY
(ABSOLUTE
(PORT clk (1353:1353:1353) (1369:1369:1369))
(PORT d (67:67:67) (78:78:78))
(IOPATH (posedge clk) q (180:180:180) (180:180:180))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (144:144:144))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[6\]\~31)
(DELAY
(ABSOLUTE
(PORT dataa (229:229:229) (306:306:306))
(IOPATH dataa combout (318:318:318) (327:327:327))
(IOPATH dataa cout (376:376:376) (275:275:275))
(IOPATH datad combout (119:119:119) (106:106:106))
(IOPATH cin combout (408:408:408) (387:387:387))
(IOPATH cin cout (50:50:50) (50:50:50))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[6\])
(DELAY
(ABSOLUTE
(PORT clk (1353:1353:1353) (1369:1369:1369))
(PORT d (67:67:67) (78:78:78))
(IOPATH (posedge clk) q (180:180:180) (180:180:180))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (144:144:144))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[7\]\~33)
(DELAY
(ABSOLUTE
(PORT datab (226:226:226) (299:299:299))
(IOPATH datab combout (319:319:319) (324:324:324))
(IOPATH datab cout (385:385:385) (280:280:280))
(IOPATH datad combout (119:119:119) (106:106:106))
(IOPATH cin combout (408:408:408) (387:387:387))
(IOPATH cin cout (50:50:50) (50:50:50))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[7\])
(DELAY
(ABSOLUTE
(PORT clk (1353:1353:1353) (1369:1369:1369))
(PORT d (67:67:67) (78:78:78))
(IOPATH (posedge clk) q (180:180:180) (180:180:180))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (144:144:144))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[8\]\~35)
(DELAY
(ABSOLUTE
(PORT dataa (229:229:229) (305:305:305))
(IOPATH dataa combout (318:318:318) (327:327:327))
(IOPATH dataa cout (376:376:376) (275:275:275))
(IOPATH datad combout (119:119:119) (106:106:106))
(IOPATH cin combout (408:408:408) (387:387:387))
(IOPATH cin cout (50:50:50) (50:50:50))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[8\])
(DELAY
(ABSOLUTE
(PORT clk (1353:1353:1353) (1369:1369:1369))
(PORT d (67:67:67) (78:78:78))
(IOPATH (posedge clk) q (180:180:180) (180:180:180))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (144:144:144))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[9\]\~37)
(DELAY
(ABSOLUTE
(PORT datab (227:227:227) (297:297:297))
(IOPATH datab combout (319:319:319) (324:324:324))
(IOPATH datab cout (385:385:385) (280:280:280))
(IOPATH datad combout (119:119:119) (106:106:106))
(IOPATH cin combout (408:408:408) (387:387:387))
(IOPATH cin cout (50:50:50) (50:50:50))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[9\])
(DELAY
(ABSOLUTE
(PORT clk (1353:1353:1353) (1369:1369:1369))
(PORT d (67:67:67) (78:78:78))
(IOPATH (posedge clk) q (180:180:180) (180:180:180))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (144:144:144))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[10\]\~39)
(DELAY
(ABSOLUTE
(PORT dataa (228:228:228) (302:302:302))
(IOPATH dataa combout (318:318:318) (327:327:327))
(IOPATH dataa cout (376:376:376) (275:275:275))
(IOPATH datad combout (119:119:119) (106:106:106))
(IOPATH cin combout (408:408:408) (387:387:387))
(IOPATH cin cout (50:50:50) (50:50:50))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[10\])
(DELAY
(ABSOLUTE
(PORT clk (1353:1353:1353) (1369:1369:1369))
(PORT d (67:67:67) (78:78:78))
(IOPATH (posedge clk) q (180:180:180) (180:180:180))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (144:144:144))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[11\]\~41)
(DELAY
(ABSOLUTE
(PORT dataa (658:658:658) (680:680:680))
(IOPATH dataa combout (318:318:318) (323:323:323))
(IOPATH dataa cout (376:376:376) (275:275:275))
(IOPATH datad combout (119:119:119) (106:106:106))
(IOPATH cin combout (408:408:408) (387:387:387))
(IOPATH cin cout (50:50:50) (50:50:50))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[11\]\~feeder)
(DELAY
(ABSOLUTE
(PORT datad (294:294:294) (300:300:300))
(IOPATH datad combout (119:119:119) (106:106:106))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[11\])
(DELAY
(ABSOLUTE
(PORT clk (1353:1353:1353) (1369:1369:1369))
(PORT d (67:67:67) (78:78:78))
(IOPATH (posedge clk) q (180:180:180) (180:180:180))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (144:144:144))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[12\]\~43)
(DELAY
(ABSOLUTE
(PORT datab (226:226:226) (297:297:297))
(IOPATH datab combout (325:325:325) (332:332:332))
(IOPATH datab cout (385:385:385) (280:280:280))
(IOPATH datad combout (119:119:119) (106:106:106))
(IOPATH cin combout (408:408:408) (387:387:387))
(IOPATH cin cout (50:50:50) (50:50:50))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[12\])
(DELAY
(ABSOLUTE
(PORT clk (1353:1353:1353) (1369:1369:1369))
(PORT d (67:67:67) (78:78:78))
(IOPATH (posedge clk) q (180:180:180) (180:180:180))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (144:144:144))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[13\]\~45)
(DELAY
(ABSOLUTE
(PORT datab (226:226:226) (299:299:299))
(IOPATH datab combout (319:319:319) (324:324:324))
(IOPATH datab cout (385:385:385) (280:280:280))
(IOPATH datad combout (119:119:119) (106:106:106))
(IOPATH cin combout (408:408:408) (387:387:387))
(IOPATH cin cout (50:50:50) (50:50:50))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[13\])
(DELAY
(ABSOLUTE
(PORT clk (1353:1353:1353) (1369:1369:1369))
(PORT d (67:67:67) (78:78:78))
(IOPATH (posedge clk) q (180:180:180) (180:180:180))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (144:144:144))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[14\]\~47)
(DELAY
(ABSOLUTE
(PORT dataa (229:229:229) (306:306:306))
(IOPATH dataa combout (318:318:318) (327:327:327))
(IOPATH dataa cout (376:376:376) (275:275:275))
(IOPATH datad combout (119:119:119) (106:106:106))
(IOPATH cin combout (408:408:408) (387:387:387))
(IOPATH cin cout (50:50:50) (50:50:50))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[14\])
(DELAY
(ABSOLUTE
(PORT clk (1353:1353:1353) (1369:1369:1369))
(PORT d (67:67:67) (78:78:78))
(IOPATH (posedge clk) q (180:180:180) (180:180:180))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (144:144:144))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[15\]\~49)
(DELAY
(ABSOLUTE
(PORT datab (228:228:228) (299:299:299))
(IOPATH datab combout (319:319:319) (324:324:324))
(IOPATH datab cout (385:385:385) (280:280:280))
(IOPATH datad combout (119:119:119) (106:106:106))
(IOPATH cin combout (408:408:408) (387:387:387))
(IOPATH cin cout (50:50:50) (50:50:50))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[15\])
(DELAY
(ABSOLUTE
(PORT clk (1353:1353:1353) (1369:1369:1369))
(PORT d (67:67:67) (78:78:78))
(IOPATH (posedge clk) q (180:180:180) (180:180:180))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (144:144:144))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[16\]\~51)
(DELAY
(ABSOLUTE
(PORT dataa (230:230:230) (306:306:306))
(IOPATH dataa combout (318:318:318) (327:327:327))
(IOPATH dataa cout (376:376:376) (275:275:275))
(IOPATH datad combout (119:119:119) (106:106:106))
(IOPATH cin combout (408:408:408) (387:387:387))
(IOPATH cin cout (50:50:50) (50:50:50))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[16\])
(DELAY
(ABSOLUTE
(PORT clk (1353:1353:1353) (1369:1369:1369))
(PORT d (67:67:67) (78:78:78))
(IOPATH (posedge clk) q (180:180:180) (180:180:180))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (144:144:144))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[17\]\~53)
(DELAY
(ABSOLUTE
(PORT dataa (231:231:231) (309:309:309))
(IOPATH dataa combout (318:318:318) (323:323:323))
(IOPATH dataa cout (376:376:376) (275:275:275))
(IOPATH datad combout (119:119:119) (106:106:106))
(IOPATH cin combout (408:408:408) (387:387:387))
(IOPATH cin cout (50:50:50) (50:50:50))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[17\])
(DELAY
(ABSOLUTE
(PORT clk (1353:1353:1353) (1369:1369:1369))
(PORT d (67:67:67) (78:78:78))
(IOPATH (posedge clk) q (180:180:180) (180:180:180))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (144:144:144))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[18\]\~55)
(DELAY
(ABSOLUTE
(PORT datab (229:229:229) (301:301:301))
(IOPATH datab combout (325:325:325) (332:332:332))
(IOPATH datab cout (385:385:385) (280:280:280))
(IOPATH datad combout (119:119:119) (106:106:106))
(IOPATH cin combout (408:408:408) (387:387:387))
(IOPATH cin cout (50:50:50) (50:50:50))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[18\])
(DELAY
(ABSOLUTE
(PORT clk (1353:1353:1353) (1369:1369:1369))
(PORT d (67:67:67) (78:78:78))
(IOPATH (posedge clk) q (180:180:180) (180:180:180))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (144:144:144))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[19\]\~57)
(DELAY
(ABSOLUTE
(PORT datab (229:229:229) (302:302:302))
(IOPATH datab combout (319:319:319) (324:324:324))
(IOPATH datab cout (385:385:385) (280:280:280))
(IOPATH datad combout (119:119:119) (106:106:106))
(IOPATH cin combout (408:408:408) (387:387:387))
(IOPATH cin cout (50:50:50) (50:50:50))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[19\])
(DELAY
(ABSOLUTE
(PORT clk (1353:1353:1353) (1369:1369:1369))
(PORT d (67:67:67) (78:78:78))
(IOPATH (posedge clk) q (180:180:180) (180:180:180))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (144:144:144))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE Equal0\~5)
(DELAY
(ABSOLUTE
(PORT dataa (232:232:232) (310:310:310))
(PORT datab (228:228:228) (300:300:300))
(PORT datac (202:202:202) (274:274:274))
(PORT datad (207:207:207) (269:269:269))
(IOPATH dataa combout (309:309:309) (326:326:326))
(IOPATH datab combout (309:309:309) (328:328:328))
(IOPATH datac combout (218:218:218) (215:215:215))
(IOPATH datad combout (119:119:119) (106:106:106))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE Equal0\~0)
(DELAY
(ABSOLUTE
(PORT dataa (230:230:230) (306:306:306))
(PORT datab (227:227:227) (300:300:300))
(PORT datac (201:201:201) (271:271:271))
(PORT datad (204:204:204) (265:265:265))
(IOPATH dataa combout (309:309:309) (326:326:326))
(IOPATH datab combout (309:309:309) (328:328:328))
(IOPATH datac combout (218:218:218) (215:215:215))
(IOPATH datad combout (119:119:119) (106:106:106))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE Equal0\~1)
(DELAY
(ABSOLUTE
(PORT dataa (230:230:230) (307:307:307))
(PORT datab (228:228:228) (301:301:301))
(PORT datac (354:354:354) (389:389:389))
(PORT datad (204:204:204) (265:265:265))
(IOPATH dataa combout (309:309:309) (326:326:326))
(IOPATH datab combout (309:309:309) (328:328:328))
(IOPATH datac combout (218:218:218) (215:215:215))
(IOPATH datad combout (119:119:119) (106:106:106))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE Equal0\~2)
(DELAY
(ABSOLUTE
(PORT dataa (233:233:233) (311:311:311))
(PORT datab (239:239:239) (308:308:308))
(PORT datac (205:205:205) (277:277:277))
(PORT datad (206:206:206) (268:268:268))
(IOPATH dataa combout (309:309:309) (326:326:326))
(IOPATH datab combout (309:309:309) (328:328:328))
(IOPATH datac combout (218:218:218) (215:215:215))
(IOPATH datad combout (119:119:119) (106:106:106))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE Equal0\~3)
(DELAY
(ABSOLUTE
(PORT dataa (232:232:232) (310:310:310))
(PORT datab (229:229:229) (303:303:303))
(PORT datac (202:202:202) (274:274:274))
(PORT datad (206:206:206) (268:268:268))
(IOPATH dataa combout (309:309:309) (326:326:326))
(IOPATH datab combout (309:309:309) (328:328:328))
(IOPATH datac combout (218:218:218) (215:215:215))
(IOPATH datad combout (119:119:119) (106:106:106))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE Equal0\~4)
(DELAY
(ABSOLUTE
(PORT dataa (314:314:314) (333:333:333))
(PORT datab (325:325:325) (332:332:332))
(PORT datac (313:313:313) (319:319:319))
(PORT datad (544:544:544) (539:539:539))
(IOPATH dataa combout (265:265:265) (269:269:269))
(IOPATH datab combout (265:265:265) (275:275:275))
(IOPATH datac combout (218:218:218) (216:216:216))
(IOPATH datad combout (119:119:119) (106:106:106))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[20\]\~59)
(DELAY
(ABSOLUTE
(PORT datab (241:241:241) (311:311:311))
(IOPATH datab combout (325:325:325) (332:332:332))
(IOPATH datab cout (385:385:385) (280:280:280))
(IOPATH datad combout (119:119:119) (106:106:106))
(IOPATH cin combout (408:408:408) (387:387:387))
(IOPATH cin cout (50:50:50) (50:50:50))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[20\])
(DELAY
(ABSOLUTE
(PORT clk (1681:1681:1681) (1700:1700:1700))
(PORT d (67:67:67) (78:78:78))
(IOPATH (posedge clk) q (180:180:180) (180:180:180))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (144:144:144))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE counter\[21\]\~61)
(DELAY
(ABSOLUTE
(PORT datad (218:218:218) (276:276:276))
(IOPATH datad combout (119:119:119) (106:106:106))
(IOPATH cin combout (408:408:408) (387:387:387))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE counter\[21\])
(DELAY
(ABSOLUTE
(PORT clk (1681:1681:1681) (1700:1700:1700))
(PORT d (67:67:67) (78:78:78))
(IOPATH (posedge clk) q (180:180:180) (180:180:180))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (144:144:144))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE Equal0\~7)
(DELAY
(ABSOLUTE
(PORT datac (624:624:624) (648:648:648))
(PORT datad (603:603:603) (623:623:623))
(IOPATH datac combout (218:218:218) (215:215:215))
(IOPATH datad combout (119:119:119) (106:106:106))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE address\[0\]\~39)
(DELAY
(ABSOLUTE
(PORT dataa (592:592:592) (593:593:593))
(PORT datab (189:189:189) (224:224:224))
(PORT datad (306:306:306) (313:313:313))
(IOPATH dataa combout (287:287:287) (289:289:289))
(IOPATH datab combout (295:295:295) (294:294:294))
(IOPATH datac combout (312:312:312) (325:325:325))
(IOPATH datad combout (119:119:119) (106:106:106))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE address\[0\])
(DELAY
(ABSOLUTE
(PORT clk (1652:1652:1652) (1662:1662:1662))
(PORT d (67:67:67) (78:78:78))
(IOPATH (posedge clk) q (180:180:180) (180:180:180))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (144:144:144))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE address\[1\]\~13)
(DELAY
(ABSOLUTE
(PORT dataa (244:244:244) (318:318:318))
(PORT datab (237:237:237) (306:306:306))
(IOPATH dataa combout (300:300:300) (323:323:323))
(IOPATH dataa cout (376:376:376) (275:275:275))
(IOPATH datab combout (306:306:306) (324:324:324))
(IOPATH datab cout (385:385:385) (280:280:280))
(IOPATH datad combout (119:119:119) (106:106:106))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE Equal0\~6)
(DELAY
(ABSOLUTE
(PORT dataa (656:656:656) (681:681:681))
(PORT datab (627:627:627) (652:652:652))
(PORT datac (564:564:564) (562:562:562))
(PORT datad (164:164:164) (189:189:189))
(IOPATH dataa combout (267:267:267) (269:269:269))
(IOPATH datab combout (267:267:267) (275:275:275))
(IOPATH datac combout (218:218:218) (216:216:216))
(IOPATH datad combout (119:119:119) (106:106:106))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE address\[1\])
(DELAY
(ABSOLUTE
(PORT clk (1352:1352:1352) (1369:1369:1369))
(PORT d (67:67:67) (78:78:78))
(PORT ena (721:721:721) (723:723:723))
(IOPATH (posedge clk) q (180:180:180) (180:180:180))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (144:144:144))
(HOLD ena (posedge clk) (144:144:144))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE address\[2\]\~15)
(DELAY
(ABSOLUTE
(PORT datab (238:238:238) (307:307:307))
(IOPATH datab combout (325:325:325) (332:332:332))
(IOPATH datab cout (385:385:385) (280:280:280))
(IOPATH datad combout (119:119:119) (106:106:106))
(IOPATH cin combout (408:408:408) (387:387:387))
(IOPATH cin cout (50:50:50) (50:50:50))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE address\[2\])
(DELAY
(ABSOLUTE
(PORT clk (1352:1352:1352) (1369:1369:1369))
(PORT d (67:67:67) (78:78:78))
(PORT ena (721:721:721) (723:723:723))
(IOPATH (posedge clk) q (180:180:180) (180:180:180))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (144:144:144))
(HOLD ena (posedge clk) (144:144:144))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE address\[3\]\~17)
(DELAY
(ABSOLUTE
(PORT datab (257:257:257) (326:326:326))
(IOPATH datab combout (319:319:319) (324:324:324))
(IOPATH datab cout (385:385:385) (280:280:280))
(IOPATH datad combout (119:119:119) (106:106:106))
(IOPATH cin combout (408:408:408) (387:387:387))
(IOPATH cin cout (50:50:50) (50:50:50))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE address\[3\])
(DELAY
(ABSOLUTE
(PORT clk (1352:1352:1352) (1369:1369:1369))
(PORT d (67:67:67) (78:78:78))
(PORT ena (721:721:721) (723:723:723))
(IOPATH (posedge clk) q (180:180:180) (180:180:180))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (144:144:144))
(HOLD ena (posedge clk) (144:144:144))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE address\[4\]\~19)
(DELAY
(ABSOLUTE
(PORT dataa (241:241:241) (313:313:313))
(IOPATH dataa combout (318:318:318) (327:327:327))
(IOPATH dataa cout (376:376:376) (275:275:275))
(IOPATH datad combout (119:119:119) (106:106:106))
(IOPATH cin combout (408:408:408) (387:387:387))
(IOPATH cin cout (50:50:50) (50:50:50))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE address\[4\])
(DELAY
(ABSOLUTE
(PORT clk (1352:1352:1352) (1369:1369:1369))
(PORT d (67:67:67) (78:78:78))
(PORT ena (721:721:721) (723:723:723))
(IOPATH (posedge clk) q (180:180:180) (180:180:180))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (144:144:144))
(HOLD ena (posedge clk) (144:144:144))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE address\[5\]\~21)
(DELAY
(ABSOLUTE
(PORT datab (240:240:240) (308:308:308))
(IOPATH datab combout (319:319:319) (324:324:324))
(IOPATH datab cout (385:385:385) (280:280:280))
(IOPATH datad combout (119:119:119) (106:106:106))
(IOPATH cin combout (408:408:408) (387:387:387))
(IOPATH cin cout (50:50:50) (50:50:50))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE address\[5\])
(DELAY
(ABSOLUTE
(PORT clk (1352:1352:1352) (1369:1369:1369))
(PORT d (67:67:67) (78:78:78))
(PORT ena (721:721:721) (723:723:723))
(IOPATH (posedge clk) q (180:180:180) (180:180:180))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (144:144:144))
(HOLD ena (posedge clk) (144:144:144))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE address\[6\]\~23)
(DELAY
(ABSOLUTE
(PORT dataa (242:242:242) (315:315:315))
(IOPATH dataa combout (318:318:318) (327:327:327))
(IOPATH dataa cout (376:376:376) (275:275:275))
(IOPATH datad combout (119:119:119) (106:106:106))
(IOPATH cin combout (408:408:408) (387:387:387))
(IOPATH cin cout (50:50:50) (50:50:50))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE address\[6\])
(DELAY
(ABSOLUTE
(PORT clk (1352:1352:1352) (1369:1369:1369))
(PORT d (67:67:67) (78:78:78))
(PORT ena (721:721:721) (723:723:723))
(IOPATH (posedge clk) q (180:180:180) (180:180:180))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (144:144:144))
(HOLD ena (posedge clk) (144:144:144))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE address\[7\]\~25)
(DELAY
(ABSOLUTE
(PORT dataa (242:242:242) (315:315:315))
(IOPATH dataa combout (318:318:318) (323:323:323))
(IOPATH dataa cout (376:376:376) (275:275:275))
(IOPATH datad combout (119:119:119) (106:106:106))
(IOPATH cin combout (408:408:408) (387:387:387))
(IOPATH cin cout (50:50:50) (50:50:50))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE address\[7\])
(DELAY
(ABSOLUTE
(PORT clk (1352:1352:1352) (1369:1369:1369))
(PORT d (67:67:67) (78:78:78))
(PORT ena (721:721:721) (723:723:723))
(IOPATH (posedge clk) q (180:180:180) (180:180:180))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (144:144:144))
(HOLD ena (posedge clk) (144:144:144))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE address\[8\]\~27)
(DELAY
(ABSOLUTE
(PORT datab (241:241:241) (310:310:310))
(IOPATH datab combout (325:325:325) (332:332:332))
(IOPATH datab cout (385:385:385) (280:280:280))
(IOPATH datad combout (119:119:119) (106:106:106))
(IOPATH cin combout (408:408:408) (387:387:387))
(IOPATH cin cout (50:50:50) (50:50:50))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE address\[8\])
(DELAY
(ABSOLUTE
(PORT clk (1352:1352:1352) (1369:1369:1369))
(PORT d (67:67:67) (78:78:78))
(PORT ena (721:721:721) (723:723:723))
(IOPATH (posedge clk) q (180:180:180) (180:180:180))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (144:144:144))
(HOLD ena (posedge clk) (144:144:144))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE address\[9\]\~29)
(DELAY
(ABSOLUTE
(PORT datab (241:241:241) (310:310:310))
(IOPATH datab combout (319:319:319) (324:324:324))
(IOPATH datab cout (385:385:385) (280:280:280))
(IOPATH datad combout (119:119:119) (106:106:106))
(IOPATH cin combout (408:408:408) (387:387:387))
(IOPATH cin cout (50:50:50) (50:50:50))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE address\[9\])
(DELAY
(ABSOLUTE
(PORT clk (1352:1352:1352) (1369:1369:1369))
(PORT d (67:67:67) (78:78:78))
(PORT ena (721:721:721) (723:723:723))
(IOPATH (posedge clk) q (180:180:180) (180:180:180))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (144:144:144))
(HOLD ena (posedge clk) (144:144:144))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE address\[10\]\~31)
(DELAY
(ABSOLUTE
(PORT datab (241:241:241) (310:310:310))
(IOPATH datab combout (325:325:325) (332:332:332))
(IOPATH datab cout (385:385:385) (280:280:280))
(IOPATH datad combout (119:119:119) (106:106:106))
(IOPATH cin combout (408:408:408) (387:387:387))
(IOPATH cin cout (50:50:50) (50:50:50))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE address\[10\])
(DELAY
(ABSOLUTE
(PORT clk (1352:1352:1352) (1369:1369:1369))
(PORT d (67:67:67) (78:78:78))
(PORT ena (721:721:721) (723:723:723))
(IOPATH (posedge clk) q (180:180:180) (180:180:180))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (144:144:144))
(HOLD ena (posedge clk) (144:144:144))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE address\[11\]\~33)
(DELAY
(ABSOLUTE
(PORT datab (241:241:241) (311:311:311))
(IOPATH datab combout (319:319:319) (324:324:324))
(IOPATH datab cout (385:385:385) (280:280:280))
(IOPATH datad combout (119:119:119) (106:106:106))
(IOPATH cin combout (408:408:408) (387:387:387))
(IOPATH cin cout (50:50:50) (50:50:50))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE address\[11\])
(DELAY
(ABSOLUTE
(PORT clk (1352:1352:1352) (1369:1369:1369))
(PORT d (67:67:67) (78:78:78))
(PORT ena (721:721:721) (723:723:723))
(IOPATH (posedge clk) q (180:180:180) (180:180:180))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (144:144:144))
(HOLD ena (posedge clk) (144:144:144))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE address\[12\]\~35)
(DELAY
(ABSOLUTE
(PORT dataa (242:242:242) (314:314:314))
(IOPATH dataa combout (318:318:318) (327:327:327))
(IOPATH dataa cout (376:376:376) (275:275:275))
(IOPATH datad combout (119:119:119) (106:106:106))
(IOPATH cin combout (408:408:408) (387:387:387))
(IOPATH cin cout (50:50:50) (50:50:50))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE address\[12\])
(DELAY
(ABSOLUTE
(PORT clk (1352:1352:1352) (1369:1369:1369))
(PORT d (67:67:67) (78:78:78))
(PORT ena (721:721:721) (723:723:723))
(IOPATH (posedge clk) q (180:180:180) (180:180:180))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (144:144:144))
(HOLD ena (posedge clk) (144:144:144))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE address\[13\]\~37)
(DELAY
(ABSOLUTE
(PORT datad (235:235:235) (292:292:292))
(IOPATH datad combout (119:119:119) (106:106:106))
(IOPATH cin combout (408:408:408) (387:387:387))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE address\[13\])
(DELAY
(ABSOLUTE
(PORT clk (1352:1352:1352) (1369:1369:1369))
(PORT d (67:67:67) (78:78:78))
(PORT ena (721:721:721) (723:723:723))
(IOPATH (posedge clk) q (180:180:180) (180:180:180))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (144:144:144))
(HOLD ena (posedge clk) (144:144:144))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE rom\|altsyncram_component\|auto_generated\|address_reg_a\[0\]\~feeder)
(DELAY
(ABSOLUTE
(PORT datad (395:395:395) (436:436:436))
(IOPATH datad combout (119:119:119) (106:106:106))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE rom\|altsyncram_component\|auto_generated\|address_reg_a\[0\])
(DELAY
(ABSOLUTE
(PORT clk (1352:1352:1352) (1368:1368:1368))
(PORT d (67:67:67) (78:78:78))
(IOPATH (posedge clk) q (180:180:180) (180:180:180))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (144:144:144))
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE rom\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\]\~feeder)
(DELAY
(ABSOLUTE
(PORT datad (201:201:201) (259:259:259))
(IOPATH datad combout (119:119:119) (106:106:106))
)
)
)
(CELL
(CELLTYPE "dffeas")
(INSTANCE rom\|altsyncram_component\|auto_generated\|out_address_reg_a\[0\])
(DELAY
(ABSOLUTE
(PORT clk (1352:1352:1352) (1368:1368:1368))
(PORT d (67:67:67) (78:78:78))
(IOPATH (posedge clk) q (180:180:180) (180:180:180))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (144:144:144))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1137:1137:1137) (1173:1173:1173))
(PORT d[1] (1176:1176:1176) (1232:1232:1232))
(PORT d[2] (1242:1242:1242) (1303:1303:1303))
(PORT d[3] (1221:1221:1221) (1276:1276:1276))
(PORT d[4] (1152:1152:1152) (1201:1201:1201))
(PORT d[5] (1260:1260:1260) (1308:1308:1308))
(PORT d[6] (1591:1591:1591) (1705:1705:1705))
(PORT d[7] (1212:1212:1212) (1268:1268:1268))
(PORT d[8] (1218:1218:1218) (1274:1274:1274))
(PORT d[9] (1254:1254:1254) (1299:1299:1299))
(PORT d[10] (1220:1220:1220) (1267:1267:1267))
(PORT d[11] (1449:1449:1449) (1466:1466:1466))
(PORT d[12] (1195:1195:1195) (1234:1234:1234))
(PORT clk (1642:1642:1642) (1670:1670:1670))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (169:169:169))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1642:1642:1642) (1670:1670:1670))
(PORT d[0] (1070:1070:1070) (1057:1057:1057))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1643:1643:1643) (1671:1671:1671))
(IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1609:1609:1609) (1636:1636:1636))
(IOPATH (posedge clk) q (268:268:268) (268:268:268))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (42:42:42))
(HOLD d (posedge clk) (142:142:142))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (880:880:880) (883:883:883))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (881:881:881) (884:884:884))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (881:881:881) (884:884:884))
(IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a8.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (881:881:881) (884:884:884))
(IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1066:1066:1066) (1108:1108:1108))
(PORT d[1] (903:903:903) (960:960:960))
(PORT d[2] (960:960:960) (1018:1018:1018))
(PORT d[3] (1239:1239:1239) (1281:1281:1281))
(PORT d[4] (1152:1152:1152) (1192:1192:1192))
(PORT d[5] (1224:1224:1224) (1264:1264:1264))
(PORT d[6] (1390:1390:1390) (1523:1523:1523))
(PORT d[7] (1170:1170:1170) (1209:1209:1209))
(PORT d[8] (1226:1226:1226) (1271:1271:1271))
(PORT d[9] (1281:1281:1281) (1333:1333:1333))
(PORT d[10] (1209:1209:1209) (1251:1251:1251))
(PORT d[11] (1182:1182:1182) (1215:1215:1215))
(PORT d[12] (1240:1240:1240) (1281:1281:1281))
(PORT clk (1643:1643:1643) (1671:1671:1671))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (169:169:169))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1643:1643:1643) (1671:1671:1671))
(PORT d[0] (859:859:859) (849:849:849))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1644:1644:1644) (1672:1672:1672))
(IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1610:1610:1610) (1637:1637:1637))
(IOPATH (posedge clk) q (268:268:268) (268:268:268))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (42:42:42))
(HOLD d (posedge clk) (142:142:142))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (881:881:881) (884:884:884))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (882:882:882) (885:885:885))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (882:882:882) (885:885:885))
(IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (882:882:882) (885:885:885))
(IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[0\]\~0)
(DELAY
(ABSOLUTE
(PORT datab (885:885:885) (944:944:944))
(PORT datac (813:813:813) (791:791:791))
(PORT datad (568:568:568) (546:546:546))
(IOPATH datab combout (308:308:308) (300:300:300))
(IOPATH datac combout (220:220:220) (216:216:216))
(IOPATH datad combout (119:119:119) (106:106:106))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1358:1358:1358) (1390:1390:1390))
(PORT d[1] (1429:1429:1429) (1457:1457:1457))
(PORT d[2] (1457:1457:1457) (1497:1497:1497))
(PORT d[3] (1164:1164:1164) (1188:1188:1188))
(PORT d[4] (1495:1495:1495) (1557:1557:1557))
(PORT d[5] (1763:1763:1763) (1849:1849:1849))
(PORT d[6] (1169:1169:1169) (1188:1188:1188))
(PORT d[7] (1246:1246:1246) (1305:1305:1305))
(PORT d[8] (1752:1752:1752) (1825:1825:1825))
(PORT d[9] (1142:1142:1142) (1172:1172:1172))
(PORT d[10] (1313:1313:1313) (1369:1369:1369))
(PORT d[11] (1131:1131:1131) (1139:1139:1139))
(PORT d[12] (1168:1168:1168) (1195:1195:1195))
(PORT clk (1635:1635:1635) (1662:1662:1662))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (169:169:169))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1635:1635:1635) (1662:1662:1662))
(PORT d[0] (1021:1021:1021) (1044:1044:1044))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1636:1636:1636) (1663:1663:1663))
(IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1602:1602:1602) (1628:1628:1628))
(IOPATH (posedge clk) q (268:268:268) (268:268:268))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (42:42:42))
(HOLD d (posedge clk) (142:142:142))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (873:873:873) (875:875:875))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (874:874:874) (876:876:876))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (874:874:874) (876:876:876))
(IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a1.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (874:874:874) (876:876:876))
(IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1395:1395:1395) (1437:1437:1437))
(PORT d[1] (1255:1255:1255) (1322:1322:1322))
(PORT d[2] (1479:1479:1479) (1521:1521:1521))
(PORT d[3] (1244:1244:1244) (1292:1292:1292))
(PORT d[4] (1222:1222:1222) (1273:1273:1273))
(PORT d[5] (1476:1476:1476) (1561:1561:1561))
(PORT d[6] (1179:1179:1179) (1243:1243:1243))
(PORT d[7] (1164:1164:1164) (1224:1224:1224))
(PORT d[8] (1495:1495:1495) (1577:1577:1577))
(PORT d[9] (1230:1230:1230) (1283:1283:1283))
(PORT d[10] (1677:1677:1677) (1744:1744:1744))
(PORT d[11] (1203:1203:1203) (1262:1262:1262))
(PORT d[12] (1455:1455:1455) (1512:1512:1512))
(PORT clk (1635:1635:1635) (1664:1664:1664))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (169:169:169))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1635:1635:1635) (1664:1664:1664))
(PORT d[0] (1111:1111:1111) (1127:1127:1127))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1636:1636:1636) (1665:1665:1665))
(IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1602:1602:1602) (1630:1630:1630))
(IOPATH (posedge clk) q (268:268:268) (268:268:268))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (42:42:42))
(HOLD d (posedge clk) (142:142:142))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (873:873:873) (877:877:877))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (874:874:874) (878:878:878))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (874:874:874) (878:878:878))
(IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a9.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (874:874:874) (878:878:878))
(IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[1\]\~1)
(DELAY
(ABSOLUTE
(PORT dataa (587:587:587) (581:581:581))
(PORT datac (815:815:815) (815:815:815))
(PORT datad (1247:1247:1247) (1247:1247:1247))
(IOPATH dataa combout (318:318:318) (323:323:323))
(IOPATH datac combout (218:218:218) (216:216:216))
(IOPATH datad combout (119:119:119) (106:106:106))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1143:1143:1143) (1193:1193:1193))
(PORT d[1] (1186:1186:1186) (1252:1252:1252))
(PORT d[2] (1471:1471:1471) (1533:1533:1533))
(PORT d[3] (1278:1278:1278) (1335:1335:1335))
(PORT d[4] (1183:1183:1183) (1244:1244:1244))
(PORT d[5] (1185:1185:1185) (1237:1237:1237))
(PORT d[6] (1596:1596:1596) (1726:1726:1726))
(PORT d[7] (1243:1243:1243) (1300:1300:1300))
(PORT d[8] (1232:1232:1232) (1284:1284:1284))
(PORT d[9] (1304:1304:1304) (1372:1372:1372))
(PORT d[10] (1636:1636:1636) (1650:1650:1650))
(PORT d[11] (1457:1457:1457) (1491:1491:1491))
(PORT d[12] (1228:1228:1228) (1274:1274:1274))
(PORT clk (1641:1641:1641) (1668:1668:1668))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (169:169:169))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1641:1641:1641) (1668:1668:1668))
(PORT d[0] (1114:1114:1114) (1098:1098:1098))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1642:1642:1642) (1669:1669:1669))
(IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1608:1608:1608) (1634:1634:1634))
(IOPATH (posedge clk) q (268:268:268) (268:268:268))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (42:42:42))
(HOLD d (posedge clk) (142:142:142))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (879:879:879) (881:881:881))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (880:880:880) (882:882:882))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (880:880:880) (882:882:882))
(IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a2.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (880:880:880) (882:882:882))
(IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (890:890:890) (939:939:939))
(PORT d[1] (1164:1164:1164) (1202:1202:1202))
(PORT d[2] (971:971:971) (1014:1014:1014))
(PORT d[3] (996:996:996) (1048:1048:1048))
(PORT d[4] (894:894:894) (953:953:953))
(PORT d[5] (1145:1145:1145) (1182:1182:1182))
(PORT d[6] (1364:1364:1364) (1494:1494:1494))
(PORT d[7] (1170:1170:1170) (1208:1208:1208))
(PORT d[8] (975:975:975) (1038:1038:1038))
(PORT d[9] (1019:1019:1019) (1085:1085:1085))
(PORT d[10] (1404:1404:1404) (1421:1421:1421))
(PORT d[11] (1181:1181:1181) (1214:1214:1214))
(PORT d[12] (1214:1214:1214) (1252:1252:1252))
(PORT clk (1643:1643:1643) (1672:1672:1672))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (169:169:169))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1643:1643:1643) (1672:1672:1672))
(PORT d[0] (848:848:848) (858:858:858))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1644:1644:1644) (1673:1673:1673))
(IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1610:1610:1610) (1638:1638:1638))
(IOPATH (posedge clk) q (268:268:268) (268:268:268))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (42:42:42))
(HOLD d (posedge clk) (142:142:142))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (881:881:881) (885:885:885))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (882:882:882) (886:886:886))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (882:882:882) (886:886:886))
(IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a10.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (882:882:882) (886:886:886))
(IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[2\]\~2)
(DELAY
(ABSOLUTE
(PORT datab (905:905:905) (961:961:961))
(PORT datac (835:835:835) (824:824:824))
(PORT datad (554:554:554) (539:539:539))
(IOPATH datab combout (325:325:325) (332:332:332))
(IOPATH datac combout (220:220:220) (216:216:216))
(IOPATH datad combout (119:119:119) (106:106:106))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (864:864:864) (888:888:888))
(PORT d[1] (904:904:904) (943:943:943))
(PORT d[2] (999:999:999) (1044:1044:1044))
(PORT d[3] (981:981:981) (1012:1012:1012))
(PORT d[4] (883:883:883) (924:924:924))
(PORT d[5] (931:931:931) (967:967:967))
(PORT d[6] (1325:1325:1325) (1435:1435:1435))
(PORT d[7] (1147:1147:1147) (1173:1173:1173))
(PORT d[8] (1501:1501:1501) (1549:1549:1549))
(PORT d[9] (1001:1001:1001) (1049:1049:1049))
(PORT d[10] (963:963:963) (1003:1003:1003))
(PORT d[11] (1202:1202:1202) (1209:1209:1209))
(PORT d[12] (1200:1200:1200) (1222:1222:1222))
(PORT clk (1643:1643:1643) (1670:1670:1670))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (169:169:169))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1643:1643:1643) (1670:1670:1670))
(PORT d[0] (832:832:832) (824:824:824))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1644:1644:1644) (1671:1671:1671))
(IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1610:1610:1610) (1636:1636:1636))
(IOPATH (posedge clk) q (268:268:268) (268:268:268))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (42:42:42))
(HOLD d (posedge clk) (142:142:142))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (881:881:881) (883:883:883))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (882:882:882) (884:884:884))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (882:882:882) (884:884:884))
(IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a11.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (882:882:882) (884:884:884))
(IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1113:1113:1113) (1125:1125:1125))
(PORT d[1] (606:606:606) (637:637:637))
(PORT d[2] (665:665:665) (695:695:695))
(PORT d[3] (709:709:709) (741:741:741))
(PORT d[4] (612:612:612) (647:647:647))
(PORT d[5] (683:683:683) (724:724:724))
(PORT d[6] (708:708:708) (738:738:738))
(PORT d[7] (688:688:688) (727:727:727))
(PORT d[8] (700:700:700) (736:736:736))
(PORT d[9] (712:712:712) (753:753:753))
(PORT d[10] (1139:1139:1139) (1140:1140:1140))
(PORT d[11] (689:689:689) (724:724:724))
(PORT d[12] (698:698:698) (736:736:736))
(PORT clk (1643:1643:1643) (1670:1670:1670))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (169:169:169))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1643:1643:1643) (1670:1670:1670))
(PORT d[0] (568:568:568) (578:578:578))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1644:1644:1644) (1671:1671:1671))
(IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1610:1610:1610) (1636:1636:1636))
(IOPATH (posedge clk) q (268:268:268) (268:268:268))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (42:42:42))
(HOLD d (posedge clk) (142:142:142))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (881:881:881) (883:883:883))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (882:882:882) (884:884:884))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (882:882:882) (884:884:884))
(IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a3.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (882:882:882) (884:884:884))
(IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[3\]\~3)
(DELAY
(ABSOLUTE
(PORT dataa (852:852:852) (853:853:853))
(PORT datac (604:604:604) (635:635:635))
(PORT datad (566:566:566) (544:544:544))
(IOPATH dataa combout (307:307:307) (306:306:306))
(IOPATH datac combout (220:220:220) (215:215:215))
(IOPATH datad combout (119:119:119) (106:106:106))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1371:1371:1371) (1392:1392:1392))
(PORT d[1] (1421:1421:1421) (1436:1436:1436))
(PORT d[2] (1449:1449:1449) (1476:1476:1476))
(PORT d[3] (924:924:924) (961:961:961))
(PORT d[4] (913:913:913) (957:957:957))
(PORT d[5] (1485:1485:1485) (1575:1575:1575))
(PORT d[6] (929:929:929) (974:974:974))
(PORT d[7] (882:882:882) (925:925:925))
(PORT d[8] (1483:1483:1483) (1569:1569:1569))
(PORT d[9] (928:928:928) (958:958:958))
(PORT d[10] (913:913:913) (949:949:949))
(PORT d[11] (894:894:894) (932:932:932))
(PORT d[12] (911:911:911) (944:944:944))
(PORT clk (1635:1635:1635) (1663:1663:1663))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (169:169:169))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1635:1635:1635) (1663:1663:1663))
(PORT d[0] (793:793:793) (817:817:817))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1636:1636:1636) (1664:1664:1664))
(IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1602:1602:1602) (1629:1629:1629))
(IOPATH (posedge clk) q (268:268:268) (268:268:268))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (42:42:42))
(HOLD d (posedge clk) (142:142:142))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (873:873:873) (876:876:876))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (874:874:874) (877:877:877))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (874:874:874) (877:877:877))
(IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a4.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (874:874:874) (877:877:877))
(IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1140:1140:1140) (1174:1174:1174))
(PORT d[1] (1169:1169:1169) (1198:1198:1198))
(PORT d[2] (1194:1194:1194) (1234:1234:1234))
(PORT d[3] (1189:1189:1189) (1216:1216:1216))
(PORT d[4] (1491:1491:1491) (1548:1548:1548))
(PORT d[5] (1484:1484:1484) (1574:1574:1574))
(PORT d[6] (1190:1190:1190) (1239:1239:1239))
(PORT d[7] (1154:1154:1154) (1198:1198:1198))
(PORT d[8] (1482:1482:1482) (1568:1568:1568))
(PORT d[9] (1174:1174:1174) (1206:1206:1206))
(PORT d[10] (1702:1702:1702) (1770:1770:1770))
(PORT d[11] (1193:1193:1193) (1235:1235:1235))
(PORT d[12] (1156:1156:1156) (1189:1189:1189))
(PORT clk (1635:1635:1635) (1663:1663:1663))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (169:169:169))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1635:1635:1635) (1663:1663:1663))
(PORT d[0] (1064:1064:1064) (1056:1056:1056))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1636:1636:1636) (1664:1664:1664))
(IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1602:1602:1602) (1629:1629:1629))
(IOPATH (posedge clk) q (268:268:268) (268:268:268))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (42:42:42))
(HOLD d (posedge clk) (142:142:142))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (873:873:873) (876:876:876))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (874:874:874) (877:877:877))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (874:874:874) (877:877:877))
(IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a12.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (874:874:874) (877:877:877))
(IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[4\]\~4)
(DELAY
(ABSOLUTE
(PORT datab (597:597:597) (583:583:583))
(PORT datac (797:797:797) (769:769:769))
(PORT datad (747:747:747) (756:756:756))
(IOPATH datab combout (319:319:319) (324:324:324))
(IOPATH datac combout (218:218:218) (216:216:216))
(IOPATH datad combout (119:119:119) (106:106:106))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1404:1404:1404) (1451:1451:1451))
(PORT d[1] (1754:1754:1754) (1846:1846:1846))
(PORT d[2] (1170:1170:1170) (1226:1226:1226))
(PORT d[3] (1230:1230:1230) (1270:1270:1270))
(PORT d[4] (1206:1206:1206) (1267:1267:1267))
(PORT d[5] (1157:1157:1157) (1221:1221:1221))
(PORT d[6] (1207:1207:1207) (1273:1273:1273))
(PORT d[7] (1170:1170:1170) (1232:1232:1232))
(PORT d[8] (1488:1488:1488) (1556:1556:1556))
(PORT d[9] (1215:1215:1215) (1269:1269:1269))
(PORT d[10] (1722:1722:1722) (1787:1787:1787))
(PORT d[11] (1184:1184:1184) (1241:1241:1241))
(PORT d[12] (1422:1422:1422) (1464:1464:1464))
(PORT clk (1635:1635:1635) (1664:1664:1664))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (169:169:169))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1635:1635:1635) (1664:1664:1664))
(PORT d[0] (1100:1100:1100) (1091:1091:1091))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1636:1636:1636) (1665:1665:1665))
(IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1602:1602:1602) (1630:1630:1630))
(IOPATH (posedge clk) q (268:268:268) (268:268:268))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (42:42:42))
(HOLD d (posedge clk) (142:142:142))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (873:873:873) (877:877:877))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (874:874:874) (878:878:878))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (874:874:874) (878:878:878))
(IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a13.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (874:874:874) (878:878:878))
(IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1448:1448:1448) (1498:1498:1498))
(PORT d[1] (1506:1506:1506) (1592:1592:1592))
(PORT d[2] (1452:1452:1452) (1509:1509:1509))
(PORT d[3] (1528:1528:1528) (1576:1576:1576))
(PORT d[4] (1475:1475:1475) (1541:1541:1541))
(PORT d[5] (1462:1462:1462) (1522:1522:1522))
(PORT d[6] (1454:1454:1454) (1503:1503:1503))
(PORT d[7] (1420:1420:1420) (1469:1469:1469))
(PORT d[8] (1442:1442:1442) (1487:1487:1487))
(PORT d[9] (1473:1473:1473) (1520:1520:1520))
(PORT d[10] (1421:1421:1421) (1470:1470:1470))
(PORT d[11] (1448:1448:1448) (1508:1508:1508))
(PORT d[12] (1420:1420:1420) (1464:1464:1464))
(PORT clk (1634:1634:1634) (1663:1663:1663))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (169:169:169))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1634:1634:1634) (1663:1663:1663))
(PORT d[0] (1331:1331:1331) (1332:1332:1332))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1635:1635:1635) (1664:1664:1664))
(IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1601:1601:1601) (1629:1629:1629))
(IOPATH (posedge clk) q (268:268:268) (268:268:268))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (42:42:42))
(HOLD d (posedge clk) (142:142:142))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (872:872:872) (876:876:876))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (873:873:873) (877:877:877))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (873:873:873) (877:877:877))
(IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a5.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (873:873:873) (877:877:877))
(IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[5\]\~5)
(DELAY
(ABSOLUTE
(PORT datab (584:584:584) (569:569:569))
(PORT datac (839:839:839) (835:835:835))
(PORT datad (1050:1050:1050) (1093:1093:1093))
(IOPATH datab combout (275:275:275) (275:275:275))
(IOPATH datac combout (220:220:220) (215:215:215))
(IOPATH datad combout (119:119:119) (106:106:106))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (891:891:891) (939:939:939))
(PORT d[1] (1151:1151:1151) (1192:1192:1192))
(PORT d[2] (982:982:982) (1034:1034:1034))
(PORT d[3] (1008:1008:1008) (1057:1057:1057))
(PORT d[4] (914:914:914) (974:974:974))
(PORT d[5] (988:988:988) (1039:1039:1039))
(PORT d[6] (1336:1336:1336) (1464:1464:1464))
(PORT d[7] (1184:1184:1184) (1228:1228:1228))
(PORT d[8] (977:977:977) (1032:1032:1032))
(PORT d[9] (982:982:982) (1046:1046:1046))
(PORT d[10] (949:949:949) (1003:1003:1003))
(PORT d[11] (1165:1165:1165) (1197:1197:1197))
(PORT d[12] (1210:1210:1210) (1246:1246:1246))
(PORT clk (1643:1643:1643) (1672:1672:1672))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (169:169:169))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1643:1643:1643) (1672:1672:1672))
(PORT d[0] (842:842:842) (851:851:851))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1644:1644:1644) (1673:1673:1673))
(IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1610:1610:1610) (1638:1638:1638))
(IOPATH (posedge clk) q (268:268:268) (268:268:268))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (42:42:42))
(HOLD d (posedge clk) (142:142:142))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (881:881:881) (885:885:885))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (882:882:882) (886:886:886))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (882:882:882) (886:886:886))
(IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a14.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (882:882:882) (886:886:886))
(IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (853:853:853) (884:884:884))
(PORT d[1] (606:606:606) (638:638:638))
(PORT d[2] (1214:1214:1214) (1272:1272:1272))
(PORT d[3] (1231:1231:1231) (1305:1305:1305))
(PORT d[4] (860:860:860) (887:887:887))
(PORT d[5] (973:973:973) (1005:1005:1005))
(PORT d[6] (1300:1300:1300) (1396:1396:1396))
(PORT d[7] (1150:1150:1150) (1164:1164:1164))
(PORT d[8] (1515:1515:1515) (1564:1564:1564))
(PORT d[9] (972:972:972) (1000:1000:1000))
(PORT d[10] (968:968:968) (992:992:992))
(PORT d[11] (1116:1116:1116) (1120:1120:1120))
(PORT d[12] (1163:1163:1163) (1171:1171:1171))
(PORT clk (1643:1643:1643) (1670:1670:1670))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (169:169:169))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1643:1643:1643) (1670:1670:1670))
(PORT d[0] (798:798:798) (816:816:816))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1644:1644:1644) (1671:1671:1671))
(IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1610:1610:1610) (1636:1636:1636))
(IOPATH (posedge clk) q (268:268:268) (268:268:268))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (42:42:42))
(HOLD d (posedge clk) (142:142:142))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (881:881:881) (883:883:883))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (882:882:882) (884:884:884))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (882:882:882) (884:884:884))
(IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a6.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (882:882:882) (884:884:884))
(IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[6\]\~6)
(DELAY
(ABSOLUTE
(PORT dataa (649:649:649) (659:659:659))
(PORT datac (837:837:837) (850:850:850))
(PORT datad (328:328:328) (320:320:320))
(IOPATH dataa combout (307:307:307) (306:306:306))
(IOPATH datac combout (220:220:220) (215:215:215))
(IOPATH datad combout (119:119:119) (106:106:106))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1373:1373:1373) (1418:1418:1418))
(PORT d[1] (1747:1747:1747) (1825:1825:1825))
(PORT d[2] (1746:1746:1746) (1807:1807:1807))
(PORT d[3] (1277:1277:1277) (1330:1330:1330))
(PORT d[4] (1743:1743:1743) (1797:1797:1797))
(PORT d[5] (1224:1224:1224) (1295:1295:1295))
(PORT d[6] (1233:1233:1233) (1302:1302:1302))
(PORT d[7] (1171:1171:1171) (1233:1233:1233))
(PORT d[8] (1217:1217:1217) (1283:1283:1283))
(PORT d[9] (1191:1191:1191) (1242:1242:1242))
(PORT d[10] (1667:1667:1667) (1716:1716:1716))
(PORT d[11] (1184:1184:1184) (1242:1242:1242))
(PORT d[12] (1175:1175:1175) (1226:1226:1226))
(PORT clk (1635:1635:1635) (1664:1664:1664))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (169:169:169))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1635:1635:1635) (1664:1664:1664))
(PORT d[0] (1135:1135:1135) (1114:1114:1114))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1636:1636:1636) (1665:1665:1665))
(IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1602:1602:1602) (1630:1630:1630))
(IOPATH (posedge clk) q (268:268:268) (268:268:268))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (42:42:42))
(HOLD d (posedge clk) (142:142:142))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (873:873:873) (877:877:877))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (874:874:874) (878:878:878))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (874:874:874) (878:878:878))
(IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a7.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (874:874:874) (878:878:878))
(IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1688:1688:1688) (1727:1727:1727))
(PORT d[1] (1489:1489:1489) (1529:1529:1529))
(PORT d[2] (1466:1466:1466) (1541:1541:1541))
(PORT d[3] (1503:1503:1503) (1555:1555:1555))
(PORT d[4] (1477:1477:1477) (1556:1556:1556))
(PORT d[5] (1450:1450:1450) (1516:1516:1516))
(PORT d[6] (1438:1438:1438) (1502:1502:1502))
(PORT d[7] (1428:1428:1428) (1489:1489:1489))
(PORT d[8] (1421:1421:1421) (1476:1476:1476))
(PORT d[9] (1475:1475:1475) (1533:1533:1533))
(PORT d[10] (1392:1392:1392) (1448:1448:1448))
(PORT d[11] (1450:1450:1450) (1514:1514:1514))
(PORT d[12] (1424:1424:1424) (1479:1479:1479))
(PORT clk (1633:1633:1633) (1660:1660:1660))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (169:169:169))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1633:1633:1633) (1660:1660:1660))
(PORT d[0] (1376:1376:1376) (1394:1394:1394))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1634:1634:1634) (1661:1661:1661))
(IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1600:1600:1600) (1626:1626:1626))
(IOPATH (posedge clk) q (268:268:268) (268:268:268))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (42:42:42))
(HOLD d (posedge clk) (142:142:142))
)
)
(CELL
(CELLTYPE "cycloneive_ram_register")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (871:871:871) (873:873:873))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (872:872:872) (874:874:874))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (872:872:872) (874:874:874))
(IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
)
)
)
(CELL
(CELLTYPE "cycloneive_ram_pulse_generator")
(INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a15.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (872:872:872) (874:874:874))
(IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386))
)
)
)
(CELL
(CELLTYPE "cycloneive_lcell_comb")
(INSTANCE rom\|altsyncram_component\|auto_generated\|mux2\|result_node\[7\]\~7)
(DELAY
(ABSOLUTE
(PORT datab (593:593:593) (577:577:577))
(PORT datac (833:833:833) (822:822:822))
(PORT datad (1052:1052:1052) (1094:1094:1094))
(IOPATH datab combout (319:319:319) (324:324:324))
(IOPATH datac combout (218:218:218) (216:216:216))
(IOPATH datad combout (119:119:119) (106:106:106))
)
)
)
)
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