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Initial import. Counter to leds

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This commit is contained in:
Adrian Scripca
2022-03-30 11:53:01 +03:00
commit fa29e9f3f6
107 changed files with 30393 additions and 0 deletions
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db/.cmp.kpt
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db/logic_util_heursitic.dat
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db/prev_cmp_spectrum.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648630297528 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648630297529 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 11:51:37 2022 " "Processing started: Wed Mar 30 11:51:37 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648630297529 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1648630297529 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1648630297529 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1648630298448 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1648630298474 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "389 " "Peak virtual memory: 389 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648630298719 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 11:51:38 2022 " "Processing ended: Wed Mar 30 11:51:38 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648630298719 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648630298719 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648630298719 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1648630298719 ""}
db/spectrum.asm.rdb
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<?xml version="1.0" ?>
<LOG_ROOT>
<PROJECT NAME="spectrum">
</PROJECT>
</LOG_ROOT>
db/spectrum.cmp.bpm
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db/spectrum.cmp.logdb
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v1
IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength or Termination assignments found.,,I/O,,
IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042,
IO_RULES_MATRIX,Total Pass,9;0;9;0;0;9;9;0;9;9;0;0;0;0;1;0;0;1;0;0;0;0;0;0;0;0;0;9;0;0,
IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
IO_RULES_MATRIX,Total Inapplicable,0;9;0;9;9;0;0;9;0;0;9;9;9;9;8;9;9;8;9;9;9;9;9;9;9;9;9;0;9;9,
IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
IO_RULES_MATRIX,LED[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,LED[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,LED[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,LED[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,LED[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,LED[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,LED[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,LED[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,CLOCK_50,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_SUMMARY,Total I/O Rules,30,
IO_RULES_SUMMARY,Number of I/O Rules Passed,9,
IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,21,
db/spectrum.cmp.rdb
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Quartus_Version = Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
Version_Index = 318808576
Creation_Time = Wed Mar 30 11:48:45 2022
db/spectrum.eda.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648630303095 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648630303096 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 11:51:42 2022 " "Processing started: Wed Mar 30 11:51:42 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648630303096 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648630303096 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648630303097 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630303387 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630303407 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_fast.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_fast.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630303428 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630303448 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630303469 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630303488 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_v_fast.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630303508 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_v.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_v.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630303527 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "352 " "Peak virtual memory: 352 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648630303559 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 11:51:43 2022 " "Processing ended: Wed Mar 30 11:51:43 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648630303559 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648630303559 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648630303559 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648630303559 ""}
db/spectrum.fit.qmsg
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db/spectrum.hier_info
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|spectrum
CLOCK_50 => LED[0]~reg0.CLK
CLOCK_50 => LED[1]~reg0.CLK
CLOCK_50 => LED[2]~reg0.CLK
CLOCK_50 => LED[3]~reg0.CLK
CLOCK_50 => LED[4]~reg0.CLK
CLOCK_50 => LED[5]~reg0.CLK
CLOCK_50 => LED[6]~reg0.CLK
CLOCK_50 => LED[7]~reg0.CLK
CLOCK_50 => counter[0].CLK
CLOCK_50 => counter[1].CLK
CLOCK_50 => counter[2].CLK
CLOCK_50 => counter[3].CLK
CLOCK_50 => counter[4].CLK
CLOCK_50 => counter[5].CLK
CLOCK_50 => counter[6].CLK
CLOCK_50 => counter[7].CLK
CLOCK_50 => counter[8].CLK
CLOCK_50 => counter[9].CLK
CLOCK_50 => counter[10].CLK
CLOCK_50 => counter[11].CLK
CLOCK_50 => counter[12].CLK
CLOCK_50 => counter[13].CLK
CLOCK_50 => counter[14].CLK
CLOCK_50 => counter[15].CLK
CLOCK_50 => counter[16].CLK
CLOCK_50 => counter[17].CLK
CLOCK_50 => counter[18].CLK
CLOCK_50 => counter[19].CLK
CLOCK_50 => counter[20].CLK
CLOCK_50 => counter[21].CLK
CLOCK_50 => counter[22].CLK
CLOCK_50 => counter[23].CLK
CLOCK_50 => counter[24].CLK
CLOCK_50 => counter[25].CLK
CLOCK_50 => counter[26].CLK
CLOCK_50 => counter[27].CLK
LED[0] <= LED[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
LED[1] <= LED[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
LED[2] <= LED[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
LED[3] <= LED[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
LED[4] <= LED[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
LED[5] <= LED[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
LED[6] <= LED[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
LED[7] <= LED[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
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<TABLE>
<TR bgcolor="#C0C0C0">
<TH>Hierarchy</TH>
<TH>Input</TH>
<TH>Constant Input</TH>
<TH>Unused Input</TH>
<TH>Floating Input</TH>
<TH>Output</TH>
<TH>Constant Output</TH>
<TH>Unused Output</TH>
<TH>Floating Output</TH>
<TH>Bidir</TH>
<TH>Constant Bidir</TH>
<TH>Unused Bidir</TH>
<TH>Input only Bidir</TH>
<TH>Output only Bidir</TH>
</TR>
</TABLE>
db/spectrum.lpc.rdb
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+--------------------------------------------------------------------------------+
; Legal Partition Candidates ;
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648630288558 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648630288559 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 11:51:28 2022 " "Processing started: Wed Mar 30 11:51:28 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648630288559 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648630288559 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum " "Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648630288559 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648630288726 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spectrum.v 1 1 " "Found 1 design units, including 1 entities, in source file spectrum.v" { { "Info" "ISGN_ENTITY_NAME" "1 spectrum " "Found entity 1: spectrum" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648630288788 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648630288788 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "spectrum " "Elaborating entity \"spectrum\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1648630288838 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 28 spectrum.v(10) " "Verilog HDL assignment warning at spectrum.v(10): truncated value with size 32 to match size of target (28)" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 10 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1648630288840 "|spectrum"}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[7\] GND " "Pin \"LED\[7\]\" is stuck at GND" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 8 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648630289171 "|spectrum|LED[7]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1648630289171 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1648630289264 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1648630289457 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648630289457 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "44 " "Implemented 44 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Implemented 1 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1648630289496 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1648630289496 ""} { "Info" "ICUT_CUT_TM_LCELLS" "35 " "Implemented 35 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1648630289496 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1648630289496 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "388 " "Peak virtual memory: 388 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648630289503 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 11:51:29 2022 " "Processing ended: Wed Mar 30 11:51:29 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648630289503 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648630289503 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648630289503 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648630289503 ""}
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DONE
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648630300061 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300062 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 11:51:39 2022 " "Processing started: Wed Mar 30 11:51:39 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648630300062 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648630300062 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta spectrum -c spectrum " "Command: quartus_sta spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648630300062 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1648630300090 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648630300188 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648630300189 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648630300231 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648630300231 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "spectrum.sdc " "Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1648630300423 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1648630300423 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300424 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300424 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1648630300550 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300550 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1648630300551 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1648630300556 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648630300564 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648630300564 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.606 " "Worst-case setup slack is -1.606" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300565 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300565 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.606 -30.234 CLOCK_50 " " -1.606 -30.234 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300565 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630300565 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.360 " "Worst-case hold slack is 0.360" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300566 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300566 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.360 0.000 CLOCK_50 " " 0.360 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300566 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630300566 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648630300566 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648630300567 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300567 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300567 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -38.000 CLOCK_50 " " -3.000 -38.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300567 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630300567 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648630300582 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1648630300605 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1648630300970 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300986 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648630300988 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648630300988 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.275 " "Worst-case setup slack is -1.275" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300989 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300989 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.275 -22.690 CLOCK_50 " " -1.275 -22.690 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300989 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630300989 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.319 " "Worst-case hold slack is 0.319" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300990 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300990 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.319 0.000 CLOCK_50 " " 0.319 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300990 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630300990 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648630300991 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648630300992 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300993 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300993 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -38.000 CLOCK_50 " " -3.000 -38.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300993 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630300993 ""}
{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648630301008 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648630301128 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648630301129 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648630301129 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.500 " "Worst-case setup slack is -0.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630301130 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630301130 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.500 -4.764 CLOCK_50 " " -0.500 -4.764 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630301130 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630301130 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.193 " "Worst-case hold slack is 0.193" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630301132 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630301132 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.193 0.000 CLOCK_50 " " 0.193 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630301132 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630301132 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648630301133 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648630301135 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630301136 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630301136 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -48.277 CLOCK_50 " " -3.000 -48.277 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630301136 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630301136 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648630301431 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648630301431 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "412 " "Peak virtual memory: 412 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648630301464 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 11:51:41 2022 " "Processing ended: Wed Mar 30 11:51:41 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648630301464 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648630301464 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648630301464 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648630301464 ""}
db/spectrum.sta.rdb
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db/spectrum.sta_cmp.6_slow_1200mv_85c.tdb
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db/spectrum.tis_db_list.ddb
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db/spectrum.tiscmp.fast_1200mv_0c.ddb
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db/spectrum.tiscmp.slow_1200mv_0c.ddb
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db/spectrum.tiscmp.slow_1200mv_85c.ddb
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db/spectrum.tmw_info
+2
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start_analysis_synthesis:s:00:00:03-start_full_compilation
start_analysis_elaboration:s-start_full_compilation
db/spectrum.vpr.ammdb
BIN
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incremental_db/README
+11
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This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.
incremental_db/compiled_partitions/spectrum.db_info
+3
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Quartus_Version = Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
Version_Index = 318808576
Creation_Time = Wed Mar 30 11:47:24 2022
incremental_db/compiled_partitions/spectrum.root_partition.cmp.ammdb
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incremental_db/compiled_partitions/spectrum.root_partition.cmp.cdb
BIN
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incremental_db/compiled_partitions/spectrum.root_partition.cmp.dfp
BIN
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incremental_db/compiled_partitions/spectrum.root_partition.cmp.hdb
BIN
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incremental_db/compiled_partitions/spectrum.root_partition.cmp.logdb
+1
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v1
incremental_db/compiled_partitions/spectrum.root_partition.cmp.rcfdb
BIN
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incremental_db/compiled_partitions/spectrum.root_partition.map.cdb
BIN
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incremental_db/compiled_partitions/spectrum.root_partition.map.dpi
BIN
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incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.cdb
BIN
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incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hb_info
BIN
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incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hdb
BIN
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incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.sig
+1
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c5eb7f6cdd530884c3b884e0a3668ea4
incremental_db/compiled_partitions/spectrum.root_partition.map.hdb
BIN
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incremental_db/compiled_partitions/spectrum.root_partition.map.kpt
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output_files/spectrum.asm.rpt
+186
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Assembler report for spectrum
Wed Mar 30 11:51:38 2022
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: spectrum.sof
6. Assembler Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Wed Mar 30 11:51:38 2022 ;
; Revision Name ; spectrum ;
; Top-level Entity Name ; spectrum ;
; Family ; Cyclone IV E ;
; Device ; EP4CE22F17C6 ;
+-----------------------+---------------------------------------+
+--------------------------------------------------------------------------------+
; Assembler Settings ;
+--------------------------------------------------------------------------------+
Option : Use smart compilation
Setting : Off
Default Value : Off
Option : Enable parallel Assembler and TimeQuest Timing Analyzer during compilation
Setting : On
Default Value : On
Option : Enable compact report table
Setting : Off
Default Value : Off
Option : Generate compressed bitstreams
Setting : On
Default Value : On
Option : Compression mode
Setting : Off
Default Value : Off
Option : Clock source for configuration device
Setting : Internal
Default Value : Internal
Option : Clock frequency of the configuration device
Setting : 10 MHZ
Default Value : 10 MHz
Option : Divide clock frequency by
Setting : 1
Default Value : 1
Option : Auto user code
Setting : On
Default Value : On
Option : Use configuration device
Setting : Off
Default Value : Off
Option : Configuration device
Setting : Auto
Default Value : Auto
Option : Configuration device auto user code
Setting : Off
Default Value : Off
Option : Generate Tabular Text File (.ttf) For Target Device
Setting : Off
Default Value : Off
Option : Generate Raw Binary File (.rbf) For Target Device
Setting : Off
Default Value : Off
Option : Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device
Setting : Off
Default Value : Off
Option : Hexadecimal Output File start address
Setting : 0
Default Value : 0
Option : Hexadecimal Output File count direction
Setting : Up
Default Value : Up
Option : Release clears before tri-states
Setting : Off
Default Value : Off
Option : Auto-restart configuration after error
Setting : On
Default Value : On
Option : Enable OCT_DONE
Setting : Off
Default Value : Off
Option : Generate Serial Vector Format File (.svf) for Target Device
Setting : Off
Default Value : Off
Option : Generate a JEDEC STAPL Format File (.jam) for Target Device
Setting : Off
Default Value : Off
Option : Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device
Setting : Off
Default Value : Off
Option : Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device
Setting : On
Default Value : On
+--------------------------------------------------------------------------------+
+---------------------------+
; Assembler Generated Files ;
+---------------------------+
; File Name ;
+---------------------------+
; spectrum.sof ;
+---------------------------+
+----------------------------------------+
; Assembler Device Options: spectrum.sof ;
+----------------+-----------------------+
; Option ; Setting ;
+----------------+-----------------------+
; Device ; EP4CE22F17C6 ;
; JTAG usercode ; 0x00138B42 ;
; Checksum ; 0x00138B42 ;
+----------------+-----------------------+
+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit Assembler
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
Info: Processing started: Wed Mar 30 11:51:37 2022
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 389 megabytes
Info: Processing ended: Wed Mar 30 11:51:38 2022
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
output_files/spectrum.cdf
+13
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@@ -0,0 +1,13 @@
/* Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition */
JedecChain;
FileRevision(JESD32A);
DefaultMfr(6E);
P ActionCode(Cfg)
Device PartName(EP4CE22F17) Path("/home/benny/work/fpga/projects/output_files/") File("spectrum.sof") MfrSpec(OpMask(1));
ChainEnd;
AlteraBegin;
ChainType(JTAG);
AlteraEnd;
output_files/spectrum.done
+1
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@@ -0,0 +1 @@
Wed Mar 30 11:51:43 2022
output_files/spectrum.eda.rpt
+107
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@@ -0,0 +1,107 @@
EDA Netlist Writer report for spectrum
Wed Mar 30 11:51:43 2022
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. EDA Netlist Writer Summary
3. Simulation Settings
4. Simulation Generated Files
5. EDA Netlist Writer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------+
; EDA Netlist Writer Summary ;
+---------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Wed Mar 30 11:51:43 2022 ;
; Revision Name ; spectrum ;
; Top-level Entity Name ; spectrum ;
; Family ; Cyclone IV E ;
; Simulation Files Creation ; Successful ;
+---------------------------+---------------------------------------+
+-------------------------------------------------------------------------------------------------------------------------------+
; Simulation Settings ;
+---------------------------------------------------------------------------------------------------+---------------------------+
; Option ; Setting ;
+---------------------------------------------------------------------------------------------------+---------------------------+
; Tool Name ; ModelSim-Altera (Verilog) ;
; Generate netlist for functional simulation only ; Off ;
; Time scale ; 1 ps ;
; Truncate long hierarchy paths ; Off ;
; Map illegal HDL characters ; Off ;
; Flatten buses into individual nodes ; Off ;
; Maintain hierarchy ; Off ;
; Bring out device-wide set/reset signals as ports ; Off ;
; Enable glitch filtering ; Off ;
; Do not write top level VHDL entity ; Off ;
; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
; Architecture name in VHDL output netlist ; structure ;
; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
; Generate third-party EDA tool command script for gate-level simulation ; Off ;
+---------------------------------------------------------------------------------------------------+---------------------------+
+--------------------------------------------------------------------------------------+
; Simulation Generated Files ;
+--------------------------------------------------------------------------------------+
; Generated Files ;
+--------------------------------------------------------------------------------------+
; /home/benny/work/fpga/projects/simulation/modelsim/spectrum_6_1200mv_85c_slow.vo ;
; /home/benny/work/fpga/projects/simulation/modelsim/spectrum_6_1200mv_0c_slow.vo ;
; /home/benny/work/fpga/projects/simulation/modelsim/spectrum_min_1200mv_0c_fast.vo ;
; /home/benny/work/fpga/projects/simulation/modelsim/spectrum.vo ;
; /home/benny/work/fpga/projects/simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo ;
; /home/benny/work/fpga/projects/simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo ;
; /home/benny/work/fpga/projects/simulation/modelsim/spectrum_min_1200mv_0c_v_fast.sdo ;
; /home/benny/work/fpga/projects/simulation/modelsim/spectrum_v.sdo ;
+--------------------------------------------------------------------------------------+
+-----------------------------+
; EDA Netlist Writer Messages ;
+-----------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit EDA Netlist Writer
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
Info: Processing started: Wed Mar 30 11:51:42 2022
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum
Info (204019): Generated file spectrum_6_1200mv_85c_slow.vo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file spectrum_6_1200mv_0c_slow.vo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file spectrum_min_1200mv_0c_fast.vo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file spectrum.vo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file spectrum_v.sdo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool
Info: Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 352 megabytes
Info: Processing ended: Wed Mar 30 11:51:43 2022
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
output_files/spectrum.fit.rpt
+7531
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File diff suppressed because it is too large Load Diff
output_files/spectrum.fit.smsg
+8
View File
@@ -0,0 +1,8 @@
Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
Extra Info (176236): Started Fast Input/Output/OE register processing
Extra Info (176237): Finished Fast Input/Output/OE register processing
Extra Info (176238): Start inferring scan chains for DSP blocks
Extra Info (176239): Inferring scan chains for DSP blocks is complete
Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
output_files/spectrum.fit.summary
+16
View File
@@ -0,0 +1,16 @@
Fitter Status : Successful - Wed Mar 30 11:51:35 2022
Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
Revision Name : spectrum
Top-level Entity Name : spectrum
Family : Cyclone IV E
Device : EP4CE22F17C6
Timing Models : Final
Total logic elements : 35 / 22,320 ( < 1 % )
Total combinational functions : 28 / 22,320 ( < 1 % )
Dedicated logic registers : 35 / 22,320 ( < 1 % )
Total registers : 35
Total pins : 9 / 154 ( 6 % )
Total virtual pins : 0
Total memory bits : 0 / 608,256 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 132 ( 0 % )
Total PLLs : 0 / 4 ( 0 % )
output_files/spectrum.flow.rpt
+227
View File
@@ -0,0 +1,227 @@
Flow report for spectrum
Wed Mar 30 11:51:43 2022
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
8. Flow Messages
9. Flow Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+--------------------------------------------+
; Flow Status ; Successful - Wed Mar 30 11:51:43 2022 ;
; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
; Revision Name ; spectrum ;
; Top-level Entity Name ; spectrum ;
; Family ; Cyclone IV E ;
; Device ; EP4CE22F17C6 ;
; Timing Models ; Final ;
; Total logic elements ; 35 / 22,320 ( < 1 % ) ;
; Total combinational functions ; 28 / 22,320 ( < 1 % ) ;
; Dedicated logic registers ; 35 / 22,320 ( < 1 % ) ;
; Total registers ; 35 ;
; Total pins ; 9 / 154 ( 6 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 / 608,256 ( 0 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
+------------------------------------+--------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 03/30/2022 11:51:28 ;
; Main task ; Compilation ;
; Revision Name ; spectrum ;
+-------------------+---------------------+
+--------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+--------------------------------------------------------------------------------+
Assignment Name : COMPILER_SIGNATURE_ID
Value : 0.164863028816849
Default Value : --
Entity Name : --
Section Id : --
Assignment Name : EDA_OUTPUT_DATA_FORMAT
Value : Verilog Hdl
Default Value : --
Entity Name : --
Section Id : eda_simulation
Assignment Name : EDA_SIMULATION_TOOL
Value : ModelSim-Altera (Verilog)
Default Value : <None>
Entity Name : --
Section Id : --
Assignment Name : MAX_CORE_JUNCTION_TEMP
Value : 85
Default Value : --
Entity Name : --
Section Id : --
Assignment Name : MIN_CORE_JUNCTION_TEMP
Value : 0
Default Value : --
Entity Name : --
Section Id : --
Assignment Name : NOMINAL_CORE_SUPPLY_VOLTAGE
Value : 1.2V
Default Value : --
Entity Name : --
Section Id : --
Assignment Name : PARTITION_COLOR
Value : 16764057
Default Value : --
Entity Name : --
Section Id : Top
Assignment Name : PARTITION_FITTER_PRESERVATION_LEVEL
Value : PLACEMENT_AND_ROUTING
Default Value : --
Entity Name : --
Section Id : Top
Assignment Name : PARTITION_NETLIST_TYPE
Value : SOURCE
Default Value : --
Entity Name : --
Section Id : Top
Assignment Name : PROJECT_OUTPUT_DIRECTORY
Value : output_files
Default Value : --
Entity Name : --
Section Id : --
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+--------------------------------------------------------------------------------+
Module Name : Analysis & Synthesis
Elapsed Time : 00:00:01
Average Processors Used : 1.0
Peak Virtual Memory : 377 MB
Total CPU Time (on all processors) : 00:00:01
Module Name : Fitter
Elapsed Time : 00:00:05
Average Processors Used : 1.0
Peak Virtual Memory : 588 MB
Total CPU Time (on all processors) : 00:00:06
Module Name : Assembler
Elapsed Time : 00:00:01
Average Processors Used : 1.0
Peak Virtual Memory : 389 MB
Total CPU Time (on all processors) : 00:00:01
Module Name : TimeQuest Timing Analyzer
Elapsed Time : 00:00:02
Average Processors Used : 1.0
Peak Virtual Memory : 412 MB
Total CPU Time (on all processors) : 00:00:02
Module Name : EDA Netlist Writer
Elapsed Time : 00:00:01
Average Processors Used : 1.0
Peak Virtual Memory : 340 MB
Total CPU Time (on all processors) : 00:00:01
Module Name : Total
Elapsed Time : 00:00:10
Average Processors Used : --
Peak Virtual Memory : --
Total CPU Time (on all processors) : 00:00:11
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Flow OS Summary ;
+--------------------------------------------------------------------------------+
Module Name : Analysis & Synthesis
Machine Hostname : alpha
OS Name : Ubuntu 21.10
OS Version : 21
Processor type : x86_64
Module Name : Fitter
Machine Hostname : alpha
OS Name : Ubuntu 21.10
OS Version : 21
Processor type : x86_64
Module Name : Assembler
Machine Hostname : alpha
OS Name : Ubuntu 21.10
OS Version : 21
Processor type : x86_64
Module Name : TimeQuest Timing Analyzer
Machine Hostname : alpha
OS Name : Ubuntu 21.10
OS Version : 21
Processor type : x86_64
Module Name : EDA Netlist Writer
Machine Hostname : alpha
OS Name : Ubuntu 21.10
OS Version : 21
Processor type : x86_64
+--------------------------------------------------------------------------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum
quartus_fit --read_settings_files=off --write_settings_files=off spectrum -c spectrum
quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum
quartus_sta spectrum -c spectrum
quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum
output_files/spectrum.jdi
+8
View File
@@ -0,0 +1,8 @@
<sld_project_info>
<project>
<hash md5_digest_80b="30de10ed078191d33504"/>
</project>
<file_info>
<file device="EP4CE22F17C6" path="spectrum.sof" usercode="0xFFFFFFFF"/>
</file_info>
</sld_project_info>
output_files/spectrum.map.rpt
+518
View File
@@ -0,0 +1,518 @@
Analysis & Synthesis report for spectrum
Wed Mar 30 11:51:29 2022
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Parallel Compilation
5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. Registers Removed During Synthesis
9. General Register Statistics
10. Elapsed Time Per Partition
11. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+--------------------------------------------+
; Analysis & Synthesis Status ; Successful - Wed Mar 30 11:51:29 2022 ;
; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
; Revision Name ; spectrum ;
; Top-level Entity Name ; spectrum ;
; Family ; Cyclone IV E ;
; Total logic elements ; 35 ;
; Total combinational functions ; 28 ;
; Dedicated logic registers ; 35 ;
; Total registers ; 35 ;
; Total pins ; 9 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Total PLLs ; 0 ;
+------------------------------------+--------------------------------------------+
+--------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+--------------------------------------------------------------------------------+
Option : Device
Setting : EP4CE22F17C6
Default Value :
Option : Top-level entity name
Setting : spectrum
Default Value : spectrum
Option : Family name
Setting : Cyclone IV E
Default Value : Cyclone IV GX
Option : Use smart compilation
Setting : Off
Default Value : Off
Option : Enable parallel Assembler and TimeQuest Timing Analyzer during compilation
Setting : On
Default Value : On
Option : Enable compact report table
Setting : Off
Default Value : Off
Option : Restructure Multiplexers
Setting : Auto
Default Value : Auto
Option : Create Debugging Nodes for IP Cores
Setting : Off
Default Value : Off
Option : Preserve fewer node names
Setting : On
Default Value : On
Option : Disable OpenCore Plus hardware evaluation
Setting : Off
Default Value : Off
Option : Verilog Version
Setting : Verilog_2001
Default Value : Verilog_2001
Option : VHDL Version
Setting : VHDL_1993
Default Value : VHDL_1993
Option : State Machine Processing
Setting : Auto
Default Value : Auto
Option : Safe State Machine
Setting : Off
Default Value : Off
Option : Extract Verilog State Machines
Setting : On
Default Value : On
Option : Extract VHDL State Machines
Setting : On
Default Value : On
Option : Ignore Verilog initial constructs
Setting : Off
Default Value : Off
Option : Iteration limit for constant Verilog loops
Setting : 5000
Default Value : 5000
Option : Iteration limit for non-constant Verilog loops
Setting : 250
Default Value : 250
Option : Add Pass-Through Logic to Inferred RAMs
Setting : On
Default Value : On
Option : Infer RAMs from Raw Logic
Setting : On
Default Value : On
Option : Parallel Synthesis
Setting : On
Default Value : On
Option : DSP Block Balancing
Setting : Auto
Default Value : Auto
Option : NOT Gate Push-Back
Setting : On
Default Value : On
Option : Power-Up Don't Care
Setting : On
Default Value : On
Option : Remove Redundant Logic Cells
Setting : Off
Default Value : Off
Option : Remove Duplicate Registers
Setting : On
Default Value : On
Option : Ignore CARRY Buffers
Setting : Off
Default Value : Off
Option : Ignore CASCADE Buffers
Setting : Off
Default Value : Off
Option : Ignore GLOBAL Buffers
Setting : Off
Default Value : Off
Option : Ignore ROW GLOBAL Buffers
Setting : Off
Default Value : Off
Option : Ignore LCELL Buffers
Setting : Off
Default Value : Off
Option : Ignore SOFT Buffers
Setting : On
Default Value : On
Option : Limit AHDL Integers to 32 Bits
Setting : Off
Default Value : Off
Option : Optimization Technique
Setting : Balanced
Default Value : Balanced
Option : Carry Chain Length
Setting : 70
Default Value : 70
Option : Auto Carry Chains
Setting : On
Default Value : On
Option : Auto Open-Drain Pins
Setting : On
Default Value : On
Option : Perform WYSIWYG Primitive Resynthesis
Setting : Off
Default Value : Off
Option : Auto ROM Replacement
Setting : On
Default Value : On
Option : Auto RAM Replacement
Setting : On
Default Value : On
Option : Auto DSP Block Replacement
Setting : On
Default Value : On
Option : Auto Shift Register Replacement
Setting : Auto
Default Value : Auto
Option : Allow Shift Register Merging across Hierarchies
Setting : Auto
Default Value : Auto
Option : Auto Clock Enable Replacement
Setting : On
Default Value : On
Option : Strict RAM Replacement
Setting : Off
Default Value : Off
Option : Allow Synchronous Control Signals
Setting : On
Default Value : On
Option : Force Use of Synchronous Clear Signals
Setting : Off
Default Value : Off
Option : Auto RAM Block Balancing
Setting : On
Default Value : On
Option : Auto RAM to Logic Cell Conversion
Setting : Off
Default Value : Off
Option : Auto Resource Sharing
Setting : Off
Default Value : Off
Option : Allow Any RAM Size For Recognition
Setting : Off
Default Value : Off
Option : Allow Any ROM Size For Recognition
Setting : Off
Default Value : Off
Option : Allow Any Shift Register Size For Recognition
Setting : Off
Default Value : Off
Option : Use LogicLock Constraints during Resource Balancing
Setting : On
Default Value : On
Option : Ignore translate_off and synthesis_off directives
Setting : Off
Default Value : Off
Option : Timing-Driven Synthesis
Setting : On
Default Value : On
Option : Report Parameter Settings
Setting : On
Default Value : On
Option : Report Source Assignments
Setting : On
Default Value : On
Option : Report Connectivity Checks
Setting : On
Default Value : On
Option : Ignore Maximum Fan-Out Assignments
Setting : Off
Default Value : Off
Option : Synchronization Register Chain Length
Setting : 2
Default Value : 2
Option : PowerPlay Power Optimization
Setting : Normal compilation
Default Value : Normal compilation
Option : HDL message level
Setting : Level2
Default Value : Level2
Option : Suppress Register Optimization Related Messages
Setting : Off
Default Value : Off
Option : Number of Removed Registers Reported in Synthesis Report
Setting : 5000
Default Value : 5000
Option : Number of Swept Nodes Reported in Synthesis Report
Setting : 5000
Default Value : 5000
Option : Number of Inverted Registers Reported in Synthesis Report
Setting : 100
Default Value : 100
Option : Clock MUX Protection
Setting : On
Default Value : On
Option : Auto Gated Clock Conversion
Setting : Off
Default Value : Off
Option : Block Design Naming
Setting : Auto
Default Value : Auto
Option : SDC constraint protection
Setting : Off
Default Value : Off
Option : Synthesis Effort
Setting : Auto
Default Value : Auto
Option : Shift Register Replacement - Allow Asynchronous Clear Signal
Setting : On
Default Value : On
Option : Pre-Mapping Resynthesis Optimization
Setting : Off
Default Value : Off
Option : Analysis & Synthesis Message Level
Setting : Medium
Default Value : Medium
Option : Disable Register Merging Across Hierarchies
Setting : Auto
Default Value : Auto
Option : Resource Aware Inference For Block RAM
Setting : On
Default Value : On
Option : Synthesis Seed
Setting : 1
Default Value : 1
+--------------------------------------------------------------------------------+
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation ;
+----------------------------+--------+
; Processors ; Number ;
+----------------------------+--------+
; Number detected on machine ; 12 ;
; Maximum allowed ; 1 ;
+----------------------------+--------+
+--------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+--------------------------------------------------------------------------------+
File Name with User-Entered Path : spectrum.v
Used in Netlist : yes
File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/projects/spectrum.v
Library :
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+----------------+
; Resource ; Usage ;
+---------------------------------------------+----------------+
; Estimated Total logic elements ; 35 ;
; ; ;
; Total combinational functions ; 28 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 0 ;
; -- 3 input functions ; 1 ;
; -- <=2 input functions ; 27 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 2 ;
; -- arithmetic mode ; 26 ;
; ; ;
; Total registers ; 35 ;
; -- Dedicated logic registers ; 35 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 9 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Maximum fan-out node ; CLOCK_50~input ;
; Maximum fan-out ; 35 ;
; Total fan-out ; 141 ;
; Average fan-out ; 1.74 ;
+---------------------------------------------+----------------+
+--------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+--------------------------------------------------------------------------------+
Compilation Hierarchy Node : |spectrum
LC Combinationals : 28 (28)
LC Registers : 35 (35)
Memory Bits : 0
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 9
Virtual Pins : 0
Full Hierarchy Name : |spectrum
Library Name : work
+--------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+---------------------------------------+----------------------------------------+
; Register name ; Reason for Removal ;
+---------------------------------------+----------------------------------------+
; LED[7]~reg0 ; Stuck at GND due to stuck port data_in ;
; Total Number of Removed Registers = 1 ; ;
+---------------------------------------+----------------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 35 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-------------------------------+
; Elapsed Time Per Partition ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top ; 00:00:00 ;
+----------------+--------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit Analysis & Synthesis
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
Info: Processing started: Wed Mar 30 11:51:28 2022
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (12021): Found 1 design units, including 1 entities, in source file spectrum.v
Info (12023): Found entity 1: spectrum
Info (12127): Elaborating entity "spectrum" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at spectrum.v(10): truncated value with size 32 to match size of target (28)
Warning (13024): Output pins are stuck at VCC or GND
Warning (13410): Pin "LED[7]" is stuck at GND
Info (286030): Timing-Driven Synthesis is running
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Info (21057): Implemented 44 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 1 input pins
Info (21059): Implemented 8 output pins
Info (21061): Implemented 35 logic cells
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 4 warnings
Info: Peak virtual memory: 388 megabytes
Info: Processing ended: Wed Mar 30 11:51:29 2022
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
output_files/spectrum.map.summary
+14
View File
@@ -0,0 +1,14 @@
Analysis & Synthesis Status : Successful - Wed Mar 30 11:51:29 2022
Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
Revision Name : spectrum
Top-level Entity Name : spectrum
Family : Cyclone IV E
Total logic elements : 35
Total combinational functions : 28
Dedicated logic registers : 35
Total registers : 35
Total pins : 9
Total virtual pins : 0
Total memory bits : 0
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0
output_files/spectrum.pin
+326
View File
@@ -0,0 +1,326 @@
-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--
-- This is a Quartus II output file. It is for reporting purposes only, and is
-- not intended for use as a Quartus II input file. This file cannot be used
-- to make Quartus II pin assignments - for instructions on how to make pin
-- assignments, please see Quartus II help.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- NC : No Connect. This pin has no internal connection to the device.
-- DNU : Do Not Use. This pin MUST NOT be connected.
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- Bank 1: 3.3V
-- Bank 2: 3.3V
-- Bank 3: 3.3V
-- Bank 4: 2.5V
-- Bank 5: 2.5V
-- Bank 6: 2.5V
-- Bank 7: 3.3V
-- Bank 8: 2.5V
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
-- It can also be used to report unused dedicated pins. The connection
-- on the board for unused dedicated pins depends on whether this will
-- be used in a future design. One example is device migration. When
-- using device migration, refer to the device pin-tables. If it is a
-- GND pin in the pin table or if it will not be used in a future design
-- for another purpose the it MUST be connected to GND. If it is an unused
-- dedicated pin, then it can be connected to a valid signal on the board
-- (low, high, or toggling) if that signal is required for a different
-- revision of the design.
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
-- This pin should be connected to GND. It may also be connected to a
-- valid signal on the board (low, high, or toggling) if that signal
-- is required for a different revision of the design.
-- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
-- or leave it unconnected.
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
-- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
-- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
-- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Pin directions (input, output or bidir) are based on device operating in user mode.
---------------------------------------------------------------------------------
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
CHIP "spectrum" ASSIGNED TO AN: EP4CE22F17C6
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
VCCIO8 : A1 : power : : 2.5V : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A2 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 8 :
GND+ : A8 : : : : 8 :
GND+ : A9 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 7 :
LED[3] : A11 : output : 3.3-V LVTTL : : 7 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 7 :
LED[1] : A13 : output : 3.3-V LVTTL : : 7 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7 :
LED[0] : A15 : output : 3.3-V LVTTL : : 7 : Y
VCCIO7 : A16 : power : : 3.3V : 7 :
LED[6] : B1 : output : 3.3-V LVTTL : : 1 : Y
GND : B2 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 :
GND+ : B8 : : : : 8 :
GND+ : B9 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B12 : : : : 7 :
LED[2] : B13 : output : 3.3-V LVTTL : : 7 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : B14 : : : : 7 :
GND : B15 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B16 : : : : 6 :
~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C1 : input : 3.3-V LVTTL : : 1 : N
RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 :
VCCIO8 : C4 : power : : 2.5V : 8 :
GND : C5 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 :
VCCIO8 : C7 : power : : 2.5V : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 7 :
VCCIO7 : C10 : power : : 3.3V : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C11 : : : : 7 :
GND : C12 : gnd : : : :
VCCIO7 : C13 : power : : 3.3V : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C16 : : : : 6 :
LED[4] : D1 : output : 3.3-V LVTTL : : 1 : Y
~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : input : 3.3-V LVTTL : : 1 : N
RESERVED_INPUT_WITH_WEAK_PULLUP : D3 : : : : 8 :
VCCD_PLL3 : D4 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 :
GND : D7 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 7 :
GND : D10 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 7 :
VCCD_PLL2 : D13 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 6 :
GND+ : E1 : : : : 1 :
GND : E2 : gnd : : : :
VCCIO1 : E3 : power : : 3.3V : 1 :
GND : E4 : gnd : : : :
GNDA3 : E5 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : E6 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 7 :
GNDA2 : E12 : gnd : : : :
GND : E13 : gnd : : : :
VCCIO6 : E14 : power : : 2.5V : 6 :
GND+ : E15 : : : : 6 :
GND+ : E16 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1 :
LED[5] : F3 : output : 3.3-V LVTTL : : 1 : Y
nSTATUS : F4 : : : : 1 :
VCCA3 : F5 : power : : 2.5V : :
GND : F6 : gnd : : : :
VCCINT : F7 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F9 : : : : 7 :
GND : F10 : gnd : : : :
VCCINT : F11 : power : : 1.2V : :
VCCA2 : F12 : power : : 2.5V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : F13 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 6 :
~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : F16 : output : 2.5 V : : 6 : N
RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : G2 : : : : 1 :
VCCIO1 : G3 : power : : 3.3V : 1 :
GND : G4 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : G5 : : : : 1 :
VCCINT : G6 : power : : 1.2V : :
VCCINT : G7 : power : : 1.2V : :
VCCINT : G8 : power : : 1.2V : :
VCCINT : G9 : power : : 1.2V : :
VCCINT : G10 : power : : 1.2V : :
GND : G11 : gnd : : : :
MSEL2 : G12 : : : : 6 :
GND : G13 : gnd : : : :
VCCIO6 : G14 : power : : 2.5V : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 6 :
~ALTERA_DCLK~ : H1 : output : 3.3-V LVTTL : : 1 : N
~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : H2 : input : 3.3-V LVTTL : : 1 : N
TCK : H3 : input : : : 1 :
TDI : H4 : input : : : 1 :
nCONFIG : H5 : : : : 1 :
VCCINT : H6 : power : : 1.2V : :
GND : H7 : gnd : : : :
GND : H8 : gnd : : : :
GND : H9 : gnd : : : :
GND : H10 : gnd : : : :
VCCINT : H11 : power : : 1.2V : :
MSEL1 : H12 : : : : 6 :
MSEL0 : H13 : : : : 6 :
CONF_DONE : H14 : : : : 6 :
GND : H15 : gnd : : : :
GND : H16 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : J1 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J2 : : : : 2 :
nCE : J3 : : : : 1 :
TDO : J4 : output : : : 1 :
TMS : J5 : input : : : 1 :
VCCINT : J6 : power : : 1.2V : :
GND : J7 : gnd : : : :
GND : J8 : gnd : : : :
GND : J9 : gnd : : : :
GND : J10 : gnd : : : :
GND : J11 : gnd : : : :
VCCINT : J12 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J16 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 2 :
VCCIO2 : K3 : power : : 3.3V : 2 :
GND : K4 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : K5 : : : : 2 :
GND : K6 : gnd : : : :
VCCINT : K7 : power : : 1.2V : :
GND : K8 : gnd : : : :
VCCINT : K9 : power : : 1.2V : :
VCCINT : K10 : power : : 1.2V : :
VCCINT : K11 : power : : 1.2V : :
GND : K12 : gnd : : : :
GND : K13 : gnd : : : :
VCCIO5 : K14 : power : : 2.5V : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : K15 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : K16 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : L1 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : L2 : : : : 2 :
LED[7] : L3 : output : 3.3-V LVTTL : : 2 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : : : : 2 :
VCCA1 : L5 : power : : 2.5V : :
VCCINT : L6 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : L7 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 3 :
GND : L9 : gnd : : : :
GND : L10 : gnd : : : :
GND : L11 : gnd : : : :
VCCA4 : L12 : power : : 2.5V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : L13 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : L14 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : L15 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : L16 : : : : 5 :
GND+ : M1 : : : : 2 :
GND+ : M2 : : : : 2 :
VCCIO2 : M3 : power : : 3.3V : 2 :
GND : M4 : gnd : : : :
GNDA1 : M5 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : M6 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M7 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 3 :
VCCINT : M9 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : M10 : : : : 4 :
VCCINT : M11 : power : : 1.2V : :
GNDA4 : M12 : gnd : : : :
GND : M13 : gnd : : : :
VCCIO5 : M14 : power : : 2.5V : 5 :
GND+ : M15 : : : : 5 :
GND+ : M16 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N1 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N2 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 3 :
VCCD_PLL1 : N4 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : N5 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N6 : : : : 3 :
GND : N7 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N9 : : : : 4 :
GND : N10 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : N11 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N12 : : : : 4 :
VCCD_PLL4 : N13 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : N14 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N15 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N16 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P2 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P3 : : : : 3 :
VCCIO3 : P4 : power : : 3.3V : 3 :
GND : P5 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : P6 : : : : 3 :
VCCIO3 : P7 : power : : 3.3V : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P8 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P9 : : : : 4 :
VCCIO4 : P10 : power : : 2.5V : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P11 : : : : 4 :
GND : P12 : gnd : : : :
VCCIO4 : P13 : power : : 2.5V : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P14 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P15 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P16 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 :
GND : R2 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R6 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 3 :
CLOCK_50 : R8 : input : 3.3-V LVTTL : : 3 : Y
GND+ : R9 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R10 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R11 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R12 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R13 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R14 : : : : 4 :
GND : R15 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : R16 : : : : 5 :
VCCIO3 : T1 : power : : 3.3V : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T2 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T4 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T5 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T6 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 3 :
GND+ : T8 : : : : 3 :
GND+ : T9 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T10 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T11 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T12 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T13 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T14 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T15 : : : : 4 :
VCCIO4 : T16 : power : : 2.5V : 4 :
output_files/spectrum.sof
BIN
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output_files/spectrum.sta.rpt
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output_files/spectrum.sta.summary
+41
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------------------------------------------------------------
TimeQuest Timing Analyzer Summary
------------------------------------------------------------
Type : Slow 1200mV 85C Model Setup 'CLOCK_50'
Slack : -1.606
TNS : -30.234
Type : Slow 1200mV 85C Model Hold 'CLOCK_50'
Slack : 0.360
TNS : 0.000
Type : Slow 1200mV 85C Model Minimum Pulse Width 'CLOCK_50'
Slack : -3.000
TNS : -38.000
Type : Slow 1200mV 0C Model Setup 'CLOCK_50'
Slack : -1.275
TNS : -22.690
Type : Slow 1200mV 0C Model Hold 'CLOCK_50'
Slack : 0.319
TNS : 0.000
Type : Slow 1200mV 0C Model Minimum Pulse Width 'CLOCK_50'
Slack : -3.000
TNS : -38.000
Type : Fast 1200mV 0C Model Setup 'CLOCK_50'
Slack : -0.500
TNS : -4.764
Type : Fast 1200mV 0C Model Hold 'CLOCK_50'
Slack : 0.193
TNS : 0.000
Type : Fast 1200mV 0C Model Minimum Pulse Width 'CLOCK_50'
Slack : -3.000
TNS : -48.277
------------------------------------------------------------
simulation/modelsim/spectrum.sft
+6
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set tool_name "ModelSim-Altera (Verilog)"
set corner_file_list {
{{"Slow -6 1.2V 85 Model"} {spectrum_6_1200mv_85c_slow.vo spectrum_6_1200mv_85c_v_slow.sdo}}
{{"Slow -6 1.2V 0 Model"} {spectrum_6_1200mv_0c_slow.vo spectrum_6_1200mv_0c_v_slow.sdo}}
{{"Fast -M 1.2V 0 Model"} {spectrum_min_1200mv_0c_fast.vo spectrum_min_1200mv_0c_v_fast.sdo}}
}
simulation/modelsim/spectrum.vo
+1574
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simulation/modelsim/spectrum_6_1200mv_0c_slow.vo
+1574
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simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo
+1072
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simulation/modelsim/spectrum_6_1200mv_85c_slow.vo
+1574
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simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo
+1072
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simulation/modelsim/spectrum_min_1200mv_0c_fast.vo
+1574
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