commit fa29e9f3f6288633b701036f6fec67d7d75daa38
Author: Adrian Scripca <benishor@gmail.com>
Date:   Wed Mar 30 11:53:01 2022 +0300

    Initial import. Counter to leds

diff --git a/db/.cmp.kpt b/db/.cmp.kpt
new file mode 100644
index 0000000..48317e4
Binary files /dev/null and b/db/.cmp.kpt differ
diff --git a/db/logic_util_heursitic.dat b/db/logic_util_heursitic.dat
new file mode 100644
index 0000000..ba84581
Binary files /dev/null and b/db/logic_util_heursitic.dat differ
diff --git a/db/prev_cmp_spectrum.qmsg b/db/prev_cmp_spectrum.qmsg
new file mode 100644
index 0000000..9b1b973
--- /dev/null
+++ b/db/prev_cmp_spectrum.qmsg
@@ -0,0 +1,127 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648630228952 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648630228953 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 11:50:28 2022 " "Processing started: Wed Mar 30 11:50:28 2022" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648630228953 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648630228953 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum " "Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648630228953 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648630229117 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spectrum.v 1 1 " "Found 1 design units, including 1 entities, in source file spectrum.v" { { "Info" "ISGN_ENTITY_NAME" "1 spectrum " "Found entity 1: spectrum" {  } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648630229180 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648630229180 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "spectrum " "Elaborating entity \"spectrum\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1648630229231 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 spectrum.v(10) " "Verilog HDL assignment warning at spectrum.v(10): truncated value with size 32 to match size of target (23)" {  } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 10 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1648630229232 "|spectrum"}
+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[7\] GND " "Pin \"LED\[7\]\" is stuck at GND" {  } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 8 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648630229558 "|spectrum|LED[7]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1648630229558 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1648630229650 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1648630229841 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648630229841 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "39 " "Implemented 39 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Implemented 1 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1648630229879 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1648630229879 ""} { "Info" "ICUT_CUT_TM_LCELLS" "30 " "Implemented 30 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1648630229879 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1648630229879 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "379 " "Peak virtual memory: 379 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648630229887 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 11:50:29 2022 " "Processing ended: Wed Mar 30 11:50:29 2022" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648630229887 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648630229887 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648630229887 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648630229887 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648630231222 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648630231223 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 11:50:30 2022 " "Processing started: Wed Mar 30 11:50:30 2022" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648630231223 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1648630231223 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_fit --read_settings_files=off --write_settings_files=off spectrum -c spectrum" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1648630231223 ""}
+{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1648630231248 ""}
+{ "Info" "0" "" "Project  = spectrum" {  } {  } 0 0 "Project  = spectrum" 0 0 "Fitter" 0 0 1648630231249 ""}
+{ "Info" "0" "" "Revision = spectrum" {  } {  } 0 0 "Revision = spectrum" 0 0 "Fitter" 0 0 1648630231249 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1648630231293 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "spectrum EP4CE22F17C6 " "Selected device EP4CE22F17C6 for design \"spectrum\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1648630231296 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648630231334 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648630231334 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648630231334 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1648630231406 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1648630231416 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17C6 " "Device EP4CE10F17C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648630231621 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C6 " "Device EP4CE6F17C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648630231621 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C6 " "Device EP4CE15F17C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648630231621 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1648630231621 ""}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" {  } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 260 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648630231626 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" {  } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 262 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648630231626 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" {  } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 264 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648630231626 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" {  } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 266 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648630231626 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" {  } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 268 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648630231626 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1648630231626 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1648630231628 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "spectrum.sdc " "Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1648630232273 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1648630232273 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1648630232275 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1648630232275 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1648630232276 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p)) " "Automatically promoted node CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G18 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648630232282 ""}  } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 255 9662 10382 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648630232282 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1648630232513 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648630232513 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648630232513 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648630232514 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648630232515 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1648630232515 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1648630232515 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1648630232515 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1648630232527 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1648630232527 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1648630232527 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS_N " "Node \"ADC_CS_N\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_CS_N" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SADDR " "Node \"ADC_SADDR\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SADDR" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCLK " "Node \"ADC_SCLK\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SCLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDAT " "Node \"ADC_SDAT\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SDAT" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_ASDO " "Node \"EPCS_ASDO\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_ASDO" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DATA0 " "Node \"EPCS_DATA0\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DATA0" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DCLK " "Node \"EPCS_DCLK\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DCLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_NCSO " "Node \"EPCS_NCSO\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_NCSO" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[0\] " "Node \"GPIO_0\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[10\] " "Node \"GPIO_0\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[11\] " "Node \"GPIO_0\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[12\] " "Node \"GPIO_0\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[13\] " "Node \"GPIO_0\[13\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[13\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[14\] " "Node \"GPIO_0\[14\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[14\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[15\] " "Node \"GPIO_0\[15\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[15\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[16\] " "Node \"GPIO_0\[16\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[16\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[17\] " "Node \"GPIO_0\[17\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[17\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[18\] " "Node \"GPIO_0\[18\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[18\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[19\] " "Node \"GPIO_0\[19\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[19\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[1\] " "Node \"GPIO_0\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[20\] " "Node \"GPIO_0\[20\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[20\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[21\] " "Node \"GPIO_0\[21\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[21\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[22\] " "Node \"GPIO_0\[22\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[22\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[23\] " "Node \"GPIO_0\[23\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[23\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[24\] " "Node \"GPIO_0\[24\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[24\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[25\] " "Node \"GPIO_0\[25\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[25\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[26\] " "Node \"GPIO_0\[26\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[26\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[27\] " "Node \"GPIO_0\[27\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[27\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[28\] " "Node \"GPIO_0\[28\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[28\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[29\] " "Node \"GPIO_0\[29\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[29\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[2\] " "Node \"GPIO_0\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[30\] " "Node \"GPIO_0\[30\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[30\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[31\] " "Node \"GPIO_0\[31\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[31\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[32\] " "Node \"GPIO_0\[32\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[32\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[33\] " "Node \"GPIO_0\[33\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[33\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[3\] " "Node \"GPIO_0\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[4\] " "Node \"GPIO_0\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[5\] " "Node \"GPIO_0\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[6\] " "Node \"GPIO_0\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[7\] " "Node \"GPIO_0\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[8\] " "Node \"GPIO_0\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[9\] " "Node \"GPIO_0\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[0\] " "Node \"GPIO_0_IN\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[1\] " "Node \"GPIO_0_IN\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[0\] " "Node \"GPIO_1\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[10\] " "Node \"GPIO_1\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[11\] " "Node \"GPIO_1\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[12\] " "Node \"GPIO_1\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[13\] " "Node \"GPIO_1\[13\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[14\] " "Node \"GPIO_1\[14\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[15\] " "Node \"GPIO_1\[15\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[16\] " "Node \"GPIO_1\[16\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[17\] " "Node \"GPIO_1\[17\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[18\] " "Node \"GPIO_1\[18\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[19\] " "Node \"GPIO_1\[19\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[1\] " "Node \"GPIO_1\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[20\] " "Node \"GPIO_1\[20\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[21\] " "Node \"GPIO_1\[21\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[22\] " "Node \"GPIO_1\[22\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[23\] " "Node \"GPIO_1\[23\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[24\] " "Node \"GPIO_1\[24\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[25\] " "Node \"GPIO_1\[25\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[26\] " "Node \"GPIO_1\[26\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[27\] " "Node \"GPIO_1\[27\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[28\] " "Node \"GPIO_1\[28\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[29\] " "Node \"GPIO_1\[29\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[2\] " "Node \"GPIO_1\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[30\] " "Node \"GPIO_1\[30\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[31\] " "Node \"GPIO_1\[31\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[32\] " "Node \"GPIO_1\[32\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[32\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[33\] " "Node \"GPIO_1\[33\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[33\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[3\] " "Node \"GPIO_1\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[4\] " "Node \"GPIO_1\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[5\] " "Node \"GPIO_1\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[6\] " "Node \"GPIO_1\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[7\] " "Node \"GPIO_1\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[8\] " "Node \"GPIO_1\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[9\] " "Node \"GPIO_1\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[0\] " "Node \"GPIO_1_IN\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[1\] " "Node \"GPIO_1_IN\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[0\] " "Node \"GPIO_2\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[10\] " "Node \"GPIO_2\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[11\] " "Node \"GPIO_2\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[12\] " "Node \"GPIO_2\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[1\] " "Node \"GPIO_2\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[2\] " "Node \"GPIO_2\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[3\] " "Node \"GPIO_2\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[4\] " "Node \"GPIO_2\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[5\] " "Node \"GPIO_2\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[6\] " "Node \"GPIO_2\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[7\] " "Node \"GPIO_2\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[8\] " "Node \"GPIO_2\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[9\] " "Node \"GPIO_2\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[0\] " "Node \"GPIO_2_IN\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[1\] " "Node \"GPIO_2_IN\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[2\] " "Node \"GPIO_2_IN\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_CS_N " "Node \"G_SENSOR_CS_N\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_CS_N" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_INT " "Node \"G_SENSOR_INT\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_INT" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1648630232539 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648630232545 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1648630233501 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648630233566 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1648630233574 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1648630233971 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648630233971 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1648630234209 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X32_Y23 X42_Y34 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X32_Y23 to location X42_Y34" {  } { { "loc" "" { Generic "/home/benny/work/fpga/projects/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X32_Y23 to location X42_Y34"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X32_Y23 to location X42_Y34"} 32 23 11 12 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1648630234782 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1648630234782 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648630235154 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1648630235154 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1648630235154 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.18 " "Total time spent on timing analysis during the Fitter is 0.18 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1648630235163 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648630235216 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648630235373 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648630235419 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648630235548 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648630235825 ""}
+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1648630236172 ""}
+{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "1 Cyclone IV E " "1 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK_50 3.3-V LVTTL R8 " "Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at R8" {  } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { CLOCK_50 } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 12 9662 10382 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648630236175 ""}  } {  } 0 169177 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1648630236175 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/projects/output_files/spectrum.fit.smsg " "Generated suppressed messages file /home/benny/work/fpga/projects/output_files/spectrum.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1648630236217 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 152 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 152 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "588 " "Peak virtual memory: 588 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648630236394 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 11:50:36 2022 " "Processing ended: Wed Mar 30 11:50:36 2022" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648630236394 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648630236394 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648630236394 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1648630236394 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1648630237921 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648630237922 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 11:50:37 2022 " "Processing started: Wed Mar 30 11:50:37 2022" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648630237922 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1648630237922 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1648630237922 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1648630238828 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1648630238854 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "390 " "Peak virtual memory: 390 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648630239091 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 11:50:39 2022 " "Processing ended: Wed Mar 30 11:50:39 2022" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648630239091 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648630239091 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648630239091 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1648630239091 ""}
+{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1648630239178 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1648630240458 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648630240459 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 11:50:40 2022 " "Processing started: Wed Mar 30 11:50:40 2022" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648630240459 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648630240459 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta spectrum -c spectrum " "Command: quartus_sta spectrum -c spectrum" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648630240459 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1648630240487 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648630240585 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648630240587 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648630240628 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648630240628 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "spectrum.sdc " "Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1648630240821 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1648630240821 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648630240822 ""}  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648630240822 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1648630240947 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648630240947 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1648630240948 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1648630240953 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648630240960 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648630240960 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.257 " "Worst-case setup slack is -1.257" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630240961 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630240961 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.257             -21.840 CLOCK_50  " "   -1.257             -21.840 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630240961 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630240961 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.361 " "Worst-case hold slack is 0.361" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630240962 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630240962 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.361               0.000 CLOCK_50  " "    0.361               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630240962 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630240962 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648630240962 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648630240963 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630240963 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630240963 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000             -33.000 CLOCK_50  " "   -3.000             -33.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630240963 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630240963 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648630240977 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1648630241000 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1648630241363 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648630241379 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648630241380 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648630241380 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.976 " "Worst-case setup slack is -0.976" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630241381 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630241381 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.976             -15.990 CLOCK_50  " "   -0.976             -15.990 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630241381 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630241381 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.319 " "Worst-case hold slack is 0.319" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630241382 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630241382 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.319               0.000 CLOCK_50  " "    0.319               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630241382 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630241382 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648630241383 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648630241384 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630241385 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630241385 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000             -33.000 CLOCK_50  " "   -3.000             -33.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630241385 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630241385 ""}
+{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648630241400 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648630241519 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648630241519 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648630241519 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.296 " "Worst-case setup slack is -0.296" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630241521 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630241521 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.296              -2.219 CLOCK_50  " "   -0.296              -2.219 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630241521 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630241521 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.193 " "Worst-case hold slack is 0.193" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630241522 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630241522 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.193               0.000 CLOCK_50  " "    0.193               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630241522 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630241522 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648630241524 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648630241525 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630241527 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630241527 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000             -41.779 CLOCK_50  " "   -3.000             -41.779 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630241527 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630241527 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648630241819 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648630241819 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "416 " "Peak virtual memory: 416 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648630241853 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 11:50:41 2022 " "Processing ended: Wed Mar 30 11:50:41 2022" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648630241853 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648630241853 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648630241853 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648630241853 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648630243435 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648630243435 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 11:50:43 2022 " "Processing started: Wed Mar 30 11:50:43 2022" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648630243435 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648630243435 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648630243436 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630243721 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630243741 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_fast.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_fast.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630243760 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630243780 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630243800 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630243819 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_v_fast.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630243838 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_v.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_v.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630243856 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "352 " "Peak virtual memory: 352 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648630243887 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 11:50:43 2022 " "Processing ended: Wed Mar 30 11:50:43 2022" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648630243887 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648630243887 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648630243887 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648630243887 ""}
+{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 161 s " "Quartus II Full Compilation was successful. 0 errors, 161 warnings" {  } {  } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648630243976 ""}
diff --git a/db/spectrum.(0).cnf.cdb b/db/spectrum.(0).cnf.cdb
new file mode 100644
index 0000000..e04e75f
Binary files /dev/null and b/db/spectrum.(0).cnf.cdb differ
diff --git a/db/spectrum.(0).cnf.hdb b/db/spectrum.(0).cnf.hdb
new file mode 100644
index 0000000..406f67d
Binary files /dev/null and b/db/spectrum.(0).cnf.hdb differ
diff --git a/db/spectrum.asm.qmsg b/db/spectrum.asm.qmsg
new file mode 100644
index 0000000..3c169f1
--- /dev/null
+++ b/db/spectrum.asm.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648630297528 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648630297529 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 11:51:37 2022 " "Processing started: Wed Mar 30 11:51:37 2022" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648630297529 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1648630297529 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1648630297529 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1648630298448 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1648630298474 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "389 " "Peak virtual memory: 389 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648630298719 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 11:51:38 2022 " "Processing ended: Wed Mar 30 11:51:38 2022" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648630298719 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648630298719 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648630298719 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1648630298719 ""}
diff --git a/db/spectrum.asm.rdb b/db/spectrum.asm.rdb
new file mode 100644
index 0000000..ed7fadc
Binary files /dev/null and b/db/spectrum.asm.rdb differ
diff --git a/db/spectrum.asm_labs.ddb b/db/spectrum.asm_labs.ddb
new file mode 100644
index 0000000..2bfdbd9
Binary files /dev/null and b/db/spectrum.asm_labs.ddb differ
diff --git a/db/spectrum.cbx.xml b/db/spectrum.cbx.xml
new file mode 100644
index 0000000..f0b154a
--- /dev/null
+++ b/db/spectrum.cbx.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0" ?>
+<LOG_ROOT>
+	<PROJECT NAME="spectrum">
+	</PROJECT>
+</LOG_ROOT>
diff --git a/db/spectrum.cmp.bpm b/db/spectrum.cmp.bpm
new file mode 100644
index 0000000..8951462
Binary files /dev/null and b/db/spectrum.cmp.bpm differ
diff --git a/db/spectrum.cmp.cdb b/db/spectrum.cmp.cdb
new file mode 100644
index 0000000..da743b4
Binary files /dev/null and b/db/spectrum.cmp.cdb differ
diff --git a/db/spectrum.cmp.hdb b/db/spectrum.cmp.hdb
new file mode 100644
index 0000000..d134eae
Binary files /dev/null and b/db/spectrum.cmp.hdb differ
diff --git a/db/spectrum.cmp.idb b/db/spectrum.cmp.idb
new file mode 100644
index 0000000..311c6e3
Binary files /dev/null and b/db/spectrum.cmp.idb differ
diff --git a/db/spectrum.cmp.logdb b/db/spectrum.cmp.logdb
new file mode 100644
index 0000000..10c46e1
--- /dev/null
+++ b/db/spectrum.cmp.logdb
@@ -0,0 +1,50 @@
+v1
+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength or Termination assignments found.,,I/O,,
+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
+IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042,
+IO_RULES_MATRIX,Total Pass,9;0;9;0;0;9;9;0;9;9;0;0;0;0;1;0;0;1;0;0;0;0;0;0;0;0;0;9;0;0,
+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Inapplicable,0;9;0;9;9;0;0;9;0;0;9;9;9;9;8;9;9;8;9;9;9;9;9;9;9;9;9;0;9;9,
+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,LED[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LED[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LED[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LED[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LED[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LED[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LED[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LED[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,CLOCK_50,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_SUMMARY,Total I/O Rules,30,
+IO_RULES_SUMMARY,Number of I/O Rules Passed,9,
+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,21,
diff --git a/db/spectrum.cmp.rdb b/db/spectrum.cmp.rdb
new file mode 100644
index 0000000..3a40804
Binary files /dev/null and b/db/spectrum.cmp.rdb differ
diff --git a/db/spectrum.cmp_merge.kpt b/db/spectrum.cmp_merge.kpt
new file mode 100644
index 0000000..1c1f058
Binary files /dev/null and b/db/spectrum.cmp_merge.kpt differ
diff --git a/db/spectrum.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd b/db/spectrum.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
new file mode 100644
index 0000000..b6c82ed
Binary files /dev/null and b/db/spectrum.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd differ
diff --git a/db/spectrum.cycloneive_io_sim_cache.45um_tt_1200mv_0c_slow.hsd b/db/spectrum.cycloneive_io_sim_cache.45um_tt_1200mv_0c_slow.hsd
new file mode 100644
index 0000000..3a5105f
Binary files /dev/null and b/db/spectrum.cycloneive_io_sim_cache.45um_tt_1200mv_0c_slow.hsd differ
diff --git a/db/spectrum.cycloneive_io_sim_cache.45um_tt_1200mv_85c_slow.hsd b/db/spectrum.cycloneive_io_sim_cache.45um_tt_1200mv_85c_slow.hsd
new file mode 100644
index 0000000..2005c89
Binary files /dev/null and b/db/spectrum.cycloneive_io_sim_cache.45um_tt_1200mv_85c_slow.hsd differ
diff --git a/db/spectrum.db_info b/db/spectrum.db_info
new file mode 100644
index 0000000..5295fd0
--- /dev/null
+++ b/db/spectrum.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+Version_Index = 318808576
+Creation_Time = Wed Mar 30 11:48:45 2022
diff --git a/db/spectrum.eda.qmsg b/db/spectrum.eda.qmsg
new file mode 100644
index 0000000..12656aa
--- /dev/null
+++ b/db/spectrum.eda.qmsg
@@ -0,0 +1,12 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648630303095 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648630303096 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 11:51:42 2022 " "Processing started: Wed Mar 30 11:51:42 2022" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648630303096 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648630303096 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648630303097 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630303387 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630303407 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_fast.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_fast.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630303428 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630303448 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630303469 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630303488 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_v_fast.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630303508 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_v.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_v.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630303527 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "352 " "Peak virtual memory: 352 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648630303559 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 11:51:43 2022 " "Processing ended: Wed Mar 30 11:51:43 2022" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648630303559 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648630303559 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648630303559 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648630303559 ""}
diff --git a/db/spectrum.fit.qmsg b/db/spectrum.fit.qmsg
new file mode 100644
index 0000000..b0460ba
--- /dev/null
+++ b/db/spectrum.fit.qmsg
@@ -0,0 +1,47 @@
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1648630290922 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "spectrum EP4CE22F17C6 " "Selected device EP4CE22F17C6 for design \"spectrum\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1648630290925 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648630290962 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648630290963 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648630290963 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1648630291034 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1648630291044 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17C6 " "Device EP4CE10F17C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648630291251 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C6 " "Device EP4CE6F17C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648630291251 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C6 " "Device EP4CE15F17C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648630291251 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1648630291251 ""}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" {  } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 275 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648630291256 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" {  } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 277 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648630291256 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" {  } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 279 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648630291256 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" {  } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 281 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648630291256 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" {  } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 283 9662 10382 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648630291256 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1648630291256 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1648630291258 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "spectrum.sdc " "Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1648630291909 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1648630291909 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1648630291911 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1648630291912 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1648630291912 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p)) " "Automatically promoted node CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G18 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648630291919 ""}  } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 270 9662 10382 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648630291919 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1648630292153 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648630292154 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648630292154 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648630292155 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648630292155 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1648630292156 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1648630292156 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1648630292156 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1648630292167 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1648630292168 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1648630292168 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS_N " "Node \"ADC_CS_N\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_CS_N" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SADDR " "Node \"ADC_SADDR\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SADDR" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCLK " "Node \"ADC_SCLK\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SCLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDAT " "Node \"ADC_SDAT\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SDAT" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_ASDO " "Node \"EPCS_ASDO\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_ASDO" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DATA0 " "Node \"EPCS_DATA0\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DATA0" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DCLK " "Node \"EPCS_DCLK\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DCLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_NCSO " "Node \"EPCS_NCSO\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_NCSO" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[0\] " "Node \"GPIO_0\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[10\] " "Node \"GPIO_0\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[11\] " "Node \"GPIO_0\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[12\] " "Node \"GPIO_0\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[13\] " "Node \"GPIO_0\[13\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[13\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[14\] " "Node \"GPIO_0\[14\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[14\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[15\] " "Node \"GPIO_0\[15\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[15\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[16\] " "Node \"GPIO_0\[16\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[16\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[17\] " "Node \"GPIO_0\[17\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[17\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[18\] " "Node \"GPIO_0\[18\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[18\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[19\] " "Node \"GPIO_0\[19\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[19\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[1\] " "Node \"GPIO_0\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[20\] " "Node \"GPIO_0\[20\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[20\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[21\] " "Node \"GPIO_0\[21\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[21\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[22\] " "Node \"GPIO_0\[22\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[22\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[23\] " "Node \"GPIO_0\[23\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[23\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[24\] " "Node \"GPIO_0\[24\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[24\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[25\] " "Node \"GPIO_0\[25\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[25\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[26\] " "Node \"GPIO_0\[26\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[26\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[27\] " "Node \"GPIO_0\[27\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[27\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[28\] " "Node \"GPIO_0\[28\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[28\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[29\] " "Node \"GPIO_0\[29\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[29\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[2\] " "Node \"GPIO_0\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[30\] " "Node \"GPIO_0\[30\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[30\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[31\] " "Node \"GPIO_0\[31\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[31\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[32\] " "Node \"GPIO_0\[32\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[32\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[33\] " "Node \"GPIO_0\[33\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[33\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[3\] " "Node \"GPIO_0\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[4\] " "Node \"GPIO_0\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[5\] " "Node \"GPIO_0\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[6\] " "Node \"GPIO_0\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[7\] " "Node \"GPIO_0\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[8\] " "Node \"GPIO_0\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[9\] " "Node \"GPIO_0\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[0\] " "Node \"GPIO_0_IN\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[1\] " "Node \"GPIO_0_IN\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[0\] " "Node \"GPIO_1\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[10\] " "Node \"GPIO_1\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[11\] " "Node \"GPIO_1\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[12\] " "Node \"GPIO_1\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[13\] " "Node \"GPIO_1\[13\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[14\] " "Node \"GPIO_1\[14\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[15\] " "Node \"GPIO_1\[15\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[16\] " "Node \"GPIO_1\[16\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[17\] " "Node \"GPIO_1\[17\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[18\] " "Node \"GPIO_1\[18\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[19\] " "Node \"GPIO_1\[19\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[1\] " "Node \"GPIO_1\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[20\] " "Node \"GPIO_1\[20\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[21\] " "Node \"GPIO_1\[21\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[22\] " "Node \"GPIO_1\[22\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[23\] " "Node \"GPIO_1\[23\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[24\] " "Node \"GPIO_1\[24\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[25\] " "Node \"GPIO_1\[25\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[26\] " "Node \"GPIO_1\[26\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[27\] " "Node \"GPIO_1\[27\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[28\] " "Node \"GPIO_1\[28\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[29\] " "Node \"GPIO_1\[29\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[2\] " "Node \"GPIO_1\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[30\] " "Node \"GPIO_1\[30\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[31\] " "Node \"GPIO_1\[31\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[32\] " "Node \"GPIO_1\[32\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[32\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[33\] " "Node \"GPIO_1\[33\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[33\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[3\] " "Node \"GPIO_1\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[4\] " "Node \"GPIO_1\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[5\] " "Node \"GPIO_1\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[6\] " "Node \"GPIO_1\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[7\] " "Node \"GPIO_1\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[8\] " "Node \"GPIO_1\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[9\] " "Node \"GPIO_1\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[0\] " "Node \"GPIO_1_IN\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[1\] " "Node \"GPIO_1_IN\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[0\] " "Node \"GPIO_2\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[10\] " "Node \"GPIO_2\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[11\] " "Node \"GPIO_2\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[12\] " "Node \"GPIO_2\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[1\] " "Node \"GPIO_2\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[2\] " "Node \"GPIO_2\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[3\] " "Node \"GPIO_2\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[4\] " "Node \"GPIO_2\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[5\] " "Node \"GPIO_2\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[6\] " "Node \"GPIO_2\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[7\] " "Node \"GPIO_2\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[8\] " "Node \"GPIO_2\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[9\] " "Node \"GPIO_2\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[0\] " "Node \"GPIO_2_IN\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[1\] " "Node \"GPIO_2_IN\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[2\] " "Node \"GPIO_2_IN\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_CS_N " "Node \"G_SENSOR_CS_N\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_CS_N" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_INT " "Node \"G_SENSOR_INT\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_INT" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1648630292180 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648630292187 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1648630293162 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648630293228 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1648630293236 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1648630293659 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648630293659 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1648630293897 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X32_Y23 X42_Y34 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X32_Y23 to location X42_Y34" {  } { { "loc" "" { Generic "/home/benny/work/fpga/projects/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X32_Y23 to location X42_Y34"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X32_Y23 to location X42_Y34"} 32 23 11 12 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1648630294466 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1648630294466 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648630294824 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1648630294824 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1648630294824 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.10 " "Total time spent on timing analysis during the Fitter is 0.10 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1648630294833 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648630294885 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648630295042 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648630295087 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648630295217 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648630295493 ""}
+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1648630295838 ""}
+{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "1 Cyclone IV E " "1 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK_50 3.3-V LVTTL R8 " "Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at R8" {  } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { CLOCK_50 } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 12 9662 10382 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648630295841 ""}  } {  } 0 169177 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1648630295841 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/projects/output_files/spectrum.fit.smsg " "Generated suppressed messages file /home/benny/work/fpga/projects/output_files/spectrum.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1648630295883 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 152 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 152 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "588 " "Peak virtual memory: 588 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648630296061 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 11:51:36 2022 " "Processing ended: Wed Mar 30 11:51:36 2022" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648630296061 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648630296061 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648630296061 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1648630296061 ""}
diff --git a/db/spectrum.hier_info b/db/spectrum.hier_info
new file mode 100644
index 0000000..f3679a9
--- /dev/null
+++ b/db/spectrum.hier_info
@@ -0,0 +1,47 @@
+|spectrum
+CLOCK_50 => LED[0]~reg0.CLK
+CLOCK_50 => LED[1]~reg0.CLK
+CLOCK_50 => LED[2]~reg0.CLK
+CLOCK_50 => LED[3]~reg0.CLK
+CLOCK_50 => LED[4]~reg0.CLK
+CLOCK_50 => LED[5]~reg0.CLK
+CLOCK_50 => LED[6]~reg0.CLK
+CLOCK_50 => LED[7]~reg0.CLK
+CLOCK_50 => counter[0].CLK
+CLOCK_50 => counter[1].CLK
+CLOCK_50 => counter[2].CLK
+CLOCK_50 => counter[3].CLK
+CLOCK_50 => counter[4].CLK
+CLOCK_50 => counter[5].CLK
+CLOCK_50 => counter[6].CLK
+CLOCK_50 => counter[7].CLK
+CLOCK_50 => counter[8].CLK
+CLOCK_50 => counter[9].CLK
+CLOCK_50 => counter[10].CLK
+CLOCK_50 => counter[11].CLK
+CLOCK_50 => counter[12].CLK
+CLOCK_50 => counter[13].CLK
+CLOCK_50 => counter[14].CLK
+CLOCK_50 => counter[15].CLK
+CLOCK_50 => counter[16].CLK
+CLOCK_50 => counter[17].CLK
+CLOCK_50 => counter[18].CLK
+CLOCK_50 => counter[19].CLK
+CLOCK_50 => counter[20].CLK
+CLOCK_50 => counter[21].CLK
+CLOCK_50 => counter[22].CLK
+CLOCK_50 => counter[23].CLK
+CLOCK_50 => counter[24].CLK
+CLOCK_50 => counter[25].CLK
+CLOCK_50 => counter[26].CLK
+CLOCK_50 => counter[27].CLK
+LED[0] <= LED[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+LED[1] <= LED[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+LED[2] <= LED[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+LED[3] <= LED[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+LED[4] <= LED[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+LED[5] <= LED[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+LED[6] <= LED[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+LED[7] <= LED[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
diff --git a/db/spectrum.hif b/db/spectrum.hif
new file mode 100644
index 0000000..6fdc03c
Binary files /dev/null and b/db/spectrum.hif differ
diff --git a/db/spectrum.ipinfo b/db/spectrum.ipinfo
new file mode 100644
index 0000000..b19e3be
Binary files /dev/null and b/db/spectrum.ipinfo differ
diff --git a/db/spectrum.lpc.html b/db/spectrum.lpc.html
new file mode 100644
index 0000000..fbc5ab5
--- /dev/null
+++ b/db/spectrum.lpc.html
@@ -0,0 +1,18 @@
+<TABLE>
+<TR  bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+</TABLE>
diff --git a/db/spectrum.lpc.rdb b/db/spectrum.lpc.rdb
new file mode 100644
index 0000000..45b47e5
Binary files /dev/null and b/db/spectrum.lpc.rdb differ
diff --git a/db/spectrum.lpc.txt b/db/spectrum.lpc.txt
new file mode 100644
index 0000000..a8bb51f
--- /dev/null
+++ b/db/spectrum.lpc.txt
@@ -0,0 +1,5 @@
++--------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                     ;
++--------------------------------------------------------------------------------+
++--------------------------------------------------------------------------------+
+
diff --git a/db/spectrum.map.ammdb b/db/spectrum.map.ammdb
new file mode 100644
index 0000000..e93ac1a
Binary files /dev/null and b/db/spectrum.map.ammdb differ
diff --git a/db/spectrum.map.bpm b/db/spectrum.map.bpm
new file mode 100644
index 0000000..8495e25
Binary files /dev/null and b/db/spectrum.map.bpm differ
diff --git a/db/spectrum.map.cdb b/db/spectrum.map.cdb
new file mode 100644
index 0000000..3231382
Binary files /dev/null and b/db/spectrum.map.cdb differ
diff --git a/db/spectrum.map.hdb b/db/spectrum.map.hdb
new file mode 100644
index 0000000..0b7898d
Binary files /dev/null and b/db/spectrum.map.hdb differ
diff --git a/db/spectrum.map.kpt b/db/spectrum.map.kpt
new file mode 100644
index 0000000..d873764
Binary files /dev/null and b/db/spectrum.map.kpt differ
diff --git a/db/spectrum.map.logdb b/db/spectrum.map.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/db/spectrum.map.logdb
@@ -0,0 +1 @@
+v1
diff --git a/db/spectrum.map.qmsg b/db/spectrum.map.qmsg
new file mode 100644
index 0000000..ddc7b33
--- /dev/null
+++ b/db/spectrum.map.qmsg
@@ -0,0 +1,12 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648630288558 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648630288559 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 11:51:28 2022 " "Processing started: Wed Mar 30 11:51:28 2022" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648630288559 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648630288559 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum " "Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648630288559 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648630288726 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spectrum.v 1 1 " "Found 1 design units, including 1 entities, in source file spectrum.v" { { "Info" "ISGN_ENTITY_NAME" "1 spectrum " "Found entity 1: spectrum" {  } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648630288788 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648630288788 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "spectrum " "Elaborating entity \"spectrum\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1648630288838 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 28 spectrum.v(10) " "Verilog HDL assignment warning at spectrum.v(10): truncated value with size 32 to match size of target (28)" {  } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 10 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1648630288840 "|spectrum"}
+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[7\] GND " "Pin \"LED\[7\]\" is stuck at GND" {  } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 8 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648630289171 "|spectrum|LED[7]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1648630289171 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1648630289264 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1648630289457 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648630289457 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "44 " "Implemented 44 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Implemented 1 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1648630289496 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1648630289496 ""} { "Info" "ICUT_CUT_TM_LCELLS" "35 " "Implemented 35 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1648630289496 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1648630289496 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "388 " "Peak virtual memory: 388 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648630289503 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 11:51:29 2022 " "Processing ended: Wed Mar 30 11:51:29 2022" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648630289503 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648630289503 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648630289503 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648630289503 ""}
diff --git a/db/spectrum.map.rdb b/db/spectrum.map.rdb
new file mode 100644
index 0000000..3765484
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diff --git a/db/spectrum.map_bb.cdb b/db/spectrum.map_bb.cdb
new file mode 100644
index 0000000..16a177a
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diff --git a/db/spectrum.map_bb.hdb b/db/spectrum.map_bb.hdb
new file mode 100644
index 0000000..0af104d
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diff --git a/db/spectrum.map_bb.logdb b/db/spectrum.map_bb.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/db/spectrum.map_bb.logdb
@@ -0,0 +1 @@
+v1
diff --git a/db/spectrum.pplq.rdb b/db/spectrum.pplq.rdb
new file mode 100644
index 0000000..9ea6ac9
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diff --git a/db/spectrum.pre_map.hdb b/db/spectrum.pre_map.hdb
new file mode 100644
index 0000000..2eee234
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diff --git a/db/spectrum.pti_db_list.ddb b/db/spectrum.pti_db_list.ddb
new file mode 100644
index 0000000..6c4406c
Binary files /dev/null and b/db/spectrum.pti_db_list.ddb differ
diff --git a/db/spectrum.quiproj.1130762.rdr.flock b/db/spectrum.quiproj.1130762.rdr.flock
new file mode 100644
index 0000000..e69de29
diff --git a/db/spectrum.root_partition.map.reg_db.cdb b/db/spectrum.root_partition.map.reg_db.cdb
new file mode 100644
index 0000000..8cd8fb1
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diff --git a/db/spectrum.routing.rdb b/db/spectrum.routing.rdb
new file mode 100644
index 0000000..1b0ac4f
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diff --git a/db/spectrum.rtlv.hdb b/db/spectrum.rtlv.hdb
new file mode 100644
index 0000000..46b0924
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diff --git a/db/spectrum.rtlv_sg.cdb b/db/spectrum.rtlv_sg.cdb
new file mode 100644
index 0000000..bf8d2f6
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diff --git a/db/spectrum.rtlv_sg_swap.cdb b/db/spectrum.rtlv_sg_swap.cdb
new file mode 100644
index 0000000..c08142b
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diff --git a/db/spectrum.sgdiff.cdb b/db/spectrum.sgdiff.cdb
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index 0000000..484ea9a
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diff --git a/db/spectrum.sgdiff.hdb b/db/spectrum.sgdiff.hdb
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index 0000000..2087b36
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diff --git a/db/spectrum.sld_design_entry.sci b/db/spectrum.sld_design_entry.sci
new file mode 100644
index 0000000..7ef0f30
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diff --git a/db/spectrum.sld_design_entry_dsc.sci b/db/spectrum.sld_design_entry_dsc.sci
new file mode 100644
index 0000000..7ef0f30
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diff --git a/db/spectrum.smart_action.txt b/db/spectrum.smart_action.txt
new file mode 100644
index 0000000..c8e8a13
--- /dev/null
+++ b/db/spectrum.smart_action.txt
@@ -0,0 +1 @@
+DONE
diff --git a/db/spectrum.sta.qmsg b/db/spectrum.sta.qmsg
new file mode 100644
index 0000000..a39d09c
--- /dev/null
+++ b/db/spectrum.sta.qmsg
@@ -0,0 +1,42 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648630300061 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300062 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 11:51:39 2022 " "Processing started: Wed Mar 30 11:51:39 2022" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648630300062 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648630300062 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta spectrum -c spectrum " "Command: quartus_sta spectrum -c spectrum" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648630300062 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1648630300090 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648630300188 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648630300189 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648630300231 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648630300231 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "spectrum.sdc " "Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1648630300423 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1648630300423 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300424 ""}  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300424 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1648630300550 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300550 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1648630300551 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1648630300556 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648630300564 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648630300564 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.606 " "Worst-case setup slack is -1.606" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300565 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300565 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.606             -30.234 CLOCK_50  " "   -1.606             -30.234 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300565 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630300565 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.360 " "Worst-case hold slack is 0.360" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300566 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300566 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.360               0.000 CLOCK_50  " "    0.360               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300566 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630300566 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648630300566 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648630300567 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300567 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300567 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000             -38.000 CLOCK_50  " "   -3.000             -38.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300567 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630300567 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648630300582 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1648630300605 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1648630300970 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300986 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648630300988 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648630300988 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.275 " "Worst-case setup slack is -1.275" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300989 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300989 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.275             -22.690 CLOCK_50  " "   -1.275             -22.690 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300989 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630300989 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.319 " "Worst-case hold slack is 0.319" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300990 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300990 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.319               0.000 CLOCK_50  " "    0.319               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300990 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630300990 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648630300991 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648630300992 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300993 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300993 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000             -38.000 CLOCK_50  " "   -3.000             -38.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300993 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630300993 ""}
+{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648630301008 ""}
+{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." {  } {  } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648630301128 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648630301129 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648630301129 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.500 " "Worst-case setup slack is -0.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630301130 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630301130 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.500              -4.764 CLOCK_50  " "   -0.500              -4.764 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630301130 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630301130 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.193 " "Worst-case hold slack is 0.193" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630301132 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630301132 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.193               0.000 CLOCK_50  " "    0.193               0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630301132 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630301132 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648630301133 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648630301135 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630301136 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630301136 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000             -48.277 CLOCK_50  " "   -3.000             -48.277 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630301136 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630301136 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648630301431 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648630301431 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "412 " "Peak virtual memory: 412 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648630301464 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 11:51:41 2022 " "Processing ended: Wed Mar 30 11:51:41 2022" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648630301464 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648630301464 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648630301464 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648630301464 ""}
diff --git a/db/spectrum.sta.rdb b/db/spectrum.sta.rdb
new file mode 100644
index 0000000..c0e5c15
Binary files /dev/null and b/db/spectrum.sta.rdb differ
diff --git a/db/spectrum.sta_cmp.6_slow_1200mv_85c.tdb b/db/spectrum.sta_cmp.6_slow_1200mv_85c.tdb
new file mode 100644
index 0000000..274da40
Binary files /dev/null and b/db/spectrum.sta_cmp.6_slow_1200mv_85c.tdb differ
diff --git a/db/spectrum.tis_db_list.ddb b/db/spectrum.tis_db_list.ddb
new file mode 100644
index 0000000..33ec2f6
Binary files /dev/null and b/db/spectrum.tis_db_list.ddb differ
diff --git a/db/spectrum.tiscmp.fast_1200mv_0c.ddb b/db/spectrum.tiscmp.fast_1200mv_0c.ddb
new file mode 100644
index 0000000..e0b01cf
Binary files /dev/null and b/db/spectrum.tiscmp.fast_1200mv_0c.ddb differ
diff --git a/db/spectrum.tiscmp.slow_1200mv_0c.ddb b/db/spectrum.tiscmp.slow_1200mv_0c.ddb
new file mode 100644
index 0000000..f2ac133
Binary files /dev/null and b/db/spectrum.tiscmp.slow_1200mv_0c.ddb differ
diff --git a/db/spectrum.tiscmp.slow_1200mv_85c.ddb b/db/spectrum.tiscmp.slow_1200mv_85c.ddb
new file mode 100644
index 0000000..503df29
Binary files /dev/null and b/db/spectrum.tiscmp.slow_1200mv_85c.ddb differ
diff --git a/db/spectrum.tmw_info b/db/spectrum.tmw_info
new file mode 100644
index 0000000..b354b94
--- /dev/null
+++ b/db/spectrum.tmw_info
@@ -0,0 +1,2 @@
+start_analysis_synthesis:s:00:00:03-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
diff --git a/db/spectrum.vpr.ammdb b/db/spectrum.vpr.ammdb
new file mode 100644
index 0000000..fefbc11
Binary files /dev/null and b/db/spectrum.vpr.ammdb differ
diff --git a/incremental_db/README b/incremental_db/README
new file mode 100644
index 0000000..9f62dcd
--- /dev/null
+++ b/incremental_db/README
@@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used.  To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+
diff --git a/incremental_db/compiled_partitions/spectrum.db_info b/incremental_db/compiled_partitions/spectrum.db_info
new file mode 100644
index 0000000..6ae15c3
--- /dev/null
+++ b/incremental_db/compiled_partitions/spectrum.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+Version_Index = 318808576
+Creation_Time = Wed Mar 30 11:47:24 2022
diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.ammdb b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.ammdb
new file mode 100644
index 0000000..9f99b48
Binary files /dev/null and b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.ammdb differ
diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.cdb b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.cdb
new file mode 100644
index 0000000..68bf3f2
Binary files /dev/null and b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.cdb differ
diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.dfp b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.dfp
new file mode 100644
index 0000000..b1c67d6
Binary files /dev/null and b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.dfp differ
diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.hdb b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.hdb
new file mode 100644
index 0000000..4ff4db2
Binary files /dev/null and b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.hdb differ
diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.logdb b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.logdb
@@ -0,0 +1 @@
+v1
diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.rcfdb b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.rcfdb
new file mode 100644
index 0000000..afab8d8
Binary files /dev/null and b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.rcfdb differ
diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.cdb b/incremental_db/compiled_partitions/spectrum.root_partition.map.cdb
new file mode 100644
index 0000000..737e0b1
Binary files /dev/null and b/incremental_db/compiled_partitions/spectrum.root_partition.map.cdb differ
diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.dpi b/incremental_db/compiled_partitions/spectrum.root_partition.map.dpi
new file mode 100644
index 0000000..66bdb56
Binary files /dev/null and b/incremental_db/compiled_partitions/spectrum.root_partition.map.dpi differ
diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.cdb b/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.cdb
new file mode 100644
index 0000000..cde2795
Binary files /dev/null and b/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.cdb differ
diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hb_info b/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hb_info
new file mode 100644
index 0000000..8210c55
Binary files /dev/null and b/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hb_info differ
diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hdb b/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hdb
new file mode 100644
index 0000000..1a2c528
Binary files /dev/null and b/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hdb differ
diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.sig b/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.sig
new file mode 100644
index 0000000..6c0af65
--- /dev/null
+++ b/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.sig
@@ -0,0 +1 @@
+c5eb7f6cdd530884c3b884e0a3668ea4
\ No newline at end of file
diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.hdb b/incremental_db/compiled_partitions/spectrum.root_partition.map.hdb
new file mode 100644
index 0000000..6be872a
Binary files /dev/null and b/incremental_db/compiled_partitions/spectrum.root_partition.map.hdb differ
diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.kpt b/incremental_db/compiled_partitions/spectrum.root_partition.map.kpt
new file mode 100644
index 0000000..2a4fcb7
Binary files /dev/null and b/incremental_db/compiled_partitions/spectrum.root_partition.map.kpt differ
diff --git a/output_files/spectrum.asm.rpt b/output_files/spectrum.asm.rpt
new file mode 100644
index 0000000..493e463
--- /dev/null
+++ b/output_files/spectrum.asm.rpt
@@ -0,0 +1,186 @@
+Assembler report for spectrum
+Wed Mar 30 11:51:38 2022
+Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: spectrum.sof
+  6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Wed Mar 30 11:51:38 2022 ;
+; Revision Name         ; spectrum                              ;
+; Top-level Entity Name ; spectrum                              ;
+; Family                ; Cyclone IV E                          ;
+; Device                ; EP4CE22F17C6                          ;
++-----------------------+---------------------------------------+
+
+
++--------------------------------------------------------------------------------+
+; Assembler Settings                                                             ;
++--------------------------------------------------------------------------------+
+Option        : Use smart compilation
+Setting       : Off
+Default Value : Off
+
+Option        : Enable parallel Assembler and TimeQuest Timing Analyzer during compilation
+Setting       : On
+Default Value : On
+
+Option        : Enable compact report table
+Setting       : Off
+Default Value : Off
+
+Option        : Generate compressed bitstreams
+Setting       : On
+Default Value : On
+
+Option        : Compression mode
+Setting       : Off
+Default Value : Off
+
+Option        : Clock source for configuration device
+Setting       : Internal
+Default Value : Internal
+
+Option        : Clock frequency of the configuration device
+Setting       : 10 MHZ
+Default Value : 10 MHz
+
+Option        : Divide clock frequency by
+Setting       : 1
+Default Value : 1
+
+Option        : Auto user code
+Setting       : On
+Default Value : On
+
+Option        : Use configuration device
+Setting       : Off
+Default Value : Off
+
+Option        : Configuration device
+Setting       : Auto
+Default Value : Auto
+
+Option        : Configuration device auto user code
+Setting       : Off
+Default Value : Off
+
+Option        : Generate Tabular Text File (.ttf) For Target Device
+Setting       : Off
+Default Value : Off
+
+Option        : Generate Raw Binary File (.rbf) For Target Device
+Setting       : Off
+Default Value : Off
+
+Option        : Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device
+Setting       : Off
+Default Value : Off
+
+Option        : Hexadecimal Output File start address
+Setting       : 0
+Default Value : 0
+
+Option        : Hexadecimal Output File count direction
+Setting       : Up
+Default Value : Up
+
+Option        : Release clears before tri-states
+Setting       : Off
+Default Value : Off
+
+Option        : Auto-restart configuration after error
+Setting       : On
+Default Value : On
+
+Option        : Enable OCT_DONE
+Setting       : Off
+Default Value : Off
+
+Option        : Generate Serial Vector Format File (.svf) for Target Device
+Setting       : Off
+Default Value : Off
+
+Option        : Generate a JEDEC STAPL Format File (.jam) for Target Device
+Setting       : Off
+Default Value : Off
+
+Option        : Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device
+Setting       : Off
+Default Value : Off
+
+Option        : Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device
+Setting       : On
+Default Value : On
++--------------------------------------------------------------------------------+
+
+
+
++---------------------------+
+; Assembler Generated Files ;
++---------------------------+
+; File Name                 ;
++---------------------------+
+; spectrum.sof              ;
++---------------------------+
+
+
++----------------------------------------+
+; Assembler Device Options: spectrum.sof ;
++----------------+-----------------------+
+; Option         ; Setting               ;
++----------------+-----------------------+
+; Device         ; EP4CE22F17C6          ;
+; JTAG usercode  ; 0x00138B42            ;
+; Checksum       ; 0x00138B42            ;
++----------------+-----------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus II 32-bit Assembler
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+    Info: Processing started: Wed Mar 30 11:51:37 2022
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum
+Info (115031): Writing out detailed assembly data for power analysis
+Info (115030): Assembler is generating device programming files
+Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 389 megabytes
+    Info: Processing ended: Wed Mar 30 11:51:38 2022
+    Info: Elapsed time: 00:00:01
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/output_files/spectrum.cdf b/output_files/spectrum.cdf
new file mode 100644
index 0000000..2d670df
--- /dev/null
+++ b/output_files/spectrum.cdf
@@ -0,0 +1,13 @@
+/* Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition */
+JedecChain;
+	FileRevision(JESD32A);
+	DefaultMfr(6E);
+
+	P ActionCode(Cfg)
+		Device PartName(EP4CE22F17) Path("/home/benny/work/fpga/projects/output_files/") File("spectrum.sof") MfrSpec(OpMask(1));
+
+ChainEnd;
+
+AlteraBegin;
+	ChainType(JTAG);
+AlteraEnd;
diff --git a/output_files/spectrum.done b/output_files/spectrum.done
new file mode 100644
index 0000000..01312d4
--- /dev/null
+++ b/output_files/spectrum.done
@@ -0,0 +1 @@
+Wed Mar 30 11:51:43 2022
diff --git a/output_files/spectrum.eda.rpt b/output_files/spectrum.eda.rpt
new file mode 100644
index 0000000..db555f7
--- /dev/null
+++ b/output_files/spectrum.eda.rpt
@@ -0,0 +1,107 @@
+EDA Netlist Writer report for spectrum
+Wed Mar 30 11:51:43 2022
+Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. EDA Netlist Writer Summary
+  3. Simulation Settings
+  4. Simulation Generated Files
+  5. EDA Netlist Writer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++-------------------------------------------------------------------+
+; EDA Netlist Writer Summary                                        ;
++---------------------------+---------------------------------------+
+; EDA Netlist Writer Status ; Successful - Wed Mar 30 11:51:43 2022 ;
+; Revision Name             ; spectrum                              ;
+; Top-level Entity Name     ; spectrum                              ;
+; Family                    ; Cyclone IV E                          ;
+; Simulation Files Creation ; Successful                            ;
++---------------------------+---------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Simulation Settings                                                                                                           ;
++---------------------------------------------------------------------------------------------------+---------------------------+
+; Option                                                                                            ; Setting                   ;
++---------------------------------------------------------------------------------------------------+---------------------------+
+; Tool Name                                                                                         ; ModelSim-Altera (Verilog) ;
+; Generate netlist for functional simulation only                                                   ; Off                       ;
+; Time scale                                                                                        ; 1 ps                      ;
+; Truncate long hierarchy paths                                                                     ; Off                       ;
+; Map illegal HDL characters                                                                        ; Off                       ;
+; Flatten buses into individual nodes                                                               ; Off                       ;
+; Maintain hierarchy                                                                                ; Off                       ;
+; Bring out device-wide set/reset signals as ports                                                  ; Off                       ;
+; Enable glitch filtering                                                                           ; Off                       ;
+; Do not write top level VHDL entity                                                                ; Off                       ;
+; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off                       ;
+; Architecture name in VHDL output netlist                                                          ; structure                 ;
+; Generate third-party EDA tool command script for RTL functional simulation                        ; Off                       ;
+; Generate third-party EDA tool command script for gate-level simulation                            ; Off                       ;
++---------------------------------------------------------------------------------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------+
+; Simulation Generated Files                                                           ;
++--------------------------------------------------------------------------------------+
+; Generated Files                                                                      ;
++--------------------------------------------------------------------------------------+
+; /home/benny/work/fpga/projects/simulation/modelsim/spectrum_6_1200mv_85c_slow.vo     ;
+; /home/benny/work/fpga/projects/simulation/modelsim/spectrum_6_1200mv_0c_slow.vo      ;
+; /home/benny/work/fpga/projects/simulation/modelsim/spectrum_min_1200mv_0c_fast.vo    ;
+; /home/benny/work/fpga/projects/simulation/modelsim/spectrum.vo                       ;
+; /home/benny/work/fpga/projects/simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo  ;
+; /home/benny/work/fpga/projects/simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo   ;
+; /home/benny/work/fpga/projects/simulation/modelsim/spectrum_min_1200mv_0c_v_fast.sdo ;
+; /home/benny/work/fpga/projects/simulation/modelsim/spectrum_v.sdo                    ;
++--------------------------------------------------------------------------------------+
+
+
++-----------------------------+
+; EDA Netlist Writer Messages ;
++-----------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 32-bit EDA Netlist Writer
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+    Info: Processing started: Wed Mar 30 11:51:42 2022
+Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum
+Info (204019): Generated file spectrum_6_1200mv_85c_slow.vo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file spectrum_6_1200mv_0c_slow.vo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file spectrum_min_1200mv_0c_fast.vo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file spectrum.vo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file spectrum_v.sdo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool
+Info: Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 352 megabytes
+    Info: Processing ended: Wed Mar 30 11:51:43 2022
+    Info: Elapsed time: 00:00:01
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/output_files/spectrum.fit.rpt b/output_files/spectrum.fit.rpt
new file mode 100644
index 0000000..94138b6
--- /dev/null
+++ b/output_files/spectrum.fit.rpt
@@ -0,0 +1,7531 @@
+Fitter report for spectrum
+Wed Mar 30 11:51:35 2022
+Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Fitter Summary
+  3. Fitter Settings
+  4. Parallel Compilation
+  5. I/O Assignment Warnings
+  6. Ignored Assignments
+  7. Incremental Compilation Preservation Summary
+  8. Incremental Compilation Partition Settings
+  9. Incremental Compilation Placement Preservation
+ 10. Pin-Out File
+ 11. Fitter Resource Usage Summary
+ 12. Fitter Partition Statistics
+ 13. Input Pins
+ 14. Output Pins
+ 15. Dual Purpose and Dedicated Pins
+ 16. I/O Bank Usage
+ 17. All Package Pins
+ 18. Fitter Resource Utilization by Entity
+ 19. Delay Chain Summary
+ 20. Pad To Core Delay Chain Fanout
+ 21. Control Signals
+ 22. Global & Other Fast Signals
+ 23. Non-Global High Fan-Out Signals
+ 24. Routing Usage Summary
+ 25. LAB Logic Elements
+ 26. LAB-wide Signals
+ 27. LAB Signals Sourced
+ 28. LAB Signals Sourced Out
+ 29. LAB Distinct Inputs
+ 30. I/O Rules Summary
+ 31. I/O Rules Details
+ 32. I/O Rules Matrix
+ 33. Fitter Device Options
+ 34. Operating Settings and Conditions
+ 35. Fitter Messages
+ 36. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------+
+; Fitter Summary                                                                  ;
++------------------------------------+--------------------------------------------+
+; Fitter Status                      ; Successful - Wed Mar 30 11:51:35 2022      ;
+; Quartus II 32-bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
+; Revision Name                      ; spectrum                                   ;
+; Top-level Entity Name              ; spectrum                                   ;
+; Family                             ; Cyclone IV E                               ;
+; Device                             ; EP4CE22F17C6                               ;
+; Timing Models                      ; Final                                      ;
+; Total logic elements               ; 35 / 22,320 ( < 1 % )                      ;
+;     Total combinational functions  ; 28 / 22,320 ( < 1 % )                      ;
+;     Dedicated logic registers      ; 35 / 22,320 ( < 1 % )                      ;
+; Total registers                    ; 35                                         ;
+; Total pins                         ; 9 / 154 ( 6 % )                            ;
+; Total virtual pins                 ; 0                                          ;
+; Total memory bits                  ; 0 / 608,256 ( 0 % )                        ;
+; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % )                            ;
+; Total PLLs                         ; 0 / 4 ( 0 % )                              ;
++------------------------------------+--------------------------------------------+
+
+
++--------------------------------------------------------------------------------+
+; Fitter Settings                                                                ;
++--------------------------------------------------------------------------------+
+Option        : Device
+Setting       : EP4CE22F17C6
+Default Value : 
+
+Option        : Nominal Core Supply Voltage
+Setting       : 1.2V
+Default Value : 
+
+Option        : Minimum Core Junction Temperature
+Setting       : 0
+Default Value : 
+
+Option        : Maximum Core Junction Temperature
+Setting       : 85
+Default Value : 
+
+Option        : Fit Attempts to Skip
+Setting       : 0
+Default Value : 0.0
+
+Option        : Device I/O Standard
+Setting       : 2.5 V
+Default Value : 
+
+Option        : Use smart compilation
+Setting       : Off
+Default Value : Off
+
+Option        : Enable parallel Assembler and TimeQuest Timing Analyzer during compilation
+Setting       : On
+Default Value : On
+
+Option        : Enable compact report table
+Setting       : Off
+Default Value : Off
+
+Option        : Auto Merge PLLs
+Setting       : On
+Default Value : On
+
+Option        : Router Timing Optimization Level
+Setting       : Normal
+Default Value : Normal
+
+Option        : Perform Clocking Topology Analysis During Routing
+Setting       : Off
+Default Value : Off
+
+Option        : Placement Effort Multiplier
+Setting       : 1.0
+Default Value : 1.0
+
+Option        : Router Effort Multiplier
+Setting       : 1.0
+Default Value : 1.0
+
+Option        : Optimize Hold Timing
+Setting       : All Paths
+Default Value : All Paths
+
+Option        : Optimize Multi-Corner Timing
+Setting       : On
+Default Value : On
+
+Option        : PowerPlay Power Optimization
+Setting       : Normal compilation
+Default Value : Normal compilation
+
+Option        : SSN Optimization
+Setting       : Off
+Default Value : Off
+
+Option        : Optimize Timing
+Setting       : Normal compilation
+Default Value : Normal compilation
+
+Option        : Optimize Timing for ECOs
+Setting       : Off
+Default Value : Off
+
+Option        : Regenerate full fit report during ECO compiles
+Setting       : Off
+Default Value : Off
+
+Option        : Optimize IOC Register Placement for Timing
+Setting       : Normal
+Default Value : Normal
+
+Option        : Limit to One Fitting Attempt
+Setting       : Off
+Default Value : Off
+
+Option        : Final Placement Optimizations
+Setting       : Automatically
+Default Value : Automatically
+
+Option        : Fitter Aggressive Routability Optimizations
+Setting       : Automatically
+Default Value : Automatically
+
+Option        : Fitter Initial Placement Seed
+Setting       : 1
+Default Value : 1
+
+Option        : PCI I/O
+Setting       : Off
+Default Value : Off
+
+Option        : Weak Pull-Up Resistor
+Setting       : Off
+Default Value : Off
+
+Option        : Enable Bus-Hold Circuitry
+Setting       : Off
+Default Value : Off
+
+Option        : Auto Packed Registers
+Setting       : Auto
+Default Value : Auto
+
+Option        : Auto Delay Chains
+Setting       : On
+Default Value : On
+
+Option        : Auto Delay Chains for High Fanout Input Pins
+Setting       : Off
+Default Value : Off
+
+Option        : Allow Single-ended Buffer for Differential-XSTL Input
+Setting       : Off
+Default Value : Off
+
+Option        : Treat Bidirectional Pin as Output Pin
+Setting       : Off
+Default Value : Off
+
+Option        : Perform Physical Synthesis for Combinational Logic for Fitting
+Setting       : Off
+Default Value : Off
+
+Option        : Perform Physical Synthesis for Combinational Logic for Performance
+Setting       : Off
+Default Value : Off
+
+Option        : Perform Register Duplication for Performance
+Setting       : Off
+Default Value : Off
+
+Option        : Perform Logic to Memory Mapping for Fitting
+Setting       : Off
+Default Value : Off
+
+Option        : Perform Register Retiming for Performance
+Setting       : Off
+Default Value : Off
+
+Option        : Perform Asynchronous Signal Pipelining
+Setting       : Off
+Default Value : Off
+
+Option        : Fitter Effort
+Setting       : Auto Fit
+Default Value : Auto Fit
+
+Option        : Physical Synthesis Effort Level
+Setting       : Normal
+Default Value : Normal
+
+Option        : Logic Cell Insertion - Logic Duplication
+Setting       : Auto
+Default Value : Auto
+
+Option        : Auto Register Duplication
+Setting       : Auto
+Default Value : Auto
+
+Option        : Auto Global Clock
+Setting       : On
+Default Value : On
+
+Option        : Auto Global Register Control Signals
+Setting       : On
+Default Value : On
+
+Option        : Reserve all unused pins
+Setting       : As input tri-stated with weak pull-up
+Default Value : As input tri-stated with weak pull-up
+
+Option        : Synchronizer Identification
+Setting       : Off
+Default Value : Off
+
+Option        : Enable Beneficial Skew Optimization
+Setting       : On
+Default Value : On
+
+Option        : Optimize Design for Metastability
+Setting       : On
+Default Value : On
+
+Option        : Force Fitter to Avoid Periphery Placement Warnings
+Setting       : Off
+Default Value : Off
+
+Option        : Enable input tri-state on active configuration pins in user mode
+Setting       : Off
+Default Value : Off
++--------------------------------------------------------------------------------+
+
+
+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation                ;
++----------------------------+--------+
+; Processors                 ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 12     ;
+; Maximum allowed            ; 1      ;
++----------------------------+--------+
+
+
++-----------------------------------+
+; I/O Assignment Warnings           ;
++----------+------------------------+
+; Pin Name ; Reason                 ;
++----------+------------------------+
+; LED[0]   ; Missing drive strength ;
+; LED[1]   ; Missing drive strength ;
+; LED[2]   ; Missing drive strength ;
+; LED[3]   ; Missing drive strength ;
+; LED[4]   ; Missing drive strength ;
+; LED[5]   ; Missing drive strength ;
+; LED[6]   ; Missing drive strength ;
+; LED[7]   ; Missing drive strength ;
++----------+------------------------+
+
+
++--------------------------------------------------------------------------------+
+; Ignored Assignments                                                            ;
++--------------------------------------------------------------------------------+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : ADC_CS_N
+Ignored Value  : PIN_A10
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : ADC_SADDR
+Ignored Value  : PIN_B10
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : ADC_SCLK
+Ignored Value  : PIN_B14
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : ADC_SDAT
+Ignored Value  : PIN_A9
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : DRAM_ADDR[0]
+Ignored Value  : PIN_P2
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : DRAM_ADDR[10]
+Ignored Value  : PIN_N2
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : DRAM_ADDR[11]
+Ignored Value  : PIN_N1
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : DRAM_ADDR[12]
+Ignored Value  : PIN_L4
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : DRAM_ADDR[1]
+Ignored Value  : PIN_N5
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : DRAM_ADDR[2]
+Ignored Value  : PIN_N6
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : DRAM_ADDR[3]
+Ignored Value  : PIN_M8
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : DRAM_ADDR[4]
+Ignored Value  : PIN_P8
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : DRAM_ADDR[5]
+Ignored Value  : PIN_T7
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : DRAM_ADDR[6]
+Ignored Value  : PIN_N8
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : DRAM_ADDR[7]
+Ignored Value  : PIN_T6
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : DRAM_ADDR[8]
+Ignored Value  : PIN_R1
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : DRAM_ADDR[9]
+Ignored Value  : PIN_P1
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : DRAM_BA[0]
+Ignored Value  : PIN_M7
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : DRAM_BA[1]
+Ignored Value  : PIN_M6
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : DRAM_CAS_N
+Ignored Value  : PIN_L1
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : DRAM_CKE
+Ignored Value  : PIN_L7
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : DRAM_CLK
+Ignored Value  : PIN_R4
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : DRAM_CS_N
+Ignored Value  : PIN_P6
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : DRAM_DQM[0]
+Ignored Value  : PIN_R6
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : DRAM_DQM[1]
+Ignored Value  : PIN_T5
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : DRAM_DQ[0]
+Ignored Value  : PIN_G2
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : DRAM_DQ[10]
+Ignored Value  : PIN_T3
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : DRAM_DQ[11]
+Ignored Value  : PIN_R3
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : DRAM_DQ[12]
+Ignored Value  : PIN_R5
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : DRAM_DQ[13]
+Ignored Value  : PIN_P3
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : DRAM_DQ[14]
+Ignored Value  : PIN_N3
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : DRAM_DQ[15]
+Ignored Value  : PIN_K1
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : DRAM_DQ[1]
+Ignored Value  : PIN_G1
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : DRAM_DQ[2]
+Ignored Value  : PIN_L8
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : DRAM_DQ[3]
+Ignored Value  : PIN_K5
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : DRAM_DQ[4]
+Ignored Value  : PIN_K2
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : DRAM_DQ[5]
+Ignored Value  : PIN_J2
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : DRAM_DQ[6]
+Ignored Value  : PIN_J1
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : DRAM_DQ[7]
+Ignored Value  : PIN_R7
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : DRAM_DQ[8]
+Ignored Value  : PIN_T4
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : DRAM_DQ[9]
+Ignored Value  : PIN_T2
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : DRAM_RAS_N
+Ignored Value  : PIN_L2
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : DRAM_WE_N
+Ignored Value  : PIN_C2
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : EPCS_ASDO
+Ignored Value  : PIN_C1
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : EPCS_DATA0
+Ignored Value  : PIN_H2
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : EPCS_DCLK
+Ignored Value  : PIN_H1
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : EPCS_NCSO
+Ignored Value  : PIN_D2
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_0[0]
+Ignored Value  : PIN_D3
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_0[10]
+Ignored Value  : PIN_B6
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_0[11]
+Ignored Value  : PIN_A6
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_0[12]
+Ignored Value  : PIN_B7
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_0[13]
+Ignored Value  : PIN_D6
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_0[14]
+Ignored Value  : PIN_A7
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_0[15]
+Ignored Value  : PIN_C6
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_0[16]
+Ignored Value  : PIN_C8
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_0[17]
+Ignored Value  : PIN_E6
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_0[18]
+Ignored Value  : PIN_E7
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_0[19]
+Ignored Value  : PIN_D8
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_0[1]
+Ignored Value  : PIN_C3
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_0[20]
+Ignored Value  : PIN_E8
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_0[21]
+Ignored Value  : PIN_F8
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_0[22]
+Ignored Value  : PIN_F9
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_0[23]
+Ignored Value  : PIN_E9
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_0[24]
+Ignored Value  : PIN_C9
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_0[25]
+Ignored Value  : PIN_D9
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_0[26]
+Ignored Value  : PIN_E11
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_0[27]
+Ignored Value  : PIN_E10
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_0[28]
+Ignored Value  : PIN_C11
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_0[29]
+Ignored Value  : PIN_B11
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_0[2]
+Ignored Value  : PIN_A2
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_0[30]
+Ignored Value  : PIN_A12
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_0[31]
+Ignored Value  : PIN_D11
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_0[32]
+Ignored Value  : PIN_D12
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_0[33]
+Ignored Value  : PIN_B12
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_0[3]
+Ignored Value  : PIN_A3
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_0[4]
+Ignored Value  : PIN_B3
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_0[5]
+Ignored Value  : PIN_B4
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_0[6]
+Ignored Value  : PIN_A4
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_0[7]
+Ignored Value  : PIN_B5
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_0[8]
+Ignored Value  : PIN_A5
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_0[9]
+Ignored Value  : PIN_D5
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_0_IN[0]
+Ignored Value  : PIN_A8
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_0_IN[1]
+Ignored Value  : PIN_B8
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_1[0]
+Ignored Value  : PIN_F13
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_1[10]
+Ignored Value  : PIN_P11
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_1[11]
+Ignored Value  : PIN_R10
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_1[12]
+Ignored Value  : PIN_N12
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_1[13]
+Ignored Value  : PIN_P9
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_1[14]
+Ignored Value  : PIN_N9
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_1[15]
+Ignored Value  : PIN_N11
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_1[16]
+Ignored Value  : PIN_L16
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_1[17]
+Ignored Value  : PIN_K16
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_1[18]
+Ignored Value  : PIN_R16
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_1[19]
+Ignored Value  : PIN_L15
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_1[1]
+Ignored Value  : PIN_T15
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_1[20]
+Ignored Value  : PIN_P15
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_1[21]
+Ignored Value  : PIN_P16
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_1[22]
+Ignored Value  : PIN_R14
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_1[23]
+Ignored Value  : PIN_N16
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_1[24]
+Ignored Value  : PIN_N15
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_1[25]
+Ignored Value  : PIN_P14
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_1[26]
+Ignored Value  : PIN_L14
+Ignored Source : QSF Assignment
+
+Name           : Location
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+Ignored From   : 
+Ignored To     : GPIO_1[27]
+Ignored Value  : PIN_N14
+Ignored Source : QSF Assignment
+
+Name           : Location
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+Ignored From   : 
+Ignored To     : GPIO_1[28]
+Ignored Value  : PIN_M10
+Ignored Source : QSF Assignment
+
+Name           : Location
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+Ignored From   : 
+Ignored To     : GPIO_1[29]
+Ignored Value  : PIN_L13
+Ignored Source : QSF Assignment
+
+Name           : Location
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+Ignored To     : GPIO_1[2]
+Ignored Value  : PIN_T14
+Ignored Source : QSF Assignment
+
+Name           : Location
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+Ignored From   : 
+Ignored To     : GPIO_1[30]
+Ignored Value  : PIN_J16
+Ignored Source : QSF Assignment
+
+Name           : Location
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+Ignored From   : 
+Ignored To     : GPIO_1[31]
+Ignored Value  : PIN_K15
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+
+Name           : Location
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+Ignored From   : 
+Ignored To     : GPIO_1[32]
+Ignored Value  : PIN_J13
+Ignored Source : QSF Assignment
+
+Name           : Location
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+Ignored From   : 
+Ignored To     : GPIO_1[33]
+Ignored Value  : PIN_J14
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+
+Name           : Location
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+Ignored To     : GPIO_1[3]
+Ignored Value  : PIN_T13
+Ignored Source : QSF Assignment
+
+Name           : Location
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+Ignored From   : 
+Ignored To     : GPIO_1[4]
+Ignored Value  : PIN_R13
+Ignored Source : QSF Assignment
+
+Name           : Location
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+Ignored From   : 
+Ignored To     : GPIO_1[5]
+Ignored Value  : PIN_T12
+Ignored Source : QSF Assignment
+
+Name           : Location
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+Ignored From   : 
+Ignored To     : GPIO_1[6]
+Ignored Value  : PIN_R12
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+
+Name           : Location
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+Ignored From   : 
+Ignored To     : GPIO_1[7]
+Ignored Value  : PIN_T11
+Ignored Source : QSF Assignment
+
+Name           : Location
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+Ignored To     : GPIO_1[8]
+Ignored Value  : PIN_T10
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+
+Name           : Location
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+Ignored To     : GPIO_1[9]
+Ignored Value  : PIN_R11
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+
+Name           : Location
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+Ignored From   : 
+Ignored To     : GPIO_1_IN[0]
+Ignored Value  : PIN_T9
+Ignored Source : QSF Assignment
+
+Name           : Location
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+Ignored From   : 
+Ignored To     : GPIO_1_IN[1]
+Ignored Value  : PIN_R9
+Ignored Source : QSF Assignment
+
+Name           : Location
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+Ignored From   : 
+Ignored To     : GPIO_2[0]
+Ignored Value  : PIN_A14
+Ignored Source : QSF Assignment
+
+Name           : Location
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+Ignored From   : 
+Ignored To     : GPIO_2[10]
+Ignored Value  : PIN_F14
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+
+Name           : Location
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+Ignored From   : 
+Ignored To     : GPIO_2[11]
+Ignored Value  : PIN_G16
+Ignored Source : QSF Assignment
+
+Name           : Location
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+Ignored From   : 
+Ignored To     : GPIO_2[12]
+Ignored Value  : PIN_G15
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_2[1]
+Ignored Value  : PIN_B16
+Ignored Source : QSF Assignment
+
+Name           : Location
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+Ignored From   : 
+Ignored To     : GPIO_2[2]
+Ignored Value  : PIN_C14
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+
+Name           : Location
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+Ignored From   : 
+Ignored To     : GPIO_2[3]
+Ignored Value  : PIN_C16
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_2[4]
+Ignored Value  : PIN_C15
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+
+Name           : Location
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+Ignored From   : 
+Ignored To     : GPIO_2[5]
+Ignored Value  : PIN_D16
+Ignored Source : QSF Assignment
+
+Name           : Location
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+Ignored From   : 
+Ignored To     : GPIO_2[6]
+Ignored Value  : PIN_D15
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+
+Name           : Location
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+Ignored From   : 
+Ignored To     : GPIO_2[7]
+Ignored Value  : PIN_D14
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_2[8]
+Ignored Value  : PIN_F15
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_2[9]
+Ignored Value  : PIN_F16
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_2_IN[0]
+Ignored Value  : PIN_E15
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : GPIO_2_IN[1]
+Ignored Value  : PIN_E16
+Ignored Source : QSF Assignment
+
+Name           : Location
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+Ignored From   : 
+Ignored To     : GPIO_2_IN[2]
+Ignored Value  : PIN_M16
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : G_SENSOR_CS_N
+Ignored Value  : PIN_G5
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+
+Name           : Location
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+Ignored From   : 
+Ignored To     : G_SENSOR_INT
+Ignored Value  : PIN_M2
+Ignored Source : QSF Assignment
+
+Name           : Location
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+Ignored From   : 
+Ignored To     : I2C_SCLK
+Ignored Value  : PIN_F2
+Ignored Source : QSF Assignment
+
+Name           : Location
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+Ignored From   : 
+Ignored To     : I2C_SDAT
+Ignored Value  : PIN_F1
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : KEY[0]
+Ignored Value  : PIN_J15
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : KEY[1]
+Ignored Value  : PIN_E1
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+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : SW[0]
+Ignored Value  : PIN_M1
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+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : SW[1]
+Ignored Value  : PIN_T8
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : SW[2]
+Ignored Value  : PIN_B9
+Ignored Source : QSF Assignment
+
+Name           : Location
+Ignored Entity : 
+Ignored From   : 
+Ignored To     : SW[3]
+Ignored Value  : PIN_M15
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : ADC_CS_N
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : ADC_SADDR
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : ADC_SCLK
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : ADC_SDAT
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : DRAM_ADDR[0]
+Ignored Value  : 3.3-V LVTTL
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+
+Name           : I/O Standard
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+Ignored From   : 
+Ignored To     : DRAM_ADDR[10]
+Ignored Value  : 3.3-V LVTTL
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+
+Name           : I/O Standard
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+Ignored To     : DRAM_ADDR[11]
+Ignored Value  : 3.3-V LVTTL
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+
+Name           : I/O Standard
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+Ignored To     : DRAM_ADDR[12]
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+
+Name           : I/O Standard
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+Ignored To     : DRAM_ADDR[1]
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+
+Name           : I/O Standard
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+Ignored To     : DRAM_ADDR[2]
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+
+Name           : I/O Standard
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+Ignored To     : DRAM_ADDR[3]
+Ignored Value  : 3.3-V LVTTL
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+
+Name           : I/O Standard
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+Ignored To     : DRAM_ADDR[4]
+Ignored Value  : 3.3-V LVTTL
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+
+Name           : I/O Standard
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+Ignored To     : DRAM_ADDR[5]
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+
+Name           : I/O Standard
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+
+Name           : I/O Standard
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+Ignored To     : DRAM_ADDR[7]
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+
+Name           : I/O Standard
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+Ignored To     : DRAM_ADDR[8]
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+
+Name           : I/O Standard
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+Ignored To     : DRAM_ADDR[9]
+Ignored Value  : 3.3-V LVTTL
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+
+Name           : I/O Standard
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+Ignored To     : DRAM_BA[0]
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+
+Name           : I/O Standard
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+Ignored To     : DRAM_BA[1]
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+
+Name           : I/O Standard
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+Ignored To     : DRAM_CAS_N
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+
+Name           : I/O Standard
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+Ignored To     : DRAM_CKE
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+
+Name           : I/O Standard
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+
+Name           : I/O Standard
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+
+Name           : I/O Standard
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+Ignored To     : DRAM_DQM[0]
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+
+Name           : I/O Standard
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+
+Name           : I/O Standard
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+
+Name           : I/O Standard
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+
+Name           : I/O Standard
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+
+Name           : I/O Standard
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+
+Name           : I/O Standard
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+
+Name           : I/O Standard
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+
+Name           : I/O Standard
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+
+Name           : I/O Standard
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+
+Name           : I/O Standard
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+
+Name           : I/O Standard
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+
+Name           : I/O Standard
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+
+Name           : I/O Standard
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+
+Name           : I/O Standard
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+
+Name           : I/O Standard
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+
+Name           : I/O Standard
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+
+Name           : I/O Standard
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+
+Name           : I/O Standard
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+
+Name           : I/O Standard
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+
+Name           : I/O Standard
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+
+Name           : I/O Standard
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+
+Name           : I/O Standard
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+
+Name           : I/O Standard
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+
+Name           : I/O Standard
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+
+Name           : I/O Standard
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+Ignored To     : GPIO_0[10]
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+
+Name           : I/O Standard
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+Ignored To     : GPIO_0[11]
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+
+Name           : I/O Standard
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+Ignored To     : GPIO_0[12]
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+
+Name           : I/O Standard
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+Ignored To     : GPIO_0[13]
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+
+Name           : I/O Standard
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+Ignored To     : GPIO_0[14]
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+
+Name           : I/O Standard
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+Ignored To     : GPIO_0[15]
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+
+Name           : I/O Standard
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+Ignored To     : GPIO_0[16]
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+
+Name           : I/O Standard
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+Ignored To     : GPIO_0[17]
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+
+Name           : I/O Standard
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+Ignored To     : GPIO_0[18]
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+
+Name           : I/O Standard
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+Ignored To     : GPIO_0[19]
+Ignored Value  : 3.3-V LVTTL
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+
+Name           : I/O Standard
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+Ignored To     : GPIO_0[1]
+Ignored Value  : 3.3-V LVTTL
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+
+Name           : I/O Standard
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+Ignored To     : GPIO_0[20]
+Ignored Value  : 3.3-V LVTTL
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+
+Name           : I/O Standard
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+Ignored To     : GPIO_0[21]
+Ignored Value  : 3.3-V LVTTL
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+
+Name           : I/O Standard
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+Ignored To     : GPIO_0[22]
+Ignored Value  : 3.3-V LVTTL
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+
+Name           : I/O Standard
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+Ignored To     : GPIO_0[23]
+Ignored Value  : 3.3-V LVTTL
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+
+Name           : I/O Standard
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+Ignored To     : GPIO_0[24]
+Ignored Value  : 3.3-V LVTTL
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+
+Name           : I/O Standard
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+Ignored To     : GPIO_0[25]
+Ignored Value  : 3.3-V LVTTL
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+
+Name           : I/O Standard
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+Ignored To     : GPIO_0[26]
+Ignored Value  : 3.3-V LVTTL
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+
+Name           : I/O Standard
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+Ignored To     : GPIO_0[27]
+Ignored Value  : 3.3-V LVTTL
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+
+Name           : I/O Standard
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+Ignored To     : GPIO_0[28]
+Ignored Value  : 3.3-V LVTTL
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+
+Name           : I/O Standard
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+Ignored To     : GPIO_0[29]
+Ignored Value  : 3.3-V LVTTL
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+
+Name           : I/O Standard
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+Ignored To     : GPIO_0[2]
+Ignored Value  : 3.3-V LVTTL
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+
+Name           : I/O Standard
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+Ignored To     : GPIO_0[30]
+Ignored Value  : 3.3-V LVTTL
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+
+Name           : I/O Standard
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+Ignored To     : GPIO_0[31]
+Ignored Value  : 3.3-V LVTTL
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+
+Name           : I/O Standard
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+Ignored To     : GPIO_0[32]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_0[33]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_0[3]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_0[4]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_0[5]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_0[6]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_0[7]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_0[8]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_0[9]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_0_IN[0]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_0_IN[1]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_1[0]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_1[10]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_1[11]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_1[12]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_1[13]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_1[14]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_1[15]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_1[16]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_1[17]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_1[18]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_1[19]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_1[1]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_1[20]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_1[21]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_1[22]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_1[23]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_1[24]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_1[25]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_1[26]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_1[27]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_1[28]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_1[29]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_1[2]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_1[30]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_1[31]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_1[32]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_1[33]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_1[3]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_1[4]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_1[5]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_1[6]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_1[7]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_1[8]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_1[9]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_1_IN[0]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_1_IN[1]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_2[0]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_2[10]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_2[11]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_2[12]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_2[1]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_2[2]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_2[3]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_2[4]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_2[5]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_2[6]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_2[7]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_2[8]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_2[9]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_2_IN[0]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_2_IN[1]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : GPIO_2_IN[2]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : G_SENSOR_CS_N
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : G_SENSOR_INT
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : I2C_SCLK
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : I2C_SDAT
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : KEY[0]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : KEY[1]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : SW[0]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : SW[1]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : SW[2]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
+
+Name           : I/O Standard
+Ignored Entity : spectrum
+Ignored From   : 
+Ignored To     : SW[3]
+Ignored Value  : 3.3-V LVTTL
+Ignored Source : QSF Assignment
++--------------------------------------------------------------------------------+
+
+
+
++--------------------------------------------------------------------------------+
+; Incremental Compilation Preservation Summary                                   ;
++--------------------------------------------------------------------------------+
+Type                       : Placement (by node)
+Total [A + B]              : 
+From Design Partitions [A] : 
+From Rapid Recompile [B]   : 
+
+Type                       :     -- Requested
+Total [A + B]              : 0.00 % ( 0 / 93 )
+From Design Partitions [A] : 0.00 % ( 0 / 93 )
+From Rapid Recompile [B]   : 0.00 % ( 0 / 93 )
+
+Type                       :     -- Achieved
+Total [A + B]              : 0.00 % ( 0 / 93 )
+From Design Partitions [A] : 0.00 % ( 0 / 93 )
+From Rapid Recompile [B]   : 0.00 % ( 0 / 93 )
+
+Type                       : 
+Total [A + B]              : 
+From Design Partitions [A] : 
+From Rapid Recompile [B]   : 
+
+Type                       : Routing (by net)
+Total [A + B]              : 
+From Design Partitions [A] : 
+From Rapid Recompile [B]   : 
+
+Type                       :     -- Requested
+Total [A + B]              : 0.00 % ( 0 / 0 )
+From Design Partitions [A] : 0.00 % ( 0 / 0 )
+From Rapid Recompile [B]   : 0.00 % ( 0 / 0 )
+
+Type                       :     -- Achieved
+Total [A + B]              : 0.00 % ( 0 / 0 )
+From Design Partitions [A] : 0.00 % ( 0 / 0 )
+From Rapid Recompile [B]   : 0.00 % ( 0 / 0 )
++--------------------------------------------------------------------------------+
+
+
+
++--------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings                                     ;
++--------------------------------------------------------------------------------+
+Partition Name               : Top
+Partition Type               : User-created
+Netlist Type Used            : Source File
+Preservation Level Used      : N/A
+Netlist Type Requested       : Source File
+Preservation Level Requested : N/A
+Contents                     : 
+
+Partition Name               : hard_block:auto_generated_inst
+Partition Type               : Auto-generated
+Netlist Type Used            : Source File
+Preservation Level Used      : N/A
+Netlist Type Requested       : Source File
+Preservation Level Requested : N/A
+Contents                     : hard_block:auto_generated_inst
++--------------------------------------------------------------------------------+
+
+
+
++--------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation                                 ;
++--------------------------------------------------------------------------------+
+Partition Name          : Top
+Preservation Achieved   : 0.00 % ( 0 / 83 )
+Preservation Level Used : N/A
+Netlist Type Used       : Source File
+Preservation Method     : N/A
+Notes                   : 
+
+Partition Name          : hard_block:auto_generated_inst
+Preservation Achieved   : 0.00 % ( 0 / 10 )
+Preservation Level Used : N/A
+Netlist Type Used       : Source File
+Preservation Method     : N/A
+Notes                   : 
++--------------------------------------------------------------------------------+
+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in /home/benny/work/fpga/projects/output_files/spectrum.pin.
+
+
++---------------------------------------------------------------------+
+; Fitter Resource Usage Summary                                       ;
++---------------------------------------------+-----------------------+
+; Resource                                    ; Usage                 ;
++---------------------------------------------+-----------------------+
+; Total logic elements                        ; 35 / 22,320 ( < 1 % ) ;
+;     -- Combinational with no register       ; 0                     ;
+;     -- Register only                        ; 7                     ;
+;     -- Combinational with a register        ; 28                    ;
+;                                             ;                       ;
+; Logic element usage by number of LUT inputs ;                       ;
+;     -- 4 input functions                    ; 0                     ;
+;     -- 3 input functions                    ; 1                     ;
+;     -- <=2 input functions                  ; 27                    ;
+;     -- Register only                        ; 7                     ;
+;                                             ;                       ;
+; Logic elements by mode                      ;                       ;
+;     -- normal mode                          ; 2                     ;
+;     -- arithmetic mode                      ; 26                    ;
+;                                             ;                       ;
+; Total registers*                            ; 35 / 23,018 ( < 1 % ) ;
+;     -- Dedicated logic registers            ; 35 / 22,320 ( < 1 % ) ;
+;     -- I/O registers                        ; 0 / 698 ( 0 % )       ;
+;                                             ;                       ;
+; Total LABs:  partially or completely used   ; 5 / 1,395 ( < 1 % )   ;
+; Virtual pins                                ; 0                     ;
+; I/O pins                                    ; 9 / 154 ( 6 % )       ;
+;     -- Clock pins                           ; 1 / 7 ( 14 % )        ;
+;     -- Dedicated input pins                 ; 0 / 9 ( 0 % )         ;
+;                                             ;                       ;
+; Global signals                              ; 1                     ;
+; M9Ks                                        ; 0 / 66 ( 0 % )        ;
+; Total block memory bits                     ; 0 / 608,256 ( 0 % )   ;
+; Total block memory implementation bits      ; 0 / 608,256 ( 0 % )   ;
+; Embedded Multiplier 9-bit elements          ; 0 / 132 ( 0 % )       ;
+; PLLs                                        ; 0 / 4 ( 0 % )         ;
+; Global clocks                               ; 1 / 20 ( 5 % )        ;
+; JTAGs                                       ; 0 / 1 ( 0 % )         ;
+; CRC blocks                                  ; 0 / 1 ( 0 % )         ;
+; ASMI blocks                                 ; 0 / 1 ( 0 % )         ;
+; Impedance control blocks                    ; 0 / 4 ( 0 % )         ;
+; Average interconnect usage (total/H/V)      ; 0% / 0% / 0%          ;
+; Peak interconnect usage (total/H/V)         ; 0% / 0% / 0%          ;
+; Maximum fan-out                             ; 35                    ;
+; Highest non-global fan-out                  ; 2                     ;
+; Total fan-out                               ; 154                   ;
+; Average fan-out                             ; 1.56                  ;
++---------------------------------------------+-----------------------+
+*  Register count does not include registers inside RAM blocks or DSP blocks.
+
+
+
++--------------------------------------------------------------------------------+
+; Fitter Partition Statistics                                                    ;
++--------------------------------------------------------------------------------+
+Statistic                      : Difficulty Clustering Region
+Top                            : Low
+hard_block:auto_generated_inst : Low
+
+Statistic                      : 
+Top                            : 
+hard_block:auto_generated_inst : 
+
+Statistic                      : Total logic elements
+Top                            : 35 / 22320 ( < 1 % )
+hard_block:auto_generated_inst : 0 / 22320 ( 0 % )
+
+Statistic                      :     -- Combinational with no register
+Top                            : 0
+hard_block:auto_generated_inst : 0
+
+Statistic                      :     -- Register only
+Top                            : 7
+hard_block:auto_generated_inst : 0
+
+Statistic                      :     -- Combinational with a register
+Top                            : 28
+hard_block:auto_generated_inst : 0
+
+Statistic                      : 
+Top                            : 
+hard_block:auto_generated_inst : 
+
+Statistic                      : Logic element usage by number of LUT inputs
+Top                            : 
+hard_block:auto_generated_inst : 
+
+Statistic                      :     -- 4 input functions
+Top                            : 0
+hard_block:auto_generated_inst : 0
+
+Statistic                      :     -- 3 input functions
+Top                            : 1
+hard_block:auto_generated_inst : 0
+
+Statistic                      :     -- <=2 input functions
+Top                            : 27
+hard_block:auto_generated_inst : 0
+
+Statistic                      :     -- Register only
+Top                            : 7
+hard_block:auto_generated_inst : 0
+
+Statistic                      : 
+Top                            : 
+hard_block:auto_generated_inst : 
+
+Statistic                      : Logic elements by mode
+Top                            : 
+hard_block:auto_generated_inst : 
+
+Statistic                      :     -- normal mode
+Top                            : 2
+hard_block:auto_generated_inst : 0
+
+Statistic                      :     -- arithmetic mode
+Top                            : 26
+hard_block:auto_generated_inst : 0
+
+Statistic                      : 
+Top                            : 
+hard_block:auto_generated_inst : 
+
+Statistic                      : Total registers
+Top                            : 35
+hard_block:auto_generated_inst : 0
+
+Statistic                      :     -- Dedicated logic registers
+Top                            : 35 / 22320 ( < 1 % )
+hard_block:auto_generated_inst : 0 / 22320 ( 0 % )
+
+Statistic                      :     -- I/O registers
+Top                            : 0
+hard_block:auto_generated_inst : 0
+
+Statistic                      : 
+Top                            : 
+hard_block:auto_generated_inst : 
+
+Statistic                      : Total LABs:  partially or completely used
+Top                            : 5 / 1395 ( < 1 % )
+hard_block:auto_generated_inst : 0 / 1395 ( 0 % )
+
+Statistic                      : 
+Top                            : 
+hard_block:auto_generated_inst : 
+
+Statistic                      : Virtual pins
+Top                            : 0
+hard_block:auto_generated_inst : 0
+
+Statistic                      : I/O pins
+Top                            : 9
+hard_block:auto_generated_inst : 0
+
+Statistic                      : Embedded Multiplier 9-bit elements
+Top                            : 0 / 132 ( 0 % )
+hard_block:auto_generated_inst : 0 / 132 ( 0 % )
+
+Statistic                      : Total memory bits
+Top                            : 0
+hard_block:auto_generated_inst : 0
+
+Statistic                      : Total RAM block bits
+Top                            : 0
+hard_block:auto_generated_inst : 0
+
+Statistic                      : Clock control block
+Top                            : 1 / 24 ( 4 % )
+hard_block:auto_generated_inst : 0 / 24 ( 0 % )
+
+Statistic                      : 
+Top                            : 
+hard_block:auto_generated_inst : 
+
+Statistic                      : Connections
+Top                            : 
+hard_block:auto_generated_inst : 
+
+Statistic                      :     -- Input Connections
+Top                            : 0
+hard_block:auto_generated_inst : 0
+
+Statistic                      :     -- Registered Input Connections
+Top                            : 0
+hard_block:auto_generated_inst : 0
+
+Statistic                      :     -- Output Connections
+Top                            : 0
+hard_block:auto_generated_inst : 0
+
+Statistic                      :     -- Registered Output Connections
+Top                            : 0
+hard_block:auto_generated_inst : 0
+
+Statistic                      : 
+Top                            : 
+hard_block:auto_generated_inst : 
+
+Statistic                      : Internal Connections
+Top                            : 
+hard_block:auto_generated_inst : 
+
+Statistic                      :     -- Total Connections
+Top                            : 149
+hard_block:auto_generated_inst : 5
+
+Statistic                      :     -- Registered Connections
+Top                            : 43
+hard_block:auto_generated_inst : 0
+
+Statistic                      : 
+Top                            : 
+hard_block:auto_generated_inst : 
+
+Statistic                      : External Connections
+Top                            : 
+hard_block:auto_generated_inst : 
+
+Statistic                      :     -- Top
+Top                            : 0
+hard_block:auto_generated_inst : 0
+
+Statistic                      :     -- hard_block:auto_generated_inst
+Top                            : 0
+hard_block:auto_generated_inst : 0
+
+Statistic                      : 
+Top                            : 
+hard_block:auto_generated_inst : 
+
+Statistic                      : Partition Interface
+Top                            : 
+hard_block:auto_generated_inst : 
+
+Statistic                      :     -- Input Ports
+Top                            : 1
+hard_block:auto_generated_inst : 0
+
+Statistic                      :     -- Output Ports
+Top                            : 8
+hard_block:auto_generated_inst : 0
+
+Statistic                      :     -- Bidir Ports
+Top                            : 0
+hard_block:auto_generated_inst : 0
+
+Statistic                      : 
+Top                            : 
+hard_block:auto_generated_inst : 
+
+Statistic                      : Registered Ports
+Top                            : 
+hard_block:auto_generated_inst : 
+
+Statistic                      :     -- Registered Input Ports
+Top                            : 0
+hard_block:auto_generated_inst : 0
+
+Statistic                      :     -- Registered Output Ports
+Top                            : 0
+hard_block:auto_generated_inst : 0
+
+Statistic                      : 
+Top                            : 
+hard_block:auto_generated_inst : 
+
+Statistic                      : Port Connectivity
+Top                            : 
+hard_block:auto_generated_inst : 
+
+Statistic                      :     -- Input Ports driven by GND
+Top                            : 0
+hard_block:auto_generated_inst : 0
+
+Statistic                      :     -- Output Ports driven by GND
+Top                            : 0
+hard_block:auto_generated_inst : 0
+
+Statistic                      :     -- Input Ports driven by VCC
+Top                            : 0
+hard_block:auto_generated_inst : 0
+
+Statistic                      :     -- Output Ports driven by VCC
+Top                            : 0
+hard_block:auto_generated_inst : 0
+
+Statistic                      :     -- Input Ports with no Source
+Top                            : 0
+hard_block:auto_generated_inst : 0
+
+Statistic                      :     -- Output Ports with no Source
+Top                            : 0
+hard_block:auto_generated_inst : 0
+
+Statistic                      :     -- Input Ports with no Fanout
+Top                            : 0
+hard_block:auto_generated_inst : 0
+
+Statistic                      :     -- Output Ports with no Fanout
+Top                            : 0
+hard_block:auto_generated_inst : 0
++--------------------------------------------------------------------------------+
+
+
+
++--------------------------------------------------------------------------------+
+; Input Pins                                                                     ;
++--------------------------------------------------------------------------------+
+Name                      : CLOCK_50
+Pin #                     : R8
+I/O Bank                  : 3
+X coordinate              : 27
+Y coordinate              : 0
+Z coordinate              : 21
+Combinational Fan-Out     : 35
+Registered Fan-Out        : 0
+Global                    : yes
+Input Register            : no
+Power Up High             : no
+PCI I/O Enabled           : yes
+Bus Hold                  : no
+Weak Pull Up              : Off
+I/O Standard              : 3.3-V LVTTL
+Termination Control Block : --
+Location assigned by      : User
++--------------------------------------------------------------------------------+
+
+
+
++--------------------------------------------------------------------------------+
+; Output Pins                                                                    ;
++--------------------------------------------------------------------------------+
+Name                        : LED[0]
+Pin #                       : A15
+I/O Bank                    : 7
+X coordinate                : 38
+Y coordinate                : 34
+Z coordinate                : 14
+Output Register             : no
+Output Enable Register      : no
+Power Up High               : no
+Slew Rate                   : 2
+PCI I/O Enabled             : no
+Open Drain                  : no
+TRI Primitive               : no
+Bus Hold                    : no
+Weak Pull Up                : Off
+I/O Standard                : 3.3-V LVTTL
+Current Strength            : 8mA
+Termination                 : Off
+Termination Control Block   : --
+Output Buffer Pre-emphasis  : no
+Voltage Output Differential : no
+Location assigned by        : User
+Output Enable Source        : -
+Output Enable Group         : -
+
+Name                        : LED[1]
+Pin #                       : A13
+I/O Bank                    : 7
+X coordinate                : 49
+Y coordinate                : 34
+Z coordinate                : 0
+Output Register             : no
+Output Enable Register      : no
+Power Up High               : no
+Slew Rate                   : 2
+PCI I/O Enabled             : no
+Open Drain                  : no
+TRI Primitive               : no
+Bus Hold                    : no
+Weak Pull Up                : Off
+I/O Standard                : 3.3-V LVTTL
+Current Strength            : 8mA
+Termination                 : Off
+Termination Control Block   : --
+Output Buffer Pre-emphasis  : no
+Voltage Output Differential : no
+Location assigned by        : User
+Output Enable Source        : -
+Output Enable Group         : -
+
+Name                        : LED[2]
+Pin #                       : B13
+I/O Bank                    : 7
+X coordinate                : 49
+Y coordinate                : 34
+Z coordinate                : 7
+Output Register             : no
+Output Enable Register      : no
+Power Up High               : no
+Slew Rate                   : 2
+PCI I/O Enabled             : no
+Open Drain                  : no
+TRI Primitive               : no
+Bus Hold                    : no
+Weak Pull Up                : Off
+I/O Standard                : 3.3-V LVTTL
+Current Strength            : 8mA
+Termination                 : Off
+Termination Control Block   : --
+Output Buffer Pre-emphasis  : no
+Voltage Output Differential : no
+Location assigned by        : User
+Output Enable Source        : -
+Output Enable Group         : -
+
+Name                        : LED[3]
+Pin #                       : A11
+I/O Bank                    : 7
+X coordinate                : 40
+Y coordinate                : 34
+Z coordinate                : 0
+Output Register             : no
+Output Enable Register      : no
+Power Up High               : no
+Slew Rate                   : 2
+PCI I/O Enabled             : no
+Open Drain                  : no
+TRI Primitive               : no
+Bus Hold                    : no
+Weak Pull Up                : Off
+I/O Standard                : 3.3-V LVTTL
+Current Strength            : 8mA
+Termination                 : Off
+Termination Control Block   : --
+Output Buffer Pre-emphasis  : no
+Voltage Output Differential : no
+Location assigned by        : User
+Output Enable Source        : -
+Output Enable Group         : -
+
+Name                        : LED[4]
+Pin #                       : D1
+I/O Bank                    : 1
+X coordinate                : 0
+Y coordinate                : 25
+Z coordinate                : 7
+Output Register             : no
+Output Enable Register      : no
+Power Up High               : no
+Slew Rate                   : 2
+PCI I/O Enabled             : no
+Open Drain                  : no
+TRI Primitive               : no
+Bus Hold                    : no
+Weak Pull Up                : Off
+I/O Standard                : 3.3-V LVTTL
+Current Strength            : 8mA
+Termination                 : Off
+Termination Control Block   : --
+Output Buffer Pre-emphasis  : no
+Voltage Output Differential : no
+Location assigned by        : User
+Output Enable Source        : -
+Output Enable Group         : -
+
+Name                        : LED[5]
+Pin #                       : F3
+I/O Bank                    : 1
+X coordinate                : 0
+Y coordinate                : 26
+Z coordinate                : 14
+Output Register             : no
+Output Enable Register      : no
+Power Up High               : no
+Slew Rate                   : 2
+PCI I/O Enabled             : no
+Open Drain                  : no
+TRI Primitive               : no
+Bus Hold                    : no
+Weak Pull Up                : Off
+I/O Standard                : 3.3-V LVTTL
+Current Strength            : 8mA
+Termination                 : Off
+Termination Control Block   : --
+Output Buffer Pre-emphasis  : no
+Voltage Output Differential : no
+Location assigned by        : User
+Output Enable Source        : -
+Output Enable Group         : -
+
+Name                        : LED[6]
+Pin #                       : B1
+I/O Bank                    : 1
+X coordinate                : 0
+Y coordinate                : 28
+Z coordinate                : 7
+Output Register             : no
+Output Enable Register      : no
+Power Up High               : no
+Slew Rate                   : 2
+PCI I/O Enabled             : no
+Open Drain                  : no
+TRI Primitive               : no
+Bus Hold                    : no
+Weak Pull Up                : Off
+I/O Standard                : 3.3-V LVTTL
+Current Strength            : 8mA
+Termination                 : Off
+Termination Control Block   : --
+Output Buffer Pre-emphasis  : no
+Voltage Output Differential : no
+Location assigned by        : User
+Output Enable Source        : -
+Output Enable Group         : -
+
+Name                        : LED[7]
+Pin #                       : L3
+I/O Bank                    : 2
+X coordinate                : 0
+Y coordinate                : 10
+Z coordinate                : 21
+Output Register             : no
+Output Enable Register      : no
+Power Up High               : no
+Slew Rate                   : 2
+PCI I/O Enabled             : no
+Open Drain                  : no
+TRI Primitive               : no
+Bus Hold                    : no
+Weak Pull Up                : Off
+I/O Standard                : 3.3-V LVTTL
+Current Strength            : 8mA
+Termination                 : Off
+Termination Control Block   : --
+Output Buffer Pre-emphasis  : no
+Voltage Output Differential : no
+Location assigned by        : User
+Output Enable Source        : -
+Output Enable Group         : -
++--------------------------------------------------------------------------------+
+
+
+
++--------------------------------------------------------------------------------+
+; Dual Purpose and Dedicated Pins                                                ;
++--------------------------------------------------------------------------------+
+Location         : C1
+Pin Name         : DIFFIO_L3n, DATA1, ASDO
+Reserved As      : As input tri-stated
+User Signal Name : ~ALTERA_ASDO_DATA1~
+Pin Type         : Dual Purpose Pin
+
+Location         : D2
+Pin Name         : DIFFIO_L4p, FLASH_nCE, nCSO
+Reserved As      : As input tri-stated
+User Signal Name : ~ALTERA_FLASH_nCE_nCSO~
+Pin Type         : Dual Purpose Pin
+
+Location         : F4
+Pin Name         : nSTATUS
+Reserved As      : -
+User Signal Name : -
+Pin Type         : Dedicated Programming Pin
+
+Location         : H1
+Pin Name         : DCLK
+Reserved As      : As output driving ground
+User Signal Name : ~ALTERA_DCLK~
+Pin Type         : Dual Purpose Pin
+
+Location         : H2
+Pin Name         : DATA0
+Reserved As      : As input tri-stated
+User Signal Name : ~ALTERA_DATA0~
+Pin Type         : Dual Purpose Pin
+
+Location         : H5
+Pin Name         : nCONFIG
+Reserved As      : -
+User Signal Name : -
+Pin Type         : Dedicated Programming Pin
+
+Location         : J3
+Pin Name         : nCE
+Reserved As      : -
+User Signal Name : -
+Pin Type         : Dedicated Programming Pin
+
+Location         : H14
+Pin Name         : CONF_DONE
+Reserved As      : -
+User Signal Name : -
+Pin Type         : Dedicated Programming Pin
+
+Location         : H13
+Pin Name         : MSEL0
+Reserved As      : -
+User Signal Name : -
+Pin Type         : Dedicated Programming Pin
+
+Location         : H12
+Pin Name         : MSEL1
+Reserved As      : -
+User Signal Name : -
+Pin Type         : Dedicated Programming Pin
+
+Location         : G12
+Pin Name         : MSEL2
+Reserved As      : -
+User Signal Name : -
+Pin Type         : Dedicated Programming Pin
+
+Location         : G12
+Pin Name         : MSEL3
+Reserved As      : -
+User Signal Name : -
+Pin Type         : Dedicated Programming Pin
+
+Location         : F16
+Pin Name         : DIFFIO_R4n, nCEO
+Reserved As      : Use as programming pin
+User Signal Name : ~ALTERA_nCEO~
+Pin Type         : Dual Purpose Pin
+
+Location         : A15
+Pin Name         : DIFFIO_T19n, PADD1
+Reserved As      : Use as regular IO
+User Signal Name : LED[0]
+Pin Type         : Dual Purpose Pin
++--------------------------------------------------------------------------------+
+
+
+
++--------------------------------------------------------------------------------+
+; I/O Bank Usage                                                                 ;
++--------------------------------------------------------------------------------+
+I/O Bank      : 1
+Usage         : 7 / 14 ( 50 % )
+VCCIO Voltage : 3.3V
+VREF Voltage  : --
+
+I/O Bank      : 2
+Usage         : 1 / 16 ( 6 % )
+VCCIO Voltage : 3.3V
+VREF Voltage  : --
+
+I/O Bank      : 3
+Usage         : 1 / 25 ( 4 % )
+VCCIO Voltage : 3.3V
+VREF Voltage  : --
+
+I/O Bank      : 4
+Usage         : 0 / 20 ( 0 % )
+VCCIO Voltage : 2.5V
+VREF Voltage  : --
+
+I/O Bank      : 5
+Usage         : 0 / 18 ( 0 % )
+VCCIO Voltage : 2.5V
+VREF Voltage  : --
+
+I/O Bank      : 6
+Usage         : 1 / 13 ( 8 % )
+VCCIO Voltage : 2.5V
+VREF Voltage  : --
+
+I/O Bank      : 7
+Usage         : 4 / 24 ( 17 % )
+VCCIO Voltage : 3.3V
+VREF Voltage  : --
+
+I/O Bank      : 8
+Usage         : 0 / 24 ( 0 % )
+VCCIO Voltage : 2.5V
+VREF Voltage  : --
++--------------------------------------------------------------------------------+
+
+
+
++--------------------------------------------------------------------------------+
+; All Package Pins                                                               ;
++--------------------------------------------------------------------------------+
+Location        : A1
+Pad Number      : 
+I/O Bank        : 8
+Pin Name/Usage  : VCCIO8
+Dir.            : power
+I/O Standard    : 
+Voltage         : 2.5V
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : A2
+Pad Number      : 238
+I/O Bank        : 8
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : A3
+Pad Number      : 239
+I/O Bank        : 8
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : A4
+Pad Number      : 236
+I/O Bank        : 8
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : A5
+Pad Number      : 232
+I/O Bank        : 8
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : A6
+Pad Number      : 225
+I/O Bank        : 8
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : A7
+Pad Number      : 220
+I/O Bank        : 8
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : A8
+Pad Number      : 211
+I/O Bank        : 8
+Pin Name/Usage  : GND+
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : A9
+Pad Number      : 209
+I/O Bank        : 7
+Pin Name/Usage  : GND+
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : A10
+Pad Number      : 198
+I/O Bank        : 7
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : A11
+Pad Number      : 188
+I/O Bank        : 7
+Pin Name/Usage  : LED[3]
+Dir.            : output
+I/O Standard    : 3.3-V LVTTL
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : Y
+Bus Hold        : no
+Weak Pull Up    : Off
+
+Location        : A12
+Pad Number      : 186
+I/O Bank        : 7
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : A13
+Pad Number      : 179
+I/O Bank        : 7
+Pin Name/Usage  : LED[1]
+Dir.            : output
+I/O Standard    : 3.3-V LVTTL
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : Y
+Bus Hold        : no
+Weak Pull Up    : Off
+
+Location        : A14
+Pad Number      : 181
+I/O Bank        : 7
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : A15
+Pad Number      : 191
+I/O Bank        : 7
+Pin Name/Usage  : LED[0]
+Dir.            : output
+I/O Standard    : 3.3-V LVTTL
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : Y
+Bus Hold        : no
+Weak Pull Up    : Off
+
+Location        : A16
+Pad Number      : 
+I/O Bank        : 7
+Pin Name/Usage  : VCCIO7
+Dir.            : power
+I/O Standard    : 
+Voltage         : 3.3V
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : B1
+Pad Number      : 5
+I/O Bank        : 1
+Pin Name/Usage  : LED[6]
+Dir.            : output
+I/O Standard    : 3.3-V LVTTL
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : Y
+Bus Hold        : no
+Weak Pull Up    : Off
+
+Location        : B2
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : GND
+Dir.            : gnd
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : B3
+Pad Number      : 242
+I/O Bank        : 8
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : B4
+Pad Number      : 237
+I/O Bank        : 8
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : B5
+Pad Number      : 233
+I/O Bank        : 8
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : B6
+Pad Number      : 226
+I/O Bank        : 8
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : B7
+Pad Number      : 221
+I/O Bank        : 8
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : B8
+Pad Number      : 212
+I/O Bank        : 8
+Pin Name/Usage  : GND+
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : B9
+Pad Number      : 210
+I/O Bank        : 7
+Pin Name/Usage  : GND+
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : B10
+Pad Number      : 199
+I/O Bank        : 7
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : B11
+Pad Number      : 189
+I/O Bank        : 7
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : B12
+Pad Number      : 187
+I/O Bank        : 7
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : B13
+Pad Number      : 180
+I/O Bank        : 7
+Pin Name/Usage  : LED[2]
+Dir.            : output
+I/O Standard    : 3.3-V LVTTL
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : Y
+Bus Hold        : no
+Weak Pull Up    : Off
+
+Location        : B14
+Pad Number      : 182
+I/O Bank        : 7
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : B15
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : GND
+Dir.            : gnd
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : B16
+Pad Number      : 164
+I/O Bank        : 6
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : C1
+Pad Number      : 7
+I/O Bank        : 1
+Pin Name/Usage  : ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : input
+I/O Standard    : 3.3-V LVTTL
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : N
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : C2
+Pad Number      : 6
+I/O Bank        : 1
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : C3
+Pad Number      : 245
+I/O Bank        : 8
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : C4
+Pad Number      : 
+I/O Bank        : 8
+Pin Name/Usage  : VCCIO8
+Dir.            : power
+I/O Standard    : 
+Voltage         : 2.5V
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : C5
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : GND
+Dir.            : gnd
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : C6
+Pad Number      : 224
+I/O Bank        : 8
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : C7
+Pad Number      : 
+I/O Bank        : 8
+Pin Name/Usage  : VCCIO8
+Dir.            : power
+I/O Standard    : 
+Voltage         : 2.5V
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : C8
+Pad Number      : 215
+I/O Bank        : 8
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : C9
+Pad Number      : 200
+I/O Bank        : 7
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : C10
+Pad Number      : 
+I/O Bank        : 7
+Pin Name/Usage  : VCCIO7
+Dir.            : power
+I/O Standard    : 
+Voltage         : 3.3V
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : C11
+Pad Number      : 190
+I/O Bank        : 7
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : C12
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : GND
+Dir.            : gnd
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : C13
+Pad Number      : 
+I/O Bank        : 7
+Pin Name/Usage  : VCCIO7
+Dir.            : power
+I/O Standard    : 
+Voltage         : 3.3V
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : C14
+Pad Number      : 175
+I/O Bank        : 7
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : C15
+Pad Number      : 174
+I/O Bank        : 6
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : C16
+Pad Number      : 173
+I/O Bank        : 6
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : D1
+Pad Number      : 10
+I/O Bank        : 1
+Pin Name/Usage  : LED[4]
+Dir.            : output
+I/O Standard    : 3.3-V LVTTL
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : Y
+Bus Hold        : no
+Weak Pull Up    : Off
+
+Location        : D2
+Pad Number      : 9
+I/O Bank        : 1
+Pin Name/Usage  : ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : input
+I/O Standard    : 3.3-V LVTTL
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : N
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : D3
+Pad Number      : 246
+I/O Bank        : 8
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : D4
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : VCCD_PLL3
+Dir.            : power
+I/O Standard    : 
+Voltage         : 1.2V
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : D5
+Pad Number      : 241
+I/O Bank        : 8
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : D6
+Pad Number      : 234
+I/O Bank        : 8
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : D7
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : GND
+Dir.            : gnd
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : D8
+Pad Number      : 216
+I/O Bank        : 8
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : D9
+Pad Number      : 201
+I/O Bank        : 7
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : D10
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : GND
+Dir.            : gnd
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : D11
+Pad Number      : 177
+I/O Bank        : 7
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : D12
+Pad Number      : 178
+I/O Bank        : 7
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : D13
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : VCCD_PLL2
+Dir.            : power
+I/O Standard    : 
+Voltage         : 1.2V
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : D14
+Pad Number      : 176
+I/O Bank        : 7
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : D15
+Pad Number      : 170
+I/O Bank        : 6
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : D16
+Pad Number      : 169
+I/O Bank        : 6
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : E1
+Pad Number      : 26
+I/O Bank        : 1
+Pin Name/Usage  : GND+
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : E2
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : GND
+Dir.            : gnd
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : E3
+Pad Number      : 
+I/O Bank        : 1
+Pin Name/Usage  : VCCIO1
+Dir.            : power
+I/O Standard    : 
+Voltage         : 3.3V
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : E4
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : GND
+Dir.            : gnd
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : E5
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : GNDA3
+Dir.            : gnd
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : E6
+Pad Number      : 231
+I/O Bank        : 8
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : E7
+Pad Number      : 227
+I/O Bank        : 8
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : E8
+Pad Number      : 218
+I/O Bank        : 8
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : E9
+Pad Number      : 205
+I/O Bank        : 7
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : E10
+Pad Number      : 184
+I/O Bank        : 7
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : E11
+Pad Number      : 183
+I/O Bank        : 7
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : E12
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : GNDA2
+Dir.            : gnd
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : E13
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : GND
+Dir.            : gnd
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : E14
+Pad Number      : 
+I/O Bank        : 6
+Pin Name/Usage  : VCCIO6
+Dir.            : power
+I/O Standard    : 
+Voltage         : 2.5V
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : E15
+Pad Number      : 151
+I/O Bank        : 6
+Pin Name/Usage  : GND+
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : E16
+Pad Number      : 150
+I/O Bank        : 6
+Pin Name/Usage  : GND+
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : F1
+Pad Number      : 14
+I/O Bank        : 1
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : F2
+Pad Number      : 13
+I/O Bank        : 1
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : F3
+Pad Number      : 8
+I/O Bank        : 1
+Pin Name/Usage  : LED[5]
+Dir.            : output
+I/O Standard    : 3.3-V LVTTL
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : Y
+Bus Hold        : no
+Weak Pull Up    : Off
+
+Location        : F4
+Pad Number      : 11
+I/O Bank        : 1
+Pin Name/Usage  : ^nSTATUS
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : F5
+Pad Number      : 
+I/O Bank        : --
+Pin Name/Usage  : VCCA3
+Dir.            : power
+I/O Standard    : 
+Voltage         : 2.5V
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : F6
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : GND
+Dir.            : gnd
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : F7
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : VCCINT
+Dir.            : power
+I/O Standard    : 
+Voltage         : 1.2V
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : F8
+Pad Number      : 219
+I/O Bank        : 8
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : F9
+Pad Number      : 197
+I/O Bank        : 7
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : F10
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : GND
+Dir.            : gnd
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : F11
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : VCCINT
+Dir.            : power
+I/O Standard    : 
+Voltage         : 1.2V
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : F12
+Pad Number      : 
+I/O Bank        : --
+Pin Name/Usage  : VCCA2
+Dir.            : power
+I/O Standard    : 
+Voltage         : 2.5V
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : F13
+Pad Number      : 161
+I/O Bank        : 6
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : F14
+Pad Number      : 167
+I/O Bank        : 6
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : F15
+Pad Number      : 163
+I/O Bank        : 6
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : F16
+Pad Number      : 162
+I/O Bank        : 6
+Pin Name/Usage  : ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN
+Dir.            : output
+I/O Standard    : 2.5 V
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : N
+Bus Hold        : no
+Weak Pull Up    : Off
+
+Location        : G1
+Pad Number      : 16
+I/O Bank        : 1
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : G2
+Pad Number      : 15
+I/O Bank        : 1
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : G3
+Pad Number      : 
+I/O Bank        : 1
+Pin Name/Usage  : VCCIO1
+Dir.            : power
+I/O Standard    : 
+Voltage         : 3.3V
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : G4
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : GND
+Dir.            : gnd
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : G5
+Pad Number      : 12
+I/O Bank        : 1
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : G6
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : VCCINT
+Dir.            : power
+I/O Standard    : 
+Voltage         : 1.2V
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : G7
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : VCCINT
+Dir.            : power
+I/O Standard    : 
+Voltage         : 1.2V
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : G8
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : VCCINT
+Dir.            : power
+I/O Standard    : 
+Voltage         : 1.2V
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : G9
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : VCCINT
+Dir.            : power
+I/O Standard    : 
+Voltage         : 1.2V
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : G10
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : VCCINT
+Dir.            : power
+I/O Standard    : 
+Voltage         : 1.2V
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : G11
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : GND
+Dir.            : gnd
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : G12
+Pad Number      : 155
+I/O Bank        : 6
+Pin Name/Usage  : ^MSEL2
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : G12
+Pad Number      : 156
+I/O Bank        : 6
+Pin Name/Usage  : ^MSEL3
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : G13
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : GND
+Dir.            : gnd
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : G14
+Pad Number      : 
+I/O Bank        : 6
+Pin Name/Usage  : VCCIO6
+Dir.            : power
+I/O Standard    : 
+Voltage         : 2.5V
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : G15
+Pad Number      : 160
+I/O Bank        : 6
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : G16
+Pad Number      : 159
+I/O Bank        : 6
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : H1
+Pad Number      : 17
+I/O Bank        : 1
+Pin Name/Usage  : ~ALTERA_DCLK~
+Dir.            : output
+I/O Standard    : 3.3-V LVTTL
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : N
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : H2
+Pad Number      : 18
+I/O Bank        : 1
+Pin Name/Usage  : ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : input
+I/O Standard    : 3.3-V LVTTL
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : N
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : H3
+Pad Number      : 21
+I/O Bank        : 1
+Pin Name/Usage  : #TCK
+Dir.            : input
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : H4
+Pad Number      : 20
+I/O Bank        : 1
+Pin Name/Usage  : #TDI
+Dir.            : input
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : H5
+Pad Number      : 19
+I/O Bank        : 1
+Pin Name/Usage  : ^nCONFIG
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : H6
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : VCCINT
+Dir.            : power
+I/O Standard    : 
+Voltage         : 1.2V
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : H7
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : GND
+Dir.            : gnd
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : H8
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : GND
+Dir.            : gnd
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : H9
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : GND
+Dir.            : gnd
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : H10
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : GND
+Dir.            : gnd
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : H11
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : VCCINT
+Dir.            : power
+I/O Standard    : 
+Voltage         : 1.2V
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : H12
+Pad Number      : 154
+I/O Bank        : 6
+Pin Name/Usage  : ^MSEL1
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : H13
+Pad Number      : 153
+I/O Bank        : 6
+Pin Name/Usage  : ^MSEL0
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : H14
+Pad Number      : 152
+I/O Bank        : 6
+Pin Name/Usage  : ^CONF_DONE
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : H15
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : GND
+Dir.            : gnd
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : H16
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : GND
+Dir.            : gnd
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : J1
+Pad Number      : 30
+I/O Bank        : 2
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : J2
+Pad Number      : 29
+I/O Bank        : 2
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : J3
+Pad Number      : 24
+I/O Bank        : 1
+Pin Name/Usage  : ^nCE
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : J4
+Pad Number      : 23
+I/O Bank        : 1
+Pin Name/Usage  : #TDO
+Dir.            : output
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : J5
+Pad Number      : 22
+I/O Bank        : 1
+Pin Name/Usage  : #TMS
+Dir.            : input
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : J6
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : VCCINT
+Dir.            : power
+I/O Standard    : 
+Voltage         : 1.2V
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : J7
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : GND
+Dir.            : gnd
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : J8
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : GND
+Dir.            : gnd
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : J9
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : GND
+Dir.            : gnd
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : J10
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : GND
+Dir.            : gnd
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : J11
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : GND
+Dir.            : gnd
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : J12
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : VCCINT
+Dir.            : power
+I/O Standard    : 
+Voltage         : 1.2V
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : J13
+Pad Number      : 146
+I/O Bank        : 5
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : J14
+Pad Number      : 144
+I/O Bank        : 5
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : J15
+Pad Number      : 143
+I/O Bank        : 5
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : J16
+Pad Number      : 142
+I/O Bank        : 5
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : K1
+Pad Number      : 37
+I/O Bank        : 2
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : K2
+Pad Number      : 36
+I/O Bank        : 2
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : K3
+Pad Number      : 
+I/O Bank        : 2
+Pin Name/Usage  : VCCIO2
+Dir.            : power
+I/O Standard    : 
+Voltage         : 3.3V
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : K4
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : GND
+Dir.            : gnd
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : K5
+Pad Number      : 45
+I/O Bank        : 2
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : K6
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : GND
+Dir.            : gnd
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : K7
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : VCCINT
+Dir.            : power
+I/O Standard    : 
+Voltage         : 1.2V
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : K8
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : GND
+Dir.            : gnd
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : K9
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : VCCINT
+Dir.            : power
+I/O Standard    : 
+Voltage         : 1.2V
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : K10
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : VCCINT
+Dir.            : power
+I/O Standard    : 
+Voltage         : 1.2V
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : K11
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : VCCINT
+Dir.            : power
+I/O Standard    : 
+Voltage         : 1.2V
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : K12
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : GND
+Dir.            : gnd
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : K13
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : GND
+Dir.            : gnd
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : K14
+Pad Number      : 
+I/O Bank        : 5
+Pin Name/Usage  : VCCIO5
+Dir.            : power
+I/O Standard    : 
+Voltage         : 2.5V
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : K15
+Pad Number      : 141
+I/O Bank        : 5
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : K16
+Pad Number      : 140
+I/O Bank        : 5
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : L1
+Pad Number      : 39
+I/O Bank        : 2
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : L2
+Pad Number      : 38
+I/O Bank        : 2
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : L3
+Pad Number      : 40
+I/O Bank        : 2
+Pin Name/Usage  : LED[7]
+Dir.            : output
+I/O Standard    : 3.3-V LVTTL
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : Y
+Bus Hold        : no
+Weak Pull Up    : Off
+
+Location        : L4
+Pad Number      : 46
+I/O Bank        : 2
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : L5
+Pad Number      : 
+I/O Bank        : --
+Pin Name/Usage  : VCCA1
+Dir.            : power
+I/O Standard    : 
+Voltage         : 2.5V
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : L6
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : VCCINT
+Dir.            : power
+I/O Standard    : 
+Voltage         : 1.2V
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : L7
+Pad Number      : 75
+I/O Bank        : 3
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : L8
+Pad Number      : 79
+I/O Bank        : 3
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : L9
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : GND
+Dir.            : gnd
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : L10
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : GND
+Dir.            : gnd
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : L11
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : GND
+Dir.            : gnd
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : L12
+Pad Number      : 
+I/O Bank        : --
+Pin Name/Usage  : VCCA4
+Dir.            : power
+I/O Standard    : 
+Voltage         : 2.5V
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : L13
+Pad Number      : 136
+I/O Bank        : 5
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : L14
+Pad Number      : 134
+I/O Bank        : 5
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : L15
+Pad Number      : 138
+I/O Bank        : 5
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : L16
+Pad Number      : 137
+I/O Bank        : 5
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : M1
+Pad Number      : 28
+I/O Bank        : 2
+Pin Name/Usage  : GND+
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : M2
+Pad Number      : 27
+I/O Bank        : 2
+Pin Name/Usage  : GND+
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : M3
+Pad Number      : 
+I/O Bank        : 2
+Pin Name/Usage  : VCCIO2
+Dir.            : power
+I/O Standard    : 
+Voltage         : 3.3V
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : M4
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : GND
+Dir.            : gnd
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : M5
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : GNDA1
+Dir.            : gnd
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : M6
+Pad Number      : 64
+I/O Bank        : 3
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : M7
+Pad Number      : 68
+I/O Bank        : 3
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : M8
+Pad Number      : 81
+I/O Bank        : 3
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : M9
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : VCCINT
+Dir.            : power
+I/O Standard    : 
+Voltage         : 1.2V
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : M10
+Pad Number      : 111
+I/O Bank        : 4
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : M11
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : VCCINT
+Dir.            : power
+I/O Standard    : 
+Voltage         : 1.2V
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : M12
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : GNDA4
+Dir.            : gnd
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : M13
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : GND
+Dir.            : gnd
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : M14
+Pad Number      : 
+I/O Bank        : 5
+Pin Name/Usage  : VCCIO5
+Dir.            : power
+I/O Standard    : 
+Voltage         : 2.5V
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : M15
+Pad Number      : 149
+I/O Bank        : 5
+Pin Name/Usage  : GND+
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : M16
+Pad Number      : 148
+I/O Bank        : 5
+Pin Name/Usage  : GND+
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : N1
+Pad Number      : 44
+I/O Bank        : 2
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : N2
+Pad Number      : 43
+I/O Bank        : 2
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : N3
+Pad Number      : 52
+I/O Bank        : 3
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : N4
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : VCCD_PLL1
+Dir.            : power
+I/O Standard    : 
+Voltage         : 1.2V
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : N5
+Pad Number      : 62
+I/O Bank        : 3
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : N6
+Pad Number      : 63
+I/O Bank        : 3
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : N7
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : GND
+Dir.            : gnd
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : N8
+Pad Number      : 82
+I/O Bank        : 3
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : N9
+Pad Number      : 93
+I/O Bank        : 4
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : N10
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : GND
+Dir.            : gnd
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : N11
+Pad Number      : 112
+I/O Bank        : 4
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : N12
+Pad Number      : 117
+I/O Bank        : 4
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : N13
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : VCCD_PLL4
+Dir.            : power
+I/O Standard    : 
+Voltage         : 1.2V
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : N14
+Pad Number      : 126
+I/O Bank        : 5
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : N15
+Pad Number      : 133
+I/O Bank        : 5
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : N16
+Pad Number      : 132
+I/O Bank        : 5
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : P1
+Pad Number      : 51
+I/O Bank        : 2
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : P2
+Pad Number      : 50
+I/O Bank        : 2
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : P3
+Pad Number      : 53
+I/O Bank        : 3
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : P4
+Pad Number      : 
+I/O Bank        : 3
+Pin Name/Usage  : VCCIO3
+Dir.            : power
+I/O Standard    : 
+Voltage         : 3.3V
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : P5
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : GND
+Dir.            : gnd
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : P6
+Pad Number      : 67
+I/O Bank        : 3
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : P7
+Pad Number      : 
+I/O Bank        : 3
+Pin Name/Usage  : VCCIO3
+Dir.            : power
+I/O Standard    : 
+Voltage         : 3.3V
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : P8
+Pad Number      : 85
+I/O Bank        : 3
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : P9
+Pad Number      : 105
+I/O Bank        : 4
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : P10
+Pad Number      : 
+I/O Bank        : 4
+Pin Name/Usage  : VCCIO4
+Dir.            : power
+I/O Standard    : 
+Voltage         : 2.5V
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : P11
+Pad Number      : 106
+I/O Bank        : 4
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : P12
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : GND
+Dir.            : gnd
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : P13
+Pad Number      : 
+I/O Bank        : 4
+Pin Name/Usage  : VCCIO4
+Dir.            : power
+I/O Standard    : 
+Voltage         : 2.5V
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : P14
+Pad Number      : 119
+I/O Bank        : 4
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : P15
+Pad Number      : 127
+I/O Bank        : 5
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : P16
+Pad Number      : 128
+I/O Bank        : 5
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : R1
+Pad Number      : 49
+I/O Bank        : 2
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : R2
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : GND
+Dir.            : gnd
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : R3
+Pad Number      : 54
+I/O Bank        : 3
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : R4
+Pad Number      : 60
+I/O Bank        : 3
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : R5
+Pad Number      : 71
+I/O Bank        : 3
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : R6
+Pad Number      : 73
+I/O Bank        : 3
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : R7
+Pad Number      : 76
+I/O Bank        : 3
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : R8
+Pad Number      : 86
+I/O Bank        : 3
+Pin Name/Usage  : CLOCK_50
+Dir.            : input
+I/O Standard    : 3.3-V LVTTL
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : Y
+Bus Hold        : no
+Weak Pull Up    : Off
+
+Location        : R9
+Pad Number      : 88
+I/O Bank        : 4
+Pin Name/Usage  : GND+
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : R10
+Pad Number      : 96
+I/O Bank        : 4
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : R11
+Pad Number      : 98
+I/O Bank        : 4
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : R12
+Pad Number      : 100
+I/O Bank        : 4
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : R13
+Pad Number      : 107
+I/O Bank        : 4
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : R14
+Pad Number      : 120
+I/O Bank        : 4
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : R15
+Pad Number      : 
+I/O Bank        : 
+Pin Name/Usage  : GND
+Dir.            : gnd
+I/O Standard    : 
+Voltage         : 
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : R16
+Pad Number      : 129
+I/O Bank        : 5
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Row I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : T1
+Pad Number      : 
+I/O Bank        : 3
+Pin Name/Usage  : VCCIO3
+Dir.            : power
+I/O Standard    : 
+Voltage         : 3.3V
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : T2
+Pad Number      : 59
+I/O Bank        : 3
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : T3
+Pad Number      : 55
+I/O Bank        : 3
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : T4
+Pad Number      : 61
+I/O Bank        : 3
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : T5
+Pad Number      : 72
+I/O Bank        : 3
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : T6
+Pad Number      : 74
+I/O Bank        : 3
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : T7
+Pad Number      : 77
+I/O Bank        : 3
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : T8
+Pad Number      : 87
+I/O Bank        : 3
+Pin Name/Usage  : GND+
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : T9
+Pad Number      : 89
+I/O Bank        : 4
+Pin Name/Usage  : GND+
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
+
+Location        : T10
+Pad Number      : 97
+I/O Bank        : 4
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : T11
+Pad Number      : 99
+I/O Bank        : 4
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : T12
+Pad Number      : 101
+I/O Bank        : 4
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : T13
+Pad Number      : 108
+I/O Bank        : 4
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : T14
+Pad Number      : 115
+I/O Bank        : 4
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : T15
+Pad Number      : 116
+I/O Bank        : 4
+Pin Name/Usage  : RESERVED_INPUT_WITH_WEAK_PULLUP
+Dir.            : 
+I/O Standard    : 
+Voltage         : 
+I/O Type        : Column I/O
+User Assignment : 
+Bus Hold        : no
+Weak Pull Up    : On
+
+Location        : T16
+Pad Number      : 
+I/O Bank        : 4
+Pin Name/Usage  : VCCIO4
+Dir.            : power
+I/O Standard    : 
+Voltage         : 2.5V
+I/O Type        : --
+User Assignment : 
+Bus Hold        : --
+Weak Pull Up    : --
++--------------------------------------------------------------------------------+
+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++--------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                          ;
++--------------------------------------------------------------------------------+
+Compilation Hierarchy Node : |spectrum
+Logic Cells                : 35 (35)
+Dedicated Logic Registers  : 35 (35)
+I/O Registers              : 0 (0)
+Memory Bits                : 0
+M9Ks                       : 0
+DSP Elements               : 0
+DSP 9x9                    : 0
+DSP 18x18                  : 0
+Pins                       : 9
+Virtual Pins               : 0
+LUT-Only LCs               : 0 (0)
+Register-Only LCs          : 7 (7)
+LUT/Register LCs           : 28 (28)
+Full Hierarchy Name        : |spectrum
+Library Name               : work
++--------------------------------------------------------------------------------+
+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++--------------------------------------------------------------------------------+
+; Delay Chain Summary                                                            ;
++--------------------------------------------------------------------------------+
+Name                  : LED[0]
+Pin Type              : Output
+Pad to Core 0         : --
+Pad to Core 1         : --
+Pad to Input Register : --
+TCO                   : --
+TCOE                  : --
+
+Name                  : LED[1]
+Pin Type              : Output
+Pad to Core 0         : --
+Pad to Core 1         : --
+Pad to Input Register : --
+TCO                   : --
+TCOE                  : --
+
+Name                  : LED[2]
+Pin Type              : Output
+Pad to Core 0         : --
+Pad to Core 1         : --
+Pad to Input Register : --
+TCO                   : --
+TCOE                  : --
+
+Name                  : LED[3]
+Pin Type              : Output
+Pad to Core 0         : --
+Pad to Core 1         : --
+Pad to Input Register : --
+TCO                   : --
+TCOE                  : --
+
+Name                  : LED[4]
+Pin Type              : Output
+Pad to Core 0         : --
+Pad to Core 1         : --
+Pad to Input Register : --
+TCO                   : --
+TCOE                  : --
+
+Name                  : LED[5]
+Pin Type              : Output
+Pad to Core 0         : --
+Pad to Core 1         : --
+Pad to Input Register : --
+TCO                   : --
+TCOE                  : --
+
+Name                  : LED[6]
+Pin Type              : Output
+Pad to Core 0         : --
+Pad to Core 1         : --
+Pad to Input Register : --
+TCO                   : --
+TCOE                  : --
+
+Name                  : LED[7]
+Pin Type              : Output
+Pad to Core 0         : --
+Pad to Core 1         : --
+Pad to Input Register : --
+TCO                   : --
+TCOE                  : --
+
+Name                  : CLOCK_50
+Pin Type              : Input
+Pad to Core 0         : (0) 0 ps
+Pad to Core 1         : --
+Pad to Input Register : --
+TCO                   : --
+TCOE                  : --
++--------------------------------------------------------------------------------+
+
+
+
++--------------------------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout                                                 ;
++--------------------------------------------------------------------------------+
+Source Pin / Fanout : CLOCK_50
+Pad To Core Index   :  
+Setting             :  
++--------------------------------------------------------------------------------+
+
+
+
++--------------------------------------------------------------------------------+
+; Control Signals                                                                ;
++--------------------------------------------------------------------------------+
+Name                      : CLOCK_50
+Location                  : PIN_R8
+Fan-Out                   : 35
+Usage                     : Clock
+Global                    : yes
+Global Resource Used      : Global Clock
+Global Line Name          : GCLK18
+Enable Signal Source Name : --
++--------------------------------------------------------------------------------+
+
+
+
++--------------------------------------------------------------------------------+
+; Global & Other Fast Signals                                                    ;
++--------------------------------------------------------------------------------+
+Name                                 : CLOCK_50
+Location                             : PIN_R8
+Fan-Out                              : 35
+Fan-Out Using Intentional Clock Skew : 12
+Global Resource Used                 : Global Clock
+Global Line Name                     : GCLK18
+Enable Signal Source Name            : --
++--------------------------------------------------------------------------------+
+
+
+
++---------------------------------+
+; Non-Global High Fan-Out Signals ;
++----------------+----------------+
+; Name           ; Fan-Out        ;
++----------------+----------------+
+; counter[0]     ; 2              ;
+; counter[27]    ; 2              ;
+; counter[26]    ; 2              ;
+; counter[25]    ; 2              ;
+; counter[24]    ; 2              ;
+; counter[23]    ; 2              ;
+; counter[22]    ; 2              ;
+; counter[21]    ; 2              ;
+; counter[0]~81  ; 1              ;
+; LED[6]~reg0    ; 1              ;
+; LED[5]~reg0    ; 1              ;
+; LED[4]~reg0    ; 1              ;
+; LED[3]~reg0    ; 1              ;
+; LED[2]~reg0    ; 1              ;
+; LED[1]~reg0    ; 1              ;
+; LED[0]~reg0    ; 1              ;
+; counter[27]~79 ; 1              ;
+; counter[26]~78 ; 1              ;
+; counter[26]~77 ; 1              ;
+; counter[25]~76 ; 1              ;
+; counter[25]~75 ; 1              ;
+; counter[24]~74 ; 1              ;
+; counter[24]~73 ; 1              ;
+; counter[23]~72 ; 1              ;
+; counter[23]~71 ; 1              ;
+; counter[22]~70 ; 1              ;
+; counter[22]~69 ; 1              ;
+; counter[21]~68 ; 1              ;
+; counter[21]~67 ; 1              ;
+; counter[20]~66 ; 1              ;
+; counter[20]~65 ; 1              ;
+; counter[19]~64 ; 1              ;
+; counter[19]~63 ; 1              ;
+; counter[18]~62 ; 1              ;
+; counter[18]~61 ; 1              ;
+; counter[17]~60 ; 1              ;
+; counter[17]~59 ; 1              ;
+; counter[16]~58 ; 1              ;
+; counter[16]~57 ; 1              ;
+; counter[15]~56 ; 1              ;
+; counter[15]~55 ; 1              ;
+; counter[14]~54 ; 1              ;
+; counter[14]~53 ; 1              ;
+; counter[13]~52 ; 1              ;
+; counter[13]~51 ; 1              ;
+; counter[12]~50 ; 1              ;
+; counter[12]~49 ; 1              ;
+; counter[11]~48 ; 1              ;
+; counter[11]~47 ; 1              ;
+; counter[10]~46 ; 1              ;
+; counter[10]~45 ; 1              ;
+; counter[9]~44  ; 1              ;
+; counter[9]~43  ; 1              ;
+; counter[8]~42  ; 1              ;
+; counter[8]~41  ; 1              ;
+; counter[7]~40  ; 1              ;
+; counter[7]~39  ; 1              ;
+; counter[6]~38  ; 1              ;
+; counter[6]~37  ; 1              ;
+; counter[5]~36  ; 1              ;
+; counter[5]~35  ; 1              ;
+; counter[4]~34  ; 1              ;
+; counter[4]~33  ; 1              ;
+; counter[3]~32  ; 1              ;
+; counter[3]~31  ; 1              ;
+; counter[2]~30  ; 1              ;
+; counter[2]~29  ; 1              ;
+; counter[1]~28  ; 1              ;
+; counter[1]~27  ; 1              ;
+; counter[1]     ; 1              ;
+; counter[2]     ; 1              ;
+; counter[3]     ; 1              ;
+; counter[4]     ; 1              ;
+; counter[5]     ; 1              ;
+; counter[6]     ; 1              ;
+; counter[7]     ; 1              ;
+; counter[8]     ; 1              ;
+; counter[9]     ; 1              ;
+; counter[10]    ; 1              ;
+; counter[11]    ; 1              ;
+; counter[12]    ; 1              ;
+; counter[13]    ; 1              ;
+; counter[14]    ; 1              ;
+; counter[15]    ; 1              ;
+; counter[16]    ; 1              ;
+; counter[17]    ; 1              ;
+; counter[18]    ; 1              ;
+; counter[19]    ; 1              ;
+; counter[20]    ; 1              ;
++----------------+----------------+
+
+
++-----------------------------------------------+
+; Routing Usage Summary                         ;
++-----------------------+-----------------------+
+; Routing Resource Type ; Usage                 ;
++-----------------------+-----------------------+
+; Block interconnects   ; 16 / 71,559 ( < 1 % ) ;
+; C16 interconnects     ; 0 / 2,597 ( 0 % )     ;
+; C4 interconnects      ; 9 / 46,848 ( < 1 % )  ;
+; Direct links          ; 4 / 71,559 ( < 1 % )  ;
+; Global clocks         ; 1 / 20 ( 5 % )        ;
+; Local interconnects   ; 28 / 24,624 ( < 1 % ) ;
+; R24 interconnects     ; 4 / 2,496 ( < 1 % )   ;
+; R4 interconnects      ; 17 / 62,424 ( < 1 % ) ;
++-----------------------+-----------------------+
+
+
++--------------------------------------------------------------------------+
+; LAB Logic Elements                                                       ;
++--------------------------------------------+-----------------------------+
+; Number of Logic Elements  (Average = 7.00) ; Number of LABs  (Total = 5) ;
++--------------------------------------------+-----------------------------+
+; 1                                          ; 1                           ;
+; 2                                          ; 1                           ;
+; 3                                          ; 0                           ;
+; 4                                          ; 1                           ;
+; 5                                          ; 0                           ;
+; 6                                          ; 0                           ;
+; 7                                          ; 0                           ;
+; 8                                          ; 0                           ;
+; 9                                          ; 0                           ;
+; 10                                         ; 0                           ;
+; 11                                         ; 0                           ;
+; 12                                         ; 0                           ;
+; 13                                         ; 0                           ;
+; 14                                         ; 2                           ;
+; 15                                         ; 0                           ;
+; 16                                         ; 0                           ;
++--------------------------------------------+-----------------------------+
+
+
++------------------------------------------------------------------+
+; LAB-wide Signals                                                 ;
++------------------------------------+-----------------------------+
+; LAB-wide Signals  (Average = 1.00) ; Number of LABs  (Total = 5) ;
++------------------------------------+-----------------------------+
+; 1 Clock                            ; 5                           ;
++------------------------------------+-----------------------------+
+
+
++----------------------------------------------------------------------------+
+; LAB Signals Sourced                                                        ;
++----------------------------------------------+-----------------------------+
+; Number of Signals Sourced  (Average = 14.00) ; Number of LABs  (Total = 5) ;
++----------------------------------------------+-----------------------------+
+; 0                                            ; 0                           ;
+; 1                                            ; 0                           ;
+; 2                                            ; 1                           ;
+; 3                                            ; 0                           ;
+; 4                                            ; 1                           ;
+; 5                                            ; 0                           ;
+; 6                                            ; 0                           ;
+; 7                                            ; 0                           ;
+; 8                                            ; 1                           ;
+; 9                                            ; 0                           ;
+; 10                                           ; 0                           ;
+; 11                                           ; 0                           ;
+; 12                                           ; 0                           ;
+; 13                                           ; 0                           ;
+; 14                                           ; 0                           ;
+; 15                                           ; 0                           ;
+; 16                                           ; 0                           ;
+; 17                                           ; 0                           ;
+; 18                                           ; 0                           ;
+; 19                                           ; 0                           ;
+; 20                                           ; 0                           ;
+; 21                                           ; 0                           ;
+; 22                                           ; 0                           ;
+; 23                                           ; 0                           ;
+; 24                                           ; 0                           ;
+; 25                                           ; 0                           ;
+; 26                                           ; 0                           ;
+; 27                                           ; 0                           ;
+; 28                                           ; 2                           ;
++----------------------------------------------+-----------------------------+
+
+
++-------------------------------------------------------------------------------+
+; LAB Signals Sourced Out                                                       ;
++-------------------------------------------------+-----------------------------+
+; Number of Signals Sourced Out  (Average = 2.80) ; Number of LABs  (Total = 5) ;
++-------------------------------------------------+-----------------------------+
+; 0                                               ; 1                           ;
+; 1                                               ; 1                           ;
+; 2                                               ; 1                           ;
+; 3                                               ; 0                           ;
+; 4                                               ; 1                           ;
+; 5                                               ; 0                           ;
+; 6                                               ; 0                           ;
+; 7                                               ; 1                           ;
++-------------------------------------------------+-----------------------------+
+
+
++---------------------------------------------------------------------------+
+; LAB Distinct Inputs                                                       ;
++---------------------------------------------+-----------------------------+
+; Number of Distinct Inputs  (Average = 2.60) ; Number of LABs  (Total = 5) ;
++---------------------------------------------+-----------------------------+
+; 0                                           ; 0                           ;
+; 1                                           ; 1                           ;
+; 2                                           ; 2                           ;
+; 3                                           ; 1                           ;
+; 4                                           ; 0                           ;
+; 5                                           ; 1                           ;
++---------------------------------------------+-----------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary                        ;
++----------------------------------+-------+
+; I/O Rules Statistic              ; Total ;
++----------------------------------+-------+
+; Total I/O Rules                  ; 30    ;
+; Number of I/O Rules Passed       ; 9     ;
+; Number of I/O Rules Failed       ; 0     ;
+; Number of I/O Rules Unchecked    ; 0     ;
+; Number of I/O Rules Inapplicable ; 21    ;
++----------------------------------+-------+
+
+
++--------------------------------------------------------------------------------+
+; I/O Rules Details                                                              ;
++--------------------------------------------------------------------------------+
+Status            : Pass
+ID                : IO_000001
+Category          : Capacity Checks
+Rule Description  : Number of pins in an I/O bank should not exceed the number of locations available.
+Severity          : Critical
+Information       : 0 such failures found.
+Area              : I/O
+Extra Information : 
+
+Status            : Inapplicable
+ID                : IO_000002
+Category          : Capacity Checks
+Rule Description  : Number of clocks in an I/O bank should not exceed the number of clocks available.
+Severity          : Critical
+Information       : No Global Signal assignments found.
+Area              : I/O
+Extra Information : 
+
+Status            : Pass
+ID                : IO_000003
+Category          : Capacity Checks
+Rule Description  : Number of pins in a Vrefgroup should not exceed the number of locations available.
+Severity          : Critical
+Information       : 0 such failures found.
+Area              : I/O
+Extra Information : 
+
+Status            : Inapplicable
+ID                : IO_000004
+Category          : Voltage Compatibility Checks
+Rule Description  : The I/O bank should support the requested VCCIO.
+Severity          : Critical
+Information       : No IOBANK_VCCIO assignments found.
+Area              : I/O
+Extra Information : 
+
+Status            : Inapplicable
+ID                : IO_000005
+Category          : Voltage Compatibility Checks
+Rule Description  : The I/O bank should not have competing VREF values.
+Severity          : Critical
+Information       : No VREF I/O Standard assignments found.
+Area              : I/O
+Extra Information : 
+
+Status            : Pass
+ID                : IO_000006
+Category          : Voltage Compatibility Checks
+Rule Description  : The I/O bank should not have competing VCCIO values.
+Severity          : Critical
+Information       : 0 such failures found.
+Area              : I/O
+Extra Information : 
+
+Status            : Pass
+ID                : IO_000007
+Category          : Valid Location Checks
+Rule Description  : Checks for unavailable locations.
+Severity          : Critical
+Information       : 0 such failures found.
+Area              : I/O
+Extra Information : 
+
+Status            : Inapplicable
+ID                : IO_000008
+Category          : Valid Location Checks
+Rule Description  : Checks for reserved locations.
+Severity          : Critical
+Information       : No reserved LogicLock region found.
+Area              : I/O
+Extra Information : 
+
+Status            : Pass
+ID                : IO_000009
+Category          : I/O Properties Checks for One I/O
+Rule Description  : The location should support the requested I/O standard.
+Severity          : Critical
+Information       : 0 such failures found.
+Area              : I/O
+Extra Information : 
+
+Status            : Pass
+ID                : IO_000010
+Category          : I/O Properties Checks for One I/O
+Rule Description  : The location should support the requested I/O direction.
+Severity          : Critical
+Information       : 0 such failures found.
+Area              : I/O
+Extra Information : 
+
+Status            : Inapplicable
+ID                : IO_000011
+Category          : I/O Properties Checks for One I/O
+Rule Description  : The location should support the requested Current Strength.
+Severity          : Critical
+Information       : No Current Strength assignments found.
+Area              : I/O
+Extra Information : 
+
+Status            : Inapplicable
+ID                : IO_000012
+Category          : I/O Properties Checks for One I/O
+Rule Description  : The location should support the requested On Chip Termination value.
+Severity          : Critical
+Information       : No Termination assignments found.
+Area              : I/O
+Extra Information : 
+
+Status            : Inapplicable
+ID                : IO_000013
+Category          : I/O Properties Checks for One I/O
+Rule Description  : The location should support the requested Bus Hold value.
+Severity          : Critical
+Information       : No Enable Bus-Hold Circuitry assignments found.
+Area              : I/O
+Extra Information : 
+
+Status            : Inapplicable
+ID                : IO_000014
+Category          : I/O Properties Checks for One I/O
+Rule Description  : The location should support the requested Weak Pull Up value.
+Severity          : Critical
+Information       : No Weak Pull-Up Resistor assignments found.
+Area              : I/O
+Extra Information : 
+
+Status            : Pass
+ID                : IO_000015
+Category          : I/O Properties Checks for One I/O
+Rule Description  : The location should support the requested PCI Clamp Diode.
+Severity          : Critical
+Information       : 0 such failures found.
+Area              : I/O
+Extra Information : 
+
+Status            : Inapplicable
+ID                : IO_000018
+Category          : I/O Properties Checks for One I/O
+Rule Description  : The I/O standard should support the requested Current Strength.
+Severity          : Critical
+Information       : No Current Strength assignments found.
+Area              : I/O
+Extra Information : 
+
+Status            : Inapplicable
+ID                : IO_000019
+Category          : I/O Properties Checks for One I/O
+Rule Description  : The I/O standard should support the requested On Chip Termination value.
+Severity          : Critical
+Information       : No Termination assignments found.
+Area              : I/O
+Extra Information : 
+
+Status            : Pass
+ID                : IO_000020
+Category          : I/O Properties Checks for One I/O
+Rule Description  : The I/O standard should support the requested PCI Clamp Diode.
+Severity          : Critical
+Information       : 0 such failures found.
+Area              : I/O
+Extra Information : 
+
+Status            : Inapplicable
+ID                : IO_000021
+Category          : I/O Properties Checks for One I/O
+Rule Description  : The I/O standard should support the requested Weak Pull Up value.
+Severity          : Critical
+Information       : No Weak Pull-Up Resistor assignments found.
+Area              : I/O
+Extra Information : 
+
+Status            : Inapplicable
+ID                : IO_000022
+Category          : I/O Properties Checks for One I/O
+Rule Description  : The I/O standard should support the requested Bus Hold value.
+Severity          : Critical
+Information       : No Enable Bus-Hold Circuitry assignments found.
+Area              : I/O
+Extra Information : 
+
+Status            : Inapplicable
+ID                : IO_000023
+Category          : I/O Properties Checks for One I/O
+Rule Description  : The I/O standard should support the Open Drain value.
+Severity          : Critical
+Information       : No open drain assignments found.
+Area              : I/O
+Extra Information : 
+
+Status            : Inapplicable
+ID                : IO_000024
+Category          : I/O Properties Checks for One I/O
+Rule Description  : The I/O direction should support the On Chip Termination value.
+Severity          : Critical
+Information       : No Termination assignments found.
+Area              : I/O
+Extra Information : 
+
+Status            : Inapplicable
+ID                : IO_000026
+Category          : I/O Properties Checks for One I/O
+Rule Description  : On Chip Termination and Current Strength should not be used at the same time.
+Severity          : Critical
+Information       : No Current Strength or Termination assignments found.
+Area              : I/O
+Extra Information : 
+
+Status            : Inapplicable
+ID                : IO_000027
+Category          : I/O Properties Checks for One I/O
+Rule Description  : Weak Pull Up and Bus Hold should not be used at the same time.
+Severity          : Critical
+Information       : No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.
+Area              : I/O
+Extra Information : 
+
+Status            : Inapplicable
+ID                : IO_000045
+Category          : I/O Properties Checks for One I/O
+Rule Description  : The I/O standard should support the requested Slew Rate value.
+Severity          : Critical
+Information       : No Slew Rate assignments found.
+Area              : I/O
+Extra Information : 
+
+Status            : Inapplicable
+ID                : IO_000046
+Category          : I/O Properties Checks for One I/O
+Rule Description  : The location should support the requested Slew Rate value.
+Severity          : Critical
+Information       : No Slew Rate assignments found.
+Area              : I/O
+Extra Information : 
+
+Status            : Inapplicable
+ID                : IO_000047
+Category          : I/O Properties Checks for One I/O
+Rule Description  : On Chip Termination and Slew Rate should not be used at the same time.
+Severity          : Critical
+Information       : No Slew Rate assignments found.
+Area              : I/O
+Extra Information : 
+
+Status            : Pass
+ID                : IO_000033
+Category          : Electromigration Checks
+Rule Description  : Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.
+Severity          : Critical
+Information       : 0 such failures found.
+Area              : I/O
+Extra Information : 
+
+Status            : Inapplicable
+ID                : IO_000034
+Category          : SI Related Distance Checks
+Rule Description  : Single-ended outputs should be 5 LAB row(s) away from a differential I/O.
+Severity          : High
+Information       : No Differential I/O Standard assignments found.
+Area              : I/O
+Extra Information : 
+
+Status            : Inapplicable
+ID                : IO_000042
+Category          : SI Related SSO Limit Checks
+Rule Description  : No more than 20 outputs are allowed in a VREF group when VREF is being read from.
+Severity          : High
+Information       : No VREF I/O Standard assignments found.
+Area              : I/O
+Extra Information : 
++--------------------------------------------------------------------------------+
+
+
+
++--------------------------------------------------------------------------------+
+; I/O Rules Matrix                                                               ;
++--------------------------------------------------------------------------------+
+Pin/Rules : Total Pass
+IO_000001 : 9
+IO_000002 : 0
+IO_000003 : 9
+IO_000004 : 0
+IO_000005 : 0
+IO_000006 : 9
+IO_000007 : 9
+IO_000008 : 0
+IO_000009 : 9
+IO_000010 : 9
+IO_000011 : 0
+IO_000012 : 0
+IO_000013 : 0
+IO_000014 : 0
+IO_000015 : 1
+IO_000018 : 0
+IO_000019 : 0
+IO_000020 : 1
+IO_000021 : 0
+IO_000022 : 0
+IO_000023 : 0
+IO_000024 : 0
+IO_000026 : 0
+IO_000027 : 0
+IO_000045 : 0
+IO_000046 : 0
+IO_000047 : 0
+IO_000033 : 9
+IO_000034 : 0
+IO_000042 : 0
+
+Pin/Rules : Total Unchecked
+IO_000001 : 0
+IO_000002 : 0
+IO_000003 : 0
+IO_000004 : 0
+IO_000005 : 0
+IO_000006 : 0
+IO_000007 : 0
+IO_000008 : 0
+IO_000009 : 0
+IO_000010 : 0
+IO_000011 : 0
+IO_000012 : 0
+IO_000013 : 0
+IO_000014 : 0
+IO_000015 : 0
+IO_000018 : 0
+IO_000019 : 0
+IO_000020 : 0
+IO_000021 : 0
+IO_000022 : 0
+IO_000023 : 0
+IO_000024 : 0
+IO_000026 : 0
+IO_000027 : 0
+IO_000045 : 0
+IO_000046 : 0
+IO_000047 : 0
+IO_000033 : 0
+IO_000034 : 0
+IO_000042 : 0
+
+Pin/Rules : Total Inapplicable
+IO_000001 : 0
+IO_000002 : 9
+IO_000003 : 0
+IO_000004 : 9
+IO_000005 : 9
+IO_000006 : 0
+IO_000007 : 0
+IO_000008 : 9
+IO_000009 : 0
+IO_000010 : 0
+IO_000011 : 9
+IO_000012 : 9
+IO_000013 : 9
+IO_000014 : 9
+IO_000015 : 8
+IO_000018 : 9
+IO_000019 : 9
+IO_000020 : 8
+IO_000021 : 9
+IO_000022 : 9
+IO_000023 : 9
+IO_000024 : 9
+IO_000026 : 9
+IO_000027 : 9
+IO_000045 : 9
+IO_000046 : 9
+IO_000047 : 9
+IO_000033 : 0
+IO_000034 : 9
+IO_000042 : 9
+
+Pin/Rules : Total Fail
+IO_000001 : 0
+IO_000002 : 0
+IO_000003 : 0
+IO_000004 : 0
+IO_000005 : 0
+IO_000006 : 0
+IO_000007 : 0
+IO_000008 : 0
+IO_000009 : 0
+IO_000010 : 0
+IO_000011 : 0
+IO_000012 : 0
+IO_000013 : 0
+IO_000014 : 0
+IO_000015 : 0
+IO_000018 : 0
+IO_000019 : 0
+IO_000020 : 0
+IO_000021 : 0
+IO_000022 : 0
+IO_000023 : 0
+IO_000024 : 0
+IO_000026 : 0
+IO_000027 : 0
+IO_000045 : 0
+IO_000046 : 0
+IO_000047 : 0
+IO_000033 : 0
+IO_000034 : 0
+IO_000042 : 0
+
+Pin/Rules : LED[0]
+IO_000001 : Pass
+IO_000002 : Inapplicable
+IO_000003 : Pass
+IO_000004 : Inapplicable
+IO_000005 : Inapplicable
+IO_000006 : Pass
+IO_000007 : Pass
+IO_000008 : Inapplicable
+IO_000009 : Pass
+IO_000010 : Pass
+IO_000011 : Inapplicable
+IO_000012 : Inapplicable
+IO_000013 : Inapplicable
+IO_000014 : Inapplicable
+IO_000015 : Inapplicable
+IO_000018 : Inapplicable
+IO_000019 : Inapplicable
+IO_000020 : Inapplicable
+IO_000021 : Inapplicable
+IO_000022 : Inapplicable
+IO_000023 : Inapplicable
+IO_000024 : Inapplicable
+IO_000026 : Inapplicable
+IO_000027 : Inapplicable
+IO_000045 : Inapplicable
+IO_000046 : Inapplicable
+IO_000047 : Inapplicable
+IO_000033 : Pass
+IO_000034 : Inapplicable
+IO_000042 : Inapplicable
+
+Pin/Rules : LED[1]
+IO_000001 : Pass
+IO_000002 : Inapplicable
+IO_000003 : Pass
+IO_000004 : Inapplicable
+IO_000005 : Inapplicable
+IO_000006 : Pass
+IO_000007 : Pass
+IO_000008 : Inapplicable
+IO_000009 : Pass
+IO_000010 : Pass
+IO_000011 : Inapplicable
+IO_000012 : Inapplicable
+IO_000013 : Inapplicable
+IO_000014 : Inapplicable
+IO_000015 : Inapplicable
+IO_000018 : Inapplicable
+IO_000019 : Inapplicable
+IO_000020 : Inapplicable
+IO_000021 : Inapplicable
+IO_000022 : Inapplicable
+IO_000023 : Inapplicable
+IO_000024 : Inapplicable
+IO_000026 : Inapplicable
+IO_000027 : Inapplicable
+IO_000045 : Inapplicable
+IO_000046 : Inapplicable
+IO_000047 : Inapplicable
+IO_000033 : Pass
+IO_000034 : Inapplicable
+IO_000042 : Inapplicable
+
+Pin/Rules : LED[2]
+IO_000001 : Pass
+IO_000002 : Inapplicable
+IO_000003 : Pass
+IO_000004 : Inapplicable
+IO_000005 : Inapplicable
+IO_000006 : Pass
+IO_000007 : Pass
+IO_000008 : Inapplicable
+IO_000009 : Pass
+IO_000010 : Pass
+IO_000011 : Inapplicable
+IO_000012 : Inapplicable
+IO_000013 : Inapplicable
+IO_000014 : Inapplicable
+IO_000015 : Inapplicable
+IO_000018 : Inapplicable
+IO_000019 : Inapplicable
+IO_000020 : Inapplicable
+IO_000021 : Inapplicable
+IO_000022 : Inapplicable
+IO_000023 : Inapplicable
+IO_000024 : Inapplicable
+IO_000026 : Inapplicable
+IO_000027 : Inapplicable
+IO_000045 : Inapplicable
+IO_000046 : Inapplicable
+IO_000047 : Inapplicable
+IO_000033 : Pass
+IO_000034 : Inapplicable
+IO_000042 : Inapplicable
+
+Pin/Rules : LED[3]
+IO_000001 : Pass
+IO_000002 : Inapplicable
+IO_000003 : Pass
+IO_000004 : Inapplicable
+IO_000005 : Inapplicable
+IO_000006 : Pass
+IO_000007 : Pass
+IO_000008 : Inapplicable
+IO_000009 : Pass
+IO_000010 : Pass
+IO_000011 : Inapplicable
+IO_000012 : Inapplicable
+IO_000013 : Inapplicable
+IO_000014 : Inapplicable
+IO_000015 : Inapplicable
+IO_000018 : Inapplicable
+IO_000019 : Inapplicable
+IO_000020 : Inapplicable
+IO_000021 : Inapplicable
+IO_000022 : Inapplicable
+IO_000023 : Inapplicable
+IO_000024 : Inapplicable
+IO_000026 : Inapplicable
+IO_000027 : Inapplicable
+IO_000045 : Inapplicable
+IO_000046 : Inapplicable
+IO_000047 : Inapplicable
+IO_000033 : Pass
+IO_000034 : Inapplicable
+IO_000042 : Inapplicable
+
+Pin/Rules : LED[4]
+IO_000001 : Pass
+IO_000002 : Inapplicable
+IO_000003 : Pass
+IO_000004 : Inapplicable
+IO_000005 : Inapplicable
+IO_000006 : Pass
+IO_000007 : Pass
+IO_000008 : Inapplicable
+IO_000009 : Pass
+IO_000010 : Pass
+IO_000011 : Inapplicable
+IO_000012 : Inapplicable
+IO_000013 : Inapplicable
+IO_000014 : Inapplicable
+IO_000015 : Inapplicable
+IO_000018 : Inapplicable
+IO_000019 : Inapplicable
+IO_000020 : Inapplicable
+IO_000021 : Inapplicable
+IO_000022 : Inapplicable
+IO_000023 : Inapplicable
+IO_000024 : Inapplicable
+IO_000026 : Inapplicable
+IO_000027 : Inapplicable
+IO_000045 : Inapplicable
+IO_000046 : Inapplicable
+IO_000047 : Inapplicable
+IO_000033 : Pass
+IO_000034 : Inapplicable
+IO_000042 : Inapplicable
+
+Pin/Rules : LED[5]
+IO_000001 : Pass
+IO_000002 : Inapplicable
+IO_000003 : Pass
+IO_000004 : Inapplicable
+IO_000005 : Inapplicable
+IO_000006 : Pass
+IO_000007 : Pass
+IO_000008 : Inapplicable
+IO_000009 : Pass
+IO_000010 : Pass
+IO_000011 : Inapplicable
+IO_000012 : Inapplicable
+IO_000013 : Inapplicable
+IO_000014 : Inapplicable
+IO_000015 : Inapplicable
+IO_000018 : Inapplicable
+IO_000019 : Inapplicable
+IO_000020 : Inapplicable
+IO_000021 : Inapplicable
+IO_000022 : Inapplicable
+IO_000023 : Inapplicable
+IO_000024 : Inapplicable
+IO_000026 : Inapplicable
+IO_000027 : Inapplicable
+IO_000045 : Inapplicable
+IO_000046 : Inapplicable
+IO_000047 : Inapplicable
+IO_000033 : Pass
+IO_000034 : Inapplicable
+IO_000042 : Inapplicable
+
+Pin/Rules : LED[6]
+IO_000001 : Pass
+IO_000002 : Inapplicable
+IO_000003 : Pass
+IO_000004 : Inapplicable
+IO_000005 : Inapplicable
+IO_000006 : Pass
+IO_000007 : Pass
+IO_000008 : Inapplicable
+IO_000009 : Pass
+IO_000010 : Pass
+IO_000011 : Inapplicable
+IO_000012 : Inapplicable
+IO_000013 : Inapplicable
+IO_000014 : Inapplicable
+IO_000015 : Inapplicable
+IO_000018 : Inapplicable
+IO_000019 : Inapplicable
+IO_000020 : Inapplicable
+IO_000021 : Inapplicable
+IO_000022 : Inapplicable
+IO_000023 : Inapplicable
+IO_000024 : Inapplicable
+IO_000026 : Inapplicable
+IO_000027 : Inapplicable
+IO_000045 : Inapplicable
+IO_000046 : Inapplicable
+IO_000047 : Inapplicable
+IO_000033 : Pass
+IO_000034 : Inapplicable
+IO_000042 : Inapplicable
+
+Pin/Rules : LED[7]
+IO_000001 : Pass
+IO_000002 : Inapplicable
+IO_000003 : Pass
+IO_000004 : Inapplicable
+IO_000005 : Inapplicable
+IO_000006 : Pass
+IO_000007 : Pass
+IO_000008 : Inapplicable
+IO_000009 : Pass
+IO_000010 : Pass
+IO_000011 : Inapplicable
+IO_000012 : Inapplicable
+IO_000013 : Inapplicable
+IO_000014 : Inapplicable
+IO_000015 : Inapplicable
+IO_000018 : Inapplicable
+IO_000019 : Inapplicable
+IO_000020 : Inapplicable
+IO_000021 : Inapplicable
+IO_000022 : Inapplicable
+IO_000023 : Inapplicable
+IO_000024 : Inapplicable
+IO_000026 : Inapplicable
+IO_000027 : Inapplicable
+IO_000045 : Inapplicable
+IO_000046 : Inapplicable
+IO_000047 : Inapplicable
+IO_000033 : Pass
+IO_000034 : Inapplicable
+IO_000042 : Inapplicable
+
+Pin/Rules : CLOCK_50
+IO_000001 : Pass
+IO_000002 : Inapplicable
+IO_000003 : Pass
+IO_000004 : Inapplicable
+IO_000005 : Inapplicable
+IO_000006 : Pass
+IO_000007 : Pass
+IO_000008 : Inapplicable
+IO_000009 : Pass
+IO_000010 : Pass
+IO_000011 : Inapplicable
+IO_000012 : Inapplicable
+IO_000013 : Inapplicable
+IO_000014 : Inapplicable
+IO_000015 : Pass
+IO_000018 : Inapplicable
+IO_000019 : Inapplicable
+IO_000020 : Pass
+IO_000021 : Inapplicable
+IO_000022 : Inapplicable
+IO_000023 : Inapplicable
+IO_000024 : Inapplicable
+IO_000026 : Inapplicable
+IO_000027 : Inapplicable
+IO_000045 : Inapplicable
+IO_000046 : Inapplicable
+IO_000047 : Inapplicable
+IO_000033 : Pass
+IO_000034 : Inapplicable
+IO_000042 : Inapplicable
++--------------------------------------------------------------------------------+
+
+
+
++---------------------------------------------------------------------------------------------+
+; Fitter Device Options                                                                       ;
++------------------------------------------------------------------+--------------------------+
+; Option                                                           ; Setting                  ;
++------------------------------------------------------------------+--------------------------+
+; Enable user-supplied start-up clock (CLKUSR)                     ; Off                      ;
+; Enable device-wide reset (DEV_CLRn)                              ; Off                      ;
+; Enable device-wide output enable (DEV_OE)                        ; Off                      ;
+; Enable INIT_DONE output                                          ; Off                      ;
+; Configuration scheme                                             ; Active Serial            ;
+; Error detection CRC                                              ; Off                      ;
+; Enable open drain on CRC_ERROR pin                               ; Off                      ;
+; Enable input tri-state on active configuration pins in user mode ; Off                      ;
+; Configuration Voltage Level                                      ; Auto                     ;
+; Force Configuration Voltage Level                                ; Off                      ;
+; nCEO                                                             ; As output driving ground ;
+; Data[0]                                                          ; As input tri-stated      ;
+; Data[1]/ASDO                                                     ; As input tri-stated      ;
+; Data[7..2]                                                       ; Unreserved               ;
+; FLASH_nCE/nCSO                                                   ; As input tri-stated      ;
+; Other Active Parallel pins                                       ; Unreserved               ;
+; DCLK                                                             ; As output driving ground ;
+; Base pin-out file on sameframe device                            ; Off                      ;
++------------------------------------------------------------------+--------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions  ;
++---------------------------+--------+
+; Setting                   ; Value  ;
++---------------------------+--------+
+; Nominal Core Voltage      ; 1.20 V ;
+; Low Junction Temperature  ; 0 °C   ;
+; High Junction Temperature ; 85 °C  ;
++---------------------------+--------+
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Warning (20028): Parallel compilation is not licensed and has been disabled
+Info (119006): Selected device EP4CE22F17C6 for design "spectrum"
+Info (21077): Core supply voltage is 1.2V
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
+Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
+    Info (176445): Device EP4CE10F17C6 is compatible
+    Info (176445): Device EP4CE6F17C6 is compatible
+    Info (176445): Device EP4CE15F17C6 is compatible
+Info (169124): Fitter converted 5 user pins into dedicated programming pins
+    Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1
+    Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2
+    Info (169125): Pin ~ALTERA_DCLK~ is reserved at location H1
+    Info (169125): Pin ~ALTERA_DATA0~ is reserved at location H2
+    Info (169125): Pin ~ALTERA_nCEO~ is reserved at location F16
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332144): No user constrained base clocks found in the design
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
+Info (176353): Automatically promoted node CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p))
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18
+Info (176233): Starting register packing
+Info (176235): Finished register packing
+    Extra Info (176219): No registers were packed into other blocks
+Warning (15705): Ignored locations or region assignments to the following nodes
+    Warning (15706): Node "ADC_CS_N" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "ADC_SADDR" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "ADC_SCLK" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "ADC_SDAT" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[10]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[11]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[12]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[7]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[8]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[9]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_BA[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_BA[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_CAS_N" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_CKE" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_CLK" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_CS_N" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQM[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQM[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[10]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[11]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[12]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[13]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[14]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[15]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[7]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[8]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[9]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_RAS_N" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_WE_N" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "EPCS_ASDO" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "EPCS_DATA0" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "EPCS_DCLK" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "EPCS_NCSO" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[10]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[11]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[12]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[13]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[14]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[15]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[16]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[17]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[18]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[19]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[20]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[21]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[22]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[23]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[24]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[25]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[26]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[27]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[28]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[29]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[30]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[31]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[32]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[33]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[7]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[8]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[9]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0_IN[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0_IN[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[10]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[11]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[12]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[13]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[14]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[15]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[16]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[17]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[18]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[19]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[20]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[21]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[22]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[23]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[24]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[25]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[26]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[27]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[28]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[29]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[30]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[31]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[32]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[33]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[7]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[8]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[9]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1_IN[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1_IN[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_2[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_2[10]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_2[11]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_2[12]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_2[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_2[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_2[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_2[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_2[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_2[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_2[7]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_2[8]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_2[9]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_2_IN[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_2_IN[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_2_IN[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "G_SENSOR_CS_N" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "G_SENSOR_INT" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "I2C_SCLK" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "I2C_SDAT" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "KEY[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "KEY[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SW[3]" is assigned to location or region, but does not exist in design
+Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
+Info (170189): Fitter placement preparation operations beginning
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 0% of the available device resources
+    Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X32_Y23 to location X42_Y34
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
+    Info (170201): Optimizations that may affect the design's routability were skipped
+Info (11888): Total time spent on timing analysis during the Fitter is 0.10 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01
+Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
+Warning (169177): 1 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
+    Info (169178): Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at R8
+Info (144001): Generated suppressed messages file /home/benny/work/fpga/projects/output_files/spectrum.fit.smsg
+Info: Quartus II 32-bit Fitter was successful. 0 errors, 152 warnings
+    Info: Peak virtual memory: 588 megabytes
+    Info: Processing ended: Wed Mar 30 11:51:36 2022
+    Info: Elapsed time: 00:00:06
+    Info: Total CPU time (on all processors): 00:00:06
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in /home/benny/work/fpga/projects/output_files/spectrum.fit.smsg.
+
+
diff --git a/output_files/spectrum.fit.smsg b/output_files/spectrum.fit.smsg
new file mode 100644
index 0000000..7121cbb
--- /dev/null
+++ b/output_files/spectrum.fit.smsg
@@ -0,0 +1,8 @@
+Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
+Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
+Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176238): Start inferring scan chains for DSP blocks
+Extra Info (176239): Inferring scan chains for DSP blocks is complete
+Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
+Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/output_files/spectrum.fit.summary b/output_files/spectrum.fit.summary
new file mode 100644
index 0000000..287f5af
--- /dev/null
+++ b/output_files/spectrum.fit.summary
@@ -0,0 +1,16 @@
+Fitter Status : Successful - Wed Mar 30 11:51:35 2022
+Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
+Revision Name : spectrum
+Top-level Entity Name : spectrum
+Family : Cyclone IV E
+Device : EP4CE22F17C6
+Timing Models : Final
+Total logic elements : 35 / 22,320 ( < 1 % )
+    Total combinational functions : 28 / 22,320 ( < 1 % )
+    Dedicated logic registers : 35 / 22,320 ( < 1 % )
+Total registers : 35
+Total pins : 9 / 154 ( 6 % )
+Total virtual pins : 0
+Total memory bits : 0 / 608,256 ( 0 % )
+Embedded Multiplier 9-bit elements : 0 / 132 ( 0 % )
+Total PLLs : 0 / 4 ( 0 % )
diff --git a/output_files/spectrum.flow.rpt b/output_files/spectrum.flow.rpt
new file mode 100644
index 0000000..e2ccaed
--- /dev/null
+++ b/output_files/spectrum.flow.rpt
@@ -0,0 +1,227 @@
+Flow report for spectrum
+Wed Mar 30 11:51:43 2022
+Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------+
+; Flow Summary                                                                    ;
++------------------------------------+--------------------------------------------+
+; Flow Status                        ; Successful - Wed Mar 30 11:51:43 2022      ;
+; Quartus II 32-bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
+; Revision Name                      ; spectrum                                   ;
+; Top-level Entity Name              ; spectrum                                   ;
+; Family                             ; Cyclone IV E                               ;
+; Device                             ; EP4CE22F17C6                               ;
+; Timing Models                      ; Final                                      ;
+; Total logic elements               ; 35 / 22,320 ( < 1 % )                      ;
+;     Total combinational functions  ; 28 / 22,320 ( < 1 % )                      ;
+;     Dedicated logic registers      ; 35 / 22,320 ( < 1 % )                      ;
+; Total registers                    ; 35                                         ;
+; Total pins                         ; 9 / 154 ( 6 % )                            ;
+; Total virtual pins                 ; 0                                          ;
+; Total memory bits                  ; 0 / 608,256 ( 0 % )                        ;
+; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % )                            ;
+; Total PLLs                         ; 0 / 4 ( 0 % )                              ;
++------------------------------------+--------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 03/30/2022 11:51:28 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; spectrum            ;
++-------------------+---------------------+
+
+
++--------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                               ;
++--------------------------------------------------------------------------------+
+Assignment Name : COMPILER_SIGNATURE_ID
+Value           : 0.164863028816849
+Default Value   : --
+Entity Name     : --
+Section Id      : --
+
+Assignment Name : EDA_OUTPUT_DATA_FORMAT
+Value           : Verilog Hdl
+Default Value   : --
+Entity Name     : --
+Section Id      : eda_simulation
+
+Assignment Name : EDA_SIMULATION_TOOL
+Value           : ModelSim-Altera (Verilog)
+Default Value   : <None>
+Entity Name     : --
+Section Id      : --
+
+Assignment Name : MAX_CORE_JUNCTION_TEMP
+Value           : 85
+Default Value   : --
+Entity Name     : --
+Section Id      : --
+
+Assignment Name : MIN_CORE_JUNCTION_TEMP
+Value           : 0
+Default Value   : --
+Entity Name     : --
+Section Id      : --
+
+Assignment Name : NOMINAL_CORE_SUPPLY_VOLTAGE
+Value           : 1.2V
+Default Value   : --
+Entity Name     : --
+Section Id      : --
+
+Assignment Name : PARTITION_COLOR
+Value           : 16764057
+Default Value   : --
+Entity Name     : --
+Section Id      : Top
+
+Assignment Name : PARTITION_FITTER_PRESERVATION_LEVEL
+Value           : PLACEMENT_AND_ROUTING
+Default Value   : --
+Entity Name     : --
+Section Id      : Top
+
+Assignment Name : PARTITION_NETLIST_TYPE
+Value           : SOURCE
+Default Value   : --
+Entity Name     : --
+Section Id      : Top
+
+Assignment Name : PROJECT_OUTPUT_DIRECTORY
+Value           : output_files
+Default Value   : --
+Entity Name     : --
+Section Id      : --
++--------------------------------------------------------------------------------+
+
+
+
++--------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                              ;
++--------------------------------------------------------------------------------+
+Module Name                        : Analysis & Synthesis
+Elapsed Time                       : 00:00:01
+Average Processors Used            : 1.0
+Peak Virtual Memory                : 377 MB
+Total CPU Time (on all processors) : 00:00:01
+
+Module Name                        : Fitter
+Elapsed Time                       : 00:00:05
+Average Processors Used            : 1.0
+Peak Virtual Memory                : 588 MB
+Total CPU Time (on all processors) : 00:00:06
+
+Module Name                        : Assembler
+Elapsed Time                       : 00:00:01
+Average Processors Used            : 1.0
+Peak Virtual Memory                : 389 MB
+Total CPU Time (on all processors) : 00:00:01
+
+Module Name                        : TimeQuest Timing Analyzer
+Elapsed Time                       : 00:00:02
+Average Processors Used            : 1.0
+Peak Virtual Memory                : 412 MB
+Total CPU Time (on all processors) : 00:00:02
+
+Module Name                        : EDA Netlist Writer
+Elapsed Time                       : 00:00:01
+Average Processors Used            : 1.0
+Peak Virtual Memory                : 340 MB
+Total CPU Time (on all processors) : 00:00:01
+
+Module Name                        : Total
+Elapsed Time                       : 00:00:10
+Average Processors Used            : --
+Peak Virtual Memory                : --
+Total CPU Time (on all processors) : 00:00:11
++--------------------------------------------------------------------------------+
+
+
+
++--------------------------------------------------------------------------------+
+; Flow OS Summary                                                                ;
++--------------------------------------------------------------------------------+
+Module Name      : Analysis & Synthesis
+Machine Hostname : alpha
+OS Name          : Ubuntu 21.10
+OS Version       : 21
+Processor type   : x86_64
+
+Module Name      : Fitter
+Machine Hostname : alpha
+OS Name          : Ubuntu 21.10
+OS Version       : 21
+Processor type   : x86_64
+
+Module Name      : Assembler
+Machine Hostname : alpha
+OS Name          : Ubuntu 21.10
+OS Version       : 21
+Processor type   : x86_64
+
+Module Name      : TimeQuest Timing Analyzer
+Machine Hostname : alpha
+OS Name          : Ubuntu 21.10
+OS Version       : 21
+Processor type   : x86_64
+
+Module Name      : EDA Netlist Writer
+Machine Hostname : alpha
+OS Name          : Ubuntu 21.10
+OS Version       : 21
+Processor type   : x86_64
++--------------------------------------------------------------------------------+
+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum
+quartus_fit --read_settings_files=off --write_settings_files=off spectrum -c spectrum
+quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum
+quartus_sta spectrum -c spectrum
+quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum
+
+
+
diff --git a/output_files/spectrum.jdi b/output_files/spectrum.jdi
new file mode 100644
index 0000000..7b0c904
--- /dev/null
+++ b/output_files/spectrum.jdi
@@ -0,0 +1,8 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="30de10ed078191d33504"/>
+  </project>
+  <file_info>
+    <file device="EP4CE22F17C6" path="spectrum.sof" usercode="0xFFFFFFFF"/>
+  </file_info>
+</sld_project_info>
diff --git a/output_files/spectrum.map.rpt b/output_files/spectrum.map.rpt
new file mode 100644
index 0000000..3ef869f
--- /dev/null
+++ b/output_files/spectrum.map.rpt
@@ -0,0 +1,518 @@
+Analysis & Synthesis report for spectrum
+Wed Mar 30 11:51:29 2022
+Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. Registers Removed During Synthesis
+  9. General Register Statistics
+ 10. Elapsed Time Per Partition
+ 11. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                    ;
++------------------------------------+--------------------------------------------+
+; Analysis & Synthesis Status        ; Successful - Wed Mar 30 11:51:29 2022      ;
+; Quartus II 32-bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
+; Revision Name                      ; spectrum                                   ;
+; Top-level Entity Name              ; spectrum                                   ;
+; Family                             ; Cyclone IV E                               ;
+; Total logic elements               ; 35                                         ;
+;     Total combinational functions  ; 28                                         ;
+;     Dedicated logic registers      ; 35                                         ;
+; Total registers                    ; 35                                         ;
+; Total pins                         ; 9                                          ;
+; Total virtual pins                 ; 0                                          ;
+; Total memory bits                  ; 0                                          ;
+; Embedded Multiplier 9-bit elements ; 0                                          ;
+; Total PLLs                         ; 0                                          ;
++------------------------------------+--------------------------------------------+
+
+
++--------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                  ;
++--------------------------------------------------------------------------------+
+Option        : Device
+Setting       : EP4CE22F17C6
+Default Value : 
+
+Option        : Top-level entity name
+Setting       : spectrum
+Default Value : spectrum
+
+Option        : Family name
+Setting       : Cyclone IV E
+Default Value : Cyclone IV GX
+
+Option        : Use smart compilation
+Setting       : Off
+Default Value : Off
+
+Option        : Enable parallel Assembler and TimeQuest Timing Analyzer during compilation
+Setting       : On
+Default Value : On
+
+Option        : Enable compact report table
+Setting       : Off
+Default Value : Off
+
+Option        : Restructure Multiplexers
+Setting       : Auto
+Default Value : Auto
+
+Option        : Create Debugging Nodes for IP Cores
+Setting       : Off
+Default Value : Off
+
+Option        : Preserve fewer node names
+Setting       : On
+Default Value : On
+
+Option        : Disable OpenCore Plus hardware evaluation
+Setting       : Off
+Default Value : Off
+
+Option        : Verilog Version
+Setting       : Verilog_2001
+Default Value : Verilog_2001
+
+Option        : VHDL Version
+Setting       : VHDL_1993
+Default Value : VHDL_1993
+
+Option        : State Machine Processing
+Setting       : Auto
+Default Value : Auto
+
+Option        : Safe State Machine
+Setting       : Off
+Default Value : Off
+
+Option        : Extract Verilog State Machines
+Setting       : On
+Default Value : On
+
+Option        : Extract VHDL State Machines
+Setting       : On
+Default Value : On
+
+Option        : Ignore Verilog initial constructs
+Setting       : Off
+Default Value : Off
+
+Option        : Iteration limit for constant Verilog loops
+Setting       : 5000
+Default Value : 5000
+
+Option        : Iteration limit for non-constant Verilog loops
+Setting       : 250
+Default Value : 250
+
+Option        : Add Pass-Through Logic to Inferred RAMs
+Setting       : On
+Default Value : On
+
+Option        : Infer RAMs from Raw Logic
+Setting       : On
+Default Value : On
+
+Option        : Parallel Synthesis
+Setting       : On
+Default Value : On
+
+Option        : DSP Block Balancing
+Setting       : Auto
+Default Value : Auto
+
+Option        : NOT Gate Push-Back
+Setting       : On
+Default Value : On
+
+Option        : Power-Up Don't Care
+Setting       : On
+Default Value : On
+
+Option        : Remove Redundant Logic Cells
+Setting       : Off
+Default Value : Off
+
+Option        : Remove Duplicate Registers
+Setting       : On
+Default Value : On
+
+Option        : Ignore CARRY Buffers
+Setting       : Off
+Default Value : Off
+
+Option        : Ignore CASCADE Buffers
+Setting       : Off
+Default Value : Off
+
+Option        : Ignore GLOBAL Buffers
+Setting       : Off
+Default Value : Off
+
+Option        : Ignore ROW GLOBAL Buffers
+Setting       : Off
+Default Value : Off
+
+Option        : Ignore LCELL Buffers
+Setting       : Off
+Default Value : Off
+
+Option        : Ignore SOFT Buffers
+Setting       : On
+Default Value : On
+
+Option        : Limit AHDL Integers to 32 Bits
+Setting       : Off
+Default Value : Off
+
+Option        : Optimization Technique
+Setting       : Balanced
+Default Value : Balanced
+
+Option        : Carry Chain Length
+Setting       : 70
+Default Value : 70
+
+Option        : Auto Carry Chains
+Setting       : On
+Default Value : On
+
+Option        : Auto Open-Drain Pins
+Setting       : On
+Default Value : On
+
+Option        : Perform WYSIWYG Primitive Resynthesis
+Setting       : Off
+Default Value : Off
+
+Option        : Auto ROM Replacement
+Setting       : On
+Default Value : On
+
+Option        : Auto RAM Replacement
+Setting       : On
+Default Value : On
+
+Option        : Auto DSP Block Replacement
+Setting       : On
+Default Value : On
+
+Option        : Auto Shift Register Replacement
+Setting       : Auto
+Default Value : Auto
+
+Option        : Allow Shift Register Merging across Hierarchies
+Setting       : Auto
+Default Value : Auto
+
+Option        : Auto Clock Enable Replacement
+Setting       : On
+Default Value : On
+
+Option        : Strict RAM Replacement
+Setting       : Off
+Default Value : Off
+
+Option        : Allow Synchronous Control Signals
+Setting       : On
+Default Value : On
+
+Option        : Force Use of Synchronous Clear Signals
+Setting       : Off
+Default Value : Off
+
+Option        : Auto RAM Block Balancing
+Setting       : On
+Default Value : On
+
+Option        : Auto RAM to Logic Cell Conversion
+Setting       : Off
+Default Value : Off
+
+Option        : Auto Resource Sharing
+Setting       : Off
+Default Value : Off
+
+Option        : Allow Any RAM Size For Recognition
+Setting       : Off
+Default Value : Off
+
+Option        : Allow Any ROM Size For Recognition
+Setting       : Off
+Default Value : Off
+
+Option        : Allow Any Shift Register Size For Recognition
+Setting       : Off
+Default Value : Off
+
+Option        : Use LogicLock Constraints during Resource Balancing
+Setting       : On
+Default Value : On
+
+Option        : Ignore translate_off and synthesis_off directives
+Setting       : Off
+Default Value : Off
+
+Option        : Timing-Driven Synthesis
+Setting       : On
+Default Value : On
+
+Option        : Report Parameter Settings
+Setting       : On
+Default Value : On
+
+Option        : Report Source Assignments
+Setting       : On
+Default Value : On
+
+Option        : Report Connectivity Checks
+Setting       : On
+Default Value : On
+
+Option        : Ignore Maximum Fan-Out Assignments
+Setting       : Off
+Default Value : Off
+
+Option        : Synchronization Register Chain Length
+Setting       : 2
+Default Value : 2
+
+Option        : PowerPlay Power Optimization
+Setting       : Normal compilation
+Default Value : Normal compilation
+
+Option        : HDL message level
+Setting       : Level2
+Default Value : Level2
+
+Option        : Suppress Register Optimization Related Messages
+Setting       : Off
+Default Value : Off
+
+Option        : Number of Removed Registers Reported in Synthesis Report
+Setting       : 5000
+Default Value : 5000
+
+Option        : Number of Swept Nodes Reported in Synthesis Report
+Setting       : 5000
+Default Value : 5000
+
+Option        : Number of Inverted Registers Reported in Synthesis Report
+Setting       : 100
+Default Value : 100
+
+Option        : Clock MUX Protection
+Setting       : On
+Default Value : On
+
+Option        : Auto Gated Clock Conversion
+Setting       : Off
+Default Value : Off
+
+Option        : Block Design Naming
+Setting       : Auto
+Default Value : Auto
+
+Option        : SDC constraint protection
+Setting       : Off
+Default Value : Off
+
+Option        : Synthesis Effort
+Setting       : Auto
+Default Value : Auto
+
+Option        : Shift Register Replacement - Allow Asynchronous Clear Signal
+Setting       : On
+Default Value : On
+
+Option        : Pre-Mapping Resynthesis Optimization
+Setting       : Off
+Default Value : Off
+
+Option        : Analysis & Synthesis Message Level
+Setting       : Medium
+Default Value : Medium
+
+Option        : Disable Register Merging Across Hierarchies
+Setting       : Auto
+Default Value : Auto
+
+Option        : Resource Aware Inference For Block RAM
+Setting       : On
+Default Value : On
+
+Option        : Synthesis Seed
+Setting       : 1
+Default Value : 1
++--------------------------------------------------------------------------------+
+
+
+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation                ;
++----------------------------+--------+
+; Processors                 ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 12     ;
+; Maximum allowed            ; 1      ;
++----------------------------+--------+
+
+
++--------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                         ;
++--------------------------------------------------------------------------------+
+File Name with User-Entered Path : spectrum.v
+Used in Netlist                  : yes
+File Type                        : User Verilog HDL File 
+File Name with Absolute Path     : /home/benny/work/fpga/projects/spectrum.v
+Library                          : 
++--------------------------------------------------------------------------------+
+
+
+
++--------------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary                  ;
++---------------------------------------------+----------------+
+; Resource                                    ; Usage          ;
++---------------------------------------------+----------------+
+; Estimated Total logic elements              ; 35             ;
+;                                             ;                ;
+; Total combinational functions               ; 28             ;
+; Logic element usage by number of LUT inputs ;                ;
+;     -- 4 input functions                    ; 0              ;
+;     -- 3 input functions                    ; 1              ;
+;     -- <=2 input functions                  ; 27             ;
+;                                             ;                ;
+; Logic elements by mode                      ;                ;
+;     -- normal mode                          ; 2              ;
+;     -- arithmetic mode                      ; 26             ;
+;                                             ;                ;
+; Total registers                             ; 35             ;
+;     -- Dedicated logic registers            ; 35             ;
+;     -- I/O registers                        ; 0              ;
+;                                             ;                ;
+; I/O pins                                    ; 9              ;
+; Embedded Multiplier 9-bit elements          ; 0              ;
+; Maximum fan-out node                        ; CLOCK_50~input ;
+; Maximum fan-out                             ; 35             ;
+; Total fan-out                               ; 141            ;
+; Average fan-out                             ; 1.74           ;
++---------------------------------------------+----------------+
+
+
++--------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                            ;
++--------------------------------------------------------------------------------+
+Compilation Hierarchy Node : |spectrum
+LC Combinationals          : 28 (28)
+LC Registers               : 35 (35)
+Memory Bits                : 0
+DSP Elements               : 0
+DSP 9x9                    : 0
+DSP 18x18                  : 0
+Pins                       : 9
+Virtual Pins               : 0
+Full Hierarchy Name        : |spectrum
+Library Name               : work
++--------------------------------------------------------------------------------+
+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++--------------------------------------------------------------------------------+
+; Registers Removed During Synthesis                                             ;
++---------------------------------------+----------------------------------------+
+; Register name                         ; Reason for Removal                     ;
++---------------------------------------+----------------------------------------+
+; LED[7]~reg0                           ; Stuck at GND due to stuck port data_in ;
+; Total Number of Removed Registers = 1 ;                                        ;
++---------------------------------------+----------------------------------------+
+
+
++------------------------------------------------------+
+; General Register Statistics                          ;
++----------------------------------------------+-------+
+; Statistic                                    ; Value ;
++----------------------------------------------+-------+
+; Total registers                              ; 35    ;
+; Number of registers using Synchronous Clear  ; 0     ;
+; Number of registers using Synchronous Load   ; 0     ;
+; Number of registers using Asynchronous Clear ; 0     ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 0     ;
+; Number of registers using Preset             ; 0     ;
++----------------------------------------------+-------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition    ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top            ; 00:00:00     ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 32-bit Analysis & Synthesis
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+    Info: Processing started: Wed Mar 30 11:51:28 2022
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum
+Warning (20028): Parallel compilation is not licensed and has been disabled
+Info (12021): Found 1 design units, including 1 entities, in source file spectrum.v
+    Info (12023): Found entity 1: spectrum
+Info (12127): Elaborating entity "spectrum" for the top level hierarchy
+Warning (10230): Verilog HDL assignment warning at spectrum.v(10): truncated value with size 32 to match size of target (28)
+Warning (13024): Output pins are stuck at VCC or GND
+    Warning (13410): Pin "LED[7]" is stuck at GND
+Info (286030): Timing-Driven Synthesis is running
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
+Info (21057): Implemented 44 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 1 input pins
+    Info (21059): Implemented 8 output pins
+    Info (21061): Implemented 35 logic cells
+Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 4 warnings
+    Info: Peak virtual memory: 388 megabytes
+    Info: Processing ended: Wed Mar 30 11:51:29 2022
+    Info: Elapsed time: 00:00:01
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/output_files/spectrum.map.summary b/output_files/spectrum.map.summary
new file mode 100644
index 0000000..57cbaf7
--- /dev/null
+++ b/output_files/spectrum.map.summary
@@ -0,0 +1,14 @@
+Analysis & Synthesis Status : Successful - Wed Mar 30 11:51:29 2022
+Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
+Revision Name : spectrum
+Top-level Entity Name : spectrum
+Family : Cyclone IV E
+Total logic elements : 35
+    Total combinational functions : 28
+    Dedicated logic registers : 35
+Total registers : 35
+Total pins : 9
+Total virtual pins : 0
+Total memory bits : 0
+Embedded Multiplier 9-bit elements : 0
+Total PLLs : 0
diff --git a/output_files/spectrum.pin b/output_files/spectrum.pin
new file mode 100644
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+ -- Copyright (C) 1991-2013 Altera Corporation
+ -- Your use of Altera Corporation's design tools, logic functions 
+ -- and other software and tools, and its AMPP partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Altera Program License 
+ -- Subscription Agreement, Altera MegaCore Function License 
+ -- Agreement, or other applicable license agreement, including, 
+ -- without limitation, that your use is for the sole purpose of 
+ -- programming logic devices manufactured by Altera and sold by 
+ -- Altera or its authorized distributors.  Please refer to the 
+ -- applicable agreement for further details.
+ -- 
+ -- This is a Quartus II output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus II input file. This file cannot be used
+ -- to make Quartus II pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus II help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.2V).
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ --					Bank 1:		3.3V
+ --					Bank 2:		3.3V
+ --					Bank 3:		3.3V
+ --					Bank 4:		2.5V
+ --					Bank 5:		2.5V
+ --					Bank 6:		2.5V
+ --					Bank 7:		3.3V
+ --					Bank 8:		2.5V
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --					It can also be used to report unused dedicated pins. The connection
+ --					on the board for unused dedicated pins depends on whether this will
+ --					be used in a future design. One example is device migration. When
+ --					using device migration, refer to the device pin-tables. If it is a
+ --					GND pin in the pin table or if it will not be used in a future design
+ --					for another purpose the it MUST be connected to GND. If it is an unused
+ --					dedicated pin, then it can be connected to a valid signal on the board
+ --					(low, high, or toggling) if that signal is required for a different
+ --					revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --					This pin should be connected to GND. It may also be connected  to a
+ --					valid signal  on the board  (low, high, or toggling)  if that signal
+ --					is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
+ --           	    or leave it unconnected.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+CHIP  "spectrum"  ASSIGNED TO AN: EP4CE22F17C6
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+VCCIO8                       : A1        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A2        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A3        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A4        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A5        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A7        :        :                   :         : 8         :                
+GND+                         : A8        :        :                   :         : 8         :                
+GND+                         : A9        :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A10       :        :                   :         : 7         :                
+LED[3]                       : A11       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : A12       :        :                   :         : 7         :                
+LED[1]                       : A13       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : A14       :        :                   :         : 7         :                
+LED[0]                       : A15       : output : 3.3-V LVTTL       :         : 7         : Y              
+VCCIO7                       : A16       : power  :                   : 3.3V    : 7         :                
+LED[6]                       : B1        : output : 3.3-V LVTTL       :         : 1         : Y              
+GND                          : B2        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B3        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B4        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B5        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B7        :        :                   :         : 8         :                
+GND+                         : B8        :        :                   :         : 8         :                
+GND+                         : B9        :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B10       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B11       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B12       :        :                   :         : 7         :                
+LED[2]                       : B13       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : B14       :        :                   :         : 7         :                
+GND                          : B15       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B16       :        :                   :         : 6         :                
+~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C1        : input  : 3.3-V LVTTL       :         : 1         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : C2        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C3        :        :                   :         : 8         :                
+VCCIO8                       : C4        : power  :                   : 2.5V    : 8         :                
+GND                          : C5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C6        :        :                   :         : 8         :                
+VCCIO8                       : C7        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C9        :        :                   :         : 7         :                
+VCCIO7                       : C10       : power  :                   : 3.3V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C11       :        :                   :         : 7         :                
+GND                          : C12       : gnd    :                   :         :           :                
+VCCIO7                       : C13       : power  :                   : 3.3V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C16       :        :                   :         : 6         :                
+LED[4]                       : D1        : output : 3.3-V LVTTL       :         : 1         : Y              
+~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D2        : input  : 3.3-V LVTTL       :         : 1         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : D3        :        :                   :         : 8         :                
+VCCD_PLL3                    : D4        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D5        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D6        :        :                   :         : 8         :                
+GND                          : D7        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D9        :        :                   :         : 7         :                
+GND                          : D10       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D11       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D12       :        :                   :         : 7         :                
+VCCD_PLL2                    : D13       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D16       :        :                   :         : 6         :                
+GND+                         : E1        :        :                   :         : 1         :                
+GND                          : E2        : gnd    :                   :         :           :                
+VCCIO1                       : E3        : power  :                   : 3.3V    : 1         :                
+GND                          : E4        : gnd    :                   :         :           :                
+GNDA3                        : E5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E9        :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E10       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E11       :        :                   :         : 7         :                
+GNDA2                        : E12       : gnd    :                   :         :           :                
+GND                          : E13       : gnd    :                   :         :           :                
+VCCIO6                       : E14       : power  :                   : 2.5V    : 6         :                
+GND+                         : E15       :        :                   :         : 6         :                
+GND+                         : E16       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F1        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F2        :        :                   :         : 1         :                
+LED[5]                       : F3        : output : 3.3-V LVTTL       :         : 1         : Y              
+nSTATUS                      : F4        :        :                   :         : 1         :                
+VCCA3                        : F5        : power  :                   : 2.5V    :           :                
+GND                          : F6        : gnd    :                   :         :           :                
+VCCINT                       : F7        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F9        :        :                   :         : 7         :                
+GND                          : F10       : gnd    :                   :         :           :                
+VCCINT                       : F11       : power  :                   : 1.2V    :           :                
+VCCA2                        : F12       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F13       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F14       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F15       :        :                   :         : 6         :                
+~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : F16       : output : 2.5 V             :         : 6         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : G1        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G2        :        :                   :         : 1         :                
+VCCIO1                       : G3        : power  :                   : 3.3V    : 1         :                
+GND                          : G4        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G5        :        :                   :         : 1         :                
+VCCINT                       : G6        : power  :                   : 1.2V    :           :                
+VCCINT                       : G7        : power  :                   : 1.2V    :           :                
+VCCINT                       : G8        : power  :                   : 1.2V    :           :                
+VCCINT                       : G9        : power  :                   : 1.2V    :           :                
+VCCINT                       : G10       : power  :                   : 1.2V    :           :                
+GND                          : G11       : gnd    :                   :         :           :                
+MSEL2                        : G12       :        :                   :         : 6         :                
+GND                          : G13       : gnd    :                   :         :           :                
+VCCIO6                       : G14       : power  :                   : 2.5V    : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 6         :                
+~ALTERA_DCLK~                : H1        : output : 3.3-V LVTTL       :         : 1         : N              
+~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : H2        : input  : 3.3-V LVTTL       :         : 1         : N              
+TCK                          : H3        : input  :                   :         : 1         :                
+TDI                          : H4        : input  :                   :         : 1         :                
+nCONFIG                      : H5        :        :                   :         : 1         :                
+VCCINT                       : H6        : power  :                   : 1.2V    :           :                
+GND                          : H7        : gnd    :                   :         :           :                
+GND                          : H8        : gnd    :                   :         :           :                
+GND                          : H9        : gnd    :                   :         :           :                
+GND                          : H10       : gnd    :                   :         :           :                
+VCCINT                       : H11       : power  :                   : 1.2V    :           :                
+MSEL1                        : H12       :        :                   :         : 6         :                
+MSEL0                        : H13       :        :                   :         : 6         :                
+CONF_DONE                    : H14       :        :                   :         : 6         :                
+GND                          : H15       : gnd    :                   :         :           :                
+GND                          : H16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J2        :        :                   :         : 2         :                
+nCE                          : J3        :        :                   :         : 1         :                
+TDO                          : J4        : output :                   :         : 1         :                
+TMS                          : J5        : input  :                   :         : 1         :                
+VCCINT                       : J6        : power  :                   : 1.2V    :           :                
+GND                          : J7        : gnd    :                   :         :           :                
+GND                          : J8        : gnd    :                   :         :           :                
+GND                          : J9        : gnd    :                   :         :           :                
+GND                          : J10       : gnd    :                   :         :           :                
+GND                          : J11       : gnd    :                   :         :           :                
+VCCINT                       : J12       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J13       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J14       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J16       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K2        :        :                   :         : 2         :                
+VCCIO2                       : K3        : power  :                   : 3.3V    : 2         :                
+GND                          : K4        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K5        :        :                   :         : 2         :                
+GND                          : K6        : gnd    :                   :         :           :                
+VCCINT                       : K7        : power  :                   : 1.2V    :           :                
+GND                          : K8        : gnd    :                   :         :           :                
+VCCINT                       : K9        : power  :                   : 1.2V    :           :                
+VCCINT                       : K10       : power  :                   : 1.2V    :           :                
+VCCINT                       : K11       : power  :                   : 1.2V    :           :                
+GND                          : K12       : gnd    :                   :         :           :                
+GND                          : K13       : gnd    :                   :         :           :                
+VCCIO5                       : K14       : power  :                   : 2.5V    : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K16       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L2        :        :                   :         : 2         :                
+LED[7]                       : L3        : output : 3.3-V LVTTL       :         : 2         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : L4        :        :                   :         : 2         :                
+VCCA1                        : L5        : power  :                   : 2.5V    :           :                
+VCCINT                       : L6        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L8        :        :                   :         : 3         :                
+GND                          : L9        : gnd    :                   :         :           :                
+GND                          : L10       : gnd    :                   :         :           :                
+GND                          : L11       : gnd    :                   :         :           :                
+VCCA4                        : L12       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L13       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L14       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L16       :        :                   :         : 5         :                
+GND+                         : M1        :        :                   :         : 2         :                
+GND+                         : M2        :        :                   :         : 2         :                
+VCCIO2                       : M3        : power  :                   : 3.3V    : 2         :                
+GND                          : M4        : gnd    :                   :         :           :                
+GNDA1                        : M5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M8        :        :                   :         : 3         :                
+VCCINT                       : M9        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M10       :        :                   :         : 4         :                
+VCCINT                       : M11       : power  :                   : 1.2V    :           :                
+GNDA4                        : M12       : gnd    :                   :         :           :                
+GND                          : M13       : gnd    :                   :         :           :                
+VCCIO5                       : M14       : power  :                   : 2.5V    : 5         :                
+GND+                         : M15       :        :                   :         : 5         :                
+GND+                         : M16       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N3        :        :                   :         : 3         :                
+VCCD_PLL1                    : N4        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N5        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N6        :        :                   :         : 3         :                
+GND                          : N7        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N9        :        :                   :         : 4         :                
+GND                          : N10       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N11       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N12       :        :                   :         : 4         :                
+VCCD_PLL4                    : N13       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N14       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P3        :        :                   :         : 3         :                
+VCCIO3                       : P4        : power  :                   : 3.3V    : 3         :                
+GND                          : P5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P6        :        :                   :         : 3         :                
+VCCIO3                       : P7        : power  :                   : 3.3V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P9        :        :                   :         : 4         :                
+VCCIO4                       : P10       : power  :                   : 2.5V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P11       :        :                   :         : 4         :                
+GND                          : P12       : gnd    :                   :         :           :                
+VCCIO4                       : P13       : power  :                   : 2.5V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P16       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R1        :        :                   :         : 2         :                
+GND                          : R2        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R3        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R4        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R5        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R7        :        :                   :         : 3         :                
+CLOCK_50                     : R8        : input  : 3.3-V LVTTL       :         : 3         : Y              
+GND+                         : R9        :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R10       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R11       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R12       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R14       :        :                   :         : 4         :                
+GND                          : R15       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R16       :        :                   :         : 5         :                
+VCCIO3                       : T1        : power  :                   : 3.3V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T2        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T3        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T4        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T5        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T7        :        :                   :         : 3         :                
+GND+                         : T8        :        :                   :         : 3         :                
+GND+                         : T9        :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T10       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T11       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T12       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T15       :        :                   :         : 4         :                
+VCCIO4                       : T16       : power  :                   : 2.5V    : 4         :                
diff --git a/output_files/spectrum.sof b/output_files/spectrum.sof
new file mode 100644
index 0000000..07d3c8b
Binary files /dev/null and b/output_files/spectrum.sof differ
diff --git a/output_files/spectrum.sta.rpt b/output_files/spectrum.sta.rpt
new file mode 100644
index 0000000..41c1382
--- /dev/null
+++ b/output_files/spectrum.sta.rpt
@@ -0,0 +1,9874 @@
+TimeQuest Timing Analyzer report for spectrum
+Wed Mar 30 11:51:41 2022
+Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. TimeQuest Timing Analyzer Summary
+  3. Parallel Compilation
+  4. Clocks
+  5. Slow 1200mV 85C Model Fmax Summary
+  6. Timing Closure Recommendations
+  7. Slow 1200mV 85C Model Setup Summary
+  8. Slow 1200mV 85C Model Hold Summary
+  9. Slow 1200mV 85C Model Recovery Summary
+ 10. Slow 1200mV 85C Model Removal Summary
+ 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
+ 12. Slow 1200mV 85C Model Setup: 'CLOCK_50'
+ 13. Slow 1200mV 85C Model Hold: 'CLOCK_50'
+ 14. Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50'
+ 15. Clock to Output Times
+ 16. Minimum Clock to Output Times
+ 17. Slow 1200mV 85C Model Metastability Report
+ 18. Slow 1200mV 0C Model Fmax Summary
+ 19. Slow 1200mV 0C Model Setup Summary
+ 20. Slow 1200mV 0C Model Hold Summary
+ 21. Slow 1200mV 0C Model Recovery Summary
+ 22. Slow 1200mV 0C Model Removal Summary
+ 23. Slow 1200mV 0C Model Minimum Pulse Width Summary
+ 24. Slow 1200mV 0C Model Setup: 'CLOCK_50'
+ 25. Slow 1200mV 0C Model Hold: 'CLOCK_50'
+ 26. Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'
+ 27. Clock to Output Times
+ 28. Minimum Clock to Output Times
+ 29. Slow 1200mV 0C Model Metastability Report
+ 30. Fast 1200mV 0C Model Setup Summary
+ 31. Fast 1200mV 0C Model Hold Summary
+ 32. Fast 1200mV 0C Model Recovery Summary
+ 33. Fast 1200mV 0C Model Removal Summary
+ 34. Fast 1200mV 0C Model Minimum Pulse Width Summary
+ 35. Fast 1200mV 0C Model Setup: 'CLOCK_50'
+ 36. Fast 1200mV 0C Model Hold: 'CLOCK_50'
+ 37. Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'
+ 38. Clock to Output Times
+ 39. Minimum Clock to Output Times
+ 40. Fast 1200mV 0C Model Metastability Report
+ 41. Multicorner Timing Analysis Summary
+ 42. Clock to Output Times
+ 43. Minimum Clock to Output Times
+ 44. Board Trace Model Assignments
+ 45. Input Transition Times
+ 46. Signal Integrity Metrics (Slow 1200mv 0c Model)
+ 47. Signal Integrity Metrics (Slow 1200mv 85c Model)
+ 48. Signal Integrity Metrics (Fast 1200mv 0c Model)
+ 49. Setup Transfers
+ 50. Hold Transfers
+ 51. Report TCCS
+ 52. Report RSKM
+ 53. Unconstrained Paths
+ 54. TimeQuest Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++-------------------------------------------------------------------------+
+; TimeQuest Timing Analyzer Summary                                       ;
++--------------------+----------------------------------------------------+
+; Quartus II Version ; Version 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
+; Revision Name      ; spectrum                                           ;
+; Device Family      ; Cyclone IV E                                       ;
+; Device Name        ; EP4CE22F17C6                                       ;
+; Timing Models      ; Final                                              ;
+; Delay Model        ; Combined                                           ;
+; Rise/Fall Delays   ; Enabled                                            ;
++--------------------+----------------------------------------------------+
+
+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation                ;
++----------------------------+--------+
+; Processors                 ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 12     ;
+; Maximum allowed            ; 1      ;
++----------------------------+--------+
+
+
++--------------------------------------------------------------------------------+
+; Clocks                                                                         ;
++--------------------------------------------------------------------------------+
+Clock Name  : CLOCK_50
+Type        : Base
+Period      : 1.000
+Frequency   : 1000.0 MHz
+Rise        : 0.000
+Fall        : 0.500
+Duty Cycle  : 
+Divide by   : 
+Multiply by : 
+Phase       : 
+Offset      : 
+Edge List   : 
+Edge Shift  : 
+Inverted    : 
+Master      : 
+Source      : 
+Targets     : { CLOCK_50 }
++--------------------------------------------------------------------------------+
+
+
+
++--------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Fmax Summary                                             ;
++--------------------------------------------------------------------------------+
+Fmax            : 383.73 MHz
+Restricted Fmax : 250.0 MHz
+Clock Name      : CLOCK_50
+Note            : limit due to minimum period restriction (max I/O toggle rate)
++--------------------------------------------------------------------------------+
+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
+----------------------------------
+; Timing Closure Recommendations ;
+----------------------------------
+HTML report is unavailable in plain text report export.
+
+
++--------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup Summary                                            ;
++--------------------------------------------------------------------------------+
+Clock         : CLOCK_50
+Slack         : -1.606
+End Point TNS : -30.234
++--------------------------------------------------------------------------------+
+
+
+
++--------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold Summary                                             ;
++--------------------------------------------------------------------------------+
+Clock         : CLOCK_50
+Slack         : 0.360
+End Point TNS : 0.000
++--------------------------------------------------------------------------------+
+
+
+
+------------------------------------------
+; Slow 1200mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1200mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width Summary                              ;
++--------------------------------------------------------------------------------+
+Clock         : CLOCK_50
+Slack         : -3.000
+End Point TNS : -38.000
++--------------------------------------------------------------------------------+
+
+
+
++--------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'CLOCK_50'                                        ;
++--------------------------------------------------------------------------------+
+Slack        : -1.606
+From Node    : counter[2]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.889
+
+Slack        : -1.525
+From Node    : counter[1]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.808
+
+Slack        : -1.523
+From Node    : counter[0]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.806
+
+Slack        : -1.490
+From Node    : counter[2]
+To Node      : counter[25]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.773
+
+Slack        : -1.488
+From Node    : counter[0]
+To Node      : counter[26]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.771
+
+Slack        : -1.488
+From Node    : counter[4]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.771
+
+Slack        : -1.485
+From Node    : counter[1]
+To Node      : counter[26]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.768
+
+Slack        : -1.484
+From Node    : counter[2]
+To Node      : counter[26]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.767
+
+Slack        : -1.411
+From Node    : counter[3]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.694
+
+Slack        : -1.409
+From Node    : counter[1]
+To Node      : counter[25]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.692
+
+Slack        : -1.407
+From Node    : counter[0]
+To Node      : counter[25]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.690
+
+Slack        : -1.376
+From Node    : counter[6]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.659
+
+Slack        : -1.374
+From Node    : counter[2]
+To Node      : counter[23]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.657
+
+Slack        : -1.372
+From Node    : counter[0]
+To Node      : counter[24]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.655
+
+Slack        : -1.372
+From Node    : counter[4]
+To Node      : counter[25]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.655
+
+Slack        : -1.370
+From Node    : counter[3]
+To Node      : counter[26]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.653
+
+Slack        : -1.369
+From Node    : counter[1]
+To Node      : counter[24]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.652
+
+Slack        : -1.368
+From Node    : counter[2]
+To Node      : counter[24]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.651
+
+Slack        : -1.366
+From Node    : counter[4]
+To Node      : counter[26]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.649
+
+Slack        : -1.295
+From Node    : counter[3]
+To Node      : counter[25]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.578
+
+Slack        : -1.293
+From Node    : counter[5]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.576
+
+Slack        : -1.293
+From Node    : counter[1]
+To Node      : counter[23]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.576
+
+Slack        : -1.291
+From Node    : counter[0]
+To Node      : counter[23]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.574
+
+Slack        : -1.261
+From Node    : counter[2]
+To Node      : counter[15]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.063
+Data Delay   : 2.193
+
+Slack        : -1.260
+From Node    : counter[8]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.543
+
+Slack        : -1.260
+From Node    : counter[6]
+To Node      : counter[25]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.543
+
+Slack        : -1.259
+From Node    : counter[0]
+To Node      : counter[16]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.063
+Data Delay   : 2.191
+
+Slack        : -1.258
+From Node    : counter[2]
+To Node      : counter[21]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.541
+
+Slack        : -1.257
+From Node    : counter[5]
+To Node      : counter[26]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.540
+
+Slack        : -1.256
+From Node    : counter[0]
+To Node      : counter[22]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.539
+
+Slack        : -1.256
+From Node    : counter[4]
+To Node      : counter[23]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.539
+
+Slack        : -1.256
+From Node    : counter[1]
+To Node      : counter[16]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.063
+Data Delay   : 2.188
+
+Slack        : -1.255
+From Node    : counter[2]
+To Node      : counter[16]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.063
+Data Delay   : 2.187
+
+Slack        : -1.254
+From Node    : counter[6]
+To Node      : counter[26]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.537
+
+Slack        : -1.254
+From Node    : counter[3]
+To Node      : counter[24]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.537
+
+Slack        : -1.253
+From Node    : counter[1]
+To Node      : counter[22]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.536
+
+Slack        : -1.252
+From Node    : counter[2]
+To Node      : counter[22]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.535
+
+Slack        : -1.250
+From Node    : counter[4]
+To Node      : counter[24]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.533
+
+Slack        : -1.194
+From Node    : counter[13]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.077
+Data Delay   : 2.112
+
+Slack        : -1.180
+From Node    : counter[1]
+To Node      : counter[15]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.063
+Data Delay   : 2.112
+
+Slack        : -1.179
+From Node    : counter[3]
+To Node      : counter[23]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.462
+
+Slack        : -1.178
+From Node    : counter[0]
+To Node      : counter[15]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.063
+Data Delay   : 2.110
+
+Slack        : -1.177
+From Node    : counter[7]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.460
+
+Slack        : -1.177
+From Node    : counter[5]
+To Node      : counter[25]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.460
+
+Slack        : -1.177
+From Node    : counter[1]
+To Node      : counter[21]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.460
+
+Slack        : -1.175
+From Node    : counter[0]
+To Node      : counter[21]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.458
+
+Slack        : -1.154
+From Node    : counter[13]
+To Node      : counter[26]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.077
+Data Delay   : 2.072
+
+Slack        : -1.144
+From Node    : counter[8]
+To Node      : counter[25]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.427
+
+Slack        : -1.144
+From Node    : counter[6]
+To Node      : counter[23]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.427
+
+Slack        : -1.143
+From Node    : counter[0]
+To Node      : counter[14]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.063
+Data Delay   : 2.075
+
+Slack        : -1.143
+From Node    : counter[4]
+To Node      : counter[15]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.063
+Data Delay   : 2.075
+
+Slack        : -1.142
+From Node    : counter[2]
+To Node      : counter[19]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.425
+
+Slack        : -1.142
+From Node    : counter[10]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.425
+
+Slack        : -1.141
+From Node    : counter[7]
+To Node      : counter[26]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.424
+
+Slack        : -1.141
+From Node    : counter[5]
+To Node      : counter[24]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.424
+
+Slack        : -1.141
+From Node    : counter[3]
+To Node      : counter[16]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.063
+Data Delay   : 2.073
+
+Slack        : -1.140
+From Node    : counter[0]
+To Node      : counter[20]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.423
+
+Slack        : -1.140
+From Node    : counter[4]
+To Node      : counter[21]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.423
+
+Slack        : -1.140
+From Node    : counter[1]
+To Node      : counter[14]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.063
+Data Delay   : 2.072
+
+Slack        : -1.139
+From Node    : counter[2]
+To Node      : counter[14]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.063
+Data Delay   : 2.071
+
+Slack        : -1.138
+From Node    : counter[8]
+To Node      : counter[26]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.421
+
+Slack        : -1.138
+From Node    : counter[6]
+To Node      : counter[24]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.421
+
+Slack        : -1.138
+From Node    : counter[3]
+To Node      : counter[22]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.421
+
+Slack        : -1.137
+From Node    : counter[4]
+To Node      : counter[16]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.063
+Data Delay   : 2.069
+
+Slack        : -1.137
+From Node    : counter[1]
+To Node      : counter[20]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.420
+
+Slack        : -1.136
+From Node    : counter[2]
+To Node      : counter[20]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.419
+
+Slack        : -1.134
+From Node    : counter[4]
+To Node      : counter[22]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.417
+
+Slack        : -1.078
+From Node    : counter[13]
+To Node      : counter[25]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.077
+Data Delay   : 1.996
+
+Slack        : -1.066
+From Node    : counter[3]
+To Node      : counter[15]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.063
+Data Delay   : 1.998
+
+Slack        : -1.063
+From Node    : counter[3]
+To Node      : counter[21]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.346
+
+Slack        : -1.062
+From Node    : counter[9]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.345
+
+Slack        : -1.061
+From Node    : counter[7]
+To Node      : counter[25]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.344
+
+Slack        : -1.061
+From Node    : counter[5]
+To Node      : counter[23]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.344
+
+Slack        : -1.061
+From Node    : counter[1]
+To Node      : counter[19]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.344
+
+Slack        : -1.059
+From Node    : counter[0]
+To Node      : counter[19]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.342
+
+Slack        : -1.044
+From Node    : counter[18]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.077
+Data Delay   : 1.962
+
+Slack        : -1.038
+From Node    : counter[13]
+To Node      : counter[24]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.077
+Data Delay   : 1.956
+
+Slack        : -1.031
+From Node    : counter[6]
+To Node      : counter[15]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.063
+Data Delay   : 1.963
+
+Slack        : -1.029
+From Node    : counter[2]
+To Node      : counter[11]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.063
+Data Delay   : 1.961
+
+Slack        : -1.028
+From Node    : counter[8]
+To Node      : counter[23]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.311
+
+Slack        : -1.028
+From Node    : counter[5]
+To Node      : counter[16]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.063
+Data Delay   : 1.960
+
+Slack        : -1.028
+From Node    : counter[6]
+To Node      : counter[21]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.311
+
+Slack        : -1.027
+From Node    : counter[0]
+To Node      : counter[12]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.063
+Data Delay   : 1.959
+
+Slack        : -1.026
+From Node    : counter[2]
+To Node      : counter[17]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.309
+
+Slack        : -1.026
+From Node    : counter[12]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.309
+
+Slack        : -1.026
+From Node    : counter[10]
+To Node      : counter[25]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.309
+
+Slack        : -1.025
+From Node    : counter[7]
+To Node      : counter[24]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.308
+
+Slack        : -1.025
+From Node    : counter[5]
+To Node      : counter[22]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.308
+
+Slack        : -1.025
+From Node    : counter[6]
+To Node      : counter[16]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.063
+Data Delay   : 1.957
+
+Slack        : -1.025
+From Node    : counter[3]
+To Node      : counter[14]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.063
+Data Delay   : 1.957
+
+Slack        : -1.024
+From Node    : counter[0]
+To Node      : counter[18]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.307
+
+Slack        : -1.024
+From Node    : counter[4]
+To Node      : counter[19]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.307
+
+Slack        : -1.024
+From Node    : counter[1]
+To Node      : counter[12]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.063
+Data Delay   : 1.956
+
+Slack        : -1.023
+From Node    : counter[2]
+To Node      : counter[12]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.063
+Data Delay   : 1.955
+
+Slack        : -1.022
+From Node    : counter[9]
+To Node      : counter[26]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.305
+
+Slack        : -1.022
+From Node    : counter[8]
+To Node      : counter[24]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.305
+
+Slack        : -1.022
+From Node    : counter[6]
+To Node      : counter[22]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.305
+
+Slack        : -1.022
+From Node    : counter[3]
+To Node      : counter[20]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.305
+
+Slack        : -1.021
+From Node    : counter[4]
+To Node      : counter[14]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.063
+Data Delay   : 1.953
+
+Slack        : -1.021
+From Node    : counter[1]
+To Node      : counter[18]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.288
+Data Delay   : 2.304
++--------------------------------------------------------------------------------+
+
+
+
++--------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'CLOCK_50'                                         ;
++--------------------------------------------------------------------------------+
+Slack        : 0.360
+From Node    : counter[0]
+To Node      : counter[0]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.063
+Data Delay   : 0.580
+
+Slack        : 0.458
+From Node    : counter[12]
+To Node      : counter[13]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.428
+Data Delay   : 1.043
+
+Slack        : 0.459
+From Node    : counter[16]
+To Node      : counter[17]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.428
+Data Delay   : 1.044
+
+Slack        : 0.473
+From Node    : counter[11]
+To Node      : counter[13]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.428
+Data Delay   : 1.058
+
+Slack        : 0.475
+From Node    : counter[15]
+To Node      : counter[17]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.428
+Data Delay   : 1.060
+
+Slack        : 0.534
+From Node    : counter[13]
+To Node      : counter[13]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.077
+Data Delay   : 0.768
+
+Slack        : 0.535
+From Node    : counter[20]
+To Node      : counter[20]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.077
+Data Delay   : 0.769
+
+Slack        : 0.535
+From Node    : counter[17]
+To Node      : counter[17]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.077
+Data Delay   : 0.769
+
+Slack        : 0.536
+From Node    : counter[19]
+To Node      : counter[19]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.077
+Data Delay   : 0.770
+
+Slack        : 0.537
+From Node    : counter[18]
+To Node      : counter[18]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.077
+Data Delay   : 0.771
+
+Slack        : 0.548
+From Node    : counter[11]
+To Node      : counter[11]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.063
+Data Delay   : 0.768
+
+Slack        : 0.548
+From Node    : counter[4]
+To Node      : counter[4]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.063
+Data Delay   : 0.768
+
+Slack        : 0.549
+From Node    : counter[12]
+To Node      : counter[12]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.063
+Data Delay   : 0.769
+
+Slack        : 0.549
+From Node    : counter[9]
+To Node      : counter[9]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.063
+Data Delay   : 0.769
+
+Slack        : 0.549
+From Node    : counter[3]
+To Node      : counter[3]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.063
+Data Delay   : 0.769
+
+Slack        : 0.550
+From Node    : counter[14]
+To Node      : counter[14]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.062
+Data Delay   : 0.769
+
+Slack        : 0.550
+From Node    : counter[10]
+To Node      : counter[10]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.063
+Data Delay   : 0.770
+
+Slack        : 0.550
+From Node    : counter[2]
+To Node      : counter[2]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.063
+Data Delay   : 0.770
+
+Slack        : 0.551
+From Node    : counter[16]
+To Node      : counter[16]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.062
+Data Delay   : 0.770
+
+Slack        : 0.551
+From Node    : counter[8]
+To Node      : counter[8]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.063
+Data Delay   : 0.771
+
+Slack        : 0.551
+From Node    : counter[6]
+To Node      : counter[6]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.063
+Data Delay   : 0.771
+
+Slack        : 0.552
+From Node    : counter[15]
+To Node      : counter[15]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.062
+Data Delay   : 0.771
+
+Slack        : 0.553
+From Node    : counter[7]
+To Node      : counter[7]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.063
+Data Delay   : 0.773
+
+Slack        : 0.553
+From Node    : counter[5]
+To Node      : counter[5]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.063
+Data Delay   : 0.773
+
+Slack        : 0.556
+From Node    : counter[27]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.077
+Data Delay   : 0.790
+
+Slack        : 0.556
+From Node    : counter[25]
+To Node      : counter[25]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.077
+Data Delay   : 0.790
+
+Slack        : 0.557
+From Node    : counter[26]
+To Node      : counter[26]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.077
+Data Delay   : 0.791
+
+Slack        : 0.558
+From Node    : counter[24]
+To Node      : counter[24]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.077
+Data Delay   : 0.792
+
+Slack        : 0.558
+From Node    : counter[22]
+To Node      : counter[22]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.077
+Data Delay   : 0.792
+
+Slack        : 0.559
+From Node    : counter[23]
+To Node      : counter[23]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.077
+Data Delay   : 0.793
+
+Slack        : 0.559
+From Node    : counter[21]
+To Node      : counter[21]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.077
+Data Delay   : 0.793
+
+Slack        : 0.560
+From Node    : counter[0]
+To Node      : counter[1]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.063
+Data Delay   : 0.780
+
+Slack        : 0.562
+From Node    : counter[1]
+To Node      : counter[1]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.063
+Data Delay   : 0.782
+
+Slack        : 0.569
+From Node    : counter[16]
+To Node      : counter[18]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.428
+Data Delay   : 1.154
+
+Slack        : 0.570
+From Node    : counter[14]
+To Node      : counter[17]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.428
+Data Delay   : 1.155
+
+Slack        : 0.571
+From Node    : counter[10]
+To Node      : counter[13]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.428
+Data Delay   : 1.156
+
+Slack        : 0.571
+From Node    : counter[16]
+To Node      : counter[19]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.428
+Data Delay   : 1.156
+
+Slack        : 0.585
+From Node    : counter[15]
+To Node      : counter[18]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.428
+Data Delay   : 1.170
+
+Slack        : 0.586
+From Node    : counter[9]
+To Node      : counter[13]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.428
+Data Delay   : 1.171
+
+Slack        : 0.587
+From Node    : counter[15]
+To Node      : counter[19]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.428
+Data Delay   : 1.172
+
+Slack        : 0.680
+From Node    : counter[14]
+To Node      : counter[18]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.428
+Data Delay   : 1.265
+
+Slack        : 0.681
+From Node    : counter[16]
+To Node      : counter[20]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.428
+Data Delay   : 1.266
+
+Slack        : 0.682
+From Node    : counter[12]
+To Node      : counter[17]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.428
+Data Delay   : 1.267
+
+Slack        : 0.682
+From Node    : counter[14]
+To Node      : counter[19]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.428
+Data Delay   : 1.267
+
+Slack        : 0.683
+From Node    : counter[16]
+To Node      : counter[21]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.428
+Data Delay   : 1.268
+
+Slack        : 0.684
+From Node    : counter[8]
+To Node      : counter[13]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.428
+Data Delay   : 1.269
+
+Slack        : 0.697
+From Node    : counter[15]
+To Node      : counter[20]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.428
+Data Delay   : 1.282
+
+Slack        : 0.697
+From Node    : counter[11]
+To Node      : counter[17]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.428
+Data Delay   : 1.282
+
+Slack        : 0.699
+From Node    : counter[15]
+To Node      : counter[21]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.428
+Data Delay   : 1.284
+
+Slack        : 0.701
+From Node    : counter[7]
+To Node      : counter[13]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.428
+Data Delay   : 1.286
+
+Slack        : 0.792
+From Node    : counter[12]
+To Node      : counter[18]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.428
+Data Delay   : 1.377
+
+Slack        : 0.792
+From Node    : counter[14]
+To Node      : counter[20]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.428
+Data Delay   : 1.377
+
+Slack        : 0.793
+From Node    : counter[16]
+To Node      : counter[22]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.428
+Data Delay   : 1.378
+
+Slack        : 0.794
+From Node    : counter[12]
+To Node      : counter[19]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.428
+Data Delay   : 1.379
+
+Slack        : 0.794
+From Node    : counter[14]
+To Node      : counter[21]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.428
+Data Delay   : 1.379
+
+Slack        : 0.795
+From Node    : counter[16]
+To Node      : counter[23]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.428
+Data Delay   : 1.380
+
+Slack        : 0.795
+From Node    : counter[10]
+To Node      : counter[17]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.428
+Data Delay   : 1.380
+
+Slack        : 0.796
+From Node    : counter[6]
+To Node      : counter[13]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.428
+Data Delay   : 1.381
+
+Slack        : 0.807
+From Node    : counter[11]
+To Node      : counter[18]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.428
+Data Delay   : 1.392
+
+Slack        : 0.809
+From Node    : counter[15]
+To Node      : counter[22]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.428
+Data Delay   : 1.394
+
+Slack        : 0.809
+From Node    : counter[11]
+To Node      : counter[19]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.428
+Data Delay   : 1.394
+
+Slack        : 0.810
+From Node    : counter[20]
+To Node      : counter[21]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.077
+Data Delay   : 1.044
+
+Slack        : 0.810
+From Node    : counter[9]
+To Node      : counter[17]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.428
+Data Delay   : 1.395
+
+Slack        : 0.811
+From Node    : counter[18]
+To Node      : counter[19]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.077
+Data Delay   : 1.045
+
+Slack        : 0.811
+From Node    : counter[15]
+To Node      : counter[23]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.428
+Data Delay   : 1.396
+
+Slack        : 0.813
+From Node    : counter[5]
+To Node      : counter[13]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.428
+Data Delay   : 1.398
+
+Slack        : 0.823
+From Node    : counter[4]
+To Node      : counter[5]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.063
+Data Delay   : 1.043
+
+Slack        : 0.823
+From Node    : counter[17]
+To Node      : counter[18]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.077
+Data Delay   : 1.057
+
+Slack        : 0.824
+From Node    : counter[10]
+To Node      : counter[11]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.063
+Data Delay   : 1.044
+
+Slack        : 0.824
+From Node    : counter[2]
+To Node      : counter[3]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.063
+Data Delay   : 1.044
+
+Slack        : 0.824
+From Node    : counter[14]
+To Node      : counter[15]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.062
+Data Delay   : 1.043
+
+Slack        : 0.824
+From Node    : counter[19]
+To Node      : counter[20]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.077
+Data Delay   : 1.058
+
+Slack        : 0.825
+From Node    : counter[8]
+To Node      : counter[9]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.063
+Data Delay   : 1.045
+
+Slack        : 0.825
+From Node    : counter[6]
+To Node      : counter[7]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.063
+Data Delay   : 1.045
+
+Slack        : 0.825
+From Node    : counter[17]
+To Node      : counter[19]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.077
+Data Delay   : 1.059
+
+Slack        : 0.826
+From Node    : counter[19]
+To Node      : counter[21]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.077
+Data Delay   : 1.060
+
+Slack        : 0.831
+From Node    : counter[26]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.077
+Data Delay   : 1.065
+
+Slack        : 0.832
+From Node    : counter[24]
+To Node      : counter[25]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.077
+Data Delay   : 1.066
+
+Slack        : 0.832
+From Node    : counter[22]
+To Node      : counter[23]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.077
+Data Delay   : 1.066
+
+Slack        : 0.836
+From Node    : counter[11]
+To Node      : counter[12]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.063
+Data Delay   : 1.056
+
+Slack        : 0.836
+From Node    : counter[1]
+To Node      : counter[2]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.063
+Data Delay   : 1.056
+
+Slack        : 0.837
+From Node    : counter[3]
+To Node      : counter[4]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.063
+Data Delay   : 1.057
+
+Slack        : 0.837
+From Node    : counter[9]
+To Node      : counter[10]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.063
+Data Delay   : 1.057
+
+Slack        : 0.838
+From Node    : counter[1]
+To Node      : counter[3]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.063
+Data Delay   : 1.058
+
+Slack        : 0.838
+From Node    : counter[0]
+To Node      : counter[2]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.063
+Data Delay   : 1.058
+
+Slack        : 0.839
+From Node    : counter[15]
+To Node      : counter[16]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.062
+Data Delay   : 1.058
+
+Slack        : 0.839
+From Node    : counter[3]
+To Node      : counter[5]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.063
+Data Delay   : 1.059
+
+Slack        : 0.839
+From Node    : counter[9]
+To Node      : counter[11]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.063
+Data Delay   : 1.059
+
+Slack        : 0.840
+From Node    : counter[7]
+To Node      : counter[8]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.063
+Data Delay   : 1.060
+
+Slack        : 0.840
+From Node    : counter[5]
+To Node      : counter[6]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.063
+Data Delay   : 1.060
+
+Slack        : 0.840
+From Node    : counter[0]
+To Node      : counter[3]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.063
+Data Delay   : 1.060
+
+Slack        : 0.842
+From Node    : counter[7]
+To Node      : counter[9]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.063
+Data Delay   : 1.062
+
+Slack        : 0.842
+From Node    : counter[5]
+To Node      : counter[7]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.063
+Data Delay   : 1.062
+
+Slack        : 0.844
+From Node    : counter[25]
+To Node      : counter[26]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.077
+Data Delay   : 1.078
+
+Slack        : 0.846
+From Node    : counter[23]
+To Node      : counter[24]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.077
+Data Delay   : 1.080
+
+Slack        : 0.846
+From Node    : counter[21]
+To Node      : counter[22]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.077
+Data Delay   : 1.080
+
+Slack        : 0.846
+From Node    : counter[25]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.077
+Data Delay   : 1.080
+
+Slack        : 0.848
+From Node    : counter[21]
+To Node      : counter[23]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.077
+Data Delay   : 1.082
+
+Slack        : 0.848
+From Node    : counter[23]
+To Node      : counter[25]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.077
+Data Delay   : 1.082
+
+Slack        : 0.897
+From Node    : counter[24]
+To Node      : LED[3]~reg0
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : -0.288
+Data Delay   : 0.766
++--------------------------------------------------------------------------------+
+
+
+
++--------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50'                          ;
++--------------------------------------------------------------------------------+
+Slack          : -3.000
+Actual Width   : 1.000
+Required Width : 4.000
+Type           : Port Rate
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : CLOCK_50
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[0]~reg0
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[1]~reg0
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[2]~reg0
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[3]~reg0
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[4]~reg0
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[5]~reg0
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[6]~reg0
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[0]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[10]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[11]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[12]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[13]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[14]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[15]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[16]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[17]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[18]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[19]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[1]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[20]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[21]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[22]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[23]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[24]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[25]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[26]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[27]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[2]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[3]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[4]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[5]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[6]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[7]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[8]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[9]
+
+Slack          : 0.088
+Actual Width   : 0.272
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[13]
+
+Slack          : 0.088
+Actual Width   : 0.272
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[17]
+
+Slack          : 0.088
+Actual Width   : 0.272
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[18]
+
+Slack          : 0.088
+Actual Width   : 0.272
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[19]
+
+Slack          : 0.088
+Actual Width   : 0.272
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[20]
+
+Slack          : 0.088
+Actual Width   : 0.272
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[21]
+
+Slack          : 0.088
+Actual Width   : 0.272
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[22]
+
+Slack          : 0.088
+Actual Width   : 0.272
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[23]
+
+Slack          : 0.088
+Actual Width   : 0.272
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[24]
+
+Slack          : 0.088
+Actual Width   : 0.272
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[25]
+
+Slack          : 0.088
+Actual Width   : 0.272
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[26]
+
+Slack          : 0.088
+Actual Width   : 0.272
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[27]
+
+Slack          : 0.097
+Actual Width   : 0.281
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[14]
+
+Slack          : 0.097
+Actual Width   : 0.281
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[15]
+
+Slack          : 0.097
+Actual Width   : 0.281
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[16]
+
+Slack          : 0.098
+Actual Width   : 0.282
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[0]~reg0
+
+Slack          : 0.098
+Actual Width   : 0.282
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[1]~reg0
+
+Slack          : 0.098
+Actual Width   : 0.282
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[2]~reg0
+
+Slack          : 0.098
+Actual Width   : 0.282
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[3]~reg0
+
+Slack          : 0.098
+Actual Width   : 0.282
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[4]~reg0
+
+Slack          : 0.098
+Actual Width   : 0.282
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[5]~reg0
+
+Slack          : 0.098
+Actual Width   : 0.282
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[6]~reg0
+
+Slack          : 0.098
+Actual Width   : 0.282
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[0]
+
+Slack          : 0.098
+Actual Width   : 0.282
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[10]
+
+Slack          : 0.098
+Actual Width   : 0.282
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[11]
+
+Slack          : 0.098
+Actual Width   : 0.282
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[12]
+
+Slack          : 0.098
+Actual Width   : 0.282
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[1]
+
+Slack          : 0.098
+Actual Width   : 0.282
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[2]
+
+Slack          : 0.098
+Actual Width   : 0.282
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[3]
+
+Slack          : 0.098
+Actual Width   : 0.282
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[4]
+
+Slack          : 0.098
+Actual Width   : 0.282
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[5]
+
+Slack          : 0.098
+Actual Width   : 0.282
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[6]
+
+Slack          : 0.098
+Actual Width   : 0.282
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[7]
+
+Slack          : 0.098
+Actual Width   : 0.282
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[8]
+
+Slack          : 0.098
+Actual Width   : 0.282
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[9]
+
+Slack          : 0.247
+Actual Width   : 0.247
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : CLOCK_50~input|o
+
+Slack          : 0.250
+Actual Width   : 0.250
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[13]|clk
+
+Slack          : 0.250
+Actual Width   : 0.250
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[17]|clk
+
+Slack          : 0.250
+Actual Width   : 0.250
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[18]|clk
+
+Slack          : 0.250
+Actual Width   : 0.250
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[19]|clk
+
+Slack          : 0.250
+Actual Width   : 0.250
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[20]|clk
+
+Slack          : 0.250
+Actual Width   : 0.250
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[21]|clk
+
+Slack          : 0.250
+Actual Width   : 0.250
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[22]|clk
+
+Slack          : 0.250
+Actual Width   : 0.250
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[23]|clk
+
+Slack          : 0.250
+Actual Width   : 0.250
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[24]|clk
+
+Slack          : 0.250
+Actual Width   : 0.250
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[25]|clk
+
+Slack          : 0.250
+Actual Width   : 0.250
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[26]|clk
+
+Slack          : 0.250
+Actual Width   : 0.250
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[27]|clk
+
+Slack          : 0.259
+Actual Width   : 0.259
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[0]~reg0|clk
+
+Slack          : 0.259
+Actual Width   : 0.259
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[1]~reg0|clk
+
+Slack          : 0.259
+Actual Width   : 0.259
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[2]~reg0|clk
+
+Slack          : 0.259
+Actual Width   : 0.259
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[4]~reg0|clk
+
+Slack          : 0.259
+Actual Width   : 0.259
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[5]~reg0|clk
+
+Slack          : 0.259
+Actual Width   : 0.259
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[6]~reg0|clk
+
+Slack          : 0.259
+Actual Width   : 0.259
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[0]|clk
+
+Slack          : 0.259
+Actual Width   : 0.259
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[10]|clk
+
+Slack          : 0.259
+Actual Width   : 0.259
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[11]|clk
+
+Slack          : 0.259
+Actual Width   : 0.259
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[12]|clk
+
+Slack          : 0.259
+Actual Width   : 0.259
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[14]|clk
+
+Slack          : 0.259
+Actual Width   : 0.259
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[15]|clk
+
+Slack          : 0.259
+Actual Width   : 0.259
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[16]|clk
+
+Slack          : 0.259
+Actual Width   : 0.259
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[1]|clk
+
+Slack          : 0.259
+Actual Width   : 0.259
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[2]|clk
+
+Slack          : 0.259
+Actual Width   : 0.259
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[3]|clk
++--------------------------------------------------------------------------------+
+
+
+
++--------------------------------------------------------------------------------+
+; Clock to Output Times                                                          ;
++--------------------------------------------------------------------------------+
+Data Port       : LED[*]
+Clock Port      : CLOCK_50
+Rise            : 9.276
+Fall            : 9.028
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[0]
+Clock Port      : CLOCK_50
+Rise            : 5.406
+Fall            : 5.347
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[1]
+Clock Port      : CLOCK_50
+Rise            : 5.653
+Fall            : 5.580
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[2]
+Clock Port      : CLOCK_50
+Rise            : 5.633
+Fall            : 5.560
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[3]
+Clock Port      : CLOCK_50
+Rise            : 5.406
+Fall            : 5.347
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[4]
+Clock Port      : CLOCK_50
+Rise            : 7.391
+Fall            : 7.410
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[5]
+Clock Port      : CLOCK_50
+Rise            : 9.276
+Fall            : 9.028
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[6]
+Clock Port      : CLOCK_50
+Rise            : 6.114
+Fall            : 6.176
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
++--------------------------------------------------------------------------------+
+
+
+
++--------------------------------------------------------------------------------+
+; Minimum Clock to Output Times                                                  ;
++--------------------------------------------------------------------------------+
+Data Port       : LED[*]
+Clock Port      : CLOCK_50
+Rise            : 5.227
+Fall            : 5.167
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[0]
+Clock Port      : CLOCK_50
+Rise            : 5.227
+Fall            : 5.167
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[1]
+Clock Port      : CLOCK_50
+Rise            : 5.465
+Fall            : 5.391
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[2]
+Clock Port      : CLOCK_50
+Rise            : 5.446
+Fall            : 5.372
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[3]
+Clock Port      : CLOCK_50
+Rise            : 5.228
+Fall            : 5.168
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[4]
+Clock Port      : CLOCK_50
+Rise            : 7.136
+Fall            : 7.151
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[5]
+Clock Port      : CLOCK_50
+Rise            : 9.022
+Fall            : 8.769
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[6]
+Clock Port      : CLOCK_50
+Rise            : 5.905
+Fall            : 5.962
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
++--------------------------------------------------------------------------------+
+
+
+
+----------------------------------------------
+; Slow 1200mV 85C Model Metastability Report ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
++--------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Fmax Summary                                              ;
++--------------------------------------------------------------------------------+
+Fmax            : 439.56 MHz
+Restricted Fmax : 250.0 MHz
+Clock Name      : CLOCK_50
+Note            : limit due to minimum period restriction (max I/O toggle rate)
++--------------------------------------------------------------------------------+
+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
++--------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup Summary                                             ;
++--------------------------------------------------------------------------------+
+Clock         : CLOCK_50
+Slack         : -1.275
+End Point TNS : -22.690
++--------------------------------------------------------------------------------+
+
+
+
++--------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold Summary                                              ;
++--------------------------------------------------------------------------------+
+Clock         : CLOCK_50
+Slack         : 0.319
+End Point TNS : 0.000
++--------------------------------------------------------------------------------+
+
+
+
+-----------------------------------------
+; Slow 1200mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Slow 1200mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width Summary                               ;
++--------------------------------------------------------------------------------+
+Clock         : CLOCK_50
+Slack         : -3.000
+End Point TNS : -38.000
++--------------------------------------------------------------------------------+
+
+
+
++--------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'CLOCK_50'                                         ;
++--------------------------------------------------------------------------------+
+Slack        : -1.275
+From Node    : counter[2]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.529
+
+Slack        : -1.208
+From Node    : counter[1]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.462
+
+Slack        : -1.204
+From Node    : counter[0]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.458
+
+Slack        : -1.175
+From Node    : counter[0]
+To Node      : counter[26]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.429
+
+Slack        : -1.175
+From Node    : counter[2]
+To Node      : counter[25]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.429
+
+Slack        : -1.173
+From Node    : counter[4]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.427
+
+Slack        : -1.171
+From Node    : counter[1]
+To Node      : counter[26]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.425
+
+Slack        : -1.157
+From Node    : counter[2]
+To Node      : counter[26]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.411
+
+Slack        : -1.111
+From Node    : counter[3]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.365
+
+Slack        : -1.108
+From Node    : counter[1]
+To Node      : counter[25]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.362
+
+Slack        : -1.104
+From Node    : counter[0]
+To Node      : counter[25]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.358
+
+Slack        : -1.076
+From Node    : counter[6]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.330
+
+Slack        : -1.075
+From Node    : counter[0]
+To Node      : counter[24]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.329
+
+Slack        : -1.075
+From Node    : counter[2]
+To Node      : counter[23]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.329
+
+Slack        : -1.073
+From Node    : counter[4]
+To Node      : counter[25]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.327
+
+Slack        : -1.072
+From Node    : counter[3]
+To Node      : counter[26]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.326
+
+Slack        : -1.071
+From Node    : counter[1]
+To Node      : counter[24]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.325
+
+Slack        : -1.057
+From Node    : counter[2]
+To Node      : counter[24]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.311
+
+Slack        : -1.055
+From Node    : counter[4]
+To Node      : counter[26]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.309
+
+Slack        : -1.011
+From Node    : counter[3]
+To Node      : counter[25]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.265
+
+Slack        : -1.008
+From Node    : counter[1]
+To Node      : counter[23]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.262
+
+Slack        : -1.006
+From Node    : counter[5]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.260
+
+Slack        : -1.004
+From Node    : counter[0]
+To Node      : counter[23]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.258
+
+Slack        : -0.990
+From Node    : counter[0]
+To Node      : counter[16]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.056
+Data Delay   : 1.929
+
+Slack        : -0.990
+From Node    : counter[2]
+To Node      : counter[15]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.056
+Data Delay   : 1.929
+
+Slack        : -0.986
+From Node    : counter[1]
+To Node      : counter[16]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.056
+Data Delay   : 1.925
+
+Slack        : -0.977
+From Node    : counter[8]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.231
+
+Slack        : -0.976
+From Node    : counter[5]
+To Node      : counter[26]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.230
+
+Slack        : -0.976
+From Node    : counter[6]
+To Node      : counter[25]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.230
+
+Slack        : -0.975
+From Node    : counter[0]
+To Node      : counter[22]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.229
+
+Slack        : -0.975
+From Node    : counter[2]
+To Node      : counter[21]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.229
+
+Slack        : -0.973
+From Node    : counter[4]
+To Node      : counter[23]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.227
+
+Slack        : -0.972
+From Node    : counter[3]
+To Node      : counter[24]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.226
+
+Slack        : -0.972
+From Node    : counter[2]
+To Node      : counter[16]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.056
+Data Delay   : 1.911
+
+Slack        : -0.971
+From Node    : counter[1]
+To Node      : counter[22]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.225
+
+Slack        : -0.958
+From Node    : counter[6]
+To Node      : counter[26]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.212
+
+Slack        : -0.957
+From Node    : counter[2]
+To Node      : counter[22]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.211
+
+Slack        : -0.955
+From Node    : counter[4]
+To Node      : counter[24]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.209
+
+Slack        : -0.936
+From Node    : counter[13]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.068
+Data Delay   : 1.863
+
+Slack        : -0.923
+From Node    : counter[1]
+To Node      : counter[15]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.056
+Data Delay   : 1.862
+
+Slack        : -0.919
+From Node    : counter[0]
+To Node      : counter[15]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.056
+Data Delay   : 1.858
+
+Slack        : -0.911
+From Node    : counter[3]
+To Node      : counter[23]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.165
+
+Slack        : -0.908
+From Node    : counter[1]
+To Node      : counter[21]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.162
+
+Slack        : -0.906
+From Node    : counter[7]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.160
+
+Slack        : -0.906
+From Node    : counter[5]
+To Node      : counter[25]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.160
+
+Slack        : -0.904
+From Node    : counter[0]
+To Node      : counter[21]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.158
+
+Slack        : -0.898
+From Node    : counter[13]
+To Node      : counter[26]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.068
+Data Delay   : 1.825
+
+Slack        : -0.890
+From Node    : counter[0]
+To Node      : counter[14]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.056
+Data Delay   : 1.829
+
+Slack        : -0.888
+From Node    : counter[4]
+To Node      : counter[15]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.056
+Data Delay   : 1.827
+
+Slack        : -0.887
+From Node    : counter[3]
+To Node      : counter[16]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.056
+Data Delay   : 1.826
+
+Slack        : -0.886
+From Node    : counter[1]
+To Node      : counter[14]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.056
+Data Delay   : 1.825
+
+Slack        : -0.877
+From Node    : counter[8]
+To Node      : counter[25]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.131
+
+Slack        : -0.876
+From Node    : counter[7]
+To Node      : counter[26]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.130
+
+Slack        : -0.876
+From Node    : counter[5]
+To Node      : counter[24]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.130
+
+Slack        : -0.876
+From Node    : counter[6]
+To Node      : counter[23]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.130
+
+Slack        : -0.875
+From Node    : counter[0]
+To Node      : counter[20]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.129
+
+Slack        : -0.875
+From Node    : counter[2]
+To Node      : counter[19]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.129
+
+Slack        : -0.875
+From Node    : counter[10]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.129
+
+Slack        : -0.873
+From Node    : counter[4]
+To Node      : counter[21]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.127
+
+Slack        : -0.872
+From Node    : counter[3]
+To Node      : counter[22]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.126
+
+Slack        : -0.872
+From Node    : counter[2]
+To Node      : counter[14]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.056
+Data Delay   : 1.811
+
+Slack        : -0.871
+From Node    : counter[1]
+To Node      : counter[20]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.125
+
+Slack        : -0.870
+From Node    : counter[4]
+To Node      : counter[16]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.056
+Data Delay   : 1.809
+
+Slack        : -0.859
+From Node    : counter[8]
+To Node      : counter[26]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.113
+
+Slack        : -0.858
+From Node    : counter[6]
+To Node      : counter[24]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.112
+
+Slack        : -0.857
+From Node    : counter[2]
+To Node      : counter[20]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.111
+
+Slack        : -0.855
+From Node    : counter[4]
+To Node      : counter[22]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.109
+
+Slack        : -0.836
+From Node    : counter[13]
+To Node      : counter[25]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.068
+Data Delay   : 1.763
+
+Slack        : -0.826
+From Node    : counter[3]
+To Node      : counter[15]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.056
+Data Delay   : 1.765
+
+Slack        : -0.811
+From Node    : counter[3]
+To Node      : counter[21]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.065
+
+Slack        : -0.809
+From Node    : counter[9]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.063
+
+Slack        : -0.808
+From Node    : counter[1]
+To Node      : counter[19]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.062
+
+Slack        : -0.806
+From Node    : counter[7]
+To Node      : counter[25]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.060
+
+Slack        : -0.806
+From Node    : counter[5]
+To Node      : counter[23]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.060
+
+Slack        : -0.804
+From Node    : counter[0]
+To Node      : counter[19]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.058
+
+Slack        : -0.803
+From Node    : counter[18]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.068
+Data Delay   : 1.730
+
+Slack        : -0.798
+From Node    : counter[13]
+To Node      : counter[24]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.068
+Data Delay   : 1.725
+
+Slack        : -0.791
+From Node    : counter[5]
+To Node      : counter[16]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.056
+Data Delay   : 1.730
+
+Slack        : -0.791
+From Node    : counter[6]
+To Node      : counter[15]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.056
+Data Delay   : 1.730
+
+Slack        : -0.790
+From Node    : counter[0]
+To Node      : counter[12]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.056
+Data Delay   : 1.729
+
+Slack        : -0.790
+From Node    : counter[2]
+To Node      : counter[11]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.056
+Data Delay   : 1.729
+
+Slack        : -0.787
+From Node    : counter[3]
+To Node      : counter[14]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.056
+Data Delay   : 1.726
+
+Slack        : -0.786
+From Node    : counter[1]
+To Node      : counter[12]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.056
+Data Delay   : 1.725
+
+Slack        : -0.777
+From Node    : counter[8]
+To Node      : counter[23]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.031
+
+Slack        : -0.776
+From Node    : counter[7]
+To Node      : counter[24]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.030
+
+Slack        : -0.776
+From Node    : counter[5]
+To Node      : counter[22]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.030
+
+Slack        : -0.776
+From Node    : counter[6]
+To Node      : counter[21]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.030
+
+Slack        : -0.775
+From Node    : counter[0]
+To Node      : counter[18]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.029
+
+Slack        : -0.775
+From Node    : counter[2]
+To Node      : counter[17]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.029
+
+Slack        : -0.775
+From Node    : counter[10]
+To Node      : counter[25]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.029
+
+Slack        : -0.774
+From Node    : counter[12]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.028
+
+Slack        : -0.773
+From Node    : counter[6]
+To Node      : counter[16]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.056
+Data Delay   : 1.712
+
+Slack        : -0.773
+From Node    : counter[4]
+To Node      : counter[19]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.027
+
+Slack        : -0.772
+From Node    : counter[9]
+To Node      : counter[26]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.026
+
+Slack        : -0.772
+From Node    : counter[3]
+To Node      : counter[20]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.026
+
+Slack        : -0.772
+From Node    : counter[2]
+To Node      : counter[12]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.056
+Data Delay   : 1.711
+
+Slack        : -0.771
+From Node    : counter[1]
+To Node      : counter[18]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.025
+
+Slack        : -0.770
+From Node    : counter[4]
+To Node      : counter[14]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.056
+Data Delay   : 1.709
+
+Slack        : -0.759
+From Node    : counter[8]
+To Node      : counter[24]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.013
+
+Slack        : -0.758
+From Node    : counter[6]
+To Node      : counter[22]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.259
+Data Delay   : 2.012
++--------------------------------------------------------------------------------+
+
+
+
++--------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'CLOCK_50'                                          ;
++--------------------------------------------------------------------------------+
+Slack        : 0.319
+From Node    : counter[0]
+To Node      : counter[0]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.056
+Data Delay   : 0.519
+
+Slack        : 0.412
+From Node    : counter[16]
+To Node      : counter[17]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.383
+Data Delay   : 0.939
+
+Slack        : 0.412
+From Node    : counter[12]
+To Node      : counter[13]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.383
+Data Delay   : 0.939
+
+Slack        : 0.421
+From Node    : counter[11]
+To Node      : counter[13]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.383
+Data Delay   : 0.948
+
+Slack        : 0.425
+From Node    : counter[15]
+To Node      : counter[17]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.383
+Data Delay   : 0.952
+
+Slack        : 0.480
+From Node    : counter[13]
+To Node      : counter[13]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.068
+Data Delay   : 0.692
+
+Slack        : 0.481
+From Node    : counter[20]
+To Node      : counter[20]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.068
+Data Delay   : 0.693
+
+Slack        : 0.481
+From Node    : counter[17]
+To Node      : counter[17]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.068
+Data Delay   : 0.693
+
+Slack        : 0.482
+From Node    : counter[19]
+To Node      : counter[19]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.068
+Data Delay   : 0.694
+
+Slack        : 0.484
+From Node    : counter[18]
+To Node      : counter[18]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.068
+Data Delay   : 0.696
+
+Slack        : 0.492
+From Node    : counter[11]
+To Node      : counter[11]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.056
+Data Delay   : 0.692
+
+Slack        : 0.492
+From Node    : counter[4]
+To Node      : counter[4]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.056
+Data Delay   : 0.692
+
+Slack        : 0.493
+From Node    : counter[9]
+To Node      : counter[9]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.056
+Data Delay   : 0.693
+
+Slack        : 0.494
+From Node    : counter[14]
+To Node      : counter[14]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.055
+Data Delay   : 0.693
+
+Slack        : 0.494
+From Node    : counter[12]
+To Node      : counter[12]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.056
+Data Delay   : 0.694
+
+Slack        : 0.494
+From Node    : counter[3]
+To Node      : counter[3]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.056
+Data Delay   : 0.694
+
+Slack        : 0.495
+From Node    : counter[16]
+To Node      : counter[16]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.055
+Data Delay   : 0.694
+
+Slack        : 0.495
+From Node    : counter[10]
+To Node      : counter[10]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.056
+Data Delay   : 0.695
+
+Slack        : 0.495
+From Node    : counter[8]
+To Node      : counter[8]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.056
+Data Delay   : 0.695
+
+Slack        : 0.495
+From Node    : counter[2]
+To Node      : counter[2]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.056
+Data Delay   : 0.695
+
+Slack        : 0.496
+From Node    : counter[6]
+To Node      : counter[6]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.056
+Data Delay   : 0.696
+
+Slack        : 0.497
+From Node    : counter[15]
+To Node      : counter[15]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.055
+Data Delay   : 0.696
+
+Slack        : 0.497
+From Node    : counter[7]
+To Node      : counter[7]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.056
+Data Delay   : 0.697
+
+Slack        : 0.498
+From Node    : counter[5]
+To Node      : counter[5]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.056
+Data Delay   : 0.698
+
+Slack        : 0.500
+From Node    : counter[27]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.068
+Data Delay   : 0.712
+
+Slack        : 0.500
+From Node    : counter[25]
+To Node      : counter[25]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.068
+Data Delay   : 0.712
+
+Slack        : 0.501
+From Node    : counter[26]
+To Node      : counter[26]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.068
+Data Delay   : 0.713
+
+Slack        : 0.501
+From Node    : counter[16]
+To Node      : counter[18]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.383
+Data Delay   : 1.028
+
+Slack        : 0.502
+From Node    : counter[24]
+To Node      : counter[24]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.068
+Data Delay   : 0.714
+
+Slack        : 0.502
+From Node    : counter[22]
+To Node      : counter[22]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.068
+Data Delay   : 0.714
+
+Slack        : 0.504
+From Node    : counter[23]
+To Node      : counter[23]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.068
+Data Delay   : 0.716
+
+Slack        : 0.504
+From Node    : counter[21]
+To Node      : counter[21]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.068
+Data Delay   : 0.716
+
+Slack        : 0.506
+From Node    : counter[0]
+To Node      : counter[1]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.056
+Data Delay   : 0.706
+
+Slack        : 0.507
+From Node    : counter[14]
+To Node      : counter[17]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.383
+Data Delay   : 1.034
+
+Slack        : 0.507
+From Node    : counter[1]
+To Node      : counter[1]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.056
+Data Delay   : 0.707
+
+Slack        : 0.508
+From Node    : counter[16]
+To Node      : counter[19]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.383
+Data Delay   : 1.035
+
+Slack        : 0.509
+From Node    : counter[10]
+To Node      : counter[13]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.383
+Data Delay   : 1.036
+
+Slack        : 0.514
+From Node    : counter[15]
+To Node      : counter[18]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.383
+Data Delay   : 1.041
+
+Slack        : 0.518
+From Node    : counter[9]
+To Node      : counter[13]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.383
+Data Delay   : 1.045
+
+Slack        : 0.521
+From Node    : counter[15]
+To Node      : counter[19]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.383
+Data Delay   : 1.048
+
+Slack        : 0.596
+From Node    : counter[14]
+To Node      : counter[18]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.383
+Data Delay   : 1.123
+
+Slack        : 0.597
+From Node    : counter[16]
+To Node      : counter[20]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.383
+Data Delay   : 1.124
+
+Slack        : 0.603
+From Node    : counter[14]
+To Node      : counter[19]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.383
+Data Delay   : 1.130
+
+Slack        : 0.604
+From Node    : counter[16]
+To Node      : counter[21]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.383
+Data Delay   : 1.131
+
+Slack        : 0.604
+From Node    : counter[12]
+To Node      : counter[17]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.383
+Data Delay   : 1.131
+
+Slack        : 0.605
+From Node    : counter[8]
+To Node      : counter[13]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.383
+Data Delay   : 1.132
+
+Slack        : 0.610
+From Node    : counter[15]
+To Node      : counter[20]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.383
+Data Delay   : 1.137
+
+Slack        : 0.613
+From Node    : counter[11]
+To Node      : counter[17]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.383
+Data Delay   : 1.140
+
+Slack        : 0.617
+From Node    : counter[15]
+To Node      : counter[21]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.383
+Data Delay   : 1.144
+
+Slack        : 0.618
+From Node    : counter[7]
+To Node      : counter[13]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.383
+Data Delay   : 1.145
+
+Slack        : 0.692
+From Node    : counter[14]
+To Node      : counter[20]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.383
+Data Delay   : 1.219
+
+Slack        : 0.693
+From Node    : counter[16]
+To Node      : counter[22]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.383
+Data Delay   : 1.220
+
+Slack        : 0.693
+From Node    : counter[12]
+To Node      : counter[18]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.383
+Data Delay   : 1.220
+
+Slack        : 0.699
+From Node    : counter[14]
+To Node      : counter[21]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.383
+Data Delay   : 1.226
+
+Slack        : 0.700
+From Node    : counter[16]
+To Node      : counter[23]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.383
+Data Delay   : 1.227
+
+Slack        : 0.700
+From Node    : counter[12]
+To Node      : counter[19]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.383
+Data Delay   : 1.227
+
+Slack        : 0.701
+From Node    : counter[10]
+To Node      : counter[17]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.383
+Data Delay   : 1.228
+
+Slack        : 0.702
+From Node    : counter[6]
+To Node      : counter[13]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.383
+Data Delay   : 1.229
+
+Slack        : 0.702
+From Node    : counter[11]
+To Node      : counter[18]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.383
+Data Delay   : 1.229
+
+Slack        : 0.706
+From Node    : counter[15]
+To Node      : counter[22]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.383
+Data Delay   : 1.233
+
+Slack        : 0.709
+From Node    : counter[11]
+To Node      : counter[19]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.383
+Data Delay   : 1.236
+
+Slack        : 0.710
+From Node    : counter[9]
+To Node      : counter[17]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.383
+Data Delay   : 1.237
+
+Slack        : 0.713
+From Node    : counter[15]
+To Node      : counter[23]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.383
+Data Delay   : 1.240
+
+Slack        : 0.715
+From Node    : counter[5]
+To Node      : counter[13]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.383
+Data Delay   : 1.242
+
+Slack        : 0.725
+From Node    : counter[20]
+To Node      : counter[21]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.068
+Data Delay   : 0.937
+
+Slack        : 0.729
+From Node    : counter[18]
+To Node      : counter[19]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.068
+Data Delay   : 0.941
+
+Slack        : 0.730
+From Node    : counter[17]
+To Node      : counter[18]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.068
+Data Delay   : 0.942
+
+Slack        : 0.731
+From Node    : counter[19]
+To Node      : counter[20]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.068
+Data Delay   : 0.943
+
+Slack        : 0.736
+From Node    : counter[4]
+To Node      : counter[5]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.056
+Data Delay   : 0.936
+
+Slack        : 0.737
+From Node    : counter[17]
+To Node      : counter[19]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.068
+Data Delay   : 0.949
+
+Slack        : 0.738
+From Node    : counter[19]
+To Node      : counter[21]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.068
+Data Delay   : 0.950
+
+Slack        : 0.739
+From Node    : counter[14]
+To Node      : counter[15]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.055
+Data Delay   : 0.938
+
+Slack        : 0.740
+From Node    : counter[10]
+To Node      : counter[11]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.056
+Data Delay   : 0.940
+
+Slack        : 0.740
+From Node    : counter[8]
+To Node      : counter[9]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.056
+Data Delay   : 0.940
+
+Slack        : 0.740
+From Node    : counter[2]
+To Node      : counter[3]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.056
+Data Delay   : 0.940
+
+Slack        : 0.741
+From Node    : counter[6]
+To Node      : counter[7]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.056
+Data Delay   : 0.941
+
+Slack        : 0.741
+From Node    : counter[11]
+To Node      : counter[12]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.056
+Data Delay   : 0.941
+
+Slack        : 0.742
+From Node    : counter[9]
+To Node      : counter[10]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.056
+Data Delay   : 0.942
+
+Slack        : 0.742
+From Node    : counter[1]
+To Node      : counter[2]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.056
+Data Delay   : 0.942
+
+Slack        : 0.743
+From Node    : counter[3]
+To Node      : counter[4]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.056
+Data Delay   : 0.943
+
+Slack        : 0.745
+From Node    : counter[0]
+To Node      : counter[2]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.056
+Data Delay   : 0.945
+
+Slack        : 0.746
+From Node    : counter[26]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.068
+Data Delay   : 0.958
+
+Slack        : 0.746
+From Node    : counter[15]
+To Node      : counter[16]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.055
+Data Delay   : 0.945
+
+Slack        : 0.746
+From Node    : counter[7]
+To Node      : counter[8]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.056
+Data Delay   : 0.946
+
+Slack        : 0.747
+From Node    : counter[24]
+To Node      : counter[25]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.068
+Data Delay   : 0.959
+
+Slack        : 0.747
+From Node    : counter[5]
+To Node      : counter[6]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.056
+Data Delay   : 0.947
+
+Slack        : 0.747
+From Node    : counter[22]
+To Node      : counter[23]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.068
+Data Delay   : 0.959
+
+Slack        : 0.749
+From Node    : counter[25]
+To Node      : counter[26]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.068
+Data Delay   : 0.961
+
+Slack        : 0.749
+From Node    : counter[9]
+To Node      : counter[11]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.056
+Data Delay   : 0.949
+
+Slack        : 0.749
+From Node    : counter[1]
+To Node      : counter[3]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.056
+Data Delay   : 0.949
+
+Slack        : 0.750
+From Node    : counter[3]
+To Node      : counter[5]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.056
+Data Delay   : 0.950
+
+Slack        : 0.752
+From Node    : counter[0]
+To Node      : counter[3]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.056
+Data Delay   : 0.952
+
+Slack        : 0.753
+From Node    : counter[23]
+To Node      : counter[24]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.068
+Data Delay   : 0.965
+
+Slack        : 0.753
+From Node    : counter[21]
+To Node      : counter[22]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.068
+Data Delay   : 0.965
+
+Slack        : 0.753
+From Node    : counter[7]
+To Node      : counter[9]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.056
+Data Delay   : 0.953
+
+Slack        : 0.754
+From Node    : counter[5]
+To Node      : counter[7]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.056
+Data Delay   : 0.954
+
+Slack        : 0.756
+From Node    : counter[25]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.068
+Data Delay   : 0.968
+
+Slack        : 0.760
+From Node    : counter[21]
+To Node      : counter[23]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.068
+Data Delay   : 0.972
+
+Slack        : 0.760
+From Node    : counter[23]
+To Node      : counter[25]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.068
+Data Delay   : 0.972
+
+Slack        : 0.788
+From Node    : counter[14]
+To Node      : counter[22]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.383
+Data Delay   : 1.315
++--------------------------------------------------------------------------------+
+
+
+
++--------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'                           ;
++--------------------------------------------------------------------------------+
+Slack          : -3.000
+Actual Width   : 1.000
+Required Width : 4.000
+Type           : Port Rate
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : CLOCK_50
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[0]~reg0
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[1]~reg0
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[2]~reg0
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[3]~reg0
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[4]~reg0
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[5]~reg0
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[6]~reg0
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[0]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[10]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[11]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[12]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[13]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[14]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[15]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[16]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[17]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[18]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[19]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[1]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[20]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[21]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[22]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[23]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[24]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[25]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[26]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[27]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[2]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[3]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[4]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[5]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[6]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[7]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[8]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[9]
+
+Slack          : 0.095
+Actual Width   : 0.279
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[13]
+
+Slack          : 0.095
+Actual Width   : 0.279
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[17]
+
+Slack          : 0.095
+Actual Width   : 0.279
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[18]
+
+Slack          : 0.095
+Actual Width   : 0.279
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[19]
+
+Slack          : 0.095
+Actual Width   : 0.279
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[20]
+
+Slack          : 0.095
+Actual Width   : 0.279
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[21]
+
+Slack          : 0.095
+Actual Width   : 0.279
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[22]
+
+Slack          : 0.095
+Actual Width   : 0.279
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[23]
+
+Slack          : 0.095
+Actual Width   : 0.279
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[24]
+
+Slack          : 0.095
+Actual Width   : 0.279
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[25]
+
+Slack          : 0.095
+Actual Width   : 0.279
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[26]
+
+Slack          : 0.095
+Actual Width   : 0.279
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[27]
+
+Slack          : 0.097
+Actual Width   : 0.281
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[0]~reg0
+
+Slack          : 0.097
+Actual Width   : 0.281
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[4]~reg0
+
+Slack          : 0.097
+Actual Width   : 0.281
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[5]~reg0
+
+Slack          : 0.097
+Actual Width   : 0.281
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[6]~reg0
+
+Slack          : 0.098
+Actual Width   : 0.282
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[1]~reg0
+
+Slack          : 0.098
+Actual Width   : 0.282
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[2]~reg0
+
+Slack          : 0.098
+Actual Width   : 0.282
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[3]~reg0
+
+Slack          : 0.098
+Actual Width   : 0.282
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[0]
+
+Slack          : 0.098
+Actual Width   : 0.282
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[10]
+
+Slack          : 0.098
+Actual Width   : 0.282
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[11]
+
+Slack          : 0.098
+Actual Width   : 0.282
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[12]
+
+Slack          : 0.098
+Actual Width   : 0.282
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[14]
+
+Slack          : 0.098
+Actual Width   : 0.282
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[15]
+
+Slack          : 0.098
+Actual Width   : 0.282
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[16]
+
+Slack          : 0.098
+Actual Width   : 0.282
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[1]
+
+Slack          : 0.098
+Actual Width   : 0.282
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[2]
+
+Slack          : 0.098
+Actual Width   : 0.282
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[3]
+
+Slack          : 0.098
+Actual Width   : 0.282
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[4]
+
+Slack          : 0.098
+Actual Width   : 0.282
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[5]
+
+Slack          : 0.098
+Actual Width   : 0.282
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[6]
+
+Slack          : 0.098
+Actual Width   : 0.282
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[7]
+
+Slack          : 0.098
+Actual Width   : 0.282
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[8]
+
+Slack          : 0.098
+Actual Width   : 0.282
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[9]
+
+Slack          : 0.251
+Actual Width   : 0.251
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : CLOCK_50~input|o
+
+Slack          : 0.255
+Actual Width   : 0.255
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[13]|clk
+
+Slack          : 0.255
+Actual Width   : 0.255
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[17]|clk
+
+Slack          : 0.255
+Actual Width   : 0.255
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[18]|clk
+
+Slack          : 0.255
+Actual Width   : 0.255
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[19]|clk
+
+Slack          : 0.255
+Actual Width   : 0.255
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[20]|clk
+
+Slack          : 0.255
+Actual Width   : 0.255
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[21]|clk
+
+Slack          : 0.255
+Actual Width   : 0.255
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[22]|clk
+
+Slack          : 0.255
+Actual Width   : 0.255
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[23]|clk
+
+Slack          : 0.255
+Actual Width   : 0.255
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[24]|clk
+
+Slack          : 0.255
+Actual Width   : 0.255
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[25]|clk
+
+Slack          : 0.255
+Actual Width   : 0.255
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[26]|clk
+
+Slack          : 0.255
+Actual Width   : 0.255
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[27]|clk
+
+Slack          : 0.257
+Actual Width   : 0.257
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[0]~reg0|clk
+
+Slack          : 0.257
+Actual Width   : 0.257
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[4]~reg0|clk
+
+Slack          : 0.257
+Actual Width   : 0.257
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[5]~reg0|clk
+
+Slack          : 0.257
+Actual Width   : 0.257
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[6]~reg0|clk
+
+Slack          : 0.258
+Actual Width   : 0.258
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[1]~reg0|clk
+
+Slack          : 0.258
+Actual Width   : 0.258
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[2]~reg0|clk
+
+Slack          : 0.258
+Actual Width   : 0.258
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[3]~reg0|clk
+
+Slack          : 0.258
+Actual Width   : 0.258
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[0]|clk
+
+Slack          : 0.258
+Actual Width   : 0.258
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[10]|clk
+
+Slack          : 0.258
+Actual Width   : 0.258
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[11]|clk
+
+Slack          : 0.258
+Actual Width   : 0.258
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[12]|clk
+
+Slack          : 0.258
+Actual Width   : 0.258
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[14]|clk
+
+Slack          : 0.258
+Actual Width   : 0.258
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[15]|clk
+
+Slack          : 0.258
+Actual Width   : 0.258
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[16]|clk
+
+Slack          : 0.258
+Actual Width   : 0.258
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[1]|clk
+
+Slack          : 0.258
+Actual Width   : 0.258
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[2]|clk
++--------------------------------------------------------------------------------+
+
+
+
++--------------------------------------------------------------------------------+
+; Clock to Output Times                                                          ;
++--------------------------------------------------------------------------------+
+Data Port       : LED[*]
+Clock Port      : CLOCK_50
+Rise            : 8.355
+Fall            : 7.943
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[0]
+Clock Port      : CLOCK_50
+Rise            : 4.866
+Fall            : 4.790
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[1]
+Clock Port      : CLOCK_50
+Rise            : 5.094
+Fall            : 4.999
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[2]
+Clock Port      : CLOCK_50
+Rise            : 5.080
+Fall            : 4.980
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[3]
+Clock Port      : CLOCK_50
+Rise            : 4.866
+Fall            : 4.790
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[4]
+Clock Port      : CLOCK_50
+Rise            : 6.680
+Fall            : 6.595
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[5]
+Clock Port      : CLOCK_50
+Rise            : 8.355
+Fall            : 7.943
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[6]
+Clock Port      : CLOCK_50
+Rise            : 5.527
+Fall            : 5.526
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
++--------------------------------------------------------------------------------+
+
+
+
++--------------------------------------------------------------------------------+
+; Minimum Clock to Output Times                                                  ;
++--------------------------------------------------------------------------------+
+Data Port       : LED[*]
+Clock Port      : CLOCK_50
+Rise            : 4.695
+Fall            : 4.618
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[0]
+Clock Port      : CLOCK_50
+Rise            : 4.695
+Fall            : 4.618
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[1]
+Clock Port      : CLOCK_50
+Rise            : 4.914
+Fall            : 4.819
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[2]
+Clock Port      : CLOCK_50
+Rise            : 4.900
+Fall            : 4.802
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[3]
+Clock Port      : CLOCK_50
+Rise            : 4.696
+Fall            : 4.619
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[4]
+Clock Port      : CLOCK_50
+Rise            : 6.438
+Fall            : 6.352
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[5]
+Clock Port      : CLOCK_50
+Rise            : 8.113
+Fall            : 7.701
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[6]
+Clock Port      : CLOCK_50
+Rise            : 5.328
+Fall            : 5.323
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
++--------------------------------------------------------------------------------+
+
+
+
+---------------------------------------------
+; Slow 1200mV 0C Model Metastability Report ;
+---------------------------------------------
+No synchronizer chains to report.
+
+
++--------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup Summary                                             ;
++--------------------------------------------------------------------------------+
+Clock         : CLOCK_50
+Slack         : -0.500
+End Point TNS : -4.764
++--------------------------------------------------------------------------------+
+
+
+
++--------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold Summary                                              ;
++--------------------------------------------------------------------------------+
+Clock         : CLOCK_50
+Slack         : 0.193
+End Point TNS : 0.000
++--------------------------------------------------------------------------------+
+
+
+
+-----------------------------------------
+; Fast 1200mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Fast 1200mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width Summary                               ;
++--------------------------------------------------------------------------------+
+Clock         : CLOCK_50
+Slack         : -3.000
+End Point TNS : -48.277
++--------------------------------------------------------------------------------+
+
+
+
++--------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'CLOCK_50'                                         ;
++--------------------------------------------------------------------------------+
+Slack        : -0.500
+From Node    : counter[2]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.639
+
+Slack        : -0.452
+From Node    : counter[1]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.591
+
+Slack        : -0.452
+From Node    : counter[0]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.591
+
+Slack        : -0.436
+From Node    : counter[2]
+To Node      : counter[26]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.575
+
+Slack        : -0.432
+From Node    : counter[2]
+To Node      : counter[25]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.571
+
+Slack        : -0.428
+From Node    : counter[4]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.567
+
+Slack        : -0.422
+From Node    : counter[1]
+To Node      : counter[26]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.561
+
+Slack        : -0.422
+From Node    : counter[0]
+To Node      : counter[26]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.561
+
+Slack        : -0.384
+From Node    : counter[1]
+To Node      : counter[25]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.523
+
+Slack        : -0.384
+From Node    : counter[0]
+To Node      : counter[25]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.523
+
+Slack        : -0.383
+From Node    : counter[3]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.522
+
+Slack        : -0.368
+From Node    : counter[2]
+To Node      : counter[24]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.507
+
+Slack        : -0.364
+From Node    : counter[2]
+To Node      : counter[23]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.503
+
+Slack        : -0.364
+From Node    : counter[6]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.503
+
+Slack        : -0.364
+From Node    : counter[4]
+To Node      : counter[26]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.503
+
+Slack        : -0.360
+From Node    : counter[4]
+To Node      : counter[25]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.499
+
+Slack        : -0.354
+From Node    : counter[3]
+To Node      : counter[26]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.493
+
+Slack        : -0.354
+From Node    : counter[1]
+To Node      : counter[24]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.493
+
+Slack        : -0.354
+From Node    : counter[0]
+To Node      : counter[24]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.493
+
+Slack        : -0.316
+From Node    : counter[5]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.455
+
+Slack        : -0.316
+From Node    : counter[1]
+To Node      : counter[23]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.455
+
+Slack        : -0.316
+From Node    : counter[0]
+To Node      : counter[23]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.455
+
+Slack        : -0.315
+From Node    : counter[3]
+To Node      : counter[25]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.454
+
+Slack        : -0.300
+From Node    : counter[2]
+To Node      : counter[22]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.439
+
+Slack        : -0.300
+From Node    : counter[6]
+To Node      : counter[26]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.439
+
+Slack        : -0.296
+From Node    : counter[2]
+To Node      : counter[21]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.435
+
+Slack        : -0.296
+From Node    : counter[8]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.435
+
+Slack        : -0.296
+From Node    : counter[6]
+To Node      : counter[25]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.435
+
+Slack        : -0.296
+From Node    : counter[4]
+To Node      : counter[24]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.435
+
+Slack        : -0.292
+From Node    : counter[4]
+To Node      : counter[23]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.431
+
+Slack        : -0.286
+From Node    : counter[2]
+To Node      : counter[16]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.038
+Data Delay   : 1.235
+
+Slack        : -0.286
+From Node    : counter[5]
+To Node      : counter[26]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.425
+
+Slack        : -0.286
+From Node    : counter[3]
+To Node      : counter[24]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.425
+
+Slack        : -0.286
+From Node    : counter[1]
+To Node      : counter[22]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.425
+
+Slack        : -0.286
+From Node    : counter[0]
+To Node      : counter[22]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.425
+
+Slack        : -0.282
+From Node    : counter[2]
+To Node      : counter[15]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.038
+Data Delay   : 1.231
+
+Slack        : -0.272
+From Node    : counter[1]
+To Node      : counter[16]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.038
+Data Delay   : 1.221
+
+Slack        : -0.272
+From Node    : counter[0]
+To Node      : counter[16]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.038
+Data Delay   : 1.221
+
+Slack        : -0.248
+From Node    : counter[7]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.387
+
+Slack        : -0.248
+From Node    : counter[5]
+To Node      : counter[25]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.387
+
+Slack        : -0.248
+From Node    : counter[1]
+To Node      : counter[21]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.387
+
+Slack        : -0.248
+From Node    : counter[0]
+To Node      : counter[21]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.387
+
+Slack        : -0.247
+From Node    : counter[3]
+To Node      : counter[23]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.386
+
+Slack        : -0.240
+From Node    : counter[13]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.045
+Data Delay   : 1.182
+
+Slack        : -0.234
+From Node    : counter[1]
+To Node      : counter[15]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.038
+Data Delay   : 1.183
+
+Slack        : -0.234
+From Node    : counter[0]
+To Node      : counter[15]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.038
+Data Delay   : 1.183
+
+Slack        : -0.232
+From Node    : counter[2]
+To Node      : counter[20]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.371
+
+Slack        : -0.232
+From Node    : counter[8]
+To Node      : counter[26]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.371
+
+Slack        : -0.232
+From Node    : counter[6]
+To Node      : counter[24]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.371
+
+Slack        : -0.228
+From Node    : counter[2]
+To Node      : counter[19]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.367
+
+Slack        : -0.228
+From Node    : counter[10]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.367
+
+Slack        : -0.228
+From Node    : counter[8]
+To Node      : counter[25]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.367
+
+Slack        : -0.228
+From Node    : counter[6]
+To Node      : counter[23]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.367
+
+Slack        : -0.228
+From Node    : counter[4]
+To Node      : counter[22]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.367
+
+Slack        : -0.224
+From Node    : counter[4]
+To Node      : counter[21]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.363
+
+Slack        : -0.219
+From Node    : counter[7]
+To Node      : counter[26]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.358
+
+Slack        : -0.218
+From Node    : counter[2]
+To Node      : counter[14]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.038
+Data Delay   : 1.167
+
+Slack        : -0.218
+From Node    : counter[5]
+To Node      : counter[24]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.357
+
+Slack        : -0.218
+From Node    : counter[3]
+To Node      : counter[22]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.357
+
+Slack        : -0.218
+From Node    : counter[1]
+To Node      : counter[20]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.357
+
+Slack        : -0.218
+From Node    : counter[0]
+To Node      : counter[20]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.357
+
+Slack        : -0.214
+From Node    : counter[4]
+To Node      : counter[16]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.038
+Data Delay   : 1.163
+
+Slack        : -0.210
+From Node    : counter[13]
+To Node      : counter[26]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.045
+Data Delay   : 1.152
+
+Slack        : -0.210
+From Node    : counter[4]
+To Node      : counter[15]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.038
+Data Delay   : 1.159
+
+Slack        : -0.204
+From Node    : counter[3]
+To Node      : counter[16]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.038
+Data Delay   : 1.153
+
+Slack        : -0.204
+From Node    : counter[1]
+To Node      : counter[14]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.038
+Data Delay   : 1.153
+
+Slack        : -0.204
+From Node    : counter[0]
+To Node      : counter[14]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.038
+Data Delay   : 1.153
+
+Slack        : -0.180
+From Node    : counter[7]
+To Node      : counter[25]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.319
+
+Slack        : -0.180
+From Node    : counter[5]
+To Node      : counter[23]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.319
+
+Slack        : -0.180
+From Node    : counter[1]
+To Node      : counter[19]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.319
+
+Slack        : -0.180
+From Node    : counter[0]
+To Node      : counter[19]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.319
+
+Slack        : -0.179
+From Node    : counter[9]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.318
+
+Slack        : -0.179
+From Node    : counter[3]
+To Node      : counter[21]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.318
+
+Slack        : -0.172
+From Node    : counter[13]
+To Node      : counter[25]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.045
+Data Delay   : 1.114
+
+Slack        : -0.165
+From Node    : counter[3]
+To Node      : counter[15]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.038
+Data Delay   : 1.114
+
+Slack        : -0.164
+From Node    : counter[2]
+To Node      : counter[18]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.303
+
+Slack        : -0.164
+From Node    : counter[10]
+To Node      : counter[26]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.303
+
+Slack        : -0.164
+From Node    : counter[8]
+To Node      : counter[24]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.303
+
+Slack        : -0.164
+From Node    : counter[6]
+To Node      : counter[22]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.303
+
+Slack        : -0.160
+From Node    : counter[2]
+To Node      : counter[17]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.299
+
+Slack        : -0.160
+From Node    : counter[12]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.299
+
+Slack        : -0.160
+From Node    : counter[10]
+To Node      : counter[25]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.299
+
+Slack        : -0.160
+From Node    : counter[8]
+To Node      : counter[23]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.299
+
+Slack        : -0.160
+From Node    : counter[6]
+To Node      : counter[21]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.299
+
+Slack        : -0.160
+From Node    : counter[4]
+To Node      : counter[20]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.299
+
+Slack        : -0.156
+From Node    : counter[4]
+To Node      : counter[19]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.295
+
+Slack        : -0.154
+From Node    : counter[18]
+To Node      : counter[27]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.045
+Data Delay   : 1.096
+
+Slack        : -0.151
+From Node    : counter[9]
+To Node      : counter[26]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.290
+
+Slack        : -0.151
+From Node    : counter[7]
+To Node      : counter[24]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.290
+
+Slack        : -0.150
+From Node    : counter[6]
+To Node      : counter[16]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.038
+Data Delay   : 1.099
+
+Slack        : -0.150
+From Node    : counter[5]
+To Node      : counter[22]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.289
+
+Slack        : -0.150
+From Node    : counter[3]
+To Node      : counter[20]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.289
+
+Slack        : -0.150
+From Node    : counter[1]
+To Node      : counter[18]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.289
+
+Slack        : -0.150
+From Node    : counter[0]
+To Node      : counter[18]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : 0.152
+Data Delay   : 1.289
+
+Slack        : -0.149
+From Node    : counter[2]
+To Node      : counter[12]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.037
+Data Delay   : 1.099
+
+Slack        : -0.146
+From Node    : counter[6]
+To Node      : counter[15]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.038
+Data Delay   : 1.095
+
+Slack        : -0.146
+From Node    : counter[4]
+To Node      : counter[14]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.038
+Data Delay   : 1.095
+
+Slack        : -0.145
+From Node    : counter[2]
+To Node      : counter[11]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.037
+Data Delay   : 1.095
+
+Slack        : -0.142
+From Node    : counter[13]
+To Node      : counter[24]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.045
+Data Delay   : 1.084
+
+Slack        : -0.136
+From Node    : counter[5]
+To Node      : counter[16]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 1.000
+Clock Skew   : -0.038
+Data Delay   : 1.085
++--------------------------------------------------------------------------------+
+
+
+
++--------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'CLOCK_50'                                          ;
++--------------------------------------------------------------------------------+
+Slack        : 0.193
+From Node    : counter[0]
+To Node      : counter[0]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.037
+Data Delay   : 0.314
+
+Slack        : 0.244
+From Node    : counter[16]
+To Node      : counter[17]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.235
+Data Delay   : 0.563
+
+Slack        : 0.245
+From Node    : counter[12]
+To Node      : counter[13]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.234
+Data Delay   : 0.563
+
+Slack        : 0.257
+From Node    : counter[15]
+To Node      : counter[17]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.235
+Data Delay   : 0.576
+
+Slack        : 0.257
+From Node    : counter[11]
+To Node      : counter[13]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.234
+Data Delay   : 0.575
+
+Slack        : 0.284
+From Node    : counter[13]
+To Node      : counter[13]
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : 0.045
+Data Delay   : 0.413
+
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+Data Delay   : 0.589
+
+Slack        : 0.469
+From Node    : counter[24]
+To Node      : LED[3]~reg0
+Launch Clock : CLOCK_50
+Latch Clock  : CLOCK_50
+Relationship : 0.000
+Clock Skew   : -0.152
+Data Delay   : 0.401
++--------------------------------------------------------------------------------+
+
+
+
++--------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'                           ;
++--------------------------------------------------------------------------------+
+Slack          : -3.000
+Actual Width   : 1.000
+Required Width : 4.000
+Type           : Port Rate
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : CLOCK_50
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[0]~reg0
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[1]~reg0
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[2]~reg0
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[3]~reg0
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[4]~reg0
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[5]~reg0
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[6]~reg0
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[0]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[10]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[11]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[12]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[13]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[14]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[15]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[16]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[17]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[18]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[19]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[1]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[20]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[21]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[22]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[23]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[24]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[25]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[26]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[27]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[2]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[3]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[4]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[5]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[6]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[7]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[8]
+
+Slack          : -1.000
+Actual Width   : 1.000
+Required Width : 2.000
+Type           : Min Period
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[9]
+
+Slack          : -0.251
+Actual Width   : -0.067
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[13]
+
+Slack          : -0.251
+Actual Width   : -0.067
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[17]
+
+Slack          : -0.251
+Actual Width   : -0.067
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[18]
+
+Slack          : -0.251
+Actual Width   : -0.067
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[19]
+
+Slack          : -0.251
+Actual Width   : -0.067
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[20]
+
+Slack          : -0.251
+Actual Width   : -0.067
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[21]
+
+Slack          : -0.251
+Actual Width   : -0.067
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[22]
+
+Slack          : -0.251
+Actual Width   : -0.067
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[23]
+
+Slack          : -0.251
+Actual Width   : -0.067
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[24]
+
+Slack          : -0.251
+Actual Width   : -0.067
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[25]
+
+Slack          : -0.251
+Actual Width   : -0.067
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[26]
+
+Slack          : -0.251
+Actual Width   : -0.067
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[27]
+
+Slack          : -0.227
+Actual Width   : -0.043
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[1]~reg0
+
+Slack          : -0.227
+Actual Width   : -0.043
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[2]~reg0
+
+Slack          : -0.227
+Actual Width   : -0.043
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[3]~reg0
+
+Slack          : -0.227
+Actual Width   : -0.043
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[14]
+
+Slack          : -0.227
+Actual Width   : -0.043
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[15]
+
+Slack          : -0.227
+Actual Width   : -0.043
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[16]
+
+Slack          : -0.226
+Actual Width   : -0.042
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[0]~reg0
+
+Slack          : -0.226
+Actual Width   : -0.042
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[4]~reg0
+
+Slack          : -0.226
+Actual Width   : -0.042
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[5]~reg0
+
+Slack          : -0.226
+Actual Width   : -0.042
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[6]~reg0
+
+Slack          : -0.226
+Actual Width   : -0.042
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[0]
+
+Slack          : -0.226
+Actual Width   : -0.042
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[10]
+
+Slack          : -0.226
+Actual Width   : -0.042
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[11]
+
+Slack          : -0.226
+Actual Width   : -0.042
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[12]
+
+Slack          : -0.226
+Actual Width   : -0.042
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[1]
+
+Slack          : -0.226
+Actual Width   : -0.042
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[2]
+
+Slack          : -0.226
+Actual Width   : -0.042
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[3]
+
+Slack          : -0.226
+Actual Width   : -0.042
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[4]
+
+Slack          : -0.226
+Actual Width   : -0.042
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[5]
+
+Slack          : -0.226
+Actual Width   : -0.042
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[6]
+
+Slack          : -0.226
+Actual Width   : -0.042
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[7]
+
+Slack          : -0.226
+Actual Width   : -0.042
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[8]
+
+Slack          : -0.226
+Actual Width   : -0.042
+Required Width : 0.184
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[9]
+
+Slack          : -0.071
+Actual Width   : -0.071
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[13]|clk
+
+Slack          : -0.071
+Actual Width   : -0.071
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[17]|clk
+
+Slack          : -0.071
+Actual Width   : -0.071
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[18]|clk
+
+Slack          : -0.071
+Actual Width   : -0.071
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[19]|clk
+
+Slack          : -0.071
+Actual Width   : -0.071
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[20]|clk
+
+Slack          : -0.071
+Actual Width   : -0.071
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[21]|clk
+
+Slack          : -0.071
+Actual Width   : -0.071
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[22]|clk
+
+Slack          : -0.071
+Actual Width   : -0.071
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[23]|clk
+
+Slack          : -0.071
+Actual Width   : -0.071
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[24]|clk
+
+Slack          : -0.071
+Actual Width   : -0.071
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[25]|clk
+
+Slack          : -0.071
+Actual Width   : -0.071
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[26]|clk
+
+Slack          : -0.071
+Actual Width   : -0.071
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[27]|clk
+
+Slack          : -0.051
+Actual Width   : -0.051
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : CLOCK_50~input|o
+
+Slack          : -0.048
+Actual Width   : -0.048
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[14]|clk
+
+Slack          : -0.048
+Actual Width   : -0.048
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[15]|clk
+
+Slack          : -0.048
+Actual Width   : -0.048
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[16]|clk
+
+Slack          : -0.047
+Actual Width   : -0.047
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[1]~reg0|clk
+
+Slack          : -0.047
+Actual Width   : -0.047
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[2]~reg0|clk
+
+Slack          : -0.047
+Actual Width   : -0.047
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : LED[3]~reg0|clk
+
+Slack          : -0.047
+Actual Width   : -0.047
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[0]|clk
+
+Slack          : -0.047
+Actual Width   : -0.047
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[10]|clk
+
+Slack          : -0.047
+Actual Width   : -0.047
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[11]|clk
+
+Slack          : -0.047
+Actual Width   : -0.047
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[12]|clk
+
+Slack          : -0.047
+Actual Width   : -0.047
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[1]|clk
+
+Slack          : -0.047
+Actual Width   : -0.047
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[2]|clk
+
+Slack          : -0.047
+Actual Width   : -0.047
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[3]|clk
+
+Slack          : -0.047
+Actual Width   : -0.047
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[4]|clk
+
+Slack          : -0.047
+Actual Width   : -0.047
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[5]|clk
+
+Slack          : -0.047
+Actual Width   : -0.047
+Required Width : 0.000
+Type           : Low Pulse Width
+Clock          : CLOCK_50
+Clock Edge     : Rise
+Target         : counter[6]|clk
++--------------------------------------------------------------------------------+
+
+
+
++--------------------------------------------------------------------------------+
+; Clock to Output Times                                                          ;
++--------------------------------------------------------------------------------+
+Data Port       : LED[*]
+Clock Port      : CLOCK_50
+Rise            : 5.723
+Fall            : 5.678
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[0]
+Clock Port      : CLOCK_50
+Rise            : 3.173
+Fall            : 3.159
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[1]
+Clock Port      : CLOCK_50
+Rise            : 3.305
+Fall            : 3.303
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[2]
+Clock Port      : CLOCK_50
+Rise            : 3.295
+Fall            : 3.291
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[3]
+Clock Port      : CLOCK_50
+Rise            : 3.174
+Fall            : 3.161
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[4]
+Clock Port      : CLOCK_50
+Rise            : 4.301
+Fall            : 4.440
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[5]
+Clock Port      : CLOCK_50
+Rise            : 5.723
+Fall            : 5.678
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[6]
+Clock Port      : CLOCK_50
+Rise            : 3.602
+Fall            : 3.688
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
++--------------------------------------------------------------------------------+
+
+
+
++--------------------------------------------------------------------------------+
+; Minimum Clock to Output Times                                                  ;
++--------------------------------------------------------------------------------+
+Data Port       : LED[*]
+Clock Port      : CLOCK_50
+Rise            : 3.068
+Fall            : 3.052
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[0]
+Clock Port      : CLOCK_50
+Rise            : 3.068
+Fall            : 3.052
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[1]
+Clock Port      : CLOCK_50
+Rise            : 3.194
+Fall            : 3.189
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[2]
+Clock Port      : CLOCK_50
+Rise            : 3.184
+Fall            : 3.177
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[3]
+Clock Port      : CLOCK_50
+Rise            : 3.068
+Fall            : 3.052
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[4]
+Clock Port      : CLOCK_50
+Rise            : 4.154
+Fall            : 4.284
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[5]
+Clock Port      : CLOCK_50
+Rise            : 5.577
+Fall            : 5.523
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[6]
+Clock Port      : CLOCK_50
+Rise            : 3.480
+Fall            : 3.561
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
++--------------------------------------------------------------------------------+
+
+
+
+---------------------------------------------
+; Fast 1200mV 0C Model Metastability Report ;
+---------------------------------------------
+No synchronizer chains to report.
+
+
++--------------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary                                            ;
++--------------------------------------------------------------------------------+
+Clock               : Worst-case Slack
+Setup               : -1.606
+Hold                : 0.193
+Recovery            : N/A
+Removal             : N/A
+Minimum Pulse Width : -3.000
+
+Clock               :  CLOCK_50
+Setup               : -1.606
+Hold                : 0.193
+Recovery            : N/A
+Removal             : N/A
+Minimum Pulse Width : -3.000
+
+Clock               : Design-wide TNS
+Setup               : -30.234
+Hold                : 0.0
+Recovery            : 0.0
+Removal             : 0.0
+Minimum Pulse Width : -48.277
+
+Clock               :  CLOCK_50
+Setup               : -30.234
+Hold                : 0.000
+Recovery            : N/A
+Removal             : N/A
+Minimum Pulse Width : -48.277
++--------------------------------------------------------------------------------+
+
+
+
++--------------------------------------------------------------------------------+
+; Clock to Output Times                                                          ;
++--------------------------------------------------------------------------------+
+Data Port       : LED[*]
+Clock Port      : CLOCK_50
+Rise            : 9.276
+Fall            : 9.028
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[0]
+Clock Port      : CLOCK_50
+Rise            : 5.406
+Fall            : 5.347
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[1]
+Clock Port      : CLOCK_50
+Rise            : 5.653
+Fall            : 5.580
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[2]
+Clock Port      : CLOCK_50
+Rise            : 5.633
+Fall            : 5.560
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[3]
+Clock Port      : CLOCK_50
+Rise            : 5.406
+Fall            : 5.347
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[4]
+Clock Port      : CLOCK_50
+Rise            : 7.391
+Fall            : 7.410
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[5]
+Clock Port      : CLOCK_50
+Rise            : 9.276
+Fall            : 9.028
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[6]
+Clock Port      : CLOCK_50
+Rise            : 6.114
+Fall            : 6.176
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
++--------------------------------------------------------------------------------+
+
+
+
++--------------------------------------------------------------------------------+
+; Minimum Clock to Output Times                                                  ;
++--------------------------------------------------------------------------------+
+Data Port       : LED[*]
+Clock Port      : CLOCK_50
+Rise            : 3.068
+Fall            : 3.052
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[0]
+Clock Port      : CLOCK_50
+Rise            : 3.068
+Fall            : 3.052
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[1]
+Clock Port      : CLOCK_50
+Rise            : 3.194
+Fall            : 3.189
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[2]
+Clock Port      : CLOCK_50
+Rise            : 3.184
+Fall            : 3.177
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[3]
+Clock Port      : CLOCK_50
+Rise            : 3.068
+Fall            : 3.052
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[4]
+Clock Port      : CLOCK_50
+Rise            : 4.154
+Fall            : 4.284
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[5]
+Clock Port      : CLOCK_50
+Rise            : 5.577
+Fall            : 5.523
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
+
+Data Port       :  LED[6]
+Clock Port      : CLOCK_50
+Rise            : 3.480
+Fall            : 3.561
+Clock Edge      : Rise
+Clock Reference : CLOCK_50
++--------------------------------------------------------------------------------+
+
+
+
++--------------------------------------------------------------------------------+
+; Board Trace Model Assignments                                                  ;
++--------------------------------------------------------------------------------+
+Pin                     : LED[0]
+I/O Standard            : 3.3-V LVTTL
+Near Tline Length       : 0 in
+Near Tline L per Length : 0 H/in
+Near Tline C per Length : 0 F/in
+Near Series R           : short
+Near Differential R     : -
+Near Pull-up R          : open
+Near Pull-down R        : open
+Near C                  : open
+Far Tline Length        : 0 in
+Far Tline L per Length  : 0 H/in
+Far Tline C per Length  : 0 F/in
+Far Series R            : short
+Far Pull-up R           : open
+Far Pull-down R         : open
+Far C                   : open
+Termination Voltage     : 0 V
+Far Differential R      : -
+EBD File Name           : n/a
+EBD Signal Name         : n/a
+EBD Far-end             : n/a
+
+Pin                     : LED[1]
+I/O Standard            : 3.3-V LVTTL
+Near Tline Length       : 0 in
+Near Tline L per Length : 0 H/in
+Near Tline C per Length : 0 F/in
+Near Series R           : short
+Near Differential R     : -
+Near Pull-up R          : open
+Near Pull-down R        : open
+Near C                  : open
+Far Tline Length        : 0 in
+Far Tline L per Length  : 0 H/in
+Far Tline C per Length  : 0 F/in
+Far Series R            : short
+Far Pull-up R           : open
+Far Pull-down R         : open
+Far C                   : open
+Termination Voltage     : 0 V
+Far Differential R      : -
+EBD File Name           : n/a
+EBD Signal Name         : n/a
+EBD Far-end             : n/a
+
+Pin                     : LED[2]
+I/O Standard            : 3.3-V LVTTL
+Near Tline Length       : 0 in
+Near Tline L per Length : 0 H/in
+Near Tline C per Length : 0 F/in
+Near Series R           : short
+Near Differential R     : -
+Near Pull-up R          : open
+Near Pull-down R        : open
+Near C                  : open
+Far Tline Length        : 0 in
+Far Tline L per Length  : 0 H/in
+Far Tline C per Length  : 0 F/in
+Far Series R            : short
+Far Pull-up R           : open
+Far Pull-down R         : open
+Far C                   : open
+Termination Voltage     : 0 V
+Far Differential R      : -
+EBD File Name           : n/a
+EBD Signal Name         : n/a
+EBD Far-end             : n/a
+
+Pin                     : LED[3]
+I/O Standard            : 3.3-V LVTTL
+Near Tline Length       : 0 in
+Near Tline L per Length : 0 H/in
+Near Tline C per Length : 0 F/in
+Near Series R           : short
+Near Differential R     : -
+Near Pull-up R          : open
+Near Pull-down R        : open
+Near C                  : open
+Far Tline Length        : 0 in
+Far Tline L per Length  : 0 H/in
+Far Tline C per Length  : 0 F/in
+Far Series R            : short
+Far Pull-up R           : open
+Far Pull-down R         : open
+Far C                   : open
+Termination Voltage     : 0 V
+Far Differential R      : -
+EBD File Name           : n/a
+EBD Signal Name         : n/a
+EBD Far-end             : n/a
+
+Pin                     : LED[4]
+I/O Standard            : 3.3-V LVTTL
+Near Tline Length       : 0 in
+Near Tline L per Length : 0 H/in
+Near Tline C per Length : 0 F/in
+Near Series R           : short
+Near Differential R     : -
+Near Pull-up R          : open
+Near Pull-down R        : open
+Near C                  : open
+Far Tline Length        : 0 in
+Far Tline L per Length  : 0 H/in
+Far Tline C per Length  : 0 F/in
+Far Series R            : short
+Far Pull-up R           : open
+Far Pull-down R         : open
+Far C                   : open
+Termination Voltage     : 0 V
+Far Differential R      : -
+EBD File Name           : n/a
+EBD Signal Name         : n/a
+EBD Far-end             : n/a
+
+Pin                     : LED[5]
+I/O Standard            : 3.3-V LVTTL
+Near Tline Length       : 0 in
+Near Tline L per Length : 0 H/in
+Near Tline C per Length : 0 F/in
+Near Series R           : short
+Near Differential R     : -
+Near Pull-up R          : open
+Near Pull-down R        : open
+Near C                  : open
+Far Tline Length        : 0 in
+Far Tline L per Length  : 0 H/in
+Far Tline C per Length  : 0 F/in
+Far Series R            : short
+Far Pull-up R           : open
+Far Pull-down R         : open
+Far C                   : open
+Termination Voltage     : 0 V
+Far Differential R      : -
+EBD File Name           : n/a
+EBD Signal Name         : n/a
+EBD Far-end             : n/a
+
+Pin                     : LED[6]
+I/O Standard            : 3.3-V LVTTL
+Near Tline Length       : 0 in
+Near Tline L per Length : 0 H/in
+Near Tline C per Length : 0 F/in
+Near Series R           : short
+Near Differential R     : -
+Near Pull-up R          : open
+Near Pull-down R        : open
+Near C                  : open
+Far Tline Length        : 0 in
+Far Tline L per Length  : 0 H/in
+Far Tline C per Length  : 0 F/in
+Far Series R            : short
+Far Pull-up R           : open
+Far Pull-down R         : open
+Far C                   : open
+Termination Voltage     : 0 V
+Far Differential R      : -
+EBD File Name           : n/a
+EBD Signal Name         : n/a
+EBD Far-end             : n/a
+
+Pin                     : LED[7]
+I/O Standard            : 3.3-V LVTTL
+Near Tline Length       : 0 in
+Near Tline L per Length : 0 H/in
+Near Tline C per Length : 0 F/in
+Near Series R           : short
+Near Differential R     : -
+Near Pull-up R          : open
+Near Pull-down R        : open
+Near C                  : open
+Far Tline Length        : 0 in
+Far Tline L per Length  : 0 H/in
+Far Tline C per Length  : 0 F/in
+Far Series R            : short
+Far Pull-up R           : open
+Far Pull-down R         : open
+Far C                   : open
+Termination Voltage     : 0 V
+Far Differential R      : -
+EBD File Name           : n/a
+EBD Signal Name         : n/a
+EBD Far-end             : n/a
+
+Pin                     : ~ALTERA_DCLK~
+I/O Standard            : 3.3-V LVTTL
+Near Tline Length       : 0 in
+Near Tline L per Length : 0 H/in
+Near Tline C per Length : 0 F/in
+Near Series R           : short
+Near Differential R     : -
+Near Pull-up R          : open
+Near Pull-down R        : open
+Near C                  : open
+Far Tline Length        : 0 in
+Far Tline L per Length  : 0 H/in
+Far Tline C per Length  : 0 F/in
+Far Series R            : short
+Far Pull-up R           : open
+Far Pull-down R         : open
+Far C                   : open
+Termination Voltage     : 0 V
+Far Differential R      : -
+EBD File Name           : n/a
+EBD Signal Name         : n/a
+EBD Far-end             : n/a
+
+Pin                     : ~ALTERA_nCEO~
+I/O Standard            : 2.5 V
+Near Tline Length       : 0 in
+Near Tline L per Length : 0 H/in
+Near Tline C per Length : 0 F/in
+Near Series R           : short
+Near Differential R     : -
+Near Pull-up R          : open
+Near Pull-down R        : open
+Near C                  : open
+Far Tline Length        : 0 in
+Far Tline L per Length  : 0 H/in
+Far Tline C per Length  : 0 F/in
+Far Series R            : short
+Far Pull-up R           : open
+Far Pull-down R         : open
+Far C                   : open
+Termination Voltage     : 0 V
+Far Differential R      : -
+EBD File Name           : n/a
+EBD Signal Name         : n/a
+EBD Far-end             : n/a
++--------------------------------------------------------------------------------+
+
+
+
++--------------------------------------------------------------------------------+
+; Input Transition Times                                                         ;
++--------------------------------------------------------------------------------+
+Pin             : CLOCK_50
+I/O Standard    : 3.3-V LVTTL
+10-90 Rise Time : 2640 ps
+90-10 Fall Time : 2640 ps
+
+Pin             : ~ALTERA_ASDO_DATA1~
+I/O Standard    : 3.3-V LVTTL
+10-90 Rise Time : 2640 ps
+90-10 Fall Time : 2640 ps
+
+Pin             : ~ALTERA_FLASH_nCE_nCSO~
+I/O Standard    : 3.3-V LVTTL
+10-90 Rise Time : 2640 ps
+90-10 Fall Time : 2640 ps
+
+Pin             : ~ALTERA_DATA0~
+I/O Standard    : 3.3-V LVTTL
+10-90 Rise Time : 2640 ps
+90-10 Fall Time : 2640 ps
++--------------------------------------------------------------------------------+
+
+
+
++--------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1200mv 0c Model)                                ;
++--------------------------------------------------------------------------------+
+Pin                                  : LED[0]
+I/O Standard                         : 3.3-V LVTTL
+Board Delay on Rise                  : 0 s
+Board Delay on Fall                  : 0 s
+Steady State Voh at FPGA Pin         : 3.08 V
+Steady State Vol at FPGA Pin         : 2.24e-08 V
+Voh Max at FPGA Pin                  : 3.14 V
+Vol Min at FPGA Pin                  : -0.115 V
+Ringback Voltage on Rise at FPGA Pin : 0.31 V
+Ringback Voltage on Fall at FPGA Pin : 0.241 V
+10-90 Rise Time at FPGA Pin          : 5.06e-10 s
+90-10 Fall Time at FPGA Pin          : 4.37e-10 s
+Monotonic Rise at FPGA Pin           : No
+Monotonic Fall at FPGA Pin           : No
+Steady State Voh at Far-end          : 3.08 V
+Steady State Vol at Far-end          : 2.24e-08 V
+Voh Max at Far-end                   : 3.14 V
+Vol Min at Far-end                   : -0.115 V
+Ringback Voltage on Rise at Far-end  : 0.31 V
+Ringback Voltage on Fall at Far-end  : 0.241 V
+10-90 Rise Time at Far-end           : 5.06e-10 s
+90-10 Fall Time at Far-end           : 4.37e-10 s
+Monotonic Rise at Far-end            : No
+Monotonic Fall at Far-end            : No
+
+Pin                                  : LED[1]
+I/O Standard                         : 3.3-V LVTTL
+Board Delay on Rise                  : 0 s
+Board Delay on Fall                  : 0 s
+Steady State Voh at FPGA Pin         : 3.08 V
+Steady State Vol at FPGA Pin         : 2.24e-08 V
+Voh Max at FPGA Pin                  : 3.14 V
+Vol Min at FPGA Pin                  : -0.115 V
+Ringback Voltage on Rise at FPGA Pin : 0.31 V
+Ringback Voltage on Fall at FPGA Pin : 0.241 V
+10-90 Rise Time at FPGA Pin          : 5.06e-10 s
+90-10 Fall Time at FPGA Pin          : 4.37e-10 s
+Monotonic Rise at FPGA Pin           : No
+Monotonic Fall at FPGA Pin           : No
+Steady State Voh at Far-end          : 3.08 V
+Steady State Vol at Far-end          : 2.24e-08 V
+Voh Max at Far-end                   : 3.14 V
+Vol Min at Far-end                   : -0.115 V
+Ringback Voltage on Rise at Far-end  : 0.31 V
+Ringback Voltage on Fall at Far-end  : 0.241 V
+10-90 Rise Time at Far-end           : 5.06e-10 s
+90-10 Fall Time at Far-end           : 4.37e-10 s
+Monotonic Rise at Far-end            : No
+Monotonic Fall at Far-end            : No
+
+Pin                                  : LED[2]
+I/O Standard                         : 3.3-V LVTTL
+Board Delay on Rise                  : 0 s
+Board Delay on Fall                  : 0 s
+Steady State Voh at FPGA Pin         : 3.08 V
+Steady State Vol at FPGA Pin         : 2.24e-08 V
+Voh Max at FPGA Pin                  : 3.14 V
+Vol Min at FPGA Pin                  : -0.115 V
+Ringback Voltage on Rise at FPGA Pin : 0.31 V
+Ringback Voltage on Fall at FPGA Pin : 0.241 V
+10-90 Rise Time at FPGA Pin          : 5.06e-10 s
+90-10 Fall Time at FPGA Pin          : 4.37e-10 s
+Monotonic Rise at FPGA Pin           : No
+Monotonic Fall at FPGA Pin           : No
+Steady State Voh at Far-end          : 3.08 V
+Steady State Vol at Far-end          : 2.24e-08 V
+Voh Max at Far-end                   : 3.14 V
+Vol Min at Far-end                   : -0.115 V
+Ringback Voltage on Rise at Far-end  : 0.31 V
+Ringback Voltage on Fall at Far-end  : 0.241 V
+10-90 Rise Time at Far-end           : 5.06e-10 s
+90-10 Fall Time at Far-end           : 4.37e-10 s
+Monotonic Rise at Far-end            : No
+Monotonic Fall at Far-end            : No
+
+Pin                                  : LED[3]
+I/O Standard                         : 3.3-V LVTTL
+Board Delay on Rise                  : 0 s
+Board Delay on Fall                  : 0 s
+Steady State Voh at FPGA Pin         : 3.08 V
+Steady State Vol at FPGA Pin         : 2.24e-08 V
+Voh Max at FPGA Pin                  : 3.14 V
+Vol Min at FPGA Pin                  : -0.115 V
+Ringback Voltage on Rise at FPGA Pin : 0.31 V
+Ringback Voltage on Fall at FPGA Pin : 0.241 V
+10-90 Rise Time at FPGA Pin          : 5.06e-10 s
+90-10 Fall Time at FPGA Pin          : 4.37e-10 s
+Monotonic Rise at FPGA Pin           : No
+Monotonic Fall at FPGA Pin           : No
+Steady State Voh at Far-end          : 3.08 V
+Steady State Vol at Far-end          : 2.24e-08 V
+Voh Max at Far-end                   : 3.14 V
+Vol Min at Far-end                   : -0.115 V
+Ringback Voltage on Rise at Far-end  : 0.31 V
+Ringback Voltage on Fall at Far-end  : 0.241 V
+10-90 Rise Time at Far-end           : 5.06e-10 s
+90-10 Fall Time at Far-end           : 4.37e-10 s
+Monotonic Rise at Far-end            : No
+Monotonic Fall at Far-end            : No
+
+Pin                                  : LED[4]
+I/O Standard                         : 3.3-V LVTTL
+Board Delay on Rise                  : 0 s
+Board Delay on Fall                  : 0 s
+Steady State Voh at FPGA Pin         : 3.08 V
+Steady State Vol at FPGA Pin         : 1.54e-08 V
+Voh Max at FPGA Pin                  : 3.14 V
+Vol Min at FPGA Pin                  : -0.074 V
+Ringback Voltage on Rise at FPGA Pin : 0.343 V
+Ringback Voltage on Fall at FPGA Pin : 0.194 V
+10-90 Rise Time at FPGA Pin          : 7.35e-10 s
+90-10 Fall Time at FPGA Pin          : 6.36e-10 s
+Monotonic Rise at FPGA Pin           : No
+Monotonic Fall at FPGA Pin           : No
+Steady State Voh at Far-end          : 3.08 V
+Steady State Vol at Far-end          : 1.54e-08 V
+Voh Max at Far-end                   : 3.14 V
+Vol Min at Far-end                   : -0.074 V
+Ringback Voltage on Rise at Far-end  : 0.343 V
+Ringback Voltage on Fall at Far-end  : 0.194 V
+10-90 Rise Time at Far-end           : 7.35e-10 s
+90-10 Fall Time at Far-end           : 6.36e-10 s
+Monotonic Rise at Far-end            : No
+Monotonic Fall at Far-end            : No
+
+Pin                                  : LED[5]
+I/O Standard                         : 3.3-V LVTTL
+Board Delay on Rise                  : 0 s
+Board Delay on Fall                  : 0 s
+Steady State Voh at FPGA Pin         : 3.08 V
+Steady State Vol at FPGA Pin         : 1.54e-08 V
+Voh Max at FPGA Pin                  : 3.09 V
+Vol Min at FPGA Pin                  : -0.0119 V
+Ringback Voltage on Rise at FPGA Pin : 0.277 V
+Ringback Voltage on Fall at FPGA Pin : 0.297 V
+10-90 Rise Time at FPGA Pin          : 4.54e-09 s
+90-10 Fall Time at FPGA Pin          : 3.32e-09 s
+Monotonic Rise at FPGA Pin           : No
+Monotonic Fall at FPGA Pin           : No
+Steady State Voh at Far-end          : 3.08 V
+Steady State Vol at Far-end          : 1.54e-08 V
+Voh Max at Far-end                   : 3.09 V
+Vol Min at Far-end                   : -0.0119 V
+Ringback Voltage on Rise at Far-end  : 0.277 V
+Ringback Voltage on Fall at Far-end  : 0.297 V
+10-90 Rise Time at Far-end           : 4.54e-09 s
+90-10 Fall Time at Far-end           : 3.32e-09 s
+Monotonic Rise at Far-end            : No
+Monotonic Fall at Far-end            : No
+
+Pin                                  : LED[6]
+I/O Standard                         : 3.3-V LVTTL
+Board Delay on Rise                  : 0 s
+Board Delay on Fall                  : 0 s
+Steady State Voh at FPGA Pin         : 3.08 V
+Steady State Vol at FPGA Pin         : 1.54e-08 V
+Voh Max at FPGA Pin                  : 3.16 V
+Vol Min at FPGA Pin                  : -0.11 V
+Ringback Voltage on Rise at FPGA Pin : 0.302 V
+Ringback Voltage on Fall at FPGA Pin : 0.22 V
+10-90 Rise Time at FPGA Pin          : 4.82e-10 s
+90-10 Fall Time at FPGA Pin          : 4.27e-10 s
+Monotonic Rise at FPGA Pin           : Yes
+Monotonic Fall at FPGA Pin           : No
+Steady State Voh at Far-end          : 3.08 V
+Steady State Vol at Far-end          : 1.54e-08 V
+Voh Max at Far-end                   : 3.16 V
+Vol Min at Far-end                   : -0.11 V
+Ringback Voltage on Rise at Far-end  : 0.302 V
+Ringback Voltage on Fall at Far-end  : 0.22 V
+10-90 Rise Time at Far-end           : 4.82e-10 s
+90-10 Fall Time at Far-end           : 4.27e-10 s
+Monotonic Rise at Far-end            : Yes
+Monotonic Fall at Far-end            : No
+
+Pin                                  : LED[7]
+I/O Standard                         : 3.3-V LVTTL
+Board Delay on Rise                  : 0 s
+Board Delay on Fall                  : 0 s
+Steady State Voh at FPGA Pin         : 3.08 V
+Steady State Vol at FPGA Pin         : 1.54e-08 V
+Voh Max at FPGA Pin                  : 3.09 V
+Vol Min at FPGA Pin                  : -0.0119 V
+Ringback Voltage on Rise at FPGA Pin : 0.277 V
+Ringback Voltage on Fall at FPGA Pin : 0.297 V
+10-90 Rise Time at FPGA Pin          : 4.54e-09 s
+90-10 Fall Time at FPGA Pin          : 3.32e-09 s
+Monotonic Rise at FPGA Pin           : No
+Monotonic Fall at FPGA Pin           : No
+Steady State Voh at Far-end          : 3.08 V
+Steady State Vol at Far-end          : 1.54e-08 V
+Voh Max at Far-end                   : 3.09 V
+Vol Min at Far-end                   : -0.0119 V
+Ringback Voltage on Rise at Far-end  : 0.277 V
+Ringback Voltage on Fall at Far-end  : 0.297 V
+10-90 Rise Time at Far-end           : 4.54e-09 s
+90-10 Fall Time at Far-end           : 3.32e-09 s
+Monotonic Rise at Far-end            : No
+Monotonic Fall at Far-end            : No
+
+Pin                                  : ~ALTERA_DCLK~
+I/O Standard                         : 3.3-V LVTTL
+Board Delay on Rise                  : 0 s
+Board Delay on Fall                  : 0 s
+Steady State Voh at FPGA Pin         : 3.08 V
+Steady State Vol at FPGA Pin         : 8.05e-09 V
+Voh Max at FPGA Pin                  : 3.21 V
+Vol Min at FPGA Pin                  : -0.181 V
+Ringback Voltage on Rise at FPGA Pin : 0.16 V
+Ringback Voltage on Fall at FPGA Pin : 0.253 V
+10-90 Rise Time at FPGA Pin          : 2.77e-10 s
+90-10 Fall Time at FPGA Pin          : 2.32e-10 s
+Monotonic Rise at FPGA Pin           : No
+Monotonic Fall at FPGA Pin           : Yes
+Steady State Voh at Far-end          : 3.08 V
+Steady State Vol at Far-end          : 8.05e-09 V
+Voh Max at Far-end                   : 3.21 V
+Vol Min at Far-end                   : -0.181 V
+Ringback Voltage on Rise at Far-end  : 0.16 V
+Ringback Voltage on Fall at Far-end  : 0.253 V
+10-90 Rise Time at Far-end           : 2.77e-10 s
+90-10 Fall Time at Far-end           : 2.32e-10 s
+Monotonic Rise at Far-end            : No
+Monotonic Fall at Far-end            : Yes
+
+Pin                                  : ~ALTERA_nCEO~
+I/O Standard                         : 2.5 V
+Board Delay on Rise                  : 0 s
+Board Delay on Fall                  : 0 s
+Steady State Voh at FPGA Pin         : 2.32 V
+Steady State Vol at FPGA Pin         : 5.61e-09 V
+Voh Max at FPGA Pin                  : 2.38 V
+Vol Min at FPGA Pin                  : -0.00274 V
+Ringback Voltage on Rise at FPGA Pin : 0.141 V
+Ringback Voltage on Fall at FPGA Pin : 0.006 V
+10-90 Rise Time at FPGA Pin          : 4.7e-10 s
+90-10 Fall Time at FPGA Pin          : 6.02e-10 s
+Monotonic Rise at FPGA Pin           : Yes
+Monotonic Fall at FPGA Pin           : Yes
+Steady State Voh at Far-end          : 2.32 V
+Steady State Vol at Far-end          : 5.61e-09 V
+Voh Max at Far-end                   : 2.38 V
+Vol Min at Far-end                   : -0.00274 V
+Ringback Voltage on Rise at Far-end  : 0.141 V
+Ringback Voltage on Fall at Far-end  : 0.006 V
+10-90 Rise Time at Far-end           : 4.7e-10 s
+90-10 Fall Time at Far-end           : 6.02e-10 s
+Monotonic Rise at Far-end            : Yes
+Monotonic Fall at Far-end            : Yes
++--------------------------------------------------------------------------------+
+
+
+
++--------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1200mv 85c Model)                               ;
++--------------------------------------------------------------------------------+
+Pin                                  : LED[0]
+I/O Standard                         : 3.3-V LVTTL
+Board Delay on Rise                  : 0 s
+Board Delay on Fall                  : 0 s
+Steady State Voh at FPGA Pin         : 3.08 V
+Steady State Vol at FPGA Pin         : 2.99e-06 V
+Voh Max at FPGA Pin                  : 3.11 V
+Vol Min at FPGA Pin                  : -0.0717 V
+Ringback Voltage on Rise at FPGA Pin : 0.209 V
+Ringback Voltage on Fall at FPGA Pin : 0.168 V
+10-90 Rise Time at FPGA Pin          : 6.66e-10 s
+90-10 Fall Time at FPGA Pin          : 6.19e-10 s
+Monotonic Rise at FPGA Pin           : Yes
+Monotonic Fall at FPGA Pin           : No
+Steady State Voh at Far-end          : 3.08 V
+Steady State Vol at Far-end          : 2.99e-06 V
+Voh Max at Far-end                   : 3.11 V
+Vol Min at Far-end                   : -0.0717 V
+Ringback Voltage on Rise at Far-end  : 0.209 V
+Ringback Voltage on Fall at Far-end  : 0.168 V
+10-90 Rise Time at Far-end           : 6.66e-10 s
+90-10 Fall Time at Far-end           : 6.19e-10 s
+Monotonic Rise at Far-end            : Yes
+Monotonic Fall at Far-end            : No
+
+Pin                                  : LED[1]
+I/O Standard                         : 3.3-V LVTTL
+Board Delay on Rise                  : 0 s
+Board Delay on Fall                  : 0 s
+Steady State Voh at FPGA Pin         : 3.08 V
+Steady State Vol at FPGA Pin         : 2.99e-06 V
+Voh Max at FPGA Pin                  : 3.11 V
+Vol Min at FPGA Pin                  : -0.0717 V
+Ringback Voltage on Rise at FPGA Pin : 0.209 V
+Ringback Voltage on Fall at FPGA Pin : 0.168 V
+10-90 Rise Time at FPGA Pin          : 6.66e-10 s
+90-10 Fall Time at FPGA Pin          : 6.19e-10 s
+Monotonic Rise at FPGA Pin           : Yes
+Monotonic Fall at FPGA Pin           : No
+Steady State Voh at Far-end          : 3.08 V
+Steady State Vol at Far-end          : 2.99e-06 V
+Voh Max at Far-end                   : 3.11 V
+Vol Min at Far-end                   : -0.0717 V
+Ringback Voltage on Rise at Far-end  : 0.209 V
+Ringback Voltage on Fall at Far-end  : 0.168 V
+10-90 Rise Time at Far-end           : 6.66e-10 s
+90-10 Fall Time at Far-end           : 6.19e-10 s
+Monotonic Rise at Far-end            : Yes
+Monotonic Fall at Far-end            : No
+
+Pin                                  : LED[2]
+I/O Standard                         : 3.3-V LVTTL
+Board Delay on Rise                  : 0 s
+Board Delay on Fall                  : 0 s
+Steady State Voh at FPGA Pin         : 3.08 V
+Steady State Vol at FPGA Pin         : 2.99e-06 V
+Voh Max at FPGA Pin                  : 3.11 V
+Vol Min at FPGA Pin                  : -0.0717 V
+Ringback Voltage on Rise at FPGA Pin : 0.209 V
+Ringback Voltage on Fall at FPGA Pin : 0.168 V
+10-90 Rise Time at FPGA Pin          : 6.66e-10 s
+90-10 Fall Time at FPGA Pin          : 6.19e-10 s
+Monotonic Rise at FPGA Pin           : Yes
+Monotonic Fall at FPGA Pin           : No
+Steady State Voh at Far-end          : 3.08 V
+Steady State Vol at Far-end          : 2.99e-06 V
+Voh Max at Far-end                   : 3.11 V
+Vol Min at Far-end                   : -0.0717 V
+Ringback Voltage on Rise at Far-end  : 0.209 V
+Ringback Voltage on Fall at Far-end  : 0.168 V
+10-90 Rise Time at Far-end           : 6.66e-10 s
+90-10 Fall Time at Far-end           : 6.19e-10 s
+Monotonic Rise at Far-end            : Yes
+Monotonic Fall at Far-end            : No
+
+Pin                                  : LED[3]
+I/O Standard                         : 3.3-V LVTTL
+Board Delay on Rise                  : 0 s
+Board Delay on Fall                  : 0 s
+Steady State Voh at FPGA Pin         : 3.08 V
+Steady State Vol at FPGA Pin         : 2.99e-06 V
+Voh Max at FPGA Pin                  : 3.11 V
+Vol Min at FPGA Pin                  : -0.0717 V
+Ringback Voltage on Rise at FPGA Pin : 0.209 V
+Ringback Voltage on Fall at FPGA Pin : 0.168 V
+10-90 Rise Time at FPGA Pin          : 6.66e-10 s
+90-10 Fall Time at FPGA Pin          : 6.19e-10 s
+Monotonic Rise at FPGA Pin           : Yes
+Monotonic Fall at FPGA Pin           : No
+Steady State Voh at Far-end          : 3.08 V
+Steady State Vol at Far-end          : 2.99e-06 V
+Voh Max at Far-end                   : 3.11 V
+Vol Min at Far-end                   : -0.0717 V
+Ringback Voltage on Rise at Far-end  : 0.209 V
+Ringback Voltage on Fall at Far-end  : 0.168 V
+10-90 Rise Time at Far-end           : 6.66e-10 s
+90-10 Fall Time at Far-end           : 6.19e-10 s
+Monotonic Rise at Far-end            : Yes
+Monotonic Fall at Far-end            : No
+
+Pin                                  : LED[4]
+I/O Standard                         : 3.3-V LVTTL
+Board Delay on Rise                  : 0 s
+Board Delay on Fall                  : 0 s
+Steady State Voh at FPGA Pin         : 3.08 V
+Steady State Vol at FPGA Pin         : 2e-06 V
+Voh Max at FPGA Pin                  : 3.12 V
+Vol Min at FPGA Pin                  : -0.0547 V
+Ringback Voltage on Rise at FPGA Pin : 0.276 V
+Ringback Voltage on Fall at FPGA Pin : 0.181 V
+10-90 Rise Time at FPGA Pin          : 9.17e-10 s
+90-10 Fall Time at FPGA Pin          : 8.31e-10 s
+Monotonic Rise at FPGA Pin           : Yes
+Monotonic Fall at FPGA Pin           : No
+Steady State Voh at Far-end          : 3.08 V
+Steady State Vol at Far-end          : 2e-06 V
+Voh Max at Far-end                   : 3.12 V
+Vol Min at Far-end                   : -0.0547 V
+Ringback Voltage on Rise at Far-end  : 0.276 V
+Ringback Voltage on Fall at Far-end  : 0.181 V
+10-90 Rise Time at Far-end           : 9.17e-10 s
+90-10 Fall Time at Far-end           : 8.31e-10 s
+Monotonic Rise at Far-end            : Yes
+Monotonic Fall at Far-end            : No
+
+Pin                                  : LED[5]
+I/O Standard                         : 3.3-V LVTTL
+Board Delay on Rise                  : 0 s
+Board Delay on Fall                  : 0 s
+Steady State Voh at FPGA Pin         : 3.08 V
+Steady State Vol at FPGA Pin         : 2e-06 V
+Voh Max at FPGA Pin                  : 3.08 V
+Vol Min at FPGA Pin                  : -0.00666 V
+Ringback Voltage on Rise at FPGA Pin : 0.298 V
+Ringback Voltage on Fall at FPGA Pin : 0.277 V
+10-90 Rise Time at FPGA Pin          : 5.29e-09 s
+90-10 Fall Time at FPGA Pin          : 4.2e-09 s
+Monotonic Rise at FPGA Pin           : Yes
+Monotonic Fall at FPGA Pin           : No
+Steady State Voh at Far-end          : 3.08 V
+Steady State Vol at Far-end          : 2e-06 V
+Voh Max at Far-end                   : 3.08 V
+Vol Min at Far-end                   : -0.00666 V
+Ringback Voltage on Rise at Far-end  : 0.298 V
+Ringback Voltage on Fall at Far-end  : 0.277 V
+10-90 Rise Time at Far-end           : 5.29e-09 s
+90-10 Fall Time at Far-end           : 4.2e-09 s
+Monotonic Rise at Far-end            : Yes
+Monotonic Fall at Far-end            : No
+
+Pin                                  : LED[6]
+I/O Standard                         : 3.3-V LVTTL
+Board Delay on Rise                  : 0 s
+Board Delay on Fall                  : 0 s
+Steady State Voh at FPGA Pin         : 3.08 V
+Steady State Vol at FPGA Pin         : 2e-06 V
+Voh Max at FPGA Pin                  : 3.13 V
+Vol Min at FPGA Pin                  : -0.0781 V
+Ringback Voltage on Rise at FPGA Pin : 0.202 V
+Ringback Voltage on Fall at FPGA Pin : 0.359 V
+10-90 Rise Time at FPGA Pin          : 6.54e-10 s
+90-10 Fall Time at FPGA Pin          : 5e-10 s
+Monotonic Rise at FPGA Pin           : No
+Monotonic Fall at FPGA Pin           : No
+Steady State Voh at Far-end          : 3.08 V
+Steady State Vol at Far-end          : 2e-06 V
+Voh Max at Far-end                   : 3.13 V
+Vol Min at Far-end                   : -0.0781 V
+Ringback Voltage on Rise at Far-end  : 0.202 V
+Ringback Voltage on Fall at Far-end  : 0.359 V
+10-90 Rise Time at Far-end           : 6.54e-10 s
+90-10 Fall Time at Far-end           : 5e-10 s
+Monotonic Rise at Far-end            : No
+Monotonic Fall at Far-end            : No
+
+Pin                                  : LED[7]
+I/O Standard                         : 3.3-V LVTTL
+Board Delay on Rise                  : 0 s
+Board Delay on Fall                  : 0 s
+Steady State Voh at FPGA Pin         : 3.08 V
+Steady State Vol at FPGA Pin         : 2e-06 V
+Voh Max at FPGA Pin                  : 3.08 V
+Vol Min at FPGA Pin                  : -0.00666 V
+Ringback Voltage on Rise at FPGA Pin : 0.298 V
+Ringback Voltage on Fall at FPGA Pin : 0.277 V
+10-90 Rise Time at FPGA Pin          : 5.29e-09 s
+90-10 Fall Time at FPGA Pin          : 4.2e-09 s
+Monotonic Rise at FPGA Pin           : Yes
+Monotonic Fall at FPGA Pin           : No
+Steady State Voh at Far-end          : 3.08 V
+Steady State Vol at Far-end          : 2e-06 V
+Voh Max at Far-end                   : 3.08 V
+Vol Min at Far-end                   : -0.00666 V
+Ringback Voltage on Rise at Far-end  : 0.298 V
+Ringback Voltage on Fall at Far-end  : 0.277 V
+10-90 Rise Time at Far-end           : 5.29e-09 s
+90-10 Fall Time at Far-end           : 4.2e-09 s
+Monotonic Rise at Far-end            : Yes
+Monotonic Fall at Far-end            : No
+
+Pin                                  : ~ALTERA_DCLK~
+I/O Standard                         : 3.3-V LVTTL
+Board Delay on Rise                  : 0 s
+Board Delay on Fall                  : 0 s
+Steady State Voh at FPGA Pin         : 3.08 V
+Steady State Vol at FPGA Pin         : 1.02e-06 V
+Voh Max at FPGA Pin                  : 3.14 V
+Vol Min at FPGA Pin                  : -0.124 V
+Ringback Voltage on Rise at FPGA Pin : 0.134 V
+Ringback Voltage on Fall at FPGA Pin : 0.323 V
+10-90 Rise Time at FPGA Pin          : 3.02e-10 s
+90-10 Fall Time at FPGA Pin          : 2.85e-10 s
+Monotonic Rise at FPGA Pin           : Yes
+Monotonic Fall at FPGA Pin           : No
+Steady State Voh at Far-end          : 3.08 V
+Steady State Vol at Far-end          : 1.02e-06 V
+Voh Max at Far-end                   : 3.14 V
+Vol Min at Far-end                   : -0.124 V
+Ringback Voltage on Rise at Far-end  : 0.134 V
+Ringback Voltage on Fall at Far-end  : 0.323 V
+10-90 Rise Time at Far-end           : 3.02e-10 s
+90-10 Fall Time at Far-end           : 2.85e-10 s
+Monotonic Rise at Far-end            : Yes
+Monotonic Fall at Far-end            : No
+
+Pin                                  : ~ALTERA_nCEO~
+I/O Standard                         : 2.5 V
+Board Delay on Rise                  : 0 s
+Board Delay on Fall                  : 0 s
+Steady State Voh at FPGA Pin         : 2.32 V
+Steady State Vol at FPGA Pin         : 9.45e-07 V
+Voh Max at FPGA Pin                  : 2.35 V
+Vol Min at FPGA Pin                  : -0.00643 V
+Ringback Voltage on Rise at FPGA Pin : 0.081 V
+Ringback Voltage on Fall at FPGA Pin : 0.031 V
+10-90 Rise Time at FPGA Pin          : 5.31e-10 s
+90-10 Fall Time at FPGA Pin          : 7.59e-10 s
+Monotonic Rise at FPGA Pin           : Yes
+Monotonic Fall at FPGA Pin           : Yes
+Steady State Voh at Far-end          : 2.32 V
+Steady State Vol at Far-end          : 9.45e-07 V
+Voh Max at Far-end                   : 2.35 V
+Vol Min at Far-end                   : -0.00643 V
+Ringback Voltage on Rise at Far-end  : 0.081 V
+Ringback Voltage on Fall at Far-end  : 0.031 V
+10-90 Rise Time at Far-end           : 5.31e-10 s
+90-10 Fall Time at Far-end           : 7.59e-10 s
+Monotonic Rise at Far-end            : Yes
+Monotonic Fall at Far-end            : Yes
++--------------------------------------------------------------------------------+
+
+
+
++--------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1200mv 0c Model)                                ;
++--------------------------------------------------------------------------------+
+Pin                                  : LED[0]
+I/O Standard                         : 3.3-V LVTTL
+Board Delay on Rise                  : 0 s
+Board Delay on Fall                  : 0 s
+Steady State Voh at FPGA Pin         : 3.46 V
+Steady State Vol at FPGA Pin         : 1.85e-07 V
+Voh Max at FPGA Pin                  : 3.57 V
+Vol Min at FPGA Pin                  : -0.141 V
+Ringback Voltage on Rise at FPGA Pin : 0.301 V
+Ringback Voltage on Fall at FPGA Pin : 0.239 V
+10-90 Rise Time at FPGA Pin          : 4.61e-10 s
+90-10 Fall Time at FPGA Pin          : 4.2e-10 s
+Monotonic Rise at FPGA Pin           : No
+Monotonic Fall at FPGA Pin           : No
+Steady State Voh at Far-end          : 3.46 V
+Steady State Vol at Far-end          : 1.85e-07 V
+Voh Max at Far-end                   : 3.57 V
+Vol Min at Far-end                   : -0.141 V
+Ringback Voltage on Rise at Far-end  : 0.301 V
+Ringback Voltage on Fall at Far-end  : 0.239 V
+10-90 Rise Time at Far-end           : 4.61e-10 s
+90-10 Fall Time at Far-end           : 4.2e-10 s
+Monotonic Rise at Far-end            : No
+Monotonic Fall at Far-end            : No
+
+Pin                                  : LED[1]
+I/O Standard                         : 3.3-V LVTTL
+Board Delay on Rise                  : 0 s
+Board Delay on Fall                  : 0 s
+Steady State Voh at FPGA Pin         : 3.46 V
+Steady State Vol at FPGA Pin         : 1.85e-07 V
+Voh Max at FPGA Pin                  : 3.57 V
+Vol Min at FPGA Pin                  : -0.141 V
+Ringback Voltage on Rise at FPGA Pin : 0.301 V
+Ringback Voltage on Fall at FPGA Pin : 0.239 V
+10-90 Rise Time at FPGA Pin          : 4.61e-10 s
+90-10 Fall Time at FPGA Pin          : 4.2e-10 s
+Monotonic Rise at FPGA Pin           : No
+Monotonic Fall at FPGA Pin           : No
+Steady State Voh at Far-end          : 3.46 V
+Steady State Vol at Far-end          : 1.85e-07 V
+Voh Max at Far-end                   : 3.57 V
+Vol Min at Far-end                   : -0.141 V
+Ringback Voltage on Rise at Far-end  : 0.301 V
+Ringback Voltage on Fall at Far-end  : 0.239 V
+10-90 Rise Time at Far-end           : 4.61e-10 s
+90-10 Fall Time at Far-end           : 4.2e-10 s
+Monotonic Rise at Far-end            : No
+Monotonic Fall at Far-end            : No
+
+Pin                                  : LED[2]
+I/O Standard                         : 3.3-V LVTTL
+Board Delay on Rise                  : 0 s
+Board Delay on Fall                  : 0 s
+Steady State Voh at FPGA Pin         : 3.46 V
+Steady State Vol at FPGA Pin         : 1.85e-07 V
+Voh Max at FPGA Pin                  : 3.57 V
+Vol Min at FPGA Pin                  : -0.141 V
+Ringback Voltage on Rise at FPGA Pin : 0.301 V
+Ringback Voltage on Fall at FPGA Pin : 0.239 V
+10-90 Rise Time at FPGA Pin          : 4.61e-10 s
+90-10 Fall Time at FPGA Pin          : 4.2e-10 s
+Monotonic Rise at FPGA Pin           : No
+Monotonic Fall at FPGA Pin           : No
+Steady State Voh at Far-end          : 3.46 V
+Steady State Vol at Far-end          : 1.85e-07 V
+Voh Max at Far-end                   : 3.57 V
+Vol Min at Far-end                   : -0.141 V
+Ringback Voltage on Rise at Far-end  : 0.301 V
+Ringback Voltage on Fall at Far-end  : 0.239 V
+10-90 Rise Time at Far-end           : 4.61e-10 s
+90-10 Fall Time at Far-end           : 4.2e-10 s
+Monotonic Rise at Far-end            : No
+Monotonic Fall at Far-end            : No
+
+Pin                                  : LED[3]
+I/O Standard                         : 3.3-V LVTTL
+Board Delay on Rise                  : 0 s
+Board Delay on Fall                  : 0 s
+Steady State Voh at FPGA Pin         : 3.46 V
+Steady State Vol at FPGA Pin         : 1.85e-07 V
+Voh Max at FPGA Pin                  : 3.57 V
+Vol Min at FPGA Pin                  : -0.141 V
+Ringback Voltage on Rise at FPGA Pin : 0.301 V
+Ringback Voltage on Fall at FPGA Pin : 0.239 V
+10-90 Rise Time at FPGA Pin          : 4.61e-10 s
+90-10 Fall Time at FPGA Pin          : 4.2e-10 s
+Monotonic Rise at FPGA Pin           : No
+Monotonic Fall at FPGA Pin           : No
+Steady State Voh at Far-end          : 3.46 V
+Steady State Vol at Far-end          : 1.85e-07 V
+Voh Max at Far-end                   : 3.57 V
+Vol Min at Far-end                   : -0.141 V
+Ringback Voltage on Rise at Far-end  : 0.301 V
+Ringback Voltage on Fall at Far-end  : 0.239 V
+10-90 Rise Time at Far-end           : 4.61e-10 s
+90-10 Fall Time at Far-end           : 4.2e-10 s
+Monotonic Rise at Far-end            : No
+Monotonic Fall at Far-end            : No
+
+Pin                                  : LED[4]
+I/O Standard                         : 3.3-V LVTTL
+Board Delay on Rise                  : 0 s
+Board Delay on Fall                  : 0 s
+Steady State Voh at FPGA Pin         : 3.46 V
+Steady State Vol at FPGA Pin         : 1.25e-07 V
+Voh Max at FPGA Pin                  : 3.57 V
+Vol Min at FPGA Pin                  : -0.0855 V
+Ringback Voltage on Rise at FPGA Pin : 0.315 V
+Ringback Voltage on Fall at FPGA Pin : 0.175 V
+10-90 Rise Time at FPGA Pin          : 6.79e-10 s
+90-10 Fall Time at FPGA Pin          : 6.15e-10 s
+Monotonic Rise at FPGA Pin           : No
+Monotonic Fall at FPGA Pin           : No
+Steady State Voh at Far-end          : 3.46 V
+Steady State Vol at Far-end          : 1.25e-07 V
+Voh Max at Far-end                   : 3.57 V
+Vol Min at Far-end                   : -0.0855 V
+Ringback Voltage on Rise at Far-end  : 0.315 V
+Ringback Voltage on Fall at Far-end  : 0.175 V
+10-90 Rise Time at Far-end           : 6.79e-10 s
+90-10 Fall Time at Far-end           : 6.15e-10 s
+Monotonic Rise at Far-end            : No
+Monotonic Fall at Far-end            : No
+
+Pin                                  : LED[5]
+I/O Standard                         : 3.3-V LVTTL
+Board Delay on Rise                  : 0 s
+Board Delay on Fall                  : 0 s
+Steady State Voh at FPGA Pin         : 3.46 V
+Steady State Vol at FPGA Pin         : 1.25e-07 V
+Voh Max at FPGA Pin                  : 3.48 V
+Vol Min at FPGA Pin                  : -0.0162 V
+Ringback Voltage on Rise at FPGA Pin : 0.354 V
+Ringback Voltage on Fall at FPGA Pin : 0.317 V
+10-90 Rise Time at FPGA Pin          : 3.88e-09 s
+90-10 Fall Time at FPGA Pin          : 3.06e-09 s
+Monotonic Rise at FPGA Pin           : No
+Monotonic Fall at FPGA Pin           : No
+Steady State Voh at Far-end          : 3.46 V
+Steady State Vol at Far-end          : 1.25e-07 V
+Voh Max at Far-end                   : 3.48 V
+Vol Min at Far-end                   : -0.0162 V
+Ringback Voltage on Rise at Far-end  : 0.354 V
+Ringback Voltage on Fall at Far-end  : 0.317 V
+10-90 Rise Time at Far-end           : 3.88e-09 s
+90-10 Fall Time at Far-end           : 3.06e-09 s
+Monotonic Rise at Far-end            : No
+Monotonic Fall at Far-end            : No
+
+Pin                                  : LED[6]
+I/O Standard                         : 3.3-V LVTTL
+Board Delay on Rise                  : 0 s
+Board Delay on Fall                  : 0 s
+Steady State Voh at FPGA Pin         : 3.46 V
+Steady State Vol at FPGA Pin         : 1.25e-07 V
+Voh Max at FPGA Pin                  : 3.6 V
+Vol Min at FPGA Pin                  : -0.127 V
+Ringback Voltage on Rise at FPGA Pin : 0.302 V
+Ringback Voltage on Fall at FPGA Pin : 0.21 V
+10-90 Rise Time at FPGA Pin          : 4.55e-10 s
+90-10 Fall Time at FPGA Pin          : 4.11e-10 s
+Monotonic Rise at FPGA Pin           : No
+Monotonic Fall at FPGA Pin           : No
+Steady State Voh at Far-end          : 3.46 V
+Steady State Vol at Far-end          : 1.25e-07 V
+Voh Max at Far-end                   : 3.6 V
+Vol Min at Far-end                   : -0.127 V
+Ringback Voltage on Rise at Far-end  : 0.302 V
+Ringback Voltage on Fall at Far-end  : 0.21 V
+10-90 Rise Time at Far-end           : 4.55e-10 s
+90-10 Fall Time at Far-end           : 4.11e-10 s
+Monotonic Rise at Far-end            : No
+Monotonic Fall at Far-end            : No
+
+Pin                                  : LED[7]
+I/O Standard                         : 3.3-V LVTTL
+Board Delay on Rise                  : 0 s
+Board Delay on Fall                  : 0 s
+Steady State Voh at FPGA Pin         : 3.46 V
+Steady State Vol at FPGA Pin         : 1.25e-07 V
+Voh Max at FPGA Pin                  : 3.48 V
+Vol Min at FPGA Pin                  : -0.0162 V
+Ringback Voltage on Rise at FPGA Pin : 0.354 V
+Ringback Voltage on Fall at FPGA Pin : 0.317 V
+10-90 Rise Time at FPGA Pin          : 3.88e-09 s
+90-10 Fall Time at FPGA Pin          : 3.06e-09 s
+Monotonic Rise at FPGA Pin           : No
+Monotonic Fall at FPGA Pin           : No
+Steady State Voh at Far-end          : 3.46 V
+Steady State Vol at Far-end          : 1.25e-07 V
+Voh Max at Far-end                   : 3.48 V
+Vol Min at Far-end                   : -0.0162 V
+Ringback Voltage on Rise at Far-end  : 0.354 V
+Ringback Voltage on Fall at Far-end  : 0.317 V
+10-90 Rise Time at Far-end           : 3.88e-09 s
+90-10 Fall Time at Far-end           : 3.06e-09 s
+Monotonic Rise at Far-end            : No
+Monotonic Fall at Far-end            : No
+
+Pin                                  : ~ALTERA_DCLK~
+I/O Standard                         : 3.3-V LVTTL
+Board Delay on Rise                  : 0 s
+Board Delay on Fall                  : 0 s
+Steady State Voh at FPGA Pin         : 3.46 V
+Steady State Vol at FPGA Pin         : 6.54e-08 V
+Voh Max at FPGA Pin                  : 3.66 V
+Vol Min at FPGA Pin                  : -0.258 V
+Ringback Voltage on Rise at FPGA Pin : 0.41 V
+Ringback Voltage on Fall at FPGA Pin : 0.318 V
+10-90 Rise Time at FPGA Pin          : 1.57e-10 s
+90-10 Fall Time at FPGA Pin          : 2.15e-10 s
+Monotonic Rise at FPGA Pin           : No
+Monotonic Fall at FPGA Pin           : Yes
+Steady State Voh at Far-end          : 3.46 V
+Steady State Vol at Far-end          : 6.54e-08 V
+Voh Max at Far-end                   : 3.66 V
+Vol Min at Far-end                   : -0.258 V
+Ringback Voltage on Rise at Far-end  : 0.41 V
+Ringback Voltage on Fall at Far-end  : 0.318 V
+10-90 Rise Time at Far-end           : 1.57e-10 s
+90-10 Fall Time at Far-end           : 2.15e-10 s
+Monotonic Rise at Far-end            : No
+Monotonic Fall at Far-end            : Yes
+
+Pin                                  : ~ALTERA_nCEO~
+I/O Standard                         : 2.5 V
+Board Delay on Rise                  : 0 s
+Board Delay on Fall                  : 0 s
+Steady State Voh at FPGA Pin         : 2.62 V
+Steady State Vol at FPGA Pin         : 3.54e-08 V
+Voh Max at FPGA Pin                  : 2.7 V
+Vol Min at FPGA Pin                  : -0.00943 V
+Ringback Voltage on Rise at FPGA Pin : 0.276 V
+Ringback Voltage on Fall at FPGA Pin : 0.035 V
+10-90 Rise Time at FPGA Pin          : 3.19e-10 s
+90-10 Fall Time at FPGA Pin          : 4.99e-10 s
+Monotonic Rise at FPGA Pin           : No
+Monotonic Fall at FPGA Pin           : Yes
+Steady State Voh at Far-end          : 2.62 V
+Steady State Vol at Far-end          : 3.54e-08 V
+Voh Max at Far-end                   : 2.7 V
+Vol Min at Far-end                   : -0.00943 V
+Ringback Voltage on Rise at Far-end  : 0.276 V
+Ringback Voltage on Fall at Far-end  : 0.035 V
+10-90 Rise Time at Far-end           : 3.19e-10 s
+90-10 Fall Time at Far-end           : 4.99e-10 s
+Monotonic Rise at Far-end            : No
+Monotonic Fall at Far-end            : Yes
++--------------------------------------------------------------------------------+
+
+
+
++--------------------------------------------------------------------------------+
+; Setup Transfers                                                                ;
++--------------------------------------------------------------------------------+
+From Clock : CLOCK_50
+To Clock   : CLOCK_50
+RR Paths   : 413
+FR Paths   : 0
+RF Paths   : 0
+FF Paths   : 0
++--------------------------------------------------------------------------------+
+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++--------------------------------------------------------------------------------+
+; Hold Transfers                                                                 ;
++--------------------------------------------------------------------------------+
+From Clock : CLOCK_50
+To Clock   : CLOCK_50
+RR Paths   : 413
+FR Paths   : 0
+RF Paths   : 0
+FF Paths   : 0
++--------------------------------------------------------------------------------+
+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+
+
++--------------------------------------------------------------------------------+
+; Unconstrained Paths                                                            ;
++--------------------------------------------------------------------------------+
+Property : Illegal Clocks
+Setup    : 0
+Hold     : 0
+
+Property : Unconstrained Clocks
+Setup    : 0
+Hold     : 0
+
+Property : Unconstrained Input Ports
+Setup    : 0
+Hold     : 0
+
+Property : Unconstrained Input Port Paths
+Setup    : 0
+Hold     : 0
+
+Property : Unconstrained Output Ports
+Setup    : 7
+Hold     : 7
+
+Property : Unconstrained Output Port Paths
+Setup    : 7
+Hold     : 7
++--------------------------------------------------------------------------------+
+
+
+
++------------------------------------+
+; TimeQuest Timing Analyzer Messages ;
++------------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+    Info: Processing started: Wed Mar 30 11:51:39 2022
+Info: Command: quartus_sta spectrum -c spectrum
+Info: qsta_default_script.tcl version: #1
+Warning (20028): Parallel compilation is not licensed and has been disabled
+Info (21077): Core supply voltage is 1.2V
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332105): Deriving Clocks
+    Info (332105): create_clock -period 1.000 -name CLOCK_50 CLOCK_50
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info: Analyzing Slow 1200mV 85C Model
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -1.606
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -1.606             -30.234 CLOCK_50 
+Info (332146): Worst-case hold slack is 0.360
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.360               0.000 CLOCK_50 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -3.000
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -3.000             -38.000 CLOCK_50 
+Info: Analyzing Slow 1200mV 0C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -1.275
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -1.275             -22.690 CLOCK_50 
+Info (332146): Worst-case hold slack is 0.319
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.319               0.000 CLOCK_50 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -3.000
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -3.000             -38.000 CLOCK_50 
+Info: Analyzing Fast 1200mV 0C Model
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -0.500
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -0.500              -4.764 CLOCK_50 
+Info (332146): Worst-case hold slack is 0.193
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.193               0.000 CLOCK_50 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -3.000
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -3.000             -48.277 CLOCK_50 
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings
+    Info: Peak virtual memory: 412 megabytes
+    Info: Processing ended: Wed Mar 30 11:51:41 2022
+    Info: Elapsed time: 00:00:02
+    Info: Total CPU time (on all processors): 00:00:02
+
+
diff --git a/output_files/spectrum.sta.summary b/output_files/spectrum.sta.summary
new file mode 100644
index 0000000..53ba926
--- /dev/null
+++ b/output_files/spectrum.sta.summary
@@ -0,0 +1,41 @@
+------------------------------------------------------------
+TimeQuest Timing Analyzer Summary
+------------------------------------------------------------
+
+Type  : Slow 1200mV 85C Model Setup 'CLOCK_50'
+Slack : -1.606
+TNS   : -30.234
+
+Type  : Slow 1200mV 85C Model Hold 'CLOCK_50'
+Slack : 0.360
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -3.000
+TNS   : -38.000
+
+Type  : Slow 1200mV 0C Model Setup 'CLOCK_50'
+Slack : -1.275
+TNS   : -22.690
+
+Type  : Slow 1200mV 0C Model Hold 'CLOCK_50'
+Slack : 0.319
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -3.000
+TNS   : -38.000
+
+Type  : Fast 1200mV 0C Model Setup 'CLOCK_50'
+Slack : -0.500
+TNS   : -4.764
+
+Type  : Fast 1200mV 0C Model Hold 'CLOCK_50'
+Slack : 0.193
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'CLOCK_50'
+Slack : -3.000
+TNS   : -48.277
+
+------------------------------------------------------------
diff --git a/simulation/modelsim/spectrum.sft b/simulation/modelsim/spectrum.sft
new file mode 100644
index 0000000..4623861
--- /dev/null
+++ b/simulation/modelsim/spectrum.sft
@@ -0,0 +1,6 @@
+set tool_name "ModelSim-Altera (Verilog)"
+set corner_file_list {
+	{{"Slow -6 1.2V 85 Model"} {spectrum_6_1200mv_85c_slow.vo spectrum_6_1200mv_85c_v_slow.sdo}}
+	{{"Slow -6 1.2V 0 Model"} {spectrum_6_1200mv_0c_slow.vo spectrum_6_1200mv_0c_v_slow.sdo}}
+	{{"Fast -M 1.2V 0 Model"} {spectrum_min_1200mv_0c_fast.vo spectrum_min_1200mv_0c_v_fast.sdo}}
+}
diff --git a/simulation/modelsim/spectrum.vo b/simulation/modelsim/spectrum.vo
new file mode 100644
index 0000000..d287dcb
--- /dev/null
+++ b/simulation/modelsim/spectrum.vo
@@ -0,0 +1,1574 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+// VENDOR "Altera"
+// PROGRAM "Quartus II 32-bit"
+// VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+// DATE "03/30/2022 11:51:43"
+
+// 
+// Device: Altera EP4CE22F17C6 Package FBGA256
+// 
+
+// 
+// This Verilog file should be used for ModelSim-Altera (Verilog) only
+// 
+
+`timescale 1 ps/ 1 ps
+
+module spectrum (
+	CLOCK_50,
+	LED);
+input 	CLOCK_50;
+output 	[7:0] LED;
+
+// Design Ports Information
+// LED[0]	=>  Location: PIN_A15,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LED[1]	=>  Location: PIN_A13,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LED[2]	=>  Location: PIN_B13,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LED[3]	=>  Location: PIN_A11,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LED[4]	=>  Location: PIN_D1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LED[5]	=>  Location: PIN_F3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LED[6]	=>  Location: PIN_B1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LED[7]	=>  Location: PIN_L3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// CLOCK_50	=>  Location: PIN_R8,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+
+
+wire gnd;
+wire vcc;
+wire unknown;
+
+assign gnd = 1'b0;
+assign vcc = 1'b1;
+assign unknown = 1'bx;
+
+tri1 devclrn;
+tri1 devpor;
+tri1 devoe;
+// synopsys translate_off
+initial $sdf_annotate("spectrum_v.sdo");
+// synopsys translate_on
+
+wire \LED[0]~output_o ;
+wire \LED[1]~output_o ;
+wire \LED[2]~output_o ;
+wire \LED[3]~output_o ;
+wire \LED[4]~output_o ;
+wire \LED[5]~output_o ;
+wire \LED[6]~output_o ;
+wire \LED[7]~output_o ;
+wire \CLOCK_50~input_o ;
+wire \CLOCK_50~inputclkctrl_outclk ;
+wire \counter[0]~81_combout ;
+wire \counter[1]~27_combout ;
+wire \counter[1]~28 ;
+wire \counter[2]~29_combout ;
+wire \counter[2]~30 ;
+wire \counter[3]~31_combout ;
+wire \counter[3]~32 ;
+wire \counter[4]~33_combout ;
+wire \counter[4]~34 ;
+wire \counter[5]~35_combout ;
+wire \counter[5]~36 ;
+wire \counter[6]~37_combout ;
+wire \counter[6]~38 ;
+wire \counter[7]~39_combout ;
+wire \counter[7]~40 ;
+wire \counter[8]~41_combout ;
+wire \counter[8]~42 ;
+wire \counter[9]~43_combout ;
+wire \counter[9]~44 ;
+wire \counter[10]~45_combout ;
+wire \counter[10]~46 ;
+wire \counter[11]~47_combout ;
+wire \counter[11]~48 ;
+wire \counter[12]~49_combout ;
+wire \counter[12]~50 ;
+wire \counter[13]~51_combout ;
+wire \counter[13]~52 ;
+wire \counter[14]~53_combout ;
+wire \counter[14]~54 ;
+wire \counter[15]~55_combout ;
+wire \counter[15]~56 ;
+wire \counter[16]~57_combout ;
+wire \counter[16]~58 ;
+wire \counter[17]~59_combout ;
+wire \counter[17]~60 ;
+wire \counter[18]~61_combout ;
+wire \counter[18]~62 ;
+wire \counter[19]~63_combout ;
+wire \counter[19]~64 ;
+wire \counter[20]~65_combout ;
+wire \counter[20]~66 ;
+wire \counter[21]~67_combout ;
+wire \LED[0]~reg0feeder_combout ;
+wire \LED[0]~reg0_q ;
+wire \counter[21]~68 ;
+wire \counter[22]~69_combout ;
+wire \LED[1]~reg0feeder_combout ;
+wire \LED[1]~reg0_q ;
+wire \counter[22]~70 ;
+wire \counter[23]~71_combout ;
+wire \LED[2]~reg0feeder_combout ;
+wire \LED[2]~reg0_q ;
+wire \counter[23]~72 ;
+wire \counter[24]~73_combout ;
+wire \LED[3]~reg0feeder_combout ;
+wire \LED[3]~reg0_q ;
+wire \counter[24]~74 ;
+wire \counter[25]~75_combout ;
+wire \LED[4]~reg0feeder_combout ;
+wire \LED[4]~reg0_q ;
+wire \counter[25]~76 ;
+wire \counter[26]~77_combout ;
+wire \LED[5]~reg0feeder_combout ;
+wire \LED[5]~reg0_q ;
+wire \counter[26]~78 ;
+wire \counter[27]~79_combout ;
+wire \LED[6]~reg0feeder_combout ;
+wire \LED[6]~reg0_q ;
+wire [27:0] counter;
+
+
+// Location: IOOBUF_X38_Y34_N16
+cycloneive_io_obuf \LED[0]~output (
+	.i(\LED[0]~reg0_q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LED[0]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LED[0]~output .bus_hold = "false";
+defparam \LED[0]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X49_Y34_N2
+cycloneive_io_obuf \LED[1]~output (
+	.i(\LED[1]~reg0_q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LED[1]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LED[1]~output .bus_hold = "false";
+defparam \LED[1]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X49_Y34_N9
+cycloneive_io_obuf \LED[2]~output (
+	.i(\LED[2]~reg0_q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LED[2]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LED[2]~output .bus_hold = "false";
+defparam \LED[2]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X40_Y34_N2
+cycloneive_io_obuf \LED[3]~output (
+	.i(\LED[3]~reg0_q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LED[3]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LED[3]~output .bus_hold = "false";
+defparam \LED[3]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y25_N9
+cycloneive_io_obuf \LED[4]~output (
+	.i(\LED[4]~reg0_q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LED[4]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LED[4]~output .bus_hold = "false";
+defparam \LED[4]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y26_N16
+cycloneive_io_obuf \LED[5]~output (
+	.i(\LED[5]~reg0_q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LED[5]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LED[5]~output .bus_hold = "false";
+defparam \LED[5]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y28_N9
+cycloneive_io_obuf \LED[6]~output (
+	.i(\LED[6]~reg0_q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LED[6]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LED[6]~output .bus_hold = "false";
+defparam \LED[6]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y10_N23
+cycloneive_io_obuf \LED[7]~output (
+	.i(gnd),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LED[7]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LED[7]~output .bus_hold = "false";
+defparam \LED[7]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOIBUF_X27_Y0_N22
+cycloneive_io_ibuf \CLOCK_50~input (
+	.i(CLOCK_50),
+	.ibar(gnd),
+	.o(\CLOCK_50~input_o ));
+// synopsys translate_off
+defparam \CLOCK_50~input .bus_hold = "false";
+defparam \CLOCK_50~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: CLKCTRL_G18
+cycloneive_clkctrl \CLOCK_50~inputclkctrl (
+	.ena(vcc),
+	.inclk({vcc,vcc,vcc,\CLOCK_50~input_o }),
+	.clkselect(2'b00),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.outclk(\CLOCK_50~inputclkctrl_outclk ));
+// synopsys translate_off
+defparam \CLOCK_50~inputclkctrl .clock_type = "global clock";
+defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N4
+cycloneive_lcell_comb \counter[0]~81 (
+// Equation(s):
+// \counter[0]~81_combout  = !counter[0]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(counter[0]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\counter[0]~81_combout ),
+	.cout());
+// synopsys translate_off
+defparam \counter[0]~81 .lut_mask = 16'h0F0F;
+defparam \counter[0]~81 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N5
+dffeas \counter[0] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[0]~81_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[0] .is_wysiwyg = "true";
+defparam \counter[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N6
+cycloneive_lcell_comb \counter[1]~27 (
+// Equation(s):
+// \counter[1]~27_combout  = (counter[1] & (counter[0] $ (VCC))) # (!counter[1] & (counter[0] & VCC))
+// \counter[1]~28  = CARRY((counter[1] & counter[0]))
+
+	.dataa(counter[1]),
+	.datab(counter[0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\counter[1]~27_combout ),
+	.cout(\counter[1]~28 ));
+// synopsys translate_off
+defparam \counter[1]~27 .lut_mask = 16'h6688;
+defparam \counter[1]~27 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N7
+dffeas \counter[1] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[1]~27_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[1] .is_wysiwyg = "true";
+defparam \counter[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N8
+cycloneive_lcell_comb \counter[2]~29 (
+// Equation(s):
+// \counter[2]~29_combout  = (counter[2] & (!\counter[1]~28 )) # (!counter[2] & ((\counter[1]~28 ) # (GND)))
+// \counter[2]~30  = CARRY((!\counter[1]~28 ) # (!counter[2]))
+
+	.dataa(gnd),
+	.datab(counter[2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[1]~28 ),
+	.combout(\counter[2]~29_combout ),
+	.cout(\counter[2]~30 ));
+// synopsys translate_off
+defparam \counter[2]~29 .lut_mask = 16'h3C3F;
+defparam \counter[2]~29 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N9
+dffeas \counter[2] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[2]~29_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[2] .is_wysiwyg = "true";
+defparam \counter[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N10
+cycloneive_lcell_comb \counter[3]~31 (
+// Equation(s):
+// \counter[3]~31_combout  = (counter[3] & (\counter[2]~30  $ (GND))) # (!counter[3] & (!\counter[2]~30  & VCC))
+// \counter[3]~32  = CARRY((counter[3] & !\counter[2]~30 ))
+
+	.dataa(counter[3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[2]~30 ),
+	.combout(\counter[3]~31_combout ),
+	.cout(\counter[3]~32 ));
+// synopsys translate_off
+defparam \counter[3]~31 .lut_mask = 16'hA50A;
+defparam \counter[3]~31 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N11
+dffeas \counter[3] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[3]~31_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[3] .is_wysiwyg = "true";
+defparam \counter[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N12
+cycloneive_lcell_comb \counter[4]~33 (
+// Equation(s):
+// \counter[4]~33_combout  = (counter[4] & (!\counter[3]~32 )) # (!counter[4] & ((\counter[3]~32 ) # (GND)))
+// \counter[4]~34  = CARRY((!\counter[3]~32 ) # (!counter[4]))
+
+	.dataa(counter[4]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[3]~32 ),
+	.combout(\counter[4]~33_combout ),
+	.cout(\counter[4]~34 ));
+// synopsys translate_off
+defparam \counter[4]~33 .lut_mask = 16'h5A5F;
+defparam \counter[4]~33 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N13
+dffeas \counter[4] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[4]~33_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[4] .is_wysiwyg = "true";
+defparam \counter[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N14
+cycloneive_lcell_comb \counter[5]~35 (
+// Equation(s):
+// \counter[5]~35_combout  = (counter[5] & (\counter[4]~34  $ (GND))) # (!counter[5] & (!\counter[4]~34  & VCC))
+// \counter[5]~36  = CARRY((counter[5] & !\counter[4]~34 ))
+
+	.dataa(gnd),
+	.datab(counter[5]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[4]~34 ),
+	.combout(\counter[5]~35_combout ),
+	.cout(\counter[5]~36 ));
+// synopsys translate_off
+defparam \counter[5]~35 .lut_mask = 16'hC30C;
+defparam \counter[5]~35 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N15
+dffeas \counter[5] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[5]~35_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[5] .is_wysiwyg = "true";
+defparam \counter[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N16
+cycloneive_lcell_comb \counter[6]~37 (
+// Equation(s):
+// \counter[6]~37_combout  = (counter[6] & (!\counter[5]~36 )) # (!counter[6] & ((\counter[5]~36 ) # (GND)))
+// \counter[6]~38  = CARRY((!\counter[5]~36 ) # (!counter[6]))
+
+	.dataa(gnd),
+	.datab(counter[6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[5]~36 ),
+	.combout(\counter[6]~37_combout ),
+	.cout(\counter[6]~38 ));
+// synopsys translate_off
+defparam \counter[6]~37 .lut_mask = 16'h3C3F;
+defparam \counter[6]~37 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N17
+dffeas \counter[6] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[6]~37_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[6] .is_wysiwyg = "true";
+defparam \counter[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N18
+cycloneive_lcell_comb \counter[7]~39 (
+// Equation(s):
+// \counter[7]~39_combout  = (counter[7] & (\counter[6]~38  $ (GND))) # (!counter[7] & (!\counter[6]~38  & VCC))
+// \counter[7]~40  = CARRY((counter[7] & !\counter[6]~38 ))
+
+	.dataa(gnd),
+	.datab(counter[7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[6]~38 ),
+	.combout(\counter[7]~39_combout ),
+	.cout(\counter[7]~40 ));
+// synopsys translate_off
+defparam \counter[7]~39 .lut_mask = 16'hC30C;
+defparam \counter[7]~39 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N19
+dffeas \counter[7] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[7]~39_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[7] .is_wysiwyg = "true";
+defparam \counter[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N20
+cycloneive_lcell_comb \counter[8]~41 (
+// Equation(s):
+// \counter[8]~41_combout  = (counter[8] & (!\counter[7]~40 )) # (!counter[8] & ((\counter[7]~40 ) # (GND)))
+// \counter[8]~42  = CARRY((!\counter[7]~40 ) # (!counter[8]))
+
+	.dataa(gnd),
+	.datab(counter[8]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[7]~40 ),
+	.combout(\counter[8]~41_combout ),
+	.cout(\counter[8]~42 ));
+// synopsys translate_off
+defparam \counter[8]~41 .lut_mask = 16'h3C3F;
+defparam \counter[8]~41 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N21
+dffeas \counter[8] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[8]~41_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[8] .is_wysiwyg = "true";
+defparam \counter[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N22
+cycloneive_lcell_comb \counter[9]~43 (
+// Equation(s):
+// \counter[9]~43_combout  = (counter[9] & (\counter[8]~42  $ (GND))) # (!counter[9] & (!\counter[8]~42  & VCC))
+// \counter[9]~44  = CARRY((counter[9] & !\counter[8]~42 ))
+
+	.dataa(counter[9]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[8]~42 ),
+	.combout(\counter[9]~43_combout ),
+	.cout(\counter[9]~44 ));
+// synopsys translate_off
+defparam \counter[9]~43 .lut_mask = 16'hA50A;
+defparam \counter[9]~43 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N23
+dffeas \counter[9] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[9]~43_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[9] .is_wysiwyg = "true";
+defparam \counter[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N24
+cycloneive_lcell_comb \counter[10]~45 (
+// Equation(s):
+// \counter[10]~45_combout  = (counter[10] & (!\counter[9]~44 )) # (!counter[10] & ((\counter[9]~44 ) # (GND)))
+// \counter[10]~46  = CARRY((!\counter[9]~44 ) # (!counter[10]))
+
+	.dataa(gnd),
+	.datab(counter[10]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[9]~44 ),
+	.combout(\counter[10]~45_combout ),
+	.cout(\counter[10]~46 ));
+// synopsys translate_off
+defparam \counter[10]~45 .lut_mask = 16'h3C3F;
+defparam \counter[10]~45 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N25
+dffeas \counter[10] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[10]~45_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[10] .is_wysiwyg = "true";
+defparam \counter[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N26
+cycloneive_lcell_comb \counter[11]~47 (
+// Equation(s):
+// \counter[11]~47_combout  = (counter[11] & (\counter[10]~46  $ (GND))) # (!counter[11] & (!\counter[10]~46  & VCC))
+// \counter[11]~48  = CARRY((counter[11] & !\counter[10]~46 ))
+
+	.dataa(counter[11]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[10]~46 ),
+	.combout(\counter[11]~47_combout ),
+	.cout(\counter[11]~48 ));
+// synopsys translate_off
+defparam \counter[11]~47 .lut_mask = 16'hA50A;
+defparam \counter[11]~47 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N27
+dffeas \counter[11] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[11]~47_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[11] .is_wysiwyg = "true";
+defparam \counter[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N28
+cycloneive_lcell_comb \counter[12]~49 (
+// Equation(s):
+// \counter[12]~49_combout  = (counter[12] & (!\counter[11]~48 )) # (!counter[12] & ((\counter[11]~48 ) # (GND)))
+// \counter[12]~50  = CARRY((!\counter[11]~48 ) # (!counter[12]))
+
+	.dataa(gnd),
+	.datab(counter[12]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[11]~48 ),
+	.combout(\counter[12]~49_combout ),
+	.cout(\counter[12]~50 ));
+// synopsys translate_off
+defparam \counter[12]~49 .lut_mask = 16'h3C3F;
+defparam \counter[12]~49 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N29
+dffeas \counter[12] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[12]~49_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[12] .is_wysiwyg = "true";
+defparam \counter[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N30
+cycloneive_lcell_comb \counter[13]~51 (
+// Equation(s):
+// \counter[13]~51_combout  = (counter[13] & (\counter[12]~50  $ (GND))) # (!counter[13] & (!\counter[12]~50  & VCC))
+// \counter[13]~52  = CARRY((counter[13] & !\counter[12]~50 ))
+
+	.dataa(counter[13]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[12]~50 ),
+	.combout(\counter[13]~51_combout ),
+	.cout(\counter[13]~52 ));
+// synopsys translate_off
+defparam \counter[13]~51 .lut_mask = 16'hA50A;
+defparam \counter[13]~51 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N31
+dffeas \counter[13] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[13]~51_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[13]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[13] .is_wysiwyg = "true";
+defparam \counter[13] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N0
+cycloneive_lcell_comb \counter[14]~53 (
+// Equation(s):
+// \counter[14]~53_combout  = (counter[14] & (!\counter[13]~52 )) # (!counter[14] & ((\counter[13]~52 ) # (GND)))
+// \counter[14]~54  = CARRY((!\counter[13]~52 ) # (!counter[14]))
+
+	.dataa(gnd),
+	.datab(counter[14]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[13]~52 ),
+	.combout(\counter[14]~53_combout ),
+	.cout(\counter[14]~54 ));
+// synopsys translate_off
+defparam \counter[14]~53 .lut_mask = 16'h3C3F;
+defparam \counter[14]~53 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N1
+dffeas \counter[14] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[14]~53_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[14]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[14] .is_wysiwyg = "true";
+defparam \counter[14] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N2
+cycloneive_lcell_comb \counter[15]~55 (
+// Equation(s):
+// \counter[15]~55_combout  = (counter[15] & (\counter[14]~54  $ (GND))) # (!counter[15] & (!\counter[14]~54  & VCC))
+// \counter[15]~56  = CARRY((counter[15] & !\counter[14]~54 ))
+
+	.dataa(gnd),
+	.datab(counter[15]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[14]~54 ),
+	.combout(\counter[15]~55_combout ),
+	.cout(\counter[15]~56 ));
+// synopsys translate_off
+defparam \counter[15]~55 .lut_mask = 16'hC30C;
+defparam \counter[15]~55 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N3
+dffeas \counter[15] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[15]~55_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[15]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[15] .is_wysiwyg = "true";
+defparam \counter[15] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N4
+cycloneive_lcell_comb \counter[16]~57 (
+// Equation(s):
+// \counter[16]~57_combout  = (counter[16] & (!\counter[15]~56 )) # (!counter[16] & ((\counter[15]~56 ) # (GND)))
+// \counter[16]~58  = CARRY((!\counter[15]~56 ) # (!counter[16]))
+
+	.dataa(gnd),
+	.datab(counter[16]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[15]~56 ),
+	.combout(\counter[16]~57_combout ),
+	.cout(\counter[16]~58 ));
+// synopsys translate_off
+defparam \counter[16]~57 .lut_mask = 16'h3C3F;
+defparam \counter[16]~57 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N5
+dffeas \counter[16] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[16]~57_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[16]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[16] .is_wysiwyg = "true";
+defparam \counter[16] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N6
+cycloneive_lcell_comb \counter[17]~59 (
+// Equation(s):
+// \counter[17]~59_combout  = (counter[17] & (\counter[16]~58  $ (GND))) # (!counter[17] & (!\counter[16]~58  & VCC))
+// \counter[17]~60  = CARRY((counter[17] & !\counter[16]~58 ))
+
+	.dataa(counter[17]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[16]~58 ),
+	.combout(\counter[17]~59_combout ),
+	.cout(\counter[17]~60 ));
+// synopsys translate_off
+defparam \counter[17]~59 .lut_mask = 16'hA50A;
+defparam \counter[17]~59 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N7
+dffeas \counter[17] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[17]~59_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[17]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[17] .is_wysiwyg = "true";
+defparam \counter[17] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N8
+cycloneive_lcell_comb \counter[18]~61 (
+// Equation(s):
+// \counter[18]~61_combout  = (counter[18] & (!\counter[17]~60 )) # (!counter[18] & ((\counter[17]~60 ) # (GND)))
+// \counter[18]~62  = CARRY((!\counter[17]~60 ) # (!counter[18]))
+
+	.dataa(gnd),
+	.datab(counter[18]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[17]~60 ),
+	.combout(\counter[18]~61_combout ),
+	.cout(\counter[18]~62 ));
+// synopsys translate_off
+defparam \counter[18]~61 .lut_mask = 16'h3C3F;
+defparam \counter[18]~61 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N9
+dffeas \counter[18] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[18]~61_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[18]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[18] .is_wysiwyg = "true";
+defparam \counter[18] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N10
+cycloneive_lcell_comb \counter[19]~63 (
+// Equation(s):
+// \counter[19]~63_combout  = (counter[19] & (\counter[18]~62  $ (GND))) # (!counter[19] & (!\counter[18]~62  & VCC))
+// \counter[19]~64  = CARRY((counter[19] & !\counter[18]~62 ))
+
+	.dataa(counter[19]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[18]~62 ),
+	.combout(\counter[19]~63_combout ),
+	.cout(\counter[19]~64 ));
+// synopsys translate_off
+defparam \counter[19]~63 .lut_mask = 16'hA50A;
+defparam \counter[19]~63 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N11
+dffeas \counter[19] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[19]~63_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[19]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[19] .is_wysiwyg = "true";
+defparam \counter[19] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N12
+cycloneive_lcell_comb \counter[20]~65 (
+// Equation(s):
+// \counter[20]~65_combout  = (counter[20] & (!\counter[19]~64 )) # (!counter[20] & ((\counter[19]~64 ) # (GND)))
+// \counter[20]~66  = CARRY((!\counter[19]~64 ) # (!counter[20]))
+
+	.dataa(counter[20]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[19]~64 ),
+	.combout(\counter[20]~65_combout ),
+	.cout(\counter[20]~66 ));
+// synopsys translate_off
+defparam \counter[20]~65 .lut_mask = 16'h5A5F;
+defparam \counter[20]~65 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N13
+dffeas \counter[20] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[20]~65_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[20]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[20] .is_wysiwyg = "true";
+defparam \counter[20] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N14
+cycloneive_lcell_comb \counter[21]~67 (
+// Equation(s):
+// \counter[21]~67_combout  = (counter[21] & (\counter[20]~66  $ (GND))) # (!counter[21] & (!\counter[20]~66  & VCC))
+// \counter[21]~68  = CARRY((counter[21] & !\counter[20]~66 ))
+
+	.dataa(gnd),
+	.datab(counter[21]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[20]~66 ),
+	.combout(\counter[21]~67_combout ),
+	.cout(\counter[21]~68 ));
+// synopsys translate_off
+defparam \counter[21]~67 .lut_mask = 16'hC30C;
+defparam \counter[21]~67 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N15
+dffeas \counter[21] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[21]~67_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[21]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[21] .is_wysiwyg = "true";
+defparam \counter[21] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X38_Y32_N4
+cycloneive_lcell_comb \LED[0]~reg0feeder (
+// Equation(s):
+// \LED[0]~reg0feeder_combout  = counter[21]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(counter[21]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\LED[0]~reg0feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \LED[0]~reg0feeder .lut_mask = 16'hF0F0;
+defparam \LED[0]~reg0feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X38_Y32_N5
+dffeas \LED[0]~reg0 (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\LED[0]~reg0feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\LED[0]~reg0_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \LED[0]~reg0 .is_wysiwyg = "true";
+defparam \LED[0]~reg0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N16
+cycloneive_lcell_comb \counter[22]~69 (
+// Equation(s):
+// \counter[22]~69_combout  = (counter[22] & (!\counter[21]~68 )) # (!counter[22] & ((\counter[21]~68 ) # (GND)))
+// \counter[22]~70  = CARRY((!\counter[21]~68 ) # (!counter[22]))
+
+	.dataa(gnd),
+	.datab(counter[22]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[21]~68 ),
+	.combout(\counter[22]~69_combout ),
+	.cout(\counter[22]~70 ));
+// synopsys translate_off
+defparam \counter[22]~69 .lut_mask = 16'h3C3F;
+defparam \counter[22]~69 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N17
+dffeas \counter[22] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[22]~69_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[22]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[22] .is_wysiwyg = "true";
+defparam \counter[22] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X46_Y32_N12
+cycloneive_lcell_comb \LED[1]~reg0feeder (
+// Equation(s):
+// \LED[1]~reg0feeder_combout  = counter[22]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(counter[22]),
+	.cin(gnd),
+	.combout(\LED[1]~reg0feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \LED[1]~reg0feeder .lut_mask = 16'hFF00;
+defparam \LED[1]~reg0feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X46_Y32_N13
+dffeas \LED[1]~reg0 (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\LED[1]~reg0feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\LED[1]~reg0_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \LED[1]~reg0 .is_wysiwyg = "true";
+defparam \LED[1]~reg0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N18
+cycloneive_lcell_comb \counter[23]~71 (
+// Equation(s):
+// \counter[23]~71_combout  = (counter[23] & (\counter[22]~70  $ (GND))) # (!counter[23] & (!\counter[22]~70  & VCC))
+// \counter[23]~72  = CARRY((counter[23] & !\counter[22]~70 ))
+
+	.dataa(gnd),
+	.datab(counter[23]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[22]~70 ),
+	.combout(\counter[23]~71_combout ),
+	.cout(\counter[23]~72 ));
+// synopsys translate_off
+defparam \counter[23]~71 .lut_mask = 16'hC30C;
+defparam \counter[23]~71 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N19
+dffeas \counter[23] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[23]~71_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[23]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[23] .is_wysiwyg = "true";
+defparam \counter[23] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X46_Y32_N6
+cycloneive_lcell_comb \LED[2]~reg0feeder (
+// Equation(s):
+// \LED[2]~reg0feeder_combout  = counter[23]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(counter[23]),
+	.cin(gnd),
+	.combout(\LED[2]~reg0feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \LED[2]~reg0feeder .lut_mask = 16'hFF00;
+defparam \LED[2]~reg0feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X46_Y32_N7
+dffeas \LED[2]~reg0 (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\LED[2]~reg0feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\LED[2]~reg0_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \LED[2]~reg0 .is_wysiwyg = "true";
+defparam \LED[2]~reg0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N20
+cycloneive_lcell_comb \counter[24]~73 (
+// Equation(s):
+// \counter[24]~73_combout  = (counter[24] & (!\counter[23]~72 )) # (!counter[24] & ((\counter[23]~72 ) # (GND)))
+// \counter[24]~74  = CARRY((!\counter[23]~72 ) # (!counter[24]))
+
+	.dataa(gnd),
+	.datab(counter[24]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[23]~72 ),
+	.combout(\counter[24]~73_combout ),
+	.cout(\counter[24]~74 ));
+// synopsys translate_off
+defparam \counter[24]~73 .lut_mask = 16'h3C3F;
+defparam \counter[24]~73 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N21
+dffeas \counter[24] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[24]~73_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[24]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[24] .is_wysiwyg = "true";
+defparam \counter[24] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X40_Y32_N4
+cycloneive_lcell_comb \LED[3]~reg0feeder (
+// Equation(s):
+// \LED[3]~reg0feeder_combout  = counter[24]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(counter[24]),
+	.cin(gnd),
+	.combout(\LED[3]~reg0feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \LED[3]~reg0feeder .lut_mask = 16'hFF00;
+defparam \LED[3]~reg0feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X40_Y32_N5
+dffeas \LED[3]~reg0 (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\LED[3]~reg0feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\LED[3]~reg0_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \LED[3]~reg0 .is_wysiwyg = "true";
+defparam \LED[3]~reg0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N22
+cycloneive_lcell_comb \counter[25]~75 (
+// Equation(s):
+// \counter[25]~75_combout  = (counter[25] & (\counter[24]~74  $ (GND))) # (!counter[25] & (!\counter[24]~74  & VCC))
+// \counter[25]~76  = CARRY((counter[25] & !\counter[24]~74 ))
+
+	.dataa(counter[25]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[24]~74 ),
+	.combout(\counter[25]~75_combout ),
+	.cout(\counter[25]~76 ));
+// synopsys translate_off
+defparam \counter[25]~75 .lut_mask = 16'hA50A;
+defparam \counter[25]~75 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N23
+dffeas \counter[25] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[25]~75_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[25]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[25] .is_wysiwyg = "true";
+defparam \counter[25] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X38_Y32_N18
+cycloneive_lcell_comb \LED[4]~reg0feeder (
+// Equation(s):
+// \LED[4]~reg0feeder_combout  = counter[25]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(counter[25]),
+	.cin(gnd),
+	.combout(\LED[4]~reg0feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \LED[4]~reg0feeder .lut_mask = 16'hFF00;
+defparam \LED[4]~reg0feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X38_Y32_N19
+dffeas \LED[4]~reg0 (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\LED[4]~reg0feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\LED[4]~reg0_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \LED[4]~reg0 .is_wysiwyg = "true";
+defparam \LED[4]~reg0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N24
+cycloneive_lcell_comb \counter[26]~77 (
+// Equation(s):
+// \counter[26]~77_combout  = (counter[26] & (!\counter[25]~76 )) # (!counter[26] & ((\counter[25]~76 ) # (GND)))
+// \counter[26]~78  = CARRY((!\counter[25]~76 ) # (!counter[26]))
+
+	.dataa(gnd),
+	.datab(counter[26]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[25]~76 ),
+	.combout(\counter[26]~77_combout ),
+	.cout(\counter[26]~78 ));
+// synopsys translate_off
+defparam \counter[26]~77 .lut_mask = 16'h3C3F;
+defparam \counter[26]~77 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N25
+dffeas \counter[26] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[26]~77_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[26]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[26] .is_wysiwyg = "true";
+defparam \counter[26] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X38_Y32_N24
+cycloneive_lcell_comb \LED[5]~reg0feeder (
+// Equation(s):
+// \LED[5]~reg0feeder_combout  = counter[26]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(counter[26]),
+	.cin(gnd),
+	.combout(\LED[5]~reg0feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \LED[5]~reg0feeder .lut_mask = 16'hFF00;
+defparam \LED[5]~reg0feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X38_Y32_N25
+dffeas \LED[5]~reg0 (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\LED[5]~reg0feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\LED[5]~reg0_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \LED[5]~reg0 .is_wysiwyg = "true";
+defparam \LED[5]~reg0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N26
+cycloneive_lcell_comb \counter[27]~79 (
+// Equation(s):
+// \counter[27]~79_combout  = counter[27] $ (!\counter[26]~78 )
+
+	.dataa(counter[27]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\counter[26]~78 ),
+	.combout(\counter[27]~79_combout ),
+	.cout());
+// synopsys translate_off
+defparam \counter[27]~79 .lut_mask = 16'hA5A5;
+defparam \counter[27]~79 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N27
+dffeas \counter[27] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[27]~79_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[27]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[27] .is_wysiwyg = "true";
+defparam \counter[27] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X38_Y32_N14
+cycloneive_lcell_comb \LED[6]~reg0feeder (
+// Equation(s):
+// \LED[6]~reg0feeder_combout  = counter[27]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(counter[27]),
+	.cin(gnd),
+	.combout(\LED[6]~reg0feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \LED[6]~reg0feeder .lut_mask = 16'hFF00;
+defparam \LED[6]~reg0feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X38_Y32_N15
+dffeas \LED[6]~reg0 (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\LED[6]~reg0feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\LED[6]~reg0_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \LED[6]~reg0 .is_wysiwyg = "true";
+defparam \LED[6]~reg0 .power_up = "low";
+// synopsys translate_on
+
+assign LED[0] = \LED[0]~output_o ;
+
+assign LED[1] = \LED[1]~output_o ;
+
+assign LED[2] = \LED[2]~output_o ;
+
+assign LED[3] = \LED[3]~output_o ;
+
+assign LED[4] = \LED[4]~output_o ;
+
+assign LED[5] = \LED[5]~output_o ;
+
+assign LED[6] = \LED[6]~output_o ;
+
+assign LED[7] = \LED[7]~output_o ;
+
+endmodule
diff --git a/simulation/modelsim/spectrum_6_1200mv_0c_slow.vo b/simulation/modelsim/spectrum_6_1200mv_0c_slow.vo
new file mode 100644
index 0000000..e2f2b0b
--- /dev/null
+++ b/simulation/modelsim/spectrum_6_1200mv_0c_slow.vo
@@ -0,0 +1,1574 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+// VENDOR "Altera"
+// PROGRAM "Quartus II 32-bit"
+// VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+// DATE "03/30/2022 11:51:43"
+
+// 
+// Device: Altera EP4CE22F17C6 Package FBGA256
+// 
+
+// 
+// This Verilog file should be used for ModelSim-Altera (Verilog) only
+// 
+
+`timescale 1 ps/ 1 ps
+
+module spectrum (
+	CLOCK_50,
+	LED);
+input 	CLOCK_50;
+output 	[7:0] LED;
+
+// Design Ports Information
+// LED[0]	=>  Location: PIN_A15,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LED[1]	=>  Location: PIN_A13,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LED[2]	=>  Location: PIN_B13,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LED[3]	=>  Location: PIN_A11,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LED[4]	=>  Location: PIN_D1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LED[5]	=>  Location: PIN_F3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LED[6]	=>  Location: PIN_B1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LED[7]	=>  Location: PIN_L3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// CLOCK_50	=>  Location: PIN_R8,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+
+
+wire gnd;
+wire vcc;
+wire unknown;
+
+assign gnd = 1'b0;
+assign vcc = 1'b1;
+assign unknown = 1'bx;
+
+tri1 devclrn;
+tri1 devpor;
+tri1 devoe;
+// synopsys translate_off
+initial $sdf_annotate("spectrum_6_1200mv_0c_v_slow.sdo");
+// synopsys translate_on
+
+wire \LED[0]~output_o ;
+wire \LED[1]~output_o ;
+wire \LED[2]~output_o ;
+wire \LED[3]~output_o ;
+wire \LED[4]~output_o ;
+wire \LED[5]~output_o ;
+wire \LED[6]~output_o ;
+wire \LED[7]~output_o ;
+wire \CLOCK_50~input_o ;
+wire \CLOCK_50~inputclkctrl_outclk ;
+wire \counter[0]~81_combout ;
+wire \counter[1]~27_combout ;
+wire \counter[1]~28 ;
+wire \counter[2]~29_combout ;
+wire \counter[2]~30 ;
+wire \counter[3]~31_combout ;
+wire \counter[3]~32 ;
+wire \counter[4]~33_combout ;
+wire \counter[4]~34 ;
+wire \counter[5]~35_combout ;
+wire \counter[5]~36 ;
+wire \counter[6]~37_combout ;
+wire \counter[6]~38 ;
+wire \counter[7]~39_combout ;
+wire \counter[7]~40 ;
+wire \counter[8]~41_combout ;
+wire \counter[8]~42 ;
+wire \counter[9]~43_combout ;
+wire \counter[9]~44 ;
+wire \counter[10]~45_combout ;
+wire \counter[10]~46 ;
+wire \counter[11]~47_combout ;
+wire \counter[11]~48 ;
+wire \counter[12]~49_combout ;
+wire \counter[12]~50 ;
+wire \counter[13]~51_combout ;
+wire \counter[13]~52 ;
+wire \counter[14]~53_combout ;
+wire \counter[14]~54 ;
+wire \counter[15]~55_combout ;
+wire \counter[15]~56 ;
+wire \counter[16]~57_combout ;
+wire \counter[16]~58 ;
+wire \counter[17]~59_combout ;
+wire \counter[17]~60 ;
+wire \counter[18]~61_combout ;
+wire \counter[18]~62 ;
+wire \counter[19]~63_combout ;
+wire \counter[19]~64 ;
+wire \counter[20]~65_combout ;
+wire \counter[20]~66 ;
+wire \counter[21]~67_combout ;
+wire \LED[0]~reg0feeder_combout ;
+wire \LED[0]~reg0_q ;
+wire \counter[21]~68 ;
+wire \counter[22]~69_combout ;
+wire \LED[1]~reg0feeder_combout ;
+wire \LED[1]~reg0_q ;
+wire \counter[22]~70 ;
+wire \counter[23]~71_combout ;
+wire \LED[2]~reg0feeder_combout ;
+wire \LED[2]~reg0_q ;
+wire \counter[23]~72 ;
+wire \counter[24]~73_combout ;
+wire \LED[3]~reg0feeder_combout ;
+wire \LED[3]~reg0_q ;
+wire \counter[24]~74 ;
+wire \counter[25]~75_combout ;
+wire \LED[4]~reg0feeder_combout ;
+wire \LED[4]~reg0_q ;
+wire \counter[25]~76 ;
+wire \counter[26]~77_combout ;
+wire \LED[5]~reg0feeder_combout ;
+wire \LED[5]~reg0_q ;
+wire \counter[26]~78 ;
+wire \counter[27]~79_combout ;
+wire \LED[6]~reg0feeder_combout ;
+wire \LED[6]~reg0_q ;
+wire [27:0] counter;
+
+
+// Location: IOOBUF_X38_Y34_N16
+cycloneive_io_obuf \LED[0]~output (
+	.i(\LED[0]~reg0_q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LED[0]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LED[0]~output .bus_hold = "false";
+defparam \LED[0]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X49_Y34_N2
+cycloneive_io_obuf \LED[1]~output (
+	.i(\LED[1]~reg0_q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LED[1]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LED[1]~output .bus_hold = "false";
+defparam \LED[1]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X49_Y34_N9
+cycloneive_io_obuf \LED[2]~output (
+	.i(\LED[2]~reg0_q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LED[2]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LED[2]~output .bus_hold = "false";
+defparam \LED[2]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X40_Y34_N2
+cycloneive_io_obuf \LED[3]~output (
+	.i(\LED[3]~reg0_q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LED[3]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LED[3]~output .bus_hold = "false";
+defparam \LED[3]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y25_N9
+cycloneive_io_obuf \LED[4]~output (
+	.i(\LED[4]~reg0_q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LED[4]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LED[4]~output .bus_hold = "false";
+defparam \LED[4]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y26_N16
+cycloneive_io_obuf \LED[5]~output (
+	.i(\LED[5]~reg0_q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LED[5]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LED[5]~output .bus_hold = "false";
+defparam \LED[5]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y28_N9
+cycloneive_io_obuf \LED[6]~output (
+	.i(\LED[6]~reg0_q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LED[6]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LED[6]~output .bus_hold = "false";
+defparam \LED[6]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y10_N23
+cycloneive_io_obuf \LED[7]~output (
+	.i(gnd),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LED[7]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LED[7]~output .bus_hold = "false";
+defparam \LED[7]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOIBUF_X27_Y0_N22
+cycloneive_io_ibuf \CLOCK_50~input (
+	.i(CLOCK_50),
+	.ibar(gnd),
+	.o(\CLOCK_50~input_o ));
+// synopsys translate_off
+defparam \CLOCK_50~input .bus_hold = "false";
+defparam \CLOCK_50~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: CLKCTRL_G18
+cycloneive_clkctrl \CLOCK_50~inputclkctrl (
+	.ena(vcc),
+	.inclk({vcc,vcc,vcc,\CLOCK_50~input_o }),
+	.clkselect(2'b00),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.outclk(\CLOCK_50~inputclkctrl_outclk ));
+// synopsys translate_off
+defparam \CLOCK_50~inputclkctrl .clock_type = "global clock";
+defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N4
+cycloneive_lcell_comb \counter[0]~81 (
+// Equation(s):
+// \counter[0]~81_combout  = !counter[0]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(counter[0]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\counter[0]~81_combout ),
+	.cout());
+// synopsys translate_off
+defparam \counter[0]~81 .lut_mask = 16'h0F0F;
+defparam \counter[0]~81 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N5
+dffeas \counter[0] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[0]~81_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[0] .is_wysiwyg = "true";
+defparam \counter[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N6
+cycloneive_lcell_comb \counter[1]~27 (
+// Equation(s):
+// \counter[1]~27_combout  = (counter[1] & (counter[0] $ (VCC))) # (!counter[1] & (counter[0] & VCC))
+// \counter[1]~28  = CARRY((counter[1] & counter[0]))
+
+	.dataa(counter[1]),
+	.datab(counter[0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\counter[1]~27_combout ),
+	.cout(\counter[1]~28 ));
+// synopsys translate_off
+defparam \counter[1]~27 .lut_mask = 16'h6688;
+defparam \counter[1]~27 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N7
+dffeas \counter[1] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[1]~27_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[1] .is_wysiwyg = "true";
+defparam \counter[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N8
+cycloneive_lcell_comb \counter[2]~29 (
+// Equation(s):
+// \counter[2]~29_combout  = (counter[2] & (!\counter[1]~28 )) # (!counter[2] & ((\counter[1]~28 ) # (GND)))
+// \counter[2]~30  = CARRY((!\counter[1]~28 ) # (!counter[2]))
+
+	.dataa(gnd),
+	.datab(counter[2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[1]~28 ),
+	.combout(\counter[2]~29_combout ),
+	.cout(\counter[2]~30 ));
+// synopsys translate_off
+defparam \counter[2]~29 .lut_mask = 16'h3C3F;
+defparam \counter[2]~29 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N9
+dffeas \counter[2] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[2]~29_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[2] .is_wysiwyg = "true";
+defparam \counter[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N10
+cycloneive_lcell_comb \counter[3]~31 (
+// Equation(s):
+// \counter[3]~31_combout  = (counter[3] & (\counter[2]~30  $ (GND))) # (!counter[3] & (!\counter[2]~30  & VCC))
+// \counter[3]~32  = CARRY((counter[3] & !\counter[2]~30 ))
+
+	.dataa(counter[3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[2]~30 ),
+	.combout(\counter[3]~31_combout ),
+	.cout(\counter[3]~32 ));
+// synopsys translate_off
+defparam \counter[3]~31 .lut_mask = 16'hA50A;
+defparam \counter[3]~31 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N11
+dffeas \counter[3] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[3]~31_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[3] .is_wysiwyg = "true";
+defparam \counter[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N12
+cycloneive_lcell_comb \counter[4]~33 (
+// Equation(s):
+// \counter[4]~33_combout  = (counter[4] & (!\counter[3]~32 )) # (!counter[4] & ((\counter[3]~32 ) # (GND)))
+// \counter[4]~34  = CARRY((!\counter[3]~32 ) # (!counter[4]))
+
+	.dataa(counter[4]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[3]~32 ),
+	.combout(\counter[4]~33_combout ),
+	.cout(\counter[4]~34 ));
+// synopsys translate_off
+defparam \counter[4]~33 .lut_mask = 16'h5A5F;
+defparam \counter[4]~33 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N13
+dffeas \counter[4] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[4]~33_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[4] .is_wysiwyg = "true";
+defparam \counter[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N14
+cycloneive_lcell_comb \counter[5]~35 (
+// Equation(s):
+// \counter[5]~35_combout  = (counter[5] & (\counter[4]~34  $ (GND))) # (!counter[5] & (!\counter[4]~34  & VCC))
+// \counter[5]~36  = CARRY((counter[5] & !\counter[4]~34 ))
+
+	.dataa(gnd),
+	.datab(counter[5]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[4]~34 ),
+	.combout(\counter[5]~35_combout ),
+	.cout(\counter[5]~36 ));
+// synopsys translate_off
+defparam \counter[5]~35 .lut_mask = 16'hC30C;
+defparam \counter[5]~35 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N15
+dffeas \counter[5] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[5]~35_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[5] .is_wysiwyg = "true";
+defparam \counter[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N16
+cycloneive_lcell_comb \counter[6]~37 (
+// Equation(s):
+// \counter[6]~37_combout  = (counter[6] & (!\counter[5]~36 )) # (!counter[6] & ((\counter[5]~36 ) # (GND)))
+// \counter[6]~38  = CARRY((!\counter[5]~36 ) # (!counter[6]))
+
+	.dataa(gnd),
+	.datab(counter[6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[5]~36 ),
+	.combout(\counter[6]~37_combout ),
+	.cout(\counter[6]~38 ));
+// synopsys translate_off
+defparam \counter[6]~37 .lut_mask = 16'h3C3F;
+defparam \counter[6]~37 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N17
+dffeas \counter[6] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[6]~37_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[6] .is_wysiwyg = "true";
+defparam \counter[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N18
+cycloneive_lcell_comb \counter[7]~39 (
+// Equation(s):
+// \counter[7]~39_combout  = (counter[7] & (\counter[6]~38  $ (GND))) # (!counter[7] & (!\counter[6]~38  & VCC))
+// \counter[7]~40  = CARRY((counter[7] & !\counter[6]~38 ))
+
+	.dataa(gnd),
+	.datab(counter[7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[6]~38 ),
+	.combout(\counter[7]~39_combout ),
+	.cout(\counter[7]~40 ));
+// synopsys translate_off
+defparam \counter[7]~39 .lut_mask = 16'hC30C;
+defparam \counter[7]~39 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N19
+dffeas \counter[7] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[7]~39_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[7] .is_wysiwyg = "true";
+defparam \counter[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N20
+cycloneive_lcell_comb \counter[8]~41 (
+// Equation(s):
+// \counter[8]~41_combout  = (counter[8] & (!\counter[7]~40 )) # (!counter[8] & ((\counter[7]~40 ) # (GND)))
+// \counter[8]~42  = CARRY((!\counter[7]~40 ) # (!counter[8]))
+
+	.dataa(gnd),
+	.datab(counter[8]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[7]~40 ),
+	.combout(\counter[8]~41_combout ),
+	.cout(\counter[8]~42 ));
+// synopsys translate_off
+defparam \counter[8]~41 .lut_mask = 16'h3C3F;
+defparam \counter[8]~41 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N21
+dffeas \counter[8] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[8]~41_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[8] .is_wysiwyg = "true";
+defparam \counter[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N22
+cycloneive_lcell_comb \counter[9]~43 (
+// Equation(s):
+// \counter[9]~43_combout  = (counter[9] & (\counter[8]~42  $ (GND))) # (!counter[9] & (!\counter[8]~42  & VCC))
+// \counter[9]~44  = CARRY((counter[9] & !\counter[8]~42 ))
+
+	.dataa(counter[9]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[8]~42 ),
+	.combout(\counter[9]~43_combout ),
+	.cout(\counter[9]~44 ));
+// synopsys translate_off
+defparam \counter[9]~43 .lut_mask = 16'hA50A;
+defparam \counter[9]~43 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N23
+dffeas \counter[9] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[9]~43_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[9] .is_wysiwyg = "true";
+defparam \counter[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N24
+cycloneive_lcell_comb \counter[10]~45 (
+// Equation(s):
+// \counter[10]~45_combout  = (counter[10] & (!\counter[9]~44 )) # (!counter[10] & ((\counter[9]~44 ) # (GND)))
+// \counter[10]~46  = CARRY((!\counter[9]~44 ) # (!counter[10]))
+
+	.dataa(gnd),
+	.datab(counter[10]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[9]~44 ),
+	.combout(\counter[10]~45_combout ),
+	.cout(\counter[10]~46 ));
+// synopsys translate_off
+defparam \counter[10]~45 .lut_mask = 16'h3C3F;
+defparam \counter[10]~45 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N25
+dffeas \counter[10] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[10]~45_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[10] .is_wysiwyg = "true";
+defparam \counter[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N26
+cycloneive_lcell_comb \counter[11]~47 (
+// Equation(s):
+// \counter[11]~47_combout  = (counter[11] & (\counter[10]~46  $ (GND))) # (!counter[11] & (!\counter[10]~46  & VCC))
+// \counter[11]~48  = CARRY((counter[11] & !\counter[10]~46 ))
+
+	.dataa(counter[11]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[10]~46 ),
+	.combout(\counter[11]~47_combout ),
+	.cout(\counter[11]~48 ));
+// synopsys translate_off
+defparam \counter[11]~47 .lut_mask = 16'hA50A;
+defparam \counter[11]~47 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N27
+dffeas \counter[11] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[11]~47_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[11] .is_wysiwyg = "true";
+defparam \counter[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N28
+cycloneive_lcell_comb \counter[12]~49 (
+// Equation(s):
+// \counter[12]~49_combout  = (counter[12] & (!\counter[11]~48 )) # (!counter[12] & ((\counter[11]~48 ) # (GND)))
+// \counter[12]~50  = CARRY((!\counter[11]~48 ) # (!counter[12]))
+
+	.dataa(gnd),
+	.datab(counter[12]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[11]~48 ),
+	.combout(\counter[12]~49_combout ),
+	.cout(\counter[12]~50 ));
+// synopsys translate_off
+defparam \counter[12]~49 .lut_mask = 16'h3C3F;
+defparam \counter[12]~49 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N29
+dffeas \counter[12] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[12]~49_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[12] .is_wysiwyg = "true";
+defparam \counter[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N30
+cycloneive_lcell_comb \counter[13]~51 (
+// Equation(s):
+// \counter[13]~51_combout  = (counter[13] & (\counter[12]~50  $ (GND))) # (!counter[13] & (!\counter[12]~50  & VCC))
+// \counter[13]~52  = CARRY((counter[13] & !\counter[12]~50 ))
+
+	.dataa(counter[13]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[12]~50 ),
+	.combout(\counter[13]~51_combout ),
+	.cout(\counter[13]~52 ));
+// synopsys translate_off
+defparam \counter[13]~51 .lut_mask = 16'hA50A;
+defparam \counter[13]~51 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N31
+dffeas \counter[13] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[13]~51_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[13]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[13] .is_wysiwyg = "true";
+defparam \counter[13] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N0
+cycloneive_lcell_comb \counter[14]~53 (
+// Equation(s):
+// \counter[14]~53_combout  = (counter[14] & (!\counter[13]~52 )) # (!counter[14] & ((\counter[13]~52 ) # (GND)))
+// \counter[14]~54  = CARRY((!\counter[13]~52 ) # (!counter[14]))
+
+	.dataa(gnd),
+	.datab(counter[14]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[13]~52 ),
+	.combout(\counter[14]~53_combout ),
+	.cout(\counter[14]~54 ));
+// synopsys translate_off
+defparam \counter[14]~53 .lut_mask = 16'h3C3F;
+defparam \counter[14]~53 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N1
+dffeas \counter[14] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[14]~53_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[14]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[14] .is_wysiwyg = "true";
+defparam \counter[14] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N2
+cycloneive_lcell_comb \counter[15]~55 (
+// Equation(s):
+// \counter[15]~55_combout  = (counter[15] & (\counter[14]~54  $ (GND))) # (!counter[15] & (!\counter[14]~54  & VCC))
+// \counter[15]~56  = CARRY((counter[15] & !\counter[14]~54 ))
+
+	.dataa(gnd),
+	.datab(counter[15]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[14]~54 ),
+	.combout(\counter[15]~55_combout ),
+	.cout(\counter[15]~56 ));
+// synopsys translate_off
+defparam \counter[15]~55 .lut_mask = 16'hC30C;
+defparam \counter[15]~55 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N3
+dffeas \counter[15] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[15]~55_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[15]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[15] .is_wysiwyg = "true";
+defparam \counter[15] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N4
+cycloneive_lcell_comb \counter[16]~57 (
+// Equation(s):
+// \counter[16]~57_combout  = (counter[16] & (!\counter[15]~56 )) # (!counter[16] & ((\counter[15]~56 ) # (GND)))
+// \counter[16]~58  = CARRY((!\counter[15]~56 ) # (!counter[16]))
+
+	.dataa(gnd),
+	.datab(counter[16]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[15]~56 ),
+	.combout(\counter[16]~57_combout ),
+	.cout(\counter[16]~58 ));
+// synopsys translate_off
+defparam \counter[16]~57 .lut_mask = 16'h3C3F;
+defparam \counter[16]~57 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N5
+dffeas \counter[16] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[16]~57_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[16]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[16] .is_wysiwyg = "true";
+defparam \counter[16] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N6
+cycloneive_lcell_comb \counter[17]~59 (
+// Equation(s):
+// \counter[17]~59_combout  = (counter[17] & (\counter[16]~58  $ (GND))) # (!counter[17] & (!\counter[16]~58  & VCC))
+// \counter[17]~60  = CARRY((counter[17] & !\counter[16]~58 ))
+
+	.dataa(counter[17]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[16]~58 ),
+	.combout(\counter[17]~59_combout ),
+	.cout(\counter[17]~60 ));
+// synopsys translate_off
+defparam \counter[17]~59 .lut_mask = 16'hA50A;
+defparam \counter[17]~59 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N7
+dffeas \counter[17] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[17]~59_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[17]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[17] .is_wysiwyg = "true";
+defparam \counter[17] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N8
+cycloneive_lcell_comb \counter[18]~61 (
+// Equation(s):
+// \counter[18]~61_combout  = (counter[18] & (!\counter[17]~60 )) # (!counter[18] & ((\counter[17]~60 ) # (GND)))
+// \counter[18]~62  = CARRY((!\counter[17]~60 ) # (!counter[18]))
+
+	.dataa(gnd),
+	.datab(counter[18]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[17]~60 ),
+	.combout(\counter[18]~61_combout ),
+	.cout(\counter[18]~62 ));
+// synopsys translate_off
+defparam \counter[18]~61 .lut_mask = 16'h3C3F;
+defparam \counter[18]~61 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N9
+dffeas \counter[18] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[18]~61_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[18]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[18] .is_wysiwyg = "true";
+defparam \counter[18] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N10
+cycloneive_lcell_comb \counter[19]~63 (
+// Equation(s):
+// \counter[19]~63_combout  = (counter[19] & (\counter[18]~62  $ (GND))) # (!counter[19] & (!\counter[18]~62  & VCC))
+// \counter[19]~64  = CARRY((counter[19] & !\counter[18]~62 ))
+
+	.dataa(counter[19]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[18]~62 ),
+	.combout(\counter[19]~63_combout ),
+	.cout(\counter[19]~64 ));
+// synopsys translate_off
+defparam \counter[19]~63 .lut_mask = 16'hA50A;
+defparam \counter[19]~63 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N11
+dffeas \counter[19] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[19]~63_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[19]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[19] .is_wysiwyg = "true";
+defparam \counter[19] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N12
+cycloneive_lcell_comb \counter[20]~65 (
+// Equation(s):
+// \counter[20]~65_combout  = (counter[20] & (!\counter[19]~64 )) # (!counter[20] & ((\counter[19]~64 ) # (GND)))
+// \counter[20]~66  = CARRY((!\counter[19]~64 ) # (!counter[20]))
+
+	.dataa(counter[20]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[19]~64 ),
+	.combout(\counter[20]~65_combout ),
+	.cout(\counter[20]~66 ));
+// synopsys translate_off
+defparam \counter[20]~65 .lut_mask = 16'h5A5F;
+defparam \counter[20]~65 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N13
+dffeas \counter[20] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[20]~65_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[20]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[20] .is_wysiwyg = "true";
+defparam \counter[20] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N14
+cycloneive_lcell_comb \counter[21]~67 (
+// Equation(s):
+// \counter[21]~67_combout  = (counter[21] & (\counter[20]~66  $ (GND))) # (!counter[21] & (!\counter[20]~66  & VCC))
+// \counter[21]~68  = CARRY((counter[21] & !\counter[20]~66 ))
+
+	.dataa(gnd),
+	.datab(counter[21]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[20]~66 ),
+	.combout(\counter[21]~67_combout ),
+	.cout(\counter[21]~68 ));
+// synopsys translate_off
+defparam \counter[21]~67 .lut_mask = 16'hC30C;
+defparam \counter[21]~67 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N15
+dffeas \counter[21] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[21]~67_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[21]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[21] .is_wysiwyg = "true";
+defparam \counter[21] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X38_Y32_N4
+cycloneive_lcell_comb \LED[0]~reg0feeder (
+// Equation(s):
+// \LED[0]~reg0feeder_combout  = counter[21]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(counter[21]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\LED[0]~reg0feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \LED[0]~reg0feeder .lut_mask = 16'hF0F0;
+defparam \LED[0]~reg0feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X38_Y32_N5
+dffeas \LED[0]~reg0 (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\LED[0]~reg0feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\LED[0]~reg0_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \LED[0]~reg0 .is_wysiwyg = "true";
+defparam \LED[0]~reg0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N16
+cycloneive_lcell_comb \counter[22]~69 (
+// Equation(s):
+// \counter[22]~69_combout  = (counter[22] & (!\counter[21]~68 )) # (!counter[22] & ((\counter[21]~68 ) # (GND)))
+// \counter[22]~70  = CARRY((!\counter[21]~68 ) # (!counter[22]))
+
+	.dataa(gnd),
+	.datab(counter[22]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[21]~68 ),
+	.combout(\counter[22]~69_combout ),
+	.cout(\counter[22]~70 ));
+// synopsys translate_off
+defparam \counter[22]~69 .lut_mask = 16'h3C3F;
+defparam \counter[22]~69 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N17
+dffeas \counter[22] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[22]~69_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[22]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[22] .is_wysiwyg = "true";
+defparam \counter[22] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X46_Y32_N12
+cycloneive_lcell_comb \LED[1]~reg0feeder (
+// Equation(s):
+// \LED[1]~reg0feeder_combout  = counter[22]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(counter[22]),
+	.cin(gnd),
+	.combout(\LED[1]~reg0feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \LED[1]~reg0feeder .lut_mask = 16'hFF00;
+defparam \LED[1]~reg0feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X46_Y32_N13
+dffeas \LED[1]~reg0 (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\LED[1]~reg0feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\LED[1]~reg0_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \LED[1]~reg0 .is_wysiwyg = "true";
+defparam \LED[1]~reg0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N18
+cycloneive_lcell_comb \counter[23]~71 (
+// Equation(s):
+// \counter[23]~71_combout  = (counter[23] & (\counter[22]~70  $ (GND))) # (!counter[23] & (!\counter[22]~70  & VCC))
+// \counter[23]~72  = CARRY((counter[23] & !\counter[22]~70 ))
+
+	.dataa(gnd),
+	.datab(counter[23]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[22]~70 ),
+	.combout(\counter[23]~71_combout ),
+	.cout(\counter[23]~72 ));
+// synopsys translate_off
+defparam \counter[23]~71 .lut_mask = 16'hC30C;
+defparam \counter[23]~71 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N19
+dffeas \counter[23] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[23]~71_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[23]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[23] .is_wysiwyg = "true";
+defparam \counter[23] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X46_Y32_N6
+cycloneive_lcell_comb \LED[2]~reg0feeder (
+// Equation(s):
+// \LED[2]~reg0feeder_combout  = counter[23]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(counter[23]),
+	.cin(gnd),
+	.combout(\LED[2]~reg0feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \LED[2]~reg0feeder .lut_mask = 16'hFF00;
+defparam \LED[2]~reg0feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X46_Y32_N7
+dffeas \LED[2]~reg0 (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\LED[2]~reg0feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\LED[2]~reg0_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \LED[2]~reg0 .is_wysiwyg = "true";
+defparam \LED[2]~reg0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N20
+cycloneive_lcell_comb \counter[24]~73 (
+// Equation(s):
+// \counter[24]~73_combout  = (counter[24] & (!\counter[23]~72 )) # (!counter[24] & ((\counter[23]~72 ) # (GND)))
+// \counter[24]~74  = CARRY((!\counter[23]~72 ) # (!counter[24]))
+
+	.dataa(gnd),
+	.datab(counter[24]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[23]~72 ),
+	.combout(\counter[24]~73_combout ),
+	.cout(\counter[24]~74 ));
+// synopsys translate_off
+defparam \counter[24]~73 .lut_mask = 16'h3C3F;
+defparam \counter[24]~73 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N21
+dffeas \counter[24] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[24]~73_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[24]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[24] .is_wysiwyg = "true";
+defparam \counter[24] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X40_Y32_N4
+cycloneive_lcell_comb \LED[3]~reg0feeder (
+// Equation(s):
+// \LED[3]~reg0feeder_combout  = counter[24]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(counter[24]),
+	.cin(gnd),
+	.combout(\LED[3]~reg0feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \LED[3]~reg0feeder .lut_mask = 16'hFF00;
+defparam \LED[3]~reg0feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X40_Y32_N5
+dffeas \LED[3]~reg0 (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\LED[3]~reg0feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\LED[3]~reg0_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \LED[3]~reg0 .is_wysiwyg = "true";
+defparam \LED[3]~reg0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N22
+cycloneive_lcell_comb \counter[25]~75 (
+// Equation(s):
+// \counter[25]~75_combout  = (counter[25] & (\counter[24]~74  $ (GND))) # (!counter[25] & (!\counter[24]~74  & VCC))
+// \counter[25]~76  = CARRY((counter[25] & !\counter[24]~74 ))
+
+	.dataa(counter[25]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[24]~74 ),
+	.combout(\counter[25]~75_combout ),
+	.cout(\counter[25]~76 ));
+// synopsys translate_off
+defparam \counter[25]~75 .lut_mask = 16'hA50A;
+defparam \counter[25]~75 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N23
+dffeas \counter[25] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[25]~75_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[25]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[25] .is_wysiwyg = "true";
+defparam \counter[25] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X38_Y32_N18
+cycloneive_lcell_comb \LED[4]~reg0feeder (
+// Equation(s):
+// \LED[4]~reg0feeder_combout  = counter[25]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(counter[25]),
+	.cin(gnd),
+	.combout(\LED[4]~reg0feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \LED[4]~reg0feeder .lut_mask = 16'hFF00;
+defparam \LED[4]~reg0feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X38_Y32_N19
+dffeas \LED[4]~reg0 (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\LED[4]~reg0feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\LED[4]~reg0_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \LED[4]~reg0 .is_wysiwyg = "true";
+defparam \LED[4]~reg0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N24
+cycloneive_lcell_comb \counter[26]~77 (
+// Equation(s):
+// \counter[26]~77_combout  = (counter[26] & (!\counter[25]~76 )) # (!counter[26] & ((\counter[25]~76 ) # (GND)))
+// \counter[26]~78  = CARRY((!\counter[25]~76 ) # (!counter[26]))
+
+	.dataa(gnd),
+	.datab(counter[26]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[25]~76 ),
+	.combout(\counter[26]~77_combout ),
+	.cout(\counter[26]~78 ));
+// synopsys translate_off
+defparam \counter[26]~77 .lut_mask = 16'h3C3F;
+defparam \counter[26]~77 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N25
+dffeas \counter[26] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[26]~77_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[26]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[26] .is_wysiwyg = "true";
+defparam \counter[26] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X38_Y32_N24
+cycloneive_lcell_comb \LED[5]~reg0feeder (
+// Equation(s):
+// \LED[5]~reg0feeder_combout  = counter[26]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(counter[26]),
+	.cin(gnd),
+	.combout(\LED[5]~reg0feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \LED[5]~reg0feeder .lut_mask = 16'hFF00;
+defparam \LED[5]~reg0feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X38_Y32_N25
+dffeas \LED[5]~reg0 (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\LED[5]~reg0feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\LED[5]~reg0_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \LED[5]~reg0 .is_wysiwyg = "true";
+defparam \LED[5]~reg0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N26
+cycloneive_lcell_comb \counter[27]~79 (
+// Equation(s):
+// \counter[27]~79_combout  = counter[27] $ (!\counter[26]~78 )
+
+	.dataa(counter[27]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\counter[26]~78 ),
+	.combout(\counter[27]~79_combout ),
+	.cout());
+// synopsys translate_off
+defparam \counter[27]~79 .lut_mask = 16'hA5A5;
+defparam \counter[27]~79 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N27
+dffeas \counter[27] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[27]~79_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[27]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[27] .is_wysiwyg = "true";
+defparam \counter[27] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X38_Y32_N14
+cycloneive_lcell_comb \LED[6]~reg0feeder (
+// Equation(s):
+// \LED[6]~reg0feeder_combout  = counter[27]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(counter[27]),
+	.cin(gnd),
+	.combout(\LED[6]~reg0feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \LED[6]~reg0feeder .lut_mask = 16'hFF00;
+defparam \LED[6]~reg0feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X38_Y32_N15
+dffeas \LED[6]~reg0 (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\LED[6]~reg0feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\LED[6]~reg0_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \LED[6]~reg0 .is_wysiwyg = "true";
+defparam \LED[6]~reg0 .power_up = "low";
+// synopsys translate_on
+
+assign LED[0] = \LED[0]~output_o ;
+
+assign LED[1] = \LED[1]~output_o ;
+
+assign LED[2] = \LED[2]~output_o ;
+
+assign LED[3] = \LED[3]~output_o ;
+
+assign LED[4] = \LED[4]~output_o ;
+
+assign LED[5] = \LED[5]~output_o ;
+
+assign LED[6] = \LED[6]~output_o ;
+
+assign LED[7] = \LED[7]~output_o ;
+
+endmodule
diff --git a/simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo b/simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo
new file mode 100644
index 0000000..9d25589
--- /dev/null
+++ b/simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo
@@ -0,0 +1,1072 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP4CE22F17C6 Package FBGA256
+// 
+
+//
+// This file contains Slow Corner delays for the design using part EP4CE22F17C6,
+// with speed grade 6, core voltage 1.2V, and temperature 0 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (Verilog) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "spectrum")
+  (DATE "03/30/2022 11:51:43")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 32-bit")
+  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneive_io_obuf")
+    (INSTANCE LED\[0\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (476:476:476) (485:485:485))
+        (IOPATH i o (2265:2265:2265) (2180:2180:2180))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_obuf")
+    (INSTANCE LED\[1\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (698:698:698) (688:688:688))
+        (IOPATH i o (2265:2265:2265) (2180:2180:2180))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_obuf")
+    (INSTANCE LED\[2\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (684:684:684) (669:669:669))
+        (IOPATH i o (2265:2265:2265) (2180:2180:2180))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_obuf")
+    (INSTANCE LED\[3\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (475:475:475) (484:484:484))
+        (IOPATH i o (2265:2265:2265) (2180:2180:2180))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_obuf")
+    (INSTANCE LED\[4\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (2278:2278:2278) (2290:2290:2290))
+        (IOPATH i o (2277:2277:2277) (2180:2180:2180))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_obuf")
+    (INSTANCE LED\[5\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (2269:2269:2269) (2279:2279:2279))
+        (IOPATH i o (3961:3961:3961) (3539:3539:3539))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_obuf")
+    (INSTANCE LED\[6\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1208:1208:1208) (1282:1282:1282))
+        (IOPATH i o (2194:2194:2194) (2119:2119:2119))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_ibuf")
+    (INSTANCE CLOCK_50\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (459:459:459) (708:708:708))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_clkctrl")
+    (INSTANCE CLOCK_50\~inputclkctrl)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (133:133:133) (124:124:124))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[0\]\~81)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH datac combout (312:312:312) (325:325:325))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1354:1354:1354) (1369:1369:1369))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[1\]\~27)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (221:221:221) (293:293:293))
+        (PORT datab (220:220:220) (288:288:288))
+        (IOPATH dataa combout (300:300:300) (323:323:323))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datab combout (306:306:306) (324:324:324))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1354:1354:1354) (1369:1369:1369))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[2\]\~29)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (221:221:221) (289:289:289))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1354:1354:1354) (1369:1369:1369))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[3\]\~31)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (222:222:222) (296:296:296))
+        (IOPATH dataa combout (318:318:318) (323:323:323))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1354:1354:1354) (1369:1369:1369))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[4\]\~33)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (222:222:222) (296:296:296))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1354:1354:1354) (1369:1369:1369))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[5\]\~35)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (221:221:221) (290:290:290))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1354:1354:1354) (1369:1369:1369))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[6\]\~37)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (221:221:221) (290:290:290))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1354:1354:1354) (1369:1369:1369))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[7\]\~39)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (221:221:221) (290:290:290))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1354:1354:1354) (1369:1369:1369))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[8\]\~41)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (221:221:221) (291:291:291))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1354:1354:1354) (1369:1369:1369))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[9\]\~43)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (222:222:222) (294:294:294))
+        (IOPATH dataa combout (318:318:318) (323:323:323))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1354:1354:1354) (1369:1369:1369))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[10\]\~45)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (221:221:221) (289:289:289))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1354:1354:1354) (1369:1369:1369))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[11\]\~47)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (221:221:221) (293:293:293))
+        (IOPATH dataa combout (318:318:318) (323:323:323))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1354:1354:1354) (1369:1369:1369))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[12\]\~49)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (220:220:220) (288:288:288))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[12\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1354:1354:1354) (1369:1369:1369))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[13\]\~51)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (221:221:221) (294:294:294))
+        (IOPATH dataa combout (318:318:318) (323:323:323))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[13\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1681:1681:1681) (1700:1700:1700))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[14\]\~53)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (219:219:219) (288:288:288))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[14\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1353:1353:1353) (1369:1369:1369))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[15\]\~55)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (220:220:220) (288:288:288))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[15\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1353:1353:1353) (1369:1369:1369))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[16\]\~57)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (220:220:220) (289:289:289))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[16\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1353:1353:1353) (1369:1369:1369))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[17\]\~59)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (222:222:222) (294:294:294))
+        (IOPATH dataa combout (318:318:318) (323:323:323))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[17\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1681:1681:1681) (1700:1700:1700))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[18\]\~61)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (222:222:222) (290:290:290))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[18\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1681:1681:1681) (1700:1700:1700))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[19\]\~63)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (223:223:223) (297:297:297))
+        (IOPATH dataa combout (318:318:318) (323:323:323))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[19\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1681:1681:1681) (1700:1700:1700))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[20\]\~65)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (223:223:223) (297:297:297))
+        (IOPATH dataa combout (318:318:318) (327:327:327))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[20\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1681:1681:1681) (1700:1700:1700))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[21\]\~67)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (241:241:241) (310:310:310))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[21\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1681:1681:1681) (1700:1700:1700))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE LED\[0\]\~reg0feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (385:385:385) (415:415:415))
+        (IOPATH datac combout (220:220:220) (216:216:216))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE LED\[0\]\~reg0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1353:1353:1353) (1369:1369:1369))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[22\]\~69)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (241:241:241) (310:310:310))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[22\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1681:1681:1681) (1700:1700:1700))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE LED\[1\]\~reg0feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (749:749:749) (752:752:752))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE LED\[1\]\~reg0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1359:1359:1359) (1375:1375:1375))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[23\]\~71)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (241:241:241) (310:310:310))
+        (IOPATH datab combout (319:319:319) (324:324:324))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[23\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1681:1681:1681) (1700:1700:1700))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE LED\[2\]\~reg0feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (721:721:721) (721:721:721))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE LED\[2\]\~reg0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1359:1359:1359) (1375:1375:1375))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[24\]\~73)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (241:241:241) (311:311:311))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[24\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1681:1681:1681) (1700:1700:1700))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE LED\[3\]\~reg0feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (369:369:369) (405:405:405))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE LED\[3\]\~reg0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1354:1354:1354) (1370:1370:1370))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[25\]\~75)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (242:242:242) (314:314:314))
+        (IOPATH dataa combout (318:318:318) (323:323:323))
+        (IOPATH dataa cout (376:376:376) (275:275:275))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[25\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1681:1681:1681) (1700:1700:1700))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE LED\[4\]\~reg0feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (376:376:376) (411:411:411))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE LED\[4\]\~reg0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1353:1353:1353) (1369:1369:1369))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[26\]\~77)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (240:240:240) (309:309:309))
+        (IOPATH datab combout (325:325:325) (332:332:332))
+        (IOPATH datab cout (385:385:385) (280:280:280))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+        (IOPATH cin cout (50:50:50) (50:50:50))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[26\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1681:1681:1681) (1700:1700:1700))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE LED\[5\]\~reg0feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (568:568:568) (590:590:590))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE LED\[5\]\~reg0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1353:1353:1353) (1369:1369:1369))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[27\]\~79)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (242:242:242) (315:315:315))
+        (IOPATH dataa combout (329:329:329) (332:332:332))
+        (IOPATH cin combout (408:408:408) (387:387:387))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[27\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1681:1681:1681) (1700:1700:1700))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE LED\[6\]\~reg0feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (378:378:378) (412:412:412))
+        (IOPATH datad combout (119:119:119) (106:106:106))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE LED\[6\]\~reg0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1353:1353:1353) (1369:1369:1369))
+        (PORT d (67:67:67) (78:78:78))
+        (IOPATH (posedge clk) q (180:180:180) (180:180:180))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (144:144:144))
+    )
+  )
+)
diff --git a/simulation/modelsim/spectrum_6_1200mv_85c_slow.vo b/simulation/modelsim/spectrum_6_1200mv_85c_slow.vo
new file mode 100644
index 0000000..2c40645
--- /dev/null
+++ b/simulation/modelsim/spectrum_6_1200mv_85c_slow.vo
@@ -0,0 +1,1574 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+// VENDOR "Altera"
+// PROGRAM "Quartus II 32-bit"
+// VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+// DATE "03/30/2022 11:51:43"
+
+// 
+// Device: Altera EP4CE22F17C6 Package FBGA256
+// 
+
+// 
+// This Verilog file should be used for ModelSim-Altera (Verilog) only
+// 
+
+`timescale 1 ps/ 1 ps
+
+module spectrum (
+	CLOCK_50,
+	LED);
+input 	CLOCK_50;
+output 	[7:0] LED;
+
+// Design Ports Information
+// LED[0]	=>  Location: PIN_A15,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LED[1]	=>  Location: PIN_A13,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LED[2]	=>  Location: PIN_B13,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LED[3]	=>  Location: PIN_A11,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LED[4]	=>  Location: PIN_D1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LED[5]	=>  Location: PIN_F3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LED[6]	=>  Location: PIN_B1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LED[7]	=>  Location: PIN_L3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// CLOCK_50	=>  Location: PIN_R8,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+
+
+wire gnd;
+wire vcc;
+wire unknown;
+
+assign gnd = 1'b0;
+assign vcc = 1'b1;
+assign unknown = 1'bx;
+
+tri1 devclrn;
+tri1 devpor;
+tri1 devoe;
+// synopsys translate_off
+initial $sdf_annotate("spectrum_6_1200mv_85c_v_slow.sdo");
+// synopsys translate_on
+
+wire \LED[0]~output_o ;
+wire \LED[1]~output_o ;
+wire \LED[2]~output_o ;
+wire \LED[3]~output_o ;
+wire \LED[4]~output_o ;
+wire \LED[5]~output_o ;
+wire \LED[6]~output_o ;
+wire \LED[7]~output_o ;
+wire \CLOCK_50~input_o ;
+wire \CLOCK_50~inputclkctrl_outclk ;
+wire \counter[0]~81_combout ;
+wire \counter[1]~27_combout ;
+wire \counter[1]~28 ;
+wire \counter[2]~29_combout ;
+wire \counter[2]~30 ;
+wire \counter[3]~31_combout ;
+wire \counter[3]~32 ;
+wire \counter[4]~33_combout ;
+wire \counter[4]~34 ;
+wire \counter[5]~35_combout ;
+wire \counter[5]~36 ;
+wire \counter[6]~37_combout ;
+wire \counter[6]~38 ;
+wire \counter[7]~39_combout ;
+wire \counter[7]~40 ;
+wire \counter[8]~41_combout ;
+wire \counter[8]~42 ;
+wire \counter[9]~43_combout ;
+wire \counter[9]~44 ;
+wire \counter[10]~45_combout ;
+wire \counter[10]~46 ;
+wire \counter[11]~47_combout ;
+wire \counter[11]~48 ;
+wire \counter[12]~49_combout ;
+wire \counter[12]~50 ;
+wire \counter[13]~51_combout ;
+wire \counter[13]~52 ;
+wire \counter[14]~53_combout ;
+wire \counter[14]~54 ;
+wire \counter[15]~55_combout ;
+wire \counter[15]~56 ;
+wire \counter[16]~57_combout ;
+wire \counter[16]~58 ;
+wire \counter[17]~59_combout ;
+wire \counter[17]~60 ;
+wire \counter[18]~61_combout ;
+wire \counter[18]~62 ;
+wire \counter[19]~63_combout ;
+wire \counter[19]~64 ;
+wire \counter[20]~65_combout ;
+wire \counter[20]~66 ;
+wire \counter[21]~67_combout ;
+wire \LED[0]~reg0feeder_combout ;
+wire \LED[0]~reg0_q ;
+wire \counter[21]~68 ;
+wire \counter[22]~69_combout ;
+wire \LED[1]~reg0feeder_combout ;
+wire \LED[1]~reg0_q ;
+wire \counter[22]~70 ;
+wire \counter[23]~71_combout ;
+wire \LED[2]~reg0feeder_combout ;
+wire \LED[2]~reg0_q ;
+wire \counter[23]~72 ;
+wire \counter[24]~73_combout ;
+wire \LED[3]~reg0feeder_combout ;
+wire \LED[3]~reg0_q ;
+wire \counter[24]~74 ;
+wire \counter[25]~75_combout ;
+wire \LED[4]~reg0feeder_combout ;
+wire \LED[4]~reg0_q ;
+wire \counter[25]~76 ;
+wire \counter[26]~77_combout ;
+wire \LED[5]~reg0feeder_combout ;
+wire \LED[5]~reg0_q ;
+wire \counter[26]~78 ;
+wire \counter[27]~79_combout ;
+wire \LED[6]~reg0feeder_combout ;
+wire \LED[6]~reg0_q ;
+wire [27:0] counter;
+
+
+// Location: IOOBUF_X38_Y34_N16
+cycloneive_io_obuf \LED[0]~output (
+	.i(\LED[0]~reg0_q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LED[0]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LED[0]~output .bus_hold = "false";
+defparam \LED[0]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X49_Y34_N2
+cycloneive_io_obuf \LED[1]~output (
+	.i(\LED[1]~reg0_q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LED[1]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LED[1]~output .bus_hold = "false";
+defparam \LED[1]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X49_Y34_N9
+cycloneive_io_obuf \LED[2]~output (
+	.i(\LED[2]~reg0_q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LED[2]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LED[2]~output .bus_hold = "false";
+defparam \LED[2]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X40_Y34_N2
+cycloneive_io_obuf \LED[3]~output (
+	.i(\LED[3]~reg0_q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LED[3]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LED[3]~output .bus_hold = "false";
+defparam \LED[3]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y25_N9
+cycloneive_io_obuf \LED[4]~output (
+	.i(\LED[4]~reg0_q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LED[4]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LED[4]~output .bus_hold = "false";
+defparam \LED[4]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y26_N16
+cycloneive_io_obuf \LED[5]~output (
+	.i(\LED[5]~reg0_q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LED[5]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LED[5]~output .bus_hold = "false";
+defparam \LED[5]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y28_N9
+cycloneive_io_obuf \LED[6]~output (
+	.i(\LED[6]~reg0_q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LED[6]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LED[6]~output .bus_hold = "false";
+defparam \LED[6]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y10_N23
+cycloneive_io_obuf \LED[7]~output (
+	.i(gnd),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LED[7]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LED[7]~output .bus_hold = "false";
+defparam \LED[7]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOIBUF_X27_Y0_N22
+cycloneive_io_ibuf \CLOCK_50~input (
+	.i(CLOCK_50),
+	.ibar(gnd),
+	.o(\CLOCK_50~input_o ));
+// synopsys translate_off
+defparam \CLOCK_50~input .bus_hold = "false";
+defparam \CLOCK_50~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: CLKCTRL_G18
+cycloneive_clkctrl \CLOCK_50~inputclkctrl (
+	.ena(vcc),
+	.inclk({vcc,vcc,vcc,\CLOCK_50~input_o }),
+	.clkselect(2'b00),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.outclk(\CLOCK_50~inputclkctrl_outclk ));
+// synopsys translate_off
+defparam \CLOCK_50~inputclkctrl .clock_type = "global clock";
+defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N4
+cycloneive_lcell_comb \counter[0]~81 (
+// Equation(s):
+// \counter[0]~81_combout  = !counter[0]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(counter[0]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\counter[0]~81_combout ),
+	.cout());
+// synopsys translate_off
+defparam \counter[0]~81 .lut_mask = 16'h0F0F;
+defparam \counter[0]~81 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N5
+dffeas \counter[0] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[0]~81_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[0] .is_wysiwyg = "true";
+defparam \counter[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N6
+cycloneive_lcell_comb \counter[1]~27 (
+// Equation(s):
+// \counter[1]~27_combout  = (counter[1] & (counter[0] $ (VCC))) # (!counter[1] & (counter[0] & VCC))
+// \counter[1]~28  = CARRY((counter[1] & counter[0]))
+
+	.dataa(counter[1]),
+	.datab(counter[0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\counter[1]~27_combout ),
+	.cout(\counter[1]~28 ));
+// synopsys translate_off
+defparam \counter[1]~27 .lut_mask = 16'h6688;
+defparam \counter[1]~27 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N7
+dffeas \counter[1] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[1]~27_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[1] .is_wysiwyg = "true";
+defparam \counter[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N8
+cycloneive_lcell_comb \counter[2]~29 (
+// Equation(s):
+// \counter[2]~29_combout  = (counter[2] & (!\counter[1]~28 )) # (!counter[2] & ((\counter[1]~28 ) # (GND)))
+// \counter[2]~30  = CARRY((!\counter[1]~28 ) # (!counter[2]))
+
+	.dataa(gnd),
+	.datab(counter[2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[1]~28 ),
+	.combout(\counter[2]~29_combout ),
+	.cout(\counter[2]~30 ));
+// synopsys translate_off
+defparam \counter[2]~29 .lut_mask = 16'h3C3F;
+defparam \counter[2]~29 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N9
+dffeas \counter[2] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[2]~29_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[2] .is_wysiwyg = "true";
+defparam \counter[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N10
+cycloneive_lcell_comb \counter[3]~31 (
+// Equation(s):
+// \counter[3]~31_combout  = (counter[3] & (\counter[2]~30  $ (GND))) # (!counter[3] & (!\counter[2]~30  & VCC))
+// \counter[3]~32  = CARRY((counter[3] & !\counter[2]~30 ))
+
+	.dataa(counter[3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[2]~30 ),
+	.combout(\counter[3]~31_combout ),
+	.cout(\counter[3]~32 ));
+// synopsys translate_off
+defparam \counter[3]~31 .lut_mask = 16'hA50A;
+defparam \counter[3]~31 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N11
+dffeas \counter[3] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[3]~31_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[3] .is_wysiwyg = "true";
+defparam \counter[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N12
+cycloneive_lcell_comb \counter[4]~33 (
+// Equation(s):
+// \counter[4]~33_combout  = (counter[4] & (!\counter[3]~32 )) # (!counter[4] & ((\counter[3]~32 ) # (GND)))
+// \counter[4]~34  = CARRY((!\counter[3]~32 ) # (!counter[4]))
+
+	.dataa(counter[4]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[3]~32 ),
+	.combout(\counter[4]~33_combout ),
+	.cout(\counter[4]~34 ));
+// synopsys translate_off
+defparam \counter[4]~33 .lut_mask = 16'h5A5F;
+defparam \counter[4]~33 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N13
+dffeas \counter[4] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[4]~33_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[4] .is_wysiwyg = "true";
+defparam \counter[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N14
+cycloneive_lcell_comb \counter[5]~35 (
+// Equation(s):
+// \counter[5]~35_combout  = (counter[5] & (\counter[4]~34  $ (GND))) # (!counter[5] & (!\counter[4]~34  & VCC))
+// \counter[5]~36  = CARRY((counter[5] & !\counter[4]~34 ))
+
+	.dataa(gnd),
+	.datab(counter[5]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[4]~34 ),
+	.combout(\counter[5]~35_combout ),
+	.cout(\counter[5]~36 ));
+// synopsys translate_off
+defparam \counter[5]~35 .lut_mask = 16'hC30C;
+defparam \counter[5]~35 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N15
+dffeas \counter[5] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[5]~35_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[5] .is_wysiwyg = "true";
+defparam \counter[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N16
+cycloneive_lcell_comb \counter[6]~37 (
+// Equation(s):
+// \counter[6]~37_combout  = (counter[6] & (!\counter[5]~36 )) # (!counter[6] & ((\counter[5]~36 ) # (GND)))
+// \counter[6]~38  = CARRY((!\counter[5]~36 ) # (!counter[6]))
+
+	.dataa(gnd),
+	.datab(counter[6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[5]~36 ),
+	.combout(\counter[6]~37_combout ),
+	.cout(\counter[6]~38 ));
+// synopsys translate_off
+defparam \counter[6]~37 .lut_mask = 16'h3C3F;
+defparam \counter[6]~37 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N17
+dffeas \counter[6] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[6]~37_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[6] .is_wysiwyg = "true";
+defparam \counter[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N18
+cycloneive_lcell_comb \counter[7]~39 (
+// Equation(s):
+// \counter[7]~39_combout  = (counter[7] & (\counter[6]~38  $ (GND))) # (!counter[7] & (!\counter[6]~38  & VCC))
+// \counter[7]~40  = CARRY((counter[7] & !\counter[6]~38 ))
+
+	.dataa(gnd),
+	.datab(counter[7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[6]~38 ),
+	.combout(\counter[7]~39_combout ),
+	.cout(\counter[7]~40 ));
+// synopsys translate_off
+defparam \counter[7]~39 .lut_mask = 16'hC30C;
+defparam \counter[7]~39 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N19
+dffeas \counter[7] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[7]~39_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[7] .is_wysiwyg = "true";
+defparam \counter[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N20
+cycloneive_lcell_comb \counter[8]~41 (
+// Equation(s):
+// \counter[8]~41_combout  = (counter[8] & (!\counter[7]~40 )) # (!counter[8] & ((\counter[7]~40 ) # (GND)))
+// \counter[8]~42  = CARRY((!\counter[7]~40 ) # (!counter[8]))
+
+	.dataa(gnd),
+	.datab(counter[8]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[7]~40 ),
+	.combout(\counter[8]~41_combout ),
+	.cout(\counter[8]~42 ));
+// synopsys translate_off
+defparam \counter[8]~41 .lut_mask = 16'h3C3F;
+defparam \counter[8]~41 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N21
+dffeas \counter[8] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[8]~41_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[8] .is_wysiwyg = "true";
+defparam \counter[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N22
+cycloneive_lcell_comb \counter[9]~43 (
+// Equation(s):
+// \counter[9]~43_combout  = (counter[9] & (\counter[8]~42  $ (GND))) # (!counter[9] & (!\counter[8]~42  & VCC))
+// \counter[9]~44  = CARRY((counter[9] & !\counter[8]~42 ))
+
+	.dataa(counter[9]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[8]~42 ),
+	.combout(\counter[9]~43_combout ),
+	.cout(\counter[9]~44 ));
+// synopsys translate_off
+defparam \counter[9]~43 .lut_mask = 16'hA50A;
+defparam \counter[9]~43 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N23
+dffeas \counter[9] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[9]~43_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[9] .is_wysiwyg = "true";
+defparam \counter[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N24
+cycloneive_lcell_comb \counter[10]~45 (
+// Equation(s):
+// \counter[10]~45_combout  = (counter[10] & (!\counter[9]~44 )) # (!counter[10] & ((\counter[9]~44 ) # (GND)))
+// \counter[10]~46  = CARRY((!\counter[9]~44 ) # (!counter[10]))
+
+	.dataa(gnd),
+	.datab(counter[10]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[9]~44 ),
+	.combout(\counter[10]~45_combout ),
+	.cout(\counter[10]~46 ));
+// synopsys translate_off
+defparam \counter[10]~45 .lut_mask = 16'h3C3F;
+defparam \counter[10]~45 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N25
+dffeas \counter[10] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[10]~45_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[10] .is_wysiwyg = "true";
+defparam \counter[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N26
+cycloneive_lcell_comb \counter[11]~47 (
+// Equation(s):
+// \counter[11]~47_combout  = (counter[11] & (\counter[10]~46  $ (GND))) # (!counter[11] & (!\counter[10]~46  & VCC))
+// \counter[11]~48  = CARRY((counter[11] & !\counter[10]~46 ))
+
+	.dataa(counter[11]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[10]~46 ),
+	.combout(\counter[11]~47_combout ),
+	.cout(\counter[11]~48 ));
+// synopsys translate_off
+defparam \counter[11]~47 .lut_mask = 16'hA50A;
+defparam \counter[11]~47 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N27
+dffeas \counter[11] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[11]~47_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[11] .is_wysiwyg = "true";
+defparam \counter[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N28
+cycloneive_lcell_comb \counter[12]~49 (
+// Equation(s):
+// \counter[12]~49_combout  = (counter[12] & (!\counter[11]~48 )) # (!counter[12] & ((\counter[11]~48 ) # (GND)))
+// \counter[12]~50  = CARRY((!\counter[11]~48 ) # (!counter[12]))
+
+	.dataa(gnd),
+	.datab(counter[12]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[11]~48 ),
+	.combout(\counter[12]~49_combout ),
+	.cout(\counter[12]~50 ));
+// synopsys translate_off
+defparam \counter[12]~49 .lut_mask = 16'h3C3F;
+defparam \counter[12]~49 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N29
+dffeas \counter[12] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[12]~49_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[12] .is_wysiwyg = "true";
+defparam \counter[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N30
+cycloneive_lcell_comb \counter[13]~51 (
+// Equation(s):
+// \counter[13]~51_combout  = (counter[13] & (\counter[12]~50  $ (GND))) # (!counter[13] & (!\counter[12]~50  & VCC))
+// \counter[13]~52  = CARRY((counter[13] & !\counter[12]~50 ))
+
+	.dataa(counter[13]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[12]~50 ),
+	.combout(\counter[13]~51_combout ),
+	.cout(\counter[13]~52 ));
+// synopsys translate_off
+defparam \counter[13]~51 .lut_mask = 16'hA50A;
+defparam \counter[13]~51 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N31
+dffeas \counter[13] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[13]~51_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[13]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[13] .is_wysiwyg = "true";
+defparam \counter[13] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N0
+cycloneive_lcell_comb \counter[14]~53 (
+// Equation(s):
+// \counter[14]~53_combout  = (counter[14] & (!\counter[13]~52 )) # (!counter[14] & ((\counter[13]~52 ) # (GND)))
+// \counter[14]~54  = CARRY((!\counter[13]~52 ) # (!counter[14]))
+
+	.dataa(gnd),
+	.datab(counter[14]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[13]~52 ),
+	.combout(\counter[14]~53_combout ),
+	.cout(\counter[14]~54 ));
+// synopsys translate_off
+defparam \counter[14]~53 .lut_mask = 16'h3C3F;
+defparam \counter[14]~53 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N1
+dffeas \counter[14] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[14]~53_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[14]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[14] .is_wysiwyg = "true";
+defparam \counter[14] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N2
+cycloneive_lcell_comb \counter[15]~55 (
+// Equation(s):
+// \counter[15]~55_combout  = (counter[15] & (\counter[14]~54  $ (GND))) # (!counter[15] & (!\counter[14]~54  & VCC))
+// \counter[15]~56  = CARRY((counter[15] & !\counter[14]~54 ))
+
+	.dataa(gnd),
+	.datab(counter[15]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[14]~54 ),
+	.combout(\counter[15]~55_combout ),
+	.cout(\counter[15]~56 ));
+// synopsys translate_off
+defparam \counter[15]~55 .lut_mask = 16'hC30C;
+defparam \counter[15]~55 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N3
+dffeas \counter[15] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[15]~55_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[15]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[15] .is_wysiwyg = "true";
+defparam \counter[15] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N4
+cycloneive_lcell_comb \counter[16]~57 (
+// Equation(s):
+// \counter[16]~57_combout  = (counter[16] & (!\counter[15]~56 )) # (!counter[16] & ((\counter[15]~56 ) # (GND)))
+// \counter[16]~58  = CARRY((!\counter[15]~56 ) # (!counter[16]))
+
+	.dataa(gnd),
+	.datab(counter[16]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[15]~56 ),
+	.combout(\counter[16]~57_combout ),
+	.cout(\counter[16]~58 ));
+// synopsys translate_off
+defparam \counter[16]~57 .lut_mask = 16'h3C3F;
+defparam \counter[16]~57 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N5
+dffeas \counter[16] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[16]~57_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[16]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[16] .is_wysiwyg = "true";
+defparam \counter[16] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N6
+cycloneive_lcell_comb \counter[17]~59 (
+// Equation(s):
+// \counter[17]~59_combout  = (counter[17] & (\counter[16]~58  $ (GND))) # (!counter[17] & (!\counter[16]~58  & VCC))
+// \counter[17]~60  = CARRY((counter[17] & !\counter[16]~58 ))
+
+	.dataa(counter[17]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[16]~58 ),
+	.combout(\counter[17]~59_combout ),
+	.cout(\counter[17]~60 ));
+// synopsys translate_off
+defparam \counter[17]~59 .lut_mask = 16'hA50A;
+defparam \counter[17]~59 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N7
+dffeas \counter[17] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[17]~59_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[17]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[17] .is_wysiwyg = "true";
+defparam \counter[17] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N8
+cycloneive_lcell_comb \counter[18]~61 (
+// Equation(s):
+// \counter[18]~61_combout  = (counter[18] & (!\counter[17]~60 )) # (!counter[18] & ((\counter[17]~60 ) # (GND)))
+// \counter[18]~62  = CARRY((!\counter[17]~60 ) # (!counter[18]))
+
+	.dataa(gnd),
+	.datab(counter[18]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[17]~60 ),
+	.combout(\counter[18]~61_combout ),
+	.cout(\counter[18]~62 ));
+// synopsys translate_off
+defparam \counter[18]~61 .lut_mask = 16'h3C3F;
+defparam \counter[18]~61 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N9
+dffeas \counter[18] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[18]~61_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[18]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[18] .is_wysiwyg = "true";
+defparam \counter[18] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N10
+cycloneive_lcell_comb \counter[19]~63 (
+// Equation(s):
+// \counter[19]~63_combout  = (counter[19] & (\counter[18]~62  $ (GND))) # (!counter[19] & (!\counter[18]~62  & VCC))
+// \counter[19]~64  = CARRY((counter[19] & !\counter[18]~62 ))
+
+	.dataa(counter[19]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[18]~62 ),
+	.combout(\counter[19]~63_combout ),
+	.cout(\counter[19]~64 ));
+// synopsys translate_off
+defparam \counter[19]~63 .lut_mask = 16'hA50A;
+defparam \counter[19]~63 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N11
+dffeas \counter[19] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[19]~63_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[19]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[19] .is_wysiwyg = "true";
+defparam \counter[19] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N12
+cycloneive_lcell_comb \counter[20]~65 (
+// Equation(s):
+// \counter[20]~65_combout  = (counter[20] & (!\counter[19]~64 )) # (!counter[20] & ((\counter[19]~64 ) # (GND)))
+// \counter[20]~66  = CARRY((!\counter[19]~64 ) # (!counter[20]))
+
+	.dataa(counter[20]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[19]~64 ),
+	.combout(\counter[20]~65_combout ),
+	.cout(\counter[20]~66 ));
+// synopsys translate_off
+defparam \counter[20]~65 .lut_mask = 16'h5A5F;
+defparam \counter[20]~65 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N13
+dffeas \counter[20] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[20]~65_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[20]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[20] .is_wysiwyg = "true";
+defparam \counter[20] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N14
+cycloneive_lcell_comb \counter[21]~67 (
+// Equation(s):
+// \counter[21]~67_combout  = (counter[21] & (\counter[20]~66  $ (GND))) # (!counter[21] & (!\counter[20]~66  & VCC))
+// \counter[21]~68  = CARRY((counter[21] & !\counter[20]~66 ))
+
+	.dataa(gnd),
+	.datab(counter[21]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[20]~66 ),
+	.combout(\counter[21]~67_combout ),
+	.cout(\counter[21]~68 ));
+// synopsys translate_off
+defparam \counter[21]~67 .lut_mask = 16'hC30C;
+defparam \counter[21]~67 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N15
+dffeas \counter[21] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[21]~67_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[21]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[21] .is_wysiwyg = "true";
+defparam \counter[21] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X38_Y32_N4
+cycloneive_lcell_comb \LED[0]~reg0feeder (
+// Equation(s):
+// \LED[0]~reg0feeder_combout  = counter[21]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(counter[21]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\LED[0]~reg0feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \LED[0]~reg0feeder .lut_mask = 16'hF0F0;
+defparam \LED[0]~reg0feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X38_Y32_N5
+dffeas \LED[0]~reg0 (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\LED[0]~reg0feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\LED[0]~reg0_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \LED[0]~reg0 .is_wysiwyg = "true";
+defparam \LED[0]~reg0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N16
+cycloneive_lcell_comb \counter[22]~69 (
+// Equation(s):
+// \counter[22]~69_combout  = (counter[22] & (!\counter[21]~68 )) # (!counter[22] & ((\counter[21]~68 ) # (GND)))
+// \counter[22]~70  = CARRY((!\counter[21]~68 ) # (!counter[22]))
+
+	.dataa(gnd),
+	.datab(counter[22]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[21]~68 ),
+	.combout(\counter[22]~69_combout ),
+	.cout(\counter[22]~70 ));
+// synopsys translate_off
+defparam \counter[22]~69 .lut_mask = 16'h3C3F;
+defparam \counter[22]~69 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N17
+dffeas \counter[22] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[22]~69_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[22]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[22] .is_wysiwyg = "true";
+defparam \counter[22] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X46_Y32_N12
+cycloneive_lcell_comb \LED[1]~reg0feeder (
+// Equation(s):
+// \LED[1]~reg0feeder_combout  = counter[22]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(counter[22]),
+	.cin(gnd),
+	.combout(\LED[1]~reg0feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \LED[1]~reg0feeder .lut_mask = 16'hFF00;
+defparam \LED[1]~reg0feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X46_Y32_N13
+dffeas \LED[1]~reg0 (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\LED[1]~reg0feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\LED[1]~reg0_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \LED[1]~reg0 .is_wysiwyg = "true";
+defparam \LED[1]~reg0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N18
+cycloneive_lcell_comb \counter[23]~71 (
+// Equation(s):
+// \counter[23]~71_combout  = (counter[23] & (\counter[22]~70  $ (GND))) # (!counter[23] & (!\counter[22]~70  & VCC))
+// \counter[23]~72  = CARRY((counter[23] & !\counter[22]~70 ))
+
+	.dataa(gnd),
+	.datab(counter[23]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[22]~70 ),
+	.combout(\counter[23]~71_combout ),
+	.cout(\counter[23]~72 ));
+// synopsys translate_off
+defparam \counter[23]~71 .lut_mask = 16'hC30C;
+defparam \counter[23]~71 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N19
+dffeas \counter[23] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[23]~71_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[23]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[23] .is_wysiwyg = "true";
+defparam \counter[23] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X46_Y32_N6
+cycloneive_lcell_comb \LED[2]~reg0feeder (
+// Equation(s):
+// \LED[2]~reg0feeder_combout  = counter[23]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(counter[23]),
+	.cin(gnd),
+	.combout(\LED[2]~reg0feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \LED[2]~reg0feeder .lut_mask = 16'hFF00;
+defparam \LED[2]~reg0feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X46_Y32_N7
+dffeas \LED[2]~reg0 (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\LED[2]~reg0feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\LED[2]~reg0_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \LED[2]~reg0 .is_wysiwyg = "true";
+defparam \LED[2]~reg0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N20
+cycloneive_lcell_comb \counter[24]~73 (
+// Equation(s):
+// \counter[24]~73_combout  = (counter[24] & (!\counter[23]~72 )) # (!counter[24] & ((\counter[23]~72 ) # (GND)))
+// \counter[24]~74  = CARRY((!\counter[23]~72 ) # (!counter[24]))
+
+	.dataa(gnd),
+	.datab(counter[24]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[23]~72 ),
+	.combout(\counter[24]~73_combout ),
+	.cout(\counter[24]~74 ));
+// synopsys translate_off
+defparam \counter[24]~73 .lut_mask = 16'h3C3F;
+defparam \counter[24]~73 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N21
+dffeas \counter[24] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[24]~73_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[24]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[24] .is_wysiwyg = "true";
+defparam \counter[24] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X40_Y32_N4
+cycloneive_lcell_comb \LED[3]~reg0feeder (
+// Equation(s):
+// \LED[3]~reg0feeder_combout  = counter[24]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(counter[24]),
+	.cin(gnd),
+	.combout(\LED[3]~reg0feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \LED[3]~reg0feeder .lut_mask = 16'hFF00;
+defparam \LED[3]~reg0feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X40_Y32_N5
+dffeas \LED[3]~reg0 (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\LED[3]~reg0feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\LED[3]~reg0_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \LED[3]~reg0 .is_wysiwyg = "true";
+defparam \LED[3]~reg0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N22
+cycloneive_lcell_comb \counter[25]~75 (
+// Equation(s):
+// \counter[25]~75_combout  = (counter[25] & (\counter[24]~74  $ (GND))) # (!counter[25] & (!\counter[24]~74  & VCC))
+// \counter[25]~76  = CARRY((counter[25] & !\counter[24]~74 ))
+
+	.dataa(counter[25]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[24]~74 ),
+	.combout(\counter[25]~75_combout ),
+	.cout(\counter[25]~76 ));
+// synopsys translate_off
+defparam \counter[25]~75 .lut_mask = 16'hA50A;
+defparam \counter[25]~75 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N23
+dffeas \counter[25] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[25]~75_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[25]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[25] .is_wysiwyg = "true";
+defparam \counter[25] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X38_Y32_N18
+cycloneive_lcell_comb \LED[4]~reg0feeder (
+// Equation(s):
+// \LED[4]~reg0feeder_combout  = counter[25]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(counter[25]),
+	.cin(gnd),
+	.combout(\LED[4]~reg0feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \LED[4]~reg0feeder .lut_mask = 16'hFF00;
+defparam \LED[4]~reg0feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X38_Y32_N19
+dffeas \LED[4]~reg0 (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\LED[4]~reg0feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\LED[4]~reg0_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \LED[4]~reg0 .is_wysiwyg = "true";
+defparam \LED[4]~reg0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N24
+cycloneive_lcell_comb \counter[26]~77 (
+// Equation(s):
+// \counter[26]~77_combout  = (counter[26] & (!\counter[25]~76 )) # (!counter[26] & ((\counter[25]~76 ) # (GND)))
+// \counter[26]~78  = CARRY((!\counter[25]~76 ) # (!counter[26]))
+
+	.dataa(gnd),
+	.datab(counter[26]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[25]~76 ),
+	.combout(\counter[26]~77_combout ),
+	.cout(\counter[26]~78 ));
+// synopsys translate_off
+defparam \counter[26]~77 .lut_mask = 16'h3C3F;
+defparam \counter[26]~77 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N25
+dffeas \counter[26] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[26]~77_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[26]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[26] .is_wysiwyg = "true";
+defparam \counter[26] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X38_Y32_N24
+cycloneive_lcell_comb \LED[5]~reg0feeder (
+// Equation(s):
+// \LED[5]~reg0feeder_combout  = counter[26]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(counter[26]),
+	.cin(gnd),
+	.combout(\LED[5]~reg0feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \LED[5]~reg0feeder .lut_mask = 16'hFF00;
+defparam \LED[5]~reg0feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X38_Y32_N25
+dffeas \LED[5]~reg0 (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\LED[5]~reg0feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\LED[5]~reg0_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \LED[5]~reg0 .is_wysiwyg = "true";
+defparam \LED[5]~reg0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N26
+cycloneive_lcell_comb \counter[27]~79 (
+// Equation(s):
+// \counter[27]~79_combout  = counter[27] $ (!\counter[26]~78 )
+
+	.dataa(counter[27]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\counter[26]~78 ),
+	.combout(\counter[27]~79_combout ),
+	.cout());
+// synopsys translate_off
+defparam \counter[27]~79 .lut_mask = 16'hA5A5;
+defparam \counter[27]~79 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N27
+dffeas \counter[27] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[27]~79_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[27]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[27] .is_wysiwyg = "true";
+defparam \counter[27] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X38_Y32_N14
+cycloneive_lcell_comb \LED[6]~reg0feeder (
+// Equation(s):
+// \LED[6]~reg0feeder_combout  = counter[27]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(counter[27]),
+	.cin(gnd),
+	.combout(\LED[6]~reg0feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \LED[6]~reg0feeder .lut_mask = 16'hFF00;
+defparam \LED[6]~reg0feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X38_Y32_N15
+dffeas \LED[6]~reg0 (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\LED[6]~reg0feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\LED[6]~reg0_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \LED[6]~reg0 .is_wysiwyg = "true";
+defparam \LED[6]~reg0 .power_up = "low";
+// synopsys translate_on
+
+assign LED[0] = \LED[0]~output_o ;
+
+assign LED[1] = \LED[1]~output_o ;
+
+assign LED[2] = \LED[2]~output_o ;
+
+assign LED[3] = \LED[3]~output_o ;
+
+assign LED[4] = \LED[4]~output_o ;
+
+assign LED[5] = \LED[5]~output_o ;
+
+assign LED[6] = \LED[6]~output_o ;
+
+assign LED[7] = \LED[7]~output_o ;
+
+endmodule
diff --git a/simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo b/simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo
new file mode 100644
index 0000000..e97f726
--- /dev/null
+++ b/simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo
@@ -0,0 +1,1072 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP4CE22F17C6 Package FBGA256
+// 
+
+//
+// This file contains Slow Corner delays for the design using part EP4CE22F17C6,
+// with speed grade 6, core voltage 1.2V, and temperature 85 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (Verilog) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "spectrum")
+  (DATE "03/30/2022 11:51:43")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 32-bit")
+  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneive_io_obuf")
+    (INSTANCE LED\[0\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (513:513:513) (544:544:544))
+        (IOPATH i o (2535:2535:2535) (2445:2445:2445))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_obuf")
+    (INSTANCE LED\[1\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (754:754:754) (771:771:771))
+        (IOPATH i o (2535:2535:2535) (2445:2445:2445))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_obuf")
+    (INSTANCE LED\[2\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (734:734:734) (751:751:751))
+        (IOPATH i o (2535:2535:2535) (2445:2445:2445))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_obuf")
+    (INSTANCE LED\[3\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (512:512:512) (543:543:543))
+        (IOPATH i o (2535:2535:2535) (2445:2445:2445))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_obuf")
+    (INSTANCE LED\[4\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (2451:2451:2451) (2550:2550:2550))
+        (IOPATH i o (2582:2582:2582) (2502:2502:2502))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_obuf")
+    (INSTANCE LED\[5\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (2441:2441:2441) (2543:2543:2543))
+        (IOPATH i o (4477:4477:4477) (4127:4127:4127))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_obuf")
+    (INSTANCE LED\[6\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1301:1301:1301) (1440:1440:1440))
+        (IOPATH i o (2455:2455:2455) (2378:2378:2378))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_ibuf")
+    (INSTANCE CLOCK_50\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (479:479:479) (732:732:732))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_clkctrl")
+    (INSTANCE CLOCK_50\~inputclkctrl)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (154:154:154) (138:138:138))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[0\]\~81)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH datac combout (353:353:353) (369:369:369))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1533:1533:1533) (1545:1545:1545))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[1\]\~27)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (243:243:243) (329:329:329))
+        (PORT datab (241:241:241) (323:323:323))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1533:1533:1533) (1545:1545:1545))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[2\]\~29)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (242:242:242) (323:323:323))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1533:1533:1533) (1545:1545:1545))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[3\]\~31)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (244:244:244) (331:331:331))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1533:1533:1533) (1545:1545:1545))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[4\]\~33)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (244:244:244) (331:331:331))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1533:1533:1533) (1545:1545:1545))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[5\]\~35)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (242:242:242) (325:325:325))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1533:1533:1533) (1545:1545:1545))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[6\]\~37)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (242:242:242) (325:325:325))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1533:1533:1533) (1545:1545:1545))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[7\]\~39)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (242:242:242) (325:325:325))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1533:1533:1533) (1545:1545:1545))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[8\]\~41)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (242:242:242) (325:325:325))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1533:1533:1533) (1545:1545:1545))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[9\]\~43)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (244:244:244) (330:330:330))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1533:1533:1533) (1545:1545:1545))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[10\]\~45)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (242:242:242) (323:323:323))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1533:1533:1533) (1545:1545:1545))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[11\]\~47)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (243:243:243) (329:329:329))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1533:1533:1533) (1545:1545:1545))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[12\]\~49)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (241:241:241) (323:323:323))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[12\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1533:1533:1533) (1545:1545:1545))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[13\]\~51)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (243:243:243) (329:329:329))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[13\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1898:1898:1898) (1920:1920:1920))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[14\]\~53)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (240:240:240) (322:322:322))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[14\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1532:1532:1532) (1545:1545:1545))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[15\]\~55)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (241:241:241) (323:323:323))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[15\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1532:1532:1532) (1545:1545:1545))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[16\]\~57)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (241:241:241) (323:323:323))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[16\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1532:1532:1532) (1545:1545:1545))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[17\]\~59)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (244:244:244) (330:330:330))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[17\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1898:1898:1898) (1920:1920:1920))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[18\]\~61)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (243:243:243) (324:324:324))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[18\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1898:1898:1898) (1920:1920:1920))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[19\]\~63)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (245:245:245) (333:333:333))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[19\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1898:1898:1898) (1920:1920:1920))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[20\]\~65)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (245:245:245) (332:332:332))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[20\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1898:1898:1898) (1920:1920:1920))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[21\]\~67)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (264:264:264) (347:347:347))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[21\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1898:1898:1898) (1920:1920:1920))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE LED\[0\]\~reg0feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (411:411:411) (472:472:472))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE LED\[0\]\~reg0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1532:1532:1532) (1544:1544:1544))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[22\]\~69)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (264:264:264) (347:347:347))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[22\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1898:1898:1898) (1920:1920:1920))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE LED\[1\]\~reg0feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (808:808:808) (843:843:843))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE LED\[1\]\~reg0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1538:1538:1538) (1550:1550:1550))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[23\]\~71)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (264:264:264) (347:347:347))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[23\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1898:1898:1898) (1920:1920:1920))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE LED\[2\]\~reg0feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (771:771:771) (813:813:813))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE LED\[2\]\~reg0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1538:1538:1538) (1550:1550:1550))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[24\]\~73)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (264:264:264) (347:347:347))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[24\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1898:1898:1898) (1920:1920:1920))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE LED\[3\]\~reg0feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (399:399:399) (452:452:452))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE LED\[3\]\~reg0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1533:1533:1533) (1545:1545:1545))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[25\]\~75)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (266:266:266) (352:352:352))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[25\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1898:1898:1898) (1920:1920:1920))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE LED\[4\]\~reg0feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (404:404:404) (467:467:467))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE LED\[4\]\~reg0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1532:1532:1532) (1544:1544:1544))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[26\]\~77)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (263:263:263) (345:345:345))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[26\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1898:1898:1898) (1920:1920:1920))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE LED\[5\]\~reg0feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (610:610:610) (670:670:670))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE LED\[5\]\~reg0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1532:1532:1532) (1544:1544:1544))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[27\]\~79)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (266:266:266) (353:353:353))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[27\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1898:1898:1898) (1920:1920:1920))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE LED\[6\]\~reg0feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (406:406:406) (467:467:467))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE LED\[6\]\~reg0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1532:1532:1532) (1544:1544:1544))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+)
diff --git a/simulation/modelsim/spectrum_min_1200mv_0c_fast.vo b/simulation/modelsim/spectrum_min_1200mv_0c_fast.vo
new file mode 100644
index 0000000..25a614c
--- /dev/null
+++ b/simulation/modelsim/spectrum_min_1200mv_0c_fast.vo
@@ -0,0 +1,1574 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+// VENDOR "Altera"
+// PROGRAM "Quartus II 32-bit"
+// VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+// DATE "03/30/2022 11:51:43"
+
+// 
+// Device: Altera EP4CE22F17C6 Package FBGA256
+// 
+
+// 
+// This Verilog file should be used for ModelSim-Altera (Verilog) only
+// 
+
+`timescale 1 ps/ 1 ps
+
+module spectrum (
+	CLOCK_50,
+	LED);
+input 	CLOCK_50;
+output 	[7:0] LED;
+
+// Design Ports Information
+// LED[0]	=>  Location: PIN_A15,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LED[1]	=>  Location: PIN_A13,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LED[2]	=>  Location: PIN_B13,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LED[3]	=>  Location: PIN_A11,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LED[4]	=>  Location: PIN_D1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LED[5]	=>  Location: PIN_F3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LED[6]	=>  Location: PIN_B1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// LED[7]	=>  Location: PIN_L3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
+// CLOCK_50	=>  Location: PIN_R8,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+
+
+wire gnd;
+wire vcc;
+wire unknown;
+
+assign gnd = 1'b0;
+assign vcc = 1'b1;
+assign unknown = 1'bx;
+
+tri1 devclrn;
+tri1 devpor;
+tri1 devoe;
+// synopsys translate_off
+initial $sdf_annotate("spectrum_min_1200mv_0c_v_fast.sdo");
+// synopsys translate_on
+
+wire \LED[0]~output_o ;
+wire \LED[1]~output_o ;
+wire \LED[2]~output_o ;
+wire \LED[3]~output_o ;
+wire \LED[4]~output_o ;
+wire \LED[5]~output_o ;
+wire \LED[6]~output_o ;
+wire \LED[7]~output_o ;
+wire \CLOCK_50~input_o ;
+wire \CLOCK_50~inputclkctrl_outclk ;
+wire \counter[0]~81_combout ;
+wire \counter[1]~27_combout ;
+wire \counter[1]~28 ;
+wire \counter[2]~29_combout ;
+wire \counter[2]~30 ;
+wire \counter[3]~31_combout ;
+wire \counter[3]~32 ;
+wire \counter[4]~33_combout ;
+wire \counter[4]~34 ;
+wire \counter[5]~35_combout ;
+wire \counter[5]~36 ;
+wire \counter[6]~37_combout ;
+wire \counter[6]~38 ;
+wire \counter[7]~39_combout ;
+wire \counter[7]~40 ;
+wire \counter[8]~41_combout ;
+wire \counter[8]~42 ;
+wire \counter[9]~43_combout ;
+wire \counter[9]~44 ;
+wire \counter[10]~45_combout ;
+wire \counter[10]~46 ;
+wire \counter[11]~47_combout ;
+wire \counter[11]~48 ;
+wire \counter[12]~49_combout ;
+wire \counter[12]~50 ;
+wire \counter[13]~51_combout ;
+wire \counter[13]~52 ;
+wire \counter[14]~53_combout ;
+wire \counter[14]~54 ;
+wire \counter[15]~55_combout ;
+wire \counter[15]~56 ;
+wire \counter[16]~57_combout ;
+wire \counter[16]~58 ;
+wire \counter[17]~59_combout ;
+wire \counter[17]~60 ;
+wire \counter[18]~61_combout ;
+wire \counter[18]~62 ;
+wire \counter[19]~63_combout ;
+wire \counter[19]~64 ;
+wire \counter[20]~65_combout ;
+wire \counter[20]~66 ;
+wire \counter[21]~67_combout ;
+wire \LED[0]~reg0feeder_combout ;
+wire \LED[0]~reg0_q ;
+wire \counter[21]~68 ;
+wire \counter[22]~69_combout ;
+wire \LED[1]~reg0feeder_combout ;
+wire \LED[1]~reg0_q ;
+wire \counter[22]~70 ;
+wire \counter[23]~71_combout ;
+wire \LED[2]~reg0feeder_combout ;
+wire \LED[2]~reg0_q ;
+wire \counter[23]~72 ;
+wire \counter[24]~73_combout ;
+wire \LED[3]~reg0feeder_combout ;
+wire \LED[3]~reg0_q ;
+wire \counter[24]~74 ;
+wire \counter[25]~75_combout ;
+wire \LED[4]~reg0feeder_combout ;
+wire \LED[4]~reg0_q ;
+wire \counter[25]~76 ;
+wire \counter[26]~77_combout ;
+wire \LED[5]~reg0feeder_combout ;
+wire \LED[5]~reg0_q ;
+wire \counter[26]~78 ;
+wire \counter[27]~79_combout ;
+wire \LED[6]~reg0feeder_combout ;
+wire \LED[6]~reg0_q ;
+wire [27:0] counter;
+
+
+// Location: IOOBUF_X38_Y34_N16
+cycloneive_io_obuf \LED[0]~output (
+	.i(\LED[0]~reg0_q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LED[0]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LED[0]~output .bus_hold = "false";
+defparam \LED[0]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X49_Y34_N2
+cycloneive_io_obuf \LED[1]~output (
+	.i(\LED[1]~reg0_q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LED[1]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LED[1]~output .bus_hold = "false";
+defparam \LED[1]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X49_Y34_N9
+cycloneive_io_obuf \LED[2]~output (
+	.i(\LED[2]~reg0_q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LED[2]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LED[2]~output .bus_hold = "false";
+defparam \LED[2]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X40_Y34_N2
+cycloneive_io_obuf \LED[3]~output (
+	.i(\LED[3]~reg0_q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LED[3]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LED[3]~output .bus_hold = "false";
+defparam \LED[3]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y25_N9
+cycloneive_io_obuf \LED[4]~output (
+	.i(\LED[4]~reg0_q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LED[4]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LED[4]~output .bus_hold = "false";
+defparam \LED[4]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y26_N16
+cycloneive_io_obuf \LED[5]~output (
+	.i(\LED[5]~reg0_q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LED[5]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LED[5]~output .bus_hold = "false";
+defparam \LED[5]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y28_N9
+cycloneive_io_obuf \LED[6]~output (
+	.i(\LED[6]~reg0_q ),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LED[6]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LED[6]~output .bus_hold = "false";
+defparam \LED[6]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOOBUF_X0_Y10_N23
+cycloneive_io_obuf \LED[7]~output (
+	.i(gnd),
+	.oe(vcc),
+	.seriesterminationcontrol(16'b0000000000000000),
+	.devoe(devoe),
+	.o(\LED[7]~output_o ),
+	.obar());
+// synopsys translate_off
+defparam \LED[7]~output .bus_hold = "false";
+defparam \LED[7]~output .open_drain_output = "false";
+// synopsys translate_on
+
+// Location: IOIBUF_X27_Y0_N22
+cycloneive_io_ibuf \CLOCK_50~input (
+	.i(CLOCK_50),
+	.ibar(gnd),
+	.o(\CLOCK_50~input_o ));
+// synopsys translate_off
+defparam \CLOCK_50~input .bus_hold = "false";
+defparam \CLOCK_50~input .simulate_z_as = "z";
+// synopsys translate_on
+
+// Location: CLKCTRL_G18
+cycloneive_clkctrl \CLOCK_50~inputclkctrl (
+	.ena(vcc),
+	.inclk({vcc,vcc,vcc,\CLOCK_50~input_o }),
+	.clkselect(2'b00),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.outclk(\CLOCK_50~inputclkctrl_outclk ));
+// synopsys translate_off
+defparam \CLOCK_50~inputclkctrl .clock_type = "global clock";
+defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N4
+cycloneive_lcell_comb \counter[0]~81 (
+// Equation(s):
+// \counter[0]~81_combout  = !counter[0]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(counter[0]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\counter[0]~81_combout ),
+	.cout());
+// synopsys translate_off
+defparam \counter[0]~81 .lut_mask = 16'h0F0F;
+defparam \counter[0]~81 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N5
+dffeas \counter[0] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[0]~81_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[0]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[0] .is_wysiwyg = "true";
+defparam \counter[0] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N6
+cycloneive_lcell_comb \counter[1]~27 (
+// Equation(s):
+// \counter[1]~27_combout  = (counter[1] & (counter[0] $ (VCC))) # (!counter[1] & (counter[0] & VCC))
+// \counter[1]~28  = CARRY((counter[1] & counter[0]))
+
+	.dataa(counter[1]),
+	.datab(counter[0]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(gnd),
+	.combout(\counter[1]~27_combout ),
+	.cout(\counter[1]~28 ));
+// synopsys translate_off
+defparam \counter[1]~27 .lut_mask = 16'h6688;
+defparam \counter[1]~27 .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N7
+dffeas \counter[1] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[1]~27_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[1]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[1] .is_wysiwyg = "true";
+defparam \counter[1] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N8
+cycloneive_lcell_comb \counter[2]~29 (
+// Equation(s):
+// \counter[2]~29_combout  = (counter[2] & (!\counter[1]~28 )) # (!counter[2] & ((\counter[1]~28 ) # (GND)))
+// \counter[2]~30  = CARRY((!\counter[1]~28 ) # (!counter[2]))
+
+	.dataa(gnd),
+	.datab(counter[2]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[1]~28 ),
+	.combout(\counter[2]~29_combout ),
+	.cout(\counter[2]~30 ));
+// synopsys translate_off
+defparam \counter[2]~29 .lut_mask = 16'h3C3F;
+defparam \counter[2]~29 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N9
+dffeas \counter[2] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[2]~29_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[2]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[2] .is_wysiwyg = "true";
+defparam \counter[2] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N10
+cycloneive_lcell_comb \counter[3]~31 (
+// Equation(s):
+// \counter[3]~31_combout  = (counter[3] & (\counter[2]~30  $ (GND))) # (!counter[3] & (!\counter[2]~30  & VCC))
+// \counter[3]~32  = CARRY((counter[3] & !\counter[2]~30 ))
+
+	.dataa(counter[3]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[2]~30 ),
+	.combout(\counter[3]~31_combout ),
+	.cout(\counter[3]~32 ));
+// synopsys translate_off
+defparam \counter[3]~31 .lut_mask = 16'hA50A;
+defparam \counter[3]~31 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N11
+dffeas \counter[3] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[3]~31_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[3]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[3] .is_wysiwyg = "true";
+defparam \counter[3] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N12
+cycloneive_lcell_comb \counter[4]~33 (
+// Equation(s):
+// \counter[4]~33_combout  = (counter[4] & (!\counter[3]~32 )) # (!counter[4] & ((\counter[3]~32 ) # (GND)))
+// \counter[4]~34  = CARRY((!\counter[3]~32 ) # (!counter[4]))
+
+	.dataa(counter[4]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[3]~32 ),
+	.combout(\counter[4]~33_combout ),
+	.cout(\counter[4]~34 ));
+// synopsys translate_off
+defparam \counter[4]~33 .lut_mask = 16'h5A5F;
+defparam \counter[4]~33 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N13
+dffeas \counter[4] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[4]~33_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[4]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[4] .is_wysiwyg = "true";
+defparam \counter[4] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N14
+cycloneive_lcell_comb \counter[5]~35 (
+// Equation(s):
+// \counter[5]~35_combout  = (counter[5] & (\counter[4]~34  $ (GND))) # (!counter[5] & (!\counter[4]~34  & VCC))
+// \counter[5]~36  = CARRY((counter[5] & !\counter[4]~34 ))
+
+	.dataa(gnd),
+	.datab(counter[5]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[4]~34 ),
+	.combout(\counter[5]~35_combout ),
+	.cout(\counter[5]~36 ));
+// synopsys translate_off
+defparam \counter[5]~35 .lut_mask = 16'hC30C;
+defparam \counter[5]~35 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N15
+dffeas \counter[5] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[5]~35_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[5]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[5] .is_wysiwyg = "true";
+defparam \counter[5] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N16
+cycloneive_lcell_comb \counter[6]~37 (
+// Equation(s):
+// \counter[6]~37_combout  = (counter[6] & (!\counter[5]~36 )) # (!counter[6] & ((\counter[5]~36 ) # (GND)))
+// \counter[6]~38  = CARRY((!\counter[5]~36 ) # (!counter[6]))
+
+	.dataa(gnd),
+	.datab(counter[6]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[5]~36 ),
+	.combout(\counter[6]~37_combout ),
+	.cout(\counter[6]~38 ));
+// synopsys translate_off
+defparam \counter[6]~37 .lut_mask = 16'h3C3F;
+defparam \counter[6]~37 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N17
+dffeas \counter[6] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[6]~37_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[6]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[6] .is_wysiwyg = "true";
+defparam \counter[6] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N18
+cycloneive_lcell_comb \counter[7]~39 (
+// Equation(s):
+// \counter[7]~39_combout  = (counter[7] & (\counter[6]~38  $ (GND))) # (!counter[7] & (!\counter[6]~38  & VCC))
+// \counter[7]~40  = CARRY((counter[7] & !\counter[6]~38 ))
+
+	.dataa(gnd),
+	.datab(counter[7]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[6]~38 ),
+	.combout(\counter[7]~39_combout ),
+	.cout(\counter[7]~40 ));
+// synopsys translate_off
+defparam \counter[7]~39 .lut_mask = 16'hC30C;
+defparam \counter[7]~39 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N19
+dffeas \counter[7] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[7]~39_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[7]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[7] .is_wysiwyg = "true";
+defparam \counter[7] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N20
+cycloneive_lcell_comb \counter[8]~41 (
+// Equation(s):
+// \counter[8]~41_combout  = (counter[8] & (!\counter[7]~40 )) # (!counter[8] & ((\counter[7]~40 ) # (GND)))
+// \counter[8]~42  = CARRY((!\counter[7]~40 ) # (!counter[8]))
+
+	.dataa(gnd),
+	.datab(counter[8]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[7]~40 ),
+	.combout(\counter[8]~41_combout ),
+	.cout(\counter[8]~42 ));
+// synopsys translate_off
+defparam \counter[8]~41 .lut_mask = 16'h3C3F;
+defparam \counter[8]~41 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N21
+dffeas \counter[8] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[8]~41_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[8]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[8] .is_wysiwyg = "true";
+defparam \counter[8] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N22
+cycloneive_lcell_comb \counter[9]~43 (
+// Equation(s):
+// \counter[9]~43_combout  = (counter[9] & (\counter[8]~42  $ (GND))) # (!counter[9] & (!\counter[8]~42  & VCC))
+// \counter[9]~44  = CARRY((counter[9] & !\counter[8]~42 ))
+
+	.dataa(counter[9]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[8]~42 ),
+	.combout(\counter[9]~43_combout ),
+	.cout(\counter[9]~44 ));
+// synopsys translate_off
+defparam \counter[9]~43 .lut_mask = 16'hA50A;
+defparam \counter[9]~43 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N23
+dffeas \counter[9] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[9]~43_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[9]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[9] .is_wysiwyg = "true";
+defparam \counter[9] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N24
+cycloneive_lcell_comb \counter[10]~45 (
+// Equation(s):
+// \counter[10]~45_combout  = (counter[10] & (!\counter[9]~44 )) # (!counter[10] & ((\counter[9]~44 ) # (GND)))
+// \counter[10]~46  = CARRY((!\counter[9]~44 ) # (!counter[10]))
+
+	.dataa(gnd),
+	.datab(counter[10]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[9]~44 ),
+	.combout(\counter[10]~45_combout ),
+	.cout(\counter[10]~46 ));
+// synopsys translate_off
+defparam \counter[10]~45 .lut_mask = 16'h3C3F;
+defparam \counter[10]~45 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N25
+dffeas \counter[10] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[10]~45_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[10]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[10] .is_wysiwyg = "true";
+defparam \counter[10] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N26
+cycloneive_lcell_comb \counter[11]~47 (
+// Equation(s):
+// \counter[11]~47_combout  = (counter[11] & (\counter[10]~46  $ (GND))) # (!counter[11] & (!\counter[10]~46  & VCC))
+// \counter[11]~48  = CARRY((counter[11] & !\counter[10]~46 ))
+
+	.dataa(counter[11]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[10]~46 ),
+	.combout(\counter[11]~47_combout ),
+	.cout(\counter[11]~48 ));
+// synopsys translate_off
+defparam \counter[11]~47 .lut_mask = 16'hA50A;
+defparam \counter[11]~47 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N27
+dffeas \counter[11] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[11]~47_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[11]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[11] .is_wysiwyg = "true";
+defparam \counter[11] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N28
+cycloneive_lcell_comb \counter[12]~49 (
+// Equation(s):
+// \counter[12]~49_combout  = (counter[12] & (!\counter[11]~48 )) # (!counter[12] & ((\counter[11]~48 ) # (GND)))
+// \counter[12]~50  = CARRY((!\counter[11]~48 ) # (!counter[12]))
+
+	.dataa(gnd),
+	.datab(counter[12]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[11]~48 ),
+	.combout(\counter[12]~49_combout ),
+	.cout(\counter[12]~50 ));
+// synopsys translate_off
+defparam \counter[12]~49 .lut_mask = 16'h3C3F;
+defparam \counter[12]~49 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N29
+dffeas \counter[12] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[12]~49_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[12]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[12] .is_wysiwyg = "true";
+defparam \counter[12] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y33_N30
+cycloneive_lcell_comb \counter[13]~51 (
+// Equation(s):
+// \counter[13]~51_combout  = (counter[13] & (\counter[12]~50  $ (GND))) # (!counter[13] & (!\counter[12]~50  & VCC))
+// \counter[13]~52  = CARRY((counter[13] & !\counter[12]~50 ))
+
+	.dataa(counter[13]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[12]~50 ),
+	.combout(\counter[13]~51_combout ),
+	.cout(\counter[13]~52 ));
+// synopsys translate_off
+defparam \counter[13]~51 .lut_mask = 16'hA50A;
+defparam \counter[13]~51 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y33_N31
+dffeas \counter[13] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[13]~51_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[13]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[13] .is_wysiwyg = "true";
+defparam \counter[13] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N0
+cycloneive_lcell_comb \counter[14]~53 (
+// Equation(s):
+// \counter[14]~53_combout  = (counter[14] & (!\counter[13]~52 )) # (!counter[14] & ((\counter[13]~52 ) # (GND)))
+// \counter[14]~54  = CARRY((!\counter[13]~52 ) # (!counter[14]))
+
+	.dataa(gnd),
+	.datab(counter[14]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[13]~52 ),
+	.combout(\counter[14]~53_combout ),
+	.cout(\counter[14]~54 ));
+// synopsys translate_off
+defparam \counter[14]~53 .lut_mask = 16'h3C3F;
+defparam \counter[14]~53 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N1
+dffeas \counter[14] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[14]~53_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[14]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[14] .is_wysiwyg = "true";
+defparam \counter[14] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N2
+cycloneive_lcell_comb \counter[15]~55 (
+// Equation(s):
+// \counter[15]~55_combout  = (counter[15] & (\counter[14]~54  $ (GND))) # (!counter[15] & (!\counter[14]~54  & VCC))
+// \counter[15]~56  = CARRY((counter[15] & !\counter[14]~54 ))
+
+	.dataa(gnd),
+	.datab(counter[15]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[14]~54 ),
+	.combout(\counter[15]~55_combout ),
+	.cout(\counter[15]~56 ));
+// synopsys translate_off
+defparam \counter[15]~55 .lut_mask = 16'hC30C;
+defparam \counter[15]~55 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N3
+dffeas \counter[15] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[15]~55_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[15]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[15] .is_wysiwyg = "true";
+defparam \counter[15] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N4
+cycloneive_lcell_comb \counter[16]~57 (
+// Equation(s):
+// \counter[16]~57_combout  = (counter[16] & (!\counter[15]~56 )) # (!counter[16] & ((\counter[15]~56 ) # (GND)))
+// \counter[16]~58  = CARRY((!\counter[15]~56 ) # (!counter[16]))
+
+	.dataa(gnd),
+	.datab(counter[16]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[15]~56 ),
+	.combout(\counter[16]~57_combout ),
+	.cout(\counter[16]~58 ));
+// synopsys translate_off
+defparam \counter[16]~57 .lut_mask = 16'h3C3F;
+defparam \counter[16]~57 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N5
+dffeas \counter[16] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[16]~57_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[16]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[16] .is_wysiwyg = "true";
+defparam \counter[16] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N6
+cycloneive_lcell_comb \counter[17]~59 (
+// Equation(s):
+// \counter[17]~59_combout  = (counter[17] & (\counter[16]~58  $ (GND))) # (!counter[17] & (!\counter[16]~58  & VCC))
+// \counter[17]~60  = CARRY((counter[17] & !\counter[16]~58 ))
+
+	.dataa(counter[17]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[16]~58 ),
+	.combout(\counter[17]~59_combout ),
+	.cout(\counter[17]~60 ));
+// synopsys translate_off
+defparam \counter[17]~59 .lut_mask = 16'hA50A;
+defparam \counter[17]~59 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N7
+dffeas \counter[17] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[17]~59_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[17]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[17] .is_wysiwyg = "true";
+defparam \counter[17] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N8
+cycloneive_lcell_comb \counter[18]~61 (
+// Equation(s):
+// \counter[18]~61_combout  = (counter[18] & (!\counter[17]~60 )) # (!counter[18] & ((\counter[17]~60 ) # (GND)))
+// \counter[18]~62  = CARRY((!\counter[17]~60 ) # (!counter[18]))
+
+	.dataa(gnd),
+	.datab(counter[18]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[17]~60 ),
+	.combout(\counter[18]~61_combout ),
+	.cout(\counter[18]~62 ));
+// synopsys translate_off
+defparam \counter[18]~61 .lut_mask = 16'h3C3F;
+defparam \counter[18]~61 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N9
+dffeas \counter[18] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[18]~61_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[18]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[18] .is_wysiwyg = "true";
+defparam \counter[18] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N10
+cycloneive_lcell_comb \counter[19]~63 (
+// Equation(s):
+// \counter[19]~63_combout  = (counter[19] & (\counter[18]~62  $ (GND))) # (!counter[19] & (!\counter[18]~62  & VCC))
+// \counter[19]~64  = CARRY((counter[19] & !\counter[18]~62 ))
+
+	.dataa(counter[19]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[18]~62 ),
+	.combout(\counter[19]~63_combout ),
+	.cout(\counter[19]~64 ));
+// synopsys translate_off
+defparam \counter[19]~63 .lut_mask = 16'hA50A;
+defparam \counter[19]~63 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N11
+dffeas \counter[19] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[19]~63_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[19]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[19] .is_wysiwyg = "true";
+defparam \counter[19] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N12
+cycloneive_lcell_comb \counter[20]~65 (
+// Equation(s):
+// \counter[20]~65_combout  = (counter[20] & (!\counter[19]~64 )) # (!counter[20] & ((\counter[19]~64 ) # (GND)))
+// \counter[20]~66  = CARRY((!\counter[19]~64 ) # (!counter[20]))
+
+	.dataa(counter[20]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[19]~64 ),
+	.combout(\counter[20]~65_combout ),
+	.cout(\counter[20]~66 ));
+// synopsys translate_off
+defparam \counter[20]~65 .lut_mask = 16'h5A5F;
+defparam \counter[20]~65 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N13
+dffeas \counter[20] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[20]~65_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[20]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[20] .is_wysiwyg = "true";
+defparam \counter[20] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N14
+cycloneive_lcell_comb \counter[21]~67 (
+// Equation(s):
+// \counter[21]~67_combout  = (counter[21] & (\counter[20]~66  $ (GND))) # (!counter[21] & (!\counter[20]~66  & VCC))
+// \counter[21]~68  = CARRY((counter[21] & !\counter[20]~66 ))
+
+	.dataa(gnd),
+	.datab(counter[21]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[20]~66 ),
+	.combout(\counter[21]~67_combout ),
+	.cout(\counter[21]~68 ));
+// synopsys translate_off
+defparam \counter[21]~67 .lut_mask = 16'hC30C;
+defparam \counter[21]~67 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N15
+dffeas \counter[21] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[21]~67_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[21]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[21] .is_wysiwyg = "true";
+defparam \counter[21] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X38_Y32_N4
+cycloneive_lcell_comb \LED[0]~reg0feeder (
+// Equation(s):
+// \LED[0]~reg0feeder_combout  = counter[21]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(counter[21]),
+	.datad(gnd),
+	.cin(gnd),
+	.combout(\LED[0]~reg0feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \LED[0]~reg0feeder .lut_mask = 16'hF0F0;
+defparam \LED[0]~reg0feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X38_Y32_N5
+dffeas \LED[0]~reg0 (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\LED[0]~reg0feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\LED[0]~reg0_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \LED[0]~reg0 .is_wysiwyg = "true";
+defparam \LED[0]~reg0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N16
+cycloneive_lcell_comb \counter[22]~69 (
+// Equation(s):
+// \counter[22]~69_combout  = (counter[22] & (!\counter[21]~68 )) # (!counter[22] & ((\counter[21]~68 ) # (GND)))
+// \counter[22]~70  = CARRY((!\counter[21]~68 ) # (!counter[22]))
+
+	.dataa(gnd),
+	.datab(counter[22]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[21]~68 ),
+	.combout(\counter[22]~69_combout ),
+	.cout(\counter[22]~70 ));
+// synopsys translate_off
+defparam \counter[22]~69 .lut_mask = 16'h3C3F;
+defparam \counter[22]~69 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N17
+dffeas \counter[22] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[22]~69_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[22]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[22] .is_wysiwyg = "true";
+defparam \counter[22] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X46_Y32_N12
+cycloneive_lcell_comb \LED[1]~reg0feeder (
+// Equation(s):
+// \LED[1]~reg0feeder_combout  = counter[22]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(counter[22]),
+	.cin(gnd),
+	.combout(\LED[1]~reg0feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \LED[1]~reg0feeder .lut_mask = 16'hFF00;
+defparam \LED[1]~reg0feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X46_Y32_N13
+dffeas \LED[1]~reg0 (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\LED[1]~reg0feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\LED[1]~reg0_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \LED[1]~reg0 .is_wysiwyg = "true";
+defparam \LED[1]~reg0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N18
+cycloneive_lcell_comb \counter[23]~71 (
+// Equation(s):
+// \counter[23]~71_combout  = (counter[23] & (\counter[22]~70  $ (GND))) # (!counter[23] & (!\counter[22]~70  & VCC))
+// \counter[23]~72  = CARRY((counter[23] & !\counter[22]~70 ))
+
+	.dataa(gnd),
+	.datab(counter[23]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[22]~70 ),
+	.combout(\counter[23]~71_combout ),
+	.cout(\counter[23]~72 ));
+// synopsys translate_off
+defparam \counter[23]~71 .lut_mask = 16'hC30C;
+defparam \counter[23]~71 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N19
+dffeas \counter[23] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[23]~71_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[23]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[23] .is_wysiwyg = "true";
+defparam \counter[23] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X46_Y32_N6
+cycloneive_lcell_comb \LED[2]~reg0feeder (
+// Equation(s):
+// \LED[2]~reg0feeder_combout  = counter[23]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(counter[23]),
+	.cin(gnd),
+	.combout(\LED[2]~reg0feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \LED[2]~reg0feeder .lut_mask = 16'hFF00;
+defparam \LED[2]~reg0feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X46_Y32_N7
+dffeas \LED[2]~reg0 (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\LED[2]~reg0feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\LED[2]~reg0_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \LED[2]~reg0 .is_wysiwyg = "true";
+defparam \LED[2]~reg0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N20
+cycloneive_lcell_comb \counter[24]~73 (
+// Equation(s):
+// \counter[24]~73_combout  = (counter[24] & (!\counter[23]~72 )) # (!counter[24] & ((\counter[23]~72 ) # (GND)))
+// \counter[24]~74  = CARRY((!\counter[23]~72 ) # (!counter[24]))
+
+	.dataa(gnd),
+	.datab(counter[24]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[23]~72 ),
+	.combout(\counter[24]~73_combout ),
+	.cout(\counter[24]~74 ));
+// synopsys translate_off
+defparam \counter[24]~73 .lut_mask = 16'h3C3F;
+defparam \counter[24]~73 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N21
+dffeas \counter[24] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[24]~73_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[24]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[24] .is_wysiwyg = "true";
+defparam \counter[24] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X40_Y32_N4
+cycloneive_lcell_comb \LED[3]~reg0feeder (
+// Equation(s):
+// \LED[3]~reg0feeder_combout  = counter[24]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(counter[24]),
+	.cin(gnd),
+	.combout(\LED[3]~reg0feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \LED[3]~reg0feeder .lut_mask = 16'hFF00;
+defparam \LED[3]~reg0feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X40_Y32_N5
+dffeas \LED[3]~reg0 (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\LED[3]~reg0feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\LED[3]~reg0_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \LED[3]~reg0 .is_wysiwyg = "true";
+defparam \LED[3]~reg0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N22
+cycloneive_lcell_comb \counter[25]~75 (
+// Equation(s):
+// \counter[25]~75_combout  = (counter[25] & (\counter[24]~74  $ (GND))) # (!counter[25] & (!\counter[24]~74  & VCC))
+// \counter[25]~76  = CARRY((counter[25] & !\counter[24]~74 ))
+
+	.dataa(counter[25]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[24]~74 ),
+	.combout(\counter[25]~75_combout ),
+	.cout(\counter[25]~76 ));
+// synopsys translate_off
+defparam \counter[25]~75 .lut_mask = 16'hA50A;
+defparam \counter[25]~75 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N23
+dffeas \counter[25] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[25]~75_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[25]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[25] .is_wysiwyg = "true";
+defparam \counter[25] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X38_Y32_N18
+cycloneive_lcell_comb \LED[4]~reg0feeder (
+// Equation(s):
+// \LED[4]~reg0feeder_combout  = counter[25]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(counter[25]),
+	.cin(gnd),
+	.combout(\LED[4]~reg0feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \LED[4]~reg0feeder .lut_mask = 16'hFF00;
+defparam \LED[4]~reg0feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X38_Y32_N19
+dffeas \LED[4]~reg0 (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\LED[4]~reg0feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\LED[4]~reg0_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \LED[4]~reg0 .is_wysiwyg = "true";
+defparam \LED[4]~reg0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N24
+cycloneive_lcell_comb \counter[26]~77 (
+// Equation(s):
+// \counter[26]~77_combout  = (counter[26] & (!\counter[25]~76 )) # (!counter[26] & ((\counter[25]~76 ) # (GND)))
+// \counter[26]~78  = CARRY((!\counter[25]~76 ) # (!counter[26]))
+
+	.dataa(gnd),
+	.datab(counter[26]),
+	.datac(gnd),
+	.datad(vcc),
+	.cin(\counter[25]~76 ),
+	.combout(\counter[26]~77_combout ),
+	.cout(\counter[26]~78 ));
+// synopsys translate_off
+defparam \counter[26]~77 .lut_mask = 16'h3C3F;
+defparam \counter[26]~77 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N25
+dffeas \counter[26] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[26]~77_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[26]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[26] .is_wysiwyg = "true";
+defparam \counter[26] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X38_Y32_N24
+cycloneive_lcell_comb \LED[5]~reg0feeder (
+// Equation(s):
+// \LED[5]~reg0feeder_combout  = counter[26]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(counter[26]),
+	.cin(gnd),
+	.combout(\LED[5]~reg0feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \LED[5]~reg0feeder .lut_mask = 16'hFF00;
+defparam \LED[5]~reg0feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X38_Y32_N25
+dffeas \LED[5]~reg0 (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\LED[5]~reg0feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\LED[5]~reg0_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \LED[5]~reg0 .is_wysiwyg = "true";
+defparam \LED[5]~reg0 .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X39_Y32_N26
+cycloneive_lcell_comb \counter[27]~79 (
+// Equation(s):
+// \counter[27]~79_combout  = counter[27] $ (!\counter[26]~78 )
+
+	.dataa(counter[27]),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(gnd),
+	.cin(\counter[26]~78 ),
+	.combout(\counter[27]~79_combout ),
+	.cout());
+// synopsys translate_off
+defparam \counter[27]~79 .lut_mask = 16'hA5A5;
+defparam \counter[27]~79 .sum_lutc_input = "cin";
+// synopsys translate_on
+
+// Location: FF_X39_Y32_N27
+dffeas \counter[27] (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\counter[27]~79_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(counter[27]),
+	.prn(vcc));
+// synopsys translate_off
+defparam \counter[27] .is_wysiwyg = "true";
+defparam \counter[27] .power_up = "low";
+// synopsys translate_on
+
+// Location: LCCOMB_X38_Y32_N14
+cycloneive_lcell_comb \LED[6]~reg0feeder (
+// Equation(s):
+// \LED[6]~reg0feeder_combout  = counter[27]
+
+	.dataa(gnd),
+	.datab(gnd),
+	.datac(gnd),
+	.datad(counter[27]),
+	.cin(gnd),
+	.combout(\LED[6]~reg0feeder_combout ),
+	.cout());
+// synopsys translate_off
+defparam \LED[6]~reg0feeder .lut_mask = 16'hFF00;
+defparam \LED[6]~reg0feeder .sum_lutc_input = "datac";
+// synopsys translate_on
+
+// Location: FF_X38_Y32_N15
+dffeas \LED[6]~reg0 (
+	.clk(\CLOCK_50~inputclkctrl_outclk ),
+	.d(\LED[6]~reg0feeder_combout ),
+	.asdata(vcc),
+	.clrn(vcc),
+	.aload(gnd),
+	.sclr(gnd),
+	.sload(gnd),
+	.ena(vcc),
+	.devclrn(devclrn),
+	.devpor(devpor),
+	.q(\LED[6]~reg0_q ),
+	.prn(vcc));
+// synopsys translate_off
+defparam \LED[6]~reg0 .is_wysiwyg = "true";
+defparam \LED[6]~reg0 .power_up = "low";
+// synopsys translate_on
+
+assign LED[0] = \LED[0]~output_o ;
+
+assign LED[1] = \LED[1]~output_o ;
+
+assign LED[2] = \LED[2]~output_o ;
+
+assign LED[3] = \LED[3]~output_o ;
+
+assign LED[4] = \LED[4]~output_o ;
+
+assign LED[5] = \LED[5]~output_o ;
+
+assign LED[6] = \LED[6]~output_o ;
+
+assign LED[7] = \LED[7]~output_o ;
+
+endmodule
diff --git a/simulation/modelsim/spectrum_min_1200mv_0c_v_fast.sdo b/simulation/modelsim/spectrum_min_1200mv_0c_v_fast.sdo
new file mode 100644
index 0000000..dd66449
--- /dev/null
+++ b/simulation/modelsim/spectrum_min_1200mv_0c_v_fast.sdo
@@ -0,0 +1,1072 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP4CE22F17C6 Package FBGA256
+// 
+
+//
+// This file contains Fast Corner delays for the design using part EP4CE22F17C6,
+// with speed grade M, core voltage 1.2V, and temperature 0 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (Verilog) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "spectrum")
+  (DATE "03/30/2022 11:51:43")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 32-bit")
+  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneive_io_obuf")
+    (INSTANCE LED\[0\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (268:268:268) (309:309:309))
+        (IOPATH i o (1643:1643:1643) (1588:1588:1588))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_obuf")
+    (INSTANCE LED\[1\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (394:394:394) (447:447:447))
+        (IOPATH i o (1643:1643:1643) (1588:1588:1588))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_obuf")
+    (INSTANCE LED\[2\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (384:384:384) (435:435:435))
+        (IOPATH i o (1643:1643:1643) (1588:1588:1588))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_obuf")
+    (INSTANCE LED\[3\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (267:267:267) (309:309:309))
+        (IOPATH i o (1643:1643:1643) (1588:1588:1588))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_obuf")
+    (INSTANCE LED\[4\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1373:1373:1373) (1578:1578:1578))
+        (IOPATH i o (1666:1666:1666) (1600:1600:1600))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_obuf")
+    (INSTANCE LED\[5\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1355:1355:1355) (1575:1575:1575))
+        (IOPATH i o (3106:3106:3106) (2841:2841:2841))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_obuf")
+    (INSTANCE LED\[6\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (754:754:754) (885:885:885))
+        (IOPATH i o (1586:1586:1586) (1541:1541:1541))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_ibuf")
+    (INSTANCE CLOCK_50\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (153:153:153) (704:704:704))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_clkctrl")
+    (INSTANCE CLOCK_50\~inputclkctrl)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (91:91:91) (78:78:78))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[0\]\~81)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH datac combout (190:190:190) (195:195:195))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (915:915:915) (919:919:919))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[1\]\~27)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (130:130:130) (181:181:181))
+        (PORT datab (129:129:129) (177:177:177))
+        (IOPATH dataa combout (186:186:186) (180:180:180))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datab combout (190:190:190) (181:181:181))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (915:915:915) (919:919:919))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[2\]\~29)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (130:130:130) (177:177:177))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (915:915:915) (919:919:919))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[3\]\~31)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (130:130:130) (180:180:180))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (915:915:915) (919:919:919))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[4\]\~33)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (130:130:130) (180:180:180))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (915:915:915) (919:919:919))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[5\]\~35)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (129:129:129) (177:177:177))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (915:915:915) (919:919:919))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[6\]\~37)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (129:129:129) (177:177:177))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (915:915:915) (919:919:919))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[7\]\~39)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (130:130:130) (177:177:177))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (915:915:915) (919:919:919))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[8\]\~41)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (130:130:130) (177:177:177))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (915:915:915) (919:919:919))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[9\]\~43)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (131:131:131) (180:180:180))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (915:915:915) (919:919:919))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[10\]\~45)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (130:130:130) (177:177:177))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (915:915:915) (919:919:919))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[11\]\~47)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (130:130:130) (181:181:181))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (915:915:915) (919:919:919))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[12\]\~49)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (129:129:129) (177:177:177))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[12\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (915:915:915) (919:919:919))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[13\]\~51)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (129:129:129) (180:180:180))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[13\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1112:1112:1112) (1141:1141:1141))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[14\]\~53)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (129:129:129) (177:177:177))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[14\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (914:914:914) (919:919:919))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[15\]\~55)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (129:129:129) (177:177:177))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[15\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (914:914:914) (919:919:919))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[16\]\~57)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (130:130:130) (178:178:178))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[16\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (914:914:914) (919:919:919))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[17\]\~59)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (131:131:131) (181:181:181))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[17\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1112:1112:1112) (1141:1141:1141))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[18\]\~61)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (130:130:130) (178:178:178))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[18\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1112:1112:1112) (1141:1141:1141))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[19\]\~63)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (131:131:131) (181:181:181))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[19\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1112:1112:1112) (1141:1141:1141))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[20\]\~65)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (131:131:131) (181:181:181))
+        (IOPATH dataa combout (165:165:165) (173:173:173))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[20\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1112:1112:1112) (1141:1141:1141))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[21\]\~67)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (142:142:142) (190:190:190))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[21\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1112:1112:1112) (1141:1141:1141))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE LED\[0\]\~reg0feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (213:213:213) (265:265:265))
+        (IOPATH datac combout (119:119:119) (124:124:124))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE LED\[0\]\~reg0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (913:913:913) (917:917:917))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[22\]\~69)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (142:142:142) (190:190:190))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[22\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1112:1112:1112) (1141:1141:1141))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE LED\[1\]\~reg0feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (427:427:427) (494:494:494))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE LED\[1\]\~reg0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (919:919:919) (924:924:924))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[23\]\~71)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (142:142:142) (190:190:190))
+        (IOPATH datab combout (192:192:192) (177:177:177))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[23\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1112:1112:1112) (1141:1141:1141))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE LED\[2\]\~reg0feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (416:416:416) (474:474:474))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE LED\[2\]\~reg0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (919:919:919) (924:924:924))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[24\]\~73)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (142:142:142) (190:190:190))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[24\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1112:1112:1112) (1141:1141:1141))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE LED\[3\]\~reg0feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (208:208:208) (254:254:254))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE LED\[3\]\~reg0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (915:915:915) (920:920:920))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[25\]\~75)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (143:143:143) (193:193:193))
+        (IOPATH dataa combout (186:186:186) (175:175:175))
+        (IOPATH dataa cout (226:226:226) (171:171:171))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[25\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1112:1112:1112) (1141:1141:1141))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE LED\[4\]\~reg0feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (211:211:211) (260:260:260))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE LED\[4\]\~reg0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (913:913:913) (917:917:917))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[26\]\~77)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (142:142:142) (190:190:190))
+        (IOPATH datab combout (166:166:166) (176:176:176))
+        (IOPATH datab cout (227:227:227) (175:175:175))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+        (IOPATH cin cout (34:34:34) (34:34:34))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[26\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1112:1112:1112) (1141:1141:1141))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE LED\[5\]\~reg0feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (321:321:321) (380:380:380))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE LED\[5\]\~reg0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (913:913:913) (917:917:917))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[27\]\~79)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (143:143:143) (194:194:194))
+        (IOPATH dataa combout (188:188:188) (193:193:193))
+        (IOPATH cin combout (187:187:187) (204:204:204))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[27\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1112:1112:1112) (1141:1141:1141))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE LED\[6\]\~reg0feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (211:211:211) (260:260:260))
+        (IOPATH datad combout (68:68:68) (63:63:63))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE LED\[6\]\~reg0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (913:913:913) (917:917:917))
+        (PORT d (37:37:37) (50:50:50))
+        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (84:84:84))
+    )
+  )
+)
diff --git a/simulation/modelsim/spectrum_modelsim.xrf b/simulation/modelsim/spectrum_modelsim.xrf
new file mode 100644
index 0000000..d71ae1d
--- /dev/null
+++ b/simulation/modelsim/spectrum_modelsim.xrf
@@ -0,0 +1,84 @@
+vendor_name = ModelSim
+source_file = 1, /home/benny/work/fpga/projects/spectrum.v
+source_file = 1, /home/benny/work/fpga/projects/db/spectrum.cbx.xml
+design_name = spectrum
+instance = comp, \LED[0]~output , LED[0]~output, spectrum, 1
+instance = comp, \LED[1]~output , LED[1]~output, spectrum, 1
+instance = comp, \LED[2]~output , LED[2]~output, spectrum, 1
+instance = comp, \LED[3]~output , LED[3]~output, spectrum, 1
+instance = comp, \LED[4]~output , LED[4]~output, spectrum, 1
+instance = comp, \LED[5]~output , LED[5]~output, spectrum, 1
+instance = comp, \LED[6]~output , LED[6]~output, spectrum, 1
+instance = comp, \LED[7]~output , LED[7]~output, spectrum, 1
+instance = comp, \CLOCK_50~input , CLOCK_50~input, spectrum, 1
+instance = comp, \CLOCK_50~inputclkctrl , CLOCK_50~inputclkctrl, spectrum, 1
+instance = comp, \counter[0]~81 , counter[0]~81, spectrum, 1
+instance = comp, \counter[0] , counter[0], spectrum, 1
+instance = comp, \counter[1]~27 , counter[1]~27, spectrum, 1
+instance = comp, \counter[1] , counter[1], spectrum, 1
+instance = comp, \counter[2]~29 , counter[2]~29, spectrum, 1
+instance = comp, \counter[2] , counter[2], spectrum, 1
+instance = comp, \counter[3]~31 , counter[3]~31, spectrum, 1
+instance = comp, \counter[3] , counter[3], spectrum, 1
+instance = comp, \counter[4]~33 , counter[4]~33, spectrum, 1
+instance = comp, \counter[4] , counter[4], spectrum, 1
+instance = comp, \counter[5]~35 , counter[5]~35, spectrum, 1
+instance = comp, \counter[5] , counter[5], spectrum, 1
+instance = comp, \counter[6]~37 , counter[6]~37, spectrum, 1
+instance = comp, \counter[6] , counter[6], spectrum, 1
+instance = comp, \counter[7]~39 , counter[7]~39, spectrum, 1
+instance = comp, \counter[7] , counter[7], spectrum, 1
+instance = comp, \counter[8]~41 , counter[8]~41, spectrum, 1
+instance = comp, \counter[8] , counter[8], spectrum, 1
+instance = comp, \counter[9]~43 , counter[9]~43, spectrum, 1
+instance = comp, \counter[9] , counter[9], spectrum, 1
+instance = comp, \counter[10]~45 , counter[10]~45, spectrum, 1
+instance = comp, \counter[10] , counter[10], spectrum, 1
+instance = comp, \counter[11]~47 , counter[11]~47, spectrum, 1
+instance = comp, \counter[11] , counter[11], spectrum, 1
+instance = comp, \counter[12]~49 , counter[12]~49, spectrum, 1
+instance = comp, \counter[12] , counter[12], spectrum, 1
+instance = comp, \counter[13]~51 , counter[13]~51, spectrum, 1
+instance = comp, \counter[13] , counter[13], spectrum, 1
+instance = comp, \counter[14]~53 , counter[14]~53, spectrum, 1
+instance = comp, \counter[14] , counter[14], spectrum, 1
+instance = comp, \counter[15]~55 , counter[15]~55, spectrum, 1
+instance = comp, \counter[15] , counter[15], spectrum, 1
+instance = comp, \counter[16]~57 , counter[16]~57, spectrum, 1
+instance = comp, \counter[16] , counter[16], spectrum, 1
+instance = comp, \counter[17]~59 , counter[17]~59, spectrum, 1
+instance = comp, \counter[17] , counter[17], spectrum, 1
+instance = comp, \counter[18]~61 , counter[18]~61, spectrum, 1
+instance = comp, \counter[18] , counter[18], spectrum, 1
+instance = comp, \counter[19]~63 , counter[19]~63, spectrum, 1
+instance = comp, \counter[19] , counter[19], spectrum, 1
+instance = comp, \counter[20]~65 , counter[20]~65, spectrum, 1
+instance = comp, \counter[20] , counter[20], spectrum, 1
+instance = comp, \counter[21]~67 , counter[21]~67, spectrum, 1
+instance = comp, \counter[21] , counter[21], spectrum, 1
+instance = comp, \LED[0]~reg0feeder , LED[0]~reg0feeder, spectrum, 1
+instance = comp, \LED[0]~reg0 , LED[0]~reg0, spectrum, 1
+instance = comp, \counter[22]~69 , counter[22]~69, spectrum, 1
+instance = comp, \counter[22] , counter[22], spectrum, 1
+instance = comp, \LED[1]~reg0feeder , LED[1]~reg0feeder, spectrum, 1
+instance = comp, \LED[1]~reg0 , LED[1]~reg0, spectrum, 1
+instance = comp, \counter[23]~71 , counter[23]~71, spectrum, 1
+instance = comp, \counter[23] , counter[23], spectrum, 1
+instance = comp, \LED[2]~reg0feeder , LED[2]~reg0feeder, spectrum, 1
+instance = comp, \LED[2]~reg0 , LED[2]~reg0, spectrum, 1
+instance = comp, \counter[24]~73 , counter[24]~73, spectrum, 1
+instance = comp, \counter[24] , counter[24], spectrum, 1
+instance = comp, \LED[3]~reg0feeder , LED[3]~reg0feeder, spectrum, 1
+instance = comp, \LED[3]~reg0 , LED[3]~reg0, spectrum, 1
+instance = comp, \counter[25]~75 , counter[25]~75, spectrum, 1
+instance = comp, \counter[25] , counter[25], spectrum, 1
+instance = comp, \LED[4]~reg0feeder , LED[4]~reg0feeder, spectrum, 1
+instance = comp, \LED[4]~reg0 , LED[4]~reg0, spectrum, 1
+instance = comp, \counter[26]~77 , counter[26]~77, spectrum, 1
+instance = comp, \counter[26] , counter[26], spectrum, 1
+instance = comp, \LED[5]~reg0feeder , LED[5]~reg0feeder, spectrum, 1
+instance = comp, \LED[5]~reg0 , LED[5]~reg0, spectrum, 1
+instance = comp, \counter[27]~79 , counter[27]~79, spectrum, 1
+instance = comp, \counter[27] , counter[27], spectrum, 1
+instance = comp, \LED[6]~reg0feeder , LED[6]~reg0feeder, spectrum, 1
+instance = comp, \LED[6]~reg0 , LED[6]~reg0, spectrum, 1
diff --git a/simulation/modelsim/spectrum_v.sdo b/simulation/modelsim/spectrum_v.sdo
new file mode 100644
index 0000000..e97f726
--- /dev/null
+++ b/simulation/modelsim/spectrum_v.sdo
@@ -0,0 +1,1072 @@
+// Copyright (C) 1991-2013 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP4CE22F17C6 Package FBGA256
+// 
+
+//
+// This file contains Slow Corner delays for the design using part EP4CE22F17C6,
+// with speed grade 6, core voltage 1.2V, and temperature 85 Celsius
+//
+
+// 
+// This SDF file should be used for ModelSim-Altera (Verilog) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "spectrum")
+  (DATE "03/30/2022 11:51:43")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II 32-bit")
+  (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "cycloneive_io_obuf")
+    (INSTANCE LED\[0\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (513:513:513) (544:544:544))
+        (IOPATH i o (2535:2535:2535) (2445:2445:2445))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_obuf")
+    (INSTANCE LED\[1\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (754:754:754) (771:771:771))
+        (IOPATH i o (2535:2535:2535) (2445:2445:2445))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_obuf")
+    (INSTANCE LED\[2\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (734:734:734) (751:751:751))
+        (IOPATH i o (2535:2535:2535) (2445:2445:2445))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_obuf")
+    (INSTANCE LED\[3\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (512:512:512) (543:543:543))
+        (IOPATH i o (2535:2535:2535) (2445:2445:2445))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_obuf")
+    (INSTANCE LED\[4\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (2451:2451:2451) (2550:2550:2550))
+        (IOPATH i o (2582:2582:2582) (2502:2502:2502))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_obuf")
+    (INSTANCE LED\[5\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (2441:2441:2441) (2543:2543:2543))
+        (IOPATH i o (4477:4477:4477) (4127:4127:4127))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_obuf")
+    (INSTANCE LED\[6\]\~output)
+    (DELAY
+      (ABSOLUTE
+        (PORT i (1301:1301:1301) (1440:1440:1440))
+        (IOPATH i o (2455:2455:2455) (2378:2378:2378))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_io_ibuf")
+    (INSTANCE CLOCK_50\~input)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH i o (479:479:479) (732:732:732))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_clkctrl")
+    (INSTANCE CLOCK_50\~inputclkctrl)
+    (DELAY
+      (ABSOLUTE
+        (PORT inclk[0] (154:154:154) (138:138:138))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[0\]\~81)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH datac combout (353:353:353) (369:369:369))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[0\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1533:1533:1533) (1545:1545:1545))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[1\]\~27)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (243:243:243) (329:329:329))
+        (PORT datab (241:241:241) (323:323:323))
+        (IOPATH dataa combout (339:339:339) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datab combout (344:344:344) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[1\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1533:1533:1533) (1545:1545:1545))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[2\]\~29)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (242:242:242) (323:323:323))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[2\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1533:1533:1533) (1545:1545:1545))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[3\]\~31)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (244:244:244) (331:331:331))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[3\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1533:1533:1533) (1545:1545:1545))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[4\]\~33)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (244:244:244) (331:331:331))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[4\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1533:1533:1533) (1545:1545:1545))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[5\]\~35)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (242:242:242) (325:325:325))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[5\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1533:1533:1533) (1545:1545:1545))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[6\]\~37)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (242:242:242) (325:325:325))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[6\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1533:1533:1533) (1545:1545:1545))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[7\]\~39)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (242:242:242) (325:325:325))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[7\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1533:1533:1533) (1545:1545:1545))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[8\]\~41)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (242:242:242) (325:325:325))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[8\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1533:1533:1533) (1545:1545:1545))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[9\]\~43)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (244:244:244) (330:330:330))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[9\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1533:1533:1533) (1545:1545:1545))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[10\]\~45)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (242:242:242) (323:323:323))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[10\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1533:1533:1533) (1545:1545:1545))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[11\]\~47)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (243:243:243) (329:329:329))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[11\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1533:1533:1533) (1545:1545:1545))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[12\]\~49)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (241:241:241) (323:323:323))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[12\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1533:1533:1533) (1545:1545:1545))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[13\]\~51)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (243:243:243) (329:329:329))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[13\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1898:1898:1898) (1920:1920:1920))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[14\]\~53)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (240:240:240) (322:322:322))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[14\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1532:1532:1532) (1545:1545:1545))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[15\]\~55)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (241:241:241) (323:323:323))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[15\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1532:1532:1532) (1545:1545:1545))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[16\]\~57)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (241:241:241) (323:323:323))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[16\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1532:1532:1532) (1545:1545:1545))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[17\]\~59)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (244:244:244) (330:330:330))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[17\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1898:1898:1898) (1920:1920:1920))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[18\]\~61)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (243:243:243) (324:324:324))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[18\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1898:1898:1898) (1920:1920:1920))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[19\]\~63)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (245:245:245) (333:333:333))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[19\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1898:1898:1898) (1920:1920:1920))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[20\]\~65)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (245:245:245) (332:332:332))
+        (IOPATH dataa combout (356:356:356) (368:368:368))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[20\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1898:1898:1898) (1920:1920:1920))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[21\]\~67)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (264:264:264) (347:347:347))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[21\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1898:1898:1898) (1920:1920:1920))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE LED\[0\]\~reg0feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (411:411:411) (472:472:472))
+        (IOPATH datac combout (243:243:243) (242:242:242))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE LED\[0\]\~reg0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1532:1532:1532) (1544:1544:1544))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[22\]\~69)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (264:264:264) (347:347:347))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[22\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1898:1898:1898) (1920:1920:1920))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE LED\[1\]\~reg0feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (808:808:808) (843:843:843))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE LED\[1\]\~reg0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1538:1538:1538) (1550:1550:1550))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[23\]\~71)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (264:264:264) (347:347:347))
+        (IOPATH datab combout (355:355:355) (369:369:369))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[23\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1898:1898:1898) (1920:1920:1920))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE LED\[2\]\~reg0feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (771:771:771) (813:813:813))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE LED\[2\]\~reg0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1538:1538:1538) (1550:1550:1550))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[24\]\~73)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (264:264:264) (347:347:347))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[24\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1898:1898:1898) (1920:1920:1920))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE LED\[3\]\~reg0feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (399:399:399) (452:452:452))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE LED\[3\]\~reg0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1533:1533:1533) (1545:1545:1545))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[25\]\~75)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (266:266:266) (352:352:352))
+        (IOPATH dataa combout (354:354:354) (367:367:367))
+        (IOPATH dataa cout (436:436:436) (315:315:315))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[25\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1898:1898:1898) (1920:1920:1920))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE LED\[4\]\~reg0feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (404:404:404) (467:467:467))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE LED\[4\]\~reg0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1532:1532:1532) (1544:1544:1544))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[26\]\~77)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (263:263:263) (345:345:345))
+        (IOPATH datab combout (365:365:365) (373:373:373))
+        (IOPATH datab cout (446:446:446) (318:318:318))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+        (IOPATH cin cout (58:58:58) (58:58:58))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[26\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1898:1898:1898) (1920:1920:1920))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE LED\[5\]\~reg0feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (610:610:610) (670:670:670))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE LED\[5\]\~reg0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1532:1532:1532) (1544:1544:1544))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE counter\[27\]\~79)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (266:266:266) (353:353:353))
+        (IOPATH dataa combout (371:371:371) (376:376:376))
+        (IOPATH cin combout (455:455:455) (437:437:437))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE counter\[27\])
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1898:1898:1898) (1920:1920:1920))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+  (CELL
+    (CELLTYPE "cycloneive_lcell_comb")
+    (INSTANCE LED\[6\]\~reg0feeder)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (406:406:406) (467:467:467))
+        (IOPATH datad combout (130:130:130) (120:120:120))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "dffeas")
+    (INSTANCE LED\[6\]\~reg0)
+    (DELAY
+      (ABSOLUTE
+        (PORT clk (1532:1532:1532) (1544:1544:1544))
+        (PORT d (74:74:74) (91:91:91))
+        (IOPATH (posedge clk) q (199:199:199) (199:199:199))
+      )
+    )
+    (TIMINGCHECK
+      (HOLD d (posedge clk) (157:157:157))
+    )
+  )
+)
diff --git a/spectrum.qpf b/spectrum.qpf
new file mode 100644
index 0000000..372e8e4
--- /dev/null
+++ b/spectrum.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 11:41:15  March 30, 2022
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "11:41:15  March 30, 2022"
+
+# Revisions
+
+PROJECT_REVISION = "spectrum"
diff --git a/spectrum.qsf b/spectrum.qsf
new file mode 100644
index 0000000..f25459a
--- /dev/null
+++ b/spectrum.qsf
@@ -0,0 +1,410 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 11:41:15  March 30, 2022
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		spectrum_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone IV E"
+set_global_assignment -name DEVICE EP4CE22F17C6
+set_global_assignment -name TOP_LEVEL_ENTITY spectrum
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:41:15  MARCH 30, 2022"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
+set_global_assignment -name VERILOG_FILE spectrum.v
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+#============================================================
+# CLOCK
+#============================================================
+set_location_assignment PIN_R8 -to CLOCK_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
+
+#============================================================
+# LED
+#============================================================
+set_location_assignment PIN_A15 -to LED[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
+set_location_assignment PIN_A13 -to LED[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
+set_location_assignment PIN_B13 -to LED[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
+set_location_assignment PIN_A11 -to LED[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
+set_location_assignment PIN_D1 -to LED[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4]
+set_location_assignment PIN_F3 -to LED[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5]
+set_location_assignment PIN_B1 -to LED[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6]
+set_location_assignment PIN_L3 -to LED[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7]
+
+#============================================================
+# KEY
+#============================================================
+set_location_assignment PIN_J15 -to KEY[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
+set_location_assignment PIN_E1 -to KEY[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
+
+#============================================================
+# SW
+#============================================================
+set_location_assignment PIN_M1 -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_location_assignment PIN_T8 -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_location_assignment PIN_B9 -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_location_assignment PIN_M15 -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+
+#============================================================
+# SDRAM
+#============================================================
+set_location_assignment PIN_M7 -to DRAM_BA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0]
+set_location_assignment PIN_M6 -to DRAM_BA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1]
+set_location_assignment PIN_R6 -to DRAM_DQM[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[0]
+set_location_assignment PIN_T5 -to DRAM_DQM[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[1]
+set_location_assignment PIN_L2 -to DRAM_RAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
+set_location_assignment PIN_L1 -to DRAM_CAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
+set_location_assignment PIN_L7 -to DRAM_CKE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
+set_location_assignment PIN_R4 -to DRAM_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
+set_location_assignment PIN_C2 -to DRAM_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
+set_location_assignment PIN_P6 -to DRAM_CS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N
+set_location_assignment PIN_G2 -to DRAM_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
+set_location_assignment PIN_G1 -to DRAM_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]
+set_location_assignment PIN_L8 -to DRAM_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2]
+set_location_assignment PIN_K5 -to DRAM_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3]
+set_location_assignment PIN_K2 -to DRAM_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4]
+set_location_assignment PIN_J2 -to DRAM_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5]
+set_location_assignment PIN_J1 -to DRAM_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6]
+set_location_assignment PIN_R7 -to DRAM_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7]
+set_location_assignment PIN_T4 -to DRAM_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8]
+set_location_assignment PIN_T2 -to DRAM_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9]
+set_location_assignment PIN_T3 -to DRAM_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10]
+set_location_assignment PIN_R3 -to DRAM_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11]
+set_location_assignment PIN_R5 -to DRAM_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12]
+set_location_assignment PIN_P3 -to DRAM_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13]
+set_location_assignment PIN_N3 -to DRAM_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14]
+set_location_assignment PIN_K1 -to DRAM_DQ[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15]
+set_location_assignment PIN_P2 -to DRAM_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
+set_location_assignment PIN_N5 -to DRAM_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
+set_location_assignment PIN_N6 -to DRAM_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
+set_location_assignment PIN_M8 -to DRAM_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3]
+set_location_assignment PIN_P8 -to DRAM_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4]
+set_location_assignment PIN_T7 -to DRAM_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5]
+set_location_assignment PIN_N8 -to DRAM_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6]
+set_location_assignment PIN_T6 -to DRAM_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7]
+set_location_assignment PIN_R1 -to DRAM_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8]
+set_location_assignment PIN_P1 -to DRAM_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9]
+set_location_assignment PIN_N2 -to DRAM_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10]
+set_location_assignment PIN_N1 -to DRAM_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
+set_location_assignment PIN_L4 -to DRAM_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12]
+
+#============================================================
+# EPCS
+#============================================================
+set_location_assignment PIN_H2 -to EPCS_DATA0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_DATA0
+set_location_assignment PIN_H1 -to EPCS_DCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_DCLK
+set_location_assignment PIN_D2 -to EPCS_NCSO
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_NCSO
+set_location_assignment PIN_C1 -to EPCS_ASDO
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_ASDO
+
+#============================================================
+# Accelerometer and EEPROM
+#============================================================
+set_location_assignment PIN_F2 -to I2C_SCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SCLK
+set_location_assignment PIN_F1 -to I2C_SDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SDAT
+set_location_assignment PIN_G5 -to G_SENSOR_CS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to G_SENSOR_CS_N
+set_location_assignment PIN_M2 -to G_SENSOR_INT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to G_SENSOR_INT
+
+#============================================================
+# ADC
+#============================================================
+set_location_assignment PIN_A10 -to ADC_CS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS_N
+set_location_assignment PIN_B10 -to ADC_SADDR
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SADDR
+set_location_assignment PIN_B14 -to ADC_SCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCLK
+set_location_assignment PIN_A9 -to ADC_SDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDAT
+
+#============================================================
+# 2x13 GPIO Header
+#============================================================
+set_location_assignment PIN_A14 -to GPIO_2[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[0]
+set_location_assignment PIN_B16 -to GPIO_2[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[1]
+set_location_assignment PIN_C14 -to GPIO_2[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[2]
+set_location_assignment PIN_C16 -to GPIO_2[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[3]
+set_location_assignment PIN_C15 -to GPIO_2[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[4]
+set_location_assignment PIN_D16 -to GPIO_2[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[5]
+set_location_assignment PIN_D15 -to GPIO_2[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[6]
+set_location_assignment PIN_D14 -to GPIO_2[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[7]
+set_location_assignment PIN_F15 -to GPIO_2[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[8]
+set_location_assignment PIN_F16 -to GPIO_2[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[9]
+set_location_assignment PIN_F14 -to GPIO_2[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[10]
+set_location_assignment PIN_G16 -to GPIO_2[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[11]
+set_location_assignment PIN_G15 -to GPIO_2[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[12]
+set_location_assignment PIN_E15 -to GPIO_2_IN[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[0]
+set_location_assignment PIN_E16 -to GPIO_2_IN[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[1]
+set_location_assignment PIN_M16 -to GPIO_2_IN[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[2]
+
+#============================================================
+# GPIO_0, GPIO_0 connect to GPIO Default
+#============================================================
+set_location_assignment PIN_A8 -to GPIO_0_IN[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_IN[0]
+set_location_assignment PIN_D3 -to GPIO_0[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0]
+set_location_assignment PIN_B8 -to GPIO_0_IN[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_IN[1]
+set_location_assignment PIN_C3 -to GPIO_0[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1]
+set_location_assignment PIN_A2 -to GPIO_0[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2]
+set_location_assignment PIN_A3 -to GPIO_0[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3]
+set_location_assignment PIN_B3 -to GPIO_0[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4]
+set_location_assignment PIN_B4 -to GPIO_0[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5]
+set_location_assignment PIN_A4 -to GPIO_0[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6]
+set_location_assignment PIN_B5 -to GPIO_0[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7]
+set_location_assignment PIN_A5 -to GPIO_0[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8]
+set_location_assignment PIN_D5 -to GPIO_0[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9]
+set_location_assignment PIN_B6 -to GPIO_0[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10]
+set_location_assignment PIN_A6 -to GPIO_0[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11]
+set_location_assignment PIN_B7 -to GPIO_0[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12]
+set_location_assignment PIN_D6 -to GPIO_0[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13]
+set_location_assignment PIN_A7 -to GPIO_0[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14]
+set_location_assignment PIN_C6 -to GPIO_0[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15]
+set_location_assignment PIN_C8 -to GPIO_0[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16]
+set_location_assignment PIN_E6 -to GPIO_0[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17]
+set_location_assignment PIN_E7 -to GPIO_0[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18]
+set_location_assignment PIN_D8 -to GPIO_0[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19]
+set_location_assignment PIN_E8 -to GPIO_0[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20]
+set_location_assignment PIN_F8 -to GPIO_0[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21]
+set_location_assignment PIN_F9 -to GPIO_0[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22]
+set_location_assignment PIN_E9 -to GPIO_0[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23]
+set_location_assignment PIN_C9 -to GPIO_0[24]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24]
+set_location_assignment PIN_D9 -to GPIO_0[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25]
+set_location_assignment PIN_E11 -to GPIO_0[26]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26]
+set_location_assignment PIN_E10 -to GPIO_0[27]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27]
+set_location_assignment PIN_C11 -to GPIO_0[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28]
+set_location_assignment PIN_B11 -to GPIO_0[29]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29]
+set_location_assignment PIN_A12 -to GPIO_0[30]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30]
+set_location_assignment PIN_D11 -to GPIO_0[31]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31]
+set_location_assignment PIN_D12 -to GPIO_0[32]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[32]
+set_location_assignment PIN_B12 -to GPIO_0[33]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[33]
+
+#============================================================
+# GPIO_1, GPIO_1 connect to GPIO Default
+#============================================================
+set_location_assignment PIN_T9 -to GPIO_1_IN[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_IN[0]
+set_location_assignment PIN_F13 -to GPIO_1[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0]
+set_location_assignment PIN_R9 -to GPIO_1_IN[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_IN[1]
+set_location_assignment PIN_T15 -to GPIO_1[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1]
+set_location_assignment PIN_T14 -to GPIO_1[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2]
+set_location_assignment PIN_T13 -to GPIO_1[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3]
+set_location_assignment PIN_R13 -to GPIO_1[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4]
+set_location_assignment PIN_T12 -to GPIO_1[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5]
+set_location_assignment PIN_R12 -to GPIO_1[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6]
+set_location_assignment PIN_T11 -to GPIO_1[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7]
+set_location_assignment PIN_T10 -to GPIO_1[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8]
+set_location_assignment PIN_R11 -to GPIO_1[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9]
+set_location_assignment PIN_P11 -to GPIO_1[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10]
+set_location_assignment PIN_R10 -to GPIO_1[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11]
+set_location_assignment PIN_N12 -to GPIO_1[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12]
+set_location_assignment PIN_P9 -to GPIO_1[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13]
+set_location_assignment PIN_N9 -to GPIO_1[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14]
+set_location_assignment PIN_N11 -to GPIO_1[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15]
+set_location_assignment PIN_L16 -to GPIO_1[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16]
+set_location_assignment PIN_K16 -to GPIO_1[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17]
+set_location_assignment PIN_R16 -to GPIO_1[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18]
+set_location_assignment PIN_L15 -to GPIO_1[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19]
+set_location_assignment PIN_P15 -to GPIO_1[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20]
+set_location_assignment PIN_P16 -to GPIO_1[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21]
+set_location_assignment PIN_R14 -to GPIO_1[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22]
+set_location_assignment PIN_N16 -to GPIO_1[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23]
+set_location_assignment PIN_N15 -to GPIO_1[24]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24]
+set_location_assignment PIN_P14 -to GPIO_1[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25]
+set_location_assignment PIN_L14 -to GPIO_1[26]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26]
+set_location_assignment PIN_N14 -to GPIO_1[27]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27]
+set_location_assignment PIN_M10 -to GPIO_1[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28]
+set_location_assignment PIN_L13 -to GPIO_1[29]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29]
+set_location_assignment PIN_J16 -to GPIO_1[30]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30]
+set_location_assignment PIN_K15 -to GPIO_1[31]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31]
+set_location_assignment PIN_J13 -to GPIO_1[32]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[32]
+set_location_assignment PIN_J14 -to GPIO_1[33]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[33]
+
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/spectrum.v b/spectrum.v
new file mode 100644
index 0000000..482ac9a
--- /dev/null
+++ b/spectrum.v
@@ -0,0 +1,14 @@
+module spectrum(
+	input CLOCK_50,
+	output reg[7:0] LED
+);
+
+reg[27:0] counter;
+
+always @(posedge CLOCK_50) 
+begin
+	counter <= counter + 1;
+	LED <= counter[27:21];
+end
+
+endmodule
\ No newline at end of file
diff --git a/spectrum.v.bak b/spectrum.v.bak
new file mode 100644
index 0000000..e69de29