519 lines
17 KiB
Plaintext
519 lines
17 KiB
Plaintext
Analysis & Synthesis report for spectrum
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Wed Mar 30 11:51:29 2022
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Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. Analysis & Synthesis Summary
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3. Analysis & Synthesis Settings
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4. Parallel Compilation
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5. Analysis & Synthesis Source Files Read
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6. Analysis & Synthesis Resource Usage Summary
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7. Analysis & Synthesis Resource Utilization by Entity
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8. Registers Removed During Synthesis
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9. General Register Statistics
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10. Elapsed Time Per Partition
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11. Analysis & Synthesis Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 1991-2013 Altera Corporation
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Altera Program License
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Subscription Agreement, Altera MegaCore Function License
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Agreement, or other applicable license agreement, including,
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without limitation, that your use is for the sole purpose of
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programming logic devices manufactured by Altera and sold by
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Altera or its authorized distributors. Please refer to the
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applicable agreement for further details.
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+---------------------------------------------------------------------------------+
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; Analysis & Synthesis Summary ;
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+------------------------------------+--------------------------------------------+
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; Analysis & Synthesis Status ; Successful - Wed Mar 30 11:51:29 2022 ;
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; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
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; Revision Name ; spectrum ;
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; Top-level Entity Name ; spectrum ;
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; Family ; Cyclone IV E ;
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; Total logic elements ; 35 ;
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; Total combinational functions ; 28 ;
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; Dedicated logic registers ; 35 ;
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; Total registers ; 35 ;
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; Total pins ; 9 ;
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; Total virtual pins ; 0 ;
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; Total memory bits ; 0 ;
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; Embedded Multiplier 9-bit elements ; 0 ;
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; Total PLLs ; 0 ;
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+------------------------------------+--------------------------------------------+
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+--------------------------------------------------------------------------------+
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; Analysis & Synthesis Settings ;
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+--------------------------------------------------------------------------------+
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Option : Device
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Setting : EP4CE22F17C6
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Default Value :
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Option : Top-level entity name
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Setting : spectrum
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Default Value : spectrum
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Option : Family name
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Setting : Cyclone IV E
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Default Value : Cyclone IV GX
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Option : Use smart compilation
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Setting : Off
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Default Value : Off
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Option : Enable parallel Assembler and TimeQuest Timing Analyzer during compilation
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Setting : On
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Default Value : On
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Option : Enable compact report table
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Setting : Off
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Default Value : Off
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Option : Restructure Multiplexers
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Setting : Auto
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Default Value : Auto
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Option : Create Debugging Nodes for IP Cores
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Setting : Off
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Default Value : Off
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Option : Preserve fewer node names
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Setting : On
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Default Value : On
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Option : Disable OpenCore Plus hardware evaluation
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Setting : Off
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Default Value : Off
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Option : Verilog Version
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Setting : Verilog_2001
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Default Value : Verilog_2001
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Option : VHDL Version
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Setting : VHDL_1993
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Default Value : VHDL_1993
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Option : State Machine Processing
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Setting : Auto
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Default Value : Auto
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Option : Safe State Machine
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Setting : Off
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Default Value : Off
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Option : Extract Verilog State Machines
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Setting : On
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Default Value : On
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Option : Extract VHDL State Machines
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Setting : On
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Default Value : On
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Option : Ignore Verilog initial constructs
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Setting : Off
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Default Value : Off
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Option : Iteration limit for constant Verilog loops
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Setting : 5000
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Default Value : 5000
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Option : Iteration limit for non-constant Verilog loops
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Setting : 250
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Default Value : 250
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Option : Add Pass-Through Logic to Inferred RAMs
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Setting : On
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Default Value : On
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Option : Infer RAMs from Raw Logic
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Setting : On
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Default Value : On
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Option : Parallel Synthesis
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Setting : On
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Default Value : On
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Option : DSP Block Balancing
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Setting : Auto
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Default Value : Auto
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Option : NOT Gate Push-Back
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Setting : On
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Default Value : On
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Option : Power-Up Don't Care
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Setting : On
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Default Value : On
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Option : Remove Redundant Logic Cells
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Setting : Off
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Default Value : Off
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Option : Remove Duplicate Registers
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Setting : On
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Default Value : On
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Option : Ignore CARRY Buffers
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Setting : Off
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Default Value : Off
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Option : Ignore CASCADE Buffers
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Setting : Off
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Default Value : Off
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Option : Ignore GLOBAL Buffers
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Setting : Off
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Default Value : Off
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Option : Ignore ROW GLOBAL Buffers
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Setting : Off
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Default Value : Off
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Option : Ignore LCELL Buffers
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Setting : Off
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Default Value : Off
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Option : Ignore SOFT Buffers
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Setting : On
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Default Value : On
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Option : Limit AHDL Integers to 32 Bits
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Setting : Off
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Default Value : Off
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Option : Optimization Technique
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Setting : Balanced
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Default Value : Balanced
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Option : Carry Chain Length
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Setting : 70
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Default Value : 70
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Option : Auto Carry Chains
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Setting : On
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Default Value : On
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Option : Auto Open-Drain Pins
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Setting : On
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Default Value : On
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Option : Perform WYSIWYG Primitive Resynthesis
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Setting : Off
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Default Value : Off
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Option : Auto ROM Replacement
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Setting : On
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Default Value : On
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Option : Auto RAM Replacement
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Setting : On
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Default Value : On
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Option : Auto DSP Block Replacement
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Setting : On
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Default Value : On
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Option : Auto Shift Register Replacement
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Setting : Auto
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Default Value : Auto
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Option : Allow Shift Register Merging across Hierarchies
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Setting : Auto
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Default Value : Auto
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Option : Auto Clock Enable Replacement
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Setting : On
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Default Value : On
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Option : Strict RAM Replacement
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Setting : Off
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Default Value : Off
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Option : Allow Synchronous Control Signals
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Setting : On
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Default Value : On
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Option : Force Use of Synchronous Clear Signals
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Setting : Off
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Default Value : Off
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Option : Auto RAM Block Balancing
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Setting : On
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Default Value : On
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Option : Auto RAM to Logic Cell Conversion
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Setting : Off
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Default Value : Off
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Option : Auto Resource Sharing
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Setting : Off
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Default Value : Off
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Option : Allow Any RAM Size For Recognition
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Setting : Off
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Default Value : Off
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Option : Allow Any ROM Size For Recognition
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Setting : Off
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Default Value : Off
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Option : Allow Any Shift Register Size For Recognition
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Setting : Off
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Default Value : Off
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Option : Use LogicLock Constraints during Resource Balancing
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Setting : On
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Default Value : On
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Option : Ignore translate_off and synthesis_off directives
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Setting : Off
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Default Value : Off
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Option : Timing-Driven Synthesis
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Setting : On
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Default Value : On
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Option : Report Parameter Settings
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Setting : On
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Default Value : On
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Option : Report Source Assignments
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Setting : On
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Default Value : On
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Option : Report Connectivity Checks
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Setting : On
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Default Value : On
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Option : Ignore Maximum Fan-Out Assignments
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Setting : Off
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Default Value : Off
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Option : Synchronization Register Chain Length
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Setting : 2
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Default Value : 2
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Option : PowerPlay Power Optimization
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Setting : Normal compilation
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Default Value : Normal compilation
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Option : HDL message level
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Setting : Level2
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Default Value : Level2
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Option : Suppress Register Optimization Related Messages
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Setting : Off
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Default Value : Off
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Option : Number of Removed Registers Reported in Synthesis Report
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Setting : 5000
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Default Value : 5000
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Option : Number of Swept Nodes Reported in Synthesis Report
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Setting : 5000
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Default Value : 5000
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Option : Number of Inverted Registers Reported in Synthesis Report
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Setting : 100
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Default Value : 100
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Option : Clock MUX Protection
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Setting : On
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Default Value : On
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Option : Auto Gated Clock Conversion
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Setting : Off
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Default Value : Off
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Option : Block Design Naming
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Setting : Auto
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Default Value : Auto
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Option : SDC constraint protection
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Setting : Off
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Default Value : Off
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Option : Synthesis Effort
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Setting : Auto
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Default Value : Auto
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Option : Shift Register Replacement - Allow Asynchronous Clear Signal
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Setting : On
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Default Value : On
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Option : Pre-Mapping Resynthesis Optimization
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Setting : Off
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Default Value : Off
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Option : Analysis & Synthesis Message Level
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Setting : Medium
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Default Value : Medium
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Option : Disable Register Merging Across Hierarchies
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Setting : Auto
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Default Value : Auto
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Option : Resource Aware Inference For Block RAM
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Setting : On
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Default Value : On
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Option : Synthesis Seed
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Setting : 1
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Default Value : 1
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+--------------------------------------------------------------------------------+
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Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
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+-------------------------------------+
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; Parallel Compilation ;
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+----------------------------+--------+
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; Processors ; Number ;
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+----------------------------+--------+
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; Number detected on machine ; 12 ;
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; Maximum allowed ; 1 ;
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+----------------------------+--------+
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+--------------------------------------------------------------------------------+
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; Analysis & Synthesis Source Files Read ;
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+--------------------------------------------------------------------------------+
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File Name with User-Entered Path : spectrum.v
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Used in Netlist : yes
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File Type : User Verilog HDL File
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File Name with Absolute Path : /home/benny/work/fpga/projects/spectrum.v
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Library :
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+--------------------------------------------------------------------------------+
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+--------------------------------------------------------------+
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; Analysis & Synthesis Resource Usage Summary ;
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+---------------------------------------------+----------------+
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; Resource ; Usage ;
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+---------------------------------------------+----------------+
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; Estimated Total logic elements ; 35 ;
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; ; ;
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; Total combinational functions ; 28 ;
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; Logic element usage by number of LUT inputs ; ;
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; -- 4 input functions ; 0 ;
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; -- 3 input functions ; 1 ;
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; -- <=2 input functions ; 27 ;
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; ; ;
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; Logic elements by mode ; ;
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; -- normal mode ; 2 ;
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; -- arithmetic mode ; 26 ;
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; ; ;
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; Total registers ; 35 ;
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; -- Dedicated logic registers ; 35 ;
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; -- I/O registers ; 0 ;
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; ; ;
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; I/O pins ; 9 ;
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; Embedded Multiplier 9-bit elements ; 0 ;
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; Maximum fan-out node ; CLOCK_50~input ;
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; Maximum fan-out ; 35 ;
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; Total fan-out ; 141 ;
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; Average fan-out ; 1.74 ;
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+---------------------------------------------+----------------+
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+--------------------------------------------------------------------------------+
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; Analysis & Synthesis Resource Utilization by Entity ;
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+--------------------------------------------------------------------------------+
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Compilation Hierarchy Node : |spectrum
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LC Combinationals : 28 (28)
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LC Registers : 35 (35)
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Memory Bits : 0
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DSP Elements : 0
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DSP 9x9 : 0
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DSP 18x18 : 0
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Pins : 9
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Virtual Pins : 0
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Full Hierarchy Name : |spectrum
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Library Name : work
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+--------------------------------------------------------------------------------+
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Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
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+--------------------------------------------------------------------------------+
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; Registers Removed During Synthesis ;
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+---------------------------------------+----------------------------------------+
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; Register name ; Reason for Removal ;
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+---------------------------------------+----------------------------------------+
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; LED[7]~reg0 ; Stuck at GND due to stuck port data_in ;
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; Total Number of Removed Registers = 1 ; ;
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+---------------------------------------+----------------------------------------+
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+------------------------------------------------------+
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; General Register Statistics ;
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+----------------------------------------------+-------+
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; Statistic ; Value ;
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+----------------------------------------------+-------+
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; Total registers ; 35 ;
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; Number of registers using Synchronous Clear ; 0 ;
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; Number of registers using Synchronous Load ; 0 ;
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; Number of registers using Asynchronous Clear ; 0 ;
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; Number of registers using Asynchronous Load ; 0 ;
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; Number of registers using Clock Enable ; 0 ;
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; Number of registers using Preset ; 0 ;
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+----------------------------------------------+-------+
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+-------------------------------+
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; Elapsed Time Per Partition ;
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+----------------+--------------+
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; Partition Name ; Elapsed Time ;
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+----------------+--------------+
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; Top ; 00:00:00 ;
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+----------------+--------------+
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+-------------------------------+
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; Analysis & Synthesis Messages ;
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+-------------------------------+
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Info: *******************************************************************
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Info: Running Quartus II 32-bit Analysis & Synthesis
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Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
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Info: Processing started: Wed Mar 30 11:51:28 2022
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Info: Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum
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Warning (20028): Parallel compilation is not licensed and has been disabled
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Info (12021): Found 1 design units, including 1 entities, in source file spectrum.v
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Info (12023): Found entity 1: spectrum
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Info (12127): Elaborating entity "spectrum" for the top level hierarchy
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Warning (10230): Verilog HDL assignment warning at spectrum.v(10): truncated value with size 32 to match size of target (28)
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Warning (13024): Output pins are stuck at VCC or GND
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Warning (13410): Pin "LED[7]" is stuck at GND
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Info (286030): Timing-Driven Synthesis is running
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Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
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Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
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Info (21057): Implemented 44 device resources after synthesis - the final resource count might be different
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Info (21058): Implemented 1 input pins
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Info (21059): Implemented 8 output pins
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Info (21061): Implemented 35 logic cells
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Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 4 warnings
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Info: Peak virtual memory: 388 megabytes
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Info: Processing ended: Wed Mar 30 11:51:29 2022
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Info: Elapsed time: 00:00:01
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Info: Total CPU time (on all processors): 00:00:01
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