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Added ROM based LED patterns

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This commit is contained in:
Adrian Scripca
2022-03-30 12:47:42 +03:00
parent fa29e9f3f6
commit c59b02b186
95 changed files with 13813 additions and 13354 deletions
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db/altsyncram_ro91.tdf
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--altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" ENABLE_RUNTIME_MOD="NO" INIT_FILE="led_patterns.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=8 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="CLOCK0" WIDTH_A=8 WIDTH_BYTEENA_A=1 WIDTHAD_A=3 address_a clock0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 13.1 cbx_altsyncram 2013:10:17:09:48:19:SJ cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_lpm_mux 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ cbx_stratixiii 2013:10:17:09:48:19:SJ cbx_stratixv 2013:10:17:09:48:19:SJ cbx_util_mgl 2013:10:17:09:48:19:SJ VERSION_END
-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
--synthesis_resources = M9K 1
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
SUBDESIGN altsyncram_ro91
(
address_a[2..0] : input;
clock0 : input;
q_a[7..0] : output;
)
VARIABLE
ram_block1a0 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 3,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 7,
PORT_A_LOGICAL_RAM_DEPTH = 8,
PORT_A_LOGICAL_RAM_WIDTH = 8,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a1 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 3,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 1,
PORT_A_LAST_ADDRESS = 7,
PORT_A_LOGICAL_RAM_DEPTH = 8,
PORT_A_LOGICAL_RAM_WIDTH = 8,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a2 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 3,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 2,
PORT_A_LAST_ADDRESS = 7,
PORT_A_LOGICAL_RAM_DEPTH = 8,
PORT_A_LOGICAL_RAM_WIDTH = 8,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a3 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 3,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 3,
PORT_A_LAST_ADDRESS = 7,
PORT_A_LOGICAL_RAM_DEPTH = 8,
PORT_A_LOGICAL_RAM_WIDTH = 8,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a4 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 3,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 4,
PORT_A_LAST_ADDRESS = 7,
PORT_A_LOGICAL_RAM_DEPTH = 8,
PORT_A_LOGICAL_RAM_WIDTH = 8,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a5 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 3,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 5,
PORT_A_LAST_ADDRESS = 7,
PORT_A_LOGICAL_RAM_DEPTH = 8,
PORT_A_LOGICAL_RAM_WIDTH = 8,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a6 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 3,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 6,
PORT_A_LAST_ADDRESS = 7,
PORT_A_LOGICAL_RAM_DEPTH = 8,
PORT_A_LOGICAL_RAM_WIDTH = 8,
RAM_BLOCK_TYPE = "AUTO"
);
ram_block1a7 : cycloneive_ram_block
WITH (
CLK0_CORE_CLOCK_ENABLE = "none",
CLK0_INPUT_CLOCK_ENABLE = "none",
CLK0_OUTPUT_CLOCK_ENABLE = "none",
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "led_patterns.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "rom",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 3,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "clock0",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 7,
PORT_A_LAST_ADDRESS = 7,
PORT_A_LOGICAL_RAM_DEPTH = 8,
PORT_A_LOGICAL_RAM_WIDTH = 8,
RAM_BLOCK_TYPE = "AUTO"
);
address_a_wire[2..0] : WIRE;
BEGIN
ram_block1a[7..0].clk0 = clock0;
ram_block1a[7..0].portaaddr[] = ( address_a_wire[2..0]);
ram_block1a[7..0].portare = B"11111111";
address_a_wire[] = address_a[];
q_a[] = ( ram_block1a[7..0].portadataout[0..0]);
END;
--VALID FILE
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648630297528 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648630297529 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 11:51:37 2022 " "Processing started: Wed Mar 30 11:51:37 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648630297529 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1648630297529 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1648630297529 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1648630298448 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1648630298474 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "389 " "Peak virtual memory: 389 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648630298719 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 11:51:38 2022 " "Processing ended: Wed Mar 30 11:51:38 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648630298719 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648630298719 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648630298719 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1648630298719 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648633116429 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648633116430 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 12:38:36 2022 " "Processing started: Wed Mar 30 12:38:36 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648633116430 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1648633116430 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1648633116430 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1648633117331 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1648633117357 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "393 " "Peak virtual memory: 393 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648633117592 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 12:38:37 2022 " "Processing ended: Wed Mar 30 12:38:37 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648633117592 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648633117592 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648633117592 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1648633117592 ""}
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<?xml version="1.0" ?>
<LOG_ROOT>
<PROJECT NAME="spectrum">
<CBX_INST_ENTRY INSTANCE_NAME="|spectrum|rom0:rom|altsyncram:altsyncram_component" CBX_FILE_NAME="altsyncram_ro91.tdf"/>
</PROJECT>
</LOG_ROOT>
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648630303095 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648630303096 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 11:51:42 2022 " "Processing started: Wed Mar 30 11:51:42 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648630303096 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648630303096 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648630303097 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630303387 ""}
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{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_fast.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_fast.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630303428 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630303448 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630303469 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630303488 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_v_fast.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630303508 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_v.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_v.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630303527 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "352 " "Peak virtual memory: 352 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648630303559 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 11:51:43 2022 " "Processing ended: Wed Mar 30 11:51:43 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648630303559 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648630303559 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648630303559 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648630303559 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648633122029 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648633122030 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 12:38:41 2022 " "Processing started: Wed Mar 30 12:38:41 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648633122030 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648633122030 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648633122031 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648633122334 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648633122355 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_fast.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_fast.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648633122376 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648633122396 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648633122418 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648633122437 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_v_fast.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648633122456 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_v.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_v.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648633122475 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "344 " "Peak virtual memory: 344 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648633122507 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 12:38:42 2022 " "Processing ended: Wed Mar 30 12:38:42 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648633122507 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648633122507 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648633122507 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648633122507 ""}
db/spectrum.fit.qmsg
+48 -47
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db/spectrum.hier_info
+111 -44
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@@ -1,47 +1,114 @@
|spectrum
CLOCK_50 => LED[0]~reg0.CLK
CLOCK_50 => LED[1]~reg0.CLK
CLOCK_50 => LED[2]~reg0.CLK
CLOCK_50 => LED[3]~reg0.CLK
CLOCK_50 => LED[4]~reg0.CLK
CLOCK_50 => LED[5]~reg0.CLK
CLOCK_50 => LED[6]~reg0.CLK
CLOCK_50 => LED[7]~reg0.CLK
CLOCK_50 => counter[0].CLK
CLOCK_50 => counter[1].CLK
CLOCK_50 => counter[2].CLK
CLOCK_50 => counter[3].CLK
CLOCK_50 => counter[4].CLK
CLOCK_50 => counter[5].CLK
CLOCK_50 => counter[6].CLK
CLOCK_50 => counter[7].CLK
CLOCK_50 => counter[8].CLK
CLOCK_50 => counter[9].CLK
CLOCK_50 => counter[10].CLK
CLOCK_50 => counter[11].CLK
CLOCK_50 => counter[12].CLK
CLOCK_50 => counter[13].CLK
CLOCK_50 => counter[14].CLK
CLOCK_50 => counter[15].CLK
CLOCK_50 => counter[16].CLK
CLOCK_50 => counter[17].CLK
CLOCK_50 => counter[18].CLK
CLOCK_50 => counter[19].CLK
CLOCK_50 => counter[20].CLK
CLOCK_50 => counter[21].CLK
CLOCK_50 => counter[22].CLK
CLOCK_50 => counter[23].CLK
CLOCK_50 => counter[24].CLK
CLOCK_50 => counter[25].CLK
CLOCK_50 => counter[26].CLK
CLOCK_50 => counter[27].CLK
LED[0] <= LED[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
LED[1] <= LED[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
LED[2] <= LED[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
LED[3] <= LED[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
LED[4] <= LED[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
LED[5] <= LED[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
LED[6] <= LED[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
LED[7] <= LED[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
CLOCK_50 => CLOCK_50.IN1
LED[0] <= rom0:rom.q
LED[1] <= rom0:rom.q
LED[2] <= rom0:rom.q
LED[3] <= rom0:rom.q
LED[4] <= rom0:rom.q
LED[5] <= rom0:rom.q
LED[6] <= rom0:rom.q
LED[7] <= rom0:rom.q
|spectrum|rom0:rom
address[0] => address[0].IN1
address[1] => address[1].IN1
address[2] => address[2].IN1
clock => clock.IN1
q[0] <= altsyncram:altsyncram_component.q_a
q[1] <= altsyncram:altsyncram_component.q_a
q[2] <= altsyncram:altsyncram_component.q_a
q[3] <= altsyncram:altsyncram_component.q_a
q[4] <= altsyncram:altsyncram_component.q_a
q[5] <= altsyncram:altsyncram_component.q_a
q[6] <= altsyncram:altsyncram_component.q_a
q[7] <= altsyncram:altsyncram_component.q_a
|spectrum|rom0:rom|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_ro91:auto_generated.address_a[0]
address_a[1] => altsyncram_ro91:auto_generated.address_a[1]
address_a[2] => altsyncram_ro91:auto_generated.address_a[2]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_ro91:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_ro91:auto_generated.q_a[0]
q_a[1] <= altsyncram_ro91:auto_generated.q_a[1]
q_a[2] <= altsyncram_ro91:auto_generated.q_a[2]
q_a[3] <= altsyncram_ro91:auto_generated.q_a[3]
q_a[4] <= altsyncram_ro91:auto_generated.q_a[4]
q_a[5] <= altsyncram_ro91:auto_generated.q_a[5]
q_a[6] <= altsyncram_ro91:auto_generated.q_a[6]
q_a[7] <= altsyncram_ro91:auto_generated.q_a[7]
q_b[0] <= <GND>
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>
|spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT
db/spectrum.hif
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db/spectrum.ipinfo
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db/spectrum.lpc.html
+32
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@@ -15,4 +15,36 @@
<TH>Input only Bidir</TH>
<TH>Output only Bidir</TH>
</TR>
<TR >
<TD >rom|altsyncram_component|auto_generated</TD>
<TD >4</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >8</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >rom</TD>
<TD >4</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >8</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
</TABLE>
db/spectrum.lpc.rdb
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db/spectrum.lpc.txt
+29
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@@ -1,5 +1,34 @@
+--------------------------------------------------------------------------------+
; Legal Partition Candidates ;
+--------------------------------------------------------------------------------+
Hierarchy : rom|altsyncram_component|auto_generated
Input : 4
Constant Input : 0
Unused Input : 0
Floating Input : 0
Output : 8
Constant Output : 0
Unused Output : 0
Floating Output : 0
Bidir : 0
Constant Bidir : 0
Unused Bidir : 0
Input only Bidir : 0
Output only Bidir : 0
Hierarchy : rom
Input : 4
Constant Input : 0
Unused Input : 0
Floating Input : 0
Output : 8
Constant Output : 0
Unused Output : 0
Floating Output : 0
Bidir : 0
Constant Bidir : 0
Unused Bidir : 0
Input only Bidir : 0
Output only Bidir : 0
+--------------------------------------------------------------------------------+
db/spectrum.map.bpm
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db/spectrum.map.cdb
BIN
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db/spectrum.map.hdb
BIN
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db/spectrum.map.kpt
BIN
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db/spectrum.map.qmsg
+19 -12
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@@ -1,12 +1,19 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648630288558 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648630288559 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 11:51:28 2022 " "Processing started: Wed Mar 30 11:51:28 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648630288559 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648630288559 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum " "Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648630288559 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648630288726 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spectrum.v 1 1 " "Found 1 design units, including 1 entities, in source file spectrum.v" { { "Info" "ISGN_ENTITY_NAME" "1 spectrum " "Found entity 1: spectrum" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648630288788 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648630288788 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "spectrum " "Elaborating entity \"spectrum\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1648630288838 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 28 spectrum.v(10) " "Verilog HDL assignment warning at spectrum.v(10): truncated value with size 32 to match size of target (28)" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 10 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1648630288840 "|spectrum"}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[7\] GND " "Pin \"LED\[7\]\" is stuck at GND" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 8 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648630289171 "|spectrum|LED[7]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1648630289171 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1648630289264 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1648630289457 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648630289457 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "44 " "Implemented 44 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Implemented 1 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1648630289496 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1648630289496 ""} { "Info" "ICUT_CUT_TM_LCELLS" "35 " "Implemented 35 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1648630289496 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1648630289496 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "388 " "Peak virtual memory: 388 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648630289503 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 11:51:29 2022 " "Processing ended: Wed Mar 30 11:51:29 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648630289503 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648630289503 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648630289503 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648630289503 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648633107075 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648633107076 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 12:38:26 2022 " "Processing started: Wed Mar 30 12:38:26 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648633107076 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648633107076 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum " "Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648633107076 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648633107239 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spectrum.v 1 1 " "Found 1 design units, including 1 entities, in source file spectrum.v" { { "Info" "ISGN_ENTITY_NAME" "1 spectrum " "Found entity 1: spectrum" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648633107303 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648633107303 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom0.v 1 1 " "Found 1 design units, including 1 entities, in source file rom0.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom0 " "Found entity 1: rom0" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648633107306 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648633107306 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "spectrum " "Elaborating entity \"spectrum\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1648633107357 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 21 spectrum.v(19) " "Verilog HDL assignment warning at spectrum.v(19): truncated value with size 32 to match size of target (21)" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 19 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1648633107359 "|spectrum"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 spectrum.v(21) " "Verilog HDL assignment warning at spectrum.v(21): truncated value with size 32 to match size of target (3)" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 21 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1648633107359 "|spectrum"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom0 rom0:rom " "Elaborating entity \"rom0\" for hierarchy \"rom0:rom\"" { } { { "spectrum.v" "rom" { Text "/home/benny/work/fpga/projects/spectrum.v" 14 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107369 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram rom0:rom\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "altsyncram_component" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107416 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "rom0:rom\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rom0:rom\|altsyncram:altsyncram_component " "Instantiated megafunction \"rom0:rom\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file led_patterns.mif " "Parameter \"init_file\" = \"led_patterns.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 8 " "Parameter \"numwords_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 3 " "Parameter \"widthad_a\" = \"3\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} } { { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648633107417 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_ro91.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_ro91.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_ro91 " "Found entity 1: altsyncram_ro91" { } { { "db/altsyncram_ro91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_ro91.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648633107463 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648633107463 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_ro91 rom0:rom\|altsyncram:altsyncram_component\|altsyncram_ro91:auto_generated " "Elaborating entity \"altsyncram_ro91\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_ro91:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107464 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1648633107974 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1648633108175 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648633108175 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "71 " "Implemented 71 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Implemented 1 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1648633108217 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1648633108217 ""} { "Info" "ICUT_CUT_TM_LCELLS" "54 " "Implemented 54 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1648633108217 ""} { "Info" "ICUT_CUT_TM_RAMS" "8 " "Implemented 8 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Quartus II" 0 -1 1648633108217 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1648633108217 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "384 " "Peak virtual memory: 384 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648633108224 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 12:38:28 2022 " "Processing ended: Wed Mar 30 12:38:28 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648633108224 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648633108224 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648633108224 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648633108224 ""}
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648630300061 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300062 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 11:51:39 2022 " "Processing started: Wed Mar 30 11:51:39 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648630300062 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648630300062 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta spectrum -c spectrum " "Command: quartus_sta spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648630300062 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1648630300090 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648630300188 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648630300189 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648630300231 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648630300231 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "spectrum.sdc " "Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1648630300423 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1648630300423 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300424 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300424 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1648630300550 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300550 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1648630300551 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1648630300556 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648630300564 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648630300564 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.606 " "Worst-case setup slack is -1.606" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300565 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300565 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.606 -30.234 CLOCK_50 " " -1.606 -30.234 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300565 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630300565 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.360 " "Worst-case hold slack is 0.360" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300566 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300566 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.360 0.000 CLOCK_50 " " 0.360 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300566 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630300566 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648630300566 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648630300567 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300567 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300567 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -38.000 CLOCK_50 " " -3.000 -38.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300567 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630300567 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648630300582 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1648630300605 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1648630300970 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300986 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648630300988 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648630300988 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.275 " "Worst-case setup slack is -1.275" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300989 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300989 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.275 -22.690 CLOCK_50 " " -1.275 -22.690 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300989 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630300989 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.319 " "Worst-case hold slack is 0.319" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300990 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300990 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.319 0.000 CLOCK_50 " " 0.319 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300990 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630300990 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648630300991 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648630300992 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300993 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300993 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -38.000 CLOCK_50 " " -3.000 -38.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300993 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630300993 ""}
{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648630301008 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648630301128 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648630301129 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648630301129 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.500 " "Worst-case setup slack is -0.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630301130 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630301130 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.500 -4.764 CLOCK_50 " " -0.500 -4.764 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630301130 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630301130 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.193 " "Worst-case hold slack is 0.193" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630301132 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630301132 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.193 0.000 CLOCK_50 " " 0.193 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630301132 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630301132 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648630301133 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648630301135 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630301136 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630301136 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -48.277 CLOCK_50 " " -3.000 -48.277 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630301136 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630301136 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648630301431 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648630301431 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "412 " "Peak virtual memory: 412 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648630301464 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 11:51:41 2022 " "Processing ended: Wed Mar 30 11:51:41 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648630301464 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648630301464 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648630301464 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648630301464 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648633118951 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648633118952 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 12:38:38 2022 " "Processing started: Wed Mar 30 12:38:38 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648633118952 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648633118952 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta spectrum -c spectrum " "Command: quartus_sta spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648633118952 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1648633118980 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648633119080 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648633119082 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648633119126 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648633119126 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "spectrum.sdc " "Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1648633119323 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1648633119324 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119325 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119325 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1648633119451 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119452 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1648633119452 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1648633119457 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648633119465 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648633119465 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.763 " "Worst-case setup slack is -2.763" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119466 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119466 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.763 -43.394 CLOCK_50 " " -2.763 -43.394 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119466 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648633119466 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.343 " "Worst-case hold slack is 0.343" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119466 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119466 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.343 0.000 CLOCK_50 " " 0.343 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119466 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648633119466 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648633119467 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648633119468 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119468 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119468 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -46.633 CLOCK_50 " " -3.000 -46.633 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119468 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648633119468 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648633119483 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1648633119506 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1648633119876 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119892 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648633119894 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648633119894 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.331 " "Worst-case setup slack is -2.331" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119895 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119895 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.331 -34.994 CLOCK_50 " " -2.331 -34.994 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119895 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648633119895 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.299 " "Worst-case hold slack is 0.299" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119896 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119896 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.299 0.000 CLOCK_50 " " 0.299 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119896 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648633119896 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648633119897 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648633119898 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119899 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119899 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -46.624 CLOCK_50 " " -3.000 -46.624 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119899 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648633119899 ""}
{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648633119916 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648633120038 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648633120038 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648633120038 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.122 " "Worst-case setup slack is -1.122" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633120040 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633120040 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.122 -9.363 CLOCK_50 " " -1.122 -9.363 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633120040 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648633120040 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.178 " "Worst-case hold slack is 0.178" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633120043 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633120043 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.178 0.000 CLOCK_50 " " 0.178 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633120043 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648633120043 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648633120045 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648633120047 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633120049 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633120049 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -45.480 CLOCK_50 " " -3.000 -45.480 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633120049 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648633120049 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648633120349 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648633120349 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "415 " "Peak virtual memory: 415 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648633120383 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 12:38:40 2022 " "Processing ended: Wed Mar 30 12:38:40 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648633120383 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648633120383 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648633120383 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648633120383 ""}
db/spectrum.sta.rdb
BIN
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db/spectrum.sta_cmp.6_slow_1200mv_85c.tdb
BIN
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db/spectrum.tiscmp.fast_1200mv_0c.ddb
BIN
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db/spectrum.tiscmp.slow_1200mv_0c.ddb
BIN
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db/spectrum.tiscmp.slow_1200mv_85c.ddb
BIN
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db/spectrum.vpr.ammdb
BIN
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greybox_tmp/cbx_args.txt
+16
View File
@@ -0,0 +1,16 @@
ADDRESS_ACLR_A=NONE
CLOCK_ENABLE_INPUT_A=BYPASS
CLOCK_ENABLE_OUTPUT_A=BYPASS
INIT_FILE=led_patterns.mif
INTENDED_DEVICE_FAMILY="Cyclone IV E"
NUMWORDS_A=8
OPERATION_MODE=ROM
OUTDATA_ACLR_A=NONE
OUTDATA_REG_A=CLOCK0
WIDTHAD_A=3
WIDTH_A=8
WIDTH_BYTEENA_A=1
DEVICE_FAMILY="Cyclone IV E"
address_a
clock0
q_a
incremental_db/compiled_partitions/spectrum.root_partition.cmp.ammdb
BIN
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incremental_db/compiled_partitions/spectrum.root_partition.cmp.cdb
BIN
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incremental_db/compiled_partitions/spectrum.root_partition.cmp.hdb
BIN
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incremental_db/compiled_partitions/spectrum.root_partition.cmp.rcfdb
BIN
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incremental_db/compiled_partitions/spectrum.root_partition.map.cdb
BIN
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incremental_db/compiled_partitions/spectrum.root_partition.map.dpi
BIN
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incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.cdb
BIN
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incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hdb
BIN
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incremental_db/compiled_partitions/spectrum.root_partition.map.hdb
BIN
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incremental_db/compiled_partitions/spectrum.root_partition.map.kpt
BIN
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led_patterns.mif
+31
View File
@@ -0,0 +1,31 @@
-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II generated Memory Initialization File (.mif)
WIDTH=8;
DEPTH=8;
ADDRESS_RADIX=UNS;
DATA_RADIX=UNS;
CONTENT BEGIN
0 : 129;
1 : 66;
2 : 36;
[3..4] : 24;
5 : 36;
6 : 66;
7 : 129;
END;
output_files/greybox_tmp/cbx_args.txt
+16
View File
@@ -0,0 +1,16 @@
ADDRESS_ACLR_A=NONE
CLOCK_ENABLE_INPUT_A=BYPASS
CLOCK_ENABLE_OUTPUT_A=BYPASS
INIT_FILE=
INTENDED_DEVICE_FAMILY="Cyclone IV E"
NUMWORDS_A=8
OPERATION_MODE=ROM
OUTDATA_ACLR_A=NONE
OUTDATA_REG_A=CLOCK0
WIDTHAD_A=3
WIDTH_A=8
WIDTH_BYTEENA_A=1
DEVICE_FAMILY="Cyclone IV E"
address_a
clock0
q_a
output_files/led_patterns.mif
+32
View File
@@ -0,0 +1,32 @@
-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II generated Memory Initialization File (.mif)
WIDTH=8;
DEPTH=8;
ADDRESS_RADIX=UNS;
DATA_RADIX=UNS;
CONTENT BEGIN
0 : 129;
1 : 66;
2 : 36;
3 : 24;
4 : 36;
5 : 66;
6 : 129;
7 : 255;
END;
output_files/spectrum.asm.rpt
+7 -7
View File
@@ -1,5 +1,5 @@
Assembler report for spectrum
Wed Mar 30 11:51:38 2022
Wed Mar 30 12:38:37 2022
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
@@ -37,7 +37,7 @@ applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Wed Mar 30 11:51:38 2022 ;
; Assembler Status ; Successful - Wed Mar 30 12:38:37 2022 ;
; Revision Name ; spectrum ;
; Top-level Entity Name ; spectrum ;
; Family ; Cyclone IV E ;
@@ -162,8 +162,8 @@ Default Value : On
; Option ; Setting ;
+----------------+-----------------------+
; Device ; EP4CE22F17C6 ;
; JTAG usercode ; 0x00138B42 ;
; Checksum ; 0x00138B42 ;
; JTAG usercode ; 0x00139765 ;
; Checksum ; 0x00139765 ;
+----------------+-----------------------+
@@ -173,13 +173,13 @@ Default Value : On
Info: *******************************************************************
Info: Running Quartus II 32-bit Assembler
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
Info: Processing started: Wed Mar 30 11:51:37 2022
Info: Processing started: Wed Mar 30 12:38:36 2022
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 389 megabytes
Info: Processing ended: Wed Mar 30 11:51:38 2022
Info: Peak virtual memory: 393 megabytes
Info: Processing ended: Wed Mar 30 12:38:37 2022
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
output_files/spectrum.done
+1 -1
View File
@@ -1 +1 @@
Wed Mar 30 11:51:43 2022
Wed Mar 30 12:38:42 2022
output_files/spectrum.eda.rpt
+5 -5
View File
@@ -1,5 +1,5 @@
EDA Netlist Writer report for spectrum
Wed Mar 30 11:51:43 2022
Wed Mar 30 12:38:42 2022
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
@@ -36,7 +36,7 @@ applicable agreement for further details.
+-------------------------------------------------------------------+
; EDA Netlist Writer Summary ;
+---------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Wed Mar 30 11:51:43 2022 ;
; EDA Netlist Writer Status ; Successful - Wed Mar 30 12:38:42 2022 ;
; Revision Name ; spectrum ;
; Top-level Entity Name ; spectrum ;
; Family ; Cyclone IV E ;
@@ -88,7 +88,7 @@ applicable agreement for further details.
Info: *******************************************************************
Info: Running Quartus II 32-bit EDA Netlist Writer
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
Info: Processing started: Wed Mar 30 11:51:42 2022
Info: Processing started: Wed Mar 30 12:38:41 2022
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum
Info (204019): Generated file spectrum_6_1200mv_85c_slow.vo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file spectrum_6_1200mv_0c_slow.vo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool
@@ -99,8 +99,8 @@ Info (204019): Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder "/home/b
Info (204019): Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file spectrum_v.sdo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool
Info: Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 352 megabytes
Info: Processing ended: Wed Mar 30 11:51:43 2022
Info: Peak virtual memory: 344 megabytes
Info: Processing ended: Wed Mar 30 12:38:42 2022
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
output_files/spectrum.fit.rpt
+295 -196
View File
@@ -1,5 +1,5 @@
Fitter report for spectrum
Wed Mar 30 11:51:35 2022
Wed Mar 30 12:38:34 2022
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
@@ -29,19 +29,21 @@ Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
21. Control Signals
22. Global & Other Fast Signals
23. Non-Global High Fan-Out Signals
24. Routing Usage Summary
25. LAB Logic Elements
26. LAB-wide Signals
27. LAB Signals Sourced
28. LAB Signals Sourced Out
29. LAB Distinct Inputs
30. I/O Rules Summary
31. I/O Rules Details
32. I/O Rules Matrix
33. Fitter Device Options
34. Operating Settings and Conditions
35. Fitter Messages
36. Fitter Suppressed Messages
24. Fitter RAM Summary
25. |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ALTSYNCRAM
26. Routing Usage Summary
27. LAB Logic Elements
28. LAB-wide Signals
29. LAB Signals Sourced
30. LAB Signals Sourced Out
31. LAB Distinct Inputs
32. I/O Rules Summary
33. I/O Rules Details
34. I/O Rules Matrix
35. Fitter Device Options
36. Operating Settings and Conditions
37. Fitter Messages
38. Fitter Suppressed Messages
@@ -67,20 +69,20 @@ applicable agreement for further details.
+---------------------------------------------------------------------------------+
; Fitter Summary ;
+------------------------------------+--------------------------------------------+
; Fitter Status ; Successful - Wed Mar 30 11:51:35 2022 ;
; Fitter Status ; Successful - Wed Mar 30 12:38:34 2022 ;
; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
; Revision Name ; spectrum ;
; Top-level Entity Name ; spectrum ;
; Family ; Cyclone IV E ;
; Device ; EP4CE22F17C6 ;
; Timing Models ; Final ;
; Total logic elements ; 35 / 22,320 ( < 1 % ) ;
; Total combinational functions ; 28 / 22,320 ( < 1 % ) ;
; Dedicated logic registers ; 35 / 22,320 ( < 1 % ) ;
; Total registers ; 35 ;
; Total logic elements ; 33 / 22,320 ( < 1 % ) ;
; Total combinational functions ; 33 / 22,320 ( < 1 % ) ;
; Dedicated logic registers ; 24 / 22,320 ( < 1 % ) ;
; Total registers ; 24 ;
; Total pins ; 9 / 154 ( 6 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 / 608,256 ( 0 % ) ;
; Total memory bits ; 64 / 608,256 ( < 1 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
+------------------------------------+--------------------------------------------+
@@ -2372,14 +2374,14 @@ From Design Partitions [A] :
From Rapid Recompile [B] :
Type : -- Requested
Total [A + B] : 0.00 % ( 0 / 93 )
From Design Partitions [A] : 0.00 % ( 0 / 93 )
From Rapid Recompile [B] : 0.00 % ( 0 / 93 )
Total [A + B] : 0.00 % ( 0 / 95 )
From Design Partitions [A] : 0.00 % ( 0 / 95 )
From Rapid Recompile [B] : 0.00 % ( 0 / 95 )
Type : -- Achieved
Total [A + B] : 0.00 % ( 0 / 93 )
From Design Partitions [A] : 0.00 % ( 0 / 93 )
From Rapid Recompile [B] : 0.00 % ( 0 / 93 )
Total [A + B] : 0.00 % ( 0 / 95 )
From Design Partitions [A] : 0.00 % ( 0 / 95 )
From Rapid Recompile [B] : 0.00 % ( 0 / 95 )
Type :
Total [A + B] :
@@ -2430,7 +2432,7 @@ Contents : hard_block:auto_generated_inst
; Incremental Compilation Placement Preservation ;
+--------------------------------------------------------------------------------+
Partition Name : Top
Preservation Achieved : 0.00 % ( 0 / 83 )
Preservation Achieved : 0.00 % ( 0 / 85 )
Preservation Level Used : N/A
Netlist Type Used : Source File
Preservation Method : N/A
@@ -2452,40 +2454,40 @@ Notes :
The pin-out file can be found in /home/benny/work/fpga/projects/output_files/spectrum.pin.
+---------------------------------------------------------------------+
+-----------------------------------------------------------------------+
; Fitter Resource Usage Summary ;
+---------------------------------------------+-----------------------+
+---------------------------------------------+-------------------------+
; Resource ; Usage ;
+---------------------------------------------+-----------------------+
; Total logic elements ; 35 / 22,320 ( < 1 % ) ;
; -- Combinational with no register ; 0 ;
; -- Register only ; 7 ;
; -- Combinational with a register ; 28 ;
+---------------------------------------------+-------------------------+
; Total logic elements ; 33 / 22,320 ( < 1 % ) ;
; -- Combinational with no register ; 9 ;
; -- Register only ; 0 ;
; -- Combinational with a register ; 24 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 0 ;
; -- 4 input functions ; 10 ;
; -- 3 input functions ; 1 ;
; -- <=2 input functions ; 27 ;
; -- Register only ; 7 ;
; -- <=2 input functions ; 22 ;
; -- Register only ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 2 ;
; -- arithmetic mode ; 26 ;
; -- normal mode ; 13 ;
; -- arithmetic mode ; 20 ;
; ; ;
; Total registers* ; 35 / 23,018 ( < 1 % ) ;
; -- Dedicated logic registers ; 35 / 22,320 ( < 1 % ) ;
; Total registers* ; 24 / 23,018 ( < 1 % ) ;
; -- Dedicated logic registers ; 24 / 22,320 ( < 1 % ) ;
; -- I/O registers ; 0 / 698 ( 0 % ) ;
; ; ;
; Total LABs: partially or completely used ; 5 / 1,395 ( < 1 % ) ;
; Total LABs: partially or completely used ; 3 / 1,395 ( < 1 % ) ;
; Virtual pins ; 0 ;
; I/O pins ; 9 / 154 ( 6 % ) ;
; -- Clock pins ; 1 / 7 ( 14 % ) ;
; -- Dedicated input pins ; 0 / 9 ( 0 % ) ;
; ; ;
; Global signals ; 1 ;
; M9Ks ; 0 / 66 ( 0 % ) ;
; Total block memory bits ; 0 / 608,256 ( 0 % ) ;
; Total block memory implementation bits ; 0 / 608,256 ( 0 % ) ;
; M9Ks ; 1 / 66 ( 2 % ) ;
; Total block memory bits ; 64 / 608,256 ( < 1 % ) ;
; Total block memory implementation bits ; 9,216 / 608,256 ( 2 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ;
; PLLs ; 0 / 4 ( 0 % ) ;
; Global clocks ; 1 / 20 ( 5 % ) ;
@@ -2495,11 +2497,11 @@ The pin-out file can be found in /home/benny/work/fpga/projects/output_files/spe
; Impedance control blocks ; 0 / 4 ( 0 % ) ;
; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ;
; Peak interconnect usage (total/H/V) ; 0% / 0% / 0% ;
; Maximum fan-out ; 35 ;
; Highest non-global fan-out ; 2 ;
; Total fan-out ; 154 ;
; Average fan-out ; 1.56 ;
+---------------------------------------------+-----------------------+
; Maximum fan-out ; 25 ;
; Highest non-global fan-out ; 4 ;
; Total fan-out ; 161 ;
; Average fan-out ; 1.85 ;
+---------------------------------------------+-------------------------+
* Register count does not include registers inside RAM blocks or DSP blocks.
@@ -2516,19 +2518,19 @@ Top :
hard_block:auto_generated_inst :
Statistic : Total logic elements
Top : 35 / 22320 ( < 1 % )
Top : 33 / 22320 ( < 1 % )
hard_block:auto_generated_inst : 0 / 22320 ( 0 % )
Statistic : -- Combinational with no register
Top : 0
Top : 9
hard_block:auto_generated_inst : 0
Statistic : -- Register only
Top : 7
Top : 0
hard_block:auto_generated_inst : 0
Statistic : -- Combinational with a register
Top : 28
Top : 24
hard_block:auto_generated_inst : 0
Statistic :
@@ -2540,7 +2542,7 @@ Top :
hard_block:auto_generated_inst :
Statistic : -- 4 input functions
Top : 0
Top : 10
hard_block:auto_generated_inst : 0
Statistic : -- 3 input functions
@@ -2548,11 +2550,11 @@ Top : 1
hard_block:auto_generated_inst : 0
Statistic : -- <=2 input functions
Top : 27
Top : 22
hard_block:auto_generated_inst : 0
Statistic : -- Register only
Top : 7
Top : 0
hard_block:auto_generated_inst : 0
Statistic :
@@ -2564,11 +2566,11 @@ Top :
hard_block:auto_generated_inst :
Statistic : -- normal mode
Top : 2
Top : 13
hard_block:auto_generated_inst : 0
Statistic : -- arithmetic mode
Top : 26
Top : 20
hard_block:auto_generated_inst : 0
Statistic :
@@ -2576,11 +2578,11 @@ Top :
hard_block:auto_generated_inst :
Statistic : Total registers
Top : 35
Top : 24
hard_block:auto_generated_inst : 0
Statistic : -- Dedicated logic registers
Top : 35 / 22320 ( < 1 % )
Top : 24 / 22320 ( < 1 % )
hard_block:auto_generated_inst : 0 / 22320 ( 0 % )
Statistic : -- I/O registers
@@ -2592,7 +2594,7 @@ Top :
hard_block:auto_generated_inst :
Statistic : Total LABs: partially or completely used
Top : 5 / 1395 ( < 1 % )
Top : 3 / 1395 ( < 1 % )
hard_block:auto_generated_inst : 0 / 1395 ( 0 % )
Statistic :
@@ -2612,13 +2614,17 @@ Top : 0 / 132 ( 0 % )
hard_block:auto_generated_inst : 0 / 132 ( 0 % )
Statistic : Total memory bits
Top : 0
Top : 64
hard_block:auto_generated_inst : 0
Statistic : Total RAM block bits
Top : 0
Top : 9216
hard_block:auto_generated_inst : 0
Statistic : M9K
Top : 1 / 66 ( 1 % )
hard_block:auto_generated_inst : 0 / 66 ( 0 % )
Statistic : Clock control block
Top : 1 / 24 ( 4 % )
hard_block:auto_generated_inst : 0 / 24 ( 0 % )
@@ -2656,11 +2662,11 @@ Top :
hard_block:auto_generated_inst :
Statistic : -- Total Connections
Top : 149
Top : 156
hard_block:auto_generated_inst : 5
Statistic : -- Registered Connections
Top : 43
Top : 38
hard_block:auto_generated_inst : 0
Statistic :
@@ -2767,7 +2773,7 @@ I/O Bank : 3
X coordinate : 27
Y coordinate : 0
Z coordinate : 21
Combinational Fan-Out : 35
Combinational Fan-Out : 25
Registered Fan-Out : 0
Global : yes
Input Register : no
@@ -6219,21 +6225,72 @@ Note: Pin directions (input, output or bidir) are based on device operating in u
; Fitter Resource Utilization by Entity ;
+--------------------------------------------------------------------------------+
Compilation Hierarchy Node : |spectrum
Logic Cells : 35 (35)
Dedicated Logic Registers : 35 (35)
Logic Cells : 33 (33)
Dedicated Logic Registers : 24 (24)
I/O Registers : 0 (0)
Memory Bits : 0
M9Ks : 0
Memory Bits : 64
M9Ks : 1
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 9
Virtual Pins : 0
LUT-Only LCs : 0 (0)
Register-Only LCs : 7 (7)
LUT/Register LCs : 28 (28)
LUT-Only LCs : 9 (9)
Register-Only LCs : 0 (0)
LUT/Register LCs : 24 (24)
Full Hierarchy Name : |spectrum
Library Name : work
Compilation Hierarchy Node : |rom0:rom|
Logic Cells : 0 (0)
Dedicated Logic Registers : 0 (0)
I/O Registers : 0 (0)
Memory Bits : 64
M9Ks : 1
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
LUT-Only LCs : 0 (0)
Register-Only LCs : 0 (0)
LUT/Register LCs : 0 (0)
Full Hierarchy Name : |spectrum|rom0:rom
Library Name : work
Compilation Hierarchy Node : |altsyncram:altsyncram_component|
Logic Cells : 0 (0)
Dedicated Logic Registers : 0 (0)
I/O Registers : 0 (0)
Memory Bits : 64
M9Ks : 1
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
LUT-Only LCs : 0 (0)
Register-Only LCs : 0 (0)
LUT/Register LCs : 0 (0)
Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component
Library Name : work
Compilation Hierarchy Node : |altsyncram_ro91:auto_generated|
Logic Cells : 0 (0)
Dedicated Logic Registers : 0 (0)
I/O Registers : 0 (0)
Memory Bits : 64
M9Ks : 1
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
LUT-Only LCs : 0 (0)
Register-Only LCs : 0 (0)
LUT/Register LCs : 0 (0)
Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated
Library Name : work
+--------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
@@ -6332,7 +6389,7 @@ Setting :
+--------------------------------------------------------------------------------+
Name : CLOCK_50
Location : PIN_R8
Fan-Out : 35
Fan-Out : 25
Usage : Clock
Global : yes
Global Resource Used : Global Clock
@@ -6347,8 +6404,8 @@ Enable Signal Source Name : --
+--------------------------------------------------------------------------------+
Name : CLOCK_50
Location : PIN_R8
Fan-Out : 35
Fan-Out Using Intentional Clock Skew : 12
Fan-Out : 25
Fan-Out Using Intentional Clock Skew : 3
Global Resource Used : Global Clock
Global Line Name : GCLK18
Enable Signal Source Name : --
@@ -6356,80 +6413,48 @@ Enable Signal Source Name : --
+---------------------------------+
+------------------------------------------------------------------------------------------+
; Non-Global High Fan-Out Signals ;
+----------------+----------------+
+--------------------------------------------------------------------------------+---------+
; Name ; Fan-Out ;
+----------------+----------------+
; counter[0] ; 2 ;
; counter[27] ; 2 ;
; counter[26] ; 2 ;
; counter[25] ; 2 ;
; counter[24] ; 2 ;
; counter[23] ; 2 ;
; counter[22] ; 2 ;
; counter[21] ; 2 ;
; counter[0]~81 ; 1 ;
; LED[6]~reg0 ; 1 ;
; LED[5]~reg0 ; 1 ;
; LED[4]~reg0 ; 1 ;
; LED[3]~reg0 ; 1 ;
; LED[2]~reg0 ; 1 ;
; LED[1]~reg0 ; 1 ;
; LED[0]~reg0 ; 1 ;
; counter[27]~79 ; 1 ;
; counter[26]~78 ; 1 ;
; counter[26]~77 ; 1 ;
; counter[25]~76 ; 1 ;
; counter[25]~75 ; 1 ;
; counter[24]~74 ; 1 ;
; counter[24]~73 ; 1 ;
; counter[23]~72 ; 1 ;
; counter[23]~71 ; 1 ;
; counter[22]~70 ; 1 ;
; counter[22]~69 ; 1 ;
; counter[21]~68 ; 1 ;
; counter[21]~67 ; 1 ;
; counter[20]~66 ; 1 ;
; counter[20]~65 ; 1 ;
; counter[19]~64 ; 1 ;
; counter[19]~63 ; 1 ;
; counter[18]~62 ; 1 ;
; counter[18]~61 ; 1 ;
; counter[17]~60 ; 1 ;
; counter[17]~59 ; 1 ;
; counter[16]~58 ; 1 ;
; counter[16]~57 ; 1 ;
; counter[15]~56 ; 1 ;
; counter[15]~55 ; 1 ;
; counter[14]~54 ; 1 ;
; counter[14]~53 ; 1 ;
; counter[13]~52 ; 1 ;
; counter[13]~51 ; 1 ;
; counter[12]~50 ; 1 ;
; counter[12]~49 ; 1 ;
; counter[11]~48 ; 1 ;
; counter[11]~47 ; 1 ;
; counter[10]~46 ; 1 ;
; counter[10]~45 ; 1 ;
; counter[9]~44 ; 1 ;
; counter[9]~43 ; 1 ;
; counter[8]~42 ; 1 ;
; counter[8]~41 ; 1 ;
; counter[7]~40 ; 1 ;
; counter[7]~39 ; 1 ;
; counter[6]~38 ; 1 ;
; counter[6]~37 ; 1 ;
; counter[5]~36 ; 1 ;
; counter[5]~35 ; 1 ;
; counter[4]~34 ; 1 ;
; counter[4]~33 ; 1 ;
; counter[3]~32 ; 1 ;
; counter[3]~31 ; 1 ;
; counter[2]~30 ; 1 ;
; counter[2]~29 ; 1 ;
; counter[1]~28 ; 1 ;
; counter[1]~27 ; 1 ;
+--------------------------------------------------------------------------------+---------+
; address[0] ; 4 ;
; Add0~40 ; 4 ;
; Equal0~4 ; 3 ;
; address[1] ; 3 ;
; Add0~38 ; 3 ;
; Add0~36 ; 3 ;
; Add0~34 ; 3 ;
; Add0~32 ; 3 ;
; Equal0~5 ; 2 ;
; address[2] ; 2 ;
; Add0~30 ; 2 ;
; Add0~28 ; 2 ;
; Add0~26 ; 2 ;
; Add0~24 ; 2 ;
; Add0~22 ; 2 ;
; Add0~20 ; 2 ;
; Add0~18 ; 2 ;
; Add0~16 ; 2 ;
; Add0~14 ; 2 ;
; Add0~12 ; 2 ;
; Add0~10 ; 2 ;
; Add0~8 ; 2 ;
; Add0~6 ; 2 ;
; Add0~4 ; 2 ;
; Add0~2 ; 2 ;
; Add0~0 ; 2 ;
; address[2]~3 ; 1 ;
; address[1]~2 ; 1 ;
; address[1]~1 ; 1 ;
; Equal0~7 ; 1 ;
; Equal0~6 ; 1 ;
; address[0]~0 ; 1 ;
; Equal0~3 ; 1 ;
; Equal0~2 ; 1 ;
; Equal0~1 ; 1 ;
; Equal0~0 ; 1 ;
; counter[0] ; 1 ;
; counter[1] ; 1 ;
; counter[2] ; 1 ;
; counter[3] ; 1 ;
@@ -6450,7 +6475,77 @@ Enable Signal Source Name : --
; counter[18] ; 1 ;
; counter[19] ; 1 ;
; counter[20] ; 1 ;
+----------------+----------------+
; Add0~39 ; 1 ;
; Add0~37 ; 1 ;
; Add0~35 ; 1 ;
; Add0~33 ; 1 ;
; Add0~31 ; 1 ;
; Add0~29 ; 1 ;
; Add0~27 ; 1 ;
; Add0~25 ; 1 ;
; Add0~23 ; 1 ;
; Add0~21 ; 1 ;
; Add0~19 ; 1 ;
; Add0~17 ; 1 ;
; Add0~15 ; 1 ;
; Add0~13 ; 1 ;
; Add0~11 ; 1 ;
; Add0~9 ; 1 ;
; Add0~7 ; 1 ;
; Add0~5 ; 1 ;
; Add0~3 ; 1 ;
; Add0~1 ; 1 ;
; rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[1] ; 1 ;
; rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[2] ; 1 ;
; rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[3] ; 1 ;
; rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[4] ; 1 ;
; rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[5] ; 1 ;
; rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[6] ; 1 ;
; rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[7] ; 1 ;
; rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[0] ; 1 ;
+--------------------------------------------------------------------------------+---------+
+--------------------------------------------------------------------------------+
; Fitter RAM Summary ;
+--------------------------------------------------------------------------------+
Name : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ALTSYNCRAM
Type : AUTO
Mode : ROM
Clock Mode : Single Clock
Port A Depth : 8
Port A Width : 8
Port B Depth : --
Port B Width : --
Port A Input Registers : yes
Port A Output Registers : yes
Port B Input Registers : --
Port B Output Registers : --
Size : 64
Implementation Port A Depth : 8
Implementation Port A Width : 8
Implementation Port B Depth : --
Implementation Port B Width : --
Implementation Bits : 64
M9Ks : 1
MIF : led_patterns.mif
Location : M9K_X33_Y26_N0
Mixed Width RDW Mode : Don't care
Port A RDW Mode : Old data
Port B RDW Mode : Old data
Fits in MLABs : No - Unknown
+--------------------------------------------------------------------------------+
Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.
RAM content values are presented in the following format: (Binary) (Octal) (Decimal) (Hexadecimal)
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ALTSYNCRAM ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Addr ; +0 ; +1 ; +2 ; +3 ; +4 ; +5 ; +6 ; +7 ;
+----------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+
;0;(10000001) (201) (129) (81) ;(01000010) (102) (66) (42) ;(00100100) (44) (36) (24) ;(00011000) (30) (24) (18) ;(00011000) (30) (24) (18) ;(00100100) (44) (36) (24) ;(01000010) (102) (66) (42) ;(10000001) (201) (129) (81) ;
+-----------------------------------------------+
@@ -6458,65 +6553,65 @@ Enable Signal Source Name : --
+-----------------------+-----------------------+
; Routing Resource Type ; Usage ;
+-----------------------+-----------------------+
; Block interconnects ; 16 / 71,559 ( < 1 % ) ;
; C16 interconnects ; 0 / 2,597 ( 0 % ) ;
; C4 interconnects ; 9 / 46,848 ( < 1 % ) ;
; Direct links ; 4 / 71,559 ( < 1 % ) ;
; Block interconnects ; 42 / 71,559 ( < 1 % ) ;
; C16 interconnects ; 3 / 2,597 ( < 1 % ) ;
; C4 interconnects ; 20 / 46,848 ( < 1 % ) ;
; Direct links ; 24 / 71,559 ( < 1 % ) ;
; Global clocks ; 1 / 20 ( 5 % ) ;
; Local interconnects ; 28 / 24,624 ( < 1 % ) ;
; R24 interconnects ; 4 / 2,496 ( < 1 % ) ;
; R4 interconnects ; 17 / 62,424 ( < 1 % ) ;
; Local interconnects ; 24 / 24,624 ( < 1 % ) ;
; R24 interconnects ; 7 / 2,496 ( < 1 % ) ;
; R4 interconnects ; 27 / 62,424 ( < 1 % ) ;
+-----------------------+-----------------------+
+--------------------------------------------------------------------------+
+---------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+-----------------------------+
; Number of Logic Elements (Average = 7.00) ; Number of LABs (Total = 5) ;
+--------------------------------------------+-----------------------------+
; 1 ; 1 ;
; 2 ; 1 ;
+---------------------------------------------+-----------------------------+
; Number of Logic Elements (Average = 11.00) ; Number of LABs (Total = 3) ;
+---------------------------------------------+-----------------------------+
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 1 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 6 ; 1 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 12 ; 1 ;
; 13 ; 0 ;
; 14 ; 2 ;
; 15 ; 0 ;
; 14 ; 0 ;
; 15 ; 1 ;
; 16 ; 0 ;
+--------------------------------------------+-----------------------------+
+---------------------------------------------+-----------------------------+
+------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+-----------------------------+
; LAB-wide Signals (Average = 1.00) ; Number of LABs (Total = 5) ;
; LAB-wide Signals (Average = 1.00) ; Number of LABs (Total = 3) ;
+------------------------------------+-----------------------------+
; 1 Clock ; 5 ;
; 1 Clock ; 3 ;
+------------------------------------+-----------------------------+
+----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+----------------------------------------------+-----------------------------+
; Number of Signals Sourced (Average = 14.00) ; Number of LABs (Total = 5) ;
; Number of Signals Sourced (Average = 19.00) ; Number of LABs (Total = 3) ;
+----------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 1 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 1 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 1 ;
; 9 ; 0 ;
; 8 ; 0 ;
; 9 ; 1 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 0 ;
@@ -6529,43 +6624,46 @@ Enable Signal Source Name : --
; 19 ; 0 ;
; 20 ; 0 ;
; 21 ; 0 ;
; 22 ; 0 ;
; 22 ; 1 ;
; 23 ; 0 ;
; 24 ; 0 ;
; 25 ; 0 ;
; 26 ; 0 ;
; 27 ; 0 ;
; 28 ; 2 ;
; 26 ; 1 ;
+----------------------------------------------+-----------------------------+
+-------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+-----------------------------+
; Number of Signals Sourced Out (Average = 2.80) ; Number of LABs (Total = 5) ;
; Number of Signals Sourced Out (Average = 4.33) ; Number of LABs (Total = 3) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 1 ;
; 1 ; 1 ;
; 2 ; 1 ;
; 3 ; 0 ;
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 1 ;
; 4 ; 1 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 1 ;
; 6 ; 1 ;
+-------------------------------------------------+-----------------------------+
+---------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+-----------------------------+
; Number of Distinct Inputs (Average = 2.60) ; Number of LABs (Total = 5) ;
; Number of Distinct Inputs (Average = 4.67) ; Number of LABs (Total = 3) ;
+---------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 1 ;
; 2 ; 2 ;
; 3 ; 1 ;
; 2 ; 1 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 1 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 1 ;
+---------------------------------------------+-----------------------------+
@@ -7338,6 +7436,7 @@ Info (169124): Fitter converted 5 user pins into dedicated programming pins
Info (169125): Pin ~ALTERA_DATA0~ is reserved at location H2
Info (169125): Pin ~ALTERA_nCEO~ is reserved at location F16
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Critical Warning (332012): Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332144): No user constrained base clocks found in the design
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
@@ -7503,10 +7602,10 @@ Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
Info (170193): Fitter routing operations beginning
Info (170195): Router estimated average interconnect usage is 0% of the available device resources
Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X32_Y23 to location X42_Y34
Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info (170201): Optimizations that may affect the design's routability were skipped
Info (11888): Total time spent on timing analysis during the Fitter is 0.10 seconds.
Info (11888): Total time spent on timing analysis during the Fitter is 0.16 seconds.
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (334003): Started post-fitting delay annotation
@@ -7517,9 +7616,9 @@ Warning (169177): 1 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V
Info (169178): Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at R8
Info (144001): Generated suppressed messages file /home/benny/work/fpga/projects/output_files/spectrum.fit.smsg
Info: Quartus II 32-bit Fitter was successful. 0 errors, 152 warnings
Info: Peak virtual memory: 588 megabytes
Info: Processing ended: Wed Mar 30 11:51:36 2022
Info: Elapsed time: 00:00:06
Info: Peak virtual memory: 600 megabytes
Info: Processing ended: Wed Mar 30 12:38:34 2022
Info: Elapsed time: 00:00:05
Info: Total CPU time (on all processors): 00:00:06
output_files/spectrum.fit.summary
+6 -6
View File
@@ -1,16 +1,16 @@
Fitter Status : Successful - Wed Mar 30 11:51:35 2022
Fitter Status : Successful - Wed Mar 30 12:38:34 2022
Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
Revision Name : spectrum
Top-level Entity Name : spectrum
Family : Cyclone IV E
Device : EP4CE22F17C6
Timing Models : Final
Total logic elements : 35 / 22,320 ( < 1 % )
Total combinational functions : 28 / 22,320 ( < 1 % )
Dedicated logic registers : 35 / 22,320 ( < 1 % )
Total registers : 35
Total logic elements : 33 / 22,320 ( < 1 % )
Total combinational functions : 33 / 22,320 ( < 1 % )
Dedicated logic registers : 24 / 22,320 ( < 1 % )
Total registers : 24
Total pins : 9 / 154 ( 6 % )
Total virtual pins : 0
Total memory bits : 0 / 608,256 ( 0 % )
Total memory bits : 64 / 608,256 ( < 1 % )
Embedded Multiplier 9-bit elements : 0 / 132 ( 0 % )
Total PLLs : 0 / 4 ( 0 % )
output_files/spectrum.flow.rpt
+34 -16
View File
@@ -1,5 +1,5 @@
Flow report for spectrum
Wed Mar 30 11:51:43 2022
Wed Mar 30 12:38:42 2022
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
@@ -40,20 +40,20 @@ applicable agreement for further details.
+---------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+--------------------------------------------+
; Flow Status ; Successful - Wed Mar 30 11:51:43 2022 ;
; Flow Status ; Successful - Wed Mar 30 12:38:42 2022 ;
; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
; Revision Name ; spectrum ;
; Top-level Entity Name ; spectrum ;
; Family ; Cyclone IV E ;
; Device ; EP4CE22F17C6 ;
; Timing Models ; Final ;
; Total logic elements ; 35 / 22,320 ( < 1 % ) ;
; Total combinational functions ; 28 / 22,320 ( < 1 % ) ;
; Dedicated logic registers ; 35 / 22,320 ( < 1 % ) ;
; Total registers ; 35 ;
; Total logic elements ; 33 / 22,320 ( < 1 % ) ;
; Total combinational functions ; 33 / 22,320 ( < 1 % ) ;
; Dedicated logic registers ; 24 / 22,320 ( < 1 % ) ;
; Total registers ; 24 ;
; Total pins ; 9 / 154 ( 6 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 / 608,256 ( 0 % ) ;
; Total memory bits ; 64 / 608,256 ( < 1 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
+------------------------------------+--------------------------------------------+
@@ -64,7 +64,7 @@ applicable agreement for further details.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 03/30/2022 11:51:28 ;
; Start date & time ; 03/30/2022 12:38:27 ;
; Main task ; Compilation ;
; Revision Name ; spectrum ;
+-------------------+---------------------+
@@ -74,7 +74,7 @@ applicable agreement for further details.
; Flow Non-Default Global Settings ;
+--------------------------------------------------------------------------------+
Assignment Name : COMPILER_SIGNATURE_ID
Value : 0.164863028816849
Value : 0.164863310720961
Default Value : --
Entity Name : --
Section Id : --
@@ -91,6 +91,18 @@ Default Value : <None>
Entity Name : --
Section Id : --
Assignment Name : IP_TOOL_NAME
Value : ROM: 1-PORT
Default Value : --
Entity Name : --
Section Id : --
Assignment Name : IP_TOOL_VERSION
Value : 13.1
Default Value : --
Entity Name : --
Section Id : --
Assignment Name : MAX_CORE_JUNCTION_TEMP
Value : 85
Default Value : --
@@ -103,6 +115,12 @@ Default Value : --
Entity Name : --
Section Id : --
Assignment Name : MISC_FILE
Value : rom0_bb.v
Default Value : --
Entity Name : --
Section Id : --
Assignment Name : NOMINAL_CORE_SUPPLY_VOLTAGE
Value : 1.2V
Default Value : --
@@ -140,37 +158,37 @@ Section Id : --
; Flow Elapsed Time ;
+--------------------------------------------------------------------------------+
Module Name : Analysis & Synthesis
Elapsed Time : 00:00:01
Elapsed Time : 00:00:02
Average Processors Used : 1.0
Peak Virtual Memory : 377 MB
Peak Virtual Memory : 373 MB
Total CPU Time (on all processors) : 00:00:01
Module Name : Fitter
Elapsed Time : 00:00:05
Average Processors Used : 1.0
Peak Virtual Memory : 588 MB
Peak Virtual Memory : 600 MB
Total CPU Time (on all processors) : 00:00:06
Module Name : Assembler
Elapsed Time : 00:00:01
Average Processors Used : 1.0
Peak Virtual Memory : 389 MB
Peak Virtual Memory : 393 MB
Total CPU Time (on all processors) : 00:00:01
Module Name : TimeQuest Timing Analyzer
Elapsed Time : 00:00:02
Average Processors Used : 1.0
Peak Virtual Memory : 412 MB
Peak Virtual Memory : 415 MB
Total CPU Time (on all processors) : 00:00:02
Module Name : EDA Netlist Writer
Elapsed Time : 00:00:01
Average Processors Used : 1.0
Peak Virtual Memory : 340 MB
Peak Virtual Memory : 332 MB
Total CPU Time (on all processors) : 00:00:01
Module Name : Total
Elapsed Time : 00:00:10
Elapsed Time : 00:00:11
Average Processors Used : --
Peak Virtual Memory : --
Total CPU Time (on all processors) : 00:00:11
output_files/spectrum.jdi
+1 -1
View File
@@ -1,6 +1,6 @@
<sld_project_info>
<project>
<hash md5_digest_80b="30de10ed078191d33504"/>
<hash md5_digest_80b="cb6c551d4ff42d38b754"/>
</project>
<file_info>
<file device="EP4CE22F17C6" path="spectrum.sof" usercode="0xFFFFFFFF"/>
output_files/spectrum.map.rpt
+445 -43
View File
@@ -1,5 +1,5 @@
Analysis & Synthesis report for spectrum
Wed Mar 30 11:51:29 2022
Wed Mar 30 12:38:28 2022
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
@@ -13,10 +13,14 @@ Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. Registers Removed During Synthesis
9. General Register Statistics
10. Elapsed Time Per Partition
11. Analysis & Synthesis Messages
8. Analysis & Synthesis RAM Summary
9. Analysis & Synthesis IP Cores Summary
10. General Register Statistics
11. Source assignments for rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated
12. Parameter Settings for User Entity Instance: rom0:rom|altsyncram:altsyncram_component
13. altsyncram Parameter Settings by Entity Instance
14. Elapsed Time Per Partition
15. Analysis & Synthesis Messages
@@ -42,18 +46,18 @@ applicable agreement for further details.
+---------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+--------------------------------------------+
; Analysis & Synthesis Status ; Successful - Wed Mar 30 11:51:29 2022 ;
; Analysis & Synthesis Status ; Successful - Wed Mar 30 12:38:28 2022 ;
; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
; Revision Name ; spectrum ;
; Top-level Entity Name ; spectrum ;
; Family ; Cyclone IV E ;
; Total logic elements ; 35 ;
; Total combinational functions ; 28 ;
; Dedicated logic registers ; 35 ;
; Total registers ; 35 ;
; Total logic elements ; 33 ;
; Total combinational functions ; 33 ;
; Dedicated logic registers ; 24 ;
; Total registers ; 24 ;
; Total pins ; 9 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 ;
; Total memory bits ; 64 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Total PLLs ; 0 ;
+------------------------------------+--------------------------------------------+
@@ -400,6 +404,78 @@ Used in Netlist : yes
File Type : User Verilog HDL File
File Name with Absolute Path : /home/benny/work/fpga/projects/spectrum.v
Library :
File Name with User-Entered Path : led_patterns.mif
Used in Netlist : yes
File Type : User Memory Initialization File
File Name with Absolute Path : /home/benny/work/fpga/projects/led_patterns.mif
Library :
File Name with User-Entered Path : rom0.v
Used in Netlist : yes
File Type : User Wizard-Generated File
File Name with Absolute Path : /home/benny/work/fpga/projects/rom0.v
Library :
File Name with User-Entered Path : altsyncram.tdf
Used in Netlist : yes
File Type : Megafunction
File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf
Library :
File Name with User-Entered Path : stratix_ram_block.inc
Used in Netlist : yes
File Type : Megafunction
File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/stratix_ram_block.inc
Library :
File Name with User-Entered Path : lpm_mux.inc
Used in Netlist : yes
File Type : Megafunction
File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/lpm_mux.inc
Library :
File Name with User-Entered Path : lpm_decode.inc
Used in Netlist : yes
File Type : Megafunction
File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/lpm_decode.inc
Library :
File Name with User-Entered Path : aglobal131.inc
Used in Netlist : yes
File Type : Megafunction
File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/aglobal131.inc
Library :
File Name with User-Entered Path : a_rdenreg.inc
Used in Netlist : yes
File Type : Megafunction
File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/a_rdenreg.inc
Library :
File Name with User-Entered Path : altrom.inc
Used in Netlist : yes
File Type : Megafunction
File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/altrom.inc
Library :
File Name with User-Entered Path : altram.inc
Used in Netlist : yes
File Type : Megafunction
File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/altram.inc
Library :
File Name with User-Entered Path : altdpram.inc
Used in Netlist : yes
File Type : Megafunction
File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/altdpram.inc
Library :
File Name with User-Entered Path : db/altsyncram_ro91.tdf
Used in Netlist : yes
File Type : Auto-Generated Megafunction
File Name with Absolute Path : /home/benny/work/fpga/projects/db/altsyncram_ro91.tdf
Library :
+--------------------------------------------------------------------------------+
@@ -409,28 +485,29 @@ Library :
+---------------------------------------------+----------------+
; Resource ; Usage ;
+---------------------------------------------+----------------+
; Estimated Total logic elements ; 35 ;
; Estimated Total logic elements ; 33 ;
; ; ;
; Total combinational functions ; 28 ;
; Total combinational functions ; 33 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 0 ;
; -- 4 input functions ; 10 ;
; -- 3 input functions ; 1 ;
; -- <=2 input functions ; 27 ;
; -- <=2 input functions ; 22 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 2 ;
; -- arithmetic mode ; 26 ;
; -- normal mode ; 13 ;
; -- arithmetic mode ; 20 ;
; ; ;
; Total registers ; 35 ;
; -- Dedicated logic registers ; 35 ;
; Total registers ; 24 ;
; -- Dedicated logic registers ; 24 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 9 ;
; Total memory bits ; 64 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Maximum fan-out node ; CLOCK_50~input ;
; Maximum fan-out ; 35 ;
; Total fan-out ; 141 ;
; Average fan-out ; 1.74 ;
; Maximum fan-out ; 32 ;
; Total fan-out ; 183 ;
; Average fan-out ; 2.20 ;
+---------------------------------------------+----------------+
@@ -438,9 +515,9 @@ Library :
; Analysis & Synthesis Resource Utilization by Entity ;
+--------------------------------------------------------------------------------+
Compilation Hierarchy Node : |spectrum
LC Combinationals : 28 (28)
LC Registers : 35 (35)
Memory Bits : 0
LC Combinationals : 33 (33)
LC Registers : 24 (24)
Memory Bits : 64
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
@@ -448,19 +525,75 @@ Pins : 9
Virtual Pins : 0
Full Hierarchy Name : |spectrum
Library Name : work
Compilation Hierarchy Node : |rom0:rom|
LC Combinationals : 0 (0)
LC Registers : 0 (0)
Memory Bits : 64
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|rom0:rom
Library Name : work
Compilation Hierarchy Node : |altsyncram:altsyncram_component|
LC Combinationals : 0 (0)
LC Registers : 0 (0)
Memory Bits : 64
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component
Library Name : work
Compilation Hierarchy Node : |altsyncram_ro91:auto_generated|
LC Combinationals : 0 (0)
LC Registers : 0 (0)
Memory Bits : 64
DSP Elements : 0
DSP 9x9 : 0
DSP 18x18 : 0
Pins : 0
Virtual Pins : 0
Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated
Library Name : work
+--------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+---------------------------------------+----------------------------------------+
; Register name ; Reason for Removal ;
+---------------------------------------+----------------------------------------+
; LED[7]~reg0 ; Stuck at GND due to stuck port data_in ;
; Total Number of Removed Registers = 1 ; ;
+---------------------------------------+----------------------------------------+
; Analysis & Synthesis RAM Summary ;
+--------------------------------------------------------------------------------+
Name : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ALTSYNCRAM
Type : AUTO
Mode : ROM
Port A Depth : 8
Port A Width : 8
Port B Depth : --
Port B Width : --
Size : 64
MIF : led_patterns.mif
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary ;
+--------------------------------------------------------------------------------+
Vendor : Altera
IP Core Name : ROM: 1-PORT
Version : 13.1
Release Date : N/A
License Type : N/A
Entity Instance : |spectrum|rom0:rom
IP Include File : /home/benny/work/fpga/projects/rom0.v
+--------------------------------------------------------------------------------+
+------------------------------------------------------+
@@ -468,7 +601,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 35 ;
; Total registers ; 24 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
@@ -478,6 +611,252 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+----------------------------------------------+-------+
+--------------------------------------------------------------------------------+
; Source assignments for rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated ;
+--------------------------------------------------------------------------------+
Assignment : OPTIMIZE_POWER_DURING_SYNTHESIS
Value : NORMAL_COMPILATION
From : -
To : -
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: rom0:rom|altsyncram:altsyncram_component ;
+--------------------------------------------------------------------------------+
Parameter Name : BYTE_SIZE_BLOCK
Value : 8
Type : Untyped
Parameter Name : AUTO_CARRY_CHAINS
Value : ON
Type : AUTO_CARRY
Parameter Name : IGNORE_CARRY_BUFFERS
Value : OFF
Type : IGNORE_CARRY
Parameter Name : AUTO_CASCADE_CHAINS
Value : ON
Type : AUTO_CASCADE
Parameter Name : IGNORE_CASCADE_BUFFERS
Value : OFF
Type : IGNORE_CASCADE
Parameter Name : WIDTH_BYTEENA
Value : 1
Type : Untyped
Parameter Name : OPERATION_MODE
Value : ROM
Type : Untyped
Parameter Name : WIDTH_A
Value : 8
Type : Signed Integer
Parameter Name : WIDTHAD_A
Value : 3
Type : Signed Integer
Parameter Name : NUMWORDS_A
Value : 8
Type : Signed Integer
Parameter Name : OUTDATA_REG_A
Value : CLOCK0
Type : Untyped
Parameter Name : ADDRESS_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : OUTDATA_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : WRCONTROL_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : INDATA_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : BYTEENA_ACLR_A
Value : NONE
Type : Untyped
Parameter Name : WIDTH_B
Value : 1
Type : Untyped
Parameter Name : WIDTHAD_B
Value : 1
Type : Untyped
Parameter Name : NUMWORDS_B
Value : 1
Type : Untyped
Parameter Name : INDATA_REG_B
Value : CLOCK1
Type : Untyped
Parameter Name : WRCONTROL_WRADDRESS_REG_B
Value : CLOCK1
Type : Untyped
Parameter Name : RDCONTROL_REG_B
Value : CLOCK1
Type : Untyped
Parameter Name : ADDRESS_REG_B
Value : CLOCK1
Type : Untyped
Parameter Name : OUTDATA_REG_B
Value : UNREGISTERED
Type : Untyped
Parameter Name : BYTEENA_REG_B
Value : CLOCK1
Type : Untyped
Parameter Name : INDATA_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : WRCONTROL_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : ADDRESS_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : OUTDATA_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : RDCONTROL_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : BYTEENA_ACLR_B
Value : NONE
Type : Untyped
Parameter Name : WIDTH_BYTEENA_A
Value : 1
Type : Signed Integer
Parameter Name : WIDTH_BYTEENA_B
Value : 1
Type : Untyped
Parameter Name : RAM_BLOCK_TYPE
Value : AUTO
Type : Untyped
Parameter Name : BYTE_SIZE
Value : 8
Type : Untyped
Parameter Name : READ_DURING_WRITE_MODE_MIXED_PORTS
Value : DONT_CARE
Type : Untyped
Parameter Name : READ_DURING_WRITE_MODE_PORT_A
Value : NEW_DATA_NO_NBE_READ
Type : Untyped
Parameter Name : READ_DURING_WRITE_MODE_PORT_B
Value : NEW_DATA_NO_NBE_READ
Type : Untyped
Parameter Name : INIT_FILE
Value : led_patterns.mif
Type : Untyped
Parameter Name : INIT_FILE_LAYOUT
Value : PORT_A
Type : Untyped
Parameter Name : MAXIMUM_DEPTH
Value : 0
Type : Untyped
Parameter Name : CLOCK_ENABLE_INPUT_A
Value : BYPASS
Type : Untyped
Parameter Name : CLOCK_ENABLE_INPUT_B
Value : NORMAL
Type : Untyped
Parameter Name : CLOCK_ENABLE_OUTPUT_A
Value : BYPASS
Type : Untyped
Parameter Name : CLOCK_ENABLE_OUTPUT_B
Value : NORMAL
Type : Untyped
Parameter Name : CLOCK_ENABLE_CORE_A
Value : USE_INPUT_CLKEN
Type : Untyped
Parameter Name : CLOCK_ENABLE_CORE_B
Value : USE_INPUT_CLKEN
Type : Untyped
Parameter Name : ENABLE_ECC
Value : FALSE
Type : Untyped
Parameter Name : ECC_PIPELINE_STAGE_ENABLED
Value : FALSE
Type : Untyped
Parameter Name : WIDTH_ECCSTATUS
Value : 3
Type : Untyped
Parameter Name : DEVICE_FAMILY
Value : Cyclone IV E
Type : Untyped
Parameter Name : CBXI_PARAMETER
Value : altsyncram_ro91
Type : Untyped
+--------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------------------------------------------------------------+
; altsyncram Parameter Settings by Entity Instance ;
+-------------------------------------------+------------------------------------------+
; Name ; Value ;
+-------------------------------------------+------------------------------------------+
; Number of entity instances ; 1 ;
; Entity Instance ; rom0:rom|altsyncram:altsyncram_component ;
; -- OPERATION_MODE ; ROM ;
; -- WIDTH_A ; 8 ;
; -- NUMWORDS_A ; 8 ;
; -- OUTDATA_REG_A ; CLOCK0 ;
; -- WIDTH_B ; 1 ;
; -- NUMWORDS_B ; 1 ;
; -- ADDRESS_REG_B ; CLOCK1 ;
; -- OUTDATA_REG_B ; UNREGISTERED ;
; -- RAM_BLOCK_TYPE ; AUTO ;
; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ;
+-------------------------------------------+------------------------------------------+
+-------------------------------+
; Elapsed Time Per Partition ;
+----------------+--------------+
@@ -493,26 +872,49 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
Info: *******************************************************************
Info: Running Quartus II 32-bit Analysis & Synthesis
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
Info: Processing started: Wed Mar 30 11:51:28 2022
Info: Processing started: Wed Mar 30 12:38:26 2022
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (12021): Found 1 design units, including 1 entities, in source file spectrum.v
Info (12023): Found entity 1: spectrum
Info (12021): Found 1 design units, including 1 entities, in source file rom0.v
Info (12023): Found entity 1: rom0
Info (12127): Elaborating entity "spectrum" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at spectrum.v(10): truncated value with size 32 to match size of target (28)
Warning (13024): Output pins are stuck at VCC or GND
Warning (13410): Pin "LED[7]" is stuck at GND
Warning (10230): Verilog HDL assignment warning at spectrum.v(19): truncated value with size 32 to match size of target (21)
Warning (10230): Verilog HDL assignment warning at spectrum.v(21): truncated value with size 32 to match size of target (3)
Info (12128): Elaborating entity "rom0" for hierarchy "rom0:rom"
Info (12128): Elaborating entity "altsyncram" for hierarchy "rom0:rom|altsyncram:altsyncram_component"
Info (12130): Elaborated megafunction instantiation "rom0:rom|altsyncram:altsyncram_component"
Info (12133): Instantiated megafunction "rom0:rom|altsyncram:altsyncram_component" with the following parameter:
Info (12134): Parameter "address_aclr_a" = "NONE"
Info (12134): Parameter "clock_enable_input_a" = "BYPASS"
Info (12134): Parameter "clock_enable_output_a" = "BYPASS"
Info (12134): Parameter "init_file" = "led_patterns.mif"
Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
Info (12134): Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO"
Info (12134): Parameter "lpm_type" = "altsyncram"
Info (12134): Parameter "numwords_a" = "8"
Info (12134): Parameter "operation_mode" = "ROM"
Info (12134): Parameter "outdata_aclr_a" = "NONE"
Info (12134): Parameter "outdata_reg_a" = "CLOCK0"
Info (12134): Parameter "widthad_a" = "3"
Info (12134): Parameter "width_a" = "8"
Info (12134): Parameter "width_byteena_a" = "1"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_ro91.tdf
Info (12023): Found entity 1: altsyncram_ro91
Info (12128): Elaborating entity "altsyncram_ro91" for hierarchy "rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated"
Info (286030): Timing-Driven Synthesis is running
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Info (21057): Implemented 44 device resources after synthesis - the final resource count might be different
Info (21057): Implemented 71 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 1 input pins
Info (21059): Implemented 8 output pins
Info (21061): Implemented 35 logic cells
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 4 warnings
Info: Peak virtual memory: 388 megabytes
Info: Processing ended: Wed Mar 30 11:51:29 2022
Info: Elapsed time: 00:00:01
Info (21061): Implemented 54 logic cells
Info (21064): Implemented 8 RAM segments
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 3 warnings
Info: Peak virtual memory: 384 megabytes
Info: Processing ended: Wed Mar 30 12:38:28 2022
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:01
output_files/spectrum.map.smsg
+1
View File
@@ -0,0 +1 @@
Warning (10268): Verilog HDL information at spectrum.v(18): always construct contains both blocking and non-blocking assignments
output_files/spectrum.map.summary
+6 -6
View File
@@ -1,14 +1,14 @@
Analysis & Synthesis Status : Successful - Wed Mar 30 11:51:29 2022
Analysis & Synthesis Status : Successful - Wed Mar 30 12:38:28 2022
Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
Revision Name : spectrum
Top-level Entity Name : spectrum
Family : Cyclone IV E
Total logic elements : 35
Total combinational functions : 28
Dedicated logic registers : 35
Total registers : 35
Total logic elements : 33
Total combinational functions : 33
Dedicated logic registers : 24
Total registers : 24
Total pins : 9
Total virtual pins : 0
Total memory bits : 0
Total memory bits : 64
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0
output_files/spectrum.sof
BIN
View File
Binary file not shown.
output_files/spectrum.sta.rpt
+5959 -5903
View File
File diff suppressed because it is too large Load Diff
output_files/spectrum.sta.summary
+12 -12
View File
@@ -3,39 +3,39 @@ TimeQuest Timing Analyzer Summary
------------------------------------------------------------
Type : Slow 1200mV 85C Model Setup 'CLOCK_50'
Slack : -1.606
TNS : -30.234
Slack : -2.763
TNS : -43.394
Type : Slow 1200mV 85C Model Hold 'CLOCK_50'
Slack : 0.360
Slack : 0.343
TNS : 0.000
Type : Slow 1200mV 85C Model Minimum Pulse Width 'CLOCK_50'
Slack : -3.000
TNS : -38.000
TNS : -46.633
Type : Slow 1200mV 0C Model Setup 'CLOCK_50'
Slack : -1.275
TNS : -22.690
Slack : -2.331
TNS : -34.994
Type : Slow 1200mV 0C Model Hold 'CLOCK_50'
Slack : 0.319
Slack : 0.299
TNS : 0.000
Type : Slow 1200mV 0C Model Minimum Pulse Width 'CLOCK_50'
Slack : -3.000
TNS : -38.000
TNS : -46.624
Type : Fast 1200mV 0C Model Setup 'CLOCK_50'
Slack : -0.500
TNS : -4.764
Slack : -1.122
TNS : -9.363
Type : Fast 1200mV 0C Model Hold 'CLOCK_50'
Slack : 0.193
Slack : 0.178
TNS : 0.000
Type : Fast 1200mV 0C Model Minimum Pulse Width 'CLOCK_50'
Slack : -3.000
TNS : -48.277
TNS : -45.480
------------------------------------------------------------
rom0.cnx
+98
View File
@@ -0,0 +1,98 @@
VERSION: WM1.0
MODULE: altsyncram
PRIVATE: ADDRESSSTALL_A NUMERIC "0"
PRIVATE: AclrAddr NUMERIC "0"
PRIVATE: AclrByte NUMERIC "0"
PRIVATE: AclrOutput NUMERIC "0"
PRIVATE: BYTE_ENABLE NUMERIC "0"
PRIVATE: BYTE_SIZE NUMERIC "8"
PRIVATE: BlankMemory NUMERIC "0"
PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
PRIVATE: Clken NUMERIC "0"
PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
PRIVATE: INIT_TO_SIM_X NUMERIC "0"
PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
PRIVATE: JTAG_ENABLED NUMERIC "0"
PRIVATE: JTAG_ID STRING "NONE"
PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
PRIVATE: MIFfilename STRING "led_patterns.mif"
PRIVATE: NUMWORDS_A NUMERIC "8"
PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
PRIVATE: RegAddr NUMERIC "1"
PRIVATE: RegOutput NUMERIC "1"
PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
PRIVATE: SingleClock NUMERIC "1"
PRIVATE: UseDQRAM NUMERIC "0"
PRIVATE: WidthAddr NUMERIC "3"
PRIVATE: WidthData NUMERIC "8"
PRIVATE: rden NUMERIC "0"
LIBRARY: altera_mf altera_mf.altera_mf_components.all
CONSTANT: ADDRESS_ACLR_A STRING "NONE"
CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
CONSTANT: INIT_FILE STRING "led_patterns.mif"
CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
CONSTANT: LPM_TYPE STRING "altsyncram"
CONSTANT: NUMWORDS_A NUMERIC "8"
CONSTANT: OPERATION_MODE STRING "ROM"
CONSTANT: OUTDATA_ACLR_A STRING "NONE"
CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
CONSTANT: WIDTHAD_A NUMERIC "3"
CONSTANT: WIDTH_A NUMERIC "8"
CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
USED_PORT: address 0 0 3 0 INPUT NODEFVAL "address[2..0]"
USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
CONNECT: @address_a 0 0 3 0 address 0 0 3 0
CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
CONNECT: q 0 0 8 0 @q_a 0 0 8 0
GEN_FILE: TYPE_NORMAL rom0.v TRUE
GEN_FILE: TYPE_NORMAL rom0.inc FALSE
GEN_FILE: TYPE_NORMAL rom0.cmp FALSE
GEN_FILE: TYPE_NORMAL rom0.bsf FALSE
GEN_FILE: TYPE_NORMAL rom0_inst.v FALSE
GEN_FILE: TYPE_NORMAL rom0_bb.v TRUE
LIB_FILE: altera_mf
LICENSE_ID: "DEVICE_FAMILY_Cyclone III" 30229803K6032210322T
LICENSE_ID: "DEVICE_FAMILY_Cyclone IV E" 30229803A6032210322A
LICENSE_ID: "DEVICE_FAMILY_Cyclone V" 30229803A6032210322B
LICENSE_ID: "DEVICE_FAMILY_Cyclone IV GX" 30229803A6032210322B
LICENSE_ID: "DEVICE_FAMILY_Cyclone III LS" 30229803A6032210322B
LICENSE_ID: "FEATURE_STRATIXGX_DPA" 30229803M6032210322T
LICENSE_ID: "FEATURE_STRATIXGX_BASIC" 30229803A6032210322B
SUPPORTED_DEVICE_FAMILY: "Cyclone III"
SUPPORTED_DEVICE_FAMILY: "Cyclone IV E"
SUPPORTED_DEVICE_FAMILY: "Cyclone V"
SUPPORTED_DEVICE_FAMILY: "Cyclone IV GX"
SUPPORTED_DEVICE_FAMILY: "Cyclone III LS"
SUPPORTED_DEVICE_FAMILY: "Cyclone IV E"
WIZARD_TITLE: "ROM: 1-PORT"
QUARTUS_VERSION: "Version 13.1"
QUARTUS_SVERSION: "13.1.0 Build 162 10/23/2013 SJ Web Edition:10/23/2013"
QUARTUS_BUILD_DATE: "10/23/2013"
ALTERA_COPYRIGHT: "Copyright (C) 1991-2013 Altera Corporation"
RESC_INFO: ON
HELP_MENU_ITEM: FALSE "IUG_ALIAS$STRATIX_WEB_LINK$http://www.altera.com/literature/hb/stx/ch_3_vol_2.pdf"
HELP_MENU_ITEM: FALSE "ALIAS$STRATIX_WEB_MENU_LABEL$TriMatrix Memory Blocks in Stratix (GX)"
HELP_MENU_ITEM: FALSE "IUG_ALIAS$CYCLONE_IV_WEB_LINK$http://www.altera.com/literature/hb/cyclone-iv/cyiv-51003.pdf"
HELP_MENU_ITEM: FALSE "ALIAS$CYCLONE_IV_WEB_MENU_LABEL$Cyclone IV Memory Blocks"
HELP_MENU_ITEM: FALSE "IUG_ALIAS$CYCLONEII_WEB_LINK$http://www.altera.com/literature/hb/cyc2/cyc2_cii51008.pdf"
HELP_MENU_ITEM: FALSE "ALIAS$CYCLONEII_WEB_MENU_LABEL$Cyclone II Memory Blocks"
HELP_MENU_ITEM: FALSE "IUG_ALIAS$CYCLONE_WEB_LINK$http://www.altera.com/literature/hb/cyc/cyc_c51007.pdf"
HELP_MENU_ITEM: FALSE "ALIAS$CYCLONE_WEB_MENU_LABEL$Memory Implementations Using Cyclone Memory Blocks"
HELP_MENU_ITEM: FALSE "IUG_ALIAS$STRATIXII_WEB_LINK$http://www.altera.com/literature/hb/stx2/stx2_sii52002.pdf"
HELP_MENU_ITEM: FALSE "ALIAS$STRATIXII_WEB_MENU_LABEL$TriMatrix Memory Blocks in Stratix II"
HELP_MENU_ITEM: FALSE "IUG_ALIAS$STRATIXIII_WEB_LINK$http://www.altera.com/literature/hb/stx3/stx3_siii51004.pdf"
HELP_MENU_ITEM: FALSE "ALIAS$STRATIXIII_WEB_MENU_LABEL$TriMatrix Embedded Memory Blocks in Stratix III"
HELP_MENU_ITEM: FALSE "IUG_ALIAS$APEX_WEB_LINK$http://www.altera.com/literature/an/an179.pdf"
HELP_MENU_ITEM: FALSE "ALIAS$APEX_WEB_MENU_LABEL$Designing with ESBs"
HELP_MENU_ITEM: FALSE "IUG$ROM Megafunction User Guide$http://www.altera.com/literature/ug/ug_memrom.pdf"
rom0.qip
+4
View File
@@ -0,0 +1,4 @@
set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "rom0.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "rom0_bb.v"]
rom0.v
+159
View File
@@ -0,0 +1,159 @@
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: rom0.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module rom0 (
address,
clock,
q);
input [2:0] address;
input clock;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({8{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "led_patterns.mif",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 8,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.widthad_a = 3,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "led_patterns.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "3"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "led_patterns.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "3"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 3 0 INPUT NODEFVAL "address[2..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: CONNECT: @address_a 0 0 3 0 address 0 0 3 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL rom0.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom0.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom0.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom0.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom0_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom0_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
rom0_bb.v
+110
View File
@@ -0,0 +1,110 @@
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: rom0.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module rom0 (
address,
clock,
q);
input [2:0] address;
input clock;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "led_patterns.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "3"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "led_patterns.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "3"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 3 0 INPUT NODEFVAL "address[2..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: CONNECT: @address_a 0 0 3 0 address 0 0 3 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL rom0.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom0.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom0.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom0.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom0_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom0_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
simulation/modelsim/spectrum.vo
+1059 -1259
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File diff suppressed because it is too large Load Diff
simulation/modelsim/spectrum_6_1200mv_0c_slow.vo
+1059 -1259
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File diff suppressed because it is too large Load Diff
simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo
+602 -643
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File diff suppressed because it is too large Load Diff
simulation/modelsim/spectrum_6_1200mv_85c_slow.vo
+1059 -1259
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File diff suppressed because it is too large Load Diff
simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo
+298 -339
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File diff suppressed because it is too large Load Diff
simulation/modelsim/spectrum_min_1200mv_0c_fast.vo
+1059 -1259
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File diff suppressed because it is too large Load Diff
simulation/modelsim/spectrum_min_1200mv_0c_v_fast.sdo
+340 -381
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File diff suppressed because it is too large Load Diff
simulation/modelsim/spectrum_modelsim.xrf
+72 -69
View File
@@ -1,6 +1,21 @@
vendor_name = ModelSim
source_file = 1, /home/benny/work/fpga/projects/spectrum.v
source_file = 1, /home/benny/work/fpga/projects/output_files/led_patterns.mif
source_file = 1, /home/benny/work/fpga/projects/led_patterns.mif
source_file = 1, /home/benny/work/fpga/projects/rom0.qip
source_file = 1, /home/benny/work/fpga/projects/rom0.v
source_file = 1, /home/benny/work/fpga/projects/db/spectrum.cbx.xml
source_file = 1, /home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf
source_file = 1, /home/benny/altera/13.1/quartus/libraries/megafunctions/stratix_ram_block.inc
source_file = 1, /home/benny/altera/13.1/quartus/libraries/megafunctions/lpm_mux.inc
source_file = 1, /home/benny/altera/13.1/quartus/libraries/megafunctions/lpm_decode.inc
source_file = 1, /home/benny/altera/13.1/quartus/libraries/megafunctions/aglobal131.inc
source_file = 1, /home/benny/altera/13.1/quartus/libraries/megafunctions/a_rdenreg.inc
source_file = 1, /home/benny/altera/13.1/quartus/libraries/megafunctions/altrom.inc
source_file = 1, /home/benny/altera/13.1/quartus/libraries/megafunctions/altram.inc
source_file = 1, /home/benny/altera/13.1/quartus/libraries/megafunctions/altdpram.inc
source_file = 1, /home/benny/altera/13.1/quartus/libraries/megafunctions/cbx.lst
source_file = 1, /home/benny/work/fpga/projects/db/altsyncram_ro91.tdf
design_name = spectrum
instance = comp, \LED[0]~output , LED[0]~output, spectrum, 1
instance = comp, \LED[1]~output , LED[1]~output, spectrum, 1
@@ -12,73 +27,61 @@ instance = comp, \LED[6]~output , LED[6]~output, spectrum, 1
instance = comp, \LED[7]~output , LED[7]~output, spectrum, 1
instance = comp, \CLOCK_50~input , CLOCK_50~input, spectrum, 1
instance = comp, \CLOCK_50~inputclkctrl , CLOCK_50~inputclkctrl, spectrum, 1
instance = comp, \counter[0]~81 , counter[0]~81, spectrum, 1
instance = comp, \counter[0] , counter[0], spectrum, 1
instance = comp, \counter[1]~27 , counter[1]~27, spectrum, 1
instance = comp, \counter[1] , counter[1], spectrum, 1
instance = comp, \counter[2]~29 , counter[2]~29, spectrum, 1
instance = comp, \counter[2] , counter[2], spectrum, 1
instance = comp, \counter[3]~31 , counter[3]~31, spectrum, 1
instance = comp, \counter[3] , counter[3], spectrum, 1
instance = comp, \counter[4]~33 , counter[4]~33, spectrum, 1
instance = comp, \counter[4] , counter[4], spectrum, 1
instance = comp, \counter[5]~35 , counter[5]~35, spectrum, 1
instance = comp, \counter[5] , counter[5], spectrum, 1
instance = comp, \counter[6]~37 , counter[6]~37, spectrum, 1
instance = comp, \counter[6] , counter[6], spectrum, 1
instance = comp, \counter[7]~39 , counter[7]~39, spectrum, 1
instance = comp, \counter[7] , counter[7], spectrum, 1
instance = comp, \counter[8]~41 , counter[8]~41, spectrum, 1
instance = comp, \counter[8] , counter[8], spectrum, 1
instance = comp, \counter[9]~43 , counter[9]~43, spectrum, 1
instance = comp, \counter[9] , counter[9], spectrum, 1
instance = comp, \counter[10]~45 , counter[10]~45, spectrum, 1
instance = comp, \counter[10] , counter[10], spectrum, 1
instance = comp, \counter[11]~47 , counter[11]~47, spectrum, 1
instance = comp, \counter[11] , counter[11], spectrum, 1
instance = comp, \counter[12]~49 , counter[12]~49, spectrum, 1
instance = comp, \counter[12] , counter[12], spectrum, 1
instance = comp, \counter[13]~51 , counter[13]~51, spectrum, 1
instance = comp, \counter[13] , counter[13], spectrum, 1
instance = comp, \counter[14]~53 , counter[14]~53, spectrum, 1
instance = comp, \counter[14] , counter[14], spectrum, 1
instance = comp, \counter[15]~55 , counter[15]~55, spectrum, 1
instance = comp, \counter[15] , counter[15], spectrum, 1
instance = comp, \counter[16]~57 , counter[16]~57, spectrum, 1
instance = comp, \counter[16] , counter[16], spectrum, 1
instance = comp, \counter[17]~59 , counter[17]~59, spectrum, 1
instance = comp, \counter[17] , counter[17], spectrum, 1
instance = comp, \counter[18]~61 , counter[18]~61, spectrum, 1
instance = comp, \counter[18] , counter[18], spectrum, 1
instance = comp, \counter[19]~63 , counter[19]~63, spectrum, 1
instance = comp, \counter[19] , counter[19], spectrum, 1
instance = comp, \counter[20]~65 , counter[20]~65, spectrum, 1
instance = comp, \counter[20] , counter[20], spectrum, 1
instance = comp, \counter[21]~67 , counter[21]~67, spectrum, 1
instance = comp, \counter[21] , counter[21], spectrum, 1
instance = comp, \LED[0]~reg0feeder , LED[0]~reg0feeder, spectrum, 1
instance = comp, \LED[0]~reg0 , LED[0]~reg0, spectrum, 1
instance = comp, \counter[22]~69 , counter[22]~69, spectrum, 1
instance = comp, \counter[22] , counter[22], spectrum, 1
instance = comp, \LED[1]~reg0feeder , LED[1]~reg0feeder, spectrum, 1
instance = comp, \LED[1]~reg0 , LED[1]~reg0, spectrum, 1
instance = comp, \counter[23]~71 , counter[23]~71, spectrum, 1
instance = comp, \counter[23] , counter[23], spectrum, 1
instance = comp, \LED[2]~reg0feeder , LED[2]~reg0feeder, spectrum, 1
instance = comp, \LED[2]~reg0 , LED[2]~reg0, spectrum, 1
instance = comp, \counter[24]~73 , counter[24]~73, spectrum, 1
instance = comp, \counter[24] , counter[24], spectrum, 1
instance = comp, \LED[3]~reg0feeder , LED[3]~reg0feeder, spectrum, 1
instance = comp, \LED[3]~reg0 , LED[3]~reg0, spectrum, 1
instance = comp, \counter[25]~75 , counter[25]~75, spectrum, 1
instance = comp, \counter[25] , counter[25], spectrum, 1
instance = comp, \LED[4]~reg0feeder , LED[4]~reg0feeder, spectrum, 1
instance = comp, \LED[4]~reg0 , LED[4]~reg0, spectrum, 1
instance = comp, \counter[26]~77 , counter[26]~77, spectrum, 1
instance = comp, \counter[26] , counter[26], spectrum, 1
instance = comp, \LED[5]~reg0feeder , LED[5]~reg0feeder, spectrum, 1
instance = comp, \LED[5]~reg0 , LED[5]~reg0, spectrum, 1
instance = comp, \counter[27]~79 , counter[27]~79, spectrum, 1
instance = comp, \counter[27] , counter[27], spectrum, 1
instance = comp, \LED[6]~reg0feeder , LED[6]~reg0feeder, spectrum, 1
instance = comp, \LED[6]~reg0 , LED[6]~reg0, spectrum, 1
instance = comp, \Add0~0 , Add0~0, spectrum, 1
instance = comp, \counter[0] , counter[0], spectrum, 1
instance = comp, \Add0~2 , Add0~2, spectrum, 1
instance = comp, \counter[1] , counter[1], spectrum, 1
instance = comp, \Add0~4 , Add0~4, spectrum, 1
instance = comp, \counter[2] , counter[2], spectrum, 1
instance = comp, \Add0~6 , Add0~6, spectrum, 1
instance = comp, \counter[3] , counter[3], spectrum, 1
instance = comp, \Add0~8 , Add0~8, spectrum, 1
instance = comp, \counter[4] , counter[4], spectrum, 1
instance = comp, \Add0~10 , Add0~10, spectrum, 1
instance = comp, \counter[5] , counter[5], spectrum, 1
instance = comp, \Add0~12 , Add0~12, spectrum, 1
instance = comp, \counter[6] , counter[6], spectrum, 1
instance = comp, \Add0~14 , Add0~14, spectrum, 1
instance = comp, \counter[7] , counter[7], spectrum, 1
instance = comp, \Add0~16 , Add0~16, spectrum, 1
instance = comp, \counter[8] , counter[8], spectrum, 1
instance = comp, \Add0~18 , Add0~18, spectrum, 1
instance = comp, \counter[9] , counter[9], spectrum, 1
instance = comp, \Add0~20 , Add0~20, spectrum, 1
instance = comp, \counter[10] , counter[10], spectrum, 1
instance = comp, \Add0~22 , Add0~22, spectrum, 1
instance = comp, \counter[11] , counter[11], spectrum, 1
instance = comp, \Add0~24 , Add0~24, spectrum, 1
instance = comp, \counter[12] , counter[12], spectrum, 1
instance = comp, \Add0~26 , Add0~26, spectrum, 1
instance = comp, \counter[13] , counter[13], spectrum, 1
instance = comp, \Add0~28 , Add0~28, spectrum, 1
instance = comp, \counter[14] , counter[14], spectrum, 1
instance = comp, \Add0~30 , Add0~30, spectrum, 1
instance = comp, \counter[15] , counter[15], spectrum, 1
instance = comp, \Add0~32 , Add0~32, spectrum, 1
instance = comp, \counter[16] , counter[16], spectrum, 1
instance = comp, \Add0~34 , Add0~34, spectrum, 1
instance = comp, \counter[17] , counter[17], spectrum, 1
instance = comp, \Add0~36 , Add0~36, spectrum, 1
instance = comp, \counter[18] , counter[18], spectrum, 1
instance = comp, \Add0~38 , Add0~38, spectrum, 1
instance = comp, \counter[19] , counter[19], spectrum, 1
instance = comp, \Add0~40 , Add0~40, spectrum, 1
instance = comp, \Equal0~5 , Equal0~5, spectrum, 1
instance = comp, \Equal0~1 , Equal0~1, spectrum, 1
instance = comp, \Equal0~0 , Equal0~0, spectrum, 1
instance = comp, \Equal0~2 , Equal0~2, spectrum, 1
instance = comp, \Equal0~3 , Equal0~3, spectrum, 1
instance = comp, \Equal0~4 , Equal0~4, spectrum, 1
instance = comp, \address[0]~0 , address[0]~0, spectrum, 1
instance = comp, \address[0] , address[0], spectrum, 1
instance = comp, \Equal0~6 , Equal0~6, spectrum, 1
instance = comp, \Equal0~7 , Equal0~7, spectrum, 1
instance = comp, \address[1]~1 , address[1]~1, spectrum, 1
instance = comp, \address[1] , address[1], spectrum, 1
instance = comp, \address[1]~2 , address[1]~2, spectrum, 1
instance = comp, \address[2]~3 , address[2]~3, spectrum, 1
instance = comp, \address[2] , address[2], spectrum, 1
instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a0 , rom|altsyncram_component|auto_generated|ram_block1a0, spectrum, 1
simulation/modelsim/spectrum_v.sdo
+298 -339
View File
File diff suppressed because it is too large Load Diff
spectrum.qsf
+3
View File
@@ -407,4 +407,7 @@ set_location_assignment PIN_J14 -to GPIO_1[33]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[33]
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_global_assignment -name MIF_FILE output_files/led_patterns.mif
set_global_assignment -name MIF_FILE led_patterns.mif
set_global_assignment -name QIP_FILE rom0.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
spectrum.v
+14 -4
View File
@@ -1,14 +1,24 @@
module spectrum(
input CLOCK_50,
output reg[7:0] LED
output wire[7:0] LED
);
reg[27:0] counter;
reg[2:0] address;
wire[7:0] mem_data;
rom0 rom(
.address(address),
.clock(CLOCK_50),
.q(mem_data)
);
reg[20:0] counter;
always @(posedge CLOCK_50)
begin
counter <= counter + 1;
LED <= counter[27:21];
counter = counter + 1;
if (counter == 0)
address = address + 1;
end
assign LED = mem_data;
endmodule