diff --git a/db/altsyncram_ro91.tdf b/db/altsyncram_ro91.tdf new file mode 100644 index 0000000..d0ef258 --- /dev/null +++ b/db/altsyncram_ro91.tdf @@ -0,0 +1,219 @@ +--altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" ENABLE_RUNTIME_MOD="NO" INIT_FILE="led_patterns.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=8 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="CLOCK0" WIDTH_A=8 WIDTH_BYTEENA_A=1 WIDTHAD_A=3 address_a clock0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 13.1 cbx_altsyncram 2013:10:17:09:48:19:SJ cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_lpm_mux 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ cbx_stratixiii 2013:10:17:09:48:19:SJ cbx_stratixv 2013:10:17:09:48:19:SJ cbx_util_mgl 2013:10:17:09:48:19:SJ VERSION_END + + +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) +RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = M9K 1 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_ro91 +( + address_a[2..0] : input; + clock0 : input; + q_a[7..0] : output; +) +VARIABLE + ram_block1a0 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 3, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 7, + PORT_A_LOGICAL_RAM_DEPTH = 8, + PORT_A_LOGICAL_RAM_WIDTH = 8, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 3, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 7, + PORT_A_LOGICAL_RAM_DEPTH = 8, + PORT_A_LOGICAL_RAM_WIDTH = 8, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 3, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 7, + PORT_A_LOGICAL_RAM_DEPTH = 8, + PORT_A_LOGICAL_RAM_WIDTH = 8, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 3, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 7, + PORT_A_LOGICAL_RAM_DEPTH = 8, + PORT_A_LOGICAL_RAM_WIDTH = 8, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 3, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 7, + PORT_A_LOGICAL_RAM_DEPTH = 8, + PORT_A_LOGICAL_RAM_WIDTH = 8, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 3, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 7, + PORT_A_LOGICAL_RAM_DEPTH = 8, + PORT_A_LOGICAL_RAM_WIDTH = 8, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 3, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 7, + PORT_A_LOGICAL_RAM_DEPTH = 8, + PORT_A_LOGICAL_RAM_WIDTH = 8, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "led_patterns.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 3, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 7, + PORT_A_LOGICAL_RAM_DEPTH = 8, + PORT_A_LOGICAL_RAM_WIDTH = 8, + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_wire[2..0] : WIRE; + +BEGIN + ram_block1a[7..0].clk0 = clock0; + ram_block1a[7..0].portaaddr[] = ( address_a_wire[2..0]); + ram_block1a[7..0].portare = B"11111111"; + address_a_wire[] = address_a[]; + q_a[] = ( ram_block1a[7..0].portadataout[0..0]); +END; +--VALID FILE diff --git a/db/logic_util_heursitic.dat b/db/logic_util_heursitic.dat index ba84581..02d6608 100644 Binary files a/db/logic_util_heursitic.dat and b/db/logic_util_heursitic.dat differ diff --git a/db/prev_cmp_spectrum.qmsg b/db/prev_cmp_spectrum.qmsg index 9b1b973..5fb3e8b 100644 --- a/db/prev_cmp_spectrum.qmsg +++ b/db/prev_cmp_spectrum.qmsg @@ -1,127 +1,135 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648630228952 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648630228953 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 11:50:28 2022 " "Processing started: Wed Mar 30 11:50:28 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648630228953 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648630228953 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum " "Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648630228953 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648630229117 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spectrum.v 1 1 " "Found 1 design units, including 1 entities, in source file spectrum.v" { { "Info" "ISGN_ENTITY_NAME" "1 spectrum " "Found entity 1: spectrum" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648630229180 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648630229180 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "spectrum " "Elaborating entity \"spectrum\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1648630229231 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 spectrum.v(10) " "Verilog HDL assignment warning at spectrum.v(10): truncated value with size 32 to match size of target (23)" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 10 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1648630229232 "|spectrum"} -{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[7\] GND " "Pin \"LED\[7\]\" is stuck at GND" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 8 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648630229558 "|spectrum|LED[7]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1648630229558 ""} -{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1648630229650 ""} -{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1648630229841 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648630229841 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "39 " "Implemented 39 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Implemented 1 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1648630229879 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1648630229879 ""} { "Info" "ICUT_CUT_TM_LCELLS" "30 " "Implemented 30 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1648630229879 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1648630229879 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "379 " "Peak virtual memory: 379 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648630229887 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 11:50:29 2022 " "Processing ended: Wed Mar 30 11:50:29 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648630229887 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648630229887 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648630229887 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648630229887 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648630231222 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648630231223 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 11:50:30 2022 " "Processing started: Wed Mar 30 11:50:30 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648630231223 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1648630231223 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_fit --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1648630231223 ""} -{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1648630231248 ""} -{ "Info" "0" "" "Project = spectrum" { } { } 0 0 "Project = spectrum" 0 0 "Fitter" 0 0 1648630231249 ""} -{ "Info" "0" "" "Revision = spectrum" { } { } 0 0 "Revision = spectrum" 0 0 "Fitter" 0 0 1648630231249 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1648630231293 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "spectrum EP4CE22F17C6 " "Selected device EP4CE22F17C6 for design \"spectrum\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1648630231296 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648630231334 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648630231334 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648630231334 ""} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1648630231406 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1648630231416 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17C6 " "Device EP4CE10F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648630231621 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C6 " "Device EP4CE6F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648630231621 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C6 " "Device EP4CE15F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648630231621 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1648630231621 ""} -{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 260 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648630231626 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 262 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648630231626 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 264 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648630231626 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 266 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648630231626 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 268 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648630231626 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1648630231626 ""} -{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1648630231628 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "spectrum.sdc " "Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1648630232273 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1648630232273 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1648630232275 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1648630232275 ""} -{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1648630232276 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p)) " "Automatically promoted node CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G18 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648630232282 ""} } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 255 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648630232282 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1648630232513 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648630232513 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648630232513 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648630232514 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648630232515 ""} -{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1648630232515 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1648630232515 ""} -{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1648630232515 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1648630232527 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1648630232527 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1648630232527 ""} -{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS_N " "Node \"ADC_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SADDR " "Node \"ADC_SADDR\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SADDR" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCLK " "Node \"ADC_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDAT " "Node \"ADC_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_ASDO " "Node \"EPCS_ASDO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_ASDO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DATA0 " "Node \"EPCS_DATA0\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DATA0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DCLK " "Node \"EPCS_DCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_NCSO " "Node \"EPCS_NCSO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_NCSO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[0\] " "Node \"GPIO_0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[10\] " "Node \"GPIO_0\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[11\] " "Node \"GPIO_0\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[12\] " "Node \"GPIO_0\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[13\] " "Node \"GPIO_0\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[14\] " "Node \"GPIO_0\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[15\] " "Node \"GPIO_0\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[16\] " "Node \"GPIO_0\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[17\] " "Node \"GPIO_0\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[18\] " "Node \"GPIO_0\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[19\] " "Node \"GPIO_0\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[1\] " "Node \"GPIO_0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[20\] " "Node \"GPIO_0\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[21\] " "Node \"GPIO_0\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[22\] " "Node \"GPIO_0\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[23\] " "Node \"GPIO_0\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[24\] " "Node \"GPIO_0\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[25\] " "Node \"GPIO_0\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[26\] " "Node \"GPIO_0\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[27\] " "Node \"GPIO_0\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[28\] " "Node \"GPIO_0\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[29\] " "Node \"GPIO_0\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[2\] " "Node \"GPIO_0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[30\] " "Node \"GPIO_0\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[31\] " "Node \"GPIO_0\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[32\] " "Node \"GPIO_0\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[33\] " "Node \"GPIO_0\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[3\] " "Node \"GPIO_0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[4\] " "Node \"GPIO_0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[5\] " "Node \"GPIO_0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[6\] " "Node \"GPIO_0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[7\] " "Node \"GPIO_0\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[8\] " "Node \"GPIO_0\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[9\] " "Node \"GPIO_0\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[0\] " "Node \"GPIO_0_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[1\] " "Node \"GPIO_0_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[0\] " "Node \"GPIO_1\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[10\] " "Node \"GPIO_1\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[11\] " "Node \"GPIO_1\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[12\] " "Node \"GPIO_1\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[13\] " "Node \"GPIO_1\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[14\] " "Node \"GPIO_1\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[15\] " "Node \"GPIO_1\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[16\] " "Node \"GPIO_1\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[17\] " "Node \"GPIO_1\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[18\] " "Node \"GPIO_1\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[19\] " "Node \"GPIO_1\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[1\] " "Node \"GPIO_1\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[20\] " "Node \"GPIO_1\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[21\] " "Node \"GPIO_1\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[22\] " "Node \"GPIO_1\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[23\] " "Node \"GPIO_1\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[24\] " "Node \"GPIO_1\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[25\] " "Node \"GPIO_1\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[26\] " "Node \"GPIO_1\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[27\] " "Node \"GPIO_1\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[28\] " "Node \"GPIO_1\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[29\] " "Node \"GPIO_1\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[2\] " "Node \"GPIO_1\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[30\] " "Node \"GPIO_1\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[31\] " "Node \"GPIO_1\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[32\] " "Node \"GPIO_1\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[33\] " "Node \"GPIO_1\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[3\] " "Node \"GPIO_1\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[4\] " "Node \"GPIO_1\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[5\] " "Node \"GPIO_1\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[6\] " "Node \"GPIO_1\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[7\] " "Node \"GPIO_1\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[8\] " "Node \"GPIO_1\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[9\] " "Node \"GPIO_1\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[0\] " "Node \"GPIO_1_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[1\] " "Node \"GPIO_1_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[0\] " "Node \"GPIO_2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[10\] " "Node \"GPIO_2\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[11\] " "Node \"GPIO_2\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[12\] " "Node \"GPIO_2\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[1\] " "Node \"GPIO_2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[2\] " "Node \"GPIO_2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[3\] " "Node \"GPIO_2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[4\] " "Node \"GPIO_2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[5\] " "Node \"GPIO_2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[6\] " "Node \"GPIO_2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[7\] " "Node \"GPIO_2\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[8\] " "Node \"GPIO_2\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[9\] " "Node \"GPIO_2\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[0\] " "Node \"GPIO_2_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[1\] " "Node \"GPIO_2_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[2\] " "Node \"GPIO_2_IN\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_CS_N " "Node \"G_SENSOR_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_INT " "Node \"G_SENSOR_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630232539 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1648630232539 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648630232545 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1648630233501 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648630233566 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1648630233574 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1648630233971 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648630233971 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1648630234209 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X32_Y23 X42_Y34 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X32_Y23 to location X42_Y34" { } { { "loc" "" { Generic "/home/benny/work/fpga/projects/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X32_Y23 to location X42_Y34"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X32_Y23 to location X42_Y34"} 32 23 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1648630234782 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1648630234782 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648630235154 ""} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1648630235154 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1648630235154 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.18 " "Total time spent on timing analysis during the Fitter is 0.18 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1648630235163 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648630235216 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648630235373 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648630235419 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648630235548 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648630235825 ""} -{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1648630236172 ""} -{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "1 Cyclone IV E " "1 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK_50 3.3-V LVTTL R8 " "Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at R8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { CLOCK_50 } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 12 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648630236175 ""} } { } 0 169177 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1648630236175 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/projects/output_files/spectrum.fit.smsg " "Generated suppressed messages file /home/benny/work/fpga/projects/output_files/spectrum.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1648630236217 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 152 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 152 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "588 " "Peak virtual memory: 588 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648630236394 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 11:50:36 2022 " "Processing ended: Wed Mar 30 11:50:36 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648630236394 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648630236394 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648630236394 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1648630236394 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1648630237921 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648630237922 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 11:50:37 2022 " "Processing started: Wed Mar 30 11:50:37 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648630237922 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1648630237922 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1648630237922 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1648630238828 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1648630238854 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "390 " "Peak virtual memory: 390 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648630239091 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 11:50:39 2022 " "Processing ended: Wed Mar 30 11:50:39 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648630239091 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648630239091 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648630239091 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1648630239091 ""} -{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1648630239178 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1648630240458 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648630240459 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 11:50:40 2022 " "Processing started: Wed Mar 30 11:50:40 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648630240459 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648630240459 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta spectrum -c spectrum " "Command: quartus_sta spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648630240459 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1648630240487 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648630240585 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648630240587 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648630240628 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648630240628 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "spectrum.sdc " "Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1648630240821 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1648630240821 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648630240822 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648630240822 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1648630240947 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648630240947 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1648630240948 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1648630240953 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648630240960 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648630240960 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.257 " "Worst-case setup slack is -1.257" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630240961 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630240961 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.257 -21.840 CLOCK_50 " " -1.257 -21.840 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630240961 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630240961 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.361 " "Worst-case hold slack is 0.361" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630240962 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630240962 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.361 0.000 CLOCK_50 " " 0.361 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630240962 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630240962 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648630240962 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648630240963 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630240963 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630240963 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -33.000 CLOCK_50 " " -3.000 -33.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630240963 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630240963 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648630240977 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1648630241000 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1648630241363 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648630241379 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648630241380 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648630241380 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.976 " "Worst-case setup slack is -0.976" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630241381 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630241381 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.976 -15.990 CLOCK_50 " " -0.976 -15.990 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630241381 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630241381 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.319 " "Worst-case hold slack is 0.319" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630241382 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630241382 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.319 0.000 CLOCK_50 " " 0.319 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630241382 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630241382 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648630241383 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648630241384 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630241385 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630241385 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -33.000 CLOCK_50 " " -3.000 -33.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630241385 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630241385 ""} -{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648630241400 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648630241519 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648630241519 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648630241519 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.296 " "Worst-case setup slack is -0.296" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630241521 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630241521 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.296 -2.219 CLOCK_50 " " -0.296 -2.219 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630241521 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630241521 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.193 " "Worst-case hold slack is 0.193" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630241522 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630241522 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.193 0.000 CLOCK_50 " " 0.193 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630241522 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630241522 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648630241524 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648630241525 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630241527 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630241527 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -41.779 CLOCK_50 " " -3.000 -41.779 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630241527 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630241527 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648630241819 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648630241819 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "416 " "Peak virtual memory: 416 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648630241853 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 11:50:41 2022 " "Processing ended: Wed Mar 30 11:50:41 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648630241853 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648630241853 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648630241853 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648630241853 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648630243435 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648630243435 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 11:50:43 2022 " "Processing started: Wed Mar 30 11:50:43 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648630243435 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648630243435 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648630243436 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630243721 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630243741 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_fast.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_fast.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630243760 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630243780 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630243800 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630243819 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_v_fast.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630243838 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_v.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_v.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630243856 ""} -{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "352 " "Peak virtual memory: 352 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648630243887 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 11:50:43 2022 " "Processing ended: Wed Mar 30 11:50:43 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648630243887 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648630243887 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648630243887 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648630243887 ""} -{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 161 s " "Quartus II Full Compilation was successful. 0 errors, 161 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648630243976 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648632788486 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648632788487 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 12:33:08 2022 " "Processing started: Wed Mar 30 12:33:08 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648632788487 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648632788487 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum " "Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648632788487 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648632788648 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spectrum.v 1 1 " "Found 1 design units, including 1 entities, in source file spectrum.v" { { "Info" "ISGN_ENTITY_NAME" "1 spectrum " "Found entity 1: spectrum" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648632788712 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648632788712 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom0.v 1 1 " "Found 1 design units, including 1 entities, in source file rom0.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom0 " "Found entity 1: rom0" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648632788715 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648632788715 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "spectrum " "Elaborating entity \"spectrum\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1648632788766 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 21 spectrum.v(19) " "Verilog HDL assignment warning at spectrum.v(19): truncated value with size 32 to match size of target (21)" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 19 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1648632788767 "|spectrum"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 spectrum.v(21) " "Verilog HDL assignment warning at spectrum.v(21): truncated value with size 32 to match size of target (3)" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 21 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1648632788767 "|spectrum"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom0 rom0:rom " "Elaborating entity \"rom0\" for hierarchy \"rom0:rom\"" { } { { "spectrum.v" "rom" { Text "/home/benny/work/fpga/projects/spectrum.v" 14 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648632788769 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram rom0:rom\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "altsyncram_component" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648632788816 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "rom0:rom\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648632788817 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rom0:rom\|altsyncram:altsyncram_component " "Instantiated megafunction \"rom0:rom\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648632788818 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648632788818 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648632788818 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file led_patterns.mif " "Parameter \"init_file\" = \"led_patterns.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648632788818 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648632788818 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648632788818 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648632788818 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 8 " "Parameter \"numwords_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648632788818 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648632788818 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648632788818 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648632788818 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 3 " "Parameter \"widthad_a\" = \"3\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648632788818 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648632788818 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648632788818 ""} } { { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648632788818 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_ro91.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_ro91.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_ro91 " "Found entity 1: altsyncram_ro91" { } { { "db/altsyncram_ro91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_ro91.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648632788865 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648632788865 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_ro91 rom0:rom\|altsyncram:altsyncram_component\|altsyncram_ro91:auto_generated " "Elaborating entity \"altsyncram_ro91\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_ro91:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648632788865 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1648632789369 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1648632789571 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648632789571 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "48 " "Implemented 48 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Implemented 1 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1648632789615 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1648632789615 ""} { "Info" "ICUT_CUT_TM_LCELLS" "31 " "Implemented 31 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1648632789615 ""} { "Info" "ICUT_CUT_TM_RAMS" "8 " "Implemented 8 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Quartus II" 0 -1 1648632789615 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1648632789615 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "391 " "Peak virtual memory: 391 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648632789622 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 12:33:09 2022 " "Processing ended: Wed Mar 30 12:33:09 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648632789622 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648632789622 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648632789622 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648632789622 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648632790943 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648632790943 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 12:33:10 2022 " "Processing started: Wed Mar 30 12:33:10 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648632790943 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1648632790943 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_fit --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1648632790944 ""} +{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1648632790969 ""} +{ "Info" "0" "" "Project = spectrum" { } { } 0 0 "Project = spectrum" 0 0 "Fitter" 0 0 1648632790970 ""} +{ "Info" "0" "" "Revision = spectrum" { } { } 0 0 "Revision = spectrum" 0 0 "Fitter" 0 0 1648632790970 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1648632791017 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "spectrum EP4CE22F17C6 " "Selected device EP4CE22F17C6 for design \"spectrum\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1648632791021 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648632791062 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648632791063 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648632791063 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1648632791140 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1648632791151 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17C6 " "Device EP4CE10F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648632791355 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C6 " "Device EP4CE6F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648632791355 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C6 " "Device EP4CE15F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648632791355 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1648632791355 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 330 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648632791360 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 332 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648632791360 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 334 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648632791360 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 336 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648632791360 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 338 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648632791360 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1648632791360 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1648632791362 ""} +{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1648632791363 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "spectrum.sdc " "Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1648632792037 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1648632792037 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1648632792039 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1648632792039 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1648632792040 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p)) " "Automatically promoted node CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G18 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648632792047 ""} } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 325 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648632792047 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1648632792282 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648632792282 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648632792283 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648632792283 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648632792284 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1648632792284 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1648632792284 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1648632792284 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1648632792285 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1648632792285 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1648632792285 ""} +{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS_N " "Node \"ADC_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SADDR " "Node \"ADC_SADDR\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SADDR" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCLK " "Node \"ADC_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDAT " "Node \"ADC_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_ASDO " "Node \"EPCS_ASDO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_ASDO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DATA0 " "Node \"EPCS_DATA0\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DATA0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DCLK " "Node \"EPCS_DCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_NCSO " "Node \"EPCS_NCSO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_NCSO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[0\] " "Node \"GPIO_0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[10\] " "Node \"GPIO_0\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[11\] " "Node \"GPIO_0\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[12\] " "Node \"GPIO_0\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[13\] " "Node \"GPIO_0\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[14\] " "Node \"GPIO_0\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[15\] " "Node \"GPIO_0\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[16\] " "Node \"GPIO_0\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[17\] " "Node \"GPIO_0\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[18\] " "Node \"GPIO_0\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[19\] " "Node \"GPIO_0\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[1\] " "Node \"GPIO_0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[20\] " "Node \"GPIO_0\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[21\] " "Node \"GPIO_0\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[22\] " "Node \"GPIO_0\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[23\] " "Node \"GPIO_0\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[24\] " "Node \"GPIO_0\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[25\] " "Node \"GPIO_0\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[26\] " "Node \"GPIO_0\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[27\] " "Node \"GPIO_0\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[28\] " "Node \"GPIO_0\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[29\] " "Node \"GPIO_0\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[2\] " "Node \"GPIO_0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[30\] " "Node \"GPIO_0\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[31\] " "Node \"GPIO_0\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[32\] " "Node \"GPIO_0\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[33\] " "Node \"GPIO_0\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[3\] " "Node \"GPIO_0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[4\] " "Node \"GPIO_0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[5\] " "Node \"GPIO_0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[6\] " "Node \"GPIO_0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[7\] " "Node \"GPIO_0\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[8\] " "Node \"GPIO_0\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[9\] " "Node \"GPIO_0\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[0\] " "Node \"GPIO_0_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[1\] " "Node \"GPIO_0_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[0\] " "Node \"GPIO_1\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[10\] " "Node \"GPIO_1\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[11\] " "Node \"GPIO_1\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[12\] " "Node \"GPIO_1\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[13\] " "Node \"GPIO_1\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[14\] " "Node \"GPIO_1\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[15\] " "Node \"GPIO_1\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[16\] " "Node \"GPIO_1\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[17\] " "Node \"GPIO_1\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[18\] " "Node \"GPIO_1\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[19\] " "Node \"GPIO_1\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[1\] " "Node \"GPIO_1\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[20\] " "Node \"GPIO_1\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[21\] " "Node \"GPIO_1\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[22\] " "Node \"GPIO_1\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[23\] " "Node \"GPIO_1\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[24\] " "Node \"GPIO_1\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[25\] " "Node \"GPIO_1\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[26\] " "Node \"GPIO_1\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[27\] " "Node \"GPIO_1\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[28\] " "Node \"GPIO_1\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[29\] " "Node \"GPIO_1\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[2\] " "Node \"GPIO_1\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[30\] " "Node \"GPIO_1\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[31\] " "Node \"GPIO_1\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[32\] " "Node \"GPIO_1\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[33\] " "Node \"GPIO_1\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[3\] " "Node \"GPIO_1\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[4\] " "Node \"GPIO_1\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[5\] " "Node \"GPIO_1\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[6\] " "Node \"GPIO_1\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[7\] " "Node \"GPIO_1\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[8\] " "Node \"GPIO_1\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[9\] " "Node \"GPIO_1\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[0\] " "Node \"GPIO_1_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[1\] " "Node \"GPIO_1_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[0\] " "Node \"GPIO_2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[10\] " "Node \"GPIO_2\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[11\] " "Node \"GPIO_2\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[12\] " "Node \"GPIO_2\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[1\] " "Node \"GPIO_2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[2\] " "Node \"GPIO_2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[3\] " "Node \"GPIO_2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[4\] " "Node \"GPIO_2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[5\] " "Node \"GPIO_2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[6\] " "Node \"GPIO_2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[7\] " "Node \"GPIO_2\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[8\] " "Node \"GPIO_2\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[9\] " "Node \"GPIO_2\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[0\] " "Node \"GPIO_2_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[1\] " "Node \"GPIO_2_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[2\] " "Node \"GPIO_2_IN\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_CS_N " "Node \"G_SENSOR_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_INT " "Node \"G_SENSOR_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648632792298 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1648632792298 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648632792305 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1648632793268 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648632793338 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1648632793346 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1648632793795 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648632793795 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1648632794036 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X32_Y23 X42_Y34 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X32_Y23 to location X42_Y34" { } { { "loc" "" { Generic "/home/benny/work/fpga/projects/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X32_Y23 to location X42_Y34"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X32_Y23 to location X42_Y34"} 32 23 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1648632794638 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1648632794638 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648632795024 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1648632795025 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1648632795025 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.24 " "Total time spent on timing analysis during the Fitter is 0.24 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1648632795035 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648632795087 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648632795247 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648632795292 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648632795424 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648632795700 ""} +{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1648632796044 ""} +{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "1 Cyclone IV E " "1 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK_50 3.3-V LVTTL R8 " "Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at R8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { CLOCK_50 } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 15 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648632796047 ""} } { } 0 169177 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1648632796047 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/projects/output_files/spectrum.fit.smsg " "Generated suppressed messages file /home/benny/work/fpga/projects/output_files/spectrum.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1648632796089 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 152 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 152 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "594 " "Peak virtual memory: 594 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648632796269 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 12:33:16 2022 " "Processing ended: Wed Mar 30 12:33:16 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648632796269 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648632796269 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648632796269 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1648632796269 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1648632797767 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648632797768 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 12:33:17 2022 " "Processing started: Wed Mar 30 12:33:17 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648632797768 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1648632797768 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1648632797768 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1648632798672 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1648632798698 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "390 " "Peak virtual memory: 390 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648632798946 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 12:33:18 2022 " "Processing ended: Wed Mar 30 12:33:18 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648632798946 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648632798946 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648632798946 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1648632798946 ""} +{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1648632799033 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1648632800321 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648632800322 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 12:33:20 2022 " "Processing started: Wed Mar 30 12:33:20 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648632800322 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648632800322 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta spectrum -c spectrum " "Command: quartus_sta spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648632800322 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1648632800349 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648632800451 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648632800453 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648632800497 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648632800498 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "spectrum.sdc " "Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1648632800697 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1648632800697 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648632800698 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648632800698 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1648632800824 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648632800825 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1648632800825 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1648632800830 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648632800838 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648632800838 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.756 " "Worst-case setup slack is -1.756" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632800839 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632800839 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.756 -35.786 CLOCK_50 " " -1.756 -35.786 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632800839 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648632800839 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.343 " "Worst-case hold slack is 0.343" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632800840 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632800840 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.343 0.000 CLOCK_50 " " 0.343 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632800840 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648632800840 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648632800840 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648632800841 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632800841 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632800841 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -46.624 CLOCK_50 " " -3.000 -46.624 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632800841 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648632800841 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648632800855 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1648632800878 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1648632801246 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648632801263 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648632801264 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648632801264 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.484 " "Worst-case setup slack is -1.484" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632801265 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632801265 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.484 -28.518 CLOCK_50 " " -1.484 -28.518 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632801265 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648632801265 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.298 " "Worst-case hold slack is 0.298" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632801267 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632801267 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.298 0.000 CLOCK_50 " " 0.298 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632801267 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648632801267 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648632801268 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648632801269 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632801270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632801270 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -46.624 CLOCK_50 " " -3.000 -46.624 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632801270 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648632801270 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648632801285 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648632801405 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648632801405 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648632801405 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.389 " "Worst-case setup slack is -0.389" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632801407 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632801407 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.389 -5.690 CLOCK_50 " " -0.389 -5.690 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632801407 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648632801407 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.178 " "Worst-case hold slack is 0.178" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632801409 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632801409 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.178 0.000 CLOCK_50 " " 0.178 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632801409 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648632801409 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648632801410 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648632801412 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632801413 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632801413 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -45.739 CLOCK_50 " " -3.000 -45.739 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648632801413 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648632801413 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648632801708 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648632801708 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "415 " "Peak virtual memory: 415 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648632801742 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 12:33:21 2022 " "Processing ended: Wed Mar 30 12:33:21 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648632801742 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648632801742 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648632801742 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648632801742 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648632803343 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648632803344 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 12:33:23 2022 " "Processing started: Wed Mar 30 12:33:23 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648632803344 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648632803344 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648632803345 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648632803637 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648632803657 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_fast.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_fast.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648632803678 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648632803698 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648632803719 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648632803738 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_v_fast.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648632803757 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_v.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_v.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648632803776 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "352 " "Peak virtual memory: 352 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648632803807 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 12:33:23 2022 " "Processing ended: Wed Mar 30 12:33:23 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648632803807 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648632803807 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648632803807 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648632803807 ""} +{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 160 s " "Quartus II Full Compilation was successful. 0 errors, 160 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648632803907 ""} diff --git a/db/spectrum.(0).cnf.cdb b/db/spectrum.(0).cnf.cdb index e04e75f..3f83dc8 100644 Binary files a/db/spectrum.(0).cnf.cdb and b/db/spectrum.(0).cnf.cdb differ diff --git a/db/spectrum.(0).cnf.hdb b/db/spectrum.(0).cnf.hdb index 406f67d..9e5ab7f 100644 Binary files a/db/spectrum.(0).cnf.hdb and b/db/spectrum.(0).cnf.hdb differ diff --git a/db/spectrum.(1).cnf.cdb b/db/spectrum.(1).cnf.cdb new file mode 100644 index 0000000..0fe2d99 Binary files /dev/null and b/db/spectrum.(1).cnf.cdb differ diff --git a/db/spectrum.(1).cnf.hdb b/db/spectrum.(1).cnf.hdb new file mode 100644 index 0000000..b4f72d4 Binary files /dev/null and b/db/spectrum.(1).cnf.hdb differ diff --git a/db/spectrum.(2).cnf.cdb b/db/spectrum.(2).cnf.cdb new file mode 100644 index 0000000..742f9ce Binary files /dev/null and b/db/spectrum.(2).cnf.cdb differ diff --git a/db/spectrum.(2).cnf.hdb b/db/spectrum.(2).cnf.hdb new file mode 100644 index 0000000..763a48b Binary files /dev/null and b/db/spectrum.(2).cnf.hdb differ diff --git a/db/spectrum.(3).cnf.cdb b/db/spectrum.(3).cnf.cdb new file mode 100644 index 0000000..f03f152 Binary files /dev/null and b/db/spectrum.(3).cnf.cdb differ diff --git a/db/spectrum.(3).cnf.hdb b/db/spectrum.(3).cnf.hdb new file mode 100644 index 0000000..51ad51f Binary files /dev/null and b/db/spectrum.(3).cnf.hdb differ diff --git a/db/spectrum.asm.qmsg b/db/spectrum.asm.qmsg index 3c169f1..9f4c00f 100644 --- a/db/spectrum.asm.qmsg +++ b/db/spectrum.asm.qmsg @@ -1,6 +1,6 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648630297528 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648630297529 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 11:51:37 2022 " "Processing started: Wed Mar 30 11:51:37 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648630297529 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1648630297529 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1648630297529 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1648630298448 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1648630298474 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "389 " "Peak virtual memory: 389 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648630298719 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 11:51:38 2022 " "Processing ended: Wed Mar 30 11:51:38 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648630298719 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648630298719 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648630298719 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1648630298719 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648633116429 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648633116430 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 12:38:36 2022 " "Processing started: Wed Mar 30 12:38:36 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648633116430 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1648633116430 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1648633116430 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1648633117331 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1648633117357 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "393 " "Peak virtual memory: 393 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648633117592 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 12:38:37 2022 " "Processing ended: Wed Mar 30 12:38:37 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648633117592 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648633117592 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648633117592 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1648633117592 ""} diff --git a/db/spectrum.asm.rdb b/db/spectrum.asm.rdb index ed7fadc..a2cfdbe 100644 Binary files a/db/spectrum.asm.rdb and b/db/spectrum.asm.rdb differ diff --git a/db/spectrum.asm_labs.ddb b/db/spectrum.asm_labs.ddb index 2bfdbd9..7e9aafd 100644 Binary files a/db/spectrum.asm_labs.ddb and b/db/spectrum.asm_labs.ddb differ diff --git a/db/spectrum.cbx.xml b/db/spectrum.cbx.xml index f0b154a..c2640c4 100644 --- a/db/spectrum.cbx.xml +++ b/db/spectrum.cbx.xml @@ -1,5 +1,6 @@ + diff --git a/db/spectrum.cmp.bpm b/db/spectrum.cmp.bpm index 8951462..0f55d39 100644 Binary files a/db/spectrum.cmp.bpm and b/db/spectrum.cmp.bpm differ diff --git a/db/spectrum.cmp.cdb b/db/spectrum.cmp.cdb index da743b4..b081f7f 100644 Binary files a/db/spectrum.cmp.cdb and b/db/spectrum.cmp.cdb differ diff --git a/db/spectrum.cmp.hdb b/db/spectrum.cmp.hdb index d134eae..9cf556a 100644 Binary files a/db/spectrum.cmp.hdb and b/db/spectrum.cmp.hdb differ diff --git a/db/spectrum.cmp.idb b/db/spectrum.cmp.idb index 311c6e3..fb207aa 100644 Binary files a/db/spectrum.cmp.idb and b/db/spectrum.cmp.idb differ diff --git a/db/spectrum.cmp.rdb b/db/spectrum.cmp.rdb index 3a40804..061060a 100644 Binary files a/db/spectrum.cmp.rdb and b/db/spectrum.cmp.rdb differ diff --git a/db/spectrum.cycloneive_io_sim_cache.45um_tt_1200mv_85c_slow.hsd b/db/spectrum.cycloneive_io_sim_cache.45um_tt_1200mv_85c_slow.hsd index 2005c89..7fbf94b 100644 Binary files a/db/spectrum.cycloneive_io_sim_cache.45um_tt_1200mv_85c_slow.hsd and b/db/spectrum.cycloneive_io_sim_cache.45um_tt_1200mv_85c_slow.hsd differ diff --git a/db/spectrum.eda.qmsg b/db/spectrum.eda.qmsg index 12656aa..09b95d4 100644 --- a/db/spectrum.eda.qmsg +++ b/db/spectrum.eda.qmsg @@ -1,12 +1,12 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648630303095 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648630303096 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 11:51:42 2022 " "Processing started: Wed Mar 30 11:51:42 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648630303096 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648630303096 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648630303097 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630303387 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630303407 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_fast.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_fast.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630303428 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630303448 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630303469 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630303488 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_v_fast.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630303508 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_v.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_v.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648630303527 ""} -{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "352 " "Peak virtual memory: 352 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648630303559 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 11:51:43 2022 " "Processing ended: Wed Mar 30 11:51:43 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648630303559 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648630303559 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648630303559 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648630303559 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648633122029 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 32-bit " "Running Quartus II 32-bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648633122030 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 12:38:41 2022 " "Processing started: Wed Mar 30 12:38:41 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648633122030 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648633122030 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648633122031 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648633122334 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_slow.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_slow.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648633122355 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_fast.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_fast.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648633122376 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum.vo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum.vo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648633122396 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_85c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_85c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648633122418 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_6_1200mv_0c_v_slow.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648633122437 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_min_1200mv_0c_v_fast.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648633122456 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spectrum_v.sdo /home/benny/work/fpga/projects/simulation/modelsim/ simulation " "Generated file spectrum_v.sdo in folder \"/home/benny/work/fpga/projects/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1648633122475 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "344 " "Peak virtual memory: 344 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648633122507 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 12:38:42 2022 " "Processing ended: Wed Mar 30 12:38:42 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648633122507 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648633122507 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648633122507 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648633122507 ""} diff --git a/db/spectrum.fit.qmsg b/db/spectrum.fit.qmsg index b0460ba..b2d009d 100644 --- a/db/spectrum.fit.qmsg +++ b/db/spectrum.fit.qmsg @@ -1,47 +1,48 @@ -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1648630290922 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "spectrum EP4CE22F17C6 " "Selected device EP4CE22F17C6 for design \"spectrum\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1648630290925 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648630290962 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648630290963 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648630290963 ""} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1648630291034 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1648630291044 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17C6 " "Device EP4CE10F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648630291251 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C6 " "Device EP4CE6F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648630291251 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C6 " "Device EP4CE15F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648630291251 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1648630291251 ""} -{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 275 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648630291256 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 277 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648630291256 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 279 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648630291256 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 281 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648630291256 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 283 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648630291256 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1648630291256 ""} -{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1648630291258 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "spectrum.sdc " "Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1648630291909 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1648630291909 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1648630291911 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1648630291912 ""} -{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1648630291912 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p)) " "Automatically promoted node CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G18 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648630291919 ""} } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 270 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648630291919 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1648630292153 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648630292154 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648630292154 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648630292155 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648630292155 ""} -{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1648630292156 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1648630292156 ""} -{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1648630292156 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1648630292167 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1648630292168 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1648630292168 ""} -{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS_N " "Node \"ADC_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SADDR " "Node \"ADC_SADDR\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SADDR" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCLK " "Node \"ADC_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDAT " "Node \"ADC_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_ASDO " "Node \"EPCS_ASDO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_ASDO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DATA0 " "Node \"EPCS_DATA0\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DATA0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DCLK " "Node \"EPCS_DCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_NCSO " "Node \"EPCS_NCSO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_NCSO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[0\] " "Node \"GPIO_0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[10\] " "Node \"GPIO_0\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[11\] " "Node \"GPIO_0\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[12\] " "Node \"GPIO_0\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[13\] " "Node \"GPIO_0\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[14\] " "Node \"GPIO_0\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[15\] " "Node \"GPIO_0\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[16\] " "Node \"GPIO_0\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[17\] " "Node \"GPIO_0\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[18\] " "Node \"GPIO_0\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[19\] " "Node \"GPIO_0\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[1\] " "Node \"GPIO_0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[20\] " "Node \"GPIO_0\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[21\] " "Node \"GPIO_0\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[22\] " "Node \"GPIO_0\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[23\] " "Node \"GPIO_0\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[24\] " "Node \"GPIO_0\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[25\] " "Node \"GPIO_0\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[26\] " "Node \"GPIO_0\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[27\] " "Node \"GPIO_0\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[28\] " "Node \"GPIO_0\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[29\] " "Node \"GPIO_0\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[2\] " "Node \"GPIO_0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[30\] " "Node \"GPIO_0\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[31\] " "Node \"GPIO_0\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[32\] " "Node \"GPIO_0\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[33\] " "Node \"GPIO_0\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[3\] " "Node \"GPIO_0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[4\] " "Node \"GPIO_0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[5\] " "Node \"GPIO_0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[6\] " "Node \"GPIO_0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[7\] " "Node \"GPIO_0\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[8\] " "Node \"GPIO_0\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[9\] " "Node \"GPIO_0\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[0\] " "Node \"GPIO_0_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[1\] " "Node \"GPIO_0_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[0\] " "Node \"GPIO_1\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[10\] " "Node \"GPIO_1\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[11\] " "Node \"GPIO_1\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[12\] " "Node \"GPIO_1\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[13\] " "Node \"GPIO_1\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[14\] " "Node \"GPIO_1\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[15\] " "Node \"GPIO_1\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[16\] " "Node \"GPIO_1\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[17\] " "Node \"GPIO_1\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[18\] " "Node \"GPIO_1\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[19\] " "Node \"GPIO_1\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[1\] " "Node \"GPIO_1\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[20\] " "Node \"GPIO_1\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[21\] " "Node \"GPIO_1\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[22\] " "Node \"GPIO_1\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[23\] " "Node \"GPIO_1\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[24\] " "Node \"GPIO_1\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[25\] " "Node \"GPIO_1\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[26\] " "Node \"GPIO_1\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[27\] " "Node \"GPIO_1\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[28\] " "Node \"GPIO_1\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[29\] " "Node \"GPIO_1\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[2\] " "Node \"GPIO_1\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[30\] " "Node \"GPIO_1\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[31\] " "Node \"GPIO_1\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[32\] " "Node \"GPIO_1\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[33\] " "Node \"GPIO_1\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[3\] " "Node \"GPIO_1\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[4\] " "Node \"GPIO_1\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[5\] " "Node \"GPIO_1\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[6\] " "Node \"GPIO_1\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[7\] " "Node \"GPIO_1\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[8\] " "Node \"GPIO_1\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[9\] " "Node \"GPIO_1\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[0\] " "Node \"GPIO_1_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[1\] " "Node \"GPIO_1_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[0\] " "Node \"GPIO_2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[10\] " "Node \"GPIO_2\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[11\] " "Node \"GPIO_2\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[12\] " "Node \"GPIO_2\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[1\] " "Node \"GPIO_2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[2\] " "Node \"GPIO_2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[3\] " "Node \"GPIO_2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[4\] " "Node \"GPIO_2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[5\] " "Node \"GPIO_2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[6\] " "Node \"GPIO_2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[7\] " "Node \"GPIO_2\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[8\] " "Node \"GPIO_2\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[9\] " "Node \"GPIO_2\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[0\] " "Node \"GPIO_2_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[1\] " "Node \"GPIO_2_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[2\] " "Node \"GPIO_2_IN\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_CS_N " "Node \"G_SENSOR_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_INT " "Node \"G_SENSOR_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648630292180 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1648630292180 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648630292187 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1648630293162 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648630293228 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1648630293236 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1648630293659 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648630293659 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1648630293897 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X32_Y23 X42_Y34 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X32_Y23 to location X42_Y34" { } { { "loc" "" { Generic "/home/benny/work/fpga/projects/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X32_Y23 to location X42_Y34"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X32_Y23 to location X42_Y34"} 32 23 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1648630294466 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1648630294466 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648630294824 ""} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1648630294824 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1648630294824 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.10 " "Total time spent on timing analysis during the Fitter is 0.10 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1648630294833 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648630294885 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648630295042 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648630295087 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648630295217 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648630295493 ""} -{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1648630295838 ""} -{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "1 Cyclone IV E " "1 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK_50 3.3-V LVTTL R8 " "Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at R8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { CLOCK_50 } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 12 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648630295841 ""} } { } 0 169177 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1648630295841 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/projects/output_files/spectrum.fit.smsg " "Generated suppressed messages file /home/benny/work/fpga/projects/output_files/spectrum.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1648630295883 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 152 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 152 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "588 " "Peak virtual memory: 588 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648630296061 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 11:51:36 2022 " "Processing ended: Wed Mar 30 11:51:36 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648630296061 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648630296061 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648630296061 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1648630296061 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1648633109609 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "spectrum EP4CE22F17C6 " "Selected device EP4CE22F17C6 for design \"spectrum\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1648633109613 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648633109651 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648633109652 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1648633109652 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1648633109724 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1648633109735 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17C6 " "Device EP4CE10F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648633109936 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C6 " "Device EP4CE6F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648633109936 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C6 " "Device EP4CE15F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1648633109936 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1648633109936 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 334 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648633109941 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 336 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648633109941 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 338 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648633109941 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 340 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648633109941 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 342 9662 10382 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1648633109941 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1648633109941 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1648633109942 ""} +{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1648633109944 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "spectrum.sdc " "Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1648633110614 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1648633110615 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1648633110617 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1648633110617 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1648633110617 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p)) " "Automatically promoted node CLOCK_50~input (placed in PIN R8 (CLK15, DIFFCLK_6p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G18 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1648633110629 ""} } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 329 9662 10382 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1648633110629 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1648633110867 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648633110868 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1648633110868 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648633110869 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1648633110869 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1648633110869 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1648633110869 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1648633110870 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1648633110870 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1648633110870 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1648633110870 ""} +{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS_N " "Node \"ADC_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SADDR " "Node \"ADC_SADDR\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SADDR" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCLK " "Node \"ADC_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDAT " "Node \"ADC_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "ADC_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_ASDO " "Node \"EPCS_ASDO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_ASDO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DATA0 " "Node \"EPCS_DATA0\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DATA0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_DCLK " "Node \"EPCS_DCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_DCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EPCS_NCSO " "Node \"EPCS_NCSO\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "EPCS_NCSO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[0\] " "Node \"GPIO_0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[10\] " "Node \"GPIO_0\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[11\] " "Node \"GPIO_0\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[12\] " "Node \"GPIO_0\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[13\] " "Node \"GPIO_0\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[14\] " "Node \"GPIO_0\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[15\] " "Node \"GPIO_0\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[16\] " "Node \"GPIO_0\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[17\] " "Node \"GPIO_0\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[18\] " "Node \"GPIO_0\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[19\] " "Node \"GPIO_0\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[1\] " "Node \"GPIO_0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[20\] " "Node \"GPIO_0\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[21\] " "Node \"GPIO_0\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[22\] " "Node \"GPIO_0\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[23\] " "Node \"GPIO_0\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[24\] " "Node \"GPIO_0\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[25\] " "Node \"GPIO_0\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[26\] " "Node \"GPIO_0\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[27\] " "Node \"GPIO_0\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[28\] " "Node \"GPIO_0\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[29\] " "Node \"GPIO_0\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[2\] " "Node \"GPIO_0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[30\] " "Node \"GPIO_0\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[31\] " "Node \"GPIO_0\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[32\] " "Node \"GPIO_0\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[33\] " "Node \"GPIO_0\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[3\] " "Node \"GPIO_0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[4\] " "Node \"GPIO_0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[5\] " "Node \"GPIO_0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[6\] " "Node \"GPIO_0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[7\] " "Node \"GPIO_0\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[8\] " "Node \"GPIO_0\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[9\] " "Node \"GPIO_0\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[0\] " "Node \"GPIO_0_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[1\] " "Node \"GPIO_0_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[0\] " "Node \"GPIO_1\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[10\] " "Node \"GPIO_1\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[11\] " "Node \"GPIO_1\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[12\] " "Node \"GPIO_1\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[13\] " "Node \"GPIO_1\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[14\] " "Node \"GPIO_1\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[15\] " "Node \"GPIO_1\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[16\] " "Node \"GPIO_1\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[17\] " "Node \"GPIO_1\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[18\] " "Node \"GPIO_1\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[19\] " "Node \"GPIO_1\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[1\] " "Node \"GPIO_1\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[20\] " "Node \"GPIO_1\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[21\] " "Node \"GPIO_1\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[22\] " "Node \"GPIO_1\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[23\] " "Node \"GPIO_1\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[24\] " "Node \"GPIO_1\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[25\] " "Node \"GPIO_1\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[26\] " "Node \"GPIO_1\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[27\] " "Node \"GPIO_1\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[28\] " "Node \"GPIO_1\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[29\] " "Node \"GPIO_1\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[2\] " "Node \"GPIO_1\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[30\] " "Node \"GPIO_1\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[31\] " "Node \"GPIO_1\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[32\] " "Node \"GPIO_1\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[33\] " "Node \"GPIO_1\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[3\] " "Node \"GPIO_1\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[4\] " "Node \"GPIO_1\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[5\] " "Node \"GPIO_1\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[6\] " "Node \"GPIO_1\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[7\] " "Node \"GPIO_1\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[8\] " "Node \"GPIO_1\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[9\] " "Node \"GPIO_1\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[0\] " "Node \"GPIO_1_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[1\] " "Node \"GPIO_1_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[0\] " "Node \"GPIO_2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[10\] " "Node \"GPIO_2\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[11\] " "Node \"GPIO_2\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[12\] " "Node \"GPIO_2\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[1\] " "Node \"GPIO_2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[2\] " "Node \"GPIO_2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[3\] " "Node \"GPIO_2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[4\] " "Node \"GPIO_2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[5\] " "Node \"GPIO_2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[6\] " "Node \"GPIO_2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[7\] " "Node \"GPIO_2\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[8\] " "Node \"GPIO_2\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[9\] " "Node \"GPIO_2\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[0\] " "Node \"GPIO_2_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[1\] " "Node \"GPIO_2_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[2\] " "Node \"GPIO_2_IN\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_CS_N " "Node \"G_SENSOR_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_INT " "Node \"G_SENSOR_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "G_SENSOR_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[0\] " "Node \"SW\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[1\] " "Node \"SW\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[2\] " "Node \"SW\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[3\] " "Node \"SW\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1648633110884 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1648633110884 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648633110890 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1648633111853 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648633111921 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1648633111930 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1648633112388 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648633112388 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1648633112627 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X32_Y23 X42_Y34 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X32_Y23 to location X42_Y34" { } { { "loc" "" { Generic "/home/benny/work/fpga/projects/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X32_Y23 to location X42_Y34"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X32_Y23 to location X42_Y34"} 32 23 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1648633113211 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1648633113211 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648633113709 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1648633113709 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1648633113709 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.16 " "Total time spent on timing analysis during the Fitter is 0.16 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1648633113719 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648633113772 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648633113931 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1648633113976 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1648633114109 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1648633114385 ""} +{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1648633114735 ""} +{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "1 Cyclone IV E " "1 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK_50 3.3-V LVTTL R8 " "Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at R8" { } { { "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" "" { PinPlanner "/home/benny/altera/13.1/quartus/linux/pin_planner.ppl" { CLOCK_50 } } } { "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" "" { Assignment "/home/benny/altera/13.1/quartus/linux/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 2 0 0 } } { "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/home/benny/altera/13.1/quartus/linux/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "/home/benny/work/fpga/projects/" { { 0 { 0 ""} 0 15 9662 10382 0} } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1648633114738 ""} } { } 0 169177 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1648633114738 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/benny/work/fpga/projects/output_files/spectrum.fit.smsg " "Generated suppressed messages file /home/benny/work/fpga/projects/output_files/spectrum.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1648633114780 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 152 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 152 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "600 " "Peak virtual memory: 600 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648633114959 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 12:38:34 2022 " "Processing ended: Wed Mar 30 12:38:34 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648633114959 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648633114959 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648633114959 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1648633114959 ""} diff --git a/db/spectrum.hier_info b/db/spectrum.hier_info index f3679a9..8eef65f 100644 --- a/db/spectrum.hier_info +++ b/db/spectrum.hier_info @@ -1,47 +1,114 @@ |spectrum -CLOCK_50 => LED[0]~reg0.CLK -CLOCK_50 => LED[1]~reg0.CLK -CLOCK_50 => LED[2]~reg0.CLK -CLOCK_50 => LED[3]~reg0.CLK -CLOCK_50 => LED[4]~reg0.CLK -CLOCK_50 => LED[5]~reg0.CLK -CLOCK_50 => LED[6]~reg0.CLK -CLOCK_50 => LED[7]~reg0.CLK -CLOCK_50 => counter[0].CLK -CLOCK_50 => counter[1].CLK -CLOCK_50 => counter[2].CLK -CLOCK_50 => counter[3].CLK -CLOCK_50 => counter[4].CLK -CLOCK_50 => counter[5].CLK -CLOCK_50 => counter[6].CLK -CLOCK_50 => counter[7].CLK -CLOCK_50 => counter[8].CLK -CLOCK_50 => counter[9].CLK -CLOCK_50 => counter[10].CLK -CLOCK_50 => counter[11].CLK -CLOCK_50 => counter[12].CLK -CLOCK_50 => counter[13].CLK -CLOCK_50 => counter[14].CLK -CLOCK_50 => counter[15].CLK -CLOCK_50 => counter[16].CLK -CLOCK_50 => counter[17].CLK -CLOCK_50 => counter[18].CLK -CLOCK_50 => counter[19].CLK -CLOCK_50 => counter[20].CLK -CLOCK_50 => counter[21].CLK -CLOCK_50 => counter[22].CLK -CLOCK_50 => counter[23].CLK -CLOCK_50 => counter[24].CLK -CLOCK_50 => counter[25].CLK -CLOCK_50 => counter[26].CLK -CLOCK_50 => counter[27].CLK -LED[0] <= LED[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -LED[1] <= LED[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -LED[2] <= LED[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE -LED[3] <= LED[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE -LED[4] <= LED[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE -LED[5] <= LED[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE -LED[6] <= LED[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE -LED[7] <= LED[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +CLOCK_50 => CLOCK_50.IN1 +LED[0] <= rom0:rom.q +LED[1] <= rom0:rom.q +LED[2] <= rom0:rom.q +LED[3] <= rom0:rom.q +LED[4] <= rom0:rom.q +LED[5] <= rom0:rom.q +LED[6] <= rom0:rom.q +LED[7] <= rom0:rom.q + + +|spectrum|rom0:rom +address[0] => address[0].IN1 +address[1] => address[1].IN1 +address[2] => address[2].IN1 +clock => clock.IN1 +q[0] <= altsyncram:altsyncram_component.q_a +q[1] <= altsyncram:altsyncram_component.q_a +q[2] <= altsyncram:altsyncram_component.q_a +q[3] <= altsyncram:altsyncram_component.q_a +q[4] <= altsyncram:altsyncram_component.q_a +q[5] <= altsyncram:altsyncram_component.q_a +q[6] <= altsyncram:altsyncram_component.q_a +q[7] <= altsyncram:altsyncram_component.q_a + + +|spectrum|rom0:rom|altsyncram:altsyncram_component +wren_a => ~NO_FANOUT~ +rden_a => ~NO_FANOUT~ +wren_b => ~NO_FANOUT~ +rden_b => ~NO_FANOUT~ +data_a[0] => ~NO_FANOUT~ +data_a[1] => ~NO_FANOUT~ +data_a[2] => ~NO_FANOUT~ +data_a[3] => ~NO_FANOUT~ +data_a[4] => ~NO_FANOUT~ +data_a[5] => ~NO_FANOUT~ +data_a[6] => ~NO_FANOUT~ +data_a[7] => ~NO_FANOUT~ +data_b[0] => ~NO_FANOUT~ +address_a[0] => altsyncram_ro91:auto_generated.address_a[0] +address_a[1] => altsyncram_ro91:auto_generated.address_a[1] +address_a[2] => altsyncram_ro91:auto_generated.address_a[2] +address_b[0] => ~NO_FANOUT~ +addressstall_a => ~NO_FANOUT~ +addressstall_b => ~NO_FANOUT~ +clock0 => altsyncram_ro91:auto_generated.clock0 +clock1 => ~NO_FANOUT~ +clocken0 => ~NO_FANOUT~ +clocken1 => ~NO_FANOUT~ +clocken2 => ~NO_FANOUT~ +clocken3 => ~NO_FANOUT~ +aclr0 => ~NO_FANOUT~ +aclr1 => ~NO_FANOUT~ +byteena_a[0] => ~NO_FANOUT~ +byteena_b[0] => ~NO_FANOUT~ +q_a[0] <= altsyncram_ro91:auto_generated.q_a[0] +q_a[1] <= altsyncram_ro91:auto_generated.q_a[1] +q_a[2] <= altsyncram_ro91:auto_generated.q_a[2] +q_a[3] <= altsyncram_ro91:auto_generated.q_a[3] +q_a[4] <= altsyncram_ro91:auto_generated.q_a[4] +q_a[5] <= altsyncram_ro91:auto_generated.q_a[5] +q_a[6] <= altsyncram_ro91:auto_generated.q_a[6] +q_a[7] <= altsyncram_ro91:auto_generated.q_a[7] +q_b[0] <= +eccstatus[0] <= +eccstatus[1] <= +eccstatus[2] <= + + +|spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated +address_a[0] => ram_block1a0.PORTAADDR +address_a[0] => ram_block1a1.PORTAADDR +address_a[0] => ram_block1a2.PORTAADDR +address_a[0] => ram_block1a3.PORTAADDR +address_a[0] => ram_block1a4.PORTAADDR +address_a[0] => ram_block1a5.PORTAADDR +address_a[0] => ram_block1a6.PORTAADDR +address_a[0] => ram_block1a7.PORTAADDR +address_a[1] => ram_block1a0.PORTAADDR1 +address_a[1] => ram_block1a1.PORTAADDR1 +address_a[1] => ram_block1a2.PORTAADDR1 +address_a[1] => ram_block1a3.PORTAADDR1 +address_a[1] => ram_block1a4.PORTAADDR1 +address_a[1] => ram_block1a5.PORTAADDR1 +address_a[1] => ram_block1a6.PORTAADDR1 +address_a[1] => ram_block1a7.PORTAADDR1 +address_a[2] => ram_block1a0.PORTAADDR2 +address_a[2] => ram_block1a1.PORTAADDR2 +address_a[2] => ram_block1a2.PORTAADDR2 +address_a[2] => ram_block1a3.PORTAADDR2 +address_a[2] => ram_block1a4.PORTAADDR2 +address_a[2] => ram_block1a5.PORTAADDR2 +address_a[2] => ram_block1a6.PORTAADDR2 +address_a[2] => ram_block1a7.PORTAADDR2 +clock0 => ram_block1a0.CLK0 +clock0 => ram_block1a1.CLK0 +clock0 => ram_block1a2.CLK0 +clock0 => ram_block1a3.CLK0 +clock0 => ram_block1a4.CLK0 +clock0 => ram_block1a5.CLK0 +clock0 => ram_block1a6.CLK0 +clock0 => ram_block1a7.CLK0 +q_a[0] <= ram_block1a0.PORTADATAOUT +q_a[1] <= ram_block1a1.PORTADATAOUT +q_a[2] <= ram_block1a2.PORTADATAOUT +q_a[3] <= ram_block1a3.PORTADATAOUT +q_a[4] <= ram_block1a4.PORTADATAOUT +q_a[5] <= ram_block1a5.PORTADATAOUT +q_a[6] <= ram_block1a6.PORTADATAOUT +q_a[7] <= ram_block1a7.PORTADATAOUT diff --git a/db/spectrum.hif b/db/spectrum.hif index 6fdc03c..0eb8925 100644 Binary files a/db/spectrum.hif and b/db/spectrum.hif differ diff --git a/db/spectrum.ipinfo b/db/spectrum.ipinfo index b19e3be..294d6a6 100644 Binary files a/db/spectrum.ipinfo and b/db/spectrum.ipinfo differ diff --git a/db/spectrum.lpc.html b/db/spectrum.lpc.html index fbc5ab5..64d61ed 100644 --- a/db/spectrum.lpc.html +++ b/db/spectrum.lpc.html @@ -15,4 +15,36 @@ Input only Bidir Output only Bidir + +rom|altsyncram_component|auto_generated +4 +0 +0 +0 +8 +0 +0 +0 +0 +0 +0 +0 +0 + + +rom +4 +0 +0 +0 +8 +0 +0 +0 +0 +0 +0 +0 +0 + diff --git a/db/spectrum.lpc.rdb b/db/spectrum.lpc.rdb index 45b47e5..7e954c4 100644 Binary files a/db/spectrum.lpc.rdb and b/db/spectrum.lpc.rdb differ diff --git a/db/spectrum.lpc.txt b/db/spectrum.lpc.txt index a8bb51f..0c0421d 100644 --- a/db/spectrum.lpc.txt +++ b/db/spectrum.lpc.txt @@ -1,5 +1,34 @@ +--------------------------------------------------------------------------------+ ; Legal Partition Candidates ; +--------------------------------------------------------------------------------+ +Hierarchy : rom|altsyncram_component|auto_generated +Input : 4 +Constant Input : 0 +Unused Input : 0 +Floating Input : 0 +Output : 8 +Constant Output : 0 +Unused Output : 0 +Floating Output : 0 +Bidir : 0 +Constant Bidir : 0 +Unused Bidir : 0 +Input only Bidir : 0 +Output only Bidir : 0 + +Hierarchy : rom +Input : 4 +Constant Input : 0 +Unused Input : 0 +Floating Input : 0 +Output : 8 +Constant Output : 0 +Unused Output : 0 +Floating Output : 0 +Bidir : 0 +Constant Bidir : 0 +Unused Bidir : 0 +Input only Bidir : 0 +Output only Bidir : 0 +--------------------------------------------------------------------------------+ diff --git a/db/spectrum.map.bpm b/db/spectrum.map.bpm index 8495e25..de551a6 100644 Binary files a/db/spectrum.map.bpm and b/db/spectrum.map.bpm differ diff --git a/db/spectrum.map.cdb b/db/spectrum.map.cdb index 3231382..1de03c9 100644 Binary files a/db/spectrum.map.cdb and b/db/spectrum.map.cdb differ diff --git a/db/spectrum.map.hdb b/db/spectrum.map.hdb index 0b7898d..43258f9 100644 Binary files a/db/spectrum.map.hdb and b/db/spectrum.map.hdb differ diff --git a/db/spectrum.map.kpt b/db/spectrum.map.kpt index d873764..d696b5c 100644 Binary files a/db/spectrum.map.kpt and b/db/spectrum.map.kpt differ diff --git a/db/spectrum.map.qmsg b/db/spectrum.map.qmsg index ddc7b33..df94b18 100644 --- a/db/spectrum.map.qmsg +++ b/db/spectrum.map.qmsg @@ -1,12 +1,19 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648630288558 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648630288559 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 11:51:28 2022 " "Processing started: Wed Mar 30 11:51:28 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648630288559 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648630288559 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum " "Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648630288559 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648630288726 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spectrum.v 1 1 " "Found 1 design units, including 1 entities, in source file spectrum.v" { { "Info" "ISGN_ENTITY_NAME" "1 spectrum " "Found entity 1: spectrum" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648630288788 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648630288788 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "spectrum " "Elaborating entity \"spectrum\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1648630288838 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 28 spectrum.v(10) " "Verilog HDL assignment warning at spectrum.v(10): truncated value with size 32 to match size of target (28)" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 10 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1648630288840 "|spectrum"} -{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[7\] GND " "Pin \"LED\[7\]\" is stuck at GND" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 8 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1648630289171 "|spectrum|LED[7]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1648630289171 ""} -{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1648630289264 ""} -{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1648630289457 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648630289457 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "44 " "Implemented 44 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Implemented 1 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1648630289496 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1648630289496 ""} { "Info" "ICUT_CUT_TM_LCELLS" "35 " "Implemented 35 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1648630289496 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1648630289496 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "388 " "Peak virtual memory: 388 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648630289503 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 11:51:29 2022 " "Processing ended: Wed Mar 30 11:51:29 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648630289503 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648630289503 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648630289503 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648630289503 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648633107075 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648633107076 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 12:38:26 2022 " "Processing started: Wed Mar 30 12:38:26 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648633107076 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648633107076 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum " "Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648633107076 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648633107239 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spectrum.v 1 1 " "Found 1 design units, including 1 entities, in source file spectrum.v" { { "Info" "ISGN_ENTITY_NAME" "1 spectrum " "Found entity 1: spectrum" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648633107303 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648633107303 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom0.v 1 1 " "Found 1 design units, including 1 entities, in source file rom0.v" { { "Info" "ISGN_ENTITY_NAME" "1 rom0 " "Found entity 1: rom0" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648633107306 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648633107306 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "spectrum " "Elaborating entity \"spectrum\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1648633107357 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 21 spectrum.v(19) " "Verilog HDL assignment warning at spectrum.v(19): truncated value with size 32 to match size of target (21)" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 19 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1648633107359 "|spectrum"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 spectrum.v(21) " "Verilog HDL assignment warning at spectrum.v(21): truncated value with size 32 to match size of target (3)" { } { { "spectrum.v" "" { Text "/home/benny/work/fpga/projects/spectrum.v" 21 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1648633107359 "|spectrum"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom0 rom0:rom " "Elaborating entity \"rom0\" for hierarchy \"rom0:rom\"" { } { { "spectrum.v" "rom" { Text "/home/benny/work/fpga/projects/spectrum.v" 14 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107369 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram rom0:rom\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "altsyncram_component" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107416 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "rom0:rom\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"rom0:rom\|altsyncram:altsyncram_component\"" { } { { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "rom0:rom\|altsyncram:altsyncram_component " "Instantiated megafunction \"rom0:rom\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file led_patterns.mif " "Parameter \"init_file\" = \"led_patterns.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 8 " "Parameter \"numwords_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 3 " "Parameter \"widthad_a\" = \"3\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Parameter \"width_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107417 ""} } { { "rom0.v" "" { Text "/home/benny/work/fpga/projects/rom0.v" 81 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1648633107417 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_ro91.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_ro91.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_ro91 " "Found entity 1: altsyncram_ro91" { } { { "db/altsyncram_ro91.tdf" "" { Text "/home/benny/work/fpga/projects/db/altsyncram_ro91.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1648633107463 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1648633107463 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_ro91 rom0:rom\|altsyncram:altsyncram_component\|altsyncram_ro91:auto_generated " "Elaborating entity \"altsyncram_ro91\" for hierarchy \"rom0:rom\|altsyncram:altsyncram_component\|altsyncram_ro91:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "/home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1648633107464 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1648633107974 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1648633108175 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1648633108175 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "71 " "Implemented 71 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Implemented 1 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1648633108217 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1648633108217 ""} { "Info" "ICUT_CUT_TM_LCELLS" "54 " "Implemented 54 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1648633108217 ""} { "Info" "ICUT_CUT_TM_RAMS" "8 " "Implemented 8 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Quartus II" 0 -1 1648633108217 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1648633108217 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "384 " "Peak virtual memory: 384 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648633108224 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 12:38:28 2022 " "Processing ended: Wed Mar 30 12:38:28 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648633108224 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648633108224 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648633108224 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648633108224 ""} diff --git a/db/spectrum.map.rdb b/db/spectrum.map.rdb index 3765484..af645e1 100644 Binary files a/db/spectrum.map.rdb and b/db/spectrum.map.rdb differ diff --git a/db/spectrum.map_bb.cdb b/db/spectrum.map_bb.cdb index 16a177a..62e3482 100644 Binary files a/db/spectrum.map_bb.cdb and b/db/spectrum.map_bb.cdb differ diff --git a/db/spectrum.map_bb.hdb b/db/spectrum.map_bb.hdb index 0af104d..2c52639 100644 Binary files a/db/spectrum.map_bb.hdb and b/db/spectrum.map_bb.hdb differ diff --git a/db/spectrum.pre_map.hdb b/db/spectrum.pre_map.hdb index 2eee234..f253d5f 100644 Binary files a/db/spectrum.pre_map.hdb and b/db/spectrum.pre_map.hdb differ diff --git a/db/spectrum.qns b/db/spectrum.qns new file mode 100644 index 0000000..baa2e3e --- /dev/null +++ b/db/spectrum.qns @@ -0,0 +1 @@ +spectrum/done diff --git a/db/spectrum.root_partition.map.reg_db.cdb b/db/spectrum.root_partition.map.reg_db.cdb index 8cd8fb1..d836860 100644 Binary files a/db/spectrum.root_partition.map.reg_db.cdb and b/db/spectrum.root_partition.map.reg_db.cdb differ diff --git a/db/spectrum.routing.rdb b/db/spectrum.routing.rdb index 1b0ac4f..94d9041 100644 Binary files a/db/spectrum.routing.rdb and b/db/spectrum.routing.rdb differ diff --git a/db/spectrum.rtlv.hdb b/db/spectrum.rtlv.hdb index 46b0924..d4688ac 100644 Binary files a/db/spectrum.rtlv.hdb and b/db/spectrum.rtlv.hdb differ diff --git a/db/spectrum.rtlv_sg.cdb b/db/spectrum.rtlv_sg.cdb index bf8d2f6..722a8c8 100644 Binary files a/db/spectrum.rtlv_sg.cdb and b/db/spectrum.rtlv_sg.cdb differ diff --git a/db/spectrum.rtlv_sg_swap.cdb b/db/spectrum.rtlv_sg_swap.cdb index c08142b..3e6cc42 100644 Binary files a/db/spectrum.rtlv_sg_swap.cdb and b/db/spectrum.rtlv_sg_swap.cdb differ diff --git a/db/spectrum.sgdiff.cdb b/db/spectrum.sgdiff.cdb index 484ea9a..b821413 100644 Binary files a/db/spectrum.sgdiff.cdb and b/db/spectrum.sgdiff.cdb differ diff --git a/db/spectrum.sgdiff.hdb b/db/spectrum.sgdiff.hdb index 2087b36..82753ed 100644 Binary files a/db/spectrum.sgdiff.hdb and b/db/spectrum.sgdiff.hdb differ diff --git a/db/spectrum.sta.qmsg b/db/spectrum.sta.qmsg index a39d09c..36eb91b 100644 --- a/db/spectrum.sta.qmsg +++ b/db/spectrum.sta.qmsg @@ -1,42 +1,42 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648630300061 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300062 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 11:51:39 2022 " "Processing started: Wed Mar 30 11:51:39 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648630300062 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648630300062 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta spectrum -c spectrum " "Command: quartus_sta spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648630300062 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1648630300090 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648630300188 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648630300189 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648630300231 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648630300231 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "spectrum.sdc " "Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1648630300423 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1648630300423 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300424 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300424 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1648630300550 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300550 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1648630300551 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1648630300556 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648630300564 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648630300564 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.606 " "Worst-case setup slack is -1.606" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300565 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300565 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.606 -30.234 CLOCK_50 " " -1.606 -30.234 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300565 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630300565 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.360 " "Worst-case hold slack is 0.360" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300566 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300566 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.360 0.000 CLOCK_50 " " 0.360 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300566 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630300566 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648630300566 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648630300567 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300567 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300567 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -38.000 CLOCK_50 " " -3.000 -38.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300567 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630300567 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648630300582 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1648630300605 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1648630300970 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300986 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648630300988 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648630300988 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.275 " "Worst-case setup slack is -1.275" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300989 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300989 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.275 -22.690 CLOCK_50 " " -1.275 -22.690 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300989 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630300989 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.319 " "Worst-case hold slack is 0.319" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300990 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300990 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.319 0.000 CLOCK_50 " " 0.319 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300990 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630300990 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648630300991 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648630300992 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300993 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300993 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -38.000 CLOCK_50 " " -3.000 -38.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630300993 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630300993 ""} -{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648630301008 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648630301128 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648630301129 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648630301129 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.500 " "Worst-case setup slack is -0.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630301130 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630301130 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.500 -4.764 CLOCK_50 " " -0.500 -4.764 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630301130 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630301130 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.193 " "Worst-case hold slack is 0.193" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630301132 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630301132 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.193 0.000 CLOCK_50 " " 0.193 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630301132 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630301132 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648630301133 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648630301135 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630301136 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630301136 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -48.277 CLOCK_50 " " -3.000 -48.277 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648630301136 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648630301136 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648630301431 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648630301431 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "412 " "Peak virtual memory: 412 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648630301464 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 11:51:41 2022 " "Processing ended: Wed Mar 30 11:51:41 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648630301464 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648630301464 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648630301464 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648630301464 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1648633118951 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition " "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1648633118952 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 30 12:38:38 2022 " "Processing started: Wed Mar 30 12:38:38 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1648633118952 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1648633118952 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta spectrum -c spectrum " "Command: quartus_sta spectrum -c spectrum" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1648633118952 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1648633118980 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1648633119080 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648633119082 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648633119126 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1648633119126 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "spectrum.sdc " "Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1648633119323 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1648633119324 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119325 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119325 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1648633119451 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119452 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1648633119452 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1648633119457 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648633119465 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648633119465 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.763 " "Worst-case setup slack is -2.763" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119466 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119466 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.763 -43.394 CLOCK_50 " " -2.763 -43.394 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119466 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648633119466 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.343 " "Worst-case hold slack is 0.343" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119466 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119466 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.343 0.000 CLOCK_50 " " 0.343 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119466 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648633119466 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648633119467 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648633119468 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119468 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119468 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -46.633 CLOCK_50 " " -3.000 -46.633 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119468 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648633119468 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648633119483 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1648633119506 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1648633119876 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119892 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648633119894 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648633119894 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.331 " "Worst-case setup slack is -2.331" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119895 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119895 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.331 -34.994 CLOCK_50 " " -2.331 -34.994 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119895 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648633119895 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.299 " "Worst-case hold slack is 0.299" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119896 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119896 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.299 0.000 CLOCK_50 " " 0.299 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119896 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648633119896 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648633119897 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648633119898 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119899 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119899 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -46.624 CLOCK_50 " " -3.000 -46.624 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633119899 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648633119899 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1648633119916 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Quartus II" 0 -1 1648633120038 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1648633120038 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1648633120038 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.122 " "Worst-case setup slack is -1.122" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633120040 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633120040 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.122 -9.363 CLOCK_50 " " -1.122 -9.363 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633120040 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648633120040 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.178 " "Worst-case hold slack is 0.178" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633120043 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633120043 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.178 0.000 CLOCK_50 " " 0.178 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633120043 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648633120043 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648633120045 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1648633120047 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633120049 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633120049 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -45.480 CLOCK_50 " " -3.000 -45.480 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1648633120049 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1648633120049 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648633120349 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1648633120349 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "415 " "Peak virtual memory: 415 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1648633120383 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 30 12:38:40 2022 " "Processing ended: Wed Mar 30 12:38:40 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1648633120383 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1648633120383 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1648633120383 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1648633120383 ""} diff --git a/db/spectrum.sta.rdb b/db/spectrum.sta.rdb index c0e5c15..85eafb1 100644 Binary files a/db/spectrum.sta.rdb and b/db/spectrum.sta.rdb differ diff --git a/db/spectrum.sta_cmp.6_slow_1200mv_85c.tdb b/db/spectrum.sta_cmp.6_slow_1200mv_85c.tdb index 274da40..a411007 100644 Binary files a/db/spectrum.sta_cmp.6_slow_1200mv_85c.tdb and b/db/spectrum.sta_cmp.6_slow_1200mv_85c.tdb differ diff --git a/db/spectrum.tiscmp.fast_1200mv_0c.ddb b/db/spectrum.tiscmp.fast_1200mv_0c.ddb index e0b01cf..9c4bf0a 100644 Binary files a/db/spectrum.tiscmp.fast_1200mv_0c.ddb and b/db/spectrum.tiscmp.fast_1200mv_0c.ddb differ diff --git a/db/spectrum.tiscmp.slow_1200mv_0c.ddb b/db/spectrum.tiscmp.slow_1200mv_0c.ddb index f2ac133..d7eb207 100644 Binary files a/db/spectrum.tiscmp.slow_1200mv_0c.ddb and b/db/spectrum.tiscmp.slow_1200mv_0c.ddb differ diff --git a/db/spectrum.tiscmp.slow_1200mv_85c.ddb b/db/spectrum.tiscmp.slow_1200mv_85c.ddb index 503df29..3035867 100644 Binary files a/db/spectrum.tiscmp.slow_1200mv_85c.ddb and b/db/spectrum.tiscmp.slow_1200mv_85c.ddb differ diff --git a/db/spectrum.vpr.ammdb b/db/spectrum.vpr.ammdb index fefbc11..06d6bfa 100644 Binary files a/db/spectrum.vpr.ammdb and b/db/spectrum.vpr.ammdb differ diff --git a/greybox_tmp/cbx_args.txt b/greybox_tmp/cbx_args.txt new file mode 100644 index 0000000..d4ad6e2 --- /dev/null +++ b/greybox_tmp/cbx_args.txt @@ -0,0 +1,16 @@ +ADDRESS_ACLR_A=NONE +CLOCK_ENABLE_INPUT_A=BYPASS +CLOCK_ENABLE_OUTPUT_A=BYPASS +INIT_FILE=led_patterns.mif +INTENDED_DEVICE_FAMILY="Cyclone IV E" +NUMWORDS_A=8 +OPERATION_MODE=ROM +OUTDATA_ACLR_A=NONE +OUTDATA_REG_A=CLOCK0 +WIDTHAD_A=3 +WIDTH_A=8 +WIDTH_BYTEENA_A=1 +DEVICE_FAMILY="Cyclone IV E" +address_a +clock0 +q_a diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.ammdb b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.ammdb index 9f99b48..36f0f06 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.ammdb and b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.ammdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.cdb b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.cdb index 68bf3f2..b673015 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.cdb and b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.cdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.hdb b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.hdb index 4ff4db2..49e2853 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.hdb and b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.hdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.rcfdb b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.rcfdb index afab8d8..9c58c40 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.cmp.rcfdb and b/incremental_db/compiled_partitions/spectrum.root_partition.cmp.rcfdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.cdb b/incremental_db/compiled_partitions/spectrum.root_partition.map.cdb index 737e0b1..e14e8a3 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.map.cdb and b/incremental_db/compiled_partitions/spectrum.root_partition.map.cdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.dpi b/incremental_db/compiled_partitions/spectrum.root_partition.map.dpi index 66bdb56..2703abc 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.map.dpi and b/incremental_db/compiled_partitions/spectrum.root_partition.map.dpi differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.cdb b/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.cdb index cde2795..ecf5e6e 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.cdb and b/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.cdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hdb b/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hdb index 1a2c528..f3a40d7 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hdb and b/incremental_db/compiled_partitions/spectrum.root_partition.map.hbdb.hdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.hdb b/incremental_db/compiled_partitions/spectrum.root_partition.map.hdb index 6be872a..73492e1 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.map.hdb and b/incremental_db/compiled_partitions/spectrum.root_partition.map.hdb differ diff --git a/incremental_db/compiled_partitions/spectrum.root_partition.map.kpt b/incremental_db/compiled_partitions/spectrum.root_partition.map.kpt index 2a4fcb7..461d6ec 100644 Binary files a/incremental_db/compiled_partitions/spectrum.root_partition.map.kpt and b/incremental_db/compiled_partitions/spectrum.root_partition.map.kpt differ diff --git a/led_patterns.mif b/led_patterns.mif new file mode 100644 index 0000000..a3e49fc --- /dev/null +++ b/led_patterns.mif @@ -0,0 +1,31 @@ +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- Quartus II generated Memory Initialization File (.mif) + +WIDTH=8; +DEPTH=8; + +ADDRESS_RADIX=UNS; +DATA_RADIX=UNS; + +CONTENT BEGIN + 0 : 129; + 1 : 66; + 2 : 36; + [3..4] : 24; + 5 : 36; + 6 : 66; + 7 : 129; +END; diff --git a/output_files/greybox_tmp/cbx_args.txt b/output_files/greybox_tmp/cbx_args.txt new file mode 100644 index 0000000..90803fd --- /dev/null +++ b/output_files/greybox_tmp/cbx_args.txt @@ -0,0 +1,16 @@ +ADDRESS_ACLR_A=NONE +CLOCK_ENABLE_INPUT_A=BYPASS +CLOCK_ENABLE_OUTPUT_A=BYPASS +INIT_FILE= +INTENDED_DEVICE_FAMILY="Cyclone IV E" +NUMWORDS_A=8 +OPERATION_MODE=ROM +OUTDATA_ACLR_A=NONE +OUTDATA_REG_A=CLOCK0 +WIDTHAD_A=3 +WIDTH_A=8 +WIDTH_BYTEENA_A=1 +DEVICE_FAMILY="Cyclone IV E" +address_a +clock0 +q_a diff --git a/output_files/led_patterns.mif b/output_files/led_patterns.mif new file mode 100644 index 0000000..c4106c4 --- /dev/null +++ b/output_files/led_patterns.mif @@ -0,0 +1,32 @@ +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- Quartus II generated Memory Initialization File (.mif) + +WIDTH=8; +DEPTH=8; + +ADDRESS_RADIX=UNS; +DATA_RADIX=UNS; + +CONTENT BEGIN + 0 : 129; + 1 : 66; + 2 : 36; + 3 : 24; + 4 : 36; + 5 : 66; + 6 : 129; + 7 : 255; +END; diff --git a/output_files/spectrum.asm.rpt b/output_files/spectrum.asm.rpt index 493e463..bf2d0d1 100644 --- a/output_files/spectrum.asm.rpt +++ b/output_files/spectrum.asm.rpt @@ -1,5 +1,5 @@ Assembler report for spectrum -Wed Mar 30 11:51:38 2022 +Wed Mar 30 12:38:37 2022 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition @@ -37,7 +37,7 @@ applicable agreement for further details. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Wed Mar 30 11:51:38 2022 ; +; Assembler Status ; Successful - Wed Mar 30 12:38:37 2022 ; ; Revision Name ; spectrum ; ; Top-level Entity Name ; spectrum ; ; Family ; Cyclone IV E ; @@ -162,8 +162,8 @@ Default Value : On ; Option ; Setting ; +----------------+-----------------------+ ; Device ; EP4CE22F17C6 ; -; JTAG usercode ; 0x00138B42 ; -; Checksum ; 0x00138B42 ; +; JTAG usercode ; 0x00139765 ; +; Checksum ; 0x00139765 ; +----------------+-----------------------+ @@ -173,13 +173,13 @@ Default Value : On Info: ******************************************************************* Info: Running Quartus II 32-bit Assembler Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition - Info: Processing started: Wed Mar 30 11:51:37 2022 + Info: Processing started: Wed Mar 30 12:38:36 2022 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off spectrum -c spectrum Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 389 megabytes - Info: Processing ended: Wed Mar 30 11:51:38 2022 + Info: Peak virtual memory: 393 megabytes + Info: Processing ended: Wed Mar 30 12:38:37 2022 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 diff --git a/output_files/spectrum.done b/output_files/spectrum.done index 01312d4..49347a3 100644 --- a/output_files/spectrum.done +++ b/output_files/spectrum.done @@ -1 +1 @@ -Wed Mar 30 11:51:43 2022 +Wed Mar 30 12:38:42 2022 diff --git a/output_files/spectrum.eda.rpt b/output_files/spectrum.eda.rpt index db555f7..55633f7 100644 --- a/output_files/spectrum.eda.rpt +++ b/output_files/spectrum.eda.rpt @@ -1,5 +1,5 @@ EDA Netlist Writer report for spectrum -Wed Mar 30 11:51:43 2022 +Wed Mar 30 12:38:42 2022 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition @@ -36,7 +36,7 @@ applicable agreement for further details. +-------------------------------------------------------------------+ ; EDA Netlist Writer Summary ; +---------------------------+---------------------------------------+ -; EDA Netlist Writer Status ; Successful - Wed Mar 30 11:51:43 2022 ; +; EDA Netlist Writer Status ; Successful - Wed Mar 30 12:38:42 2022 ; ; Revision Name ; spectrum ; ; Top-level Entity Name ; spectrum ; ; Family ; Cyclone IV E ; @@ -88,7 +88,7 @@ applicable agreement for further details. Info: ******************************************************************* Info: Running Quartus II 32-bit EDA Netlist Writer Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition - Info: Processing started: Wed Mar 30 11:51:42 2022 + Info: Processing started: Wed Mar 30 12:38:41 2022 Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off spectrum -c spectrum Info (204019): Generated file spectrum_6_1200mv_85c_slow.vo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file spectrum_6_1200mv_0c_slow.vo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool @@ -99,8 +99,8 @@ Info (204019): Generated file spectrum_6_1200mv_0c_v_slow.sdo in folder "/home/b Info (204019): Generated file spectrum_min_1200mv_0c_v_fast.sdo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file spectrum_v.sdo in folder "/home/benny/work/fpga/projects/simulation/modelsim/" for EDA simulation tool Info: Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 352 megabytes - Info: Processing ended: Wed Mar 30 11:51:43 2022 + Info: Peak virtual memory: 344 megabytes + Info: Processing ended: Wed Mar 30 12:38:42 2022 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 diff --git a/output_files/spectrum.fit.rpt b/output_files/spectrum.fit.rpt index 94138b6..febc4a2 100644 --- a/output_files/spectrum.fit.rpt +++ b/output_files/spectrum.fit.rpt @@ -1,5 +1,5 @@ Fitter report for spectrum -Wed Mar 30 11:51:35 2022 +Wed Mar 30 12:38:34 2022 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition @@ -29,19 +29,21 @@ Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition 21. Control Signals 22. Global & Other Fast Signals 23. Non-Global High Fan-Out Signals - 24. Routing Usage Summary - 25. LAB Logic Elements - 26. LAB-wide Signals - 27. LAB Signals Sourced - 28. LAB Signals Sourced Out - 29. LAB Distinct Inputs - 30. I/O Rules Summary - 31. I/O Rules Details - 32. I/O Rules Matrix - 33. Fitter Device Options - 34. Operating Settings and Conditions - 35. Fitter Messages - 36. Fitter Suppressed Messages + 24. Fitter RAM Summary + 25. |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ALTSYNCRAM + 26. Routing Usage Summary + 27. LAB Logic Elements + 28. LAB-wide Signals + 29. LAB Signals Sourced + 30. LAB Signals Sourced Out + 31. LAB Distinct Inputs + 32. I/O Rules Summary + 33. I/O Rules Details + 34. I/O Rules Matrix + 35. Fitter Device Options + 36. Operating Settings and Conditions + 37. Fitter Messages + 38. Fitter Suppressed Messages @@ -67,20 +69,20 @@ applicable agreement for further details. +---------------------------------------------------------------------------------+ ; Fitter Summary ; +------------------------------------+--------------------------------------------+ -; Fitter Status ; Successful - Wed Mar 30 11:51:35 2022 ; +; Fitter Status ; Successful - Wed Mar 30 12:38:34 2022 ; ; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ; ; Revision Name ; spectrum ; ; Top-level Entity Name ; spectrum ; ; Family ; Cyclone IV E ; ; Device ; EP4CE22F17C6 ; ; Timing Models ; Final ; -; Total logic elements ; 35 / 22,320 ( < 1 % ) ; -; Total combinational functions ; 28 / 22,320 ( < 1 % ) ; -; Dedicated logic registers ; 35 / 22,320 ( < 1 % ) ; -; Total registers ; 35 ; +; Total logic elements ; 33 / 22,320 ( < 1 % ) ; +; Total combinational functions ; 33 / 22,320 ( < 1 % ) ; +; Dedicated logic registers ; 24 / 22,320 ( < 1 % ) ; +; Total registers ; 24 ; ; Total pins ; 9 / 154 ( 6 % ) ; ; Total virtual pins ; 0 ; -; Total memory bits ; 0 / 608,256 ( 0 % ) ; +; Total memory bits ; 64 / 608,256 ( < 1 % ) ; ; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ; ; Total PLLs ; 0 / 4 ( 0 % ) ; +------------------------------------+--------------------------------------------+ @@ -2372,14 +2374,14 @@ From Design Partitions [A] : From Rapid Recompile [B] : Type : -- Requested -Total [A + B] : 0.00 % ( 0 / 93 ) -From Design Partitions [A] : 0.00 % ( 0 / 93 ) -From Rapid Recompile [B] : 0.00 % ( 0 / 93 ) +Total [A + B] : 0.00 % ( 0 / 95 ) +From Design Partitions [A] : 0.00 % ( 0 / 95 ) +From Rapid Recompile [B] : 0.00 % ( 0 / 95 ) Type : -- Achieved -Total [A + B] : 0.00 % ( 0 / 93 ) -From Design Partitions [A] : 0.00 % ( 0 / 93 ) -From Rapid Recompile [B] : 0.00 % ( 0 / 93 ) +Total [A + B] : 0.00 % ( 0 / 95 ) +From Design Partitions [A] : 0.00 % ( 0 / 95 ) +From Rapid Recompile [B] : 0.00 % ( 0 / 95 ) Type : Total [A + B] : @@ -2430,7 +2432,7 @@ Contents : hard_block:auto_generated_inst ; Incremental Compilation Placement Preservation ; +--------------------------------------------------------------------------------+ Partition Name : Top -Preservation Achieved : 0.00 % ( 0 / 83 ) +Preservation Achieved : 0.00 % ( 0 / 85 ) Preservation Level Used : N/A Netlist Type Used : Source File Preservation Method : N/A @@ -2452,54 +2454,54 @@ Notes : The pin-out file can be found in /home/benny/work/fpga/projects/output_files/spectrum.pin. -+---------------------------------------------------------------------+ -; Fitter Resource Usage Summary ; -+---------------------------------------------+-----------------------+ -; Resource ; Usage ; -+---------------------------------------------+-----------------------+ -; Total logic elements ; 35 / 22,320 ( < 1 % ) ; -; -- Combinational with no register ; 0 ; -; -- Register only ; 7 ; -; -- Combinational with a register ; 28 ; -; ; ; -; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 0 ; -; -- 3 input functions ; 1 ; -; -- <=2 input functions ; 27 ; -; -- Register only ; 7 ; -; ; ; -; Logic elements by mode ; ; -; -- normal mode ; 2 ; -; -- arithmetic mode ; 26 ; -; ; ; -; Total registers* ; 35 / 23,018 ( < 1 % ) ; -; -- Dedicated logic registers ; 35 / 22,320 ( < 1 % ) ; -; -- I/O registers ; 0 / 698 ( 0 % ) ; -; ; ; -; Total LABs: partially or completely used ; 5 / 1,395 ( < 1 % ) ; -; Virtual pins ; 0 ; -; I/O pins ; 9 / 154 ( 6 % ) ; -; -- Clock pins ; 1 / 7 ( 14 % ) ; -; -- Dedicated input pins ; 0 / 9 ( 0 % ) ; -; ; ; -; Global signals ; 1 ; -; M9Ks ; 0 / 66 ( 0 % ) ; -; Total block memory bits ; 0 / 608,256 ( 0 % ) ; -; Total block memory implementation bits ; 0 / 608,256 ( 0 % ) ; -; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ; -; PLLs ; 0 / 4 ( 0 % ) ; -; Global clocks ; 1 / 20 ( 5 % ) ; -; JTAGs ; 0 / 1 ( 0 % ) ; -; CRC blocks ; 0 / 1 ( 0 % ) ; -; ASMI blocks ; 0 / 1 ( 0 % ) ; -; Impedance control blocks ; 0 / 4 ( 0 % ) ; -; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ; -; Peak interconnect usage (total/H/V) ; 0% / 0% / 0% ; -; Maximum fan-out ; 35 ; -; Highest non-global fan-out ; 2 ; -; Total fan-out ; 154 ; -; Average fan-out ; 1.56 ; -+---------------------------------------------+-----------------------+ ++-----------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+-------------------------+ +; Resource ; Usage ; ++---------------------------------------------+-------------------------+ +; Total logic elements ; 33 / 22,320 ( < 1 % ) ; +; -- Combinational with no register ; 9 ; +; -- Register only ; 0 ; +; -- Combinational with a register ; 24 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 10 ; +; -- 3 input functions ; 1 ; +; -- <=2 input functions ; 22 ; +; -- Register only ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 13 ; +; -- arithmetic mode ; 20 ; +; ; ; +; Total registers* ; 24 / 23,018 ( < 1 % ) ; +; -- Dedicated logic registers ; 24 / 22,320 ( < 1 % ) ; +; -- I/O registers ; 0 / 698 ( 0 % ) ; +; ; ; +; Total LABs: partially or completely used ; 3 / 1,395 ( < 1 % ) ; +; Virtual pins ; 0 ; +; I/O pins ; 9 / 154 ( 6 % ) ; +; -- Clock pins ; 1 / 7 ( 14 % ) ; +; -- Dedicated input pins ; 0 / 9 ( 0 % ) ; +; ; ; +; Global signals ; 1 ; +; M9Ks ; 1 / 66 ( 2 % ) ; +; Total block memory bits ; 64 / 608,256 ( < 1 % ) ; +; Total block memory implementation bits ; 9,216 / 608,256 ( 2 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ; +; PLLs ; 0 / 4 ( 0 % ) ; +; Global clocks ; 1 / 20 ( 5 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; ASMI blocks ; 0 / 1 ( 0 % ) ; +; Impedance control blocks ; 0 / 4 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ; +; Peak interconnect usage (total/H/V) ; 0% / 0% / 0% ; +; Maximum fan-out ; 25 ; +; Highest non-global fan-out ; 4 ; +; Total fan-out ; 161 ; +; Average fan-out ; 1.85 ; ++---------------------------------------------+-------------------------+ * Register count does not include registers inside RAM blocks or DSP blocks. @@ -2516,19 +2518,19 @@ Top : hard_block:auto_generated_inst : Statistic : Total logic elements -Top : 35 / 22320 ( < 1 % ) +Top : 33 / 22320 ( < 1 % ) hard_block:auto_generated_inst : 0 / 22320 ( 0 % ) Statistic : -- Combinational with no register -Top : 0 +Top : 9 hard_block:auto_generated_inst : 0 Statistic : -- Register only -Top : 7 +Top : 0 hard_block:auto_generated_inst : 0 Statistic : -- Combinational with a register -Top : 28 +Top : 24 hard_block:auto_generated_inst : 0 Statistic : @@ -2540,7 +2542,7 @@ Top : hard_block:auto_generated_inst : Statistic : -- 4 input functions -Top : 0 +Top : 10 hard_block:auto_generated_inst : 0 Statistic : -- 3 input functions @@ -2548,11 +2550,11 @@ Top : 1 hard_block:auto_generated_inst : 0 Statistic : -- <=2 input functions -Top : 27 +Top : 22 hard_block:auto_generated_inst : 0 Statistic : -- Register only -Top : 7 +Top : 0 hard_block:auto_generated_inst : 0 Statistic : @@ -2564,11 +2566,11 @@ Top : hard_block:auto_generated_inst : Statistic : -- normal mode -Top : 2 +Top : 13 hard_block:auto_generated_inst : 0 Statistic : -- arithmetic mode -Top : 26 +Top : 20 hard_block:auto_generated_inst : 0 Statistic : @@ -2576,11 +2578,11 @@ Top : hard_block:auto_generated_inst : Statistic : Total registers -Top : 35 +Top : 24 hard_block:auto_generated_inst : 0 Statistic : -- Dedicated logic registers -Top : 35 / 22320 ( < 1 % ) +Top : 24 / 22320 ( < 1 % ) hard_block:auto_generated_inst : 0 / 22320 ( 0 % ) Statistic : -- I/O registers @@ -2592,7 +2594,7 @@ Top : hard_block:auto_generated_inst : Statistic : Total LABs: partially or completely used -Top : 5 / 1395 ( < 1 % ) +Top : 3 / 1395 ( < 1 % ) hard_block:auto_generated_inst : 0 / 1395 ( 0 % ) Statistic : @@ -2612,13 +2614,17 @@ Top : 0 / 132 ( 0 % ) hard_block:auto_generated_inst : 0 / 132 ( 0 % ) Statistic : Total memory bits -Top : 0 +Top : 64 hard_block:auto_generated_inst : 0 Statistic : Total RAM block bits -Top : 0 +Top : 9216 hard_block:auto_generated_inst : 0 +Statistic : M9K +Top : 1 / 66 ( 1 % ) +hard_block:auto_generated_inst : 0 / 66 ( 0 % ) + Statistic : Clock control block Top : 1 / 24 ( 4 % ) hard_block:auto_generated_inst : 0 / 24 ( 0 % ) @@ -2656,11 +2662,11 @@ Top : hard_block:auto_generated_inst : Statistic : -- Total Connections -Top : 149 +Top : 156 hard_block:auto_generated_inst : 5 Statistic : -- Registered Connections -Top : 43 +Top : 38 hard_block:auto_generated_inst : 0 Statistic : @@ -2767,7 +2773,7 @@ I/O Bank : 3 X coordinate : 27 Y coordinate : 0 Z coordinate : 21 -Combinational Fan-Out : 35 +Combinational Fan-Out : 25 Registered Fan-Out : 0 Global : yes Input Register : no @@ -6219,21 +6225,72 @@ Note: Pin directions (input, output or bidir) are based on device operating in u ; Fitter Resource Utilization by Entity ; +--------------------------------------------------------------------------------+ Compilation Hierarchy Node : |spectrum -Logic Cells : 35 (35) -Dedicated Logic Registers : 35 (35) +Logic Cells : 33 (33) +Dedicated Logic Registers : 24 (24) I/O Registers : 0 (0) -Memory Bits : 0 -M9Ks : 0 +Memory Bits : 64 +M9Ks : 1 DSP Elements : 0 DSP 9x9 : 0 DSP 18x18 : 0 Pins : 9 Virtual Pins : 0 -LUT-Only LCs : 0 (0) -Register-Only LCs : 7 (7) -LUT/Register LCs : 28 (28) +LUT-Only LCs : 9 (9) +Register-Only LCs : 0 (0) +LUT/Register LCs : 24 (24) Full Hierarchy Name : |spectrum Library Name : work + +Compilation Hierarchy Node : |rom0:rom| +Logic Cells : 0 (0) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 64 +M9Ks : 1 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 0 (0) +LUT/Register LCs : 0 (0) +Full Hierarchy Name : |spectrum|rom0:rom +Library Name : work + +Compilation Hierarchy Node : |altsyncram:altsyncram_component| +Logic Cells : 0 (0) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 64 +M9Ks : 1 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 0 (0) +LUT/Register LCs : 0 (0) +Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component +Library Name : work + +Compilation Hierarchy Node : |altsyncram_ro91:auto_generated| +Logic Cells : 0 (0) +Dedicated Logic Registers : 0 (0) +I/O Registers : 0 (0) +Memory Bits : 64 +M9Ks : 1 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +LUT-Only LCs : 0 (0) +Register-Only LCs : 0 (0) +LUT/Register LCs : 0 (0) +Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated +Library Name : work +--------------------------------------------------------------------------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. @@ -6332,7 +6389,7 @@ Setting : +--------------------------------------------------------------------------------+ Name : CLOCK_50 Location : PIN_R8 -Fan-Out : 35 +Fan-Out : 25 Usage : Clock Global : yes Global Resource Used : Global Clock @@ -6347,8 +6404,8 @@ Enable Signal Source Name : -- +--------------------------------------------------------------------------------+ Name : CLOCK_50 Location : PIN_R8 -Fan-Out : 35 -Fan-Out Using Intentional Clock Skew : 12 +Fan-Out : 25 +Fan-Out Using Intentional Clock Skew : 3 Global Resource Used : Global Clock Global Line Name : GCLK18 Enable Signal Source Name : -- @@ -6356,101 +6413,139 @@ Enable Signal Source Name : -- -+---------------------------------+ -; Non-Global High Fan-Out Signals ; -+----------------+----------------+ -; Name ; Fan-Out ; -+----------------+----------------+ -; counter[0] ; 2 ; -; counter[27] ; 2 ; -; counter[26] ; 2 ; -; counter[25] ; 2 ; -; counter[24] ; 2 ; -; counter[23] ; 2 ; -; counter[22] ; 2 ; -; counter[21] ; 2 ; -; counter[0]~81 ; 1 ; -; LED[6]~reg0 ; 1 ; -; LED[5]~reg0 ; 1 ; -; LED[4]~reg0 ; 1 ; -; LED[3]~reg0 ; 1 ; -; LED[2]~reg0 ; 1 ; -; LED[1]~reg0 ; 1 ; -; LED[0]~reg0 ; 1 ; -; counter[27]~79 ; 1 ; -; counter[26]~78 ; 1 ; -; counter[26]~77 ; 1 ; -; counter[25]~76 ; 1 ; -; counter[25]~75 ; 1 ; -; counter[24]~74 ; 1 ; -; counter[24]~73 ; 1 ; -; counter[23]~72 ; 1 ; -; counter[23]~71 ; 1 ; -; counter[22]~70 ; 1 ; -; counter[22]~69 ; 1 ; -; counter[21]~68 ; 1 ; -; counter[21]~67 ; 1 ; -; counter[20]~66 ; 1 ; -; counter[20]~65 ; 1 ; -; counter[19]~64 ; 1 ; -; counter[19]~63 ; 1 ; -; counter[18]~62 ; 1 ; -; counter[18]~61 ; 1 ; -; counter[17]~60 ; 1 ; -; counter[17]~59 ; 1 ; -; counter[16]~58 ; 1 ; -; counter[16]~57 ; 1 ; -; counter[15]~56 ; 1 ; -; counter[15]~55 ; 1 ; -; counter[14]~54 ; 1 ; -; counter[14]~53 ; 1 ; -; counter[13]~52 ; 1 ; -; counter[13]~51 ; 1 ; -; counter[12]~50 ; 1 ; -; counter[12]~49 ; 1 ; -; counter[11]~48 ; 1 ; -; counter[11]~47 ; 1 ; -; counter[10]~46 ; 1 ; -; counter[10]~45 ; 1 ; -; counter[9]~44 ; 1 ; -; counter[9]~43 ; 1 ; -; counter[8]~42 ; 1 ; -; counter[8]~41 ; 1 ; -; counter[7]~40 ; 1 ; -; counter[7]~39 ; 1 ; -; counter[6]~38 ; 1 ; -; counter[6]~37 ; 1 ; -; counter[5]~36 ; 1 ; -; counter[5]~35 ; 1 ; -; counter[4]~34 ; 1 ; -; counter[4]~33 ; 1 ; -; counter[3]~32 ; 1 ; -; counter[3]~31 ; 1 ; -; counter[2]~30 ; 1 ; -; counter[2]~29 ; 1 ; -; counter[1]~28 ; 1 ; -; counter[1]~27 ; 1 ; -; counter[1] ; 1 ; -; counter[2] ; 1 ; -; counter[3] ; 1 ; -; counter[4] ; 1 ; -; counter[5] ; 1 ; -; counter[6] ; 1 ; -; counter[7] ; 1 ; -; counter[8] ; 1 ; -; counter[9] ; 1 ; -; counter[10] ; 1 ; -; counter[11] ; 1 ; -; counter[12] ; 1 ; -; counter[13] ; 1 ; -; counter[14] ; 1 ; -; counter[15] ; 1 ; -; counter[16] ; 1 ; -; counter[17] ; 1 ; -; counter[18] ; 1 ; -; counter[19] ; 1 ; -; counter[20] ; 1 ; -+----------------+----------------+ ++------------------------------------------------------------------------------------------+ +; Non-Global High Fan-Out Signals ; ++--------------------------------------------------------------------------------+---------+ +; Name ; Fan-Out ; ++--------------------------------------------------------------------------------+---------+ +; address[0] ; 4 ; +; Add0~40 ; 4 ; +; Equal0~4 ; 3 ; +; address[1] ; 3 ; +; Add0~38 ; 3 ; +; Add0~36 ; 3 ; +; Add0~34 ; 3 ; +; Add0~32 ; 3 ; +; Equal0~5 ; 2 ; +; address[2] ; 2 ; +; Add0~30 ; 2 ; +; Add0~28 ; 2 ; +; Add0~26 ; 2 ; +; Add0~24 ; 2 ; +; Add0~22 ; 2 ; +; Add0~20 ; 2 ; +; Add0~18 ; 2 ; +; Add0~16 ; 2 ; +; Add0~14 ; 2 ; +; Add0~12 ; 2 ; +; Add0~10 ; 2 ; +; Add0~8 ; 2 ; +; Add0~6 ; 2 ; +; Add0~4 ; 2 ; +; Add0~2 ; 2 ; +; Add0~0 ; 2 ; +; address[2]~3 ; 1 ; +; address[1]~2 ; 1 ; +; address[1]~1 ; 1 ; +; Equal0~7 ; 1 ; +; Equal0~6 ; 1 ; +; address[0]~0 ; 1 ; +; Equal0~3 ; 1 ; +; Equal0~2 ; 1 ; +; Equal0~1 ; 1 ; +; Equal0~0 ; 1 ; +; counter[0] ; 1 ; +; counter[1] ; 1 ; +; counter[2] ; 1 ; +; counter[3] ; 1 ; +; counter[4] ; 1 ; +; counter[5] ; 1 ; +; counter[6] ; 1 ; +; counter[7] ; 1 ; +; counter[8] ; 1 ; +; counter[9] ; 1 ; +; counter[10] ; 1 ; +; counter[11] ; 1 ; +; counter[12] ; 1 ; +; counter[13] ; 1 ; +; counter[14] ; 1 ; +; counter[15] ; 1 ; +; counter[16] ; 1 ; +; counter[17] ; 1 ; +; counter[18] ; 1 ; +; counter[19] ; 1 ; +; counter[20] ; 1 ; +; Add0~39 ; 1 ; +; Add0~37 ; 1 ; +; Add0~35 ; 1 ; +; Add0~33 ; 1 ; +; Add0~31 ; 1 ; +; Add0~29 ; 1 ; +; Add0~27 ; 1 ; +; Add0~25 ; 1 ; +; Add0~23 ; 1 ; +; Add0~21 ; 1 ; +; Add0~19 ; 1 ; +; Add0~17 ; 1 ; +; Add0~15 ; 1 ; +; Add0~13 ; 1 ; +; Add0~11 ; 1 ; +; Add0~9 ; 1 ; +; Add0~7 ; 1 ; +; Add0~5 ; 1 ; +; Add0~3 ; 1 ; +; Add0~1 ; 1 ; +; rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[1] ; 1 ; +; rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[2] ; 1 ; +; rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[3] ; 1 ; +; rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[4] ; 1 ; +; rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[5] ; 1 ; +; rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[6] ; 1 ; +; rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[7] ; 1 ; +; rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[0] ; 1 ; ++--------------------------------------------------------------------------------+---------+ + + ++--------------------------------------------------------------------------------+ +; Fitter RAM Summary ; ++--------------------------------------------------------------------------------+ +Name : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ALTSYNCRAM +Type : AUTO +Mode : ROM +Clock Mode : Single Clock +Port A Depth : 8 +Port A Width : 8 +Port B Depth : -- +Port B Width : -- +Port A Input Registers : yes +Port A Output Registers : yes +Port B Input Registers : -- +Port B Output Registers : -- +Size : 64 +Implementation Port A Depth : 8 +Implementation Port A Width : 8 +Implementation Port B Depth : -- +Implementation Port B Width : -- +Implementation Bits : 64 +M9Ks : 1 +MIF : led_patterns.mif +Location : M9K_X33_Y26_N0 +Mixed Width RDW Mode : Don't care +Port A RDW Mode : Old data +Port B RDW Mode : Old data +Fits in MLABs : No - Unknown ++--------------------------------------------------------------------------------+ + +Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section. + + +RAM content values are presented in the following format: (Binary) (Octal) (Decimal) (Hexadecimal) ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ALTSYNCRAM ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Addr ; +0 ; +1 ; +2 ; +3 ; +4 ; +5 ; +6 ; +7 ; ++----------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+ +;0;(10000001) (201) (129) (81) ;(01000010) (102) (66) (42) ;(00100100) (44) (36) (24) ;(00011000) (30) (24) (18) ;(00011000) (30) (24) (18) ;(00100100) (44) (36) (24) ;(01000010) (102) (66) (42) ;(10000001) (201) (129) (81) ; +-----------------------------------------------+ @@ -6458,65 +6553,65 @@ Enable Signal Source Name : -- +-----------------------+-----------------------+ ; Routing Resource Type ; Usage ; +-----------------------+-----------------------+ -; Block interconnects ; 16 / 71,559 ( < 1 % ) ; -; C16 interconnects ; 0 / 2,597 ( 0 % ) ; -; C4 interconnects ; 9 / 46,848 ( < 1 % ) ; -; Direct links ; 4 / 71,559 ( < 1 % ) ; +; Block interconnects ; 42 / 71,559 ( < 1 % ) ; +; C16 interconnects ; 3 / 2,597 ( < 1 % ) ; +; C4 interconnects ; 20 / 46,848 ( < 1 % ) ; +; Direct links ; 24 / 71,559 ( < 1 % ) ; ; Global clocks ; 1 / 20 ( 5 % ) ; -; Local interconnects ; 28 / 24,624 ( < 1 % ) ; -; R24 interconnects ; 4 / 2,496 ( < 1 % ) ; -; R4 interconnects ; 17 / 62,424 ( < 1 % ) ; +; Local interconnects ; 24 / 24,624 ( < 1 % ) ; +; R24 interconnects ; 7 / 2,496 ( < 1 % ) ; +; R4 interconnects ; 27 / 62,424 ( < 1 % ) ; +-----------------------+-----------------------+ -+--------------------------------------------------------------------------+ -; LAB Logic Elements ; -+--------------------------------------------+-----------------------------+ -; Number of Logic Elements (Average = 7.00) ; Number of LABs (Total = 5) ; -+--------------------------------------------+-----------------------------+ -; 1 ; 1 ; -; 2 ; 1 ; -; 3 ; 0 ; -; 4 ; 1 ; -; 5 ; 0 ; -; 6 ; 0 ; -; 7 ; 0 ; -; 8 ; 0 ; -; 9 ; 0 ; -; 10 ; 0 ; -; 11 ; 0 ; -; 12 ; 0 ; -; 13 ; 0 ; -; 14 ; 2 ; -; 15 ; 0 ; -; 16 ; 0 ; -+--------------------------------------------+-----------------------------+ ++---------------------------------------------------------------------------+ +; LAB Logic Elements ; ++---------------------------------------------+-----------------------------+ +; Number of Logic Elements (Average = 11.00) ; Number of LABs (Total = 3) ; ++---------------------------------------------+-----------------------------+ +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 1 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 1 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 1 ; +; 16 ; 0 ; ++---------------------------------------------+-----------------------------+ +------------------------------------------------------------------+ ; LAB-wide Signals ; +------------------------------------+-----------------------------+ -; LAB-wide Signals (Average = 1.00) ; Number of LABs (Total = 5) ; +; LAB-wide Signals (Average = 1.00) ; Number of LABs (Total = 3) ; +------------------------------------+-----------------------------+ -; 1 Clock ; 5 ; +; 1 Clock ; 3 ; +------------------------------------+-----------------------------+ +----------------------------------------------------------------------------+ ; LAB Signals Sourced ; +----------------------------------------------+-----------------------------+ -; Number of Signals Sourced (Average = 14.00) ; Number of LABs (Total = 5) ; +; Number of Signals Sourced (Average = 19.00) ; Number of LABs (Total = 3) ; +----------------------------------------------+-----------------------------+ ; 0 ; 0 ; ; 1 ; 0 ; -; 2 ; 1 ; +; 2 ; 0 ; ; 3 ; 0 ; -; 4 ; 1 ; +; 4 ; 0 ; ; 5 ; 0 ; ; 6 ; 0 ; ; 7 ; 0 ; -; 8 ; 1 ; -; 9 ; 0 ; +; 8 ; 0 ; +; 9 ; 1 ; ; 10 ; 0 ; ; 11 ; 0 ; ; 12 ; 0 ; @@ -6529,43 +6624,46 @@ Enable Signal Source Name : -- ; 19 ; 0 ; ; 20 ; 0 ; ; 21 ; 0 ; -; 22 ; 0 ; +; 22 ; 1 ; ; 23 ; 0 ; ; 24 ; 0 ; ; 25 ; 0 ; -; 26 ; 0 ; -; 27 ; 0 ; -; 28 ; 2 ; +; 26 ; 1 ; +----------------------------------------------+-----------------------------+ +-------------------------------------------------------------------------------+ ; LAB Signals Sourced Out ; +-------------------------------------------------+-----------------------------+ -; Number of Signals Sourced Out (Average = 2.80) ; Number of LABs (Total = 5) ; +; Number of Signals Sourced Out (Average = 4.33) ; Number of LABs (Total = 3) ; +-------------------------------------------------+-----------------------------+ -; 0 ; 1 ; -; 1 ; 1 ; -; 2 ; 1 ; -; 3 ; 0 ; +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 1 ; ; 4 ; 1 ; ; 5 ; 0 ; -; 6 ; 0 ; -; 7 ; 1 ; +; 6 ; 1 ; +-------------------------------------------------+-----------------------------+ +---------------------------------------------------------------------------+ ; LAB Distinct Inputs ; +---------------------------------------------+-----------------------------+ -; Number of Distinct Inputs (Average = 2.60) ; Number of LABs (Total = 5) ; +; Number of Distinct Inputs (Average = 4.67) ; Number of LABs (Total = 3) ; +---------------------------------------------+-----------------------------+ ; 0 ; 0 ; ; 1 ; 1 ; -; 2 ; 2 ; -; 3 ; 1 ; +; 2 ; 1 ; +; 3 ; 0 ; ; 4 ; 0 ; -; 5 ; 1 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 1 ; +---------------------------------------------+-----------------------------+ @@ -7338,6 +7436,7 @@ Info (169124): Fitter converted 5 user pins into dedicated programming pins Info (169125): Pin ~ALTERA_DATA0~ is reserved at location H2 Info (169125): Pin ~ALTERA_nCEO~ is reserved at location F16 Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements. Critical Warning (332012): Synopsys Design Constraints File file not found: 'spectrum.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. Info (332144): No user constrained base clocks found in the design Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" @@ -7503,10 +7602,10 @@ Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 Info (170193): Fitter routing operations beginning Info (170195): Router estimated average interconnect usage is 0% of the available device resources Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X32_Y23 to location X42_Y34 -Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 +Info (170194): Fitter routing operations ending: elapsed time is 00:00:01 Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. Info (170201): Optimizations that may affect the design's routability were skipped -Info (11888): Total time spent on timing analysis during the Fitter is 0.10 seconds. +Info (11888): Total time spent on timing analysis during the Fitter is 0.16 seconds. Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (334003): Started post-fitting delay annotation @@ -7517,9 +7616,9 @@ Warning (169177): 1 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V Info (169178): Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at R8 Info (144001): Generated suppressed messages file /home/benny/work/fpga/projects/output_files/spectrum.fit.smsg Info: Quartus II 32-bit Fitter was successful. 0 errors, 152 warnings - Info: Peak virtual memory: 588 megabytes - Info: Processing ended: Wed Mar 30 11:51:36 2022 - Info: Elapsed time: 00:00:06 + Info: Peak virtual memory: 600 megabytes + Info: Processing ended: Wed Mar 30 12:38:34 2022 + Info: Elapsed time: 00:00:05 Info: Total CPU time (on all processors): 00:00:06 diff --git a/output_files/spectrum.fit.summary b/output_files/spectrum.fit.summary index 287f5af..dbfec8e 100644 --- a/output_files/spectrum.fit.summary +++ b/output_files/spectrum.fit.summary @@ -1,16 +1,16 @@ -Fitter Status : Successful - Wed Mar 30 11:51:35 2022 +Fitter Status : Successful - Wed Mar 30 12:38:34 2022 Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition Revision Name : spectrum Top-level Entity Name : spectrum Family : Cyclone IV E Device : EP4CE22F17C6 Timing Models : Final -Total logic elements : 35 / 22,320 ( < 1 % ) - Total combinational functions : 28 / 22,320 ( < 1 % ) - Dedicated logic registers : 35 / 22,320 ( < 1 % ) -Total registers : 35 +Total logic elements : 33 / 22,320 ( < 1 % ) + Total combinational functions : 33 / 22,320 ( < 1 % ) + Dedicated logic registers : 24 / 22,320 ( < 1 % ) +Total registers : 24 Total pins : 9 / 154 ( 6 % ) Total virtual pins : 0 -Total memory bits : 0 / 608,256 ( 0 % ) +Total memory bits : 64 / 608,256 ( < 1 % ) Embedded Multiplier 9-bit elements : 0 / 132 ( 0 % ) Total PLLs : 0 / 4 ( 0 % ) diff --git a/output_files/spectrum.flow.rpt b/output_files/spectrum.flow.rpt index e2ccaed..c3a2fdd 100644 --- a/output_files/spectrum.flow.rpt +++ b/output_files/spectrum.flow.rpt @@ -1,5 +1,5 @@ Flow report for spectrum -Wed Mar 30 11:51:43 2022 +Wed Mar 30 12:38:42 2022 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition @@ -40,20 +40,20 @@ applicable agreement for further details. +---------------------------------------------------------------------------------+ ; Flow Summary ; +------------------------------------+--------------------------------------------+ -; Flow Status ; Successful - Wed Mar 30 11:51:43 2022 ; +; Flow Status ; Successful - Wed Mar 30 12:38:42 2022 ; ; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ; ; Revision Name ; spectrum ; ; Top-level Entity Name ; spectrum ; ; Family ; Cyclone IV E ; ; Device ; EP4CE22F17C6 ; ; Timing Models ; Final ; -; Total logic elements ; 35 / 22,320 ( < 1 % ) ; -; Total combinational functions ; 28 / 22,320 ( < 1 % ) ; -; Dedicated logic registers ; 35 / 22,320 ( < 1 % ) ; -; Total registers ; 35 ; +; Total logic elements ; 33 / 22,320 ( < 1 % ) ; +; Total combinational functions ; 33 / 22,320 ( < 1 % ) ; +; Dedicated logic registers ; 24 / 22,320 ( < 1 % ) ; +; Total registers ; 24 ; ; Total pins ; 9 / 154 ( 6 % ) ; ; Total virtual pins ; 0 ; -; Total memory bits ; 0 / 608,256 ( 0 % ) ; +; Total memory bits ; 64 / 608,256 ( < 1 % ) ; ; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ; ; Total PLLs ; 0 / 4 ( 0 % ) ; +------------------------------------+--------------------------------------------+ @@ -64,7 +64,7 @@ applicable agreement for further details. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 03/30/2022 11:51:28 ; +; Start date & time ; 03/30/2022 12:38:27 ; ; Main task ; Compilation ; ; Revision Name ; spectrum ; +-------------------+---------------------+ @@ -74,7 +74,7 @@ applicable agreement for further details. ; Flow Non-Default Global Settings ; +--------------------------------------------------------------------------------+ Assignment Name : COMPILER_SIGNATURE_ID -Value : 0.164863028816849 +Value : 0.164863310720961 Default Value : -- Entity Name : -- Section Id : -- @@ -91,6 +91,18 @@ Default Value : Entity Name : -- Section Id : -- +Assignment Name : IP_TOOL_NAME +Value : ROM: 1-PORT +Default Value : -- +Entity Name : -- +Section Id : -- + +Assignment Name : IP_TOOL_VERSION +Value : 13.1 +Default Value : -- +Entity Name : -- +Section Id : -- + Assignment Name : MAX_CORE_JUNCTION_TEMP Value : 85 Default Value : -- @@ -103,6 +115,12 @@ Default Value : -- Entity Name : -- Section Id : -- +Assignment Name : MISC_FILE +Value : rom0_bb.v +Default Value : -- +Entity Name : -- +Section Id : -- + Assignment Name : NOMINAL_CORE_SUPPLY_VOLTAGE Value : 1.2V Default Value : -- @@ -140,37 +158,37 @@ Section Id : -- ; Flow Elapsed Time ; +--------------------------------------------------------------------------------+ Module Name : Analysis & Synthesis -Elapsed Time : 00:00:01 +Elapsed Time : 00:00:02 Average Processors Used : 1.0 -Peak Virtual Memory : 377 MB +Peak Virtual Memory : 373 MB Total CPU Time (on all processors) : 00:00:01 Module Name : Fitter Elapsed Time : 00:00:05 Average Processors Used : 1.0 -Peak Virtual Memory : 588 MB +Peak Virtual Memory : 600 MB Total CPU Time (on all processors) : 00:00:06 Module Name : Assembler Elapsed Time : 00:00:01 Average Processors Used : 1.0 -Peak Virtual Memory : 389 MB +Peak Virtual Memory : 393 MB Total CPU Time (on all processors) : 00:00:01 Module Name : TimeQuest Timing Analyzer Elapsed Time : 00:00:02 Average Processors Used : 1.0 -Peak Virtual Memory : 412 MB +Peak Virtual Memory : 415 MB Total CPU Time (on all processors) : 00:00:02 Module Name : EDA Netlist Writer Elapsed Time : 00:00:01 Average Processors Used : 1.0 -Peak Virtual Memory : 340 MB +Peak Virtual Memory : 332 MB Total CPU Time (on all processors) : 00:00:01 Module Name : Total -Elapsed Time : 00:00:10 +Elapsed Time : 00:00:11 Average Processors Used : -- Peak Virtual Memory : -- Total CPU Time (on all processors) : 00:00:11 diff --git a/output_files/spectrum.jdi b/output_files/spectrum.jdi index 7b0c904..ade2713 100644 --- a/output_files/spectrum.jdi +++ b/output_files/spectrum.jdi @@ -1,6 +1,6 @@ - + diff --git a/output_files/spectrum.map.rpt b/output_files/spectrum.map.rpt index 3ef869f..12cac49 100644 --- a/output_files/spectrum.map.rpt +++ b/output_files/spectrum.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for spectrum -Wed Mar 30 11:51:29 2022 +Wed Mar 30 12:38:28 2022 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition @@ -13,10 +13,14 @@ Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition 5. Analysis & Synthesis Source Files Read 6. Analysis & Synthesis Resource Usage Summary 7. Analysis & Synthesis Resource Utilization by Entity - 8. Registers Removed During Synthesis - 9. General Register Statistics - 10. Elapsed Time Per Partition - 11. Analysis & Synthesis Messages + 8. Analysis & Synthesis RAM Summary + 9. Analysis & Synthesis IP Cores Summary + 10. General Register Statistics + 11. Source assignments for rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated + 12. Parameter Settings for User Entity Instance: rom0:rom|altsyncram:altsyncram_component + 13. altsyncram Parameter Settings by Entity Instance + 14. Elapsed Time Per Partition + 15. Analysis & Synthesis Messages @@ -42,18 +46,18 @@ applicable agreement for further details. +---------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +------------------------------------+--------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Wed Mar 30 11:51:29 2022 ; +; Analysis & Synthesis Status ; Successful - Wed Mar 30 12:38:28 2022 ; ; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ; ; Revision Name ; spectrum ; ; Top-level Entity Name ; spectrum ; ; Family ; Cyclone IV E ; -; Total logic elements ; 35 ; -; Total combinational functions ; 28 ; -; Dedicated logic registers ; 35 ; -; Total registers ; 35 ; +; Total logic elements ; 33 ; +; Total combinational functions ; 33 ; +; Dedicated logic registers ; 24 ; +; Total registers ; 24 ; ; Total pins ; 9 ; ; Total virtual pins ; 0 ; -; Total memory bits ; 0 ; +; Total memory bits ; 64 ; ; Embedded Multiplier 9-bit elements ; 0 ; ; Total PLLs ; 0 ; +------------------------------------+--------------------------------------------+ @@ -400,6 +404,78 @@ Used in Netlist : yes File Type : User Verilog HDL File File Name with Absolute Path : /home/benny/work/fpga/projects/spectrum.v Library : + +File Name with User-Entered Path : led_patterns.mif +Used in Netlist : yes +File Type : User Memory Initialization File +File Name with Absolute Path : /home/benny/work/fpga/projects/led_patterns.mif +Library : + +File Name with User-Entered Path : rom0.v +Used in Netlist : yes +File Type : User Wizard-Generated File +File Name with Absolute Path : /home/benny/work/fpga/projects/rom0.v +Library : + +File Name with User-Entered Path : altsyncram.tdf +Used in Netlist : yes +File Type : Megafunction +File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf +Library : + +File Name with User-Entered Path : stratix_ram_block.inc +Used in Netlist : yes +File Type : Megafunction +File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/stratix_ram_block.inc +Library : + +File Name with User-Entered Path : lpm_mux.inc +Used in Netlist : yes +File Type : Megafunction +File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/lpm_mux.inc +Library : + +File Name with User-Entered Path : lpm_decode.inc +Used in Netlist : yes +File Type : Megafunction +File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/lpm_decode.inc +Library : + +File Name with User-Entered Path : aglobal131.inc +Used in Netlist : yes +File Type : Megafunction +File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/aglobal131.inc +Library : + +File Name with User-Entered Path : a_rdenreg.inc +Used in Netlist : yes +File Type : Megafunction +File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/a_rdenreg.inc +Library : + +File Name with User-Entered Path : altrom.inc +Used in Netlist : yes +File Type : Megafunction +File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/altrom.inc +Library : + +File Name with User-Entered Path : altram.inc +Used in Netlist : yes +File Type : Megafunction +File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/altram.inc +Library : + +File Name with User-Entered Path : altdpram.inc +Used in Netlist : yes +File Type : Megafunction +File Name with Absolute Path : /home/benny/altera/13.1/quartus/libraries/megafunctions/altdpram.inc +Library : + +File Name with User-Entered Path : db/altsyncram_ro91.tdf +Used in Netlist : yes +File Type : Auto-Generated Megafunction +File Name with Absolute Path : /home/benny/work/fpga/projects/db/altsyncram_ro91.tdf +Library : +--------------------------------------------------------------------------------+ @@ -409,28 +485,29 @@ Library : +---------------------------------------------+----------------+ ; Resource ; Usage ; +---------------------------------------------+----------------+ -; Estimated Total logic elements ; 35 ; +; Estimated Total logic elements ; 33 ; ; ; ; -; Total combinational functions ; 28 ; +; Total combinational functions ; 33 ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 0 ; +; -- 4 input functions ; 10 ; ; -- 3 input functions ; 1 ; -; -- <=2 input functions ; 27 ; +; -- <=2 input functions ; 22 ; ; ; ; ; Logic elements by mode ; ; -; -- normal mode ; 2 ; -; -- arithmetic mode ; 26 ; +; -- normal mode ; 13 ; +; -- arithmetic mode ; 20 ; ; ; ; -; Total registers ; 35 ; -; -- Dedicated logic registers ; 35 ; +; Total registers ; 24 ; +; -- Dedicated logic registers ; 24 ; ; -- I/O registers ; 0 ; ; ; ; ; I/O pins ; 9 ; +; Total memory bits ; 64 ; ; Embedded Multiplier 9-bit elements ; 0 ; ; Maximum fan-out node ; CLOCK_50~input ; -; Maximum fan-out ; 35 ; -; Total fan-out ; 141 ; -; Average fan-out ; 1.74 ; +; Maximum fan-out ; 32 ; +; Total fan-out ; 183 ; +; Average fan-out ; 2.20 ; +---------------------------------------------+----------------+ @@ -438,9 +515,9 @@ Library : ; Analysis & Synthesis Resource Utilization by Entity ; +--------------------------------------------------------------------------------+ Compilation Hierarchy Node : |spectrum -LC Combinationals : 28 (28) -LC Registers : 35 (35) -Memory Bits : 0 +LC Combinationals : 33 (33) +LC Registers : 24 (24) +Memory Bits : 64 DSP Elements : 0 DSP 9x9 : 0 DSP 18x18 : 0 @@ -448,19 +525,75 @@ Pins : 9 Virtual Pins : 0 Full Hierarchy Name : |spectrum Library Name : work + +Compilation Hierarchy Node : |rom0:rom| +LC Combinationals : 0 (0) +LC Registers : 0 (0) +Memory Bits : 64 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +Full Hierarchy Name : |spectrum|rom0:rom +Library Name : work + +Compilation Hierarchy Node : |altsyncram:altsyncram_component| +LC Combinationals : 0 (0) +LC Registers : 0 (0) +Memory Bits : 64 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component +Library Name : work + +Compilation Hierarchy Node : |altsyncram_ro91:auto_generated| +LC Combinationals : 0 (0) +LC Registers : 0 (0) +Memory Bits : 64 +DSP Elements : 0 +DSP 9x9 : 0 +DSP 18x18 : 0 +Pins : 0 +Virtual Pins : 0 +Full Hierarchy Name : |spectrum|rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated +Library Name : work +--------------------------------------------------------------------------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. +--------------------------------------------------------------------------------+ -; Registers Removed During Synthesis ; -+---------------------------------------+----------------------------------------+ -; Register name ; Reason for Removal ; -+---------------------------------------+----------------------------------------+ -; LED[7]~reg0 ; Stuck at GND due to stuck port data_in ; -; Total Number of Removed Registers = 1 ; ; -+---------------------------------------+----------------------------------------+ +; Analysis & Synthesis RAM Summary ; ++--------------------------------------------------------------------------------+ +Name : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ALTSYNCRAM +Type : AUTO +Mode : ROM +Port A Depth : 8 +Port A Width : 8 +Port B Depth : -- +Port B Width : -- +Size : 64 +MIF : led_patterns.mif ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Analysis & Synthesis IP Cores Summary ; ++--------------------------------------------------------------------------------+ +Vendor : Altera +IP Core Name : ROM: 1-PORT +Version : 13.1 +Release Date : N/A +License Type : N/A +Entity Instance : |spectrum|rom0:rom +IP Include File : /home/benny/work/fpga/projects/rom0.v ++--------------------------------------------------------------------------------+ + +------------------------------------------------------+ @@ -468,7 +601,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +----------------------------------------------+-------+ ; Statistic ; Value ; +----------------------------------------------+-------+ -; Total registers ; 35 ; +; Total registers ; 24 ; ; Number of registers using Synchronous Clear ; 0 ; ; Number of registers using Synchronous Load ; 0 ; ; Number of registers using Asynchronous Clear ; 0 ; @@ -478,6 +611,252 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +----------------------------------------------+-------+ ++--------------------------------------------------------------------------------+ +; Source assignments for rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated ; ++--------------------------------------------------------------------------------+ +Assignment : OPTIMIZE_POWER_DURING_SYNTHESIS +Value : NORMAL_COMPILATION +From : - +To : - ++--------------------------------------------------------------------------------+ + + + ++--------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: rom0:rom|altsyncram:altsyncram_component ; ++--------------------------------------------------------------------------------+ +Parameter Name : BYTE_SIZE_BLOCK +Value : 8 +Type : Untyped + +Parameter Name : AUTO_CARRY_CHAINS +Value : ON +Type : AUTO_CARRY + +Parameter Name : IGNORE_CARRY_BUFFERS +Value : OFF +Type : IGNORE_CARRY + +Parameter Name : AUTO_CASCADE_CHAINS +Value : ON +Type : AUTO_CASCADE + +Parameter Name : IGNORE_CASCADE_BUFFERS +Value : OFF +Type : IGNORE_CASCADE + +Parameter Name : WIDTH_BYTEENA +Value : 1 +Type : Untyped + +Parameter Name : OPERATION_MODE +Value : ROM +Type : Untyped + +Parameter Name : WIDTH_A +Value : 8 +Type : Signed Integer + +Parameter Name : WIDTHAD_A +Value : 3 +Type : Signed Integer + +Parameter Name : NUMWORDS_A +Value : 8 +Type : Signed Integer + +Parameter Name : OUTDATA_REG_A +Value : CLOCK0 +Type : Untyped + +Parameter Name : ADDRESS_ACLR_A +Value : NONE +Type : Untyped + +Parameter Name : OUTDATA_ACLR_A +Value : NONE +Type : Untyped + +Parameter Name : WRCONTROL_ACLR_A +Value : NONE +Type : Untyped + +Parameter Name : INDATA_ACLR_A +Value : NONE +Type : Untyped + +Parameter Name : BYTEENA_ACLR_A +Value : NONE +Type : Untyped + +Parameter Name : WIDTH_B +Value : 1 +Type : Untyped + +Parameter Name : WIDTHAD_B +Value : 1 +Type : Untyped + +Parameter Name : NUMWORDS_B +Value : 1 +Type : Untyped + +Parameter Name : INDATA_REG_B +Value : CLOCK1 +Type : Untyped + +Parameter Name : WRCONTROL_WRADDRESS_REG_B +Value : CLOCK1 +Type : Untyped + +Parameter Name : RDCONTROL_REG_B +Value : CLOCK1 +Type : Untyped + +Parameter Name : ADDRESS_REG_B +Value : CLOCK1 +Type : Untyped + +Parameter Name : OUTDATA_REG_B +Value : UNREGISTERED +Type : Untyped + +Parameter Name : BYTEENA_REG_B +Value : CLOCK1 +Type : Untyped + +Parameter Name : INDATA_ACLR_B +Value : NONE +Type : Untyped + +Parameter Name : WRCONTROL_ACLR_B +Value : NONE +Type : Untyped + +Parameter Name : ADDRESS_ACLR_B +Value : NONE +Type : Untyped + +Parameter Name : OUTDATA_ACLR_B +Value : NONE +Type : Untyped + +Parameter Name : RDCONTROL_ACLR_B +Value : NONE +Type : Untyped + +Parameter Name : BYTEENA_ACLR_B +Value : NONE +Type : Untyped + +Parameter Name : WIDTH_BYTEENA_A +Value : 1 +Type : Signed Integer + +Parameter Name : WIDTH_BYTEENA_B +Value : 1 +Type : Untyped + +Parameter Name : RAM_BLOCK_TYPE +Value : AUTO +Type : Untyped + +Parameter Name : BYTE_SIZE +Value : 8 +Type : Untyped + +Parameter Name : READ_DURING_WRITE_MODE_MIXED_PORTS +Value : DONT_CARE +Type : Untyped + +Parameter Name : READ_DURING_WRITE_MODE_PORT_A +Value : NEW_DATA_NO_NBE_READ +Type : Untyped + +Parameter Name : READ_DURING_WRITE_MODE_PORT_B +Value : NEW_DATA_NO_NBE_READ +Type : Untyped + +Parameter Name : INIT_FILE +Value : led_patterns.mif +Type : Untyped + +Parameter Name : INIT_FILE_LAYOUT +Value : PORT_A +Type : Untyped + +Parameter Name : MAXIMUM_DEPTH +Value : 0 +Type : Untyped + +Parameter Name : CLOCK_ENABLE_INPUT_A +Value : BYPASS +Type : Untyped + +Parameter Name : CLOCK_ENABLE_INPUT_B +Value : NORMAL +Type : Untyped + +Parameter Name : CLOCK_ENABLE_OUTPUT_A +Value : BYPASS +Type : Untyped + +Parameter Name : CLOCK_ENABLE_OUTPUT_B +Value : NORMAL +Type : Untyped + +Parameter Name : CLOCK_ENABLE_CORE_A +Value : USE_INPUT_CLKEN +Type : Untyped + +Parameter Name : CLOCK_ENABLE_CORE_B +Value : USE_INPUT_CLKEN +Type : Untyped + +Parameter Name : ENABLE_ECC +Value : FALSE +Type : Untyped + +Parameter Name : ECC_PIPELINE_STAGE_ENABLED +Value : FALSE +Type : Untyped + +Parameter Name : WIDTH_ECCSTATUS +Value : 3 +Type : Untyped + +Parameter Name : DEVICE_FAMILY +Value : Cyclone IV E +Type : Untyped + +Parameter Name : CBXI_PARAMETER +Value : altsyncram_ro91 +Type : Untyped ++--------------------------------------------------------------------------------+ + +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------+ +; altsyncram Parameter Settings by Entity Instance ; ++-------------------------------------------+------------------------------------------+ +; Name ; Value ; ++-------------------------------------------+------------------------------------------+ +; Number of entity instances ; 1 ; +; Entity Instance ; rom0:rom|altsyncram:altsyncram_component ; +; -- OPERATION_MODE ; ROM ; +; -- WIDTH_A ; 8 ; +; -- NUMWORDS_A ; 8 ; +; -- OUTDATA_REG_A ; CLOCK0 ; +; -- WIDTH_B ; 1 ; +; -- NUMWORDS_B ; 1 ; +; -- ADDRESS_REG_B ; CLOCK1 ; +; -- OUTDATA_REG_B ; UNREGISTERED ; +; -- RAM_BLOCK_TYPE ; AUTO ; +; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; ++-------------------------------------------+------------------------------------------+ + + +-------------------------------+ ; Elapsed Time Per Partition ; +----------------+--------------+ @@ -493,26 +872,49 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi Info: ******************************************************************* Info: Running Quartus II 32-bit Analysis & Synthesis Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition - Info: Processing started: Wed Mar 30 11:51:28 2022 + Info: Processing started: Wed Mar 30 12:38:26 2022 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum Warning (20028): Parallel compilation is not licensed and has been disabled Info (12021): Found 1 design units, including 1 entities, in source file spectrum.v Info (12023): Found entity 1: spectrum +Info (12021): Found 1 design units, including 1 entities, in source file rom0.v + Info (12023): Found entity 1: rom0 Info (12127): Elaborating entity "spectrum" for the top level hierarchy -Warning (10230): Verilog HDL assignment warning at spectrum.v(10): truncated value with size 32 to match size of target (28) -Warning (13024): Output pins are stuck at VCC or GND - Warning (13410): Pin "LED[7]" is stuck at GND +Warning (10230): Verilog HDL assignment warning at spectrum.v(19): truncated value with size 32 to match size of target (21) +Warning (10230): Verilog HDL assignment warning at spectrum.v(21): truncated value with size 32 to match size of target (3) +Info (12128): Elaborating entity "rom0" for hierarchy "rom0:rom" +Info (12128): Elaborating entity "altsyncram" for hierarchy "rom0:rom|altsyncram:altsyncram_component" +Info (12130): Elaborated megafunction instantiation "rom0:rom|altsyncram:altsyncram_component" +Info (12133): Instantiated megafunction "rom0:rom|altsyncram:altsyncram_component" with the following parameter: + Info (12134): Parameter "address_aclr_a" = "NONE" + Info (12134): Parameter "clock_enable_input_a" = "BYPASS" + Info (12134): Parameter "clock_enable_output_a" = "BYPASS" + Info (12134): Parameter "init_file" = "led_patterns.mif" + Info (12134): Parameter "intended_device_family" = "Cyclone IV E" + Info (12134): Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO" + Info (12134): Parameter "lpm_type" = "altsyncram" + Info (12134): Parameter "numwords_a" = "8" + Info (12134): Parameter "operation_mode" = "ROM" + Info (12134): Parameter "outdata_aclr_a" = "NONE" + Info (12134): Parameter "outdata_reg_a" = "CLOCK0" + Info (12134): Parameter "widthad_a" = "3" + Info (12134): Parameter "width_a" = "8" + Info (12134): Parameter "width_byteena_a" = "1" +Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_ro91.tdf + Info (12023): Found entity 1: altsyncram_ro91 +Info (12128): Elaborating entity "altsyncram_ro91" for hierarchy "rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated" Info (286030): Timing-Driven Synthesis is running Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL -Info (21057): Implemented 44 device resources after synthesis - the final resource count might be different +Info (21057): Implemented 71 device resources after synthesis - the final resource count might be different Info (21058): Implemented 1 input pins Info (21059): Implemented 8 output pins - Info (21061): Implemented 35 logic cells -Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 4 warnings - Info: Peak virtual memory: 388 megabytes - Info: Processing ended: Wed Mar 30 11:51:29 2022 - Info: Elapsed time: 00:00:01 + Info (21061): Implemented 54 logic cells + Info (21064): Implemented 8 RAM segments +Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 3 warnings + Info: Peak virtual memory: 384 megabytes + Info: Processing ended: Wed Mar 30 12:38:28 2022 + Info: Elapsed time: 00:00:02 Info: Total CPU time (on all processors): 00:00:01 diff --git a/output_files/spectrum.map.smsg b/output_files/spectrum.map.smsg new file mode 100644 index 0000000..9ce692e --- /dev/null +++ b/output_files/spectrum.map.smsg @@ -0,0 +1 @@ +Warning (10268): Verilog HDL information at spectrum.v(18): always construct contains both blocking and non-blocking assignments diff --git a/output_files/spectrum.map.summary b/output_files/spectrum.map.summary index 57cbaf7..5783484 100644 --- a/output_files/spectrum.map.summary +++ b/output_files/spectrum.map.summary @@ -1,14 +1,14 @@ -Analysis & Synthesis Status : Successful - Wed Mar 30 11:51:29 2022 +Analysis & Synthesis Status : Successful - Wed Mar 30 12:38:28 2022 Quartus II 32-bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition Revision Name : spectrum Top-level Entity Name : spectrum Family : Cyclone IV E -Total logic elements : 35 - Total combinational functions : 28 - Dedicated logic registers : 35 -Total registers : 35 +Total logic elements : 33 + Total combinational functions : 33 + Dedicated logic registers : 24 +Total registers : 24 Total pins : 9 Total virtual pins : 0 -Total memory bits : 0 +Total memory bits : 64 Embedded Multiplier 9-bit elements : 0 Total PLLs : 0 diff --git a/output_files/spectrum.sof b/output_files/spectrum.sof index 07d3c8b..63061a7 100644 Binary files a/output_files/spectrum.sof and b/output_files/spectrum.sof differ diff --git a/output_files/spectrum.sta.rpt b/output_files/spectrum.sta.rpt index 41c1382..11debb1 100644 --- a/output_files/spectrum.sta.rpt +++ b/output_files/spectrum.sta.rpt @@ -1,5 +1,5 @@ TimeQuest Timing Analyzer report for spectrum -Wed Mar 30 11:51:41 2022 +Wed Mar 30 12:38:40 2022 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition @@ -133,7 +133,7 @@ Targets : { CLOCK_50 } +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Fmax Summary ; +--------------------------------------------------------------------------------+ -Fmax : 383.73 MHz +Fmax : 265.75 MHz Restricted Fmax : 250.0 MHz Clock Name : CLOCK_50 Note : limit due to minimum period restriction (max I/O toggle rate) @@ -152,8 +152,8 @@ HTML report is unavailable in plain text report export. ; Slow 1200mV 85C Model Setup Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 -Slack : -1.606 -End Point TNS : -30.234 +Slack : -2.763 +End Point TNS : -43.394 +--------------------------------------------------------------------------------+ @@ -162,7 +162,7 @@ End Point TNS : -30.234 ; Slow 1200mV 85C Model Hold Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 -Slack : 0.360 +Slack : 0.343 End Point TNS : 0.000 +--------------------------------------------------------------------------------+ @@ -185,7 +185,7 @@ No paths to report. +--------------------------------------------------------------------------------+ Clock : CLOCK_50 Slack : -3.000 -End Point TNS : -38.000 +End Point TNS : -46.633 +--------------------------------------------------------------------------------+ @@ -193,905 +193,905 @@ End Point TNS : -38.000 +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Setup: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ -Slack : -1.606 -From Node : counter[2] -To Node : counter[27] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.889 - -Slack : -1.525 +Slack : -2.763 From Node : counter[1] -To Node : counter[27] +To Node : address[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.808 +Clock Skew : 0.289 +Data Delay : 4.047 -Slack : -1.523 +Slack : -2.682 From Node : counter[0] -To Node : counter[27] +To Node : address[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.806 +Clock Skew : 0.289 +Data Delay : 3.966 -Slack : -1.490 -From Node : counter[2] -To Node : counter[25] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.773 - -Slack : -1.488 -From Node : counter[0] -To Node : counter[26] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.771 - -Slack : -1.488 -From Node : counter[4] -To Node : counter[27] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.771 - -Slack : -1.485 +Slack : -2.665 From Node : counter[1] -To Node : counter[26] +To Node : address[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.768 +Clock Skew : 0.289 +Data Delay : 3.949 -Slack : -1.484 -From Node : counter[2] -To Node : counter[26] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.767 - -Slack : -1.411 -From Node : counter[3] -To Node : counter[27] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.694 - -Slack : -1.409 -From Node : counter[1] -To Node : counter[25] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.692 - -Slack : -1.407 -From Node : counter[0] -To Node : counter[25] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.690 - -Slack : -1.376 -From Node : counter[6] -To Node : counter[27] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.659 - -Slack : -1.374 -From Node : counter[2] -To Node : counter[23] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.657 - -Slack : -1.372 -From Node : counter[0] -To Node : counter[24] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.655 - -Slack : -1.372 -From Node : counter[4] -To Node : counter[25] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.655 - -Slack : -1.370 -From Node : counter[3] -To Node : counter[26] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.653 - -Slack : -1.369 -From Node : counter[1] -To Node : counter[24] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.652 - -Slack : -1.368 -From Node : counter[2] -To Node : counter[24] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.651 - -Slack : -1.366 -From Node : counter[4] -To Node : counter[26] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.649 - -Slack : -1.295 -From Node : counter[3] -To Node : counter[25] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.578 - -Slack : -1.293 +Slack : -2.659 From Node : counter[5] -To Node : counter[27] +To Node : address[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.576 +Clock Skew : 0.289 +Data Delay : 3.943 -Slack : -1.293 -From Node : counter[1] -To Node : counter[23] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.576 - -Slack : -1.291 -From Node : counter[0] -To Node : counter[23] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.574 - -Slack : -1.261 -From Node : counter[2] -To Node : counter[15] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.193 - -Slack : -1.260 -From Node : counter[8] -To Node : counter[27] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.543 - -Slack : -1.260 -From Node : counter[6] -To Node : counter[25] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.543 - -Slack : -1.259 -From Node : counter[0] -To Node : counter[16] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.191 - -Slack : -1.258 -From Node : counter[2] -To Node : counter[21] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.541 - -Slack : -1.257 -From Node : counter[5] -To Node : counter[26] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.540 - -Slack : -1.256 -From Node : counter[0] -To Node : counter[22] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.539 - -Slack : -1.256 -From Node : counter[4] -To Node : counter[23] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.539 - -Slack : -1.256 -From Node : counter[1] -To Node : counter[16] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.188 - -Slack : -1.255 -From Node : counter[2] -To Node : counter[16] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.187 - -Slack : -1.254 -From Node : counter[6] -To Node : counter[26] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.537 - -Slack : -1.254 +Slack : -2.647 From Node : counter[3] -To Node : counter[24] +To Node : address[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.537 +Clock Skew : 0.289 +Data Delay : 3.931 -Slack : -1.253 -From Node : counter[1] -To Node : counter[22] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.536 - -Slack : -1.252 -From Node : counter[2] -To Node : counter[22] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.535 - -Slack : -1.250 -From Node : counter[4] -To Node : counter[24] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.533 - -Slack : -1.194 -From Node : counter[13] -To Node : counter[27] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.077 -Data Delay : 2.112 - -Slack : -1.180 -From Node : counter[1] -To Node : counter[15] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.112 - -Slack : -1.179 -From Node : counter[3] -To Node : counter[23] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.462 - -Slack : -1.178 +Slack : -2.584 From Node : counter[0] -To Node : counter[15] +To Node : address[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.110 +Clock Skew : 0.289 +Data Delay : 3.868 -Slack : -1.177 +Slack : -2.578 +From Node : counter[4] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 3.862 + +Slack : -2.564 +From Node : counter[2] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 3.848 + +Slack : -2.541 From Node : counter[7] -To Node : counter[27] +To Node : address[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.460 +Clock Skew : 0.289 +Data Delay : 3.825 -Slack : -1.177 +Slack : -2.502 From Node : counter[5] -To Node : counter[25] +To Node : address[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.460 +Clock Skew : 0.289 +Data Delay : 3.786 -Slack : -1.177 -From Node : counter[1] -To Node : counter[21] +Slack : -2.490 +From Node : counter[3] +To Node : address[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.460 +Clock Skew : 0.289 +Data Delay : 3.774 -Slack : -1.175 -From Node : counter[0] -To Node : counter[21] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.458 - -Slack : -1.154 -From Node : counter[13] -To Node : counter[26] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.077 -Data Delay : 2.072 - -Slack : -1.144 -From Node : counter[8] -To Node : counter[25] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.427 - -Slack : -1.144 +Slack : -2.462 From Node : counter[6] -To Node : counter[23] +To Node : address[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.427 +Clock Skew : 0.289 +Data Delay : 3.746 -Slack : -1.143 -From Node : counter[0] -To Node : counter[14] +Slack : -2.426 +From Node : counter[1] +To Node : address[0] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.075 +Clock Skew : 0.289 +Data Delay : 3.710 -Slack : -1.143 +Slack : -2.421 From Node : counter[4] -To Node : counter[15] +To Node : address[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.075 +Clock Skew : 0.289 +Data Delay : 3.705 -Slack : -1.142 +Slack : -2.407 From Node : counter[2] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 3.691 + +Slack : -2.384 +From Node : counter[7] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 3.668 + +Slack : -2.345 +From Node : counter[0] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 3.629 + +Slack : -2.322 +From Node : counter[5] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 3.606 + +Slack : -2.311 +From Node : counter[11] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 3.595 + +Slack : -2.310 +From Node : counter[3] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 3.594 + +Slack : -2.305 +From Node : counter[6] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 3.589 + +Slack : -2.293 +From Node : counter[9] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 3.577 + +Slack : -2.241 +From Node : counter[4] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 3.525 + +Slack : -2.227 +From Node : counter[2] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 3.511 + +Slack : -2.214 +From Node : counter[8] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 3.498 + +Slack : -2.204 +From Node : counter[7] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 3.488 + +Slack : -2.194 +From Node : counter[13] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 3.478 + +Slack : -2.125 +From Node : counter[6] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 3.409 + +Slack : -2.111 +From Node : counter[12] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 3.395 + +Slack : -2.097 +From Node : counter[10] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 3.381 + +Slack : -2.079 +From Node : counter[15] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 3.363 + +Slack : -1.998 +From Node : counter[14] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 3.282 + +Slack : -1.990 +From Node : counter[8] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 3.274 + +Slack : -1.987 +From Node : counter[11] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 3.271 + +Slack : -1.974 +From Node : counter[11] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 3.258 + +Slack : -1.969 +From Node : counter[9] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 3.253 + +Slack : -1.959 +From Node : counter[17] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 3.243 + +Slack : -1.956 +From Node : counter[9] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 3.240 + +Slack : -1.882 +From Node : counter[16] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 3.166 + +Slack : -1.877 +From Node : counter[8] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 3.161 + +Slack : -1.873 +From Node : counter[10] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 3.157 + +Slack : -1.870 +From Node : counter[13] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 3.154 + +Slack : -1.857 +From Node : counter[13] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 3.141 + +Slack : -1.830 +From Node : counter[12] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 3.114 + +Slack : -1.774 +From Node : counter[12] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 3.058 + +Slack : -1.760 +From Node : counter[10] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 3.044 + +Slack : -1.756 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.069 +Data Delay : 2.616 + +Slack : -1.756 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.069 +Data Delay : 2.616 + +Slack : -1.756 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.069 +Data Delay : 2.616 + +Slack : -1.756 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.069 +Data Delay : 2.616 + +Slack : -1.756 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.069 +Data Delay : 2.616 + +Slack : -1.756 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.069 +Data Delay : 2.616 + +Slack : -1.756 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.069 +Data Delay : 2.616 + +Slack : -1.756 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.069 +Data Delay : 2.616 + +Slack : -1.755 +From Node : counter[15] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 3.039 + +Slack : -1.742 +From Node : counter[15] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 3.026 + +Slack : -1.678 +From Node : counter[14] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 2.962 + +Slack : -1.661 +From Node : counter[14] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 2.945 + +Slack : -1.635 +From Node : counter[17] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 2.919 + +Slack : -1.622 +From Node : counter[17] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 2.906 + +Slack : -1.609 +From Node : counter[1] +To Node : counter[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.062 +Data Delay : 2.542 + +Slack : -1.581 +From Node : counter[18] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 2.865 + +Slack : -1.566 +From Node : counter[16] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 2.850 + +Slack : -1.545 +From Node : counter[16] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 2.829 + +Slack : -1.528 +From Node : counter[0] +To Node : counter[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.062 +Data Delay : 2.461 + +Slack : -1.521 +From Node : counter[19] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 2.805 + +Slack : -1.505 +From Node : counter[5] +To Node : counter[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.062 +Data Delay : 2.438 + +Slack : -1.493 +From Node : counter[1] +To Node : counter[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.062 +Data Delay : 2.426 + +Slack : -1.493 +From Node : counter[3] +To Node : counter[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.062 +Data Delay : 2.426 + +Slack : -1.487 +From Node : counter[0] To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.425 - -Slack : -1.142 -From Node : counter[10] -To Node : counter[27] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.425 - -Slack : -1.141 -From Node : counter[7] -To Node : counter[26] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.424 - -Slack : -1.141 -From Node : counter[5] -To Node : counter[24] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.424 - -Slack : -1.141 -From Node : counter[3] -To Node : counter[16] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.073 - -Slack : -1.140 -From Node : counter[0] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.423 - -Slack : -1.140 -From Node : counter[4] -To Node : counter[21] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.423 - -Slack : -1.140 -From Node : counter[1] -To Node : counter[14] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.072 - -Slack : -1.139 -From Node : counter[2] -To Node : counter[14] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.071 - -Slack : -1.138 -From Node : counter[8] -To Node : counter[26] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.421 - -Slack : -1.138 -From Node : counter[6] -To Node : counter[24] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.421 - -Slack : -1.138 -From Node : counter[3] -To Node : counter[22] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.421 - -Slack : -1.137 -From Node : counter[4] -To Node : counter[16] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 2.069 - -Slack : -1.137 -From Node : counter[1] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 +Clock Skew : -0.062 Data Delay : 2.420 -Slack : -1.136 -From Node : counter[2] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.419 - -Slack : -1.134 -From Node : counter[4] -To Node : counter[22] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.417 - -Slack : -1.078 -From Node : counter[13] -To Node : counter[25] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.077 -Data Delay : 1.996 - -Slack : -1.066 -From Node : counter[3] -To Node : counter[15] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 1.998 - -Slack : -1.063 -From Node : counter[3] -To Node : counter[21] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.346 - -Slack : -1.062 -From Node : counter[9] -To Node : counter[27] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.345 - -Slack : -1.061 -From Node : counter[7] -To Node : counter[25] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.344 - -Slack : -1.061 -From Node : counter[5] -To Node : counter[23] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.344 - -Slack : -1.061 +Slack : -1.487 From Node : counter[1] To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.344 +Clock Skew : -0.062 +Data Delay : 2.420 -Slack : -1.059 +Slack : -1.475 +From Node : counter[19] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 2.759 + +Slack : -1.442 +From Node : counter[18] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 2.726 + +Slack : -1.424 +From Node : counter[4] +To Node : counter[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.062 +Data Delay : 2.357 + +Slack : -1.412 From Node : counter[0] +To Node : counter[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.062 +Data Delay : 2.345 + +Slack : -1.410 +From Node : counter[2] +To Node : counter[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.062 +Data Delay : 2.343 + +Slack : -1.398 +From Node : counter[4] To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.342 +Clock Skew : -0.062 +Data Delay : 2.331 -Slack : -1.044 -From Node : counter[18] -To Node : counter[27] +Slack : -1.389 +From Node : counter[5] +To Node : counter[18] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.077 -Data Delay : 1.962 +Clock Skew : -0.062 +Data Delay : 2.322 -Slack : -1.038 -From Node : counter[13] -To Node : counter[24] +Slack : -1.387 +From Node : counter[7] +To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.077 -Data Delay : 1.956 +Clock Skew : -0.062 +Data Delay : 2.320 -Slack : -1.031 -From Node : counter[6] -To Node : counter[15] +Slack : -1.383 +From Node : counter[5] +To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 1.963 +Clock Skew : -0.062 +Data Delay : 2.316 -Slack : -1.029 +Slack : -1.377 +From Node : counter[1] +To Node : counter[16] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.062 +Data Delay : 2.310 + +Slack : -1.377 +From Node : counter[3] +To Node : counter[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.062 +Data Delay : 2.310 + +Slack : -1.375 From Node : counter[2] -To Node : counter[11] +To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 1.961 +Clock Skew : -0.062 +Data Delay : 2.308 -Slack : -1.028 -From Node : counter[8] -To Node : counter[23] +Slack : -1.371 +From Node : counter[0] +To Node : counter[17] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.311 +Clock Skew : -0.062 +Data Delay : 2.304 -Slack : -1.028 +Slack : -1.371 +From Node : counter[1] +To Node : counter[17] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.062 +Data Delay : 2.304 + +Slack : -1.371 +From Node : counter[3] +To Node : counter[19] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.062 +Data Delay : 2.304 + +Slack : -1.308 +From Node : counter[6] +To Node : counter[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.062 +Data Delay : 2.241 + +Slack : -1.308 +From Node : counter[4] +To Node : counter[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.062 +Data Delay : 2.241 + +Slack : -1.296 +From Node : counter[0] +To Node : counter[16] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.062 +Data Delay : 2.229 + +Slack : -1.294 +From Node : counter[2] +To Node : counter[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.062 +Data Delay : 2.227 + +Slack : -1.282 +From Node : counter[6] +To Node : counter[19] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.062 +Data Delay : 2.215 + +Slack : -1.282 +From Node : counter[4] +To Node : counter[17] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.062 +Data Delay : 2.215 + +Slack : -1.278 +From Node : counter[19] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.289 +Data Delay : 2.562 + +Slack : -1.273 From Node : counter[5] To Node : counter[16] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 1.960 +Clock Skew : -0.062 +Data Delay : 2.206 -Slack : -1.028 -From Node : counter[6] -To Node : counter[21] +Slack : -1.271 +From Node : counter[7] +To Node : counter[18] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.311 +Clock Skew : -0.062 +Data Delay : 2.204 -Slack : -1.027 -From Node : counter[0] -To Node : counter[12] +Slack : -1.267 +From Node : counter[5] +To Node : counter[17] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 1.959 +Clock Skew : -0.062 +Data Delay : 2.200 -Slack : -1.026 +Slack : -1.265 +From Node : counter[7] +To Node : counter[19] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.062 +Data Delay : 2.198 + +Slack : -1.261 +From Node : counter[1] +To Node : counter[14] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.062 +Data Delay : 2.194 + +Slack : -1.261 +From Node : counter[3] +To Node : counter[16] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.062 +Data Delay : 2.194 + +Slack : -1.259 From Node : counter[2] To Node : counter[17] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.309 - -Slack : -1.026 -From Node : counter[12] -To Node : counter[27] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.309 - -Slack : -1.026 -From Node : counter[10] -To Node : counter[25] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.309 - -Slack : -1.025 -From Node : counter[7] -To Node : counter[24] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.308 - -Slack : -1.025 -From Node : counter[5] -To Node : counter[22] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.308 - -Slack : -1.025 -From Node : counter[6] -To Node : counter[16] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 1.957 - -Slack : -1.025 -From Node : counter[3] -To Node : counter[14] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 1.957 - -Slack : -1.024 -From Node : counter[0] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.307 - -Slack : -1.024 -From Node : counter[4] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.307 - -Slack : -1.024 -From Node : counter[1] -To Node : counter[12] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 1.956 - -Slack : -1.023 -From Node : counter[2] -To Node : counter[12] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 1.955 - -Slack : -1.022 -From Node : counter[9] -To Node : counter[26] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.305 - -Slack : -1.022 -From Node : counter[8] -To Node : counter[24] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.305 - -Slack : -1.022 -From Node : counter[6] -To Node : counter[22] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.305 - -Slack : -1.022 -From Node : counter[3] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.305 - -Slack : -1.021 -From Node : counter[4] -To Node : counter[14] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.063 -Data Delay : 1.953 - -Slack : -1.021 -From Node : counter[1] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.288 -Data Delay : 2.304 +Clock Skew : -0.062 +Data Delay : 2.192 +--------------------------------------------------------------------------------+ @@ -1099,905 +1099,905 @@ Data Delay : 2.304 +--------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Hold: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ -Slack : 0.360 -From Node : counter[0] -To Node : counter[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.580 - -Slack : 0.458 -From Node : counter[12] -To Node : counter[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.043 - -Slack : 0.459 -From Node : counter[16] -To Node : counter[17] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.044 - -Slack : 0.473 -From Node : counter[11] -To Node : counter[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.058 - -Slack : 0.475 -From Node : counter[15] -To Node : counter[17] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.060 - -Slack : 0.534 -From Node : counter[13] -To Node : counter[13] +Slack : 0.343 +From Node : address[2] +To Node : address[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.077 -Data Delay : 0.768 +Data Delay : 0.577 -Slack : 0.535 +Slack : 0.343 +From Node : address[1] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 0.577 + +Slack : 0.343 +From Node : address[0] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 0.577 + +Slack : 0.370 From Node : counter[20] To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 0.769 +Clock Skew : 0.062 +Data Delay : 0.589 -Slack : 0.535 -From Node : counter[17] -To Node : counter[17] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 0.769 - -Slack : 0.536 -From Node : counter[19] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 0.770 - -Slack : 0.537 -From Node : counter[18] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 0.771 - -Slack : 0.548 -From Node : counter[11] -To Node : counter[11] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.768 - -Slack : 0.548 -From Node : counter[4] -To Node : counter[4] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.768 - -Slack : 0.549 -From Node : counter[12] -To Node : counter[12] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.769 - -Slack : 0.549 +Slack : 0.547 From Node : counter[9] To Node : counter[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.769 +Clock Skew : 0.062 +Data Delay : 0.766 -Slack : 0.549 +Slack : 0.551 +From Node : counter[10] +To Node : counter[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.770 + +Slack : 0.551 +From Node : counter[8] +To Node : counter[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.770 + +Slack : 0.551 From Node : counter[3] To Node : counter[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.769 +Clock Skew : 0.062 +Data Delay : 0.770 -Slack : 0.550 +Slack : 0.551 +From Node : counter[1] +To Node : counter[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.770 + +Slack : 0.553 +From Node : counter[2] +To Node : counter[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.772 + +Slack : 0.568 +From Node : counter[0] +To Node : counter[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.787 + +Slack : 0.681 From Node : counter[14] To Node : counter[14] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.769 +Data Delay : 0.900 -Slack : 0.550 -From Node : counter[10] -To Node : counter[10] +Slack : 0.683 +From Node : counter[19] +To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.770 +Clock Skew : 0.062 +Data Delay : 0.902 -Slack : 0.550 -From Node : counter[2] -To Node : counter[2] +Slack : 0.684 +From Node : counter[7] +To Node : counter[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.770 +Clock Skew : 0.062 +Data Delay : 0.903 -Slack : 0.551 +Slack : 0.684 +From Node : counter[5] +To Node : counter[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.903 + +Slack : 0.685 From Node : counter[16] To Node : counter[16] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.770 +Data Delay : 0.904 -Slack : 0.551 -From Node : counter[8] -To Node : counter[8] +Slack : 0.686 +From Node : counter[18] +To Node : counter[18] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.771 +Clock Skew : 0.062 +Data Delay : 0.905 -Slack : 0.551 +Slack : 0.686 +From Node : address[1] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 0.920 + +Slack : 0.687 +From Node : counter[17] +To Node : counter[17] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.906 + +Slack : 0.687 +From Node : counter[12] +To Node : counter[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.906 + +Slack : 0.687 From Node : counter[6] To Node : counter[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.771 +Clock Skew : 0.062 +Data Delay : 0.906 -Slack : 0.552 +Slack : 0.687 +From Node : counter[4] +To Node : counter[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 0.906 + +Slack : 0.690 From Node : counter[15] To Node : counter[15] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 0.771 +Data Delay : 0.909 -Slack : 0.553 -From Node : counter[7] -To Node : counter[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.773 - -Slack : 0.553 -From Node : counter[5] -To Node : counter[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.773 - -Slack : 0.556 -From Node : counter[27] -To Node : counter[27] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 0.790 - -Slack : 0.556 -From Node : counter[25] -To Node : counter[25] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 0.790 - -Slack : 0.557 -From Node : counter[26] -To Node : counter[26] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 0.791 - -Slack : 0.558 -From Node : counter[24] -To Node : counter[24] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 0.792 - -Slack : 0.558 -From Node : counter[22] -To Node : counter[22] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 0.792 - -Slack : 0.559 -From Node : counter[23] -To Node : counter[23] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 0.793 - -Slack : 0.559 -From Node : counter[21] -To Node : counter[21] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 0.793 - -Slack : 0.560 -From Node : counter[0] -To Node : counter[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.780 - -Slack : 0.562 -From Node : counter[1] -To Node : counter[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 0.782 - -Slack : 0.569 -From Node : counter[16] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.154 - -Slack : 0.570 -From Node : counter[14] -To Node : counter[17] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.155 - -Slack : 0.571 -From Node : counter[10] +Slack : 0.690 +From Node : counter[13] To Node : counter[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.156 +Clock Skew : 0.062 +Data Delay : 0.909 -Slack : 0.571 -From Node : counter[16] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.156 - -Slack : 0.585 -From Node : counter[15] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.170 - -Slack : 0.586 -From Node : counter[9] -To Node : counter[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.171 - -Slack : 0.587 -From Node : counter[15] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.172 - -Slack : 0.680 -From Node : counter[14] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.265 - -Slack : 0.681 -From Node : counter[16] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.266 - -Slack : 0.682 -From Node : counter[12] -To Node : counter[17] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.267 - -Slack : 0.682 -From Node : counter[14] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.267 - -Slack : 0.683 -From Node : counter[16] -To Node : counter[21] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.268 - -Slack : 0.684 -From Node : counter[8] -To Node : counter[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.269 - -Slack : 0.697 -From Node : counter[15] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.282 - -Slack : 0.697 +Slack : 0.691 From Node : counter[11] -To Node : counter[17] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.282 - -Slack : 0.699 -From Node : counter[15] -To Node : counter[21] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.284 - -Slack : 0.701 -From Node : counter[7] -To Node : counter[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.286 - -Slack : 0.792 -From Node : counter[12] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.377 - -Slack : 0.792 -From Node : counter[14] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.377 - -Slack : 0.793 -From Node : counter[16] -To Node : counter[22] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.378 - -Slack : 0.794 -From Node : counter[12] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.379 - -Slack : 0.794 -From Node : counter[14] -To Node : counter[21] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.379 - -Slack : 0.795 -From Node : counter[16] -To Node : counter[23] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.380 - -Slack : 0.795 -From Node : counter[10] -To Node : counter[17] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.380 - -Slack : 0.796 -From Node : counter[6] -To Node : counter[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.381 - -Slack : 0.807 -From Node : counter[11] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.392 - -Slack : 0.809 -From Node : counter[15] -To Node : counter[22] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.394 - -Slack : 0.809 -From Node : counter[11] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.394 - -Slack : 0.810 -From Node : counter[20] -To Node : counter[21] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 1.044 - -Slack : 0.810 -From Node : counter[9] -To Node : counter[17] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.395 - -Slack : 0.811 -From Node : counter[18] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 1.045 - -Slack : 0.811 -From Node : counter[15] -To Node : counter[23] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.396 - -Slack : 0.813 -From Node : counter[5] -To Node : counter[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.428 -Data Delay : 1.398 - -Slack : 0.823 -From Node : counter[4] -To Node : counter[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.043 - -Slack : 0.823 -From Node : counter[17] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 1.057 - -Slack : 0.824 -From Node : counter[10] To Node : counter[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.044 +Clock Skew : 0.062 +Data Delay : 0.910 -Slack : 0.824 -From Node : counter[2] -To Node : counter[3] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.044 - -Slack : 0.824 -From Node : counter[14] -To Node : counter[15] +Slack : 0.822 +From Node : counter[9] +To Node : counter[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 1.043 - -Slack : 0.824 -From Node : counter[19] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 1.058 +Data Delay : 1.041 Slack : 0.825 -From Node : counter[8] -To Node : counter[9] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.045 - -Slack : 0.825 -From Node : counter[6] -To Node : counter[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.045 - -Slack : 0.825 -From Node : counter[17] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 1.059 - -Slack : 0.826 -From Node : counter[19] -To Node : counter[21] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 1.060 - -Slack : 0.831 -From Node : counter[26] -To Node : counter[27] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 1.065 - -Slack : 0.832 -From Node : counter[24] -To Node : counter[25] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 1.066 - -Slack : 0.832 -From Node : counter[22] -To Node : counter[23] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 1.066 - -Slack : 0.836 -From Node : counter[11] -To Node : counter[12] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.056 - -Slack : 0.836 From Node : counter[1] To Node : counter[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.056 +Clock Skew : 0.062 +Data Delay : 1.044 -Slack : 0.837 +Slack : 0.825 From Node : counter[3] To Node : counter[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.057 +Clock Skew : 0.062 +Data Delay : 1.044 -Slack : 0.837 -From Node : counter[9] -To Node : counter[10] +Slack : 0.838 +From Node : counter[8] +To Node : counter[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.063 +Clock Skew : 0.062 Data Delay : 1.057 Slack : 0.838 -From Node : counter[1] +From Node : counter[0] +To Node : counter[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.057 + +Slack : 0.838 +From Node : counter[10] +To Node : counter[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.057 + +Slack : 0.840 +From Node : counter[2] To Node : counter[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.058 +Clock Skew : 0.062 +Data Delay : 1.059 -Slack : 0.838 +Slack : 0.840 +From Node : counter[10] +To Node : counter[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.059 + +Slack : 0.840 +From Node : counter[8] +To Node : counter[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.059 + +Slack : 0.840 From Node : counter[0] To Node : counter[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.058 +Clock Skew : 0.062 +Data Delay : 1.059 -Slack : 0.839 +Slack : 0.842 +From Node : counter[2] +To Node : counter[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.061 + +Slack : 0.861 +From Node : counter[20] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.428 +Data Delay : 1.446 + +Slack : 0.871 +From Node : address[0] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.077 +Data Delay : 1.105 + +Slack : 0.932 +From Node : counter[9] +To Node : counter[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.151 + +Slack : 0.934 +From Node : counter[9] +To Node : counter[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.153 + +Slack : 0.935 +From Node : counter[3] +To Node : counter[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.154 + +Slack : 0.935 +From Node : counter[1] +To Node : counter[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.154 + +Slack : 0.937 +From Node : counter[3] +To Node : counter[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.156 + +Slack : 0.937 +From Node : counter[1] +To Node : counter[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.156 + +Slack : 0.950 +From Node : counter[10] +To Node : counter[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.169 + +Slack : 0.950 +From Node : counter[8] +To Node : counter[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.169 + +Slack : 0.950 +From Node : counter[0] +To Node : counter[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.169 + +Slack : 0.952 +From Node : counter[10] +To Node : counter[14] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.171 + +Slack : 0.952 +From Node : counter[8] +To Node : counter[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.171 + +Slack : 0.952 +From Node : counter[2] +To Node : counter[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.171 + +Slack : 0.952 +From Node : counter[0] +To Node : counter[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.171 + +Slack : 0.954 +From Node : counter[2] +To Node : counter[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.173 + +Slack : 0.958 +From Node : counter[19] +To Node : counter[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.177 + +Slack : 0.958 +From Node : counter[7] +To Node : counter[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.177 + +Slack : 0.958 +From Node : counter[5] +To Node : counter[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.177 + +Slack : 0.962 +From Node : counter[17] +To Node : counter[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.181 + +Slack : 0.964 From Node : counter[15] To Node : counter[16] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.062 -Data Delay : 1.058 +Data Delay : 1.183 -Slack : 0.839 -From Node : counter[3] +Slack : 0.964 +From Node : counter[13] +To Node : counter[14] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.183 + +Slack : 0.965 +From Node : counter[11] +To Node : counter[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.184 + +Slack : 0.969 +From Node : counter[14] +To Node : counter[15] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.188 + +Slack : 0.971 +From Node : counter[14] +To Node : counter[16] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.190 + +Slack : 0.972 +From Node : counter[16] +To Node : counter[17] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.191 + +Slack : 0.974 +From Node : counter[18] +To Node : counter[19] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.193 + +Slack : 0.974 +From Node : counter[12] +To Node : counter[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.193 + +Slack : 0.974 +From Node : counter[16] +To Node : counter[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.193 + +Slack : 0.975 +From Node : counter[6] +To Node : counter[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.194 + +Slack : 0.975 +From Node : counter[4] To Node : counter[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.059 +Clock Skew : 0.062 +Data Delay : 1.194 -Slack : 0.839 -From Node : counter[9] -To Node : counter[11] +Slack : 0.976 +From Node : counter[12] +To Node : counter[14] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.059 +Clock Skew : 0.062 +Data Delay : 1.195 -Slack : 0.840 -From Node : counter[7] -To Node : counter[8] +Slack : 0.976 +From Node : counter[18] +To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.060 +Clock Skew : 0.062 +Data Delay : 1.195 -Slack : 0.840 -From Node : counter[5] +Slack : 0.977 +From Node : counter[4] To Node : counter[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.060 +Clock Skew : 0.062 +Data Delay : 1.196 -Slack : 0.840 -From Node : counter[0] -To Node : counter[3] +Slack : 0.977 +From Node : counter[6] +To Node : counter[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.060 +Clock Skew : 0.062 +Data Delay : 1.196 -Slack : 0.842 +Slack : 1.044 +From Node : counter[9] +To Node : counter[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.263 + +Slack : 1.046 +From Node : counter[9] +To Node : counter[14] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.265 + +Slack : 1.047 +From Node : counter[1] +To Node : counter[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.266 + +Slack : 1.047 +From Node : counter[3] +To Node : counter[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.266 + +Slack : 1.049 +From Node : counter[1] +To Node : counter[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.268 + +Slack : 1.049 +From Node : counter[3] +To Node : counter[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.268 + +Slack : 1.053 +From Node : counter[19] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.428 +Data Delay : 1.638 + +Slack : 1.058 +From Node : counter[20] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.428 +Data Delay : 1.643 + +Slack : 1.062 +From Node : counter[10] +To Node : counter[15] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.281 + +Slack : 1.062 +From Node : counter[8] +To Node : counter[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.281 + +Slack : 1.062 +From Node : counter[0] +To Node : counter[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.281 + +Slack : 1.064 +From Node : counter[10] +To Node : counter[16] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.283 + +Slack : 1.064 +From Node : counter[8] +To Node : counter[14] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.283 + +Slack : 1.064 +From Node : counter[2] +To Node : counter[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.283 + +Slack : 1.064 +From Node : counter[0] +To Node : counter[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.283 + +Slack : 1.066 +From Node : counter[2] +To Node : counter[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.285 + +Slack : 1.068 From Node : counter[7] To Node : counter[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.062 +Clock Skew : 0.062 +Data Delay : 1.287 -Slack : 0.842 +Slack : 1.068 From Node : counter[5] To Node : counter[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.063 -Data Delay : 1.062 +Clock Skew : 0.062 +Data Delay : 1.287 -Slack : 0.844 -From Node : counter[25] -To Node : counter[26] +Slack : 1.070 +From Node : counter[7] +To Node : counter[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 1.078 +Clock Skew : 0.062 +Data Delay : 1.289 -Slack : 0.846 -From Node : counter[23] -To Node : counter[24] +Slack : 1.070 +From Node : counter[5] +To Node : counter[8] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 1.080 +Clock Skew : 0.062 +Data Delay : 1.289 -Slack : 0.846 -From Node : counter[21] -To Node : counter[22] +Slack : 1.072 +From Node : counter[17] +To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 1.080 +Clock Skew : 0.062 +Data Delay : 1.291 -Slack : 0.846 -From Node : counter[25] -To Node : counter[27] +Slack : 1.074 +From Node : counter[15] +To Node : counter[17] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 1.080 +Clock Skew : 0.062 +Data Delay : 1.293 -Slack : 0.848 -From Node : counter[21] -To Node : counter[23] +Slack : 1.074 +From Node : counter[17] +To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 1.082 +Clock Skew : 0.062 +Data Delay : 1.293 -Slack : 0.848 -From Node : counter[23] -To Node : counter[25] +Slack : 1.074 +From Node : counter[13] +To Node : counter[15] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.077 -Data Delay : 1.082 +Clock Skew : 0.062 +Data Delay : 1.293 -Slack : 0.897 -From Node : counter[24] -To Node : LED[3]~reg0 +Slack : 1.075 +From Node : counter[11] +To Node : counter[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : -0.288 -Data Delay : 0.766 +Clock Skew : 0.062 +Data Delay : 1.294 + +Slack : 1.076 +From Node : counter[15] +To Node : counter[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.295 + +Slack : 1.076 +From Node : counter[13] +To Node : counter[16] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.295 + +Slack : 1.077 +From Node : counter[11] +To Node : counter[14] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.296 + +Slack : 1.081 +From Node : counter[14] +To Node : counter[17] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.062 +Data Delay : 1.300 +--------------------------------------------------------------------------------+ @@ -2013,13 +2013,77 @@ Clock : CLOCK_50 Clock Edge : Rise Target : CLOCK_50 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : LED[0]~reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[0] + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[1] + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[2] + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[3] + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[4] + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[5] + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[6] + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[7] + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 Slack : -1.000 Actual Width : 1.000 @@ -2027,7 +2091,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : LED[1]~reg0 +Target : address[0] Slack : -1.000 Actual Width : 1.000 @@ -2035,7 +2099,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : LED[2]~reg0 +Target : address[1] Slack : -1.000 Actual Width : 1.000 @@ -2043,31 +2107,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : LED[3]~reg0 - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : LED[4]~reg0 - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : LED[5]~reg0 - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : LED[6]~reg0 +Target : address[2] Slack : -1.000 Actual Width : 1.000 @@ -2173,62 +2213,6 @@ Clock : CLOCK_50 Clock Edge : Rise Target : counter[20] -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[21] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[22] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[23] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[24] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[25] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[26] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[27] - Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 @@ -2293,102 +2277,142 @@ Clock : CLOCK_50 Clock Edge : Rise Target : counter[9] +Slack : -0.011 +Actual Width : 0.219 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 + +Slack : -0.007 +Actual Width : 0.223 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[0] + +Slack : -0.007 +Actual Width : 0.223 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[1] + +Slack : -0.007 +Actual Width : 0.223 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[2] + +Slack : -0.007 +Actual Width : 0.223 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[3] + +Slack : -0.007 +Actual Width : 0.223 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[4] + +Slack : -0.007 +Actual Width : 0.223 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[5] + +Slack : -0.007 +Actual Width : 0.223 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[6] + +Slack : -0.007 +Actual Width : 0.223 +Required Width : 0.230 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[7] + Slack : 0.088 Actual Width : 0.272 Required Width : 0.184 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise +Target : address[0] + +Slack : 0.088 +Actual Width : 0.272 +Required Width : 0.184 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : address[1] + +Slack : 0.088 +Actual Width : 0.272 +Required Width : 0.184 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : address[2] + +Slack : 0.097 +Actual Width : 0.281 +Required Width : 0.184 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[0] + +Slack : 0.097 +Actual Width : 0.281 +Required Width : 0.184 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[10] + +Slack : 0.097 +Actual Width : 0.281 +Required Width : 0.184 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[11] + +Slack : 0.097 +Actual Width : 0.281 +Required Width : 0.184 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[12] + +Slack : 0.097 +Actual Width : 0.281 +Required Width : 0.184 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise Target : counter[13] -Slack : 0.088 -Actual Width : 0.272 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[17] - -Slack : 0.088 -Actual Width : 0.272 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[18] - -Slack : 0.088 -Actual Width : 0.272 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[19] - -Slack : 0.088 -Actual Width : 0.272 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[20] - -Slack : 0.088 -Actual Width : 0.272 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[21] - -Slack : 0.088 -Actual Width : 0.272 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[22] - -Slack : 0.088 -Actual Width : 0.272 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[23] - -Slack : 0.088 -Actual Width : 0.272 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[24] - -Slack : 0.088 -Actual Width : 0.272 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[25] - -Slack : 0.088 -Actual Width : 0.272 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[26] - -Slack : 0.088 -Actual Width : 0.272 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[27] - Slack : 0.097 Actual Width : 0.281 Required Width : 0.184 @@ -2413,160 +2437,104 @@ Clock : CLOCK_50 Clock Edge : Rise Target : counter[16] -Slack : 0.098 -Actual Width : 0.282 +Slack : 0.097 +Actual Width : 0.281 Required Width : 0.184 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : LED[0]~reg0 +Target : counter[17] -Slack : 0.098 -Actual Width : 0.282 +Slack : 0.097 +Actual Width : 0.281 Required Width : 0.184 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : LED[1]~reg0 +Target : counter[18] -Slack : 0.098 -Actual Width : 0.282 +Slack : 0.097 +Actual Width : 0.281 Required Width : 0.184 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : LED[2]~reg0 +Target : counter[19] -Slack : 0.098 -Actual Width : 0.282 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : LED[3]~reg0 - -Slack : 0.098 -Actual Width : 0.282 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : LED[4]~reg0 - -Slack : 0.098 -Actual Width : 0.282 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : LED[5]~reg0 - -Slack : 0.098 -Actual Width : 0.282 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : LED[6]~reg0 - -Slack : 0.098 -Actual Width : 0.282 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[0] - -Slack : 0.098 -Actual Width : 0.282 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[10] - -Slack : 0.098 -Actual Width : 0.282 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[11] - -Slack : 0.098 -Actual Width : 0.282 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[12] - -Slack : 0.098 -Actual Width : 0.282 +Slack : 0.097 +Actual Width : 0.281 Required Width : 0.184 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : counter[1] -Slack : 0.098 -Actual Width : 0.282 +Slack : 0.097 +Actual Width : 0.281 +Required Width : 0.184 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[20] + +Slack : 0.097 +Actual Width : 0.281 Required Width : 0.184 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : counter[2] -Slack : 0.098 -Actual Width : 0.282 +Slack : 0.097 +Actual Width : 0.281 Required Width : 0.184 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : counter[3] -Slack : 0.098 -Actual Width : 0.282 +Slack : 0.097 +Actual Width : 0.281 Required Width : 0.184 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : counter[4] -Slack : 0.098 -Actual Width : 0.282 +Slack : 0.097 +Actual Width : 0.281 Required Width : 0.184 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : counter[5] -Slack : 0.098 -Actual Width : 0.282 +Slack : 0.097 +Actual Width : 0.281 Required Width : 0.184 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : counter[6] -Slack : 0.098 -Actual Width : 0.282 +Slack : 0.097 +Actual Width : 0.281 Required Width : 0.184 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : counter[7] -Slack : 0.098 -Actual Width : 0.282 +Slack : 0.097 +Actual Width : 0.281 Required Width : 0.184 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : counter[8] -Slack : 0.098 -Actual Width : 0.282 +Slack : 0.097 +Actual Width : 0.281 Required Width : 0.184 Type : Low Pulse Width Clock : CLOCK_50 @@ -2587,7 +2555,7 @@ Required Width : 0.000 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : counter[13]|clk +Target : address[0]|clk Slack : 0.250 Actual Width : 0.250 @@ -2595,7 +2563,7 @@ Required Width : 0.000 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : counter[17]|clk +Target : address[1]|clk Slack : 0.250 Actual Width : 0.250 @@ -2603,127 +2571,15 @@ Required Width : 0.000 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : counter[18]|clk +Target : address[2]|clk -Slack : 0.250 -Actual Width : 0.250 +Slack : 0.258 +Actual Width : 0.258 Required Width : 0.000 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : counter[19]|clk - -Slack : 0.250 -Actual Width : 0.250 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[20]|clk - -Slack : 0.250 -Actual Width : 0.250 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[21]|clk - -Slack : 0.250 -Actual Width : 0.250 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[22]|clk - -Slack : 0.250 -Actual Width : 0.250 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[23]|clk - -Slack : 0.250 -Actual Width : 0.250 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[24]|clk - -Slack : 0.250 -Actual Width : 0.250 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[25]|clk - -Slack : 0.250 -Actual Width : 0.250 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[26]|clk - -Slack : 0.250 -Actual Width : 0.250 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[27]|clk - -Slack : 0.259 -Actual Width : 0.259 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : LED[0]~reg0|clk - -Slack : 0.259 -Actual Width : 0.259 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : LED[1]~reg0|clk - -Slack : 0.259 -Actual Width : 0.259 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : LED[2]~reg0|clk - -Slack : 0.259 -Actual Width : 0.259 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : LED[4]~reg0|clk - -Slack : 0.259 -Actual Width : 0.259 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : LED[5]~reg0|clk - -Slack : 0.259 -Actual Width : 0.259 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : LED[6]~reg0|clk +Target : rom|altsyncram_component|auto_generated|ram_block1a0|clk0 Slack : 0.259 Actual Width : 0.259 @@ -2757,6 +2613,14 @@ Clock : CLOCK_50 Clock Edge : Rise Target : counter[12]|clk +Slack : 0.259 +Actual Width : 0.259 +Required Width : 0.000 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[13]|clk + Slack : 0.259 Actual Width : 0.259 Required Width : 0.000 @@ -2781,6 +2645,30 @@ Clock : CLOCK_50 Clock Edge : Rise Target : counter[16]|clk +Slack : 0.259 +Actual Width : 0.259 +Required Width : 0.000 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[17]|clk + +Slack : 0.259 +Actual Width : 0.259 +Required Width : 0.000 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[18]|clk + +Slack : 0.259 +Actual Width : 0.259 +Required Width : 0.000 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[19]|clk + Slack : 0.259 Actual Width : 0.259 Required Width : 0.000 @@ -2789,6 +2677,14 @@ Clock : CLOCK_50 Clock Edge : Rise Target : counter[1]|clk +Slack : 0.259 +Actual Width : 0.259 +Required Width : 0.000 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[20]|clk + Slack : 0.259 Actual Width : 0.259 Required Width : 0.000 @@ -2804,6 +2700,110 @@ Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : counter[3]|clk + +Slack : 0.259 +Actual Width : 0.259 +Required Width : 0.000 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[4]|clk + +Slack : 0.259 +Actual Width : 0.259 +Required Width : 0.000 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[5]|clk + +Slack : 0.259 +Actual Width : 0.259 +Required Width : 0.000 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[6]|clk + +Slack : 0.259 +Actual Width : 0.259 +Required Width : 0.000 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[7]|clk + +Slack : 0.259 +Actual Width : 0.259 +Required Width : 0.000 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[8]|clk + +Slack : 0.259 +Actual Width : 0.259 +Required Width : 0.000 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[9]|clk + +Slack : 0.263 +Actual Width : 0.263 +Required Width : 0.000 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : CLOCK_50~inputclkctrl|inclk[0] + +Slack : 0.263 +Actual Width : 0.263 +Required Width : 0.000 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : CLOCK_50~inputclkctrl|outclk + +Slack : 0.500 +Actual Width : 0.500 +Required Width : 0.000 +Type : High Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : CLOCK_50~input|i + +Slack : 0.500 +Actual Width : 0.500 +Required Width : 0.000 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : CLOCK_50~input|i + +Slack : 0.501 +Actual Width : 0.717 +Required Width : 0.216 +Type : High Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[0] + +Slack : 0.501 +Actual Width : 0.717 +Required Width : 0.216 +Type : High Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[10] + +Slack : 0.501 +Actual Width : 0.717 +Required Width : 0.216 +Type : High Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[11] +--------------------------------------------------------------------------------+ @@ -2813,57 +2813,64 @@ Target : counter[3]|clk +--------------------------------------------------------------------------------+ Data Port : LED[*] Clock Port : CLOCK_50 -Rise : 9.276 -Fall : 9.028 +Rise : 8.682 +Fall : 8.416 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[0] Clock Port : CLOCK_50 -Rise : 5.406 -Fall : 5.347 +Rise : 6.626 +Fall : 6.525 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[1] Clock Port : CLOCK_50 -Rise : 5.653 -Fall : 5.580 +Rise : 6.680 +Fall : 6.629 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[2] Clock Port : CLOCK_50 -Rise : 5.633 -Fall : 5.560 +Rise : 7.094 +Fall : 7.015 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[3] Clock Port : CLOCK_50 -Rise : 5.406 -Fall : 5.347 +Rise : 6.726 +Fall : 6.609 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[4] Clock Port : CLOCK_50 -Rise : 7.391 -Fall : 7.410 +Rise : 7.077 +Fall : 7.019 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[5] Clock Port : CLOCK_50 -Rise : 9.276 -Fall : 9.028 +Rise : 8.550 +Fall : 8.235 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[6] Clock Port : CLOCK_50 -Rise : 6.114 -Fall : 6.176 +Rise : 7.046 +Fall : 6.990 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : LED[7] +Clock Port : CLOCK_50 +Rise : 8.682 +Fall : 8.416 Clock Edge : Rise Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ @@ -2875,57 +2882,64 @@ Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ Data Port : LED[*] Clock Port : CLOCK_50 -Rise : 5.227 -Fall : 5.167 +Rise : 6.415 +Fall : 6.314 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[0] Clock Port : CLOCK_50 -Rise : 5.227 -Fall : 5.167 +Rise : 6.415 +Fall : 6.314 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[1] Clock Port : CLOCK_50 -Rise : 5.465 -Fall : 5.391 +Rise : 6.467 +Fall : 6.414 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[2] Clock Port : CLOCK_50 -Rise : 5.446 -Fall : 5.372 +Rise : 6.865 +Fall : 6.785 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[3] Clock Port : CLOCK_50 -Rise : 5.228 -Fall : 5.168 +Rise : 6.512 +Fall : 6.396 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[4] Clock Port : CLOCK_50 -Rise : 7.136 -Fall : 7.151 +Rise : 6.852 +Fall : 6.792 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[5] Clock Port : CLOCK_50 -Rise : 9.022 -Fall : 8.769 +Rise : 8.342 +Fall : 8.024 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[6] Clock Port : CLOCK_50 -Rise : 5.905 -Fall : 5.962 +Rise : 6.817 +Fall : 6.759 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : LED[7] +Clock Port : CLOCK_50 +Rise : 8.468 +Fall : 8.198 Clock Edge : Rise Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ @@ -2941,7 +2955,7 @@ No synchronizer chains to report. +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Fmax Summary ; +--------------------------------------------------------------------------------+ -Fmax : 439.56 MHz +Fmax : 300.21 MHz Restricted Fmax : 250.0 MHz Clock Name : CLOCK_50 Note : limit due to minimum period restriction (max I/O toggle rate) @@ -2954,8 +2968,8 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp ; Slow 1200mV 0C Model Setup Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 -Slack : -1.275 -End Point TNS : -22.690 +Slack : -2.331 +End Point TNS : -34.994 +--------------------------------------------------------------------------------+ @@ -2964,7 +2978,7 @@ End Point TNS : -22.690 ; Slow 1200mV 0C Model Hold Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 -Slack : 0.319 +Slack : 0.299 End Point TNS : 0.000 +--------------------------------------------------------------------------------+ @@ -2987,7 +3001,7 @@ No paths to report. +--------------------------------------------------------------------------------+ Clock : CLOCK_50 Slack : -3.000 -End Point TNS : -38.000 +End Point TNS : -46.624 +--------------------------------------------------------------------------------+ @@ -2995,905 +3009,905 @@ End Point TNS : -38.000 +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Setup: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ -Slack : -1.275 -From Node : counter[2] -To Node : counter[27] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.529 - -Slack : -1.208 +Slack : -2.331 From Node : counter[1] -To Node : counter[27] +To Node : address[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.462 +Clock Skew : 0.260 +Data Delay : 3.586 -Slack : -1.204 +Slack : -2.266 +From Node : counter[1] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 3.521 + +Slack : -2.266 From Node : counter[0] -To Node : counter[27] +To Node : address[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.458 +Clock Skew : 0.260 +Data Delay : 3.521 -Slack : -1.175 +Slack : -2.235 +From Node : counter[5] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 3.490 + +Slack : -2.223 +From Node : counter[3] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 3.478 + +Slack : -2.201 From Node : counter[0] -To Node : counter[26] +To Node : address[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.429 +Clock Skew : 0.260 +Data Delay : 3.456 -Slack : -1.175 -From Node : counter[2] -To Node : counter[25] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.429 - -Slack : -1.173 +Slack : -2.167 From Node : counter[4] -To Node : counter[27] +To Node : address[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.427 +Clock Skew : 0.260 +Data Delay : 3.422 + +Slack : -2.153 +From Node : counter[2] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 3.408 + +Slack : -2.134 +From Node : counter[7] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 3.389 + +Slack : -2.133 +From Node : counter[5] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 3.388 + +Slack : -2.121 +From Node : counter[3] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 3.376 + +Slack : -2.066 +From Node : counter[6] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 3.321 + +Slack : -2.065 +From Node : counter[4] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 3.320 + +Slack : -2.051 +From Node : counter[2] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 3.306 + +Slack : -2.050 +From Node : counter[1] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 3.305 + +Slack : -2.032 +From Node : counter[7] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 3.287 + +Slack : -1.985 +From Node : counter[0] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 3.240 + +Slack : -1.964 +From Node : counter[6] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 3.219 + +Slack : -1.936 +From Node : counter[5] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 3.191 + +Slack : -1.932 +From Node : counter[11] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 3.187 + +Slack : -1.924 +From Node : counter[3] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 3.179 + +Slack : -1.917 +From Node : counter[9] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 3.172 + +Slack : -1.868 +From Node : counter[4] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 3.123 + +Slack : -1.854 +From Node : counter[2] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 3.109 + +Slack : -1.851 +From Node : counter[8] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 3.106 + +Slack : -1.835 +From Node : counter[7] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 3.090 + +Slack : -1.832 +From Node : counter[13] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 3.087 + +Slack : -1.767 +From Node : counter[6] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 3.022 + +Slack : -1.763 +From Node : counter[12] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 3.018 + +Slack : -1.750 +From Node : counter[10] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 3.005 + +Slack : -1.733 +From Node : counter[15] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 2.988 + +Slack : -1.682 +From Node : counter[8] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 2.937 + +Slack : -1.670 +From Node : counter[14] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 2.925 + +Slack : -1.659 +From Node : counter[11] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 2.914 + +Slack : -1.644 +From Node : counter[9] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 2.899 + +Slack : -1.633 +From Node : counter[11] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 2.888 + +Slack : -1.629 +From Node : counter[17] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 2.884 + +Slack : -1.618 +From Node : counter[9] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 2.873 + +Slack : -1.581 +From Node : counter[10] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 2.836 + +Slack : -1.568 +From Node : counter[16] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 2.823 + +Slack : -1.559 +From Node : counter[13] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 2.814 + +Slack : -1.552 +From Node : counter[8] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 2.807 + +Slack : -1.533 +From Node : counter[13] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 2.788 + +Slack : -1.531 +From Node : counter[12] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 2.786 + +Slack : -1.484 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.069 +Data Delay : 2.353 + +Slack : -1.484 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.069 +Data Delay : 2.353 + +Slack : -1.484 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.069 +Data Delay : 2.353 + +Slack : -1.484 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.069 +Data Delay : 2.353 + +Slack : -1.484 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.069 +Data Delay : 2.353 + +Slack : -1.484 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.069 +Data Delay : 2.353 + +Slack : -1.484 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.069 +Data Delay : 2.353 + +Slack : -1.484 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.069 +Data Delay : 2.353 + +Slack : -1.464 +From Node : counter[12] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 2.719 + +Slack : -1.460 +From Node : counter[15] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 2.715 + +Slack : -1.451 +From Node : counter[10] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 2.706 + +Slack : -1.434 +From Node : counter[15] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 2.689 + +Slack : -1.407 +From Node : counter[14] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 2.662 + +Slack : -1.371 +From Node : counter[14] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 2.626 + +Slack : -1.356 +From Node : counter[17] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 2.611 + +Slack : -1.330 +From Node : counter[17] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 2.585 + +Slack : -1.312 +From Node : counter[18] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 2.567 + +Slack : -1.311 +From Node : counter[16] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 2.566 + +Slack : -1.289 +From Node : counter[1] +To Node : counter[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.055 +Data Delay : 2.229 + +Slack : -1.269 +From Node : counter[16] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 2.524 + +Slack : -1.260 +From Node : counter[19] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 2.515 + +Slack : -1.224 +From Node : counter[0] +To Node : counter[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.055 +Data Delay : 2.164 + +Slack : -1.218 +From Node : counter[19] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 2.473 + +Slack : -1.201 +From Node : counter[5] +To Node : counter[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.055 +Data Delay : 2.141 + +Slack : -1.194 +From Node : counter[18] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 2.449 + +Slack : -1.189 +From Node : counter[1] +To Node : counter[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.055 +Data Delay : 2.129 + +Slack : -1.189 +From Node : counter[3] +To Node : counter[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.055 +Data Delay : 2.129 + +Slack : -1.186 +From Node : counter[0] +To Node : counter[19] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.055 +Data Delay : 2.126 Slack : -1.171 From Node : counter[1] -To Node : counter[26] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.425 - -Slack : -1.157 -From Node : counter[2] -To Node : counter[26] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.411 - -Slack : -1.111 -From Node : counter[3] -To Node : counter[27] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.365 - -Slack : -1.108 -From Node : counter[1] -To Node : counter[25] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.362 - -Slack : -1.104 -From Node : counter[0] -To Node : counter[25] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.358 - -Slack : -1.076 -From Node : counter[6] -To Node : counter[27] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.330 - -Slack : -1.075 -From Node : counter[0] -To Node : counter[24] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.329 - -Slack : -1.075 -From Node : counter[2] -To Node : counter[23] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.329 - -Slack : -1.073 -From Node : counter[4] -To Node : counter[25] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.327 - -Slack : -1.072 -From Node : counter[3] -To Node : counter[26] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.326 - -Slack : -1.071 -From Node : counter[1] -To Node : counter[24] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.325 - -Slack : -1.057 -From Node : counter[2] -To Node : counter[24] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.311 - -Slack : -1.055 -From Node : counter[4] -To Node : counter[26] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.309 - -Slack : -1.011 -From Node : counter[3] -To Node : counter[25] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.265 - -Slack : -1.008 -From Node : counter[1] -To Node : counter[23] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.262 - -Slack : -1.006 -From Node : counter[5] -To Node : counter[27] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.260 - -Slack : -1.004 -From Node : counter[0] -To Node : counter[23] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.258 - -Slack : -0.990 -From Node : counter[0] -To Node : counter[16] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 1.929 - -Slack : -0.990 -From Node : counter[2] -To Node : counter[15] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 1.929 - -Slack : -0.986 -From Node : counter[1] -To Node : counter[16] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 1.925 - -Slack : -0.977 -From Node : counter[8] -To Node : counter[27] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.231 - -Slack : -0.976 -From Node : counter[5] -To Node : counter[26] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.230 - -Slack : -0.976 -From Node : counter[6] -To Node : counter[25] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.230 - -Slack : -0.975 -From Node : counter[0] -To Node : counter[22] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.229 - -Slack : -0.975 -From Node : counter[2] -To Node : counter[21] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.229 - -Slack : -0.973 -From Node : counter[4] -To Node : counter[23] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.227 - -Slack : -0.972 -From Node : counter[3] -To Node : counter[24] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.226 - -Slack : -0.972 -From Node : counter[2] -To Node : counter[16] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 1.911 - -Slack : -0.971 -From Node : counter[1] -To Node : counter[22] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.225 - -Slack : -0.958 -From Node : counter[6] -To Node : counter[26] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.212 - -Slack : -0.957 -From Node : counter[2] -To Node : counter[22] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.211 - -Slack : -0.955 -From Node : counter[4] -To Node : counter[24] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.209 - -Slack : -0.936 -From Node : counter[13] -To Node : counter[27] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.068 -Data Delay : 1.863 - -Slack : -0.923 -From Node : counter[1] -To Node : counter[15] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 1.862 - -Slack : -0.919 -From Node : counter[0] -To Node : counter[15] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 1.858 - -Slack : -0.911 -From Node : counter[3] -To Node : counter[23] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.165 - -Slack : -0.908 -From Node : counter[1] -To Node : counter[21] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.162 - -Slack : -0.906 -From Node : counter[7] -To Node : counter[27] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.160 - -Slack : -0.906 -From Node : counter[5] -To Node : counter[25] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.160 - -Slack : -0.904 -From Node : counter[0] -To Node : counter[21] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.158 - -Slack : -0.898 -From Node : counter[13] -To Node : counter[26] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.068 -Data Delay : 1.825 - -Slack : -0.890 -From Node : counter[0] -To Node : counter[14] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 1.829 - -Slack : -0.888 -From Node : counter[4] -To Node : counter[15] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 1.827 - -Slack : -0.887 -From Node : counter[3] -To Node : counter[16] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 1.826 - -Slack : -0.886 -From Node : counter[1] -To Node : counter[14] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 1.825 - -Slack : -0.877 -From Node : counter[8] -To Node : counter[25] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.131 - -Slack : -0.876 -From Node : counter[7] -To Node : counter[26] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.130 - -Slack : -0.876 -From Node : counter[5] -To Node : counter[24] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.130 - -Slack : -0.876 -From Node : counter[6] -To Node : counter[23] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.130 - -Slack : -0.875 -From Node : counter[0] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.129 - -Slack : -0.875 -From Node : counter[2] To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.129 - -Slack : -0.875 -From Node : counter[10] -To Node : counter[27] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.129 - -Slack : -0.873 -From Node : counter[4] -To Node : counter[21] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.127 - -Slack : -0.872 -From Node : counter[3] -To Node : counter[22] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.126 - -Slack : -0.872 -From Node : counter[2] -To Node : counter[14] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 1.811 - -Slack : -0.871 -From Node : counter[1] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.125 - -Slack : -0.870 -From Node : counter[4] -To Node : counter[16] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 1.809 - -Slack : -0.859 -From Node : counter[8] -To Node : counter[26] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.113 - -Slack : -0.858 -From Node : counter[6] -To Node : counter[24] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.112 - -Slack : -0.857 -From Node : counter[2] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 +Clock Skew : -0.055 Data Delay : 2.111 -Slack : -0.855 +Slack : -1.133 From Node : counter[4] -To Node : counter[22] +To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.109 +Clock Skew : -0.055 +Data Delay : 2.073 -Slack : -0.836 -From Node : counter[13] -To Node : counter[25] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.068 -Data Delay : 1.763 - -Slack : -0.826 -From Node : counter[3] -To Node : counter[15] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 1.765 - -Slack : -0.811 -From Node : counter[3] -To Node : counter[21] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.065 - -Slack : -0.809 -From Node : counter[9] -To Node : counter[27] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.063 - -Slack : -0.808 -From Node : counter[1] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.062 - -Slack : -0.806 -From Node : counter[7] -To Node : counter[25] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.060 - -Slack : -0.806 -From Node : counter[5] -To Node : counter[23] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.060 - -Slack : -0.804 -From Node : counter[0] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.058 - -Slack : -0.803 -From Node : counter[18] -To Node : counter[27] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.068 -Data Delay : 1.730 - -Slack : -0.798 -From Node : counter[13] -To Node : counter[24] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.068 -Data Delay : 1.725 - -Slack : -0.791 -From Node : counter[5] -To Node : counter[16] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 1.730 - -Slack : -0.791 -From Node : counter[6] -To Node : counter[15] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 1.730 - -Slack : -0.790 -From Node : counter[0] -To Node : counter[12] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 1.729 - -Slack : -0.790 -From Node : counter[2] -To Node : counter[11] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 1.729 - -Slack : -0.787 -From Node : counter[3] -To Node : counter[14] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 1.726 - -Slack : -0.786 -From Node : counter[1] -To Node : counter[12] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 1.725 - -Slack : -0.777 -From Node : counter[8] -To Node : counter[23] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.031 - -Slack : -0.776 -From Node : counter[7] -To Node : counter[24] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.030 - -Slack : -0.776 -From Node : counter[5] -To Node : counter[22] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.030 - -Slack : -0.776 -From Node : counter[6] -To Node : counter[21] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.030 - -Slack : -0.775 +Slack : -1.124 From Node : counter[0] To Node : counter[18] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.259 +Clock Skew : -0.055 +Data Delay : 2.064 + +Slack : -1.123 +From Node : counter[4] +To Node : counter[19] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.055 +Data Delay : 2.063 + +Slack : -1.119 +From Node : counter[2] +To Node : counter[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.055 +Data Delay : 2.059 + +Slack : -1.101 +From Node : counter[5] +To Node : counter[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.055 +Data Delay : 2.041 + +Slack : -1.100 +From Node : counter[7] +To Node : counter[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.055 +Data Delay : 2.040 + +Slack : -1.090 +From Node : counter[2] +To Node : counter[19] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.055 +Data Delay : 2.030 + +Slack : -1.089 +From Node : counter[1] +To Node : counter[16] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.055 Data Delay : 2.029 -Slack : -0.775 +Slack : -1.089 +From Node : counter[3] +To Node : counter[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.055 +Data Delay : 2.029 + +Slack : -1.086 +From Node : counter[0] +To Node : counter[17] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.055 +Data Delay : 2.026 + +Slack : -1.083 +From Node : counter[5] +To Node : counter[19] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.055 +Data Delay : 2.023 + +Slack : -1.071 +From Node : counter[3] +To Node : counter[19] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.055 +Data Delay : 2.011 + +Slack : -1.071 +From Node : counter[1] +To Node : counter[17] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.055 +Data Delay : 2.011 + +Slack : -1.033 +From Node : counter[4] +To Node : counter[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.055 +Data Delay : 1.973 + +Slack : -1.032 +From Node : counter[6] +To Node : counter[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.055 +Data Delay : 1.972 + +Slack : -1.031 +From Node : counter[19] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 2.286 + +Slack : -1.028 +From Node : counter[18] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.260 +Data Delay : 2.283 + +Slack : -1.024 +From Node : counter[0] +To Node : counter[16] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.055 +Data Delay : 1.964 + +Slack : -1.023 +From Node : counter[6] +To Node : counter[19] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.055 +Data Delay : 1.963 + +Slack : -1.023 +From Node : counter[4] +To Node : counter[17] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.055 +Data Delay : 1.963 + +Slack : -1.019 +From Node : counter[2] +To Node : counter[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.055 +Data Delay : 1.959 + +Slack : -1.001 +From Node : counter[5] +To Node : counter[16] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.055 +Data Delay : 1.941 + +Slack : -1.000 +From Node : counter[7] +To Node : counter[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.055 +Data Delay : 1.940 + +Slack : -0.990 From Node : counter[2] To Node : counter[17] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.029 +Clock Skew : -0.055 +Data Delay : 1.930 -Slack : -0.775 -From Node : counter[10] -To Node : counter[25] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.029 - -Slack : -0.774 -From Node : counter[12] -To Node : counter[27] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.028 - -Slack : -0.773 -From Node : counter[6] -To Node : counter[16] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 1.712 - -Slack : -0.773 -From Node : counter[4] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.027 - -Slack : -0.772 -From Node : counter[9] -To Node : counter[26] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.026 - -Slack : -0.772 -From Node : counter[3] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.026 - -Slack : -0.772 -From Node : counter[2] -To Node : counter[12] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 1.711 - -Slack : -0.771 +Slack : -0.989 From Node : counter[1] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.025 - -Slack : -0.770 -From Node : counter[4] To Node : counter[14] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.056 -Data Delay : 1.709 +Clock Skew : -0.055 +Data Delay : 1.929 -Slack : -0.759 -From Node : counter[8] -To Node : counter[24] +Slack : -0.989 +From Node : counter[3] +To Node : counter[16] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.013 +Clock Skew : -0.055 +Data Delay : 1.929 -Slack : -0.758 -From Node : counter[6] -To Node : counter[22] +Slack : -0.986 +From Node : counter[0] +To Node : counter[15] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.259 -Data Delay : 2.012 +Clock Skew : -0.055 +Data Delay : 1.926 +--------------------------------------------------------------------------------+ @@ -3901,905 +3915,905 @@ Data Delay : 2.012 +--------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Hold: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ -Slack : 0.319 -From Node : counter[0] -To Node : counter[0] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.519 - -Slack : 0.412 -From Node : counter[16] -To Node : counter[17] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.383 -Data Delay : 0.939 - -Slack : 0.412 -From Node : counter[12] -To Node : counter[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.383 -Data Delay : 0.939 - -Slack : 0.421 -From Node : counter[11] -To Node : counter[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.383 -Data Delay : 0.948 - -Slack : 0.425 -From Node : counter[15] -To Node : counter[17] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.383 -Data Delay : 0.952 - -Slack : 0.480 -From Node : counter[13] -To Node : counter[13] +Slack : 0.299 +From Node : address[2] +To Node : address[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.068 -Data Delay : 0.692 +Data Delay : 0.511 -Slack : 0.481 +Slack : 0.299 +From Node : address[1] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 0.511 + +Slack : 0.299 +From Node : address[0] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 0.511 + +Slack : 0.330 From Node : counter[20] To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.693 +Clock Skew : 0.055 +Data Delay : 0.529 -Slack : 0.481 -From Node : counter[17] -To Node : counter[17] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.693 - -Slack : 0.482 -From Node : counter[19] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.694 - -Slack : 0.484 -From Node : counter[18] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.696 - -Slack : 0.492 -From Node : counter[11] -To Node : counter[11] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.692 - -Slack : 0.492 -From Node : counter[4] -To Node : counter[4] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.692 - -Slack : 0.493 +Slack : 0.491 From Node : counter[9] To Node : counter[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.693 +Clock Skew : 0.055 +Data Delay : 0.690 -Slack : 0.494 +Slack : 0.495 +From Node : counter[10] +To Node : counter[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.694 + +Slack : 0.496 +From Node : counter[8] +To Node : counter[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.695 + +Slack : 0.496 +From Node : counter[3] +To Node : counter[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.695 + +Slack : 0.496 +From Node : counter[1] +To Node : counter[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.695 + +Slack : 0.498 +From Node : counter[2] +To Node : counter[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.697 + +Slack : 0.509 +From Node : counter[0] +To Node : counter[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.708 + +Slack : 0.618 +From Node : counter[5] +To Node : counter[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.817 + +Slack : 0.622 +From Node : counter[12] +To Node : counter[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.821 + +Slack : 0.625 +From Node : counter[17] +To Node : counter[17] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.824 + +Slack : 0.625 From Node : counter[14] To Node : counter[14] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 0.693 +Data Delay : 0.824 -Slack : 0.494 -From Node : counter[12] -To Node : counter[12] +Slack : 0.625 +From Node : counter[6] +To Node : counter[6] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.694 +Clock Skew : 0.055 +Data Delay : 0.824 -Slack : 0.494 -From Node : counter[3] -To Node : counter[3] +Slack : 0.626 +From Node : counter[19] +To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.694 +Clock Skew : 0.055 +Data Delay : 0.825 -Slack : 0.495 +Slack : 0.626 +From Node : counter[18] +To Node : counter[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.825 + +Slack : 0.626 +From Node : counter[4] +To Node : counter[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.825 + +Slack : 0.626 +From Node : address[1] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.068 +Data Delay : 0.838 + +Slack : 0.628 +From Node : counter[15] +To Node : counter[15] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.827 + +Slack : 0.628 +From Node : counter[13] +To Node : counter[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.827 + +Slack : 0.628 +From Node : counter[7] +To Node : counter[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.827 + +Slack : 0.629 From Node : counter[16] To Node : counter[16] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 0.694 +Data Delay : 0.828 -Slack : 0.495 -From Node : counter[10] -To Node : counter[10] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.695 - -Slack : 0.495 -From Node : counter[8] -To Node : counter[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.695 - -Slack : 0.495 -From Node : counter[2] -To Node : counter[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.695 - -Slack : 0.496 -From Node : counter[6] -To Node : counter[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.696 - -Slack : 0.497 -From Node : counter[15] -To Node : counter[15] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.696 - -Slack : 0.497 -From Node : counter[7] -To Node : counter[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.697 - -Slack : 0.498 -From Node : counter[5] -To Node : counter[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.698 - -Slack : 0.500 -From Node : counter[27] -To Node : counter[27] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.712 - -Slack : 0.500 -From Node : counter[25] -To Node : counter[25] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.712 - -Slack : 0.501 -From Node : counter[26] -To Node : counter[26] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.713 - -Slack : 0.501 -From Node : counter[16] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.383 -Data Delay : 1.028 - -Slack : 0.502 -From Node : counter[24] -To Node : counter[24] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.714 - -Slack : 0.502 -From Node : counter[22] -To Node : counter[22] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.714 - -Slack : 0.504 -From Node : counter[23] -To Node : counter[23] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.716 - -Slack : 0.504 -From Node : counter[21] -To Node : counter[21] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.716 - -Slack : 0.506 -From Node : counter[0] -To Node : counter[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.706 - -Slack : 0.507 -From Node : counter[14] -To Node : counter[17] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.383 -Data Delay : 1.034 - -Slack : 0.507 -From Node : counter[1] -To Node : counter[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.707 - -Slack : 0.508 -From Node : counter[16] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.383 -Data Delay : 1.035 - -Slack : 0.509 -From Node : counter[10] -To Node : counter[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.383 -Data Delay : 1.036 - -Slack : 0.514 -From Node : counter[15] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.383 -Data Delay : 1.041 - -Slack : 0.518 -From Node : counter[9] -To Node : counter[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.383 -Data Delay : 1.045 - -Slack : 0.521 -From Node : counter[15] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.383 -Data Delay : 1.048 - -Slack : 0.596 -From Node : counter[14] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.383 -Data Delay : 1.123 - -Slack : 0.597 -From Node : counter[16] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.383 -Data Delay : 1.124 - -Slack : 0.603 -From Node : counter[14] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.383 -Data Delay : 1.130 - -Slack : 0.604 -From Node : counter[16] -To Node : counter[21] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.383 -Data Delay : 1.131 - -Slack : 0.604 -From Node : counter[12] -To Node : counter[17] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.383 -Data Delay : 1.131 - -Slack : 0.605 -From Node : counter[8] -To Node : counter[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.383 -Data Delay : 1.132 - -Slack : 0.610 -From Node : counter[15] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.383 -Data Delay : 1.137 - -Slack : 0.613 +Slack : 0.629 From Node : counter[11] -To Node : counter[17] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.383 -Data Delay : 1.140 - -Slack : 0.617 -From Node : counter[15] -To Node : counter[21] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.383 -Data Delay : 1.144 - -Slack : 0.618 -From Node : counter[7] -To Node : counter[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.383 -Data Delay : 1.145 - -Slack : 0.692 -From Node : counter[14] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.383 -Data Delay : 1.219 - -Slack : 0.693 -From Node : counter[16] -To Node : counter[22] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.383 -Data Delay : 1.220 - -Slack : 0.693 -From Node : counter[12] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.383 -Data Delay : 1.220 - -Slack : 0.699 -From Node : counter[14] -To Node : counter[21] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.383 -Data Delay : 1.226 - -Slack : 0.700 -From Node : counter[16] -To Node : counter[23] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.383 -Data Delay : 1.227 - -Slack : 0.700 -From Node : counter[12] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.383 -Data Delay : 1.227 - -Slack : 0.701 -From Node : counter[10] -To Node : counter[17] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.383 -Data Delay : 1.228 - -Slack : 0.702 -From Node : counter[6] -To Node : counter[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.383 -Data Delay : 1.229 - -Slack : 0.702 -From Node : counter[11] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.383 -Data Delay : 1.229 - -Slack : 0.706 -From Node : counter[15] -To Node : counter[22] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.383 -Data Delay : 1.233 - -Slack : 0.709 -From Node : counter[11] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.383 -Data Delay : 1.236 - -Slack : 0.710 -From Node : counter[9] -To Node : counter[17] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.383 -Data Delay : 1.237 - -Slack : 0.713 -From Node : counter[15] -To Node : counter[23] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.383 -Data Delay : 1.240 - -Slack : 0.715 -From Node : counter[5] -To Node : counter[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.383 -Data Delay : 1.242 - -Slack : 0.725 -From Node : counter[20] -To Node : counter[21] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.937 - -Slack : 0.729 -From Node : counter[18] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.941 - -Slack : 0.730 -From Node : counter[17] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.942 - -Slack : 0.731 -From Node : counter[19] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.943 - -Slack : 0.736 -From Node : counter[4] -To Node : counter[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.936 - -Slack : 0.737 -From Node : counter[17] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.949 - -Slack : 0.738 -From Node : counter[19] -To Node : counter[21] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.950 - -Slack : 0.739 -From Node : counter[14] -To Node : counter[15] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.055 -Data Delay : 0.938 - -Slack : 0.740 -From Node : counter[10] To Node : counter[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.940 +Clock Skew : 0.055 +Data Delay : 0.828 -Slack : 0.740 -From Node : counter[8] -To Node : counter[9] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.940 - -Slack : 0.740 -From Node : counter[2] -To Node : counter[3] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.940 - -Slack : 0.741 -From Node : counter[6] -To Node : counter[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.941 - -Slack : 0.741 -From Node : counter[11] -To Node : counter[12] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.941 - -Slack : 0.742 +Slack : 0.735 From Node : counter[9] To Node : counter[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.942 +Clock Skew : 0.055 +Data Delay : 0.934 -Slack : 0.742 +Slack : 0.741 From Node : counter[1] To Node : counter[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.942 +Clock Skew : 0.055 +Data Delay : 0.940 -Slack : 0.743 +Slack : 0.741 From Node : counter[3] To Node : counter[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.056 +Clock Skew : 0.055 +Data Delay : 0.940 + +Slack : 0.743 +From Node : counter[0] +To Node : counter[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.942 + +Slack : 0.744 +From Node : counter[10] +To Node : counter[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 Data Delay : 0.943 Slack : 0.745 +From Node : counter[8] +To Node : counter[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.944 + +Slack : 0.747 +From Node : counter[2] +To Node : counter[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.946 + +Slack : 0.750 From Node : counter[0] To Node : counter[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.945 +Clock Skew : 0.055 +Data Delay : 0.949 -Slack : 0.746 -From Node : counter[26] -To Node : counter[27] +Slack : 0.751 +From Node : counter[10] +To Node : counter[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.950 + +Slack : 0.752 +From Node : counter[8] +To Node : counter[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.951 + +Slack : 0.754 +From Node : counter[2] +To Node : counter[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 0.953 + +Slack : 0.790 +From Node : counter[20] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.383 +Data Delay : 1.317 + +Slack : 0.804 +From Node : address[0] +To Node : address[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.068 -Data Delay : 0.958 +Data Delay : 1.016 -Slack : 0.746 +Slack : 0.824 +From Node : counter[9] +To Node : counter[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.023 + +Slack : 0.830 +From Node : counter[3] +To Node : counter[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.029 + +Slack : 0.830 +From Node : counter[1] +To Node : counter[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.029 + +Slack : 0.831 +From Node : counter[9] +To Node : counter[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.030 + +Slack : 0.837 +From Node : counter[3] +To Node : counter[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.036 + +Slack : 0.837 +From Node : counter[1] +To Node : counter[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.036 + +Slack : 0.839 +From Node : counter[0] +To Node : counter[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.038 + +Slack : 0.840 +From Node : counter[10] +To Node : counter[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.039 + +Slack : 0.841 +From Node : counter[8] +To Node : counter[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.040 + +Slack : 0.843 +From Node : counter[2] +To Node : counter[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.042 + +Slack : 0.846 +From Node : counter[0] +To Node : counter[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.045 + +Slack : 0.847 +From Node : counter[10] +To Node : counter[14] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.046 + +Slack : 0.848 +From Node : counter[8] +To Node : counter[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.047 + +Slack : 0.850 +From Node : counter[2] +To Node : counter[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.049 + +Slack : 0.863 +From Node : counter[5] +To Node : counter[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.062 + +Slack : 0.869 +From Node : counter[17] +To Node : counter[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.068 + +Slack : 0.870 +From Node : counter[19] +To Node : counter[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.069 + +Slack : 0.871 +From Node : counter[12] +To Node : counter[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.070 + +Slack : 0.873 +From Node : counter[7] +To Node : counter[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.072 + +Slack : 0.873 From Node : counter[15] To Node : counter[16] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.055 -Data Delay : 0.945 +Data Delay : 1.072 -Slack : 0.746 -From Node : counter[7] -To Node : counter[8] +Slack : 0.873 +From Node : counter[13] +To Node : counter[14] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.946 +Clock Skew : 0.055 +Data Delay : 1.072 -Slack : 0.747 -From Node : counter[24] -To Node : counter[25] +Slack : 0.874 +From Node : counter[14] +To Node : counter[15] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.959 +Clock Skew : 0.055 +Data Delay : 1.073 -Slack : 0.747 -From Node : counter[5] -To Node : counter[6] +Slack : 0.874 +From Node : counter[6] +To Node : counter[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.947 +Clock Skew : 0.055 +Data Delay : 1.073 -Slack : 0.747 -From Node : counter[22] -To Node : counter[23] +Slack : 0.874 +From Node : counter[11] +To Node : counter[12] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.959 +Clock Skew : 0.055 +Data Delay : 1.073 -Slack : 0.749 -From Node : counter[25] -To Node : counter[26] +Slack : 0.875 +From Node : counter[18] +To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.961 +Clock Skew : 0.055 +Data Delay : 1.074 -Slack : 0.749 -From Node : counter[9] -To Node : counter[11] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.949 - -Slack : 0.749 -From Node : counter[1] -To Node : counter[3] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.949 - -Slack : 0.750 -From Node : counter[3] +Slack : 0.875 +From Node : counter[4] To Node : counter[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.950 +Clock Skew : 0.055 +Data Delay : 1.074 -Slack : 0.752 +Slack : 0.878 +From Node : counter[16] +To Node : counter[17] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.077 + +Slack : 0.878 +From Node : counter[12] +To Node : counter[14] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.077 + +Slack : 0.881 +From Node : counter[6] +To Node : counter[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.080 + +Slack : 0.881 +From Node : counter[14] +To Node : counter[16] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.080 + +Slack : 0.882 +From Node : counter[4] +To Node : counter[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.081 + +Slack : 0.882 +From Node : counter[18] +To Node : counter[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.081 + +Slack : 0.885 +From Node : counter[16] +To Node : counter[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.084 + +Slack : 0.920 +From Node : counter[9] +To Node : counter[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.119 + +Slack : 0.926 +From Node : counter[1] +To Node : counter[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.125 + +Slack : 0.926 +From Node : counter[3] +To Node : counter[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.125 + +Slack : 0.927 +From Node : counter[9] +To Node : counter[14] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.126 + +Slack : 0.933 +From Node : counter[1] +To Node : counter[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.132 + +Slack : 0.933 +From Node : counter[3] +To Node : counter[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.132 + +Slack : 0.935 From Node : counter[0] -To Node : counter[3] +To Node : counter[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.952 +Clock Skew : 0.055 +Data Delay : 1.134 -Slack : 0.753 -From Node : counter[23] -To Node : counter[24] +Slack : 0.936 +From Node : counter[10] +To Node : counter[15] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.965 +Clock Skew : 0.055 +Data Delay : 1.135 -Slack : 0.753 -From Node : counter[21] -To Node : counter[22] +Slack : 0.937 +From Node : counter[8] +To Node : counter[13] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.965 +Clock Skew : 0.055 +Data Delay : 1.136 -Slack : 0.753 -From Node : counter[7] -To Node : counter[9] +Slack : 0.939 +From Node : counter[2] +To Node : counter[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.953 +Clock Skew : 0.055 +Data Delay : 1.138 -Slack : 0.754 +Slack : 0.942 +From Node : counter[0] +To Node : counter[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.141 + +Slack : 0.943 +From Node : counter[10] +To Node : counter[16] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.142 + +Slack : 0.944 +From Node : counter[8] +To Node : counter[14] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.143 + +Slack : 0.946 +From Node : counter[2] +To Node : counter[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.145 + +Slack : 0.952 From Node : counter[5] To Node : counter[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.056 -Data Delay : 0.954 +Clock Skew : 0.055 +Data Delay : 1.151 -Slack : 0.756 -From Node : counter[25] -To Node : counter[27] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.968 - -Slack : 0.760 -From Node : counter[21] -To Node : counter[23] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.972 - -Slack : 0.760 -From Node : counter[23] -To Node : counter[25] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.068 -Data Delay : 0.972 - -Slack : 0.788 -From Node : counter[14] -To Node : counter[22] +Slack : 0.953 +From Node : counter[20] +To Node : address[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.383 -Data Delay : 1.315 +Data Delay : 1.480 + +Slack : 0.954 +From Node : counter[17] +To Node : counter[19] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.153 + +Slack : 0.957 +From Node : counter[19] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.383 +Data Delay : 1.484 + +Slack : 0.958 +From Node : counter[11] +To Node : counter[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.157 + +Slack : 0.958 +From Node : counter[13] +To Node : counter[15] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.157 + +Slack : 0.959 +From Node : counter[15] +To Node : counter[17] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.158 + +Slack : 0.959 +From Node : counter[5] +To Node : counter[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.158 + +Slack : 0.960 +From Node : counter[7] +To Node : counter[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.159 + +Slack : 0.965 +From Node : counter[17] +To Node : counter[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.164 + +Slack : 0.967 +From Node : counter[12] +To Node : counter[15] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.166 + +Slack : 0.969 +From Node : counter[7] +To Node : counter[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.168 + +Slack : 0.969 +From Node : counter[15] +To Node : counter[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.168 + +Slack : 0.969 +From Node : counter[13] +To Node : counter[16] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.168 + +Slack : 0.970 +From Node : counter[11] +To Node : counter[14] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.055 +Data Delay : 1.169 +--------------------------------------------------------------------------------+ @@ -4815,13 +4829,77 @@ Clock : CLOCK_50 Clock Edge : Rise Target : CLOCK_50 -Slack : -1.000 +Slack : -2.174 Actual Width : 1.000 -Required Width : 2.000 +Required Width : 3.174 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : LED[0]~reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[0] + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[1] + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[2] + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[3] + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[4] + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[5] + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[6] + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[7] + +Slack : -2.174 +Actual Width : 1.000 +Required Width : 3.174 +Type : Min Period +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 Slack : -1.000 Actual Width : 1.000 @@ -4829,7 +4907,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : LED[1]~reg0 +Target : address[0] Slack : -1.000 Actual Width : 1.000 @@ -4837,7 +4915,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : LED[2]~reg0 +Target : address[1] Slack : -1.000 Actual Width : 1.000 @@ -4845,31 +4923,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : LED[3]~reg0 - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : LED[4]~reg0 - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : LED[5]~reg0 - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : LED[6]~reg0 +Target : address[2] Slack : -1.000 Actual Width : 1.000 @@ -4975,62 +5029,6 @@ Clock : CLOCK_50 Clock Edge : Rise Target : counter[20] -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[21] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[22] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[23] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[24] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[25] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[26] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[27] - Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 @@ -5095,157 +5093,101 @@ Clock : CLOCK_50 Clock Edge : Rise Target : counter[9] -Slack : 0.095 -Actual Width : 0.279 -Required Width : 0.184 +Slack : -0.010 +Actual Width : 0.220 +Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : counter[13] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 -Slack : 0.095 -Actual Width : 0.279 -Required Width : 0.184 +Slack : -0.006 +Actual Width : 0.224 +Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : counter[17] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[0] -Slack : 0.095 -Actual Width : 0.279 -Required Width : 0.184 +Slack : -0.006 +Actual Width : 0.224 +Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : counter[18] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[1] -Slack : 0.095 -Actual Width : 0.279 -Required Width : 0.184 +Slack : -0.006 +Actual Width : 0.224 +Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : counter[19] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[2] -Slack : 0.095 -Actual Width : 0.279 -Required Width : 0.184 +Slack : -0.006 +Actual Width : 0.224 +Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : counter[20] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[3] -Slack : 0.095 -Actual Width : 0.279 -Required Width : 0.184 +Slack : -0.006 +Actual Width : 0.224 +Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : counter[21] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[4] -Slack : 0.095 -Actual Width : 0.279 -Required Width : 0.184 +Slack : -0.006 +Actual Width : 0.224 +Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : counter[22] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[5] -Slack : 0.095 -Actual Width : 0.279 -Required Width : 0.184 +Slack : -0.006 +Actual Width : 0.224 +Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : counter[23] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[6] -Slack : 0.095 -Actual Width : 0.279 -Required Width : 0.184 +Slack : -0.006 +Actual Width : 0.224 +Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : counter[24] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[7] -Slack : 0.095 -Actual Width : 0.279 +Slack : 0.096 +Actual Width : 0.280 Required Width : 0.184 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : counter[25] +Target : address[0] -Slack : 0.095 -Actual Width : 0.279 +Slack : 0.096 +Actual Width : 0.280 Required Width : 0.184 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : counter[26] +Target : address[1] -Slack : 0.095 -Actual Width : 0.279 +Slack : 0.096 +Actual Width : 0.280 Required Width : 0.184 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : counter[27] - -Slack : 0.097 -Actual Width : 0.281 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : LED[0]~reg0 - -Slack : 0.097 -Actual Width : 0.281 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : LED[4]~reg0 - -Slack : 0.097 -Actual Width : 0.281 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : LED[5]~reg0 - -Slack : 0.097 -Actual Width : 0.281 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : LED[6]~reg0 - -Slack : 0.098 -Actual Width : 0.282 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : LED[1]~reg0 - -Slack : 0.098 -Actual Width : 0.282 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : LED[2]~reg0 - -Slack : 0.098 -Actual Width : 0.282 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : LED[3]~reg0 +Target : address[2] Slack : 0.098 Actual Width : 0.282 @@ -5279,6 +5221,14 @@ Clock : CLOCK_50 Clock Edge : Rise Target : counter[12] +Slack : 0.098 +Actual Width : 0.282 +Required Width : 0.184 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[13] + Slack : 0.098 Actual Width : 0.282 Required Width : 0.184 @@ -5303,6 +5253,30 @@ Clock : CLOCK_50 Clock Edge : Rise Target : counter[16] +Slack : 0.098 +Actual Width : 0.282 +Required Width : 0.184 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[17] + +Slack : 0.098 +Actual Width : 0.282 +Required Width : 0.184 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[18] + +Slack : 0.098 +Actual Width : 0.282 +Required Width : 0.184 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[19] + Slack : 0.098 Actual Width : 0.282 Required Width : 0.184 @@ -5311,6 +5285,14 @@ Clock : CLOCK_50 Clock Edge : Rise Target : counter[1] +Slack : 0.098 +Actual Width : 0.282 +Required Width : 0.184 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[20] + Slack : 0.098 Actual Width : 0.282 Required Width : 0.184 @@ -5383,101 +5365,29 @@ Clock : CLOCK_50 Clock Edge : Rise Target : CLOCK_50~input|o -Slack : 0.255 -Actual Width : 0.255 +Slack : 0.256 +Actual Width : 0.256 Required Width : 0.000 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : counter[13]|clk +Target : address[0]|clk -Slack : 0.255 -Actual Width : 0.255 +Slack : 0.256 +Actual Width : 0.256 Required Width : 0.000 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : counter[17]|clk +Target : address[1]|clk -Slack : 0.255 -Actual Width : 0.255 +Slack : 0.256 +Actual Width : 0.256 Required Width : 0.000 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : counter[18]|clk - -Slack : 0.255 -Actual Width : 0.255 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[19]|clk - -Slack : 0.255 -Actual Width : 0.255 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[20]|clk - -Slack : 0.255 -Actual Width : 0.255 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[21]|clk - -Slack : 0.255 -Actual Width : 0.255 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[22]|clk - -Slack : 0.255 -Actual Width : 0.255 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[23]|clk - -Slack : 0.255 -Actual Width : 0.255 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[24]|clk - -Slack : 0.255 -Actual Width : 0.255 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[25]|clk - -Slack : 0.255 -Actual Width : 0.255 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[26]|clk - -Slack : 0.255 -Actual Width : 0.255 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[27]|clk +Target : address[2]|clk Slack : 0.257 Actual Width : 0.257 @@ -5485,55 +5395,7 @@ Required Width : 0.000 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : LED[0]~reg0|clk - -Slack : 0.257 -Actual Width : 0.257 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : LED[4]~reg0|clk - -Slack : 0.257 -Actual Width : 0.257 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : LED[5]~reg0|clk - -Slack : 0.257 -Actual Width : 0.257 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : LED[6]~reg0|clk - -Slack : 0.258 -Actual Width : 0.258 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : LED[1]~reg0|clk - -Slack : 0.258 -Actual Width : 0.258 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : LED[2]~reg0|clk - -Slack : 0.258 -Actual Width : 0.258 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : LED[3]~reg0|clk +Target : rom|altsyncram_component|auto_generated|ram_block1a0|clk0 Slack : 0.258 Actual Width : 0.258 @@ -5567,6 +5429,14 @@ Clock : CLOCK_50 Clock Edge : Rise Target : counter[12]|clk +Slack : 0.258 +Actual Width : 0.258 +Required Width : 0.000 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[13]|clk + Slack : 0.258 Actual Width : 0.258 Required Width : 0.000 @@ -5591,6 +5461,30 @@ Clock : CLOCK_50 Clock Edge : Rise Target : counter[16]|clk +Slack : 0.258 +Actual Width : 0.258 +Required Width : 0.000 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[17]|clk + +Slack : 0.258 +Actual Width : 0.258 +Required Width : 0.000 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[18]|clk + +Slack : 0.258 +Actual Width : 0.258 +Required Width : 0.000 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[19]|clk + Slack : 0.258 Actual Width : 0.258 Required Width : 0.000 @@ -5599,6 +5493,14 @@ Clock : CLOCK_50 Clock Edge : Rise Target : counter[1]|clk +Slack : 0.258 +Actual Width : 0.258 +Required Width : 0.000 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[20]|clk + Slack : 0.258 Actual Width : 0.258 Required Width : 0.000 @@ -5606,6 +5508,118 @@ Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : counter[2]|clk + +Slack : 0.258 +Actual Width : 0.258 +Required Width : 0.000 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[3]|clk + +Slack : 0.258 +Actual Width : 0.258 +Required Width : 0.000 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[4]|clk + +Slack : 0.258 +Actual Width : 0.258 +Required Width : 0.000 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[5]|clk + +Slack : 0.258 +Actual Width : 0.258 +Required Width : 0.000 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[6]|clk + +Slack : 0.258 +Actual Width : 0.258 +Required Width : 0.000 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[7]|clk + +Slack : 0.258 +Actual Width : 0.258 +Required Width : 0.000 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[8]|clk + +Slack : 0.258 +Actual Width : 0.258 +Required Width : 0.000 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[9]|clk + +Slack : 0.260 +Actual Width : 0.260 +Required Width : 0.000 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : CLOCK_50~inputclkctrl|inclk[0] + +Slack : 0.260 +Actual Width : 0.260 +Required Width : 0.000 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : CLOCK_50~inputclkctrl|outclk + +Slack : 0.500 +Actual Width : 0.500 +Required Width : 0.000 +Type : High Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : CLOCK_50~input|i + +Slack : 0.500 +Actual Width : 0.500 +Required Width : 0.000 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : CLOCK_50~input|i + +Slack : 0.502 +Actual Width : 0.718 +Required Width : 0.216 +Type : High Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[0] + +Slack : 0.502 +Actual Width : 0.718 +Required Width : 0.216 +Type : High Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[10] + +Slack : 0.502 +Actual Width : 0.718 +Required Width : 0.216 +Type : High Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[11] +--------------------------------------------------------------------------------+ @@ -5615,57 +5629,64 @@ Target : counter[2]|clk +--------------------------------------------------------------------------------+ Data Port : LED[*] Clock Port : CLOCK_50 -Rise : 8.355 -Fall : 7.943 +Rise : 7.790 +Fall : 7.377 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[0] Clock Port : CLOCK_50 -Rise : 4.866 -Fall : 4.790 +Rise : 5.977 +Fall : 5.870 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[1] Clock Port : CLOCK_50 -Rise : 5.094 -Fall : 4.999 +Rise : 6.028 +Fall : 5.911 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[2] Clock Port : CLOCK_50 -Rise : 5.080 -Fall : 4.980 +Rise : 6.408 +Fall : 6.271 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[3] Clock Port : CLOCK_50 -Rise : 4.866 -Fall : 4.790 +Rise : 6.070 +Fall : 5.920 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[4] Clock Port : CLOCK_50 -Rise : 6.680 -Fall : 6.595 +Rise : 6.384 +Fall : 6.235 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[5] Clock Port : CLOCK_50 -Rise : 8.355 -Fall : 7.943 +Rise : 7.673 +Fall : 7.213 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[6] Clock Port : CLOCK_50 -Rise : 5.527 -Fall : 5.526 +Rise : 6.381 +Fall : 6.262 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : LED[7] +Clock Port : CLOCK_50 +Rise : 7.790 +Fall : 7.377 Clock Edge : Rise Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ @@ -5677,57 +5698,64 @@ Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ Data Port : LED[*] Clock Port : CLOCK_50 -Rise : 4.695 -Fall : 4.618 +Rise : 5.770 +Fall : 5.664 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[0] Clock Port : CLOCK_50 -Rise : 4.695 -Fall : 4.618 +Rise : 5.770 +Fall : 5.664 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[1] Clock Port : CLOCK_50 -Rise : 4.914 -Fall : 4.819 +Rise : 5.819 +Fall : 5.703 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[2] Clock Port : CLOCK_50 -Rise : 4.900 -Fall : 4.802 +Rise : 6.184 +Fall : 6.049 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[3] Clock Port : CLOCK_50 -Rise : 4.696 -Fall : 4.619 +Rise : 5.860 +Fall : 5.712 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[4] Clock Port : CLOCK_50 -Rise : 6.438 -Fall : 6.352 +Rise : 6.162 +Fall : 6.015 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[5] Clock Port : CLOCK_50 -Rise : 8.113 -Fall : 7.701 +Rise : 7.467 +Fall : 7.009 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[6] Clock Port : CLOCK_50 -Rise : 5.328 -Fall : 5.323 +Rise : 6.156 +Fall : 6.039 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : LED[7] +Clock Port : CLOCK_50 +Rise : 7.580 +Fall : 7.166 Clock Edge : Rise Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ @@ -5744,8 +5772,8 @@ No synchronizer chains to report. ; Fast 1200mV 0C Model Setup Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 -Slack : -0.500 -End Point TNS : -4.764 +Slack : -1.122 +End Point TNS : -9.363 +--------------------------------------------------------------------------------+ @@ -5754,7 +5782,7 @@ End Point TNS : -4.764 ; Fast 1200mV 0C Model Hold Summary ; +--------------------------------------------------------------------------------+ Clock : CLOCK_50 -Slack : 0.193 +Slack : 0.178 End Point TNS : 0.000 +--------------------------------------------------------------------------------+ @@ -5777,7 +5805,7 @@ No paths to report. +--------------------------------------------------------------------------------+ Clock : CLOCK_50 Slack : -3.000 -End Point TNS : -48.277 +End Point TNS : -45.480 +--------------------------------------------------------------------------------+ @@ -5785,905 +5813,905 @@ End Point TNS : -48.277 +--------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Setup: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ -Slack : -0.500 -From Node : counter[2] -To Node : counter[27] +Slack : -1.122 +From Node : counter[1] +To Node : address[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.152 +Clock Skew : 0.153 +Data Delay : 2.262 + +Slack : -1.072 +From Node : counter[0] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 2.212 + +Slack : -1.064 +From Node : counter[5] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 2.204 + +Slack : -1.059 +From Node : counter[1] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 2.199 + +Slack : -1.054 +From Node : counter[3] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 2.194 + +Slack : -1.014 +From Node : counter[4] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 2.154 + +Slack : -1.009 +From Node : counter[0] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 2.149 + +Slack : -1.006 +From Node : counter[2] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 2.146 + +Slack : -0.996 +From Node : counter[7] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 2.136 + +Slack : -0.946 +From Node : counter[6] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 2.086 + +Slack : -0.938 +From Node : counter[5] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 2.078 + +Slack : -0.928 +From Node : counter[3] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 2.068 + +Slack : -0.927 +From Node : counter[1] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 2.067 + +Slack : -0.894 +From Node : counter[2] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 2.034 + +Slack : -0.888 +From Node : counter[4] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 2.028 + +Slack : -0.877 +From Node : counter[0] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 2.017 + +Slack : -0.870 +From Node : counter[7] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 2.010 + +Slack : -0.869 +From Node : counter[5] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 2.009 + +Slack : -0.859 +From Node : counter[11] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.999 + +Slack : -0.859 +From Node : counter[3] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.999 + +Slack : -0.845 +From Node : counter[9] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.985 + +Slack : -0.820 +From Node : counter[6] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.960 + +Slack : -0.819 +From Node : counter[4] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.959 + +Slack : -0.811 +From Node : counter[2] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.951 + +Slack : -0.801 +From Node : counter[8] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.941 + +Slack : -0.801 +From Node : counter[7] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.941 + +Slack : -0.791 +From Node : counter[13] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.931 + +Slack : -0.751 +From Node : counter[6] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.891 + +Slack : -0.743 +From Node : counter[12] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.883 + +Slack : -0.733 +From Node : counter[10] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.873 + +Slack : -0.723 +From Node : counter[15] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.863 + +Slack : -0.682 +From Node : counter[11] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.822 + +Slack : -0.676 +From Node : counter[14] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.816 + +Slack : -0.668 +From Node : counter[9] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.808 + +Slack : -0.664 +From Node : counter[11] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.804 + +Slack : -0.651 +From Node : counter[17] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.791 + +Slack : -0.650 +From Node : counter[9] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.790 + +Slack : -0.635 +From Node : counter[8] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.775 + +Slack : -0.614 +From Node : counter[13] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.754 + +Slack : -0.610 +From Node : counter[16] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.750 + +Slack : -0.606 +From Node : counter[8] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.746 + +Slack : -0.596 +From Node : counter[13] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.736 + +Slack : -0.567 +From Node : counter[10] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.707 + +Slack : -0.566 +From Node : counter[12] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.706 + +Slack : -0.548 +From Node : counter[12] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.688 + +Slack : -0.546 +From Node : counter[15] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.686 + +Slack : -0.538 +From Node : counter[10] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.678 + +Slack : -0.528 +From Node : counter[15] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.668 + +Slack : -0.499 +From Node : counter[14] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 Data Delay : 1.639 -Slack : -0.452 -From Node : counter[1] -To Node : counter[27] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.591 - -Slack : -0.452 -From Node : counter[0] -To Node : counter[27] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.591 - -Slack : -0.436 -From Node : counter[2] -To Node : counter[26] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.575 - -Slack : -0.432 -From Node : counter[2] -To Node : counter[25] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.571 - -Slack : -0.428 -From Node : counter[4] -To Node : counter[27] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.567 - -Slack : -0.422 -From Node : counter[1] -To Node : counter[26] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.561 - -Slack : -0.422 -From Node : counter[0] -To Node : counter[26] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.561 - -Slack : -0.384 -From Node : counter[1] -To Node : counter[25] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.523 - -Slack : -0.384 -From Node : counter[0] -To Node : counter[25] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.523 - -Slack : -0.383 -From Node : counter[3] -To Node : counter[27] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.522 - -Slack : -0.368 -From Node : counter[2] -To Node : counter[24] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.507 - -Slack : -0.364 -From Node : counter[2] -To Node : counter[23] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.503 - -Slack : -0.364 -From Node : counter[6] -To Node : counter[27] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.503 - -Slack : -0.364 -From Node : counter[4] -To Node : counter[26] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.503 - -Slack : -0.360 -From Node : counter[4] -To Node : counter[25] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.499 - -Slack : -0.354 -From Node : counter[3] -To Node : counter[26] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.493 - -Slack : -0.354 -From Node : counter[1] -To Node : counter[24] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.493 - -Slack : -0.354 -From Node : counter[0] -To Node : counter[24] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.493 - -Slack : -0.316 -From Node : counter[5] -To Node : counter[27] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.455 - -Slack : -0.316 -From Node : counter[1] -To Node : counter[23] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.455 - -Slack : -0.316 -From Node : counter[0] -To Node : counter[23] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.455 - -Slack : -0.315 -From Node : counter[3] -To Node : counter[25] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.454 - -Slack : -0.300 -From Node : counter[2] -To Node : counter[22] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.439 - -Slack : -0.300 -From Node : counter[6] -To Node : counter[26] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.439 - -Slack : -0.296 -From Node : counter[2] -To Node : counter[21] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.435 - -Slack : -0.296 -From Node : counter[8] -To Node : counter[27] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.435 - -Slack : -0.296 -From Node : counter[6] -To Node : counter[25] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.435 - -Slack : -0.296 -From Node : counter[4] -To Node : counter[24] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.435 - -Slack : -0.292 -From Node : counter[4] -To Node : counter[23] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.431 - -Slack : -0.286 -From Node : counter[2] -To Node : counter[16] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.038 -Data Delay : 1.235 - -Slack : -0.286 -From Node : counter[5] -To Node : counter[26] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.425 - -Slack : -0.286 -From Node : counter[3] -To Node : counter[24] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.425 - -Slack : -0.286 -From Node : counter[1] -To Node : counter[22] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.425 - -Slack : -0.286 -From Node : counter[0] -To Node : counter[22] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.425 - -Slack : -0.282 -From Node : counter[2] -To Node : counter[15] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.038 -Data Delay : 1.231 - -Slack : -0.272 -From Node : counter[1] -To Node : counter[16] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.038 -Data Delay : 1.221 - -Slack : -0.272 -From Node : counter[0] -To Node : counter[16] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.038 -Data Delay : 1.221 - -Slack : -0.248 -From Node : counter[7] -To Node : counter[27] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.387 - -Slack : -0.248 -From Node : counter[5] -To Node : counter[25] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.387 - -Slack : -0.248 -From Node : counter[1] -To Node : counter[21] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.387 - -Slack : -0.248 -From Node : counter[0] -To Node : counter[21] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.387 - -Slack : -0.247 -From Node : counter[3] -To Node : counter[23] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.386 - -Slack : -0.240 -From Node : counter[13] -To Node : counter[27] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.045 -Data Delay : 1.182 - -Slack : -0.234 -From Node : counter[1] -To Node : counter[15] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.038 -Data Delay : 1.183 - -Slack : -0.234 -From Node : counter[0] -To Node : counter[15] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.038 -Data Delay : 1.183 - -Slack : -0.232 -From Node : counter[2] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.371 - -Slack : -0.232 -From Node : counter[8] -To Node : counter[26] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.371 - -Slack : -0.232 -From Node : counter[6] -To Node : counter[24] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.371 - -Slack : -0.228 -From Node : counter[2] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.367 - -Slack : -0.228 -From Node : counter[10] -To Node : counter[27] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.367 - -Slack : -0.228 -From Node : counter[8] -To Node : counter[25] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.367 - -Slack : -0.228 -From Node : counter[6] -To Node : counter[23] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.367 - -Slack : -0.228 -From Node : counter[4] -To Node : counter[22] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.367 - -Slack : -0.224 -From Node : counter[4] -To Node : counter[21] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.363 - -Slack : -0.219 -From Node : counter[7] -To Node : counter[26] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.358 - -Slack : -0.218 -From Node : counter[2] -To Node : counter[14] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.038 -Data Delay : 1.167 - -Slack : -0.218 -From Node : counter[5] -To Node : counter[24] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.357 - -Slack : -0.218 -From Node : counter[3] -To Node : counter[22] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.357 - -Slack : -0.218 +Slack : -0.485 From Node : counter[1] To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.357 +Clock Skew : -0.037 +Data Delay : 1.435 -Slack : -0.218 +Slack : -0.481 +From Node : counter[14] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.621 + +Slack : -0.474 +From Node : counter[17] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.614 + +Slack : -0.456 +From Node : counter[17] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.596 + +Slack : -0.435 From Node : counter[0] To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.357 +Clock Skew : -0.037 +Data Delay : 1.385 -Slack : -0.214 -From Node : counter[4] -To Node : counter[16] +Slack : -0.433 +From Node : counter[16] +To Node : address[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.038 -Data Delay : 1.163 +Clock Skew : 0.153 +Data Delay : 1.573 -Slack : -0.210 -From Node : counter[13] -To Node : counter[26] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.045 -Data Delay : 1.152 - -Slack : -0.210 -From Node : counter[4] -To Node : counter[15] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.038 -Data Delay : 1.159 - -Slack : -0.204 -From Node : counter[3] -To Node : counter[16] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.038 -Data Delay : 1.153 - -Slack : -0.204 -From Node : counter[1] -To Node : counter[14] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.038 -Data Delay : 1.153 - -Slack : -0.204 -From Node : counter[0] -To Node : counter[14] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.038 -Data Delay : 1.153 - -Slack : -0.180 -From Node : counter[7] -To Node : counter[25] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.319 - -Slack : -0.180 +Slack : -0.427 From Node : counter[5] -To Node : counter[23] +To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.319 +Clock Skew : -0.037 +Data Delay : 1.377 -Slack : -0.180 +Slack : -0.426 +From Node : counter[18] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.566 + +Slack : -0.421 From Node : counter[1] To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.319 +Clock Skew : -0.037 +Data Delay : 1.371 -Slack : -0.180 -From Node : counter[0] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.319 - -Slack : -0.179 -From Node : counter[9] -To Node : counter[27] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.318 - -Slack : -0.179 -From Node : counter[3] -To Node : counter[21] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.318 - -Slack : -0.172 -From Node : counter[13] -To Node : counter[25] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.045 -Data Delay : 1.114 - -Slack : -0.165 -From Node : counter[3] -To Node : counter[15] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.038 -Data Delay : 1.114 - -Slack : -0.164 -From Node : counter[2] +Slack : -0.417 +From Node : counter[1] To Node : counter[18] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.303 +Clock Skew : -0.037 +Data Delay : 1.367 -Slack : -0.164 -From Node : counter[10] -To Node : counter[26] +Slack : -0.417 +From Node : counter[3] +To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.303 +Clock Skew : -0.037 +Data Delay : 1.367 -Slack : -0.164 -From Node : counter[8] -To Node : counter[24] +Slack : -0.415 +From Node : counter[16] +To Node : address[0] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.303 +Clock Skew : 0.153 +Data Delay : 1.555 -Slack : -0.164 -From Node : counter[6] -To Node : counter[22] +Slack : -0.410 +From Node : counter[19] +To Node : address[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.303 +Clock Skew : 0.153 +Data Delay : 1.550 -Slack : -0.160 +Slack : -0.407 +From Node : counter[0] +To Node : counter[19] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.357 + +Slack : -0.377 +From Node : counter[4] +To Node : counter[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.327 + +Slack : -0.369 +From Node : counter[19] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.509 + +Slack : -0.369 From Node : counter[2] +To Node : counter[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.319 + +Slack : -0.367 +From Node : counter[0] +To Node : counter[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.317 + +Slack : -0.363 +From Node : counter[5] +To Node : counter[19] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.313 + +Slack : -0.361 +From Node : counter[18] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.501 + +Slack : -0.359 +From Node : counter[7] +To Node : counter[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.309 + +Slack : -0.359 +From Node : counter[5] +To Node : counter[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.309 + +Slack : -0.353 +From Node : counter[1] To Node : counter[17] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.299 +Clock Skew : -0.037 +Data Delay : 1.303 -Slack : -0.160 -From Node : counter[12] -To Node : counter[27] +Slack : -0.353 +From Node : counter[3] +To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.299 +Clock Skew : -0.037 +Data Delay : 1.303 -Slack : -0.160 -From Node : counter[10] -To Node : counter[25] +Slack : -0.349 +From Node : counter[1] +To Node : counter[16] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.152 +Clock Skew : -0.037 Data Delay : 1.299 -Slack : -0.160 -From Node : counter[8] -To Node : counter[23] +Slack : -0.349 +From Node : counter[3] +To Node : counter[18] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.152 +Clock Skew : -0.037 Data Delay : 1.299 -Slack : -0.160 -From Node : counter[6] -To Node : counter[21] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.299 - -Slack : -0.160 -From Node : counter[4] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.299 - -Slack : -0.156 +Slack : -0.341 From Node : counter[4] To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.295 +Clock Skew : -0.037 +Data Delay : 1.291 -Slack : -0.154 -From Node : counter[18] -To Node : counter[27] +Slack : -0.339 +From Node : counter[2] +To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.045 -Data Delay : 1.096 - -Slack : -0.151 -From Node : counter[9] -To Node : counter[26] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.290 - -Slack : -0.151 -From Node : counter[7] -To Node : counter[24] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.290 - -Slack : -0.150 -From Node : counter[6] -To Node : counter[16] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.038 -Data Delay : 1.099 - -Slack : -0.150 -From Node : counter[5] -To Node : counter[22] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 +Clock Skew : -0.037 Data Delay : 1.289 -Slack : -0.150 -From Node : counter[3] +Slack : -0.339 +From Node : counter[0] +To Node : counter[17] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.289 + +Slack : -0.324 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.047 +Data Delay : 1.232 + +Slack : -0.324 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.047 +Data Delay : 1.232 + +Slack : -0.324 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.047 +Data Delay : 1.232 + +Slack : -0.324 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.047 +Data Delay : 1.232 + +Slack : -0.324 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.047 +Data Delay : 1.232 + +Slack : -0.324 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.047 +Data Delay : 1.232 + +Slack : -0.324 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.047 +Data Delay : 1.232 + +Slack : -0.324 +From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 +To Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.047 +Data Delay : 1.232 + +Slack : -0.309 +From Node : counter[6] To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.289 - -Slack : -0.150 -From Node : counter[1] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.289 - -Slack : -0.150 -From Node : counter[0] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : 0.152 -Data Delay : 1.289 - -Slack : -0.149 -From Node : counter[2] -To Node : counter[12] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 Clock Skew : -0.037 -Data Delay : 1.099 +Data Delay : 1.259 -Slack : -0.146 -From Node : counter[6] -To Node : counter[15] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.038 -Data Delay : 1.095 - -Slack : -0.146 +Slack : -0.309 From Node : counter[4] -To Node : counter[14] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 1.000 -Clock Skew : -0.038 -Data Delay : 1.095 - -Slack : -0.145 -From Node : counter[2] -To Node : counter[11] +To Node : counter[18] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 Clock Skew : -0.037 -Data Delay : 1.095 +Data Delay : 1.259 -Slack : -0.142 -From Node : counter[13] -To Node : counter[24] +Slack : -0.301 +From Node : counter[2] +To Node : counter[18] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.045 -Data Delay : 1.084 +Clock Skew : -0.037 +Data Delay : 1.251 -Slack : -0.136 +Slack : -0.299 +From Node : counter[0] +To Node : counter[16] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.249 + +Slack : -0.295 +From Node : counter[7] +To Node : counter[19] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.245 + +Slack : -0.295 +From Node : counter[5] +To Node : counter[17] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.245 + +Slack : -0.291 +From Node : counter[7] +To Node : counter[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.241 + +Slack : -0.291 From Node : counter[5] To Node : counter[16] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 1.000 -Clock Skew : -0.038 -Data Delay : 1.085 +Clock Skew : -0.037 +Data Delay : 1.241 + +Slack : -0.286 +From Node : counter[19] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : 0.153 +Data Delay : 1.426 + +Slack : -0.285 +From Node : counter[1] +To Node : counter[15] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.235 + +Slack : -0.285 +From Node : counter[3] +To Node : counter[17] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.235 + +Slack : -0.281 +From Node : counter[1] +To Node : counter[14] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.231 + +Slack : -0.281 +From Node : counter[3] +To Node : counter[16] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.231 + +Slack : -0.273 +From Node : counter[6] +To Node : counter[19] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 1.000 +Clock Skew : -0.037 +Data Delay : 1.223 +--------------------------------------------------------------------------------+ @@ -6691,905 +6719,905 @@ Data Delay : 1.085 +--------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Hold: 'CLOCK_50' ; +--------------------------------------------------------------------------------+ +Slack : 0.178 +From Node : address[2] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.307 + +Slack : 0.178 +From Node : address[1] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.307 + +Slack : 0.178 +From Node : address[0] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.045 +Data Delay : 0.307 + Slack : 0.193 -From Node : counter[0] -To Node : counter[0] +From Node : counter[20] +To Node : counter[20] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.037 Data Delay : 0.314 -Slack : 0.244 -From Node : counter[16] -To Node : counter[17] +Slack : 0.291 +From Node : counter[9] +To Node : counter[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.235 -Data Delay : 0.563 +Clock Skew : 0.037 +Data Delay : 0.412 -Slack : 0.245 -From Node : counter[12] -To Node : counter[13] +Slack : 0.293 +From Node : counter[10] +To Node : counter[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.234 -Data Delay : 0.563 - -Slack : 0.257 -From Node : counter[15] -To Node : counter[17] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.235 -Data Delay : 0.576 - -Slack : 0.257 -From Node : counter[11] -To Node : counter[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.234 -Data Delay : 0.575 - -Slack : 0.284 -From Node : counter[13] -To Node : counter[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.413 - -Slack : 0.285 -From Node : counter[20] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.045 +Clock Skew : 0.037 Data Delay : 0.414 -Slack : 0.286 +Slack : 0.293 +From Node : counter[8] +To Node : counter[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.414 + +Slack : 0.293 +From Node : counter[3] +To Node : counter[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.414 + +Slack : 0.293 +From Node : counter[1] +To Node : counter[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.414 + +Slack : 0.294 +From Node : counter[2] +To Node : counter[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.415 + +Slack : 0.302 +From Node : counter[0] +To Node : counter[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.423 + +Slack : 0.359 From Node : counter[19] To Node : counter[19] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.415 +Clock Skew : 0.037 +Data Delay : 0.480 -Slack : 0.286 -From Node : counter[18] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.415 - -Slack : 0.286 -From Node : counter[17] -To Node : counter[17] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.415 - -Slack : 0.292 +Slack : 0.359 From Node : counter[14] To Node : counter[14] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.413 +Data Delay : 0.480 -Slack : 0.292 -From Node : counter[4] -To Node : counter[4] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.413 - -Slack : 0.293 -From Node : counter[16] -To Node : counter[16] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.414 - -Slack : 0.293 -From Node : counter[12] -To Node : counter[12] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.414 - -Slack : 0.293 -From Node : counter[11] -To Node : counter[11] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.414 - -Slack : 0.293 -From Node : counter[10] -To Node : counter[10] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.414 - -Slack : 0.293 -From Node : counter[9] -To Node : counter[9] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.414 - -Slack : 0.293 -From Node : counter[6] -To Node : counter[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.414 - -Slack : 0.293 -From Node : counter[3] -To Node : counter[3] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.414 - -Slack : 0.293 -From Node : counter[2] -To Node : counter[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.414 - -Slack : 0.294 -From Node : counter[15] -To Node : counter[15] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.415 - -Slack : 0.294 -From Node : counter[8] -To Node : counter[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.415 - -Slack : 0.294 +Slack : 0.359 From Node : counter[7] To Node : counter[7] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.415 +Data Delay : 0.480 -Slack : 0.294 +Slack : 0.360 +From Node : counter[17] +To Node : counter[17] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.481 + +Slack : 0.360 +From Node : counter[6] +To Node : counter[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.481 + +Slack : 0.360 From Node : counter[5] To Node : counter[5] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.415 +Data Delay : 0.481 -Slack : 0.297 -From Node : counter[27] -To Node : counter[27] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.426 - -Slack : 0.297 -From Node : counter[25] -To Node : counter[25] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.426 - -Slack : 0.297 -From Node : counter[22] -To Node : counter[22] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.426 - -Slack : 0.298 -From Node : counter[26] -To Node : counter[26] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.427 - -Slack : 0.298 -From Node : counter[24] -To Node : counter[24] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.427 - -Slack : 0.298 -From Node : counter[21] -To Node : counter[21] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.427 - -Slack : 0.299 -From Node : counter[23] -To Node : counter[23] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.428 - -Slack : 0.299 -From Node : counter[1] -To Node : counter[1] +Slack : 0.360 +From Node : counter[4] +To Node : counter[4] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.420 +Data Delay : 0.481 -Slack : 0.299 -From Node : counter[0] -To Node : counter[1] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.420 - -Slack : 0.307 -From Node : counter[16] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.235 -Data Delay : 0.626 - -Slack : 0.309 -From Node : counter[14] -To Node : counter[17] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.235 -Data Delay : 0.628 - -Slack : 0.310 -From Node : counter[16] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.235 -Data Delay : 0.629 - -Slack : 0.311 -From Node : counter[10] -To Node : counter[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.234 -Data Delay : 0.629 - -Slack : 0.320 -From Node : counter[15] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.235 -Data Delay : 0.639 - -Slack : 0.323 -From Node : counter[15] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.235 -Data Delay : 0.642 - -Slack : 0.323 -From Node : counter[9] -To Node : counter[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.234 -Data Delay : 0.641 - -Slack : 0.372 -From Node : counter[14] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.235 -Data Delay : 0.691 - -Slack : 0.373 -From Node : counter[16] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.235 -Data Delay : 0.692 - -Slack : 0.375 -From Node : counter[14] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.235 -Data Delay : 0.694 - -Slack : 0.376 -From Node : counter[16] -To Node : counter[21] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.235 -Data Delay : 0.695 - -Slack : 0.377 -From Node : counter[12] -To Node : counter[17] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.234 -Data Delay : 0.695 - -Slack : 0.378 -From Node : counter[8] -To Node : counter[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.234 -Data Delay : 0.696 - -Slack : 0.386 -From Node : counter[15] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.235 -Data Delay : 0.705 - -Slack : 0.389 -From Node : counter[15] -To Node : counter[21] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.235 -Data Delay : 0.708 - -Slack : 0.389 -From Node : counter[11] -To Node : counter[17] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.234 -Data Delay : 0.707 - -Slack : 0.390 -From Node : counter[7] -To Node : counter[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.234 -Data Delay : 0.708 - -Slack : 0.434 -From Node : counter[20] -To Node : counter[21] +Slack : 0.360 +From Node : address[1] +To Node : address[2] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.045 -Data Delay : 0.563 +Data Delay : 0.489 -Slack : 0.435 +Slack : 0.361 From Node : counter[18] -To Node : counter[19] +To Node : counter[18] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.564 +Clock Skew : 0.037 +Data Delay : 0.482 -Slack : 0.438 -From Node : counter[14] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.235 -Data Delay : 0.757 - -Slack : 0.439 +Slack : 0.361 From Node : counter[16] -To Node : counter[22] +To Node : counter[16] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : 0.235 -Data Delay : 0.758 +Clock Skew : 0.037 +Data Delay : 0.482 + +Slack : 0.361 +From Node : counter[15] +To Node : counter[15] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.482 + +Slack : 0.361 +From Node : counter[13] +To Node : counter[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.482 + +Slack : 0.361 +From Node : counter[12] +To Node : counter[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.482 + +Slack : 0.361 +From Node : counter[11] +To Node : counter[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.482 Slack : 0.440 -From Node : counter[12] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.234 -Data Delay : 0.758 - -Slack : 0.441 -From Node : counter[14] -To Node : counter[15] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.562 - -Slack : 0.441 -From Node : counter[4] -To Node : counter[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.562 - -Slack : 0.441 -From Node : counter[14] -To Node : counter[21] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.235 -Data Delay : 0.760 - -Slack : 0.442 -From Node : counter[10] -To Node : counter[11] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.563 - -Slack : 0.442 -From Node : counter[2] -To Node : counter[3] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.563 - -Slack : 0.442 -From Node : counter[6] -To Node : counter[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.563 - -Slack : 0.442 -From Node : counter[16] -To Node : counter[23] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.235 -Data Delay : 0.761 - -Slack : 0.443 -From Node : counter[8] -To Node : counter[9] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.564 - -Slack : 0.443 -From Node : counter[12] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.234 -Data Delay : 0.761 - -Slack : 0.443 -From Node : counter[10] -To Node : counter[17] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.234 -Data Delay : 0.761 - -Slack : 0.443 -From Node : counter[6] -To Node : counter[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.234 -Data Delay : 0.761 - -Slack : 0.444 -From Node : counter[17] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.573 - -Slack : 0.444 -From Node : counter[19] -To Node : counter[20] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.573 - -Slack : 0.446 -From Node : counter[22] -To Node : counter[23] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.575 - -Slack : 0.447 -From Node : counter[26] -To Node : counter[27] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.576 - -Slack : 0.447 -From Node : counter[24] -To Node : counter[25] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.576 - -Slack : 0.447 -From Node : counter[17] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.576 - -Slack : 0.447 -From Node : counter[19] -To Node : counter[21] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.576 - -Slack : 0.451 -From Node : counter[3] -To Node : counter[4] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.572 - -Slack : 0.451 -From Node : counter[11] -To Node : counter[12] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.572 - -Slack : 0.451 From Node : counter[9] To Node : counter[10] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.572 +Data Delay : 0.561 + +Slack : 0.442 +From Node : counter[20] +To Node : address[0] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.235 +Data Delay : 0.761 + +Slack : 0.442 +From Node : counter[1] +To Node : counter[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.563 + +Slack : 0.442 +From Node : counter[3] +To Node : counter[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.563 Slack : 0.451 -From Node : counter[1] -To Node : counter[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.572 - -Slack : 0.452 -From Node : counter[15] -To Node : counter[16] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.573 - -Slack : 0.452 -From Node : counter[5] -To Node : counter[6] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.573 - -Slack : 0.452 -From Node : counter[7] -To Node : counter[8] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.573 - -Slack : 0.452 -From Node : counter[15] -To Node : counter[22] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.235 -Data Delay : 0.771 - -Slack : 0.452 -From Node : counter[11] -To Node : counter[18] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.234 -Data Delay : 0.770 - -Slack : 0.452 -From Node : counter[0] -To Node : counter[2] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.573 - -Slack : 0.454 -From Node : counter[3] -To Node : counter[5] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.575 - -Slack : 0.454 -From Node : counter[9] -To Node : counter[11] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.575 - -Slack : 0.454 -From Node : counter[1] -To Node : counter[3] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.575 - -Slack : 0.455 -From Node : counter[25] -To Node : counter[26] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.584 - -Slack : 0.455 -From Node : counter[5] -To Node : counter[7] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.037 -Data Delay : 0.576 - -Slack : 0.455 -From Node : counter[15] -To Node : counter[23] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.235 -Data Delay : 0.774 - -Slack : 0.455 -From Node : counter[7] +From Node : counter[8] To Node : counter[9] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.037 -Data Delay : 0.576 +Data Delay : 0.572 -Slack : 0.455 -From Node : counter[11] -To Node : counter[19] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.234 -Data Delay : 0.773 - -Slack : 0.455 -From Node : counter[9] -To Node : counter[17] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.234 -Data Delay : 0.773 - -Slack : 0.455 +Slack : 0.451 From Node : counter[0] +To Node : counter[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.572 + +Slack : 0.451 +From Node : counter[10] +To Node : counter[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.572 + +Slack : 0.452 +From Node : counter[2] To Node : counter[3] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.037 +Data Delay : 0.573 + +Slack : 0.454 +From Node : counter[10] +To Node : counter[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.575 + +Slack : 0.454 +From Node : counter[8] +To Node : counter[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.575 + +Slack : 0.454 +From Node : counter[0] +To Node : counter[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.575 + +Slack : 0.455 +From Node : counter[2] +To Node : counter[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 Data Delay : 0.576 -Slack : 0.456 -From Node : counter[21] -To Node : counter[22] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.585 - -Slack : 0.456 -From Node : counter[5] -To Node : counter[13] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.234 -Data Delay : 0.774 - -Slack : 0.457 -From Node : counter[23] -To Node : counter[24] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.586 - -Slack : 0.458 -From Node : counter[25] -To Node : counter[27] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.587 - -Slack : 0.459 -From Node : counter[21] -To Node : counter[23] -Launch Clock : CLOCK_50 -Latch Clock : CLOCK_50 -Relationship : 0.000 -Clock Skew : 0.045 -Data Delay : 0.588 - Slack : 0.460 -From Node : counter[23] -To Node : counter[25] +From Node : address[0] +To Node : address[1] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 Clock Skew : 0.045 Data Delay : 0.589 -Slack : 0.469 -From Node : counter[24] -To Node : LED[3]~reg0 +Slack : 0.503 +From Node : counter[9] +To Node : counter[11] Launch Clock : CLOCK_50 Latch Clock : CLOCK_50 Relationship : 0.000 -Clock Skew : -0.152 -Data Delay : 0.401 +Clock Skew : 0.037 +Data Delay : 0.624 + +Slack : 0.505 +From Node : counter[3] +To Node : counter[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.626 + +Slack : 0.505 +From Node : counter[1] +To Node : counter[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.626 + +Slack : 0.506 +From Node : counter[9] +To Node : counter[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.627 + +Slack : 0.508 +From Node : counter[19] +To Node : counter[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.629 + +Slack : 0.508 +From Node : counter[7] +To Node : counter[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.629 + +Slack : 0.508 +From Node : counter[3] +To Node : counter[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.629 + +Slack : 0.508 +From Node : counter[1] +To Node : counter[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.629 + +Slack : 0.509 +From Node : counter[17] +To Node : counter[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.630 + +Slack : 0.509 +From Node : counter[5] +To Node : counter[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.630 + +Slack : 0.510 +From Node : counter[13] +To Node : counter[14] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.631 + +Slack : 0.510 +From Node : counter[15] +To Node : counter[16] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.631 + +Slack : 0.510 +From Node : counter[11] +To Node : counter[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.631 + +Slack : 0.517 +From Node : counter[14] +To Node : counter[15] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.638 + +Slack : 0.517 +From Node : counter[10] +To Node : counter[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.638 + +Slack : 0.517 +From Node : counter[8] +To Node : counter[11] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.638 + +Slack : 0.517 +From Node : counter[0] +To Node : counter[3] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.638 + +Slack : 0.518 +From Node : counter[6] +To Node : counter[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.639 + +Slack : 0.518 +From Node : counter[4] +To Node : counter[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.639 + +Slack : 0.518 +From Node : counter[2] +To Node : counter[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.639 + +Slack : 0.519 +From Node : counter[18] +To Node : counter[19] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.640 + +Slack : 0.519 +From Node : counter[16] +To Node : counter[17] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.640 + +Slack : 0.519 +From Node : counter[12] +To Node : counter[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.640 + +Slack : 0.520 +From Node : counter[8] +To Node : counter[12] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.641 + +Slack : 0.520 +From Node : counter[0] +To Node : counter[4] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.641 + +Slack : 0.520 +From Node : counter[10] +To Node : counter[14] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.641 + +Slack : 0.520 +From Node : counter[14] +To Node : counter[16] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.641 + +Slack : 0.521 +From Node : counter[6] +To Node : counter[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.642 + +Slack : 0.521 +From Node : counter[4] +To Node : counter[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.642 + +Slack : 0.521 +From Node : counter[2] +To Node : counter[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.642 + +Slack : 0.522 +From Node : counter[18] +To Node : counter[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.643 + +Slack : 0.522 +From Node : counter[16] +To Node : counter[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.643 + +Slack : 0.522 +From Node : counter[12] +To Node : counter[14] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.643 + +Slack : 0.569 +From Node : counter[20] +To Node : address[2] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.235 +Data Delay : 0.888 + +Slack : 0.569 +From Node : counter[9] +To Node : counter[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.690 + +Slack : 0.571 +From Node : counter[19] +To Node : address[1] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.235 +Data Delay : 0.890 + +Slack : 0.571 +From Node : counter[7] +To Node : counter[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.692 + +Slack : 0.571 +From Node : counter[3] +To Node : counter[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.692 + +Slack : 0.571 +From Node : counter[1] +To Node : counter[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.692 + +Slack : 0.572 +From Node : counter[17] +To Node : counter[19] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.693 + +Slack : 0.572 +From Node : counter[9] +To Node : counter[14] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.693 + +Slack : 0.572 +From Node : counter[5] +To Node : counter[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.693 + +Slack : 0.573 +From Node : counter[13] +To Node : counter[15] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.694 + +Slack : 0.573 +From Node : counter[11] +To Node : counter[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.694 + +Slack : 0.573 +From Node : counter[15] +To Node : counter[17] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.694 + +Slack : 0.574 +From Node : counter[7] +To Node : counter[10] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.695 + +Slack : 0.574 +From Node : counter[3] +To Node : counter[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.695 + +Slack : 0.574 +From Node : counter[1] +To Node : counter[6] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.695 + +Slack : 0.575 +From Node : counter[17] +To Node : counter[20] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.696 + +Slack : 0.575 +From Node : counter[5] +To Node : counter[8] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.696 + +Slack : 0.576 +From Node : counter[11] +To Node : counter[14] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.697 + +Slack : 0.576 +From Node : counter[13] +To Node : counter[16] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.697 + +Slack : 0.576 +From Node : counter[15] +To Node : counter[18] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.697 + +Slack : 0.583 +From Node : counter[8] +To Node : counter[13] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.704 + +Slack : 0.583 +From Node : counter[0] +To Node : counter[5] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.704 + +Slack : 0.583 +From Node : counter[10] +To Node : counter[15] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.704 + +Slack : 0.583 +From Node : counter[14] +To Node : counter[17] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.704 + +Slack : 0.584 +From Node : counter[6] +To Node : counter[9] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.705 + +Slack : 0.584 +From Node : counter[4] +To Node : counter[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.705 + +Slack : 0.584 +From Node : counter[2] +To Node : counter[7] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.705 + +Slack : 0.585 +From Node : counter[16] +To Node : counter[19] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.706 + +Slack : 0.585 +From Node : counter[12] +To Node : counter[15] +Launch Clock : CLOCK_50 +Latch Clock : CLOCK_50 +Relationship : 0.000 +Clock Skew : 0.037 +Data Delay : 0.706 +--------------------------------------------------------------------------------+ @@ -7611,7 +7639,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : LED[0]~reg0 +Target : address[0] Slack : -1.000 Actual Width : 1.000 @@ -7619,7 +7647,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : LED[1]~reg0 +Target : address[1] Slack : -1.000 Actual Width : 1.000 @@ -7627,39 +7655,7 @@ Required Width : 2.000 Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : LED[2]~reg0 - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : LED[3]~reg0 - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : LED[4]~reg0 - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : LED[5]~reg0 - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : LED[6]~reg0 +Target : address[2] Slack : -1.000 Actual Width : 1.000 @@ -7765,62 +7761,6 @@ Clock : CLOCK_50 Clock Edge : Rise Target : counter[20] -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[21] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[22] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[23] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[24] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[25] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[26] - -Slack : -1.000 -Actual Width : 1.000 -Required Width : 2.000 -Type : Min Period -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[27] - Slack : -1.000 Actual Width : 1.000 Required Width : 2.000 @@ -7885,181 +7825,173 @@ Clock : CLOCK_50 Clock Edge : Rise Target : counter[9] -Slack : -0.251 -Actual Width : -0.067 -Required Width : 0.184 -Type : Low Pulse Width +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : counter[13] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[0] -Slack : -0.251 -Actual Width : -0.067 -Required Width : 0.184 -Type : Low Pulse Width +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : counter[17] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[1] -Slack : -0.251 -Actual Width : -0.067 -Required Width : 0.184 -Type : Low Pulse Width +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : counter[18] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[2] -Slack : -0.251 -Actual Width : -0.067 -Required Width : 0.184 -Type : Low Pulse Width +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : counter[19] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[3] -Slack : -0.251 -Actual Width : -0.067 -Required Width : 0.184 -Type : Low Pulse Width +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : counter[20] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[4] -Slack : -0.251 -Actual Width : -0.067 -Required Width : 0.184 -Type : Low Pulse Width +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : counter[21] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[5] -Slack : -0.251 -Actual Width : -0.067 -Required Width : 0.184 -Type : Low Pulse Width +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : counter[22] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[6] -Slack : -0.251 -Actual Width : -0.067 -Required Width : 0.184 -Type : Low Pulse Width +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : counter[23] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[7] -Slack : -0.251 -Actual Width : -0.067 -Required Width : 0.184 -Type : Low Pulse Width +Slack : -1.000 +Actual Width : 1.000 +Required Width : 2.000 +Type : Min Period Clock : CLOCK_50 Clock Edge : Rise -Target : counter[24] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 -Slack : -0.251 -Actual Width : -0.067 -Required Width : 0.184 +Slack : -0.291 +Actual Width : -0.061 +Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : counter[25] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ram_block1a0~porta_address_reg0 -Slack : -0.251 -Actual Width : -0.067 -Required Width : 0.184 +Slack : -0.290 +Actual Width : -0.060 +Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : counter[26] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[0] -Slack : -0.251 -Actual Width : -0.067 -Required Width : 0.184 +Slack : -0.290 +Actual Width : -0.060 +Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : counter[27] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[1] -Slack : -0.227 -Actual Width : -0.043 -Required Width : 0.184 +Slack : -0.290 +Actual Width : -0.060 +Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : LED[1]~reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[2] -Slack : -0.227 -Actual Width : -0.043 -Required Width : 0.184 +Slack : -0.290 +Actual Width : -0.060 +Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : LED[2]~reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[3] -Slack : -0.227 -Actual Width : -0.043 -Required Width : 0.184 +Slack : -0.290 +Actual Width : -0.060 +Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : LED[3]~reg0 +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[4] -Slack : -0.227 -Actual Width : -0.043 -Required Width : 0.184 +Slack : -0.290 +Actual Width : -0.060 +Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : counter[14] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[5] -Slack : -0.227 -Actual Width : -0.043 -Required Width : 0.184 +Slack : -0.290 +Actual Width : -0.060 +Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : counter[15] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[6] -Slack : -0.227 -Actual Width : -0.043 -Required Width : 0.184 +Slack : -0.290 +Actual Width : -0.060 +Required Width : 0.230 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : counter[16] +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[7] -Slack : -0.226 -Actual Width : -0.042 +Slack : -0.250 +Actual Width : -0.066 Required Width : 0.184 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : LED[0]~reg0 +Target : address[0] -Slack : -0.226 -Actual Width : -0.042 +Slack : -0.250 +Actual Width : -0.066 Required Width : 0.184 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : LED[4]~reg0 +Target : address[1] -Slack : -0.226 -Actual Width : -0.042 +Slack : -0.250 +Actual Width : -0.066 Required Width : 0.184 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : LED[5]~reg0 - -Slack : -0.226 -Actual Width : -0.042 -Required Width : 0.184 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : LED[6]~reg0 +Target : address[2] Slack : -0.226 Actual Width : -0.042 @@ -8093,6 +8025,62 @@ Clock : CLOCK_50 Clock Edge : Rise Target : counter[12] +Slack : -0.226 +Actual Width : -0.042 +Required Width : 0.184 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[13] + +Slack : -0.226 +Actual Width : -0.042 +Required Width : 0.184 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[14] + +Slack : -0.226 +Actual Width : -0.042 +Required Width : 0.184 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[15] + +Slack : -0.226 +Actual Width : -0.042 +Required Width : 0.184 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[16] + +Slack : -0.226 +Actual Width : -0.042 +Required Width : 0.184 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[17] + +Slack : -0.226 +Actual Width : -0.042 +Required Width : 0.184 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[18] + +Slack : -0.226 +Actual Width : -0.042 +Required Width : 0.184 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[19] + Slack : -0.226 Actual Width : -0.042 Required Width : 0.184 @@ -8101,6 +8089,14 @@ Clock : CLOCK_50 Clock Edge : Rise Target : counter[1] +Slack : -0.226 +Actual Width : -0.042 +Required Width : 0.184 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[20] + Slack : -0.226 Actual Width : -0.042 Required Width : 0.184 @@ -8165,101 +8161,29 @@ Clock : CLOCK_50 Clock Edge : Rise Target : counter[9] -Slack : -0.071 -Actual Width : -0.071 +Slack : -0.070 +Actual Width : -0.070 Required Width : 0.000 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : counter[13]|clk +Target : address[0]|clk -Slack : -0.071 -Actual Width : -0.071 +Slack : -0.070 +Actual Width : -0.070 Required Width : 0.000 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : counter[17]|clk +Target : address[1]|clk -Slack : -0.071 -Actual Width : -0.071 +Slack : -0.070 +Actual Width : -0.070 Required Width : 0.000 Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise -Target : counter[18]|clk - -Slack : -0.071 -Actual Width : -0.071 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[19]|clk - -Slack : -0.071 -Actual Width : -0.071 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[20]|clk - -Slack : -0.071 -Actual Width : -0.071 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[21]|clk - -Slack : -0.071 -Actual Width : -0.071 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[22]|clk - -Slack : -0.071 -Actual Width : -0.071 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[23]|clk - -Slack : -0.071 -Actual Width : -0.071 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[24]|clk - -Slack : -0.071 -Actual Width : -0.071 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[25]|clk - -Slack : -0.071 -Actual Width : -0.071 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[26]|clk - -Slack : -0.071 -Actual Width : -0.071 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[27]|clk +Target : address[2]|clk Slack : -0.051 Actual Width : -0.051 @@ -8269,54 +8193,6 @@ Clock : CLOCK_50 Clock Edge : Rise Target : CLOCK_50~input|o -Slack : -0.048 -Actual Width : -0.048 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[14]|clk - -Slack : -0.048 -Actual Width : -0.048 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[15]|clk - -Slack : -0.048 -Actual Width : -0.048 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : counter[16]|clk - -Slack : -0.047 -Actual Width : -0.047 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : LED[1]~reg0|clk - -Slack : -0.047 -Actual Width : -0.047 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : LED[2]~reg0|clk - -Slack : -0.047 -Actual Width : -0.047 -Required Width : 0.000 -Type : Low Pulse Width -Clock : CLOCK_50 -Clock Edge : Rise -Target : LED[3]~reg0|clk - Slack : -0.047 Actual Width : -0.047 Required Width : 0.000 @@ -8349,6 +8225,62 @@ Clock : CLOCK_50 Clock Edge : Rise Target : counter[12]|clk +Slack : -0.047 +Actual Width : -0.047 +Required Width : 0.000 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[13]|clk + +Slack : -0.047 +Actual Width : -0.047 +Required Width : 0.000 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[14]|clk + +Slack : -0.047 +Actual Width : -0.047 +Required Width : 0.000 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[15]|clk + +Slack : -0.047 +Actual Width : -0.047 +Required Width : 0.000 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[16]|clk + +Slack : -0.047 +Actual Width : -0.047 +Required Width : 0.000 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[17]|clk + +Slack : -0.047 +Actual Width : -0.047 +Required Width : 0.000 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[18]|clk + +Slack : -0.047 +Actual Width : -0.047 +Required Width : 0.000 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[19]|clk + Slack : -0.047 Actual Width : -0.047 Required Width : 0.000 @@ -8357,6 +8289,14 @@ Clock : CLOCK_50 Clock Edge : Rise Target : counter[1]|clk +Slack : -0.047 +Actual Width : -0.047 +Required Width : 0.000 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[20]|clk + Slack : -0.047 Actual Width : -0.047 Required Width : 0.000 @@ -8396,6 +8336,94 @@ Type : Low Pulse Width Clock : CLOCK_50 Clock Edge : Rise Target : counter[6]|clk + +Slack : -0.047 +Actual Width : -0.047 +Required Width : 0.000 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[7]|clk + +Slack : -0.047 +Actual Width : -0.047 +Required Width : 0.000 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[8]|clk + +Slack : -0.047 +Actual Width : -0.047 +Required Width : 0.000 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : counter[9]|clk + +Slack : -0.047 +Actual Width : -0.047 +Required Width : 0.000 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom|altsyncram_component|auto_generated|ram_block1a0|clk0 + +Slack : -0.039 +Actual Width : -0.039 +Required Width : 0.000 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : CLOCK_50~inputclkctrl|inclk[0] + +Slack : -0.039 +Actual Width : -0.039 +Required Width : 0.000 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : CLOCK_50~inputclkctrl|outclk + +Slack : 0.500 +Actual Width : 0.500 +Required Width : 0.000 +Type : High Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : CLOCK_50~input|i + +Slack : 0.500 +Actual Width : 0.500 +Required Width : 0.000 +Type : Low Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : CLOCK_50~input|i + +Slack : 0.824 +Actual Width : 1.054 +Required Width : 0.230 +Type : High Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[0] + +Slack : 0.824 +Actual Width : 1.054 +Required Width : 0.230 +Type : High Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[1] + +Slack : 0.824 +Actual Width : 1.054 +Required Width : 0.230 +Type : High Pulse Width +Clock : CLOCK_50 +Clock Edge : Rise +Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|q_a[2] +--------------------------------------------------------------------------------+ @@ -8405,57 +8433,64 @@ Target : counter[6]|clk +--------------------------------------------------------------------------------+ Data Port : LED[*] Clock Port : CLOCK_50 -Rise : 5.723 -Fall : 5.678 +Rise : 5.428 +Fall : 5.282 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[0] Clock Port : CLOCK_50 -Rise : 3.173 -Fall : 3.159 +Rise : 3.889 +Fall : 3.919 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[1] Clock Port : CLOCK_50 -Rise : 3.305 -Fall : 3.303 +Rise : 3.916 +Fall : 3.960 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[2] Clock Port : CLOCK_50 -Rise : 3.295 -Fall : 3.291 +Rise : 4.151 +Fall : 4.211 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[3] Clock Port : CLOCK_50 -Rise : 3.174 -Fall : 3.161 +Rise : 3.921 +Fall : 3.944 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[4] Clock Port : CLOCK_50 -Rise : 4.301 -Fall : 4.440 +Rise : 4.131 +Fall : 4.186 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[5] Clock Port : CLOCK_50 -Rise : 5.723 -Fall : 5.678 +Rise : 5.330 +Fall : 5.170 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[6] Clock Port : CLOCK_50 -Rise : 3.602 -Fall : 3.688 +Rise : 4.099 +Fall : 4.184 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : LED[7] +Clock Port : CLOCK_50 +Rise : 5.428 +Fall : 5.282 Clock Edge : Rise Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ @@ -8467,57 +8502,64 @@ Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ Data Port : LED[*] Clock Port : CLOCK_50 -Rise : 3.068 -Fall : 3.052 +Rise : 3.755 +Fall : 3.781 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[0] Clock Port : CLOCK_50 -Rise : 3.068 -Fall : 3.052 +Rise : 3.755 +Fall : 3.781 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[1] Clock Port : CLOCK_50 -Rise : 3.194 -Fall : 3.189 +Rise : 3.780 +Fall : 3.821 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[2] Clock Port : CLOCK_50 -Rise : 3.184 -Fall : 3.177 +Rise : 4.006 +Fall : 4.062 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[3] Clock Port : CLOCK_50 -Rise : 3.068 -Fall : 3.052 +Rise : 3.785 +Fall : 3.805 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[4] Clock Port : CLOCK_50 -Rise : 4.154 -Fall : 4.284 +Rise : 3.991 +Fall : 4.041 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[5] Clock Port : CLOCK_50 -Rise : 5.577 -Fall : 5.523 +Rise : 5.199 +Fall : 5.036 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[6] Clock Port : CLOCK_50 -Rise : 3.480 -Fall : 3.561 +Rise : 3.957 +Fall : 4.036 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : LED[7] +Clock Port : CLOCK_50 +Rise : 5.294 +Fall : 5.143 Clock Edge : Rise Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ @@ -8534,32 +8576,32 @@ No synchronizer chains to report. ; Multicorner Timing Analysis Summary ; +--------------------------------------------------------------------------------+ Clock : Worst-case Slack -Setup : -1.606 -Hold : 0.193 +Setup : -2.763 +Hold : 0.178 Recovery : N/A Removal : N/A Minimum Pulse Width : -3.000 Clock : CLOCK_50 -Setup : -1.606 -Hold : 0.193 +Setup : -2.763 +Hold : 0.178 Recovery : N/A Removal : N/A Minimum Pulse Width : -3.000 Clock : Design-wide TNS -Setup : -30.234 +Setup : -43.394 Hold : 0.0 Recovery : 0.0 Removal : 0.0 -Minimum Pulse Width : -48.277 +Minimum Pulse Width : -46.633 Clock : CLOCK_50 -Setup : -30.234 +Setup : -43.394 Hold : 0.000 Recovery : N/A Removal : N/A -Minimum Pulse Width : -48.277 +Minimum Pulse Width : -46.633 +--------------------------------------------------------------------------------+ @@ -8569,57 +8611,64 @@ Minimum Pulse Width : -48.277 +--------------------------------------------------------------------------------+ Data Port : LED[*] Clock Port : CLOCK_50 -Rise : 9.276 -Fall : 9.028 +Rise : 8.682 +Fall : 8.416 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[0] Clock Port : CLOCK_50 -Rise : 5.406 -Fall : 5.347 +Rise : 6.626 +Fall : 6.525 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[1] Clock Port : CLOCK_50 -Rise : 5.653 -Fall : 5.580 +Rise : 6.680 +Fall : 6.629 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[2] Clock Port : CLOCK_50 -Rise : 5.633 -Fall : 5.560 +Rise : 7.094 +Fall : 7.015 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[3] Clock Port : CLOCK_50 -Rise : 5.406 -Fall : 5.347 +Rise : 6.726 +Fall : 6.609 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[4] Clock Port : CLOCK_50 -Rise : 7.391 -Fall : 7.410 +Rise : 7.077 +Fall : 7.019 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[5] Clock Port : CLOCK_50 -Rise : 9.276 -Fall : 9.028 +Rise : 8.550 +Fall : 8.235 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[6] Clock Port : CLOCK_50 -Rise : 6.114 -Fall : 6.176 +Rise : 7.046 +Fall : 6.990 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : LED[7] +Clock Port : CLOCK_50 +Rise : 8.682 +Fall : 8.416 Clock Edge : Rise Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ @@ -8631,57 +8680,64 @@ Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ Data Port : LED[*] Clock Port : CLOCK_50 -Rise : 3.068 -Fall : 3.052 +Rise : 3.755 +Fall : 3.781 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[0] Clock Port : CLOCK_50 -Rise : 3.068 -Fall : 3.052 +Rise : 3.755 +Fall : 3.781 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[1] Clock Port : CLOCK_50 -Rise : 3.194 -Fall : 3.189 +Rise : 3.780 +Fall : 3.821 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[2] Clock Port : CLOCK_50 -Rise : 3.184 -Fall : 3.177 +Rise : 4.006 +Fall : 4.062 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[3] Clock Port : CLOCK_50 -Rise : 3.068 -Fall : 3.052 +Rise : 3.785 +Fall : 3.805 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[4] Clock Port : CLOCK_50 -Rise : 4.154 -Fall : 4.284 +Rise : 3.991 +Fall : 4.041 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[5] Clock Port : CLOCK_50 -Rise : 5.577 -Fall : 5.523 +Rise : 5.199 +Fall : 5.036 Clock Edge : Rise Clock Reference : CLOCK_50 Data Port : LED[6] Clock Port : CLOCK_50 -Rise : 3.480 -Fall : 3.561 +Rise : 3.957 +Fall : 4.036 +Clock Edge : Rise +Clock Reference : CLOCK_50 + +Data Port : LED[7] +Clock Port : CLOCK_50 +Rise : 5.294 +Fall : 5.143 Clock Edge : Rise Clock Reference : CLOCK_50 +--------------------------------------------------------------------------------+ @@ -9723,7 +9779,7 @@ Monotonic Fall at Far-end : Yes +--------------------------------------------------------------------------------+ From Clock : CLOCK_50 To Clock : CLOCK_50 -RR Paths : 413 +RR Paths : 941 FR Paths : 0 RF Paths : 0 FF Paths : 0 @@ -9737,7 +9793,7 @@ Entries labeled "false path" only account for clock-to-clock false paths and not +--------------------------------------------------------------------------------+ From Clock : CLOCK_50 To Clock : CLOCK_50 -RR Paths : 413 +RR Paths : 941 FR Paths : 0 RF Paths : 0 FF Paths : 0 @@ -9778,12 +9834,12 @@ Setup : 0 Hold : 0 Property : Unconstrained Output Ports -Setup : 7 -Hold : 7 +Setup : 8 +Hold : 8 Property : Unconstrained Output Port Paths -Setup : 7 -Hold : 7 +Setup : 8 +Hold : 8 +--------------------------------------------------------------------------------+ @@ -9794,7 +9850,7 @@ Hold : 7 Info: ******************************************************************* Info: Running Quartus II 32-bit TimeQuest Timing Analyzer Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition - Info: Processing started: Wed Mar 30 11:51:39 2022 + Info: Processing started: Wed Mar 30 12:38:38 2022 Info: Command: quartus_sta spectrum -c spectrum Info: qsta_default_script.tcl version: #1 Warning (20028): Parallel compilation is not licensed and has been disabled @@ -9811,63 +9867,63 @@ Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Info: Analyzing Slow 1200mV 85C Model Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. -Info (332146): Worst-case setup slack is -1.606 +Info (332146): Worst-case setup slack is -2.763 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -1.606 -30.234 CLOCK_50 -Info (332146): Worst-case hold slack is 0.360 + Info (332119): -2.763 -43.394 CLOCK_50 +Info (332146): Worst-case hold slack is 0.343 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 0.360 0.000 CLOCK_50 + Info (332119): 0.343 0.000 CLOCK_50 Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is -3.000 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -3.000 -38.000 CLOCK_50 + Info (332119): -3.000 -46.633 CLOCK_50 Info: Analyzing Slow 1200mV 0C Model Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. -Info (332146): Worst-case setup slack is -1.275 +Info (332146): Worst-case setup slack is -2.331 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -1.275 -22.690 CLOCK_50 -Info (332146): Worst-case hold slack is 0.319 + Info (332119): -2.331 -34.994 CLOCK_50 +Info (332146): Worst-case hold slack is 0.299 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 0.319 0.000 CLOCK_50 + Info (332119): 0.299 0.000 CLOCK_50 Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is -3.000 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -3.000 -38.000 CLOCK_50 + Info (332119): -3.000 -46.624 CLOCK_50 Info: Analyzing Fast 1200mV 0C Model Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. -Info (332146): Worst-case setup slack is -0.500 +Info (332146): Worst-case setup slack is -1.122 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -0.500 -4.764 CLOCK_50 -Info (332146): Worst-case hold slack is 0.193 + Info (332119): -1.122 -9.363 CLOCK_50 +Info (332146): Worst-case hold slack is 0.178 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 0.193 0.000 CLOCK_50 + Info (332119): 0.178 0.000 CLOCK_50 Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is -3.000 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -3.000 -48.277 CLOCK_50 + Info (332119): -3.000 -45.480 CLOCK_50 Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings - Info: Peak virtual memory: 412 megabytes - Info: Processing ended: Wed Mar 30 11:51:41 2022 + Info: Peak virtual memory: 415 megabytes + Info: Processing ended: Wed Mar 30 12:38:40 2022 Info: Elapsed time: 00:00:02 Info: Total CPU time (on all processors): 00:00:02 diff --git a/output_files/spectrum.sta.summary b/output_files/spectrum.sta.summary index 53ba926..97ccdb9 100644 --- a/output_files/spectrum.sta.summary +++ b/output_files/spectrum.sta.summary @@ -3,39 +3,39 @@ TimeQuest Timing Analyzer Summary ------------------------------------------------------------ Type : Slow 1200mV 85C Model Setup 'CLOCK_50' -Slack : -1.606 -TNS : -30.234 +Slack : -2.763 +TNS : -43.394 Type : Slow 1200mV 85C Model Hold 'CLOCK_50' -Slack : 0.360 +Slack : 0.343 TNS : 0.000 Type : Slow 1200mV 85C Model Minimum Pulse Width 'CLOCK_50' Slack : -3.000 -TNS : -38.000 +TNS : -46.633 Type : Slow 1200mV 0C Model Setup 'CLOCK_50' -Slack : -1.275 -TNS : -22.690 +Slack : -2.331 +TNS : -34.994 Type : Slow 1200mV 0C Model Hold 'CLOCK_50' -Slack : 0.319 +Slack : 0.299 TNS : 0.000 Type : Slow 1200mV 0C Model Minimum Pulse Width 'CLOCK_50' Slack : -3.000 -TNS : -38.000 +TNS : -46.624 Type : Fast 1200mV 0C Model Setup 'CLOCK_50' -Slack : -0.500 -TNS : -4.764 +Slack : -1.122 +TNS : -9.363 Type : Fast 1200mV 0C Model Hold 'CLOCK_50' -Slack : 0.193 +Slack : 0.178 TNS : 0.000 Type : Fast 1200mV 0C Model Minimum Pulse Width 'CLOCK_50' Slack : -3.000 -TNS : -48.277 +TNS : -45.480 ------------------------------------------------------------ diff --git a/rom0.cnx b/rom0.cnx new file mode 100644 index 0000000..f793609 --- /dev/null +++ b/rom0.cnx @@ -0,0 +1,98 @@ +VERSION: WM1.0 +MODULE: altsyncram +PRIVATE: ADDRESSSTALL_A NUMERIC "0" +PRIVATE: AclrAddr NUMERIC "0" +PRIVATE: AclrByte NUMERIC "0" +PRIVATE: AclrOutput NUMERIC "0" +PRIVATE: BYTE_ENABLE NUMERIC "0" +PRIVATE: BYTE_SIZE NUMERIC "8" +PRIVATE: BlankMemory NUMERIC "0" +PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +PRIVATE: Clken NUMERIC "0" +PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +PRIVATE: INIT_TO_SIM_X NUMERIC "0" +PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +PRIVATE: JTAG_ENABLED NUMERIC "0" +PRIVATE: JTAG_ID STRING "NONE" +PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +PRIVATE: MIFfilename STRING "led_patterns.mif" +PRIVATE: NUMWORDS_A NUMERIC "8" +PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +PRIVATE: RegAddr NUMERIC "1" +PRIVATE: RegOutput NUMERIC "1" +PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +PRIVATE: SingleClock NUMERIC "1" +PRIVATE: UseDQRAM NUMERIC "0" +PRIVATE: WidthAddr NUMERIC "3" +PRIVATE: WidthData NUMERIC "8" +PRIVATE: rden NUMERIC "0" +LIBRARY: altera_mf altera_mf.altera_mf_components.all +CONSTANT: ADDRESS_ACLR_A STRING "NONE" +CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +CONSTANT: INIT_FILE STRING "led_patterns.mif" +CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +CONSTANT: LPM_TYPE STRING "altsyncram" +CONSTANT: NUMWORDS_A NUMERIC "8" +CONSTANT: OPERATION_MODE STRING "ROM" +CONSTANT: OUTDATA_ACLR_A STRING "NONE" +CONSTANT: OUTDATA_REG_A STRING "CLOCK0" +CONSTANT: WIDTHAD_A NUMERIC "3" +CONSTANT: WIDTH_A NUMERIC "8" +CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +USED_PORT: address 0 0 3 0 INPUT NODEFVAL "address[2..0]" +USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" +CONNECT: @address_a 0 0 3 0 address 0 0 3 0 +CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +CONNECT: q 0 0 8 0 @q_a 0 0 8 0 +GEN_FILE: TYPE_NORMAL rom0.v TRUE +GEN_FILE: TYPE_NORMAL rom0.inc FALSE +GEN_FILE: TYPE_NORMAL rom0.cmp FALSE +GEN_FILE: TYPE_NORMAL rom0.bsf FALSE +GEN_FILE: TYPE_NORMAL rom0_inst.v FALSE +GEN_FILE: TYPE_NORMAL rom0_bb.v TRUE +LIB_FILE: altera_mf + +LICENSE_ID: "DEVICE_FAMILY_Cyclone III" 30229803K6032210322T +LICENSE_ID: "DEVICE_FAMILY_Cyclone IV E" 30229803A6032210322A +LICENSE_ID: "DEVICE_FAMILY_Cyclone V" 30229803A6032210322B +LICENSE_ID: "DEVICE_FAMILY_Cyclone IV GX" 30229803A6032210322B +LICENSE_ID: "DEVICE_FAMILY_Cyclone III LS" 30229803A6032210322B +LICENSE_ID: "FEATURE_STRATIXGX_DPA" 30229803M6032210322T +LICENSE_ID: "FEATURE_STRATIXGX_BASIC" 30229803A6032210322B + + +SUPPORTED_DEVICE_FAMILY: "Cyclone III" +SUPPORTED_DEVICE_FAMILY: "Cyclone IV E" +SUPPORTED_DEVICE_FAMILY: "Cyclone V" +SUPPORTED_DEVICE_FAMILY: "Cyclone IV GX" +SUPPORTED_DEVICE_FAMILY: "Cyclone III LS" +SUPPORTED_DEVICE_FAMILY: "Cyclone IV E" + +WIZARD_TITLE: "ROM: 1-PORT" +QUARTUS_VERSION: "Version 13.1" +QUARTUS_SVERSION: "13.1.0 Build 162 10/23/2013 SJ Web Edition:10/23/2013" +QUARTUS_BUILD_DATE: "10/23/2013" +ALTERA_COPYRIGHT: "Copyright (C) 1991-2013 Altera Corporation" +RESC_INFO: ON + + +HELP_MENU_ITEM: FALSE "IUG_ALIAS$STRATIX_WEB_LINK$http://www.altera.com/literature/hb/stx/ch_3_vol_2.pdf" +HELP_MENU_ITEM: FALSE "ALIAS$STRATIX_WEB_MENU_LABEL$TriMatrix Memory Blocks in Stratix (GX)" +HELP_MENU_ITEM: FALSE "IUG_ALIAS$CYCLONE_IV_WEB_LINK$http://www.altera.com/literature/hb/cyclone-iv/cyiv-51003.pdf" +HELP_MENU_ITEM: FALSE "ALIAS$CYCLONE_IV_WEB_MENU_LABEL$Cyclone IV Memory Blocks" +HELP_MENU_ITEM: FALSE "IUG_ALIAS$CYCLONEII_WEB_LINK$http://www.altera.com/literature/hb/cyc2/cyc2_cii51008.pdf" +HELP_MENU_ITEM: FALSE "ALIAS$CYCLONEII_WEB_MENU_LABEL$Cyclone II Memory Blocks" +HELP_MENU_ITEM: FALSE "IUG_ALIAS$CYCLONE_WEB_LINK$http://www.altera.com/literature/hb/cyc/cyc_c51007.pdf" +HELP_MENU_ITEM: FALSE "ALIAS$CYCLONE_WEB_MENU_LABEL$Memory Implementations Using Cyclone Memory Blocks" +HELP_MENU_ITEM: FALSE "IUG_ALIAS$STRATIXII_WEB_LINK$http://www.altera.com/literature/hb/stx2/stx2_sii52002.pdf" +HELP_MENU_ITEM: FALSE "ALIAS$STRATIXII_WEB_MENU_LABEL$TriMatrix Memory Blocks in Stratix II" +HELP_MENU_ITEM: FALSE "IUG_ALIAS$STRATIXIII_WEB_LINK$http://www.altera.com/literature/hb/stx3/stx3_siii51004.pdf" +HELP_MENU_ITEM: FALSE "ALIAS$STRATIXIII_WEB_MENU_LABEL$TriMatrix Embedded Memory Blocks in Stratix III" +HELP_MENU_ITEM: FALSE "IUG_ALIAS$APEX_WEB_LINK$http://www.altera.com/literature/an/an179.pdf" +HELP_MENU_ITEM: FALSE "ALIAS$APEX_WEB_MENU_LABEL$Designing with ESBs" +HELP_MENU_ITEM: FALSE "IUG$ROM Megafunction User Guide$http://www.altera.com/literature/ug/ug_memrom.pdf" diff --git a/rom0.qip b/rom0.qip new file mode 100644 index 0000000..ff32bd6 --- /dev/null +++ b/rom0.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "rom0.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "rom0_bb.v"] diff --git a/rom0.v b/rom0.v new file mode 100644 index 0000000..1e74bb4 --- /dev/null +++ b/rom0.v @@ -0,0 +1,159 @@ +// megafunction wizard: %ROM: 1-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: rom0.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module rom0 ( + address, + clock, + q); + + input [2:0] address; + input clock; + output [7:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [7:0] sub_wire0; + wire [7:0] q = sub_wire0[7:0]; + + altsyncram altsyncram_component ( + .address_a (address), + .clock0 (clock), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_a ({8{1'b1}}), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_a (1'b0), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_a = "NONE", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.init_file = "led_patterns.mif", + altsyncram_component.intended_device_family = "Cyclone IV E", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 8, + altsyncram_component.operation_mode = "ROM", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "CLOCK0", + altsyncram_component.widthad_a = 3, + altsyncram_component.width_a = 8, + altsyncram_component.width_byteena_a = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "0" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "led_patterns.mif" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "3" +// Retrieval info: PRIVATE: WidthData NUMERIC "8" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INIT_FILE STRING "led_patterns.mif" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "3" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: USED_PORT: address 0 0 3 0 INPUT NODEFVAL "address[2..0]" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" +// Retrieval info: CONNECT: @address_a 0 0 3 0 address 0 0 3 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL rom0.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL rom0.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL rom0.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL rom0.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL rom0_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL rom0_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf diff --git a/rom0_bb.v b/rom0_bb.v new file mode 100644 index 0000000..a5d4866 --- /dev/null +++ b/rom0_bb.v @@ -0,0 +1,110 @@ +// megafunction wizard: %ROM: 1-PORT%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: rom0.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + +module rom0 ( + address, + clock, + q); + + input [2:0] address; + input clock; + output [7:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "0" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "led_patterns.mif" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "3" +// Retrieval info: PRIVATE: WidthData NUMERIC "8" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INIT_FILE STRING "led_patterns.mif" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "3" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: USED_PORT: address 0 0 3 0 INPUT NODEFVAL "address[2..0]" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" +// Retrieval info: CONNECT: @address_a 0 0 3 0 address 0 0 3 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL rom0.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL rom0.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL rom0.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL rom0.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL rom0_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL rom0_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf diff --git a/simulation/modelsim/spectrum.vo b/simulation/modelsim/spectrum.vo index d287dcb..59e758e 100644 --- a/simulation/modelsim/spectrum.vo +++ b/simulation/modelsim/spectrum.vo @@ -16,7 +16,7 @@ // PROGRAM "Quartus II 32-bit" // VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" -// DATE "03/30/2022 11:51:43" +// DATE "03/30/2022 12:38:42" // // Device: Altera EP4CE22F17C6 Package FBGA256 @@ -71,80 +71,77 @@ wire \LED[6]~output_o ; wire \LED[7]~output_o ; wire \CLOCK_50~input_o ; wire \CLOCK_50~inputclkctrl_outclk ; -wire \counter[0]~81_combout ; -wire \counter[1]~27_combout ; -wire \counter[1]~28 ; -wire \counter[2]~29_combout ; -wire \counter[2]~30 ; -wire \counter[3]~31_combout ; -wire \counter[3]~32 ; -wire \counter[4]~33_combout ; -wire \counter[4]~34 ; -wire \counter[5]~35_combout ; -wire \counter[5]~36 ; -wire \counter[6]~37_combout ; -wire \counter[6]~38 ; -wire \counter[7]~39_combout ; -wire \counter[7]~40 ; -wire \counter[8]~41_combout ; -wire \counter[8]~42 ; -wire \counter[9]~43_combout ; -wire \counter[9]~44 ; -wire \counter[10]~45_combout ; -wire \counter[10]~46 ; -wire \counter[11]~47_combout ; -wire \counter[11]~48 ; -wire \counter[12]~49_combout ; -wire \counter[12]~50 ; -wire \counter[13]~51_combout ; -wire \counter[13]~52 ; -wire \counter[14]~53_combout ; -wire \counter[14]~54 ; -wire \counter[15]~55_combout ; -wire \counter[15]~56 ; -wire \counter[16]~57_combout ; -wire \counter[16]~58 ; -wire \counter[17]~59_combout ; -wire \counter[17]~60 ; -wire \counter[18]~61_combout ; -wire \counter[18]~62 ; -wire \counter[19]~63_combout ; -wire \counter[19]~64 ; -wire \counter[20]~65_combout ; -wire \counter[20]~66 ; -wire \counter[21]~67_combout ; -wire \LED[0]~reg0feeder_combout ; -wire \LED[0]~reg0_q ; -wire \counter[21]~68 ; -wire \counter[22]~69_combout ; -wire \LED[1]~reg0feeder_combout ; -wire \LED[1]~reg0_q ; -wire \counter[22]~70 ; -wire \counter[23]~71_combout ; -wire \LED[2]~reg0feeder_combout ; -wire \LED[2]~reg0_q ; -wire \counter[23]~72 ; -wire \counter[24]~73_combout ; -wire \LED[3]~reg0feeder_combout ; -wire \LED[3]~reg0_q ; -wire \counter[24]~74 ; -wire \counter[25]~75_combout ; -wire \LED[4]~reg0feeder_combout ; -wire \LED[4]~reg0_q ; -wire \counter[25]~76 ; -wire \counter[26]~77_combout ; -wire \LED[5]~reg0feeder_combout ; -wire \LED[5]~reg0_q ; -wire \counter[26]~78 ; -wire \counter[27]~79_combout ; -wire \LED[6]~reg0feeder_combout ; -wire \LED[6]~reg0_q ; -wire [27:0] counter; +wire \Add0~0_combout ; +wire \Add0~1 ; +wire \Add0~2_combout ; +wire \Add0~3 ; +wire \Add0~4_combout ; +wire \Add0~5 ; +wire \Add0~6_combout ; +wire \Add0~7 ; +wire \Add0~8_combout ; +wire \Add0~9 ; +wire \Add0~10_combout ; +wire \Add0~11 ; +wire \Add0~12_combout ; +wire \Add0~13 ; +wire \Add0~14_combout ; +wire \Add0~15 ; +wire \Add0~16_combout ; +wire \Add0~17 ; +wire \Add0~18_combout ; +wire \Add0~19 ; +wire \Add0~20_combout ; +wire \Add0~21 ; +wire \Add0~22_combout ; +wire \Add0~23 ; +wire \Add0~24_combout ; +wire \Add0~25 ; +wire \Add0~26_combout ; +wire \Add0~27 ; +wire \Add0~28_combout ; +wire \Add0~29 ; +wire \Add0~30_combout ; +wire \Add0~31 ; +wire \Add0~32_combout ; +wire \Add0~33 ; +wire \Add0~34_combout ; +wire \Add0~35 ; +wire \Add0~36_combout ; +wire \Add0~37 ; +wire \Add0~38_combout ; +wire \Add0~39 ; +wire \Add0~40_combout ; +wire \Equal0~5_combout ; +wire \Equal0~1_combout ; +wire \Equal0~0_combout ; +wire \Equal0~2_combout ; +wire \Equal0~3_combout ; +wire \Equal0~4_combout ; +wire \address[0]~0_combout ; +wire \Equal0~6_combout ; +wire \Equal0~7_combout ; +wire \address[1]~1_combout ; +wire \address[1]~2_combout ; +wire \address[2]~3_combout ; +wire [20:0] counter; +wire [2:0] address; +wire [7:0] \rom|altsyncram_component|auto_generated|q_a ; +wire [17:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; + +assign \rom|altsyncram_component|auto_generated|q_a [0] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|q_a [1] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [1]; +assign \rom|altsyncram_component|auto_generated|q_a [2] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [2]; +assign \rom|altsyncram_component|auto_generated|q_a [3] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [3]; +assign \rom|altsyncram_component|auto_generated|q_a [4] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [4]; +assign \rom|altsyncram_component|auto_generated|q_a [5] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [5]; +assign \rom|altsyncram_component|auto_generated|q_a [6] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [6]; +assign \rom|altsyncram_component|auto_generated|q_a [7] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [7]; // Location: IOOBUF_X38_Y34_N16 cycloneive_io_obuf \LED[0]~output ( - .i(\LED[0]~reg0_q ), + .i(\rom|altsyncram_component|auto_generated|q_a [0]), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -157,7 +154,7 @@ defparam \LED[0]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y34_N2 cycloneive_io_obuf \LED[1]~output ( - .i(\LED[1]~reg0_q ), + .i(\rom|altsyncram_component|auto_generated|q_a [1]), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -170,7 +167,7 @@ defparam \LED[1]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y34_N9 cycloneive_io_obuf \LED[2]~output ( - .i(\LED[2]~reg0_q ), + .i(\rom|altsyncram_component|auto_generated|q_a [2]), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -183,7 +180,7 @@ defparam \LED[2]~output .open_drain_output = "false"; // Location: IOOBUF_X40_Y34_N2 cycloneive_io_obuf \LED[3]~output ( - .i(\LED[3]~reg0_q ), + .i(\rom|altsyncram_component|auto_generated|q_a [3]), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -196,7 +193,7 @@ defparam \LED[3]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y25_N9 cycloneive_io_obuf \LED[4]~output ( - .i(\LED[4]~reg0_q ), + .i(\rom|altsyncram_component|auto_generated|q_a [4]), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -209,7 +206,7 @@ defparam \LED[4]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y26_N16 cycloneive_io_obuf \LED[5]~output ( - .i(\LED[5]~reg0_q ), + .i(\rom|altsyncram_component|auto_generated|q_a [5]), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -222,7 +219,7 @@ defparam \LED[5]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y28_N9 cycloneive_io_obuf \LED[6]~output ( - .i(\LED[6]~reg0_q ), + .i(\rom|altsyncram_component|auto_generated|q_a [6]), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -235,7 +232,7 @@ defparam \LED[6]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y10_N23 cycloneive_io_obuf \LED[7]~output ( - .i(gnd), + .i(\rom|altsyncram_component|auto_generated|q_a [7]), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -269,767 +266,10 @@ defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N4 -cycloneive_lcell_comb \counter[0]~81 ( -// Equation(s): -// \counter[0]~81_combout = !counter[0] - - .dataa(gnd), - .datab(gnd), - .datac(counter[0]), - .datad(gnd), - .cin(gnd), - .combout(\counter[0]~81_combout ), - .cout()); -// synopsys translate_off -defparam \counter[0]~81 .lut_mask = 16'h0F0F; -defparam \counter[0]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y33_N5 -dffeas \counter[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[0]~81_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[0]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[0] .is_wysiwyg = "true"; -defparam \counter[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N6 -cycloneive_lcell_comb \counter[1]~27 ( -// Equation(s): -// \counter[1]~27_combout = (counter[1] & (counter[0] $ (VCC))) # (!counter[1] & (counter[0] & VCC)) -// \counter[1]~28 = CARRY((counter[1] & counter[0])) - - .dataa(counter[1]), - .datab(counter[0]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\counter[1]~27_combout ), - .cout(\counter[1]~28 )); -// synopsys translate_off -defparam \counter[1]~27 .lut_mask = 16'h6688; -defparam \counter[1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y33_N7 -dffeas \counter[1] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[1]~27_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[1]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[1] .is_wysiwyg = "true"; -defparam \counter[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N8 -cycloneive_lcell_comb \counter[2]~29 ( -// Equation(s): -// \counter[2]~29_combout = (counter[2] & (!\counter[1]~28 )) # (!counter[2] & ((\counter[1]~28 ) # (GND))) -// \counter[2]~30 = CARRY((!\counter[1]~28 ) # (!counter[2])) - - .dataa(gnd), - .datab(counter[2]), - .datac(gnd), - .datad(vcc), - .cin(\counter[1]~28 ), - .combout(\counter[2]~29_combout ), - .cout(\counter[2]~30 )); -// synopsys translate_off -defparam \counter[2]~29 .lut_mask = 16'h3C3F; -defparam \counter[2]~29 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N9 -dffeas \counter[2] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[2]~29_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[2]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[2] .is_wysiwyg = "true"; -defparam \counter[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N10 -cycloneive_lcell_comb \counter[3]~31 ( -// Equation(s): -// \counter[3]~31_combout = (counter[3] & (\counter[2]~30 $ (GND))) # (!counter[3] & (!\counter[2]~30 & VCC)) -// \counter[3]~32 = CARRY((counter[3] & !\counter[2]~30 )) - - .dataa(counter[3]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\counter[2]~30 ), - .combout(\counter[3]~31_combout ), - .cout(\counter[3]~32 )); -// synopsys translate_off -defparam \counter[3]~31 .lut_mask = 16'hA50A; -defparam \counter[3]~31 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N11 -dffeas \counter[3] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[3]~31_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[3]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[3] .is_wysiwyg = "true"; -defparam \counter[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N12 -cycloneive_lcell_comb \counter[4]~33 ( -// Equation(s): -// \counter[4]~33_combout = (counter[4] & (!\counter[3]~32 )) # (!counter[4] & ((\counter[3]~32 ) # (GND))) -// \counter[4]~34 = CARRY((!\counter[3]~32 ) # (!counter[4])) - - .dataa(counter[4]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\counter[3]~32 ), - .combout(\counter[4]~33_combout ), - .cout(\counter[4]~34 )); -// synopsys translate_off -defparam \counter[4]~33 .lut_mask = 16'h5A5F; -defparam \counter[4]~33 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N13 -dffeas \counter[4] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[4]~33_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[4]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[4] .is_wysiwyg = "true"; -defparam \counter[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N14 -cycloneive_lcell_comb \counter[5]~35 ( -// Equation(s): -// \counter[5]~35_combout = (counter[5] & (\counter[4]~34 $ (GND))) # (!counter[5] & (!\counter[4]~34 & VCC)) -// \counter[5]~36 = CARRY((counter[5] & !\counter[4]~34 )) - - .dataa(gnd), - .datab(counter[5]), - .datac(gnd), - .datad(vcc), - .cin(\counter[4]~34 ), - .combout(\counter[5]~35_combout ), - .cout(\counter[5]~36 )); -// synopsys translate_off -defparam \counter[5]~35 .lut_mask = 16'hC30C; -defparam \counter[5]~35 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N15 -dffeas \counter[5] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[5]~35_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[5]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[5] .is_wysiwyg = "true"; -defparam \counter[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N16 -cycloneive_lcell_comb \counter[6]~37 ( -// Equation(s): -// \counter[6]~37_combout = (counter[6] & (!\counter[5]~36 )) # (!counter[6] & ((\counter[5]~36 ) # (GND))) -// \counter[6]~38 = CARRY((!\counter[5]~36 ) # (!counter[6])) - - .dataa(gnd), - .datab(counter[6]), - .datac(gnd), - .datad(vcc), - .cin(\counter[5]~36 ), - .combout(\counter[6]~37_combout ), - .cout(\counter[6]~38 )); -// synopsys translate_off -defparam \counter[6]~37 .lut_mask = 16'h3C3F; -defparam \counter[6]~37 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N17 -dffeas \counter[6] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[6]~37_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[6]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[6] .is_wysiwyg = "true"; -defparam \counter[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N18 -cycloneive_lcell_comb \counter[7]~39 ( -// Equation(s): -// \counter[7]~39_combout = (counter[7] & (\counter[6]~38 $ (GND))) # (!counter[7] & (!\counter[6]~38 & VCC)) -// \counter[7]~40 = CARRY((counter[7] & !\counter[6]~38 )) - - .dataa(gnd), - .datab(counter[7]), - .datac(gnd), - .datad(vcc), - .cin(\counter[6]~38 ), - .combout(\counter[7]~39_combout ), - .cout(\counter[7]~40 )); -// synopsys translate_off -defparam \counter[7]~39 .lut_mask = 16'hC30C; -defparam \counter[7]~39 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N19 -dffeas \counter[7] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[7]~39_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[7]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[7] .is_wysiwyg = "true"; -defparam \counter[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N20 -cycloneive_lcell_comb \counter[8]~41 ( -// Equation(s): -// \counter[8]~41_combout = (counter[8] & (!\counter[7]~40 )) # (!counter[8] & ((\counter[7]~40 ) # (GND))) -// \counter[8]~42 = CARRY((!\counter[7]~40 ) # (!counter[8])) - - .dataa(gnd), - .datab(counter[8]), - .datac(gnd), - .datad(vcc), - .cin(\counter[7]~40 ), - .combout(\counter[8]~41_combout ), - .cout(\counter[8]~42 )); -// synopsys translate_off -defparam \counter[8]~41 .lut_mask = 16'h3C3F; -defparam \counter[8]~41 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N21 -dffeas \counter[8] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[8]~41_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[8]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[8] .is_wysiwyg = "true"; -defparam \counter[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N22 -cycloneive_lcell_comb \counter[9]~43 ( -// Equation(s): -// \counter[9]~43_combout = (counter[9] & (\counter[8]~42 $ (GND))) # (!counter[9] & (!\counter[8]~42 & VCC)) -// \counter[9]~44 = CARRY((counter[9] & !\counter[8]~42 )) - - .dataa(counter[9]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\counter[8]~42 ), - .combout(\counter[9]~43_combout ), - .cout(\counter[9]~44 )); -// synopsys translate_off -defparam \counter[9]~43 .lut_mask = 16'hA50A; -defparam \counter[9]~43 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N23 -dffeas \counter[9] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[9]~43_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[9]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[9] .is_wysiwyg = "true"; -defparam \counter[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N24 -cycloneive_lcell_comb \counter[10]~45 ( -// Equation(s): -// \counter[10]~45_combout = (counter[10] & (!\counter[9]~44 )) # (!counter[10] & ((\counter[9]~44 ) # (GND))) -// \counter[10]~46 = CARRY((!\counter[9]~44 ) # (!counter[10])) - - .dataa(gnd), - .datab(counter[10]), - .datac(gnd), - .datad(vcc), - .cin(\counter[9]~44 ), - .combout(\counter[10]~45_combout ), - .cout(\counter[10]~46 )); -// synopsys translate_off -defparam \counter[10]~45 .lut_mask = 16'h3C3F; -defparam \counter[10]~45 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N25 -dffeas \counter[10] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[10]~45_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[10]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[10] .is_wysiwyg = "true"; -defparam \counter[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N26 -cycloneive_lcell_comb \counter[11]~47 ( -// Equation(s): -// \counter[11]~47_combout = (counter[11] & (\counter[10]~46 $ (GND))) # (!counter[11] & (!\counter[10]~46 & VCC)) -// \counter[11]~48 = CARRY((counter[11] & !\counter[10]~46 )) - - .dataa(counter[11]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\counter[10]~46 ), - .combout(\counter[11]~47_combout ), - .cout(\counter[11]~48 )); -// synopsys translate_off -defparam \counter[11]~47 .lut_mask = 16'hA50A; -defparam \counter[11]~47 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N27 -dffeas \counter[11] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[11]~47_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[11]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[11] .is_wysiwyg = "true"; -defparam \counter[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N28 -cycloneive_lcell_comb \counter[12]~49 ( -// Equation(s): -// \counter[12]~49_combout = (counter[12] & (!\counter[11]~48 )) # (!counter[12] & ((\counter[11]~48 ) # (GND))) -// \counter[12]~50 = CARRY((!\counter[11]~48 ) # (!counter[12])) - - .dataa(gnd), - .datab(counter[12]), - .datac(gnd), - .datad(vcc), - .cin(\counter[11]~48 ), - .combout(\counter[12]~49_combout ), - .cout(\counter[12]~50 )); -// synopsys translate_off -defparam \counter[12]~49 .lut_mask = 16'h3C3F; -defparam \counter[12]~49 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N29 -dffeas \counter[12] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[12]~49_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[12]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[12] .is_wysiwyg = "true"; -defparam \counter[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N30 -cycloneive_lcell_comb \counter[13]~51 ( -// Equation(s): -// \counter[13]~51_combout = (counter[13] & (\counter[12]~50 $ (GND))) # (!counter[13] & (!\counter[12]~50 & VCC)) -// \counter[13]~52 = CARRY((counter[13] & !\counter[12]~50 )) - - .dataa(counter[13]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\counter[12]~50 ), - .combout(\counter[13]~51_combout ), - .cout(\counter[13]~52 )); -// synopsys translate_off -defparam \counter[13]~51 .lut_mask = 16'hA50A; -defparam \counter[13]~51 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N31 -dffeas \counter[13] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[13]~51_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[13]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[13] .is_wysiwyg = "true"; -defparam \counter[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y32_N0 -cycloneive_lcell_comb \counter[14]~53 ( -// Equation(s): -// \counter[14]~53_combout = (counter[14] & (!\counter[13]~52 )) # (!counter[14] & ((\counter[13]~52 ) # (GND))) -// \counter[14]~54 = CARRY((!\counter[13]~52 ) # (!counter[14])) - - .dataa(gnd), - .datab(counter[14]), - .datac(gnd), - .datad(vcc), - .cin(\counter[13]~52 ), - .combout(\counter[14]~53_combout ), - .cout(\counter[14]~54 )); -// synopsys translate_off -defparam \counter[14]~53 .lut_mask = 16'h3C3F; -defparam \counter[14]~53 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N1 -dffeas \counter[14] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[14]~53_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[14]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[14] .is_wysiwyg = "true"; -defparam \counter[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y32_N2 -cycloneive_lcell_comb \counter[15]~55 ( -// Equation(s): -// \counter[15]~55_combout = (counter[15] & (\counter[14]~54 $ (GND))) # (!counter[15] & (!\counter[14]~54 & VCC)) -// \counter[15]~56 = CARRY((counter[15] & !\counter[14]~54 )) - - .dataa(gnd), - .datab(counter[15]), - .datac(gnd), - .datad(vcc), - .cin(\counter[14]~54 ), - .combout(\counter[15]~55_combout ), - .cout(\counter[15]~56 )); -// synopsys translate_off -defparam \counter[15]~55 .lut_mask = 16'hC30C; -defparam \counter[15]~55 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N3 -dffeas \counter[15] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[15]~55_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[15]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[15] .is_wysiwyg = "true"; -defparam \counter[15] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y32_N4 -cycloneive_lcell_comb \counter[16]~57 ( -// Equation(s): -// \counter[16]~57_combout = (counter[16] & (!\counter[15]~56 )) # (!counter[16] & ((\counter[15]~56 ) # (GND))) -// \counter[16]~58 = CARRY((!\counter[15]~56 ) # (!counter[16])) - - .dataa(gnd), - .datab(counter[16]), - .datac(gnd), - .datad(vcc), - .cin(\counter[15]~56 ), - .combout(\counter[16]~57_combout ), - .cout(\counter[16]~58 )); -// synopsys translate_off -defparam \counter[16]~57 .lut_mask = 16'h3C3F; -defparam \counter[16]~57 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N5 -dffeas \counter[16] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[16]~57_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[16]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[16] .is_wysiwyg = "true"; -defparam \counter[16] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y32_N6 -cycloneive_lcell_comb \counter[17]~59 ( -// Equation(s): -// \counter[17]~59_combout = (counter[17] & (\counter[16]~58 $ (GND))) # (!counter[17] & (!\counter[16]~58 & VCC)) -// \counter[17]~60 = CARRY((counter[17] & !\counter[16]~58 )) - - .dataa(counter[17]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\counter[16]~58 ), - .combout(\counter[17]~59_combout ), - .cout(\counter[17]~60 )); -// synopsys translate_off -defparam \counter[17]~59 .lut_mask = 16'hA50A; -defparam \counter[17]~59 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N7 -dffeas \counter[17] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[17]~59_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[17]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[17] .is_wysiwyg = "true"; -defparam \counter[17] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y32_N8 -cycloneive_lcell_comb \counter[18]~61 ( -// Equation(s): -// \counter[18]~61_combout = (counter[18] & (!\counter[17]~60 )) # (!counter[18] & ((\counter[17]~60 ) # (GND))) -// \counter[18]~62 = CARRY((!\counter[17]~60 ) # (!counter[18])) - - .dataa(gnd), - .datab(counter[18]), - .datac(gnd), - .datad(vcc), - .cin(\counter[17]~60 ), - .combout(\counter[18]~61_combout ), - .cout(\counter[18]~62 )); -// synopsys translate_off -defparam \counter[18]~61 .lut_mask = 16'h3C3F; -defparam \counter[18]~61 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N9 -dffeas \counter[18] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[18]~61_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[18]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[18] .is_wysiwyg = "true"; -defparam \counter[18] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y32_N10 -cycloneive_lcell_comb \counter[19]~63 ( -// Equation(s): -// \counter[19]~63_combout = (counter[19] & (\counter[18]~62 $ (GND))) # (!counter[19] & (!\counter[18]~62 & VCC)) -// \counter[19]~64 = CARRY((counter[19] & !\counter[18]~62 )) - - .dataa(counter[19]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\counter[18]~62 ), - .combout(\counter[19]~63_combout ), - .cout(\counter[19]~64 )); -// synopsys translate_off -defparam \counter[19]~63 .lut_mask = 16'hA50A; -defparam \counter[19]~63 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N11 -dffeas \counter[19] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[19]~63_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[19]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[19] .is_wysiwyg = "true"; -defparam \counter[19] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y32_N12 -cycloneive_lcell_comb \counter[20]~65 ( -// Equation(s): -// \counter[20]~65_combout = (counter[20] & (!\counter[19]~64 )) # (!counter[20] & ((\counter[19]~64 ) # (GND))) -// \counter[20]~66 = CARRY((!\counter[19]~64 ) # (!counter[20])) - - .dataa(counter[20]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\counter[19]~64 ), - .combout(\counter[20]~65_combout ), - .cout(\counter[20]~66 )); -// synopsys translate_off -defparam \counter[20]~65 .lut_mask = 16'h5A5F; -defparam \counter[20]~65 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N13 +// Location: FF_X31_Y17_N21 dffeas \counter[20] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[20]~65_combout ), + .d(\Add0~40_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1045,356 +285,28 @@ defparam \counter[20] .is_wysiwyg = "true"; defparam \counter[20] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y32_N14 -cycloneive_lcell_comb \counter[21]~67 ( +// Location: LCCOMB_X31_Y18_N12 +cycloneive_lcell_comb \Add0~0 ( // Equation(s): -// \counter[21]~67_combout = (counter[21] & (\counter[20]~66 $ (GND))) # (!counter[21] & (!\counter[20]~66 & VCC)) -// \counter[21]~68 = CARRY((counter[21] & !\counter[20]~66 )) +// \Add0~0_combout = counter[0] $ (VCC) +// \Add0~1 = CARRY(counter[0]) - .dataa(gnd), - .datab(counter[21]), - .datac(gnd), - .datad(vcc), - .cin(\counter[20]~66 ), - .combout(\counter[21]~67_combout ), - .cout(\counter[21]~68 )); -// synopsys translate_off -defparam \counter[21]~67 .lut_mask = 16'hC30C; -defparam \counter[21]~67 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N15 -dffeas \counter[21] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[21]~67_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[21]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[21] .is_wysiwyg = "true"; -defparam \counter[21] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y32_N4 -cycloneive_lcell_comb \LED[0]~reg0feeder ( -// Equation(s): -// \LED[0]~reg0feeder_combout = counter[21] - - .dataa(gnd), - .datab(gnd), - .datac(counter[21]), - .datad(gnd), - .cin(gnd), - .combout(\LED[0]~reg0feeder_combout ), - .cout()); -// synopsys translate_off -defparam \LED[0]~reg0feeder .lut_mask = 16'hF0F0; -defparam \LED[0]~reg0feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y32_N5 -dffeas \LED[0]~reg0 ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\LED[0]~reg0feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\LED[0]~reg0_q ), - .prn(vcc)); -// synopsys translate_off -defparam \LED[0]~reg0 .is_wysiwyg = "true"; -defparam \LED[0]~reg0 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y32_N16 -cycloneive_lcell_comb \counter[22]~69 ( -// Equation(s): -// \counter[22]~69_combout = (counter[22] & (!\counter[21]~68 )) # (!counter[22] & ((\counter[21]~68 ) # (GND))) -// \counter[22]~70 = CARRY((!\counter[21]~68 ) # (!counter[22])) - - .dataa(gnd), - .datab(counter[22]), - .datac(gnd), - .datad(vcc), - .cin(\counter[21]~68 ), - .combout(\counter[22]~69_combout ), - .cout(\counter[22]~70 )); -// synopsys translate_off -defparam \counter[22]~69 .lut_mask = 16'h3C3F; -defparam \counter[22]~69 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N17 -dffeas \counter[22] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[22]~69_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[22]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[22] .is_wysiwyg = "true"; -defparam \counter[22] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y32_N12 -cycloneive_lcell_comb \LED[1]~reg0feeder ( -// Equation(s): -// \LED[1]~reg0feeder_combout = counter[22] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(counter[22]), - .cin(gnd), - .combout(\LED[1]~reg0feeder_combout ), - .cout()); -// synopsys translate_off -defparam \LED[1]~reg0feeder .lut_mask = 16'hFF00; -defparam \LED[1]~reg0feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X46_Y32_N13 -dffeas \LED[1]~reg0 ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\LED[1]~reg0feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\LED[1]~reg0_q ), - .prn(vcc)); -// synopsys translate_off -defparam \LED[1]~reg0 .is_wysiwyg = "true"; -defparam \LED[1]~reg0 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y32_N18 -cycloneive_lcell_comb \counter[23]~71 ( -// Equation(s): -// \counter[23]~71_combout = (counter[23] & (\counter[22]~70 $ (GND))) # (!counter[23] & (!\counter[22]~70 & VCC)) -// \counter[23]~72 = CARRY((counter[23] & !\counter[22]~70 )) - - .dataa(gnd), - .datab(counter[23]), - .datac(gnd), - .datad(vcc), - .cin(\counter[22]~70 ), - .combout(\counter[23]~71_combout ), - .cout(\counter[23]~72 )); -// synopsys translate_off -defparam \counter[23]~71 .lut_mask = 16'hC30C; -defparam \counter[23]~71 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N19 -dffeas \counter[23] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[23]~71_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[23]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[23] .is_wysiwyg = "true"; -defparam \counter[23] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y32_N6 -cycloneive_lcell_comb \LED[2]~reg0feeder ( -// Equation(s): -// \LED[2]~reg0feeder_combout = counter[23] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(counter[23]), - .cin(gnd), - .combout(\LED[2]~reg0feeder_combout ), - .cout()); -// synopsys translate_off -defparam \LED[2]~reg0feeder .lut_mask = 16'hFF00; -defparam \LED[2]~reg0feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X46_Y32_N7 -dffeas \LED[2]~reg0 ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\LED[2]~reg0feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\LED[2]~reg0_q ), - .prn(vcc)); -// synopsys translate_off -defparam \LED[2]~reg0 .is_wysiwyg = "true"; -defparam \LED[2]~reg0 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y32_N20 -cycloneive_lcell_comb \counter[24]~73 ( -// Equation(s): -// \counter[24]~73_combout = (counter[24] & (!\counter[23]~72 )) # (!counter[24] & ((\counter[23]~72 ) # (GND))) -// \counter[24]~74 = CARRY((!\counter[23]~72 ) # (!counter[24])) - - .dataa(gnd), - .datab(counter[24]), - .datac(gnd), - .datad(vcc), - .cin(\counter[23]~72 ), - .combout(\counter[24]~73_combout ), - .cout(\counter[24]~74 )); -// synopsys translate_off -defparam \counter[24]~73 .lut_mask = 16'h3C3F; -defparam \counter[24]~73 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N21 -dffeas \counter[24] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[24]~73_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[24]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[24] .is_wysiwyg = "true"; -defparam \counter[24] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y32_N4 -cycloneive_lcell_comb \LED[3]~reg0feeder ( -// Equation(s): -// \LED[3]~reg0feeder_combout = counter[24] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(counter[24]), - .cin(gnd), - .combout(\LED[3]~reg0feeder_combout ), - .cout()); -// synopsys translate_off -defparam \LED[3]~reg0feeder .lut_mask = 16'hFF00; -defparam \LED[3]~reg0feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y32_N5 -dffeas \LED[3]~reg0 ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\LED[3]~reg0feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\LED[3]~reg0_q ), - .prn(vcc)); -// synopsys translate_off -defparam \LED[3]~reg0 .is_wysiwyg = "true"; -defparam \LED[3]~reg0 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y32_N22 -cycloneive_lcell_comb \counter[25]~75 ( -// Equation(s): -// \counter[25]~75_combout = (counter[25] & (\counter[24]~74 $ (GND))) # (!counter[25] & (!\counter[24]~74 & VCC)) -// \counter[25]~76 = CARRY((counter[25] & !\counter[24]~74 )) - - .dataa(counter[25]), + .dataa(counter[0]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\counter[24]~74 ), - .combout(\counter[25]~75_combout ), - .cout(\counter[25]~76 )); -// synopsys translate_off -defparam \counter[25]~75 .lut_mask = 16'hA50A; -defparam \counter[25]~75 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N23 -dffeas \counter[25] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[25]~75_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[25]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[25] .is_wysiwyg = "true"; -defparam \counter[25] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y32_N18 -cycloneive_lcell_comb \LED[4]~reg0feeder ( -// Equation(s): -// \LED[4]~reg0feeder_combout = counter[25] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(counter[25]), .cin(gnd), - .combout(\LED[4]~reg0feeder_combout ), - .cout()); + .combout(\Add0~0_combout ), + .cout(\Add0~1 )); // synopsys translate_off -defparam \LED[4]~reg0feeder .lut_mask = 16'hFF00; -defparam \LED[4]~reg0feeder .sum_lutc_input = "datac"; +defparam \Add0~0 .lut_mask = 16'h55AA; +defparam \Add0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y32_N19 -dffeas \LED[4]~reg0 ( +// Location: FF_X31_Y18_N13 +dffeas \counter[0] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\LED[4]~reg0feeder_combout ), + .d(\Add0~0_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1403,35 +315,35 @@ dffeas \LED[4]~reg0 ( .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\LED[4]~reg0_q ), + .q(counter[0]), .prn(vcc)); // synopsys translate_off -defparam \LED[4]~reg0 .is_wysiwyg = "true"; -defparam \LED[4]~reg0 .power_up = "low"; +defparam \counter[0] .is_wysiwyg = "true"; +defparam \counter[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y32_N24 -cycloneive_lcell_comb \counter[26]~77 ( +// Location: LCCOMB_X31_Y18_N14 +cycloneive_lcell_comb \Add0~2 ( // Equation(s): -// \counter[26]~77_combout = (counter[26] & (!\counter[25]~76 )) # (!counter[26] & ((\counter[25]~76 ) # (GND))) -// \counter[26]~78 = CARRY((!\counter[25]~76 ) # (!counter[26])) +// \Add0~2_combout = (counter[1] & (!\Add0~1 )) # (!counter[1] & ((\Add0~1 ) # (GND))) +// \Add0~3 = CARRY((!\Add0~1 ) # (!counter[1])) .dataa(gnd), - .datab(counter[26]), + .datab(counter[1]), .datac(gnd), .datad(vcc), - .cin(\counter[25]~76 ), - .combout(\counter[26]~77_combout ), - .cout(\counter[26]~78 )); + .cin(\Add0~1 ), + .combout(\Add0~2_combout ), + .cout(\Add0~3 )); // synopsys translate_off -defparam \counter[26]~77 .lut_mask = 16'h3C3F; -defparam \counter[26]~77 .sum_lutc_input = "cin"; +defparam \Add0~2 .lut_mask = 16'h3C3F; +defparam \Add0~2 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X39_Y32_N25 -dffeas \counter[26] ( +// Location: FF_X31_Y18_N15 +dffeas \counter[1] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[26]~77_combout ), + .d(\Add0~2_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1440,34 +352,819 @@ dffeas \counter[26] ( .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(counter[26]), + .q(counter[1]), .prn(vcc)); // synopsys translate_off -defparam \counter[26] .is_wysiwyg = "true"; -defparam \counter[26] .power_up = "low"; +defparam \counter[1] .is_wysiwyg = "true"; +defparam \counter[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y32_N24 -cycloneive_lcell_comb \LED[5]~reg0feeder ( +// Location: LCCOMB_X31_Y18_N16 +cycloneive_lcell_comb \Add0~4 ( // Equation(s): -// \LED[5]~reg0feeder_combout = counter[26] +// \Add0~4_combout = (counter[2] & (\Add0~3 $ (GND))) # (!counter[2] & (!\Add0~3 & VCC)) +// \Add0~5 = CARRY((counter[2] & !\Add0~3 )) + + .dataa(gnd), + .datab(counter[2]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~3 ), + .combout(\Add0~4_combout ), + .cout(\Add0~5 )); +// synopsys translate_off +defparam \Add0~4 .lut_mask = 16'hC30C; +defparam \Add0~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y18_N17 +dffeas \counter[2] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[2]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[2] .is_wysiwyg = "true"; +defparam \counter[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N18 +cycloneive_lcell_comb \Add0~6 ( +// Equation(s): +// \Add0~6_combout = (counter[3] & (!\Add0~5 )) # (!counter[3] & ((\Add0~5 ) # (GND))) +// \Add0~7 = CARRY((!\Add0~5 ) # (!counter[3])) + + .dataa(gnd), + .datab(counter[3]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~5 ), + .combout(\Add0~6_combout ), + .cout(\Add0~7 )); +// synopsys translate_off +defparam \Add0~6 .lut_mask = 16'h3C3F; +defparam \Add0~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y18_N19 +dffeas \counter[3] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[3]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[3] .is_wysiwyg = "true"; +defparam \counter[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N20 +cycloneive_lcell_comb \Add0~8 ( +// Equation(s): +// \Add0~8_combout = (counter[4] & (\Add0~7 $ (GND))) # (!counter[4] & (!\Add0~7 & VCC)) +// \Add0~9 = CARRY((counter[4] & !\Add0~7 )) + + .dataa(counter[4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add0~7 ), + .combout(\Add0~8_combout ), + .cout(\Add0~9 )); +// synopsys translate_off +defparam \Add0~8 .lut_mask = 16'hA50A; +defparam \Add0~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y18_N21 +dffeas \counter[4] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[4]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[4] .is_wysiwyg = "true"; +defparam \counter[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N22 +cycloneive_lcell_comb \Add0~10 ( +// Equation(s): +// \Add0~10_combout = (counter[5] & (!\Add0~9 )) # (!counter[5] & ((\Add0~9 ) # (GND))) +// \Add0~11 = CARRY((!\Add0~9 ) # (!counter[5])) + + .dataa(gnd), + .datab(counter[5]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~9 ), + .combout(\Add0~10_combout ), + .cout(\Add0~11 )); +// synopsys translate_off +defparam \Add0~10 .lut_mask = 16'h3C3F; +defparam \Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y18_N23 +dffeas \counter[5] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~10_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[5]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[5] .is_wysiwyg = "true"; +defparam \counter[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N24 +cycloneive_lcell_comb \Add0~12 ( +// Equation(s): +// \Add0~12_combout = (counter[6] & (\Add0~11 $ (GND))) # (!counter[6] & (!\Add0~11 & VCC)) +// \Add0~13 = CARRY((counter[6] & !\Add0~11 )) + + .dataa(counter[6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add0~11 ), + .combout(\Add0~12_combout ), + .cout(\Add0~13 )); +// synopsys translate_off +defparam \Add0~12 .lut_mask = 16'hA50A; +defparam \Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y18_N25 +dffeas \counter[6] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[6]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[6] .is_wysiwyg = "true"; +defparam \counter[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N26 +cycloneive_lcell_comb \Add0~14 ( +// Equation(s): +// \Add0~14_combout = (counter[7] & (!\Add0~13 )) # (!counter[7] & ((\Add0~13 ) # (GND))) +// \Add0~15 = CARRY((!\Add0~13 ) # (!counter[7])) + + .dataa(gnd), + .datab(counter[7]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~13 ), + .combout(\Add0~14_combout ), + .cout(\Add0~15 )); +// synopsys translate_off +defparam \Add0~14 .lut_mask = 16'h3C3F; +defparam \Add0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y18_N27 +dffeas \counter[7] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~14_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[7]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[7] .is_wysiwyg = "true"; +defparam \counter[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N28 +cycloneive_lcell_comb \Add0~16 ( +// Equation(s): +// \Add0~16_combout = (counter[8] & (\Add0~15 $ (GND))) # (!counter[8] & (!\Add0~15 & VCC)) +// \Add0~17 = CARRY((counter[8] & !\Add0~15 )) + + .dataa(gnd), + .datab(counter[8]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~15 ), + .combout(\Add0~16_combout ), + .cout(\Add0~17 )); +// synopsys translate_off +defparam \Add0~16 .lut_mask = 16'hC30C; +defparam \Add0~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y18_N29 +dffeas \counter[8] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~16_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[8]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[8] .is_wysiwyg = "true"; +defparam \counter[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N30 +cycloneive_lcell_comb \Add0~18 ( +// Equation(s): +// \Add0~18_combout = (counter[9] & (!\Add0~17 )) # (!counter[9] & ((\Add0~17 ) # (GND))) +// \Add0~19 = CARRY((!\Add0~17 ) # (!counter[9])) + + .dataa(counter[9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add0~17 ), + .combout(\Add0~18_combout ), + .cout(\Add0~19 )); +// synopsys translate_off +defparam \Add0~18 .lut_mask = 16'h5A5F; +defparam \Add0~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y18_N31 +dffeas \counter[9] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~18_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[9]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[9] .is_wysiwyg = "true"; +defparam \counter[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N0 +cycloneive_lcell_comb \Add0~20 ( +// Equation(s): +// \Add0~20_combout = (counter[10] & (\Add0~19 $ (GND))) # (!counter[10] & (!\Add0~19 & VCC)) +// \Add0~21 = CARRY((counter[10] & !\Add0~19 )) + + .dataa(gnd), + .datab(counter[10]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~19 ), + .combout(\Add0~20_combout ), + .cout(\Add0~21 )); +// synopsys translate_off +defparam \Add0~20 .lut_mask = 16'hC30C; +defparam \Add0~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y17_N1 +dffeas \counter[10] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~20_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[10]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[10] .is_wysiwyg = "true"; +defparam \counter[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N2 +cycloneive_lcell_comb \Add0~22 ( +// Equation(s): +// \Add0~22_combout = (counter[11] & (!\Add0~21 )) # (!counter[11] & ((\Add0~21 ) # (GND))) +// \Add0~23 = CARRY((!\Add0~21 ) # (!counter[11])) + + .dataa(gnd), + .datab(counter[11]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~21 ), + .combout(\Add0~22_combout ), + .cout(\Add0~23 )); +// synopsys translate_off +defparam \Add0~22 .lut_mask = 16'h3C3F; +defparam \Add0~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y17_N3 +dffeas \counter[11] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~22_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[11]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[11] .is_wysiwyg = "true"; +defparam \counter[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N4 +cycloneive_lcell_comb \Add0~24 ( +// Equation(s): +// \Add0~24_combout = (counter[12] & (\Add0~23 $ (GND))) # (!counter[12] & (!\Add0~23 & VCC)) +// \Add0~25 = CARRY((counter[12] & !\Add0~23 )) + + .dataa(gnd), + .datab(counter[12]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~23 ), + .combout(\Add0~24_combout ), + .cout(\Add0~25 )); +// synopsys translate_off +defparam \Add0~24 .lut_mask = 16'hC30C; +defparam \Add0~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y17_N5 +dffeas \counter[12] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~24_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[12]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[12] .is_wysiwyg = "true"; +defparam \counter[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N6 +cycloneive_lcell_comb \Add0~26 ( +// Equation(s): +// \Add0~26_combout = (counter[13] & (!\Add0~25 )) # (!counter[13] & ((\Add0~25 ) # (GND))) +// \Add0~27 = CARRY((!\Add0~25 ) # (!counter[13])) + + .dataa(gnd), + .datab(counter[13]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~25 ), + .combout(\Add0~26_combout ), + .cout(\Add0~27 )); +// synopsys translate_off +defparam \Add0~26 .lut_mask = 16'h3C3F; +defparam \Add0~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y17_N7 +dffeas \counter[13] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~26_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[13]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[13] .is_wysiwyg = "true"; +defparam \counter[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N8 +cycloneive_lcell_comb \Add0~28 ( +// Equation(s): +// \Add0~28_combout = (counter[14] & (\Add0~27 $ (GND))) # (!counter[14] & (!\Add0~27 & VCC)) +// \Add0~29 = CARRY((counter[14] & !\Add0~27 )) + + .dataa(counter[14]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add0~27 ), + .combout(\Add0~28_combout ), + .cout(\Add0~29 )); +// synopsys translate_off +defparam \Add0~28 .lut_mask = 16'hA50A; +defparam \Add0~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y17_N9 +dffeas \counter[14] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~28_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[14]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[14] .is_wysiwyg = "true"; +defparam \counter[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N10 +cycloneive_lcell_comb \Add0~30 ( +// Equation(s): +// \Add0~30_combout = (counter[15] & (!\Add0~29 )) # (!counter[15] & ((\Add0~29 ) # (GND))) +// \Add0~31 = CARRY((!\Add0~29 ) # (!counter[15])) + + .dataa(gnd), + .datab(counter[15]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~29 ), + .combout(\Add0~30_combout ), + .cout(\Add0~31 )); +// synopsys translate_off +defparam \Add0~30 .lut_mask = 16'h3C3F; +defparam \Add0~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y17_N11 +dffeas \counter[15] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~30_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[15]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[15] .is_wysiwyg = "true"; +defparam \counter[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N12 +cycloneive_lcell_comb \Add0~32 ( +// Equation(s): +// \Add0~32_combout = (counter[16] & (\Add0~31 $ (GND))) # (!counter[16] & (!\Add0~31 & VCC)) +// \Add0~33 = CARRY((counter[16] & !\Add0~31 )) + + .dataa(gnd), + .datab(counter[16]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~31 ), + .combout(\Add0~32_combout ), + .cout(\Add0~33 )); +// synopsys translate_off +defparam \Add0~32 .lut_mask = 16'hC30C; +defparam \Add0~32 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y17_N13 +dffeas \counter[16] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~32_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[16]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[16] .is_wysiwyg = "true"; +defparam \counter[16] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N14 +cycloneive_lcell_comb \Add0~34 ( +// Equation(s): +// \Add0~34_combout = (counter[17] & (!\Add0~33 )) # (!counter[17] & ((\Add0~33 ) # (GND))) +// \Add0~35 = CARRY((!\Add0~33 ) # (!counter[17])) + + .dataa(counter[17]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add0~33 ), + .combout(\Add0~34_combout ), + .cout(\Add0~35 )); +// synopsys translate_off +defparam \Add0~34 .lut_mask = 16'h5A5F; +defparam \Add0~34 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y17_N15 +dffeas \counter[17] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~34_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[17]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[17] .is_wysiwyg = "true"; +defparam \counter[17] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N16 +cycloneive_lcell_comb \Add0~36 ( +// Equation(s): +// \Add0~36_combout = (counter[18] & (\Add0~35 $ (GND))) # (!counter[18] & (!\Add0~35 & VCC)) +// \Add0~37 = CARRY((counter[18] & !\Add0~35 )) + + .dataa(counter[18]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add0~35 ), + .combout(\Add0~36_combout ), + .cout(\Add0~37 )); +// synopsys translate_off +defparam \Add0~36 .lut_mask = 16'hA50A; +defparam \Add0~36 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y17_N17 +dffeas \counter[18] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~36_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[18]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[18] .is_wysiwyg = "true"; +defparam \counter[18] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N18 +cycloneive_lcell_comb \Add0~38 ( +// Equation(s): +// \Add0~38_combout = (counter[19] & (!\Add0~37 )) # (!counter[19] & ((\Add0~37 ) # (GND))) +// \Add0~39 = CARRY((!\Add0~37 ) # (!counter[19])) + + .dataa(counter[19]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add0~37 ), + .combout(\Add0~38_combout ), + .cout(\Add0~39 )); +// synopsys translate_off +defparam \Add0~38 .lut_mask = 16'h5A5F; +defparam \Add0~38 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y17_N19 +dffeas \counter[19] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~38_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[19]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[19] .is_wysiwyg = "true"; +defparam \counter[19] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N20 +cycloneive_lcell_comb \Add0~40 ( +// Equation(s): +// \Add0~40_combout = \Add0~39 $ (!counter[20]) .dataa(gnd), .datab(gnd), .datac(gnd), - .datad(counter[26]), + .datad(counter[20]), + .cin(\Add0~39 ), + .combout(\Add0~40_combout ), + .cout()); +// synopsys translate_off +defparam \Add0~40 .lut_mask = 16'hF00F; +defparam \Add0~40 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N28 +cycloneive_lcell_comb \Equal0~5 ( +// Equation(s): +// \Equal0~5_combout = (!\Add0~32_combout & (!\Add0~36_combout & (!\Add0~34_combout & !\Add0~38_combout ))) + + .dataa(\Add0~32_combout ), + .datab(\Add0~36_combout ), + .datac(\Add0~34_combout ), + .datad(\Add0~38_combout ), .cin(gnd), - .combout(\LED[5]~reg0feeder_combout ), + .combout(\Equal0~5_combout ), .cout()); // synopsys translate_off -defparam \LED[5]~reg0feeder .lut_mask = 16'hFF00; -defparam \LED[5]~reg0feeder .sum_lutc_input = "datac"; +defparam \Equal0~5 .lut_mask = 16'h0001; +defparam \Equal0~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y32_N25 -dffeas \LED[5]~reg0 ( +// Location: LCCOMB_X31_Y18_N6 +cycloneive_lcell_comb \Equal0~1 ( +// Equation(s): +// \Equal0~1_combout = (!\Add0~10_combout & (!\Add0~8_combout & (!\Add0~14_combout & !\Add0~12_combout ))) + + .dataa(\Add0~10_combout ), + .datab(\Add0~8_combout ), + .datac(\Add0~14_combout ), + .datad(\Add0~12_combout ), + .cin(gnd), + .combout(\Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~1 .lut_mask = 16'h0001; +defparam \Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N4 +cycloneive_lcell_comb \Equal0~0 ( +// Equation(s): +// \Equal0~0_combout = (!\Add0~4_combout & (!\Add0~0_combout & (!\Add0~6_combout & !\Add0~2_combout ))) + + .dataa(\Add0~4_combout ), + .datab(\Add0~0_combout ), + .datac(\Add0~6_combout ), + .datad(\Add0~2_combout ), + .cin(gnd), + .combout(\Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~0 .lut_mask = 16'h0001; +defparam \Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N30 +cycloneive_lcell_comb \Equal0~2 ( +// Equation(s): +// \Equal0~2_combout = (!\Add0~22_combout & (!\Add0~16_combout & (!\Add0~20_combout & !\Add0~18_combout ))) + + .dataa(\Add0~22_combout ), + .datab(\Add0~16_combout ), + .datac(\Add0~20_combout ), + .datad(\Add0~18_combout ), + .cin(gnd), + .combout(\Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~2 .lut_mask = 16'h0001; +defparam \Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N30 +cycloneive_lcell_comb \Equal0~3 ( +// Equation(s): +// \Equal0~3_combout = (!\Add0~26_combout & (!\Add0~24_combout & (!\Add0~28_combout & !\Add0~30_combout ))) + + .dataa(\Add0~26_combout ), + .datab(\Add0~24_combout ), + .datac(\Add0~28_combout ), + .datad(\Add0~30_combout ), + .cin(gnd), + .combout(\Equal0~3_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~3 .lut_mask = 16'h0001; +defparam \Equal0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N28 +cycloneive_lcell_comb \Equal0~4 ( +// Equation(s): +// \Equal0~4_combout = (\Equal0~1_combout & (\Equal0~0_combout & (\Equal0~2_combout & \Equal0~3_combout ))) + + .dataa(\Equal0~1_combout ), + .datab(\Equal0~0_combout ), + .datac(\Equal0~2_combout ), + .datad(\Equal0~3_combout ), + .cin(gnd), + .combout(\Equal0~4_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~4 .lut_mask = 16'h8000; +defparam \Equal0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N20 +cycloneive_lcell_comb \address[0]~0 ( +// Equation(s): +// \address[0]~0_combout = address[0] $ (((!\Add0~40_combout & (\Equal0~5_combout & \Equal0~4_combout )))) + + .dataa(\Add0~40_combout ), + .datab(\Equal0~5_combout ), + .datac(address[0]), + .datad(\Equal0~4_combout ), + .cin(gnd), + .combout(\address[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \address[0]~0 .lut_mask = 16'hB4F0; +defparam \address[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N21 +dffeas \address[0] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\LED[5]~reg0feeder_combout ), + .d(\address[0]~0_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1476,70 +1173,68 @@ dffeas \LED[5]~reg0 ( .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\LED[5]~reg0_q ), + .q(address[0]), .prn(vcc)); // synopsys translate_off -defparam \LED[5]~reg0 .is_wysiwyg = "true"; -defparam \LED[5]~reg0 .power_up = "low"; +defparam \address[0] .is_wysiwyg = "true"; +defparam \address[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y32_N26 -cycloneive_lcell_comb \counter[27]~79 ( +// Location: LCCOMB_X31_Y17_N26 +cycloneive_lcell_comb \Equal0~6 ( // Equation(s): -// \counter[27]~79_combout = counter[27] $ (!\counter[26]~78 ) - - .dataa(counter[27]), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(\counter[26]~78 ), - .combout(\counter[27]~79_combout ), - .cout()); -// synopsys translate_off -defparam \counter[27]~79 .lut_mask = 16'hA5A5; -defparam \counter[27]~79 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N27 -dffeas \counter[27] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[27]~79_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[27]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[27] .is_wysiwyg = "true"; -defparam \counter[27] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y32_N14 -cycloneive_lcell_comb \LED[6]~reg0feeder ( -// Equation(s): -// \LED[6]~reg0feeder_combout = counter[27] +// \Equal0~6_combout = (!\Add0~34_combout & !\Add0~32_combout ) .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(counter[27]), + .datac(\Add0~34_combout ), + .datad(\Add0~32_combout ), .cin(gnd), - .combout(\LED[6]~reg0feeder_combout ), + .combout(\Equal0~6_combout ), .cout()); // synopsys translate_off -defparam \LED[6]~reg0feeder .lut_mask = 16'hFF00; -defparam \LED[6]~reg0feeder .sum_lutc_input = "datac"; +defparam \Equal0~6 .lut_mask = 16'h000F; +defparam \Equal0~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y32_N15 -dffeas \LED[6]~reg0 ( +// Location: LCCOMB_X31_Y17_N24 +cycloneive_lcell_comb \Equal0~7 ( +// Equation(s): +// \Equal0~7_combout = (!\Add0~40_combout & (!\Add0~36_combout & (\Equal0~6_combout & !\Add0~38_combout ))) + + .dataa(\Add0~40_combout ), + .datab(\Add0~36_combout ), + .datac(\Equal0~6_combout ), + .datad(\Add0~38_combout ), + .cin(gnd), + .combout(\Equal0~7_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~7 .lut_mask = 16'h0010; +defparam \Equal0~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N10 +cycloneive_lcell_comb \address[1]~1 ( +// Equation(s): +// \address[1]~1_combout = address[1] $ (((address[0] & (\Equal0~4_combout & \Equal0~7_combout )))) + + .dataa(address[0]), + .datab(\Equal0~4_combout ), + .datac(address[1]), + .datad(\Equal0~7_combout ), + .cin(gnd), + .combout(\address[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \address[1]~1 .lut_mask = 16'h78F0; +defparam \address[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N11 +dffeas \address[1] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\LED[6]~reg0feeder_combout ), + .d(\address[1]~1_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1548,11 +1243,116 @@ dffeas \LED[6]~reg0 ( .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\LED[6]~reg0_q ), + .q(address[1]), .prn(vcc)); // synopsys translate_off -defparam \LED[6]~reg0 .is_wysiwyg = "true"; -defparam \LED[6]~reg0 .power_up = "low"; +defparam \address[1] .is_wysiwyg = "true"; +defparam \address[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N2 +cycloneive_lcell_comb \address[1]~2 ( +// Equation(s): +// \address[1]~2_combout = (address[0] & (\Equal0~5_combout & (!\Add0~40_combout & \Equal0~4_combout ))) + + .dataa(address[0]), + .datab(\Equal0~5_combout ), + .datac(\Add0~40_combout ), + .datad(\Equal0~4_combout ), + .cin(gnd), + .combout(\address[1]~2_combout ), + .cout()); +// synopsys translate_off +defparam \address[1]~2 .lut_mask = 16'h0800; +defparam \address[1]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N16 +cycloneive_lcell_comb \address[2]~3 ( +// Equation(s): +// \address[2]~3_combout = address[2] $ (((address[1] & \address[1]~2_combout ))) + + .dataa(gnd), + .datab(address[1]), + .datac(address[2]), + .datad(\address[1]~2_combout ), + .cin(gnd), + .combout(\address[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \address[2]~3 .lut_mask = 16'h3CF0; +defparam \address[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N17 +dffeas \address[2] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[2]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(address[2]), + .prn(vcc)); +// synopsys translate_off +defparam \address[2] .is_wysiwyg = "true"; +defparam \address[2] .power_up = "low"; +// synopsys translate_on + +// Location: M9K_X33_Y26_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(vcc), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(18'b000000000000000000), + .portaaddr({address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(18'b000000000000000000), + .portbaddr(3'b000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 18; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 18; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 144'h002040042000900018000600024001080081; // synopsys translate_on assign LED[0] = \LED[0]~output_o ; diff --git a/simulation/modelsim/spectrum_6_1200mv_0c_slow.vo b/simulation/modelsim/spectrum_6_1200mv_0c_slow.vo index e2f2b0b..dbe4927 100644 --- a/simulation/modelsim/spectrum_6_1200mv_0c_slow.vo +++ b/simulation/modelsim/spectrum_6_1200mv_0c_slow.vo @@ -16,7 +16,7 @@ // PROGRAM "Quartus II 32-bit" // VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" -// DATE "03/30/2022 11:51:43" +// DATE "03/30/2022 12:38:42" // // Device: Altera EP4CE22F17C6 Package FBGA256 @@ -71,80 +71,77 @@ wire \LED[6]~output_o ; wire \LED[7]~output_o ; wire \CLOCK_50~input_o ; wire \CLOCK_50~inputclkctrl_outclk ; -wire \counter[0]~81_combout ; -wire \counter[1]~27_combout ; -wire \counter[1]~28 ; -wire \counter[2]~29_combout ; -wire \counter[2]~30 ; -wire \counter[3]~31_combout ; -wire \counter[3]~32 ; -wire \counter[4]~33_combout ; -wire \counter[4]~34 ; -wire \counter[5]~35_combout ; -wire \counter[5]~36 ; -wire \counter[6]~37_combout ; -wire \counter[6]~38 ; -wire \counter[7]~39_combout ; -wire \counter[7]~40 ; -wire \counter[8]~41_combout ; -wire \counter[8]~42 ; -wire \counter[9]~43_combout ; -wire \counter[9]~44 ; -wire \counter[10]~45_combout ; -wire \counter[10]~46 ; -wire \counter[11]~47_combout ; -wire \counter[11]~48 ; -wire \counter[12]~49_combout ; -wire \counter[12]~50 ; -wire \counter[13]~51_combout ; -wire \counter[13]~52 ; -wire \counter[14]~53_combout ; -wire \counter[14]~54 ; -wire \counter[15]~55_combout ; -wire \counter[15]~56 ; -wire \counter[16]~57_combout ; -wire \counter[16]~58 ; -wire \counter[17]~59_combout ; -wire \counter[17]~60 ; -wire \counter[18]~61_combout ; -wire \counter[18]~62 ; -wire \counter[19]~63_combout ; -wire \counter[19]~64 ; -wire \counter[20]~65_combout ; -wire \counter[20]~66 ; -wire \counter[21]~67_combout ; -wire \LED[0]~reg0feeder_combout ; -wire \LED[0]~reg0_q ; -wire \counter[21]~68 ; -wire \counter[22]~69_combout ; -wire \LED[1]~reg0feeder_combout ; -wire \LED[1]~reg0_q ; -wire \counter[22]~70 ; -wire \counter[23]~71_combout ; -wire \LED[2]~reg0feeder_combout ; -wire \LED[2]~reg0_q ; -wire \counter[23]~72 ; -wire \counter[24]~73_combout ; -wire \LED[3]~reg0feeder_combout ; -wire \LED[3]~reg0_q ; -wire \counter[24]~74 ; -wire \counter[25]~75_combout ; -wire \LED[4]~reg0feeder_combout ; -wire \LED[4]~reg0_q ; -wire \counter[25]~76 ; -wire \counter[26]~77_combout ; -wire \LED[5]~reg0feeder_combout ; -wire \LED[5]~reg0_q ; -wire \counter[26]~78 ; -wire \counter[27]~79_combout ; -wire \LED[6]~reg0feeder_combout ; -wire \LED[6]~reg0_q ; -wire [27:0] counter; +wire \Add0~0_combout ; +wire \Add0~1 ; +wire \Add0~2_combout ; +wire \Add0~3 ; +wire \Add0~4_combout ; +wire \Add0~5 ; +wire \Add0~6_combout ; +wire \Add0~7 ; +wire \Add0~8_combout ; +wire \Add0~9 ; +wire \Add0~10_combout ; +wire \Add0~11 ; +wire \Add0~12_combout ; +wire \Add0~13 ; +wire \Add0~14_combout ; +wire \Add0~15 ; +wire \Add0~16_combout ; +wire \Add0~17 ; +wire \Add0~18_combout ; +wire \Add0~19 ; +wire \Add0~20_combout ; +wire \Add0~21 ; +wire \Add0~22_combout ; +wire \Add0~23 ; +wire \Add0~24_combout ; +wire \Add0~25 ; +wire \Add0~26_combout ; +wire \Add0~27 ; +wire \Add0~28_combout ; +wire \Add0~29 ; +wire \Add0~30_combout ; +wire \Add0~31 ; +wire \Add0~32_combout ; +wire \Add0~33 ; +wire \Add0~34_combout ; +wire \Add0~35 ; +wire \Add0~36_combout ; +wire \Add0~37 ; +wire \Add0~38_combout ; +wire \Add0~39 ; +wire \Add0~40_combout ; +wire \Equal0~5_combout ; +wire \Equal0~1_combout ; +wire \Equal0~0_combout ; +wire \Equal0~2_combout ; +wire \Equal0~3_combout ; +wire \Equal0~4_combout ; +wire \address[0]~0_combout ; +wire \Equal0~6_combout ; +wire \Equal0~7_combout ; +wire \address[1]~1_combout ; +wire \address[1]~2_combout ; +wire \address[2]~3_combout ; +wire [20:0] counter; +wire [2:0] address; +wire [7:0] \rom|altsyncram_component|auto_generated|q_a ; +wire [17:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; + +assign \rom|altsyncram_component|auto_generated|q_a [0] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|q_a [1] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [1]; +assign \rom|altsyncram_component|auto_generated|q_a [2] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [2]; +assign \rom|altsyncram_component|auto_generated|q_a [3] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [3]; +assign \rom|altsyncram_component|auto_generated|q_a [4] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [4]; +assign \rom|altsyncram_component|auto_generated|q_a [5] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [5]; +assign \rom|altsyncram_component|auto_generated|q_a [6] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [6]; +assign \rom|altsyncram_component|auto_generated|q_a [7] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [7]; // Location: IOOBUF_X38_Y34_N16 cycloneive_io_obuf \LED[0]~output ( - .i(\LED[0]~reg0_q ), + .i(\rom|altsyncram_component|auto_generated|q_a [0]), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -157,7 +154,7 @@ defparam \LED[0]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y34_N2 cycloneive_io_obuf \LED[1]~output ( - .i(\LED[1]~reg0_q ), + .i(\rom|altsyncram_component|auto_generated|q_a [1]), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -170,7 +167,7 @@ defparam \LED[1]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y34_N9 cycloneive_io_obuf \LED[2]~output ( - .i(\LED[2]~reg0_q ), + .i(\rom|altsyncram_component|auto_generated|q_a [2]), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -183,7 +180,7 @@ defparam \LED[2]~output .open_drain_output = "false"; // Location: IOOBUF_X40_Y34_N2 cycloneive_io_obuf \LED[3]~output ( - .i(\LED[3]~reg0_q ), + .i(\rom|altsyncram_component|auto_generated|q_a [3]), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -196,7 +193,7 @@ defparam \LED[3]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y25_N9 cycloneive_io_obuf \LED[4]~output ( - .i(\LED[4]~reg0_q ), + .i(\rom|altsyncram_component|auto_generated|q_a [4]), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -209,7 +206,7 @@ defparam \LED[4]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y26_N16 cycloneive_io_obuf \LED[5]~output ( - .i(\LED[5]~reg0_q ), + .i(\rom|altsyncram_component|auto_generated|q_a [5]), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -222,7 +219,7 @@ defparam \LED[5]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y28_N9 cycloneive_io_obuf \LED[6]~output ( - .i(\LED[6]~reg0_q ), + .i(\rom|altsyncram_component|auto_generated|q_a [6]), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -235,7 +232,7 @@ defparam \LED[6]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y10_N23 cycloneive_io_obuf \LED[7]~output ( - .i(gnd), + .i(\rom|altsyncram_component|auto_generated|q_a [7]), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -269,767 +266,10 @@ defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N4 -cycloneive_lcell_comb \counter[0]~81 ( -// Equation(s): -// \counter[0]~81_combout = !counter[0] - - .dataa(gnd), - .datab(gnd), - .datac(counter[0]), - .datad(gnd), - .cin(gnd), - .combout(\counter[0]~81_combout ), - .cout()); -// synopsys translate_off -defparam \counter[0]~81 .lut_mask = 16'h0F0F; -defparam \counter[0]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y33_N5 -dffeas \counter[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[0]~81_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[0]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[0] .is_wysiwyg = "true"; -defparam \counter[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N6 -cycloneive_lcell_comb \counter[1]~27 ( -// Equation(s): -// \counter[1]~27_combout = (counter[1] & (counter[0] $ (VCC))) # (!counter[1] & (counter[0] & VCC)) -// \counter[1]~28 = CARRY((counter[1] & counter[0])) - - .dataa(counter[1]), - .datab(counter[0]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\counter[1]~27_combout ), - .cout(\counter[1]~28 )); -// synopsys translate_off -defparam \counter[1]~27 .lut_mask = 16'h6688; -defparam \counter[1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y33_N7 -dffeas \counter[1] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[1]~27_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[1]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[1] .is_wysiwyg = "true"; -defparam \counter[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N8 -cycloneive_lcell_comb \counter[2]~29 ( -// Equation(s): -// \counter[2]~29_combout = (counter[2] & (!\counter[1]~28 )) # (!counter[2] & ((\counter[1]~28 ) # (GND))) -// \counter[2]~30 = CARRY((!\counter[1]~28 ) # (!counter[2])) - - .dataa(gnd), - .datab(counter[2]), - .datac(gnd), - .datad(vcc), - .cin(\counter[1]~28 ), - .combout(\counter[2]~29_combout ), - .cout(\counter[2]~30 )); -// synopsys translate_off -defparam \counter[2]~29 .lut_mask = 16'h3C3F; -defparam \counter[2]~29 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N9 -dffeas \counter[2] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[2]~29_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[2]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[2] .is_wysiwyg = "true"; -defparam \counter[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N10 -cycloneive_lcell_comb \counter[3]~31 ( -// Equation(s): -// \counter[3]~31_combout = (counter[3] & (\counter[2]~30 $ (GND))) # (!counter[3] & (!\counter[2]~30 & VCC)) -// \counter[3]~32 = CARRY((counter[3] & !\counter[2]~30 )) - - .dataa(counter[3]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\counter[2]~30 ), - .combout(\counter[3]~31_combout ), - .cout(\counter[3]~32 )); -// synopsys translate_off -defparam \counter[3]~31 .lut_mask = 16'hA50A; -defparam \counter[3]~31 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N11 -dffeas \counter[3] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[3]~31_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[3]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[3] .is_wysiwyg = "true"; -defparam \counter[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N12 -cycloneive_lcell_comb \counter[4]~33 ( -// Equation(s): -// \counter[4]~33_combout = (counter[4] & (!\counter[3]~32 )) # (!counter[4] & ((\counter[3]~32 ) # (GND))) -// \counter[4]~34 = CARRY((!\counter[3]~32 ) # (!counter[4])) - - .dataa(counter[4]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\counter[3]~32 ), - .combout(\counter[4]~33_combout ), - .cout(\counter[4]~34 )); -// synopsys translate_off -defparam \counter[4]~33 .lut_mask = 16'h5A5F; -defparam \counter[4]~33 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N13 -dffeas \counter[4] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[4]~33_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[4]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[4] .is_wysiwyg = "true"; -defparam \counter[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N14 -cycloneive_lcell_comb \counter[5]~35 ( -// Equation(s): -// \counter[5]~35_combout = (counter[5] & (\counter[4]~34 $ (GND))) # (!counter[5] & (!\counter[4]~34 & VCC)) -// \counter[5]~36 = CARRY((counter[5] & !\counter[4]~34 )) - - .dataa(gnd), - .datab(counter[5]), - .datac(gnd), - .datad(vcc), - .cin(\counter[4]~34 ), - .combout(\counter[5]~35_combout ), - .cout(\counter[5]~36 )); -// synopsys translate_off -defparam \counter[5]~35 .lut_mask = 16'hC30C; -defparam \counter[5]~35 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N15 -dffeas \counter[5] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[5]~35_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[5]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[5] .is_wysiwyg = "true"; -defparam \counter[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N16 -cycloneive_lcell_comb \counter[6]~37 ( -// Equation(s): -// \counter[6]~37_combout = (counter[6] & (!\counter[5]~36 )) # (!counter[6] & ((\counter[5]~36 ) # (GND))) -// \counter[6]~38 = CARRY((!\counter[5]~36 ) # (!counter[6])) - - .dataa(gnd), - .datab(counter[6]), - .datac(gnd), - .datad(vcc), - .cin(\counter[5]~36 ), - .combout(\counter[6]~37_combout ), - .cout(\counter[6]~38 )); -// synopsys translate_off -defparam \counter[6]~37 .lut_mask = 16'h3C3F; -defparam \counter[6]~37 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N17 -dffeas \counter[6] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[6]~37_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[6]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[6] .is_wysiwyg = "true"; -defparam \counter[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N18 -cycloneive_lcell_comb \counter[7]~39 ( -// Equation(s): -// \counter[7]~39_combout = (counter[7] & (\counter[6]~38 $ (GND))) # (!counter[7] & (!\counter[6]~38 & VCC)) -// \counter[7]~40 = CARRY((counter[7] & !\counter[6]~38 )) - - .dataa(gnd), - .datab(counter[7]), - .datac(gnd), - .datad(vcc), - .cin(\counter[6]~38 ), - .combout(\counter[7]~39_combout ), - .cout(\counter[7]~40 )); -// synopsys translate_off -defparam \counter[7]~39 .lut_mask = 16'hC30C; -defparam \counter[7]~39 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N19 -dffeas \counter[7] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[7]~39_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[7]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[7] .is_wysiwyg = "true"; -defparam \counter[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N20 -cycloneive_lcell_comb \counter[8]~41 ( -// Equation(s): -// \counter[8]~41_combout = (counter[8] & (!\counter[7]~40 )) # (!counter[8] & ((\counter[7]~40 ) # (GND))) -// \counter[8]~42 = CARRY((!\counter[7]~40 ) # (!counter[8])) - - .dataa(gnd), - .datab(counter[8]), - .datac(gnd), - .datad(vcc), - .cin(\counter[7]~40 ), - .combout(\counter[8]~41_combout ), - .cout(\counter[8]~42 )); -// synopsys translate_off -defparam \counter[8]~41 .lut_mask = 16'h3C3F; -defparam \counter[8]~41 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N21 -dffeas \counter[8] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[8]~41_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[8]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[8] .is_wysiwyg = "true"; -defparam \counter[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N22 -cycloneive_lcell_comb \counter[9]~43 ( -// Equation(s): -// \counter[9]~43_combout = (counter[9] & (\counter[8]~42 $ (GND))) # (!counter[9] & (!\counter[8]~42 & VCC)) -// \counter[9]~44 = CARRY((counter[9] & !\counter[8]~42 )) - - .dataa(counter[9]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\counter[8]~42 ), - .combout(\counter[9]~43_combout ), - .cout(\counter[9]~44 )); -// synopsys translate_off -defparam \counter[9]~43 .lut_mask = 16'hA50A; -defparam \counter[9]~43 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N23 -dffeas \counter[9] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[9]~43_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[9]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[9] .is_wysiwyg = "true"; -defparam \counter[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N24 -cycloneive_lcell_comb \counter[10]~45 ( -// Equation(s): -// \counter[10]~45_combout = (counter[10] & (!\counter[9]~44 )) # (!counter[10] & ((\counter[9]~44 ) # (GND))) -// \counter[10]~46 = CARRY((!\counter[9]~44 ) # (!counter[10])) - - .dataa(gnd), - .datab(counter[10]), - .datac(gnd), - .datad(vcc), - .cin(\counter[9]~44 ), - .combout(\counter[10]~45_combout ), - .cout(\counter[10]~46 )); -// synopsys translate_off -defparam \counter[10]~45 .lut_mask = 16'h3C3F; -defparam \counter[10]~45 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N25 -dffeas \counter[10] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[10]~45_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[10]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[10] .is_wysiwyg = "true"; -defparam \counter[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N26 -cycloneive_lcell_comb \counter[11]~47 ( -// Equation(s): -// \counter[11]~47_combout = (counter[11] & (\counter[10]~46 $ (GND))) # (!counter[11] & (!\counter[10]~46 & VCC)) -// \counter[11]~48 = CARRY((counter[11] & !\counter[10]~46 )) - - .dataa(counter[11]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\counter[10]~46 ), - .combout(\counter[11]~47_combout ), - .cout(\counter[11]~48 )); -// synopsys translate_off -defparam \counter[11]~47 .lut_mask = 16'hA50A; -defparam \counter[11]~47 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N27 -dffeas \counter[11] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[11]~47_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[11]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[11] .is_wysiwyg = "true"; -defparam \counter[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N28 -cycloneive_lcell_comb \counter[12]~49 ( -// Equation(s): -// \counter[12]~49_combout = (counter[12] & (!\counter[11]~48 )) # (!counter[12] & ((\counter[11]~48 ) # (GND))) -// \counter[12]~50 = CARRY((!\counter[11]~48 ) # (!counter[12])) - - .dataa(gnd), - .datab(counter[12]), - .datac(gnd), - .datad(vcc), - .cin(\counter[11]~48 ), - .combout(\counter[12]~49_combout ), - .cout(\counter[12]~50 )); -// synopsys translate_off -defparam \counter[12]~49 .lut_mask = 16'h3C3F; -defparam \counter[12]~49 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N29 -dffeas \counter[12] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[12]~49_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[12]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[12] .is_wysiwyg = "true"; -defparam \counter[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N30 -cycloneive_lcell_comb \counter[13]~51 ( -// Equation(s): -// \counter[13]~51_combout = (counter[13] & (\counter[12]~50 $ (GND))) # (!counter[13] & (!\counter[12]~50 & VCC)) -// \counter[13]~52 = CARRY((counter[13] & !\counter[12]~50 )) - - .dataa(counter[13]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\counter[12]~50 ), - .combout(\counter[13]~51_combout ), - .cout(\counter[13]~52 )); -// synopsys translate_off -defparam \counter[13]~51 .lut_mask = 16'hA50A; -defparam \counter[13]~51 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N31 -dffeas \counter[13] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[13]~51_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[13]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[13] .is_wysiwyg = "true"; -defparam \counter[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y32_N0 -cycloneive_lcell_comb \counter[14]~53 ( -// Equation(s): -// \counter[14]~53_combout = (counter[14] & (!\counter[13]~52 )) # (!counter[14] & ((\counter[13]~52 ) # (GND))) -// \counter[14]~54 = CARRY((!\counter[13]~52 ) # (!counter[14])) - - .dataa(gnd), - .datab(counter[14]), - .datac(gnd), - .datad(vcc), - .cin(\counter[13]~52 ), - .combout(\counter[14]~53_combout ), - .cout(\counter[14]~54 )); -// synopsys translate_off -defparam \counter[14]~53 .lut_mask = 16'h3C3F; -defparam \counter[14]~53 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N1 -dffeas \counter[14] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[14]~53_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[14]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[14] .is_wysiwyg = "true"; -defparam \counter[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y32_N2 -cycloneive_lcell_comb \counter[15]~55 ( -// Equation(s): -// \counter[15]~55_combout = (counter[15] & (\counter[14]~54 $ (GND))) # (!counter[15] & (!\counter[14]~54 & VCC)) -// \counter[15]~56 = CARRY((counter[15] & !\counter[14]~54 )) - - .dataa(gnd), - .datab(counter[15]), - .datac(gnd), - .datad(vcc), - .cin(\counter[14]~54 ), - .combout(\counter[15]~55_combout ), - .cout(\counter[15]~56 )); -// synopsys translate_off -defparam \counter[15]~55 .lut_mask = 16'hC30C; -defparam \counter[15]~55 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N3 -dffeas \counter[15] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[15]~55_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[15]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[15] .is_wysiwyg = "true"; -defparam \counter[15] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y32_N4 -cycloneive_lcell_comb \counter[16]~57 ( -// Equation(s): -// \counter[16]~57_combout = (counter[16] & (!\counter[15]~56 )) # (!counter[16] & ((\counter[15]~56 ) # (GND))) -// \counter[16]~58 = CARRY((!\counter[15]~56 ) # (!counter[16])) - - .dataa(gnd), - .datab(counter[16]), - .datac(gnd), - .datad(vcc), - .cin(\counter[15]~56 ), - .combout(\counter[16]~57_combout ), - .cout(\counter[16]~58 )); -// synopsys translate_off -defparam \counter[16]~57 .lut_mask = 16'h3C3F; -defparam \counter[16]~57 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N5 -dffeas \counter[16] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[16]~57_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[16]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[16] .is_wysiwyg = "true"; -defparam \counter[16] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y32_N6 -cycloneive_lcell_comb \counter[17]~59 ( -// Equation(s): -// \counter[17]~59_combout = (counter[17] & (\counter[16]~58 $ (GND))) # (!counter[17] & (!\counter[16]~58 & VCC)) -// \counter[17]~60 = CARRY((counter[17] & !\counter[16]~58 )) - - .dataa(counter[17]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\counter[16]~58 ), - .combout(\counter[17]~59_combout ), - .cout(\counter[17]~60 )); -// synopsys translate_off -defparam \counter[17]~59 .lut_mask = 16'hA50A; -defparam \counter[17]~59 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N7 -dffeas \counter[17] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[17]~59_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[17]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[17] .is_wysiwyg = "true"; -defparam \counter[17] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y32_N8 -cycloneive_lcell_comb \counter[18]~61 ( -// Equation(s): -// \counter[18]~61_combout = (counter[18] & (!\counter[17]~60 )) # (!counter[18] & ((\counter[17]~60 ) # (GND))) -// \counter[18]~62 = CARRY((!\counter[17]~60 ) # (!counter[18])) - - .dataa(gnd), - .datab(counter[18]), - .datac(gnd), - .datad(vcc), - .cin(\counter[17]~60 ), - .combout(\counter[18]~61_combout ), - .cout(\counter[18]~62 )); -// synopsys translate_off -defparam \counter[18]~61 .lut_mask = 16'h3C3F; -defparam \counter[18]~61 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N9 -dffeas \counter[18] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[18]~61_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[18]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[18] .is_wysiwyg = "true"; -defparam \counter[18] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y32_N10 -cycloneive_lcell_comb \counter[19]~63 ( -// Equation(s): -// \counter[19]~63_combout = (counter[19] & (\counter[18]~62 $ (GND))) # (!counter[19] & (!\counter[18]~62 & VCC)) -// \counter[19]~64 = CARRY((counter[19] & !\counter[18]~62 )) - - .dataa(counter[19]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\counter[18]~62 ), - .combout(\counter[19]~63_combout ), - .cout(\counter[19]~64 )); -// synopsys translate_off -defparam \counter[19]~63 .lut_mask = 16'hA50A; -defparam \counter[19]~63 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N11 -dffeas \counter[19] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[19]~63_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[19]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[19] .is_wysiwyg = "true"; -defparam \counter[19] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y32_N12 -cycloneive_lcell_comb \counter[20]~65 ( -// Equation(s): -// \counter[20]~65_combout = (counter[20] & (!\counter[19]~64 )) # (!counter[20] & ((\counter[19]~64 ) # (GND))) -// \counter[20]~66 = CARRY((!\counter[19]~64 ) # (!counter[20])) - - .dataa(counter[20]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\counter[19]~64 ), - .combout(\counter[20]~65_combout ), - .cout(\counter[20]~66 )); -// synopsys translate_off -defparam \counter[20]~65 .lut_mask = 16'h5A5F; -defparam \counter[20]~65 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N13 +// Location: FF_X31_Y17_N21 dffeas \counter[20] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[20]~65_combout ), + .d(\Add0~40_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1045,356 +285,28 @@ defparam \counter[20] .is_wysiwyg = "true"; defparam \counter[20] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y32_N14 -cycloneive_lcell_comb \counter[21]~67 ( +// Location: LCCOMB_X31_Y18_N12 +cycloneive_lcell_comb \Add0~0 ( // Equation(s): -// \counter[21]~67_combout = (counter[21] & (\counter[20]~66 $ (GND))) # (!counter[21] & (!\counter[20]~66 & VCC)) -// \counter[21]~68 = CARRY((counter[21] & !\counter[20]~66 )) +// \Add0~0_combout = counter[0] $ (VCC) +// \Add0~1 = CARRY(counter[0]) - .dataa(gnd), - .datab(counter[21]), - .datac(gnd), - .datad(vcc), - .cin(\counter[20]~66 ), - .combout(\counter[21]~67_combout ), - .cout(\counter[21]~68 )); -// synopsys translate_off -defparam \counter[21]~67 .lut_mask = 16'hC30C; -defparam \counter[21]~67 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N15 -dffeas \counter[21] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[21]~67_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[21]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[21] .is_wysiwyg = "true"; -defparam \counter[21] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y32_N4 -cycloneive_lcell_comb \LED[0]~reg0feeder ( -// Equation(s): -// \LED[0]~reg0feeder_combout = counter[21] - - .dataa(gnd), - .datab(gnd), - .datac(counter[21]), - .datad(gnd), - .cin(gnd), - .combout(\LED[0]~reg0feeder_combout ), - .cout()); -// synopsys translate_off -defparam \LED[0]~reg0feeder .lut_mask = 16'hF0F0; -defparam \LED[0]~reg0feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y32_N5 -dffeas \LED[0]~reg0 ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\LED[0]~reg0feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\LED[0]~reg0_q ), - .prn(vcc)); -// synopsys translate_off -defparam \LED[0]~reg0 .is_wysiwyg = "true"; -defparam \LED[0]~reg0 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y32_N16 -cycloneive_lcell_comb \counter[22]~69 ( -// Equation(s): -// \counter[22]~69_combout = (counter[22] & (!\counter[21]~68 )) # (!counter[22] & ((\counter[21]~68 ) # (GND))) -// \counter[22]~70 = CARRY((!\counter[21]~68 ) # (!counter[22])) - - .dataa(gnd), - .datab(counter[22]), - .datac(gnd), - .datad(vcc), - .cin(\counter[21]~68 ), - .combout(\counter[22]~69_combout ), - .cout(\counter[22]~70 )); -// synopsys translate_off -defparam \counter[22]~69 .lut_mask = 16'h3C3F; -defparam \counter[22]~69 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N17 -dffeas \counter[22] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[22]~69_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[22]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[22] .is_wysiwyg = "true"; -defparam \counter[22] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y32_N12 -cycloneive_lcell_comb \LED[1]~reg0feeder ( -// Equation(s): -// \LED[1]~reg0feeder_combout = counter[22] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(counter[22]), - .cin(gnd), - .combout(\LED[1]~reg0feeder_combout ), - .cout()); -// synopsys translate_off -defparam \LED[1]~reg0feeder .lut_mask = 16'hFF00; -defparam \LED[1]~reg0feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X46_Y32_N13 -dffeas \LED[1]~reg0 ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\LED[1]~reg0feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\LED[1]~reg0_q ), - .prn(vcc)); -// synopsys translate_off -defparam \LED[1]~reg0 .is_wysiwyg = "true"; -defparam \LED[1]~reg0 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y32_N18 -cycloneive_lcell_comb \counter[23]~71 ( -// Equation(s): -// \counter[23]~71_combout = (counter[23] & (\counter[22]~70 $ (GND))) # (!counter[23] & (!\counter[22]~70 & VCC)) -// \counter[23]~72 = CARRY((counter[23] & !\counter[22]~70 )) - - .dataa(gnd), - .datab(counter[23]), - .datac(gnd), - .datad(vcc), - .cin(\counter[22]~70 ), - .combout(\counter[23]~71_combout ), - .cout(\counter[23]~72 )); -// synopsys translate_off -defparam \counter[23]~71 .lut_mask = 16'hC30C; -defparam \counter[23]~71 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N19 -dffeas \counter[23] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[23]~71_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[23]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[23] .is_wysiwyg = "true"; -defparam \counter[23] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y32_N6 -cycloneive_lcell_comb \LED[2]~reg0feeder ( -// Equation(s): -// \LED[2]~reg0feeder_combout = counter[23] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(counter[23]), - .cin(gnd), - .combout(\LED[2]~reg0feeder_combout ), - .cout()); -// synopsys translate_off -defparam \LED[2]~reg0feeder .lut_mask = 16'hFF00; -defparam \LED[2]~reg0feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X46_Y32_N7 -dffeas \LED[2]~reg0 ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\LED[2]~reg0feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\LED[2]~reg0_q ), - .prn(vcc)); -// synopsys translate_off -defparam \LED[2]~reg0 .is_wysiwyg = "true"; -defparam \LED[2]~reg0 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y32_N20 -cycloneive_lcell_comb \counter[24]~73 ( -// Equation(s): -// \counter[24]~73_combout = (counter[24] & (!\counter[23]~72 )) # (!counter[24] & ((\counter[23]~72 ) # (GND))) -// \counter[24]~74 = CARRY((!\counter[23]~72 ) # (!counter[24])) - - .dataa(gnd), - .datab(counter[24]), - .datac(gnd), - .datad(vcc), - .cin(\counter[23]~72 ), - .combout(\counter[24]~73_combout ), - .cout(\counter[24]~74 )); -// synopsys translate_off -defparam \counter[24]~73 .lut_mask = 16'h3C3F; -defparam \counter[24]~73 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N21 -dffeas \counter[24] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[24]~73_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[24]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[24] .is_wysiwyg = "true"; -defparam \counter[24] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y32_N4 -cycloneive_lcell_comb \LED[3]~reg0feeder ( -// Equation(s): -// \LED[3]~reg0feeder_combout = counter[24] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(counter[24]), - .cin(gnd), - .combout(\LED[3]~reg0feeder_combout ), - .cout()); -// synopsys translate_off -defparam \LED[3]~reg0feeder .lut_mask = 16'hFF00; -defparam \LED[3]~reg0feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y32_N5 -dffeas \LED[3]~reg0 ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\LED[3]~reg0feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\LED[3]~reg0_q ), - .prn(vcc)); -// synopsys translate_off -defparam \LED[3]~reg0 .is_wysiwyg = "true"; -defparam \LED[3]~reg0 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y32_N22 -cycloneive_lcell_comb \counter[25]~75 ( -// Equation(s): -// \counter[25]~75_combout = (counter[25] & (\counter[24]~74 $ (GND))) # (!counter[25] & (!\counter[24]~74 & VCC)) -// \counter[25]~76 = CARRY((counter[25] & !\counter[24]~74 )) - - .dataa(counter[25]), + .dataa(counter[0]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\counter[24]~74 ), - .combout(\counter[25]~75_combout ), - .cout(\counter[25]~76 )); -// synopsys translate_off -defparam \counter[25]~75 .lut_mask = 16'hA50A; -defparam \counter[25]~75 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N23 -dffeas \counter[25] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[25]~75_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[25]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[25] .is_wysiwyg = "true"; -defparam \counter[25] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y32_N18 -cycloneive_lcell_comb \LED[4]~reg0feeder ( -// Equation(s): -// \LED[4]~reg0feeder_combout = counter[25] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(counter[25]), .cin(gnd), - .combout(\LED[4]~reg0feeder_combout ), - .cout()); + .combout(\Add0~0_combout ), + .cout(\Add0~1 )); // synopsys translate_off -defparam \LED[4]~reg0feeder .lut_mask = 16'hFF00; -defparam \LED[4]~reg0feeder .sum_lutc_input = "datac"; +defparam \Add0~0 .lut_mask = 16'h55AA; +defparam \Add0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y32_N19 -dffeas \LED[4]~reg0 ( +// Location: FF_X31_Y18_N13 +dffeas \counter[0] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\LED[4]~reg0feeder_combout ), + .d(\Add0~0_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1403,35 +315,35 @@ dffeas \LED[4]~reg0 ( .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\LED[4]~reg0_q ), + .q(counter[0]), .prn(vcc)); // synopsys translate_off -defparam \LED[4]~reg0 .is_wysiwyg = "true"; -defparam \LED[4]~reg0 .power_up = "low"; +defparam \counter[0] .is_wysiwyg = "true"; +defparam \counter[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y32_N24 -cycloneive_lcell_comb \counter[26]~77 ( +// Location: LCCOMB_X31_Y18_N14 +cycloneive_lcell_comb \Add0~2 ( // Equation(s): -// \counter[26]~77_combout = (counter[26] & (!\counter[25]~76 )) # (!counter[26] & ((\counter[25]~76 ) # (GND))) -// \counter[26]~78 = CARRY((!\counter[25]~76 ) # (!counter[26])) +// \Add0~2_combout = (counter[1] & (!\Add0~1 )) # (!counter[1] & ((\Add0~1 ) # (GND))) +// \Add0~3 = CARRY((!\Add0~1 ) # (!counter[1])) .dataa(gnd), - .datab(counter[26]), + .datab(counter[1]), .datac(gnd), .datad(vcc), - .cin(\counter[25]~76 ), - .combout(\counter[26]~77_combout ), - .cout(\counter[26]~78 )); + .cin(\Add0~1 ), + .combout(\Add0~2_combout ), + .cout(\Add0~3 )); // synopsys translate_off -defparam \counter[26]~77 .lut_mask = 16'h3C3F; -defparam \counter[26]~77 .sum_lutc_input = "cin"; +defparam \Add0~2 .lut_mask = 16'h3C3F; +defparam \Add0~2 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X39_Y32_N25 -dffeas \counter[26] ( +// Location: FF_X31_Y18_N15 +dffeas \counter[1] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[26]~77_combout ), + .d(\Add0~2_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1440,34 +352,819 @@ dffeas \counter[26] ( .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(counter[26]), + .q(counter[1]), .prn(vcc)); // synopsys translate_off -defparam \counter[26] .is_wysiwyg = "true"; -defparam \counter[26] .power_up = "low"; +defparam \counter[1] .is_wysiwyg = "true"; +defparam \counter[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y32_N24 -cycloneive_lcell_comb \LED[5]~reg0feeder ( +// Location: LCCOMB_X31_Y18_N16 +cycloneive_lcell_comb \Add0~4 ( // Equation(s): -// \LED[5]~reg0feeder_combout = counter[26] +// \Add0~4_combout = (counter[2] & (\Add0~3 $ (GND))) # (!counter[2] & (!\Add0~3 & VCC)) +// \Add0~5 = CARRY((counter[2] & !\Add0~3 )) + + .dataa(gnd), + .datab(counter[2]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~3 ), + .combout(\Add0~4_combout ), + .cout(\Add0~5 )); +// synopsys translate_off +defparam \Add0~4 .lut_mask = 16'hC30C; +defparam \Add0~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y18_N17 +dffeas \counter[2] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[2]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[2] .is_wysiwyg = "true"; +defparam \counter[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N18 +cycloneive_lcell_comb \Add0~6 ( +// Equation(s): +// \Add0~6_combout = (counter[3] & (!\Add0~5 )) # (!counter[3] & ((\Add0~5 ) # (GND))) +// \Add0~7 = CARRY((!\Add0~5 ) # (!counter[3])) + + .dataa(gnd), + .datab(counter[3]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~5 ), + .combout(\Add0~6_combout ), + .cout(\Add0~7 )); +// synopsys translate_off +defparam \Add0~6 .lut_mask = 16'h3C3F; +defparam \Add0~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y18_N19 +dffeas \counter[3] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[3]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[3] .is_wysiwyg = "true"; +defparam \counter[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N20 +cycloneive_lcell_comb \Add0~8 ( +// Equation(s): +// \Add0~8_combout = (counter[4] & (\Add0~7 $ (GND))) # (!counter[4] & (!\Add0~7 & VCC)) +// \Add0~9 = CARRY((counter[4] & !\Add0~7 )) + + .dataa(counter[4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add0~7 ), + .combout(\Add0~8_combout ), + .cout(\Add0~9 )); +// synopsys translate_off +defparam \Add0~8 .lut_mask = 16'hA50A; +defparam \Add0~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y18_N21 +dffeas \counter[4] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[4]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[4] .is_wysiwyg = "true"; +defparam \counter[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N22 +cycloneive_lcell_comb \Add0~10 ( +// Equation(s): +// \Add0~10_combout = (counter[5] & (!\Add0~9 )) # (!counter[5] & ((\Add0~9 ) # (GND))) +// \Add0~11 = CARRY((!\Add0~9 ) # (!counter[5])) + + .dataa(gnd), + .datab(counter[5]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~9 ), + .combout(\Add0~10_combout ), + .cout(\Add0~11 )); +// synopsys translate_off +defparam \Add0~10 .lut_mask = 16'h3C3F; +defparam \Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y18_N23 +dffeas \counter[5] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~10_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[5]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[5] .is_wysiwyg = "true"; +defparam \counter[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N24 +cycloneive_lcell_comb \Add0~12 ( +// Equation(s): +// \Add0~12_combout = (counter[6] & (\Add0~11 $ (GND))) # (!counter[6] & (!\Add0~11 & VCC)) +// \Add0~13 = CARRY((counter[6] & !\Add0~11 )) + + .dataa(counter[6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add0~11 ), + .combout(\Add0~12_combout ), + .cout(\Add0~13 )); +// synopsys translate_off +defparam \Add0~12 .lut_mask = 16'hA50A; +defparam \Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y18_N25 +dffeas \counter[6] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[6]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[6] .is_wysiwyg = "true"; +defparam \counter[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N26 +cycloneive_lcell_comb \Add0~14 ( +// Equation(s): +// \Add0~14_combout = (counter[7] & (!\Add0~13 )) # (!counter[7] & ((\Add0~13 ) # (GND))) +// \Add0~15 = CARRY((!\Add0~13 ) # (!counter[7])) + + .dataa(gnd), + .datab(counter[7]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~13 ), + .combout(\Add0~14_combout ), + .cout(\Add0~15 )); +// synopsys translate_off +defparam \Add0~14 .lut_mask = 16'h3C3F; +defparam \Add0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y18_N27 +dffeas \counter[7] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~14_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[7]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[7] .is_wysiwyg = "true"; +defparam \counter[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N28 +cycloneive_lcell_comb \Add0~16 ( +// Equation(s): +// \Add0~16_combout = (counter[8] & (\Add0~15 $ (GND))) # (!counter[8] & (!\Add0~15 & VCC)) +// \Add0~17 = CARRY((counter[8] & !\Add0~15 )) + + .dataa(gnd), + .datab(counter[8]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~15 ), + .combout(\Add0~16_combout ), + .cout(\Add0~17 )); +// synopsys translate_off +defparam \Add0~16 .lut_mask = 16'hC30C; +defparam \Add0~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y18_N29 +dffeas \counter[8] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~16_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[8]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[8] .is_wysiwyg = "true"; +defparam \counter[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N30 +cycloneive_lcell_comb \Add0~18 ( +// Equation(s): +// \Add0~18_combout = (counter[9] & (!\Add0~17 )) # (!counter[9] & ((\Add0~17 ) # (GND))) +// \Add0~19 = CARRY((!\Add0~17 ) # (!counter[9])) + + .dataa(counter[9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add0~17 ), + .combout(\Add0~18_combout ), + .cout(\Add0~19 )); +// synopsys translate_off +defparam \Add0~18 .lut_mask = 16'h5A5F; +defparam \Add0~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y18_N31 +dffeas \counter[9] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~18_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[9]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[9] .is_wysiwyg = "true"; +defparam \counter[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N0 +cycloneive_lcell_comb \Add0~20 ( +// Equation(s): +// \Add0~20_combout = (counter[10] & (\Add0~19 $ (GND))) # (!counter[10] & (!\Add0~19 & VCC)) +// \Add0~21 = CARRY((counter[10] & !\Add0~19 )) + + .dataa(gnd), + .datab(counter[10]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~19 ), + .combout(\Add0~20_combout ), + .cout(\Add0~21 )); +// synopsys translate_off +defparam \Add0~20 .lut_mask = 16'hC30C; +defparam \Add0~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y17_N1 +dffeas \counter[10] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~20_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[10]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[10] .is_wysiwyg = "true"; +defparam \counter[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N2 +cycloneive_lcell_comb \Add0~22 ( +// Equation(s): +// \Add0~22_combout = (counter[11] & (!\Add0~21 )) # (!counter[11] & ((\Add0~21 ) # (GND))) +// \Add0~23 = CARRY((!\Add0~21 ) # (!counter[11])) + + .dataa(gnd), + .datab(counter[11]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~21 ), + .combout(\Add0~22_combout ), + .cout(\Add0~23 )); +// synopsys translate_off +defparam \Add0~22 .lut_mask = 16'h3C3F; +defparam \Add0~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y17_N3 +dffeas \counter[11] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~22_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[11]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[11] .is_wysiwyg = "true"; +defparam \counter[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N4 +cycloneive_lcell_comb \Add0~24 ( +// Equation(s): +// \Add0~24_combout = (counter[12] & (\Add0~23 $ (GND))) # (!counter[12] & (!\Add0~23 & VCC)) +// \Add0~25 = CARRY((counter[12] & !\Add0~23 )) + + .dataa(gnd), + .datab(counter[12]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~23 ), + .combout(\Add0~24_combout ), + .cout(\Add0~25 )); +// synopsys translate_off +defparam \Add0~24 .lut_mask = 16'hC30C; +defparam \Add0~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y17_N5 +dffeas \counter[12] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~24_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[12]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[12] .is_wysiwyg = "true"; +defparam \counter[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N6 +cycloneive_lcell_comb \Add0~26 ( +// Equation(s): +// \Add0~26_combout = (counter[13] & (!\Add0~25 )) # (!counter[13] & ((\Add0~25 ) # (GND))) +// \Add0~27 = CARRY((!\Add0~25 ) # (!counter[13])) + + .dataa(gnd), + .datab(counter[13]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~25 ), + .combout(\Add0~26_combout ), + .cout(\Add0~27 )); +// synopsys translate_off +defparam \Add0~26 .lut_mask = 16'h3C3F; +defparam \Add0~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y17_N7 +dffeas \counter[13] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~26_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[13]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[13] .is_wysiwyg = "true"; +defparam \counter[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N8 +cycloneive_lcell_comb \Add0~28 ( +// Equation(s): +// \Add0~28_combout = (counter[14] & (\Add0~27 $ (GND))) # (!counter[14] & (!\Add0~27 & VCC)) +// \Add0~29 = CARRY((counter[14] & !\Add0~27 )) + + .dataa(counter[14]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add0~27 ), + .combout(\Add0~28_combout ), + .cout(\Add0~29 )); +// synopsys translate_off +defparam \Add0~28 .lut_mask = 16'hA50A; +defparam \Add0~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y17_N9 +dffeas \counter[14] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~28_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[14]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[14] .is_wysiwyg = "true"; +defparam \counter[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N10 +cycloneive_lcell_comb \Add0~30 ( +// Equation(s): +// \Add0~30_combout = (counter[15] & (!\Add0~29 )) # (!counter[15] & ((\Add0~29 ) # (GND))) +// \Add0~31 = CARRY((!\Add0~29 ) # (!counter[15])) + + .dataa(gnd), + .datab(counter[15]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~29 ), + .combout(\Add0~30_combout ), + .cout(\Add0~31 )); +// synopsys translate_off +defparam \Add0~30 .lut_mask = 16'h3C3F; +defparam \Add0~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y17_N11 +dffeas \counter[15] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~30_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[15]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[15] .is_wysiwyg = "true"; +defparam \counter[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N12 +cycloneive_lcell_comb \Add0~32 ( +// Equation(s): +// \Add0~32_combout = (counter[16] & (\Add0~31 $ (GND))) # (!counter[16] & (!\Add0~31 & VCC)) +// \Add0~33 = CARRY((counter[16] & !\Add0~31 )) + + .dataa(gnd), + .datab(counter[16]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~31 ), + .combout(\Add0~32_combout ), + .cout(\Add0~33 )); +// synopsys translate_off +defparam \Add0~32 .lut_mask = 16'hC30C; +defparam \Add0~32 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y17_N13 +dffeas \counter[16] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~32_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[16]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[16] .is_wysiwyg = "true"; +defparam \counter[16] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N14 +cycloneive_lcell_comb \Add0~34 ( +// Equation(s): +// \Add0~34_combout = (counter[17] & (!\Add0~33 )) # (!counter[17] & ((\Add0~33 ) # (GND))) +// \Add0~35 = CARRY((!\Add0~33 ) # (!counter[17])) + + .dataa(counter[17]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add0~33 ), + .combout(\Add0~34_combout ), + .cout(\Add0~35 )); +// synopsys translate_off +defparam \Add0~34 .lut_mask = 16'h5A5F; +defparam \Add0~34 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y17_N15 +dffeas \counter[17] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~34_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[17]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[17] .is_wysiwyg = "true"; +defparam \counter[17] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N16 +cycloneive_lcell_comb \Add0~36 ( +// Equation(s): +// \Add0~36_combout = (counter[18] & (\Add0~35 $ (GND))) # (!counter[18] & (!\Add0~35 & VCC)) +// \Add0~37 = CARRY((counter[18] & !\Add0~35 )) + + .dataa(counter[18]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add0~35 ), + .combout(\Add0~36_combout ), + .cout(\Add0~37 )); +// synopsys translate_off +defparam \Add0~36 .lut_mask = 16'hA50A; +defparam \Add0~36 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y17_N17 +dffeas \counter[18] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~36_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[18]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[18] .is_wysiwyg = "true"; +defparam \counter[18] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N18 +cycloneive_lcell_comb \Add0~38 ( +// Equation(s): +// \Add0~38_combout = (counter[19] & (!\Add0~37 )) # (!counter[19] & ((\Add0~37 ) # (GND))) +// \Add0~39 = CARRY((!\Add0~37 ) # (!counter[19])) + + .dataa(counter[19]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add0~37 ), + .combout(\Add0~38_combout ), + .cout(\Add0~39 )); +// synopsys translate_off +defparam \Add0~38 .lut_mask = 16'h5A5F; +defparam \Add0~38 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y17_N19 +dffeas \counter[19] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~38_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[19]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[19] .is_wysiwyg = "true"; +defparam \counter[19] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N20 +cycloneive_lcell_comb \Add0~40 ( +// Equation(s): +// \Add0~40_combout = \Add0~39 $ (!counter[20]) .dataa(gnd), .datab(gnd), .datac(gnd), - .datad(counter[26]), + .datad(counter[20]), + .cin(\Add0~39 ), + .combout(\Add0~40_combout ), + .cout()); +// synopsys translate_off +defparam \Add0~40 .lut_mask = 16'hF00F; +defparam \Add0~40 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N28 +cycloneive_lcell_comb \Equal0~5 ( +// Equation(s): +// \Equal0~5_combout = (!\Add0~32_combout & (!\Add0~36_combout & (!\Add0~34_combout & !\Add0~38_combout ))) + + .dataa(\Add0~32_combout ), + .datab(\Add0~36_combout ), + .datac(\Add0~34_combout ), + .datad(\Add0~38_combout ), .cin(gnd), - .combout(\LED[5]~reg0feeder_combout ), + .combout(\Equal0~5_combout ), .cout()); // synopsys translate_off -defparam \LED[5]~reg0feeder .lut_mask = 16'hFF00; -defparam \LED[5]~reg0feeder .sum_lutc_input = "datac"; +defparam \Equal0~5 .lut_mask = 16'h0001; +defparam \Equal0~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y32_N25 -dffeas \LED[5]~reg0 ( +// Location: LCCOMB_X31_Y18_N6 +cycloneive_lcell_comb \Equal0~1 ( +// Equation(s): +// \Equal0~1_combout = (!\Add0~10_combout & (!\Add0~8_combout & (!\Add0~14_combout & !\Add0~12_combout ))) + + .dataa(\Add0~10_combout ), + .datab(\Add0~8_combout ), + .datac(\Add0~14_combout ), + .datad(\Add0~12_combout ), + .cin(gnd), + .combout(\Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~1 .lut_mask = 16'h0001; +defparam \Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N4 +cycloneive_lcell_comb \Equal0~0 ( +// Equation(s): +// \Equal0~0_combout = (!\Add0~4_combout & (!\Add0~0_combout & (!\Add0~6_combout & !\Add0~2_combout ))) + + .dataa(\Add0~4_combout ), + .datab(\Add0~0_combout ), + .datac(\Add0~6_combout ), + .datad(\Add0~2_combout ), + .cin(gnd), + .combout(\Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~0 .lut_mask = 16'h0001; +defparam \Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N30 +cycloneive_lcell_comb \Equal0~2 ( +// Equation(s): +// \Equal0~2_combout = (!\Add0~22_combout & (!\Add0~16_combout & (!\Add0~20_combout & !\Add0~18_combout ))) + + .dataa(\Add0~22_combout ), + .datab(\Add0~16_combout ), + .datac(\Add0~20_combout ), + .datad(\Add0~18_combout ), + .cin(gnd), + .combout(\Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~2 .lut_mask = 16'h0001; +defparam \Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N30 +cycloneive_lcell_comb \Equal0~3 ( +// Equation(s): +// \Equal0~3_combout = (!\Add0~26_combout & (!\Add0~24_combout & (!\Add0~28_combout & !\Add0~30_combout ))) + + .dataa(\Add0~26_combout ), + .datab(\Add0~24_combout ), + .datac(\Add0~28_combout ), + .datad(\Add0~30_combout ), + .cin(gnd), + .combout(\Equal0~3_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~3 .lut_mask = 16'h0001; +defparam \Equal0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N28 +cycloneive_lcell_comb \Equal0~4 ( +// Equation(s): +// \Equal0~4_combout = (\Equal0~1_combout & (\Equal0~0_combout & (\Equal0~2_combout & \Equal0~3_combout ))) + + .dataa(\Equal0~1_combout ), + .datab(\Equal0~0_combout ), + .datac(\Equal0~2_combout ), + .datad(\Equal0~3_combout ), + .cin(gnd), + .combout(\Equal0~4_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~4 .lut_mask = 16'h8000; +defparam \Equal0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N20 +cycloneive_lcell_comb \address[0]~0 ( +// Equation(s): +// \address[0]~0_combout = address[0] $ (((!\Add0~40_combout & (\Equal0~5_combout & \Equal0~4_combout )))) + + .dataa(\Add0~40_combout ), + .datab(\Equal0~5_combout ), + .datac(address[0]), + .datad(\Equal0~4_combout ), + .cin(gnd), + .combout(\address[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \address[0]~0 .lut_mask = 16'hB4F0; +defparam \address[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N21 +dffeas \address[0] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\LED[5]~reg0feeder_combout ), + .d(\address[0]~0_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1476,70 +1173,68 @@ dffeas \LED[5]~reg0 ( .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\LED[5]~reg0_q ), + .q(address[0]), .prn(vcc)); // synopsys translate_off -defparam \LED[5]~reg0 .is_wysiwyg = "true"; -defparam \LED[5]~reg0 .power_up = "low"; +defparam \address[0] .is_wysiwyg = "true"; +defparam \address[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y32_N26 -cycloneive_lcell_comb \counter[27]~79 ( +// Location: LCCOMB_X31_Y17_N26 +cycloneive_lcell_comb \Equal0~6 ( // Equation(s): -// \counter[27]~79_combout = counter[27] $ (!\counter[26]~78 ) - - .dataa(counter[27]), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(\counter[26]~78 ), - .combout(\counter[27]~79_combout ), - .cout()); -// synopsys translate_off -defparam \counter[27]~79 .lut_mask = 16'hA5A5; -defparam \counter[27]~79 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N27 -dffeas \counter[27] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[27]~79_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[27]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[27] .is_wysiwyg = "true"; -defparam \counter[27] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y32_N14 -cycloneive_lcell_comb \LED[6]~reg0feeder ( -// Equation(s): -// \LED[6]~reg0feeder_combout = counter[27] +// \Equal0~6_combout = (!\Add0~34_combout & !\Add0~32_combout ) .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(counter[27]), + .datac(\Add0~34_combout ), + .datad(\Add0~32_combout ), .cin(gnd), - .combout(\LED[6]~reg0feeder_combout ), + .combout(\Equal0~6_combout ), .cout()); // synopsys translate_off -defparam \LED[6]~reg0feeder .lut_mask = 16'hFF00; -defparam \LED[6]~reg0feeder .sum_lutc_input = "datac"; +defparam \Equal0~6 .lut_mask = 16'h000F; +defparam \Equal0~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y32_N15 -dffeas \LED[6]~reg0 ( +// Location: LCCOMB_X31_Y17_N24 +cycloneive_lcell_comb \Equal0~7 ( +// Equation(s): +// \Equal0~7_combout = (!\Add0~40_combout & (!\Add0~36_combout & (\Equal0~6_combout & !\Add0~38_combout ))) + + .dataa(\Add0~40_combout ), + .datab(\Add0~36_combout ), + .datac(\Equal0~6_combout ), + .datad(\Add0~38_combout ), + .cin(gnd), + .combout(\Equal0~7_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~7 .lut_mask = 16'h0010; +defparam \Equal0~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N10 +cycloneive_lcell_comb \address[1]~1 ( +// Equation(s): +// \address[1]~1_combout = address[1] $ (((address[0] & (\Equal0~4_combout & \Equal0~7_combout )))) + + .dataa(address[0]), + .datab(\Equal0~4_combout ), + .datac(address[1]), + .datad(\Equal0~7_combout ), + .cin(gnd), + .combout(\address[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \address[1]~1 .lut_mask = 16'h78F0; +defparam \address[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N11 +dffeas \address[1] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\LED[6]~reg0feeder_combout ), + .d(\address[1]~1_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1548,11 +1243,116 @@ dffeas \LED[6]~reg0 ( .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\LED[6]~reg0_q ), + .q(address[1]), .prn(vcc)); // synopsys translate_off -defparam \LED[6]~reg0 .is_wysiwyg = "true"; -defparam \LED[6]~reg0 .power_up = "low"; +defparam \address[1] .is_wysiwyg = "true"; +defparam \address[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N2 +cycloneive_lcell_comb \address[1]~2 ( +// Equation(s): +// \address[1]~2_combout = (address[0] & (\Equal0~5_combout & (!\Add0~40_combout & \Equal0~4_combout ))) + + .dataa(address[0]), + .datab(\Equal0~5_combout ), + .datac(\Add0~40_combout ), + .datad(\Equal0~4_combout ), + .cin(gnd), + .combout(\address[1]~2_combout ), + .cout()); +// synopsys translate_off +defparam \address[1]~2 .lut_mask = 16'h0800; +defparam \address[1]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N16 +cycloneive_lcell_comb \address[2]~3 ( +// Equation(s): +// \address[2]~3_combout = address[2] $ (((address[1] & \address[1]~2_combout ))) + + .dataa(gnd), + .datab(address[1]), + .datac(address[2]), + .datad(\address[1]~2_combout ), + .cin(gnd), + .combout(\address[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \address[2]~3 .lut_mask = 16'h3CF0; +defparam \address[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N17 +dffeas \address[2] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[2]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(address[2]), + .prn(vcc)); +// synopsys translate_off +defparam \address[2] .is_wysiwyg = "true"; +defparam \address[2] .power_up = "low"; +// synopsys translate_on + +// Location: M9K_X33_Y26_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(vcc), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(18'b000000000000000000), + .portaaddr({address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(18'b000000000000000000), + .portbaddr(3'b000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 18; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 18; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 144'h002040042000900018000600024001080081; // synopsys translate_on assign LED[0] = \LED[0]~output_o ; diff --git a/simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo b/simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo index 9d25589..ce4aabf 100644 --- a/simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo +++ b/simulation/modelsim/spectrum_6_1200mv_0c_v_slow.sdo @@ -29,7 +29,7 @@ (DELAYFILE (SDFVERSION "2.1") (DESIGN "spectrum") - (DATE "03/30/2022 11:51:43") + (DATE "03/30/2022 12:38:42") (VENDOR "Altera") (PROGRAM "Quartus II 32-bit") (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") @@ -41,7 +41,7 @@ (INSTANCE LED\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (476:476:476) (485:485:485)) + (PORT i (1253:1253:1253) (1226:1226:1226)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -51,7 +51,7 @@ (INSTANCE LED\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (698:698:698) (688:688:688)) + (PORT i (1304:1304:1304) (1267:1267:1267)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -61,7 +61,7 @@ (INSTANCE LED\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (684:684:684) (669:669:669)) + (PORT i (1684:1684:1684) (1627:1627:1627)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -71,7 +71,7 @@ (INSTANCE LED\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (475:475:475) (484:484:484)) + (PORT i (1346:1346:1346) (1276:1276:1276)) (IOPATH i o (2265:2265:2265) (2180:2180:2180)) ) ) @@ -81,7 +81,7 @@ (INSTANCE LED\[4\]\~output) (DELAY (ABSOLUTE - (PORT i (2278:2278:2278) (2290:2290:2290)) + (PORT i (1648:1648:1648) (1591:1591:1591)) (IOPATH i o (2277:2277:2277) (2180:2180:2180)) ) ) @@ -91,7 +91,7 @@ (INSTANCE LED\[5\]\~output) (DELAY (ABSOLUTE - (PORT i (2269:2269:2269) (2279:2279:2279)) + (PORT i (1253:1253:1253) (1210:1210:1210)) (IOPATH i o (3961:3961:3961) (3539:3539:3539)) ) ) @@ -101,11 +101,21 @@ (INSTANCE LED\[6\]\~output) (DELAY (ABSOLUTE - (PORT i (1208:1208:1208) (1282:1282:1282)) + (PORT i (1728:1728:1728) (1679:1679:1679)) (IOPATH i o (2194:2194:2194) (2119:2119:2119)) ) ) ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE LED\[7\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1370:1370:1370) (1374:1374:1374)) + (IOPATH i o (3961:3961:3961) (3539:3539:3539)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_io_ibuf") (INSTANCE CLOCK_50\~input) @@ -125,11 +135,28 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[0\]\~81) + (CELLTYPE "dffeas") + (INSTANCE counter\[20\]) (DELAY (ABSOLUTE - (IOPATH datac combout (312:312:312) (325:325:325)) + (PORT clk (1352:1352:1352) (1368:1368:1368)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (295:295:295)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) @@ -138,7 +165,7 @@ (INSTANCE counter\[0\]) (DELAY (ABSOLUTE - (PORT clk (1354:1354:1354) (1369:1369:1369)) + (PORT clk (1352:1352:1352) (1368:1368:1368)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -149,16 +176,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[1\]\~27) + (INSTANCE Add0\~2) (DELAY (ABSOLUTE - (PORT dataa (221:221:221) (293:293:293)) - (PORT datab (220:220:220) (288:288:288)) - (IOPATH dataa combout (300:300:300) (323:323:323)) - (IOPATH dataa cout (376:376:376) (275:275:275)) - (IOPATH datab combout (306:306:306) (324:324:324)) + (PORT datab (221:221:221) (289:289:289)) + (IOPATH datab combout (325:325:325) (332:332:332)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) ) ) ) @@ -167,7 +193,7 @@ (INSTANCE counter\[1\]) (DELAY (ABSOLUTE - (PORT clk (1354:1354:1354) (1369:1369:1369)) + (PORT clk (1352:1352:1352) (1368:1368:1368)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -178,11 +204,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[2\]\~29) + (INSTANCE Add0\~4) (DELAY (ABSOLUTE (PORT datab (221:221:221) (289:289:289)) - (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab combout (319:319:319) (324:324:324)) (IOPATH datab cout (385:385:385) (280:280:280)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) @@ -195,7 +221,7 @@ (INSTANCE counter\[2\]) (DELAY (ABSOLUTE - (PORT clk (1354:1354:1354) (1369:1369:1369)) + (PORT clk (1352:1352:1352) (1368:1368:1368)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -206,371 +232,7 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[3\]\~31) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (296:296:296)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH dataa cout (376:376:376) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[3\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[4\]\~33) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (296:296:296)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH dataa cout (376:376:376) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[4\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[5\]\~35) - (DELAY - (ABSOLUTE - (PORT datab (221:221:221) (290:290:290)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datab cout (385:385:385) (280:280:280)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[5\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[6\]\~37) - (DELAY - (ABSOLUTE - (PORT datab (221:221:221) (290:290:290)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datab cout (385:385:385) (280:280:280)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[6\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[7\]\~39) - (DELAY - (ABSOLUTE - (PORT datab (221:221:221) (290:290:290)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datab cout (385:385:385) (280:280:280)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[7\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[8\]\~41) - (DELAY - (ABSOLUTE - (PORT datab (221:221:221) (291:291:291)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datab cout (385:385:385) (280:280:280)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[8\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[9\]\~43) - (DELAY - (ABSOLUTE - (PORT dataa (222:222:222) (294:294:294)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH dataa cout (376:376:376) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[9\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[10\]\~45) - (DELAY - (ABSOLUTE - (PORT datab (221:221:221) (289:289:289)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datab cout (385:385:385) (280:280:280)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[10\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[11\]\~47) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (293:293:293)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH dataa cout (376:376:376) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[11\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[12\]\~49) - (DELAY - (ABSOLUTE - (PORT datab (220:220:220) (288:288:288)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datab cout (385:385:385) (280:280:280)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[12\]) - (DELAY - (ABSOLUTE - (PORT clk (1354:1354:1354) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[13\]\~51) - (DELAY - (ABSOLUTE - (PORT dataa (221:221:221) (294:294:294)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH dataa cout (376:376:376) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[13\]) - (DELAY - (ABSOLUTE - (PORT clk (1681:1681:1681) (1700:1700:1700)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[14\]\~53) - (DELAY - (ABSOLUTE - (PORT datab (219:219:219) (288:288:288)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datab cout (385:385:385) (280:280:280)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[14\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[15\]\~55) - (DELAY - (ABSOLUTE - (PORT datab (220:220:220) (288:288:288)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datab cout (385:385:385) (280:280:280)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[15\]) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[16\]\~57) + (INSTANCE Add0\~6) (DELAY (ABSOLUTE (PORT datab (220:220:220) (289:289:289)) @@ -584,10 +246,10 @@ ) (CELL (CELLTYPE "dffeas") - (INSTANCE counter\[16\]) + (INSTANCE counter\[3\]) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) + (PORT clk (1352:1352:1352) (1368:1368:1368)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -598,10 +260,10 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[17\]\~59) + (INSTANCE Add0\~8) (DELAY (ABSOLUTE - (PORT dataa (222:222:222) (294:294:294)) + (PORT dataa (359:359:359) (404:404:404)) (IOPATH dataa combout (318:318:318) (323:323:323)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) @@ -610,12 +272,376 @@ ) ) ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE counter\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1352:1352:1352) (1368:1368:1368)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~10) + (DELAY + (ABSOLUTE + (PORT datab (348:348:348) (401:401:401)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE counter\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1352:1352:1352) (1368:1368:1368)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~12) + (DELAY + (ABSOLUTE + (PORT dataa (359:359:359) (403:403:403)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE counter\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1352:1352:1352) (1368:1368:1368)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~14) + (DELAY + (ABSOLUTE + (PORT datab (358:358:358) (400:400:400)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE counter\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1352:1352:1352) (1368:1368:1368)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~16) + (DELAY + (ABSOLUTE + (PORT datab (219:219:219) (287:287:287)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE counter\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1352:1352:1352) (1368:1368:1368)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~18) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (292:292:292)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE counter\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1352:1352:1352) (1368:1368:1368)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~20) + (DELAY + (ABSOLUTE + (PORT datab (218:218:218) (286:286:286)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE counter\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1352:1352:1352) (1368:1368:1368)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~22) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (398:398:398)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE counter\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1352:1352:1352) (1368:1368:1368)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~24) + (DELAY + (ABSOLUTE + (PORT datab (350:350:350) (399:399:399)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE counter\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1352:1352:1352) (1368:1368:1368)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~26) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (398:398:398)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE counter\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1352:1352:1352) (1368:1368:1368)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~28) + (DELAY + (ABSOLUTE + (PORT dataa (358:358:358) (407:407:407)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE counter\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1352:1352:1352) (1368:1368:1368)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~30) + (DELAY + (ABSOLUTE + (PORT datab (358:358:358) (399:399:399)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE counter\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1352:1352:1352) (1368:1368:1368)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~32) + (DELAY + (ABSOLUTE + (PORT datab (357:357:357) (404:404:404)) + (IOPATH datab combout (319:319:319) (324:324:324)) + (IOPATH datab cout (385:385:385) (280:280:280)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE counter\[16\]) + (DELAY + (ABSOLUTE + (PORT clk (1352:1352:1352) (1368:1368:1368)) + (PORT d (67:67:67) (78:78:78)) + (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (144:144:144)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~34) + (DELAY + (ABSOLUTE + (PORT dataa (359:359:359) (404:404:404)) + (IOPATH dataa combout (318:318:318) (327:327:327)) + (IOPATH dataa cout (376:376:376) (275:275:275)) + (IOPATH datad combout (119:119:119) (106:106:106)) + (IOPATH cin combout (408:408:408) (387:387:387)) + (IOPATH cin cout (50:50:50) (50:50:50)) + ) + ) + ) (CELL (CELLTYPE "dffeas") (INSTANCE counter\[17\]) (DELAY (ABSOLUTE - (PORT clk (1681:1681:1681) (1700:1700:1700)) + (PORT clk (1352:1352:1352) (1368:1368:1368)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -626,12 +652,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[18\]\~61) + (INSTANCE Add0\~36) (DELAY (ABSOLUTE - (PORT datab (222:222:222) (290:290:290)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datab cout (385:385:385) (280:280:280)) + (PORT dataa (359:359:359) (404:404:404)) + (IOPATH dataa combout (318:318:318) (323:323:323)) + (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) (IOPATH cin cout (50:50:50) (50:50:50)) @@ -643,7 +669,7 @@ (INSTANCE counter\[18\]) (DELAY (ABSOLUTE - (PORT clk (1681:1681:1681) (1700:1700:1700)) + (PORT clk (1352:1352:1352) (1368:1368:1368)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -654,11 +680,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[19\]\~63) + (INSTANCE Add0\~38) (DELAY (ABSOLUTE - (PORT dataa (223:223:223) (297:297:297)) - (IOPATH dataa combout (318:318:318) (323:323:323)) + (PORT dataa (361:361:361) (408:408:408)) + (IOPATH dataa combout (318:318:318) (327:327:327)) (IOPATH dataa cout (376:376:376) (275:275:275)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) @@ -671,7 +697,7 @@ (INSTANCE counter\[19\]) (DELAY (ABSOLUTE - (PORT clk (1681:1681:1681) (1700:1700:1700)) + (PORT clk (1352:1352:1352) (1368:1368:1368)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -682,128 +708,132 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[20\]\~65) + (INSTANCE Add0\~40) (DELAY (ABSOLUTE - (PORT dataa (223:223:223) (297:297:297)) - (IOPATH dataa combout (318:318:318) (327:327:327)) - (IOPATH dataa cout (376:376:376) (275:275:275)) + (PORT datad (199:199:199) (256:256:256)) (IOPATH datad combout (119:119:119) (106:106:106)) (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[20\]) - (DELAY - (ABSOLUTE - (PORT clk (1681:1681:1681) (1700:1700:1700)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[21\]\~67) + (INSTANCE Equal0\~5) (DELAY (ABSOLUTE - (PORT datab (241:241:241) (310:310:310)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datab cout (385:385:385) (280:280:280)) + (PORT dataa (192:192:192) (232:232:232)) + (PORT datab (189:189:189) (225:225:225)) + (PORT datac (164:164:164) (198:198:198)) + (PORT datad (166:166:166) (188:188:188)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[21\]) - (DELAY - (ABSOLUTE - (PORT clk (1681:1681:1681) (1700:1700:1700)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE LED\[0\]\~reg0feeder) + (INSTANCE Equal0\~1) (DELAY (ABSOLUTE - (PORT datac (385:385:385) (415:415:415)) - (IOPATH datac combout (220:220:220) (216:216:216)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE LED\[0\]\~reg0) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[22\]\~69) - (DELAY - (ABSOLUTE - (PORT datab (241:241:241) (310:310:310)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datab cout (385:385:385) (280:280:280)) + (PORT dataa (184:184:184) (221:221:221)) + (PORT datab (183:183:183) (215:215:215)) + (PORT datac (157:157:157) (188:188:188)) + (PORT datad (160:160:160) (181:181:181)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[22\]) - (DELAY - (ABSOLUTE - (PORT clk (1681:1681:1681) (1700:1700:1700)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE LED\[1\]\~reg0feeder) + (INSTANCE Equal0\~0) (DELAY (ABSOLUTE - (PORT datad (749:749:749) (752:752:752)) + (PORT dataa (319:319:319) (328:328:328)) + (PORT datab (319:319:319) (327:327:327)) + (PORT datac (296:296:296) (304:304:304)) + (PORT datad (297:297:297) (291:291:291)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (356:356:356)) + (PORT datab (587:587:587) (585:585:585)) + (PORT datac (312:312:312) (319:319:319)) + (PORT datad (522:522:522) (503:503:503)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (185:185:185) (223:223:223)) + (PORT datab (184:184:184) (218:218:218)) + (PORT datac (158:158:158) (189:189:189)) + (PORT datad (161:161:161) (182:182:182)) + (IOPATH dataa combout (309:309:309) (326:326:326)) + (IOPATH datab combout (309:309:309) (328:328:328)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (570:570:570) (572:572:572)) + (PORT datab (762:762:762) (749:749:749)) + (PORT datac (155:155:155) (185:185:185)) + (PORT datad (285:285:285) (290:290:290)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (216:216:216)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (556:556:556) (552:552:552)) + (PORT datab (351:351:351) (360:360:360)) + (PORT datad (171:171:171) (199:199:199)) + (IOPATH dataa combout (287:287:287) (280:280:280)) + (IOPATH datab combout (273:273:273) (275:275:275)) + (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE LED\[1\]\~reg0) + (INSTANCE address\[0\]) (DELAY (ABSOLUTE - (PORT clk (1359:1359:1359) (1375:1375:1375)) + (PORT clk (1680:1680:1680) (1698:1698:1698)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -814,48 +844,53 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[23\]\~71) + (INSTANCE Equal0\~6) (DELAY (ABSOLUTE - (PORT datab (241:241:241) (310:310:310)) - (IOPATH datab combout (319:319:319) (324:324:324)) - (IOPATH datab cout (385:385:385) (280:280:280)) + (PORT datac (164:164:164) (198:198:198)) + (PORT datad (168:168:168) (195:195:195)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[23\]) - (DELAY - (ABSOLUTE - (PORT clk (1681:1681:1681) (1700:1700:1700)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE LED\[2\]\~reg0feeder) + (INSTANCE Equal0\~7) (DELAY (ABSOLUTE - (PORT datad (721:721:721) (721:721:721)) + (PORT dataa (340:340:340) (346:346:346)) + (PORT datab (188:188:188) (224:224:224)) + (PORT datac (156:156:156) (186:186:186)) + (PORT datad (166:166:166) (188:188:188)) + (IOPATH dataa combout (299:299:299) (304:304:304)) + (IOPATH datab combout (300:300:300) (312:312:312)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (560:560:560) (594:594:594)) + (PORT datab (198:198:198) (236:236:236)) + (PORT datad (307:307:307) (316:316:316)) + (IOPATH dataa combout (287:287:287) (289:289:289)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE LED\[2\]\~reg0) + (INSTANCE address\[1\]) (DELAY (ABSOLUTE - (PORT clk (1359:1359:1359) (1375:1375:1375)) + (PORT clk (1680:1680:1680) (1698:1698:1698)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -866,48 +901,39 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[24\]\~73) + (INSTANCE address\[1\]\~2) (DELAY (ABSOLUTE - (PORT datab (241:241:241) (311:311:311)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datab cout (385:385:385) (280:280:280)) + (PORT dataa (562:562:562) (595:595:595)) + (PORT datab (354:354:354) (363:363:363)) + (PORT datac (531:531:531) (524:524:524)) + (PORT datad (174:174:174) (203:203:203)) + (IOPATH dataa combout (265:265:265) (269:269:269)) + (IOPATH datab combout (265:265:265) (275:275:275)) + (IOPATH datac combout (218:218:218) (215:215:215)) (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[24\]) - (DELAY - (ABSOLUTE - (PORT clk (1681:1681:1681) (1700:1700:1700)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE LED\[3\]\~reg0feeder) + (INSTANCE address\[2\]\~3) (DELAY (ABSOLUTE - (PORT datad (369:369:369) (405:405:405)) + (PORT datab (369:369:369) (413:413:413)) + (PORT datad (160:160:160) (182:182:182)) + (IOPATH datab combout (295:295:295) (294:294:294)) + (IOPATH datac combout (312:312:312) (325:325:325)) (IOPATH datad combout (119:119:119) (106:106:106)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE LED\[3\]\~reg0) + (INSTANCE address\[2\]) (DELAY (ABSOLUTE - (PORT clk (1354:1354:1354) (1370:1370:1370)) + (PORT clk (1680:1680:1680) (1698:1698:1698)) (PORT d (67:67:67) (78:78:78)) (IOPATH (posedge clk) q (180:180:180) (180:180:180)) ) @@ -917,156 +943,89 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[25\]\~75) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) (DELAY (ABSOLUTE - (PORT dataa (242:242:242) (314:314:314)) - (IOPATH dataa combout (318:318:318) (323:323:323)) - (IOPATH dataa cout (376:376:376) (275:275:275)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[25\]) - (DELAY - (ABSOLUTE - (PORT clk (1681:1681:1681) (1700:1700:1700)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (PORT d[0] (1170:1170:1170) (1206:1206:1206)) + (PORT d[1] (1424:1424:1424) (1458:1458:1458)) + (PORT d[2] (1417:1417:1417) (1451:1451:1451)) + (PORT clk (1643:1643:1643) (1671:1671:1671)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) + (HOLD d (posedge clk) (169:169:169)) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE LED\[4\]\~reg0feeder) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) (DELAY (ABSOLUTE - (PORT datad (376:376:376) (411:411:411)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT clk (1643:1643:1643) (1671:1671:1671)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE LED\[4\]\~reg0) + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (PORT clk (1644:1644:1644) (1672:1672:1672)) + (IOPATH (posedge clk) pulse (0:0:0) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1637:1637:1637)) + (IOPATH (posedge clk) q (268:268:268) (268:268:268)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) + (SETUP d (posedge clk) (42:42:42)) + (HOLD d (posedge clk) (142:142:142)) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[26\]\~77) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) (DELAY (ABSOLUTE - (PORT datab (240:240:240) (309:309:309)) - (IOPATH datab combout (325:325:325) (332:332:332)) - (IOPATH datab cout (385:385:385) (280:280:280)) - (IOPATH datad combout (119:119:119) (106:106:106)) - (IOPATH cin combout (408:408:408) (387:387:387)) - (IOPATH cin cout (50:50:50) (50:50:50)) + (PORT clk (881:881:881) (884:884:884)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[26\]) + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1681:1681:1681) (1700:1700:1700)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE LED\[5\]\~reg0feeder) - (DELAY - (ABSOLUTE - (PORT datad (568:568:568) (590:590:590)) - (IOPATH datad combout (119:119:119) (106:106:106)) + (PORT clk (882:882:882) (885:885:885)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE LED\[5\]\~reg0) + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[27\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (242:242:242) (315:315:315)) - (IOPATH dataa combout (329:329:329) (332:332:332)) - (IOPATH cin combout (408:408:408) (387:387:387)) + (PORT clk (882:882:882) (885:885:885)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[27\]) + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1681:1681:1681) (1700:1700:1700)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) + (PORT clk (882:882:882) (885:885:885)) + (IOPATH (posedge clk) pulse (0:0:0) (2386:2386:2386)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE LED\[6\]\~reg0feeder) - (DELAY - (ABSOLUTE - (PORT datad (378:378:378) (412:412:412)) - (IOPATH datad combout (119:119:119) (106:106:106)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE LED\[6\]\~reg0) - (DELAY - (ABSOLUTE - (PORT clk (1353:1353:1353) (1369:1369:1369)) - (PORT d (67:67:67) (78:78:78)) - (IOPATH (posedge clk) q (180:180:180) (180:180:180)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (144:144:144)) - ) ) ) diff --git a/simulation/modelsim/spectrum_6_1200mv_85c_slow.vo b/simulation/modelsim/spectrum_6_1200mv_85c_slow.vo index 2c40645..8896dc4 100644 --- a/simulation/modelsim/spectrum_6_1200mv_85c_slow.vo +++ b/simulation/modelsim/spectrum_6_1200mv_85c_slow.vo @@ -16,7 +16,7 @@ // PROGRAM "Quartus II 32-bit" // VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" -// DATE "03/30/2022 11:51:43" +// DATE "03/30/2022 12:38:42" // // Device: Altera EP4CE22F17C6 Package FBGA256 @@ -71,80 +71,77 @@ wire \LED[6]~output_o ; wire \LED[7]~output_o ; wire \CLOCK_50~input_o ; wire \CLOCK_50~inputclkctrl_outclk ; -wire \counter[0]~81_combout ; -wire \counter[1]~27_combout ; -wire \counter[1]~28 ; -wire \counter[2]~29_combout ; -wire \counter[2]~30 ; -wire \counter[3]~31_combout ; -wire \counter[3]~32 ; -wire \counter[4]~33_combout ; -wire \counter[4]~34 ; -wire \counter[5]~35_combout ; -wire \counter[5]~36 ; -wire \counter[6]~37_combout ; -wire \counter[6]~38 ; -wire \counter[7]~39_combout ; -wire \counter[7]~40 ; -wire \counter[8]~41_combout ; -wire \counter[8]~42 ; -wire \counter[9]~43_combout ; -wire \counter[9]~44 ; -wire \counter[10]~45_combout ; -wire \counter[10]~46 ; -wire \counter[11]~47_combout ; -wire \counter[11]~48 ; -wire \counter[12]~49_combout ; -wire \counter[12]~50 ; -wire \counter[13]~51_combout ; -wire \counter[13]~52 ; -wire \counter[14]~53_combout ; -wire \counter[14]~54 ; -wire \counter[15]~55_combout ; -wire \counter[15]~56 ; -wire \counter[16]~57_combout ; -wire \counter[16]~58 ; -wire \counter[17]~59_combout ; -wire \counter[17]~60 ; -wire \counter[18]~61_combout ; -wire \counter[18]~62 ; -wire \counter[19]~63_combout ; -wire \counter[19]~64 ; -wire \counter[20]~65_combout ; -wire \counter[20]~66 ; -wire \counter[21]~67_combout ; -wire \LED[0]~reg0feeder_combout ; -wire \LED[0]~reg0_q ; -wire \counter[21]~68 ; -wire \counter[22]~69_combout ; -wire \LED[1]~reg0feeder_combout ; -wire \LED[1]~reg0_q ; -wire \counter[22]~70 ; -wire \counter[23]~71_combout ; -wire \LED[2]~reg0feeder_combout ; -wire \LED[2]~reg0_q ; -wire \counter[23]~72 ; -wire \counter[24]~73_combout ; -wire \LED[3]~reg0feeder_combout ; -wire \LED[3]~reg0_q ; -wire \counter[24]~74 ; -wire \counter[25]~75_combout ; -wire \LED[4]~reg0feeder_combout ; -wire \LED[4]~reg0_q ; -wire \counter[25]~76 ; -wire \counter[26]~77_combout ; -wire \LED[5]~reg0feeder_combout ; -wire \LED[5]~reg0_q ; -wire \counter[26]~78 ; -wire \counter[27]~79_combout ; -wire \LED[6]~reg0feeder_combout ; -wire \LED[6]~reg0_q ; -wire [27:0] counter; +wire \Add0~0_combout ; +wire \Add0~1 ; +wire \Add0~2_combout ; +wire \Add0~3 ; +wire \Add0~4_combout ; +wire \Add0~5 ; +wire \Add0~6_combout ; +wire \Add0~7 ; +wire \Add0~8_combout ; +wire \Add0~9 ; +wire \Add0~10_combout ; +wire \Add0~11 ; +wire \Add0~12_combout ; +wire \Add0~13 ; +wire \Add0~14_combout ; +wire \Add0~15 ; +wire \Add0~16_combout ; +wire \Add0~17 ; +wire \Add0~18_combout ; +wire \Add0~19 ; +wire \Add0~20_combout ; +wire \Add0~21 ; +wire \Add0~22_combout ; +wire \Add0~23 ; +wire \Add0~24_combout ; +wire \Add0~25 ; +wire \Add0~26_combout ; +wire \Add0~27 ; +wire \Add0~28_combout ; +wire \Add0~29 ; +wire \Add0~30_combout ; +wire \Add0~31 ; +wire \Add0~32_combout ; +wire \Add0~33 ; +wire \Add0~34_combout ; +wire \Add0~35 ; +wire \Add0~36_combout ; +wire \Add0~37 ; +wire \Add0~38_combout ; +wire \Add0~39 ; +wire \Add0~40_combout ; +wire \Equal0~5_combout ; +wire \Equal0~1_combout ; +wire \Equal0~0_combout ; +wire \Equal0~2_combout ; +wire \Equal0~3_combout ; +wire \Equal0~4_combout ; +wire \address[0]~0_combout ; +wire \Equal0~6_combout ; +wire \Equal0~7_combout ; +wire \address[1]~1_combout ; +wire \address[1]~2_combout ; +wire \address[2]~3_combout ; +wire [20:0] counter; +wire [2:0] address; +wire [7:0] \rom|altsyncram_component|auto_generated|q_a ; +wire [17:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; + +assign \rom|altsyncram_component|auto_generated|q_a [0] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|q_a [1] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [1]; +assign \rom|altsyncram_component|auto_generated|q_a [2] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [2]; +assign \rom|altsyncram_component|auto_generated|q_a [3] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [3]; +assign \rom|altsyncram_component|auto_generated|q_a [4] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [4]; +assign \rom|altsyncram_component|auto_generated|q_a [5] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [5]; +assign \rom|altsyncram_component|auto_generated|q_a [6] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [6]; +assign \rom|altsyncram_component|auto_generated|q_a [7] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [7]; // Location: IOOBUF_X38_Y34_N16 cycloneive_io_obuf \LED[0]~output ( - .i(\LED[0]~reg0_q ), + .i(\rom|altsyncram_component|auto_generated|q_a [0]), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -157,7 +154,7 @@ defparam \LED[0]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y34_N2 cycloneive_io_obuf \LED[1]~output ( - .i(\LED[1]~reg0_q ), + .i(\rom|altsyncram_component|auto_generated|q_a [1]), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -170,7 +167,7 @@ defparam \LED[1]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y34_N9 cycloneive_io_obuf \LED[2]~output ( - .i(\LED[2]~reg0_q ), + .i(\rom|altsyncram_component|auto_generated|q_a [2]), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -183,7 +180,7 @@ defparam \LED[2]~output .open_drain_output = "false"; // Location: IOOBUF_X40_Y34_N2 cycloneive_io_obuf \LED[3]~output ( - .i(\LED[3]~reg0_q ), + .i(\rom|altsyncram_component|auto_generated|q_a [3]), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -196,7 +193,7 @@ defparam \LED[3]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y25_N9 cycloneive_io_obuf \LED[4]~output ( - .i(\LED[4]~reg0_q ), + .i(\rom|altsyncram_component|auto_generated|q_a [4]), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -209,7 +206,7 @@ defparam \LED[4]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y26_N16 cycloneive_io_obuf \LED[5]~output ( - .i(\LED[5]~reg0_q ), + .i(\rom|altsyncram_component|auto_generated|q_a [5]), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -222,7 +219,7 @@ defparam \LED[5]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y28_N9 cycloneive_io_obuf \LED[6]~output ( - .i(\LED[6]~reg0_q ), + .i(\rom|altsyncram_component|auto_generated|q_a [6]), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -235,7 +232,7 @@ defparam \LED[6]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y10_N23 cycloneive_io_obuf \LED[7]~output ( - .i(gnd), + .i(\rom|altsyncram_component|auto_generated|q_a [7]), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -269,767 +266,10 @@ defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N4 -cycloneive_lcell_comb \counter[0]~81 ( -// Equation(s): -// \counter[0]~81_combout = !counter[0] - - .dataa(gnd), - .datab(gnd), - .datac(counter[0]), - .datad(gnd), - .cin(gnd), - .combout(\counter[0]~81_combout ), - .cout()); -// synopsys translate_off -defparam \counter[0]~81 .lut_mask = 16'h0F0F; -defparam \counter[0]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y33_N5 -dffeas \counter[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[0]~81_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[0]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[0] .is_wysiwyg = "true"; -defparam \counter[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N6 -cycloneive_lcell_comb \counter[1]~27 ( -// Equation(s): -// \counter[1]~27_combout = (counter[1] & (counter[0] $ (VCC))) # (!counter[1] & (counter[0] & VCC)) -// \counter[1]~28 = CARRY((counter[1] & counter[0])) - - .dataa(counter[1]), - .datab(counter[0]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\counter[1]~27_combout ), - .cout(\counter[1]~28 )); -// synopsys translate_off -defparam \counter[1]~27 .lut_mask = 16'h6688; -defparam \counter[1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y33_N7 -dffeas \counter[1] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[1]~27_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[1]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[1] .is_wysiwyg = "true"; -defparam \counter[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N8 -cycloneive_lcell_comb \counter[2]~29 ( -// Equation(s): -// \counter[2]~29_combout = (counter[2] & (!\counter[1]~28 )) # (!counter[2] & ((\counter[1]~28 ) # (GND))) -// \counter[2]~30 = CARRY((!\counter[1]~28 ) # (!counter[2])) - - .dataa(gnd), - .datab(counter[2]), - .datac(gnd), - .datad(vcc), - .cin(\counter[1]~28 ), - .combout(\counter[2]~29_combout ), - .cout(\counter[2]~30 )); -// synopsys translate_off -defparam \counter[2]~29 .lut_mask = 16'h3C3F; -defparam \counter[2]~29 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N9 -dffeas \counter[2] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[2]~29_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[2]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[2] .is_wysiwyg = "true"; -defparam \counter[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N10 -cycloneive_lcell_comb \counter[3]~31 ( -// Equation(s): -// \counter[3]~31_combout = (counter[3] & (\counter[2]~30 $ (GND))) # (!counter[3] & (!\counter[2]~30 & VCC)) -// \counter[3]~32 = CARRY((counter[3] & !\counter[2]~30 )) - - .dataa(counter[3]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\counter[2]~30 ), - .combout(\counter[3]~31_combout ), - .cout(\counter[3]~32 )); -// synopsys translate_off -defparam \counter[3]~31 .lut_mask = 16'hA50A; -defparam \counter[3]~31 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N11 -dffeas \counter[3] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[3]~31_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[3]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[3] .is_wysiwyg = "true"; -defparam \counter[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N12 -cycloneive_lcell_comb \counter[4]~33 ( -// Equation(s): -// \counter[4]~33_combout = (counter[4] & (!\counter[3]~32 )) # (!counter[4] & ((\counter[3]~32 ) # (GND))) -// \counter[4]~34 = CARRY((!\counter[3]~32 ) # (!counter[4])) - - .dataa(counter[4]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\counter[3]~32 ), - .combout(\counter[4]~33_combout ), - .cout(\counter[4]~34 )); -// synopsys translate_off -defparam \counter[4]~33 .lut_mask = 16'h5A5F; -defparam \counter[4]~33 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N13 -dffeas \counter[4] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[4]~33_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[4]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[4] .is_wysiwyg = "true"; -defparam \counter[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N14 -cycloneive_lcell_comb \counter[5]~35 ( -// Equation(s): -// \counter[5]~35_combout = (counter[5] & (\counter[4]~34 $ (GND))) # (!counter[5] & (!\counter[4]~34 & VCC)) -// \counter[5]~36 = CARRY((counter[5] & !\counter[4]~34 )) - - .dataa(gnd), - .datab(counter[5]), - .datac(gnd), - .datad(vcc), - .cin(\counter[4]~34 ), - .combout(\counter[5]~35_combout ), - .cout(\counter[5]~36 )); -// synopsys translate_off -defparam \counter[5]~35 .lut_mask = 16'hC30C; -defparam \counter[5]~35 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N15 -dffeas \counter[5] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[5]~35_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[5]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[5] .is_wysiwyg = "true"; -defparam \counter[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N16 -cycloneive_lcell_comb \counter[6]~37 ( -// Equation(s): -// \counter[6]~37_combout = (counter[6] & (!\counter[5]~36 )) # (!counter[6] & ((\counter[5]~36 ) # (GND))) -// \counter[6]~38 = CARRY((!\counter[5]~36 ) # (!counter[6])) - - .dataa(gnd), - .datab(counter[6]), - .datac(gnd), - .datad(vcc), - .cin(\counter[5]~36 ), - .combout(\counter[6]~37_combout ), - .cout(\counter[6]~38 )); -// synopsys translate_off -defparam \counter[6]~37 .lut_mask = 16'h3C3F; -defparam \counter[6]~37 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N17 -dffeas \counter[6] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[6]~37_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[6]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[6] .is_wysiwyg = "true"; -defparam \counter[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N18 -cycloneive_lcell_comb \counter[7]~39 ( -// Equation(s): -// \counter[7]~39_combout = (counter[7] & (\counter[6]~38 $ (GND))) # (!counter[7] & (!\counter[6]~38 & VCC)) -// \counter[7]~40 = CARRY((counter[7] & !\counter[6]~38 )) - - .dataa(gnd), - .datab(counter[7]), - .datac(gnd), - .datad(vcc), - .cin(\counter[6]~38 ), - .combout(\counter[7]~39_combout ), - .cout(\counter[7]~40 )); -// synopsys translate_off -defparam \counter[7]~39 .lut_mask = 16'hC30C; -defparam \counter[7]~39 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N19 -dffeas \counter[7] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[7]~39_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[7]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[7] .is_wysiwyg = "true"; -defparam \counter[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N20 -cycloneive_lcell_comb \counter[8]~41 ( -// Equation(s): -// \counter[8]~41_combout = (counter[8] & (!\counter[7]~40 )) # (!counter[8] & ((\counter[7]~40 ) # (GND))) -// \counter[8]~42 = CARRY((!\counter[7]~40 ) # (!counter[8])) - - .dataa(gnd), - .datab(counter[8]), - .datac(gnd), - .datad(vcc), - .cin(\counter[7]~40 ), - .combout(\counter[8]~41_combout ), - .cout(\counter[8]~42 )); -// synopsys translate_off -defparam \counter[8]~41 .lut_mask = 16'h3C3F; -defparam \counter[8]~41 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N21 -dffeas \counter[8] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[8]~41_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[8]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[8] .is_wysiwyg = "true"; -defparam \counter[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N22 -cycloneive_lcell_comb \counter[9]~43 ( -// Equation(s): -// \counter[9]~43_combout = (counter[9] & (\counter[8]~42 $ (GND))) # (!counter[9] & (!\counter[8]~42 & VCC)) -// \counter[9]~44 = CARRY((counter[9] & !\counter[8]~42 )) - - .dataa(counter[9]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\counter[8]~42 ), - .combout(\counter[9]~43_combout ), - .cout(\counter[9]~44 )); -// synopsys translate_off -defparam \counter[9]~43 .lut_mask = 16'hA50A; -defparam \counter[9]~43 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N23 -dffeas \counter[9] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[9]~43_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[9]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[9] .is_wysiwyg = "true"; -defparam \counter[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N24 -cycloneive_lcell_comb \counter[10]~45 ( -// Equation(s): -// \counter[10]~45_combout = (counter[10] & (!\counter[9]~44 )) # (!counter[10] & ((\counter[9]~44 ) # (GND))) -// \counter[10]~46 = CARRY((!\counter[9]~44 ) # (!counter[10])) - - .dataa(gnd), - .datab(counter[10]), - .datac(gnd), - .datad(vcc), - .cin(\counter[9]~44 ), - .combout(\counter[10]~45_combout ), - .cout(\counter[10]~46 )); -// synopsys translate_off -defparam \counter[10]~45 .lut_mask = 16'h3C3F; -defparam \counter[10]~45 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N25 -dffeas \counter[10] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[10]~45_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[10]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[10] .is_wysiwyg = "true"; -defparam \counter[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N26 -cycloneive_lcell_comb \counter[11]~47 ( -// Equation(s): -// \counter[11]~47_combout = (counter[11] & (\counter[10]~46 $ (GND))) # (!counter[11] & (!\counter[10]~46 & VCC)) -// \counter[11]~48 = CARRY((counter[11] & !\counter[10]~46 )) - - .dataa(counter[11]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\counter[10]~46 ), - .combout(\counter[11]~47_combout ), - .cout(\counter[11]~48 )); -// synopsys translate_off -defparam \counter[11]~47 .lut_mask = 16'hA50A; -defparam \counter[11]~47 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N27 -dffeas \counter[11] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[11]~47_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[11]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[11] .is_wysiwyg = "true"; -defparam \counter[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N28 -cycloneive_lcell_comb \counter[12]~49 ( -// Equation(s): -// \counter[12]~49_combout = (counter[12] & (!\counter[11]~48 )) # (!counter[12] & ((\counter[11]~48 ) # (GND))) -// \counter[12]~50 = CARRY((!\counter[11]~48 ) # (!counter[12])) - - .dataa(gnd), - .datab(counter[12]), - .datac(gnd), - .datad(vcc), - .cin(\counter[11]~48 ), - .combout(\counter[12]~49_combout ), - .cout(\counter[12]~50 )); -// synopsys translate_off -defparam \counter[12]~49 .lut_mask = 16'h3C3F; -defparam \counter[12]~49 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N29 -dffeas \counter[12] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[12]~49_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[12]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[12] .is_wysiwyg = "true"; -defparam \counter[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N30 -cycloneive_lcell_comb \counter[13]~51 ( -// Equation(s): -// \counter[13]~51_combout = (counter[13] & (\counter[12]~50 $ (GND))) # (!counter[13] & (!\counter[12]~50 & VCC)) -// \counter[13]~52 = CARRY((counter[13] & !\counter[12]~50 )) - - .dataa(counter[13]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\counter[12]~50 ), - .combout(\counter[13]~51_combout ), - .cout(\counter[13]~52 )); -// synopsys translate_off -defparam \counter[13]~51 .lut_mask = 16'hA50A; -defparam \counter[13]~51 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N31 -dffeas \counter[13] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[13]~51_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[13]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[13] .is_wysiwyg = "true"; -defparam \counter[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y32_N0 -cycloneive_lcell_comb \counter[14]~53 ( -// Equation(s): -// \counter[14]~53_combout = (counter[14] & (!\counter[13]~52 )) # (!counter[14] & ((\counter[13]~52 ) # (GND))) -// \counter[14]~54 = CARRY((!\counter[13]~52 ) # (!counter[14])) - - .dataa(gnd), - .datab(counter[14]), - .datac(gnd), - .datad(vcc), - .cin(\counter[13]~52 ), - .combout(\counter[14]~53_combout ), - .cout(\counter[14]~54 )); -// synopsys translate_off -defparam \counter[14]~53 .lut_mask = 16'h3C3F; -defparam \counter[14]~53 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N1 -dffeas \counter[14] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[14]~53_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[14]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[14] .is_wysiwyg = "true"; -defparam \counter[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y32_N2 -cycloneive_lcell_comb \counter[15]~55 ( -// Equation(s): -// \counter[15]~55_combout = (counter[15] & (\counter[14]~54 $ (GND))) # (!counter[15] & (!\counter[14]~54 & VCC)) -// \counter[15]~56 = CARRY((counter[15] & !\counter[14]~54 )) - - .dataa(gnd), - .datab(counter[15]), - .datac(gnd), - .datad(vcc), - .cin(\counter[14]~54 ), - .combout(\counter[15]~55_combout ), - .cout(\counter[15]~56 )); -// synopsys translate_off -defparam \counter[15]~55 .lut_mask = 16'hC30C; -defparam \counter[15]~55 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N3 -dffeas \counter[15] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[15]~55_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[15]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[15] .is_wysiwyg = "true"; -defparam \counter[15] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y32_N4 -cycloneive_lcell_comb \counter[16]~57 ( -// Equation(s): -// \counter[16]~57_combout = (counter[16] & (!\counter[15]~56 )) # (!counter[16] & ((\counter[15]~56 ) # (GND))) -// \counter[16]~58 = CARRY((!\counter[15]~56 ) # (!counter[16])) - - .dataa(gnd), - .datab(counter[16]), - .datac(gnd), - .datad(vcc), - .cin(\counter[15]~56 ), - .combout(\counter[16]~57_combout ), - .cout(\counter[16]~58 )); -// synopsys translate_off -defparam \counter[16]~57 .lut_mask = 16'h3C3F; -defparam \counter[16]~57 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N5 -dffeas \counter[16] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[16]~57_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[16]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[16] .is_wysiwyg = "true"; -defparam \counter[16] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y32_N6 -cycloneive_lcell_comb \counter[17]~59 ( -// Equation(s): -// \counter[17]~59_combout = (counter[17] & (\counter[16]~58 $ (GND))) # (!counter[17] & (!\counter[16]~58 & VCC)) -// \counter[17]~60 = CARRY((counter[17] & !\counter[16]~58 )) - - .dataa(counter[17]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\counter[16]~58 ), - .combout(\counter[17]~59_combout ), - .cout(\counter[17]~60 )); -// synopsys translate_off -defparam \counter[17]~59 .lut_mask = 16'hA50A; -defparam \counter[17]~59 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N7 -dffeas \counter[17] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[17]~59_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[17]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[17] .is_wysiwyg = "true"; -defparam \counter[17] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y32_N8 -cycloneive_lcell_comb \counter[18]~61 ( -// Equation(s): -// \counter[18]~61_combout = (counter[18] & (!\counter[17]~60 )) # (!counter[18] & ((\counter[17]~60 ) # (GND))) -// \counter[18]~62 = CARRY((!\counter[17]~60 ) # (!counter[18])) - - .dataa(gnd), - .datab(counter[18]), - .datac(gnd), - .datad(vcc), - .cin(\counter[17]~60 ), - .combout(\counter[18]~61_combout ), - .cout(\counter[18]~62 )); -// synopsys translate_off -defparam \counter[18]~61 .lut_mask = 16'h3C3F; -defparam \counter[18]~61 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N9 -dffeas \counter[18] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[18]~61_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[18]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[18] .is_wysiwyg = "true"; -defparam \counter[18] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y32_N10 -cycloneive_lcell_comb \counter[19]~63 ( -// Equation(s): -// \counter[19]~63_combout = (counter[19] & (\counter[18]~62 $ (GND))) # (!counter[19] & (!\counter[18]~62 & VCC)) -// \counter[19]~64 = CARRY((counter[19] & !\counter[18]~62 )) - - .dataa(counter[19]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\counter[18]~62 ), - .combout(\counter[19]~63_combout ), - .cout(\counter[19]~64 )); -// synopsys translate_off -defparam \counter[19]~63 .lut_mask = 16'hA50A; -defparam \counter[19]~63 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N11 -dffeas \counter[19] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[19]~63_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[19]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[19] .is_wysiwyg = "true"; -defparam \counter[19] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y32_N12 -cycloneive_lcell_comb \counter[20]~65 ( -// Equation(s): -// \counter[20]~65_combout = (counter[20] & (!\counter[19]~64 )) # (!counter[20] & ((\counter[19]~64 ) # (GND))) -// \counter[20]~66 = CARRY((!\counter[19]~64 ) # (!counter[20])) - - .dataa(counter[20]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\counter[19]~64 ), - .combout(\counter[20]~65_combout ), - .cout(\counter[20]~66 )); -// synopsys translate_off -defparam \counter[20]~65 .lut_mask = 16'h5A5F; -defparam \counter[20]~65 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N13 +// Location: FF_X31_Y17_N21 dffeas \counter[20] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[20]~65_combout ), + .d(\Add0~40_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1045,356 +285,28 @@ defparam \counter[20] .is_wysiwyg = "true"; defparam \counter[20] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y32_N14 -cycloneive_lcell_comb \counter[21]~67 ( +// Location: LCCOMB_X31_Y18_N12 +cycloneive_lcell_comb \Add0~0 ( // Equation(s): -// \counter[21]~67_combout = (counter[21] & (\counter[20]~66 $ (GND))) # (!counter[21] & (!\counter[20]~66 & VCC)) -// \counter[21]~68 = CARRY((counter[21] & !\counter[20]~66 )) +// \Add0~0_combout = counter[0] $ (VCC) +// \Add0~1 = CARRY(counter[0]) - .dataa(gnd), - .datab(counter[21]), - .datac(gnd), - .datad(vcc), - .cin(\counter[20]~66 ), - .combout(\counter[21]~67_combout ), - .cout(\counter[21]~68 )); -// synopsys translate_off -defparam \counter[21]~67 .lut_mask = 16'hC30C; -defparam \counter[21]~67 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N15 -dffeas \counter[21] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[21]~67_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[21]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[21] .is_wysiwyg = "true"; -defparam \counter[21] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y32_N4 -cycloneive_lcell_comb \LED[0]~reg0feeder ( -// Equation(s): -// \LED[0]~reg0feeder_combout = counter[21] - - .dataa(gnd), - .datab(gnd), - .datac(counter[21]), - .datad(gnd), - .cin(gnd), - .combout(\LED[0]~reg0feeder_combout ), - .cout()); -// synopsys translate_off -defparam \LED[0]~reg0feeder .lut_mask = 16'hF0F0; -defparam \LED[0]~reg0feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y32_N5 -dffeas \LED[0]~reg0 ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\LED[0]~reg0feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\LED[0]~reg0_q ), - .prn(vcc)); -// synopsys translate_off -defparam \LED[0]~reg0 .is_wysiwyg = "true"; -defparam \LED[0]~reg0 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y32_N16 -cycloneive_lcell_comb \counter[22]~69 ( -// Equation(s): -// \counter[22]~69_combout = (counter[22] & (!\counter[21]~68 )) # (!counter[22] & ((\counter[21]~68 ) # (GND))) -// \counter[22]~70 = CARRY((!\counter[21]~68 ) # (!counter[22])) - - .dataa(gnd), - .datab(counter[22]), - .datac(gnd), - .datad(vcc), - .cin(\counter[21]~68 ), - .combout(\counter[22]~69_combout ), - .cout(\counter[22]~70 )); -// synopsys translate_off -defparam \counter[22]~69 .lut_mask = 16'h3C3F; -defparam \counter[22]~69 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N17 -dffeas \counter[22] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[22]~69_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[22]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[22] .is_wysiwyg = "true"; -defparam \counter[22] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y32_N12 -cycloneive_lcell_comb \LED[1]~reg0feeder ( -// Equation(s): -// \LED[1]~reg0feeder_combout = counter[22] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(counter[22]), - .cin(gnd), - .combout(\LED[1]~reg0feeder_combout ), - .cout()); -// synopsys translate_off -defparam \LED[1]~reg0feeder .lut_mask = 16'hFF00; -defparam \LED[1]~reg0feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X46_Y32_N13 -dffeas \LED[1]~reg0 ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\LED[1]~reg0feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\LED[1]~reg0_q ), - .prn(vcc)); -// synopsys translate_off -defparam \LED[1]~reg0 .is_wysiwyg = "true"; -defparam \LED[1]~reg0 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y32_N18 -cycloneive_lcell_comb \counter[23]~71 ( -// Equation(s): -// \counter[23]~71_combout = (counter[23] & (\counter[22]~70 $ (GND))) # (!counter[23] & (!\counter[22]~70 & VCC)) -// \counter[23]~72 = CARRY((counter[23] & !\counter[22]~70 )) - - .dataa(gnd), - .datab(counter[23]), - .datac(gnd), - .datad(vcc), - .cin(\counter[22]~70 ), - .combout(\counter[23]~71_combout ), - .cout(\counter[23]~72 )); -// synopsys translate_off -defparam \counter[23]~71 .lut_mask = 16'hC30C; -defparam \counter[23]~71 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N19 -dffeas \counter[23] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[23]~71_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[23]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[23] .is_wysiwyg = "true"; -defparam \counter[23] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y32_N6 -cycloneive_lcell_comb \LED[2]~reg0feeder ( -// Equation(s): -// \LED[2]~reg0feeder_combout = counter[23] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(counter[23]), - .cin(gnd), - .combout(\LED[2]~reg0feeder_combout ), - .cout()); -// synopsys translate_off -defparam \LED[2]~reg0feeder .lut_mask = 16'hFF00; -defparam \LED[2]~reg0feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X46_Y32_N7 -dffeas \LED[2]~reg0 ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\LED[2]~reg0feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\LED[2]~reg0_q ), - .prn(vcc)); -// synopsys translate_off -defparam \LED[2]~reg0 .is_wysiwyg = "true"; -defparam \LED[2]~reg0 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y32_N20 -cycloneive_lcell_comb \counter[24]~73 ( -// Equation(s): -// \counter[24]~73_combout = (counter[24] & (!\counter[23]~72 )) # (!counter[24] & ((\counter[23]~72 ) # (GND))) -// \counter[24]~74 = CARRY((!\counter[23]~72 ) # (!counter[24])) - - .dataa(gnd), - .datab(counter[24]), - .datac(gnd), - .datad(vcc), - .cin(\counter[23]~72 ), - .combout(\counter[24]~73_combout ), - .cout(\counter[24]~74 )); -// synopsys translate_off -defparam \counter[24]~73 .lut_mask = 16'h3C3F; -defparam \counter[24]~73 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N21 -dffeas \counter[24] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[24]~73_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[24]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[24] .is_wysiwyg = "true"; -defparam \counter[24] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y32_N4 -cycloneive_lcell_comb \LED[3]~reg0feeder ( -// Equation(s): -// \LED[3]~reg0feeder_combout = counter[24] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(counter[24]), - .cin(gnd), - .combout(\LED[3]~reg0feeder_combout ), - .cout()); -// synopsys translate_off -defparam \LED[3]~reg0feeder .lut_mask = 16'hFF00; -defparam \LED[3]~reg0feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y32_N5 -dffeas \LED[3]~reg0 ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\LED[3]~reg0feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\LED[3]~reg0_q ), - .prn(vcc)); -// synopsys translate_off -defparam \LED[3]~reg0 .is_wysiwyg = "true"; -defparam \LED[3]~reg0 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y32_N22 -cycloneive_lcell_comb \counter[25]~75 ( -// Equation(s): -// \counter[25]~75_combout = (counter[25] & (\counter[24]~74 $ (GND))) # (!counter[25] & (!\counter[24]~74 & VCC)) -// \counter[25]~76 = CARRY((counter[25] & !\counter[24]~74 )) - - .dataa(counter[25]), + .dataa(counter[0]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\counter[24]~74 ), - .combout(\counter[25]~75_combout ), - .cout(\counter[25]~76 )); -// synopsys translate_off -defparam \counter[25]~75 .lut_mask = 16'hA50A; -defparam \counter[25]~75 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N23 -dffeas \counter[25] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[25]~75_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[25]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[25] .is_wysiwyg = "true"; -defparam \counter[25] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y32_N18 -cycloneive_lcell_comb \LED[4]~reg0feeder ( -// Equation(s): -// \LED[4]~reg0feeder_combout = counter[25] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(counter[25]), .cin(gnd), - .combout(\LED[4]~reg0feeder_combout ), - .cout()); + .combout(\Add0~0_combout ), + .cout(\Add0~1 )); // synopsys translate_off -defparam \LED[4]~reg0feeder .lut_mask = 16'hFF00; -defparam \LED[4]~reg0feeder .sum_lutc_input = "datac"; +defparam \Add0~0 .lut_mask = 16'h55AA; +defparam \Add0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y32_N19 -dffeas \LED[4]~reg0 ( +// Location: FF_X31_Y18_N13 +dffeas \counter[0] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\LED[4]~reg0feeder_combout ), + .d(\Add0~0_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1403,35 +315,35 @@ dffeas \LED[4]~reg0 ( .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\LED[4]~reg0_q ), + .q(counter[0]), .prn(vcc)); // synopsys translate_off -defparam \LED[4]~reg0 .is_wysiwyg = "true"; -defparam \LED[4]~reg0 .power_up = "low"; +defparam \counter[0] .is_wysiwyg = "true"; +defparam \counter[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y32_N24 -cycloneive_lcell_comb \counter[26]~77 ( +// Location: LCCOMB_X31_Y18_N14 +cycloneive_lcell_comb \Add0~2 ( // Equation(s): -// \counter[26]~77_combout = (counter[26] & (!\counter[25]~76 )) # (!counter[26] & ((\counter[25]~76 ) # (GND))) -// \counter[26]~78 = CARRY((!\counter[25]~76 ) # (!counter[26])) +// \Add0~2_combout = (counter[1] & (!\Add0~1 )) # (!counter[1] & ((\Add0~1 ) # (GND))) +// \Add0~3 = CARRY((!\Add0~1 ) # (!counter[1])) .dataa(gnd), - .datab(counter[26]), + .datab(counter[1]), .datac(gnd), .datad(vcc), - .cin(\counter[25]~76 ), - .combout(\counter[26]~77_combout ), - .cout(\counter[26]~78 )); + .cin(\Add0~1 ), + .combout(\Add0~2_combout ), + .cout(\Add0~3 )); // synopsys translate_off -defparam \counter[26]~77 .lut_mask = 16'h3C3F; -defparam \counter[26]~77 .sum_lutc_input = "cin"; +defparam \Add0~2 .lut_mask = 16'h3C3F; +defparam \Add0~2 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X39_Y32_N25 -dffeas \counter[26] ( +// Location: FF_X31_Y18_N15 +dffeas \counter[1] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[26]~77_combout ), + .d(\Add0~2_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1440,34 +352,819 @@ dffeas \counter[26] ( .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(counter[26]), + .q(counter[1]), .prn(vcc)); // synopsys translate_off -defparam \counter[26] .is_wysiwyg = "true"; -defparam \counter[26] .power_up = "low"; +defparam \counter[1] .is_wysiwyg = "true"; +defparam \counter[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y32_N24 -cycloneive_lcell_comb \LED[5]~reg0feeder ( +// Location: LCCOMB_X31_Y18_N16 +cycloneive_lcell_comb \Add0~4 ( // Equation(s): -// \LED[5]~reg0feeder_combout = counter[26] +// \Add0~4_combout = (counter[2] & (\Add0~3 $ (GND))) # (!counter[2] & (!\Add0~3 & VCC)) +// \Add0~5 = CARRY((counter[2] & !\Add0~3 )) + + .dataa(gnd), + .datab(counter[2]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~3 ), + .combout(\Add0~4_combout ), + .cout(\Add0~5 )); +// synopsys translate_off +defparam \Add0~4 .lut_mask = 16'hC30C; +defparam \Add0~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y18_N17 +dffeas \counter[2] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[2]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[2] .is_wysiwyg = "true"; +defparam \counter[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N18 +cycloneive_lcell_comb \Add0~6 ( +// Equation(s): +// \Add0~6_combout = (counter[3] & (!\Add0~5 )) # (!counter[3] & ((\Add0~5 ) # (GND))) +// \Add0~7 = CARRY((!\Add0~5 ) # (!counter[3])) + + .dataa(gnd), + .datab(counter[3]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~5 ), + .combout(\Add0~6_combout ), + .cout(\Add0~7 )); +// synopsys translate_off +defparam \Add0~6 .lut_mask = 16'h3C3F; +defparam \Add0~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y18_N19 +dffeas \counter[3] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[3]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[3] .is_wysiwyg = "true"; +defparam \counter[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N20 +cycloneive_lcell_comb \Add0~8 ( +// Equation(s): +// \Add0~8_combout = (counter[4] & (\Add0~7 $ (GND))) # (!counter[4] & (!\Add0~7 & VCC)) +// \Add0~9 = CARRY((counter[4] & !\Add0~7 )) + + .dataa(counter[4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add0~7 ), + .combout(\Add0~8_combout ), + .cout(\Add0~9 )); +// synopsys translate_off +defparam \Add0~8 .lut_mask = 16'hA50A; +defparam \Add0~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y18_N21 +dffeas \counter[4] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[4]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[4] .is_wysiwyg = "true"; +defparam \counter[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N22 +cycloneive_lcell_comb \Add0~10 ( +// Equation(s): +// \Add0~10_combout = (counter[5] & (!\Add0~9 )) # (!counter[5] & ((\Add0~9 ) # (GND))) +// \Add0~11 = CARRY((!\Add0~9 ) # (!counter[5])) + + .dataa(gnd), + .datab(counter[5]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~9 ), + .combout(\Add0~10_combout ), + .cout(\Add0~11 )); +// synopsys translate_off +defparam \Add0~10 .lut_mask = 16'h3C3F; +defparam \Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y18_N23 +dffeas \counter[5] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~10_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[5]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[5] .is_wysiwyg = "true"; +defparam \counter[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N24 +cycloneive_lcell_comb \Add0~12 ( +// Equation(s): +// \Add0~12_combout = (counter[6] & (\Add0~11 $ (GND))) # (!counter[6] & (!\Add0~11 & VCC)) +// \Add0~13 = CARRY((counter[6] & !\Add0~11 )) + + .dataa(counter[6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add0~11 ), + .combout(\Add0~12_combout ), + .cout(\Add0~13 )); +// synopsys translate_off +defparam \Add0~12 .lut_mask = 16'hA50A; +defparam \Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y18_N25 +dffeas \counter[6] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[6]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[6] .is_wysiwyg = "true"; +defparam \counter[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N26 +cycloneive_lcell_comb \Add0~14 ( +// Equation(s): +// \Add0~14_combout = (counter[7] & (!\Add0~13 )) # (!counter[7] & ((\Add0~13 ) # (GND))) +// \Add0~15 = CARRY((!\Add0~13 ) # (!counter[7])) + + .dataa(gnd), + .datab(counter[7]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~13 ), + .combout(\Add0~14_combout ), + .cout(\Add0~15 )); +// synopsys translate_off +defparam \Add0~14 .lut_mask = 16'h3C3F; +defparam \Add0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y18_N27 +dffeas \counter[7] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~14_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[7]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[7] .is_wysiwyg = "true"; +defparam \counter[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N28 +cycloneive_lcell_comb \Add0~16 ( +// Equation(s): +// \Add0~16_combout = (counter[8] & (\Add0~15 $ (GND))) # (!counter[8] & (!\Add0~15 & VCC)) +// \Add0~17 = CARRY((counter[8] & !\Add0~15 )) + + .dataa(gnd), + .datab(counter[8]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~15 ), + .combout(\Add0~16_combout ), + .cout(\Add0~17 )); +// synopsys translate_off +defparam \Add0~16 .lut_mask = 16'hC30C; +defparam \Add0~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y18_N29 +dffeas \counter[8] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~16_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[8]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[8] .is_wysiwyg = "true"; +defparam \counter[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N30 +cycloneive_lcell_comb \Add0~18 ( +// Equation(s): +// \Add0~18_combout = (counter[9] & (!\Add0~17 )) # (!counter[9] & ((\Add0~17 ) # (GND))) +// \Add0~19 = CARRY((!\Add0~17 ) # (!counter[9])) + + .dataa(counter[9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add0~17 ), + .combout(\Add0~18_combout ), + .cout(\Add0~19 )); +// synopsys translate_off +defparam \Add0~18 .lut_mask = 16'h5A5F; +defparam \Add0~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y18_N31 +dffeas \counter[9] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~18_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[9]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[9] .is_wysiwyg = "true"; +defparam \counter[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N0 +cycloneive_lcell_comb \Add0~20 ( +// Equation(s): +// \Add0~20_combout = (counter[10] & (\Add0~19 $ (GND))) # (!counter[10] & (!\Add0~19 & VCC)) +// \Add0~21 = CARRY((counter[10] & !\Add0~19 )) + + .dataa(gnd), + .datab(counter[10]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~19 ), + .combout(\Add0~20_combout ), + .cout(\Add0~21 )); +// synopsys translate_off +defparam \Add0~20 .lut_mask = 16'hC30C; +defparam \Add0~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y17_N1 +dffeas \counter[10] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~20_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[10]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[10] .is_wysiwyg = "true"; +defparam \counter[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N2 +cycloneive_lcell_comb \Add0~22 ( +// Equation(s): +// \Add0~22_combout = (counter[11] & (!\Add0~21 )) # (!counter[11] & ((\Add0~21 ) # (GND))) +// \Add0~23 = CARRY((!\Add0~21 ) # (!counter[11])) + + .dataa(gnd), + .datab(counter[11]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~21 ), + .combout(\Add0~22_combout ), + .cout(\Add0~23 )); +// synopsys translate_off +defparam \Add0~22 .lut_mask = 16'h3C3F; +defparam \Add0~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y17_N3 +dffeas \counter[11] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~22_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[11]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[11] .is_wysiwyg = "true"; +defparam \counter[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N4 +cycloneive_lcell_comb \Add0~24 ( +// Equation(s): +// \Add0~24_combout = (counter[12] & (\Add0~23 $ (GND))) # (!counter[12] & (!\Add0~23 & VCC)) +// \Add0~25 = CARRY((counter[12] & !\Add0~23 )) + + .dataa(gnd), + .datab(counter[12]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~23 ), + .combout(\Add0~24_combout ), + .cout(\Add0~25 )); +// synopsys translate_off +defparam \Add0~24 .lut_mask = 16'hC30C; +defparam \Add0~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y17_N5 +dffeas \counter[12] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~24_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[12]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[12] .is_wysiwyg = "true"; +defparam \counter[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N6 +cycloneive_lcell_comb \Add0~26 ( +// Equation(s): +// \Add0~26_combout = (counter[13] & (!\Add0~25 )) # (!counter[13] & ((\Add0~25 ) # (GND))) +// \Add0~27 = CARRY((!\Add0~25 ) # (!counter[13])) + + .dataa(gnd), + .datab(counter[13]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~25 ), + .combout(\Add0~26_combout ), + .cout(\Add0~27 )); +// synopsys translate_off +defparam \Add0~26 .lut_mask = 16'h3C3F; +defparam \Add0~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y17_N7 +dffeas \counter[13] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~26_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[13]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[13] .is_wysiwyg = "true"; +defparam \counter[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N8 +cycloneive_lcell_comb \Add0~28 ( +// Equation(s): +// \Add0~28_combout = (counter[14] & (\Add0~27 $ (GND))) # (!counter[14] & (!\Add0~27 & VCC)) +// \Add0~29 = CARRY((counter[14] & !\Add0~27 )) + + .dataa(counter[14]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add0~27 ), + .combout(\Add0~28_combout ), + .cout(\Add0~29 )); +// synopsys translate_off +defparam \Add0~28 .lut_mask = 16'hA50A; +defparam \Add0~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y17_N9 +dffeas \counter[14] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~28_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[14]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[14] .is_wysiwyg = "true"; +defparam \counter[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N10 +cycloneive_lcell_comb \Add0~30 ( +// Equation(s): +// \Add0~30_combout = (counter[15] & (!\Add0~29 )) # (!counter[15] & ((\Add0~29 ) # (GND))) +// \Add0~31 = CARRY((!\Add0~29 ) # (!counter[15])) + + .dataa(gnd), + .datab(counter[15]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~29 ), + .combout(\Add0~30_combout ), + .cout(\Add0~31 )); +// synopsys translate_off +defparam \Add0~30 .lut_mask = 16'h3C3F; +defparam \Add0~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y17_N11 +dffeas \counter[15] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~30_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[15]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[15] .is_wysiwyg = "true"; +defparam \counter[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N12 +cycloneive_lcell_comb \Add0~32 ( +// Equation(s): +// \Add0~32_combout = (counter[16] & (\Add0~31 $ (GND))) # (!counter[16] & (!\Add0~31 & VCC)) +// \Add0~33 = CARRY((counter[16] & !\Add0~31 )) + + .dataa(gnd), + .datab(counter[16]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~31 ), + .combout(\Add0~32_combout ), + .cout(\Add0~33 )); +// synopsys translate_off +defparam \Add0~32 .lut_mask = 16'hC30C; +defparam \Add0~32 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y17_N13 +dffeas \counter[16] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~32_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[16]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[16] .is_wysiwyg = "true"; +defparam \counter[16] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N14 +cycloneive_lcell_comb \Add0~34 ( +// Equation(s): +// \Add0~34_combout = (counter[17] & (!\Add0~33 )) # (!counter[17] & ((\Add0~33 ) # (GND))) +// \Add0~35 = CARRY((!\Add0~33 ) # (!counter[17])) + + .dataa(counter[17]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add0~33 ), + .combout(\Add0~34_combout ), + .cout(\Add0~35 )); +// synopsys translate_off +defparam \Add0~34 .lut_mask = 16'h5A5F; +defparam \Add0~34 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y17_N15 +dffeas \counter[17] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~34_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[17]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[17] .is_wysiwyg = "true"; +defparam \counter[17] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N16 +cycloneive_lcell_comb \Add0~36 ( +// Equation(s): +// \Add0~36_combout = (counter[18] & (\Add0~35 $ (GND))) # (!counter[18] & (!\Add0~35 & VCC)) +// \Add0~37 = CARRY((counter[18] & !\Add0~35 )) + + .dataa(counter[18]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add0~35 ), + .combout(\Add0~36_combout ), + .cout(\Add0~37 )); +// synopsys translate_off +defparam \Add0~36 .lut_mask = 16'hA50A; +defparam \Add0~36 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y17_N17 +dffeas \counter[18] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~36_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[18]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[18] .is_wysiwyg = "true"; +defparam \counter[18] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N18 +cycloneive_lcell_comb \Add0~38 ( +// Equation(s): +// \Add0~38_combout = (counter[19] & (!\Add0~37 )) # (!counter[19] & ((\Add0~37 ) # (GND))) +// \Add0~39 = CARRY((!\Add0~37 ) # (!counter[19])) + + .dataa(counter[19]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add0~37 ), + .combout(\Add0~38_combout ), + .cout(\Add0~39 )); +// synopsys translate_off +defparam \Add0~38 .lut_mask = 16'h5A5F; +defparam \Add0~38 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y17_N19 +dffeas \counter[19] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~38_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[19]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[19] .is_wysiwyg = "true"; +defparam \counter[19] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N20 +cycloneive_lcell_comb \Add0~40 ( +// Equation(s): +// \Add0~40_combout = \Add0~39 $ (!counter[20]) .dataa(gnd), .datab(gnd), .datac(gnd), - .datad(counter[26]), + .datad(counter[20]), + .cin(\Add0~39 ), + .combout(\Add0~40_combout ), + .cout()); +// synopsys translate_off +defparam \Add0~40 .lut_mask = 16'hF00F; +defparam \Add0~40 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N28 +cycloneive_lcell_comb \Equal0~5 ( +// Equation(s): +// \Equal0~5_combout = (!\Add0~32_combout & (!\Add0~36_combout & (!\Add0~34_combout & !\Add0~38_combout ))) + + .dataa(\Add0~32_combout ), + .datab(\Add0~36_combout ), + .datac(\Add0~34_combout ), + .datad(\Add0~38_combout ), .cin(gnd), - .combout(\LED[5]~reg0feeder_combout ), + .combout(\Equal0~5_combout ), .cout()); // synopsys translate_off -defparam \LED[5]~reg0feeder .lut_mask = 16'hFF00; -defparam \LED[5]~reg0feeder .sum_lutc_input = "datac"; +defparam \Equal0~5 .lut_mask = 16'h0001; +defparam \Equal0~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y32_N25 -dffeas \LED[5]~reg0 ( +// Location: LCCOMB_X31_Y18_N6 +cycloneive_lcell_comb \Equal0~1 ( +// Equation(s): +// \Equal0~1_combout = (!\Add0~10_combout & (!\Add0~8_combout & (!\Add0~14_combout & !\Add0~12_combout ))) + + .dataa(\Add0~10_combout ), + .datab(\Add0~8_combout ), + .datac(\Add0~14_combout ), + .datad(\Add0~12_combout ), + .cin(gnd), + .combout(\Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~1 .lut_mask = 16'h0001; +defparam \Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N4 +cycloneive_lcell_comb \Equal0~0 ( +// Equation(s): +// \Equal0~0_combout = (!\Add0~4_combout & (!\Add0~0_combout & (!\Add0~6_combout & !\Add0~2_combout ))) + + .dataa(\Add0~4_combout ), + .datab(\Add0~0_combout ), + .datac(\Add0~6_combout ), + .datad(\Add0~2_combout ), + .cin(gnd), + .combout(\Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~0 .lut_mask = 16'h0001; +defparam \Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N30 +cycloneive_lcell_comb \Equal0~2 ( +// Equation(s): +// \Equal0~2_combout = (!\Add0~22_combout & (!\Add0~16_combout & (!\Add0~20_combout & !\Add0~18_combout ))) + + .dataa(\Add0~22_combout ), + .datab(\Add0~16_combout ), + .datac(\Add0~20_combout ), + .datad(\Add0~18_combout ), + .cin(gnd), + .combout(\Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~2 .lut_mask = 16'h0001; +defparam \Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N30 +cycloneive_lcell_comb \Equal0~3 ( +// Equation(s): +// \Equal0~3_combout = (!\Add0~26_combout & (!\Add0~24_combout & (!\Add0~28_combout & !\Add0~30_combout ))) + + .dataa(\Add0~26_combout ), + .datab(\Add0~24_combout ), + .datac(\Add0~28_combout ), + .datad(\Add0~30_combout ), + .cin(gnd), + .combout(\Equal0~3_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~3 .lut_mask = 16'h0001; +defparam \Equal0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N28 +cycloneive_lcell_comb \Equal0~4 ( +// Equation(s): +// \Equal0~4_combout = (\Equal0~1_combout & (\Equal0~0_combout & (\Equal0~2_combout & \Equal0~3_combout ))) + + .dataa(\Equal0~1_combout ), + .datab(\Equal0~0_combout ), + .datac(\Equal0~2_combout ), + .datad(\Equal0~3_combout ), + .cin(gnd), + .combout(\Equal0~4_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~4 .lut_mask = 16'h8000; +defparam \Equal0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N20 +cycloneive_lcell_comb \address[0]~0 ( +// Equation(s): +// \address[0]~0_combout = address[0] $ (((!\Add0~40_combout & (\Equal0~5_combout & \Equal0~4_combout )))) + + .dataa(\Add0~40_combout ), + .datab(\Equal0~5_combout ), + .datac(address[0]), + .datad(\Equal0~4_combout ), + .cin(gnd), + .combout(\address[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \address[0]~0 .lut_mask = 16'hB4F0; +defparam \address[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N21 +dffeas \address[0] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\LED[5]~reg0feeder_combout ), + .d(\address[0]~0_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1476,70 +1173,68 @@ dffeas \LED[5]~reg0 ( .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\LED[5]~reg0_q ), + .q(address[0]), .prn(vcc)); // synopsys translate_off -defparam \LED[5]~reg0 .is_wysiwyg = "true"; -defparam \LED[5]~reg0 .power_up = "low"; +defparam \address[0] .is_wysiwyg = "true"; +defparam \address[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y32_N26 -cycloneive_lcell_comb \counter[27]~79 ( +// Location: LCCOMB_X31_Y17_N26 +cycloneive_lcell_comb \Equal0~6 ( // Equation(s): -// \counter[27]~79_combout = counter[27] $ (!\counter[26]~78 ) - - .dataa(counter[27]), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(\counter[26]~78 ), - .combout(\counter[27]~79_combout ), - .cout()); -// synopsys translate_off -defparam \counter[27]~79 .lut_mask = 16'hA5A5; -defparam \counter[27]~79 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N27 -dffeas \counter[27] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[27]~79_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[27]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[27] .is_wysiwyg = "true"; -defparam \counter[27] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y32_N14 -cycloneive_lcell_comb \LED[6]~reg0feeder ( -// Equation(s): -// \LED[6]~reg0feeder_combout = counter[27] +// \Equal0~6_combout = (!\Add0~34_combout & !\Add0~32_combout ) .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(counter[27]), + .datac(\Add0~34_combout ), + .datad(\Add0~32_combout ), .cin(gnd), - .combout(\LED[6]~reg0feeder_combout ), + .combout(\Equal0~6_combout ), .cout()); // synopsys translate_off -defparam \LED[6]~reg0feeder .lut_mask = 16'hFF00; -defparam \LED[6]~reg0feeder .sum_lutc_input = "datac"; +defparam \Equal0~6 .lut_mask = 16'h000F; +defparam \Equal0~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y32_N15 -dffeas \LED[6]~reg0 ( +// Location: LCCOMB_X31_Y17_N24 +cycloneive_lcell_comb \Equal0~7 ( +// Equation(s): +// \Equal0~7_combout = (!\Add0~40_combout & (!\Add0~36_combout & (\Equal0~6_combout & !\Add0~38_combout ))) + + .dataa(\Add0~40_combout ), + .datab(\Add0~36_combout ), + .datac(\Equal0~6_combout ), + .datad(\Add0~38_combout ), + .cin(gnd), + .combout(\Equal0~7_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~7 .lut_mask = 16'h0010; +defparam \Equal0~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N10 +cycloneive_lcell_comb \address[1]~1 ( +// Equation(s): +// \address[1]~1_combout = address[1] $ (((address[0] & (\Equal0~4_combout & \Equal0~7_combout )))) + + .dataa(address[0]), + .datab(\Equal0~4_combout ), + .datac(address[1]), + .datad(\Equal0~7_combout ), + .cin(gnd), + .combout(\address[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \address[1]~1 .lut_mask = 16'h78F0; +defparam \address[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N11 +dffeas \address[1] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\LED[6]~reg0feeder_combout ), + .d(\address[1]~1_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1548,11 +1243,116 @@ dffeas \LED[6]~reg0 ( .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\LED[6]~reg0_q ), + .q(address[1]), .prn(vcc)); // synopsys translate_off -defparam \LED[6]~reg0 .is_wysiwyg = "true"; -defparam \LED[6]~reg0 .power_up = "low"; +defparam \address[1] .is_wysiwyg = "true"; +defparam \address[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N2 +cycloneive_lcell_comb \address[1]~2 ( +// Equation(s): +// \address[1]~2_combout = (address[0] & (\Equal0~5_combout & (!\Add0~40_combout & \Equal0~4_combout ))) + + .dataa(address[0]), + .datab(\Equal0~5_combout ), + .datac(\Add0~40_combout ), + .datad(\Equal0~4_combout ), + .cin(gnd), + .combout(\address[1]~2_combout ), + .cout()); +// synopsys translate_off +defparam \address[1]~2 .lut_mask = 16'h0800; +defparam \address[1]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N16 +cycloneive_lcell_comb \address[2]~3 ( +// Equation(s): +// \address[2]~3_combout = address[2] $ (((address[1] & \address[1]~2_combout ))) + + .dataa(gnd), + .datab(address[1]), + .datac(address[2]), + .datad(\address[1]~2_combout ), + .cin(gnd), + .combout(\address[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \address[2]~3 .lut_mask = 16'h3CF0; +defparam \address[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N17 +dffeas \address[2] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[2]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(address[2]), + .prn(vcc)); +// synopsys translate_off +defparam \address[2] .is_wysiwyg = "true"; +defparam \address[2] .power_up = "low"; +// synopsys translate_on + +// Location: M9K_X33_Y26_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(vcc), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(18'b000000000000000000), + .portaaddr({address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(18'b000000000000000000), + .portbaddr(3'b000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 18; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 18; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 144'h002040042000900018000600024001080081; // synopsys translate_on assign LED[0] = \LED[0]~output_o ; diff --git a/simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo b/simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo index e97f726..7414a00 100644 --- a/simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo +++ b/simulation/modelsim/spectrum_6_1200mv_85c_v_slow.sdo @@ -29,7 +29,7 @@ (DELAYFILE (SDFVERSION "2.1") (DESIGN "spectrum") - (DATE "03/30/2022 11:51:43") + (DATE "03/30/2022 12:38:42") (VENDOR "Altera") (PROGRAM "Quartus II 32-bit") (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") @@ -41,7 +41,7 @@ (INSTANCE LED\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (513:513:513) (544:544:544)) + (PORT i (1355:1355:1355) (1339:1339:1339)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -51,7 +51,7 @@ (INSTANCE LED\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (754:754:754) (771:771:771)) + (PORT i (1409:1409:1409) (1443:1443:1443)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -61,7 +61,7 @@ (INSTANCE LED\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (734:734:734) (751:751:751)) + (PORT i (1823:1823:1823) (1829:1829:1829)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -71,7 +71,7 @@ (INSTANCE LED\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (512:512:512) (543:543:543)) + (PORT i (1455:1455:1455) (1423:1423:1423)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -81,7 +81,7 @@ (INSTANCE LED\[4\]\~output) (DELAY (ABSOLUTE - (PORT i (2451:2451:2451) (2550:2550:2550)) + (PORT i (1759:1759:1759) (1776:1776:1776)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) ) ) @@ -91,7 +91,7 @@ (INSTANCE LED\[5\]\~output) (DELAY (ABSOLUTE - (PORT i (2441:2441:2441) (2543:2543:2543)) + (PORT i (1337:1337:1337) (1367:1367:1367)) (IOPATH i o (4477:4477:4477) (4127:4127:4127)) ) ) @@ -101,11 +101,21 @@ (INSTANCE LED\[6\]\~output) (DELAY (ABSOLUTE - (PORT i (1301:1301:1301) (1440:1440:1440)) + (PORT i (1855:1855:1855) (1871:1871:1871)) (IOPATH i o (2455:2455:2455) (2378:2378:2378)) ) ) ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE LED\[7\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1469:1469:1469) (1548:1548:1548)) + (IOPATH i o (4477:4477:4477) (4127:4127:4127)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_io_ibuf") (INSTANCE CLOCK_50\~input) @@ -125,11 +135,28 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[0\]\~81) + (CELLTYPE "dffeas") + (INSTANCE counter\[20\]) (DELAY (ABSOLUTE - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (330:330:330)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -138,7 +165,7 @@ (INSTANCE counter\[0\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -149,16 +176,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[1\]\~27) + (INSTANCE Add0\~2) (DELAY (ABSOLUTE - (PORT dataa (243:243:243) (329:329:329)) - (PORT datab (241:241:241) (323:323:323)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT datab (242:242:242) (324:324:324)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) ) ) ) @@ -167,7 +193,7 @@ (INSTANCE counter\[1\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -178,11 +204,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[2\]\~29) + (INSTANCE Add0\~4) (DELAY (ABSOLUTE - (PORT datab (242:242:242) (323:323:323)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT datab (242:242:242) (324:324:324)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) @@ -195,7 +221,7 @@ (INSTANCE counter\[2\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -206,12 +232,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[3\]\~31) + (INSTANCE Add0\~6) (DELAY (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (242:242:242) (324:324:324)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -223,7 +249,7 @@ (INSTANCE counter\[3\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -234,11 +260,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[4\]\~33) + (INSTANCE Add0\~8) (DELAY (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT dataa (386:386:386) (458:458:458)) + (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) @@ -251,7 +277,7 @@ (INSTANCE counter\[4\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -262,11 +288,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[5\]\~35) + (INSTANCE Add0\~10) (DELAY (ABSOLUTE - (PORT datab (242:242:242) (325:325:325)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT datab (380:380:380) (452:452:452)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) @@ -279,7 +305,7 @@ (INSTANCE counter\[5\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -290,12 +316,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[6\]\~37) + (INSTANCE Add0\~12) (DELAY (ABSOLUTE - (PORT datab (242:242:242) (325:325:325)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (386:386:386) (458:458:458)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -307,7 +333,7 @@ (INSTANCE counter\[6\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -318,11 +344,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[7\]\~39) + (INSTANCE Add0\~14) (DELAY (ABSOLUTE - (PORT datab (242:242:242) (325:325:325)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT datab (380:380:380) (450:450:450)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) @@ -335,7 +361,7 @@ (INSTANCE counter\[7\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -346,11 +372,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[8\]\~41) + (INSTANCE Add0\~16) (DELAY (ABSOLUTE - (PORT datab (242:242:242) (325:325:325)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT datab (240:240:240) (322:322:322)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) @@ -363,7 +389,7 @@ (INSTANCE counter\[8\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -374,11 +400,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[9\]\~43) + (INSTANCE Add0\~18) (DELAY (ABSOLUTE - (PORT dataa (244:244:244) (330:330:330)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (PORT dataa (242:242:242) (328:328:328)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) @@ -391,7 +417,7 @@ (INSTANCE counter\[9\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -402,11 +428,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[10\]\~45) + (INSTANCE Add0\~20) (DELAY (ABSOLUTE - (PORT datab (242:242:242) (323:323:323)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT datab (239:239:239) (321:321:321)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) @@ -419,7 +445,7 @@ (INSTANCE counter\[10\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -430,12 +456,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[11\]\~47) + (INSTANCE Add0\~22) (DELAY (ABSOLUTE - (PORT dataa (243:243:243) (329:329:329)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (388:388:388) (452:452:452)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -447,7 +473,7 @@ (INSTANCE counter\[11\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -458,11 +484,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[12\]\~49) + (INSTANCE Add0\~24) (DELAY (ABSOLUTE - (PORT datab (241:241:241) (323:323:323)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT datab (382:382:382) (451:451:451)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) @@ -475,7 +501,7 @@ (INSTANCE counter\[12\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -486,12 +512,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[13\]\~51) + (INSTANCE Add0\~26) (DELAY (ABSOLUTE - (PORT dataa (243:243:243) (329:329:329)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (387:387:387) (451:451:451)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -503,7 +529,7 @@ (INSTANCE counter\[13\]) (DELAY (ABSOLUTE - (PORT clk (1898:1898:1898) (1920:1920:1920)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -514,12 +540,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[14\]\~53) + (INSTANCE Add0\~28) (DELAY (ABSOLUTE - (PORT datab (240:240:240) (322:322:322)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (380:380:380) (458:458:458)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -531,7 +557,7 @@ (INSTANCE counter\[14\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -542,11 +568,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[15\]\~55) + (INSTANCE Add0\~30) (DELAY (ABSOLUTE - (PORT datab (241:241:241) (323:323:323)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT datab (387:387:387) (452:452:452)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) @@ -559,7 +585,7 @@ (INSTANCE counter\[15\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -570,11 +596,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[16\]\~57) + (INSTANCE Add0\~32) (DELAY (ABSOLUTE - (PORT datab (241:241:241) (323:323:323)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT datab (379:379:379) (454:454:454)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) @@ -587,7 +613,7 @@ (INSTANCE counter\[16\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -598,11 +624,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[17\]\~59) + (INSTANCE Add0\~34) (DELAY (ABSOLUTE - (PORT dataa (244:244:244) (330:330:330)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (PORT dataa (388:388:388) (458:458:458)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) @@ -615,7 +641,7 @@ (INSTANCE counter\[17\]) (DELAY (ABSOLUTE - (PORT clk (1898:1898:1898) (1920:1920:1920)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -626,12 +652,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[18\]\~61) + (INSTANCE Add0\~36) (DELAY (ABSOLUTE - (PORT datab (243:243:243) (324:324:324)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (386:386:386) (458:458:458)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -643,7 +669,7 @@ (INSTANCE counter\[18\]) (DELAY (ABSOLUTE - (PORT clk (1898:1898:1898) (1920:1920:1920)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -654,11 +680,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[19\]\~63) + (INSTANCE Add0\~38) (DELAY (ABSOLUTE - (PORT dataa (245:245:245) (333:333:333)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (PORT dataa (383:383:383) (460:460:460)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) @@ -671,7 +697,7 @@ (INSTANCE counter\[19\]) (DELAY (ABSOLUTE - (PORT clk (1898:1898:1898) (1920:1920:1920)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -682,128 +708,132 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[20\]\~65) + (INSTANCE Add0\~40) (DELAY (ABSOLUTE - (PORT dataa (245:245:245) (332:332:332)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datad (218:218:218) (287:287:287)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[20\]) - (DELAY - (ABSOLUTE - (PORT clk (1898:1898:1898) (1920:1920:1920)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[21\]\~67) + (INSTANCE Equal0\~5) (DELAY (ABSOLUTE - (PORT datab (264:264:264) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (210:210:210) (257:257:257)) + (PORT datab (208:208:208) (249:249:249)) + (PORT datac (181:181:181) (219:219:219)) + (PORT datad (181:181:181) (209:209:209)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[21\]) - (DELAY - (ABSOLUTE - (PORT clk (1898:1898:1898) (1920:1920:1920)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE LED\[0\]\~reg0feeder) + (INSTANCE Equal0\~1) (DELAY (ABSOLUTE - (PORT datac (411:411:411) (472:472:472)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE LED\[0\]\~reg0) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[22\]\~69) - (DELAY - (ABSOLUTE - (PORT datab (264:264:264) (347:347:347)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[22\]) - (DELAY - (ABSOLUTE - (PORT clk (1898:1898:1898) (1920:1920:1920)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE LED\[1\]\~reg0feeder) + (INSTANCE Equal0\~0) (DELAY (ABSOLUTE - (PORT datad (808:808:808) (843:843:843)) + (PORT dataa (343:343:343) (371:371:371)) + (PORT datab (336:336:336) (366:366:366)) + (PORT datac (312:312:312) (338:338:338)) + (PORT datad (318:318:318) (328:328:328)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (375:375:375) (396:396:396)) + (PORT datab (637:637:637) (652:652:652)) + (PORT datac (334:334:334) (353:353:353)) + (PORT datad (562:562:562) (570:570:570)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (247:247:247)) + (PORT datab (201:201:201) (241:241:241)) + (PORT datac (174:174:174) (208:208:208)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (612:612:612) (640:640:640)) + (PORT datab (820:820:820) (843:843:843)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (305:305:305) (321:321:321)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (601:601:601) (619:619:619)) + (PORT datab (378:378:378) (401:401:401)) + (PORT datad (189:189:189) (221:221:221)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE LED\[1\]\~reg0) + (INSTANCE address\[0\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1550:1550:1550)) + (PORT clk (1897:1897:1897) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -814,48 +844,53 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[23\]\~71) + (INSTANCE Equal0\~6) (DELAY (ABSOLUTE - (PORT datab (264:264:264) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT datac (181:181:181) (219:219:219)) + (PORT datad (183:183:183) (214:214:214)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[23\]) - (DELAY - (ABSOLUTE - (PORT clk (1898:1898:1898) (1920:1920:1920)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE LED\[2\]\~reg0feeder) + (INSTANCE Equal0\~7) (DELAY (ABSOLUTE - (PORT datad (771:771:771) (813:813:813)) + (PORT dataa (364:364:364) (391:391:391)) + (PORT datab (207:207:207) (248:248:248)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (181:181:181) (208:208:208)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (595:595:595) (669:669:669)) + (PORT datab (216:216:216) (261:261:261)) + (PORT datad (332:332:332) (350:350:350)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE LED\[2\]\~reg0) + (INSTANCE address\[1\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1550:1550:1550)) + (PORT clk (1897:1897:1897) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -866,48 +901,39 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[24\]\~73) + (INSTANCE address\[1\]\~2) (DELAY (ABSOLUTE - (PORT datab (264:264:264) (347:347:347)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (597:597:597) (670:670:670)) + (PORT datab (381:381:381) (404:404:404)) + (PORT datac (574:574:574) (583:583:583)) + (PORT datad (191:191:191) (224:224:224)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[24\]) - (DELAY - (ABSOLUTE - (PORT clk (1898:1898:1898) (1920:1920:1920)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE LED\[3\]\~reg0feeder) + (INSTANCE address\[2\]\~3) (DELAY (ABSOLUTE - (PORT datad (399:399:399) (452:452:452)) + (PORT datab (398:398:398) (468:468:468)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE LED\[3\]\~reg0) + (INSTANCE address\[2\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) + (PORT clk (1897:1897:1897) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -917,156 +943,89 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[25\]\~75) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) (DELAY (ABSOLUTE - (PORT dataa (266:266:266) (352:352:352)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[25\]) - (DELAY - (ABSOLUTE - (PORT clk (1898:1898:1898) (1920:1920:1920)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (PORT d[0] (1263:1263:1263) (1361:1361:1361)) + (PORT d[1] (1538:1538:1538) (1608:1608:1608)) + (PORT d[2] (1534:1534:1534) (1635:1635:1635)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD d (posedge clk) (187:187:187)) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE LED\[4\]\~reg0feeder) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) (DELAY (ABSOLUTE - (PORT datad (404:404:404) (467:467:467)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE LED\[4\]\~reg0) + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (PORT clk (1858:1858:1858) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1847:1847:1847)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[26\]\~77) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) (DELAY (ABSOLUTE - (PORT datab (263:263:263) (345:345:345)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) + (PORT clk (1005:1005:1005) (1010:1010:1010)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[26\]) + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1898:1898:1898) (1920:1920:1920)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE LED\[5\]\~reg0feeder) - (DELAY - (ABSOLUTE - (PORT datad (610:610:610) (670:670:670)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT clk (1006:1006:1006) (1011:1011:1011)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE LED\[5\]\~reg0) + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[27\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (266:266:266) (353:353:353)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH cin combout (455:455:455) (437:437:437)) + (PORT clk (1006:1006:1006) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[27\]) + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1898:1898:1898) (1920:1920:1920)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (PORT clk (1006:1006:1006) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE LED\[6\]\~reg0feeder) - (DELAY - (ABSOLUTE - (PORT datad (406:406:406) (467:467:467)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE LED\[6\]\~reg0) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) ) ) diff --git a/simulation/modelsim/spectrum_min_1200mv_0c_fast.vo b/simulation/modelsim/spectrum_min_1200mv_0c_fast.vo index 25a614c..59ddc72 100644 --- a/simulation/modelsim/spectrum_min_1200mv_0c_fast.vo +++ b/simulation/modelsim/spectrum_min_1200mv_0c_fast.vo @@ -16,7 +16,7 @@ // PROGRAM "Quartus II 32-bit" // VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" -// DATE "03/30/2022 11:51:43" +// DATE "03/30/2022 12:38:42" // // Device: Altera EP4CE22F17C6 Package FBGA256 @@ -71,80 +71,77 @@ wire \LED[6]~output_o ; wire \LED[7]~output_o ; wire \CLOCK_50~input_o ; wire \CLOCK_50~inputclkctrl_outclk ; -wire \counter[0]~81_combout ; -wire \counter[1]~27_combout ; -wire \counter[1]~28 ; -wire \counter[2]~29_combout ; -wire \counter[2]~30 ; -wire \counter[3]~31_combout ; -wire \counter[3]~32 ; -wire \counter[4]~33_combout ; -wire \counter[4]~34 ; -wire \counter[5]~35_combout ; -wire \counter[5]~36 ; -wire \counter[6]~37_combout ; -wire \counter[6]~38 ; -wire \counter[7]~39_combout ; -wire \counter[7]~40 ; -wire \counter[8]~41_combout ; -wire \counter[8]~42 ; -wire \counter[9]~43_combout ; -wire \counter[9]~44 ; -wire \counter[10]~45_combout ; -wire \counter[10]~46 ; -wire \counter[11]~47_combout ; -wire \counter[11]~48 ; -wire \counter[12]~49_combout ; -wire \counter[12]~50 ; -wire \counter[13]~51_combout ; -wire \counter[13]~52 ; -wire \counter[14]~53_combout ; -wire \counter[14]~54 ; -wire \counter[15]~55_combout ; -wire \counter[15]~56 ; -wire \counter[16]~57_combout ; -wire \counter[16]~58 ; -wire \counter[17]~59_combout ; -wire \counter[17]~60 ; -wire \counter[18]~61_combout ; -wire \counter[18]~62 ; -wire \counter[19]~63_combout ; -wire \counter[19]~64 ; -wire \counter[20]~65_combout ; -wire \counter[20]~66 ; -wire \counter[21]~67_combout ; -wire \LED[0]~reg0feeder_combout ; -wire \LED[0]~reg0_q ; -wire \counter[21]~68 ; -wire \counter[22]~69_combout ; -wire \LED[1]~reg0feeder_combout ; -wire \LED[1]~reg0_q ; -wire \counter[22]~70 ; -wire \counter[23]~71_combout ; -wire \LED[2]~reg0feeder_combout ; -wire \LED[2]~reg0_q ; -wire \counter[23]~72 ; -wire \counter[24]~73_combout ; -wire \LED[3]~reg0feeder_combout ; -wire \LED[3]~reg0_q ; -wire \counter[24]~74 ; -wire \counter[25]~75_combout ; -wire \LED[4]~reg0feeder_combout ; -wire \LED[4]~reg0_q ; -wire \counter[25]~76 ; -wire \counter[26]~77_combout ; -wire \LED[5]~reg0feeder_combout ; -wire \LED[5]~reg0_q ; -wire \counter[26]~78 ; -wire \counter[27]~79_combout ; -wire \LED[6]~reg0feeder_combout ; -wire \LED[6]~reg0_q ; -wire [27:0] counter; +wire \Add0~0_combout ; +wire \Add0~1 ; +wire \Add0~2_combout ; +wire \Add0~3 ; +wire \Add0~4_combout ; +wire \Add0~5 ; +wire \Add0~6_combout ; +wire \Add0~7 ; +wire \Add0~8_combout ; +wire \Add0~9 ; +wire \Add0~10_combout ; +wire \Add0~11 ; +wire \Add0~12_combout ; +wire \Add0~13 ; +wire \Add0~14_combout ; +wire \Add0~15 ; +wire \Add0~16_combout ; +wire \Add0~17 ; +wire \Add0~18_combout ; +wire \Add0~19 ; +wire \Add0~20_combout ; +wire \Add0~21 ; +wire \Add0~22_combout ; +wire \Add0~23 ; +wire \Add0~24_combout ; +wire \Add0~25 ; +wire \Add0~26_combout ; +wire \Add0~27 ; +wire \Add0~28_combout ; +wire \Add0~29 ; +wire \Add0~30_combout ; +wire \Add0~31 ; +wire \Add0~32_combout ; +wire \Add0~33 ; +wire \Add0~34_combout ; +wire \Add0~35 ; +wire \Add0~36_combout ; +wire \Add0~37 ; +wire \Add0~38_combout ; +wire \Add0~39 ; +wire \Add0~40_combout ; +wire \Equal0~5_combout ; +wire \Equal0~1_combout ; +wire \Equal0~0_combout ; +wire \Equal0~2_combout ; +wire \Equal0~3_combout ; +wire \Equal0~4_combout ; +wire \address[0]~0_combout ; +wire \Equal0~6_combout ; +wire \Equal0~7_combout ; +wire \address[1]~1_combout ; +wire \address[1]~2_combout ; +wire \address[2]~3_combout ; +wire [20:0] counter; +wire [2:0] address; +wire [7:0] \rom|altsyncram_component|auto_generated|q_a ; +wire [17:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; + +assign \rom|altsyncram_component|auto_generated|q_a [0] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; +assign \rom|altsyncram_component|auto_generated|q_a [1] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [1]; +assign \rom|altsyncram_component|auto_generated|q_a [2] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [2]; +assign \rom|altsyncram_component|auto_generated|q_a [3] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [3]; +assign \rom|altsyncram_component|auto_generated|q_a [4] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [4]; +assign \rom|altsyncram_component|auto_generated|q_a [5] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [5]; +assign \rom|altsyncram_component|auto_generated|q_a [6] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [6]; +assign \rom|altsyncram_component|auto_generated|q_a [7] = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [7]; // Location: IOOBUF_X38_Y34_N16 cycloneive_io_obuf \LED[0]~output ( - .i(\LED[0]~reg0_q ), + .i(\rom|altsyncram_component|auto_generated|q_a [0]), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -157,7 +154,7 @@ defparam \LED[0]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y34_N2 cycloneive_io_obuf \LED[1]~output ( - .i(\LED[1]~reg0_q ), + .i(\rom|altsyncram_component|auto_generated|q_a [1]), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -170,7 +167,7 @@ defparam \LED[1]~output .open_drain_output = "false"; // Location: IOOBUF_X49_Y34_N9 cycloneive_io_obuf \LED[2]~output ( - .i(\LED[2]~reg0_q ), + .i(\rom|altsyncram_component|auto_generated|q_a [2]), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -183,7 +180,7 @@ defparam \LED[2]~output .open_drain_output = "false"; // Location: IOOBUF_X40_Y34_N2 cycloneive_io_obuf \LED[3]~output ( - .i(\LED[3]~reg0_q ), + .i(\rom|altsyncram_component|auto_generated|q_a [3]), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -196,7 +193,7 @@ defparam \LED[3]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y25_N9 cycloneive_io_obuf \LED[4]~output ( - .i(\LED[4]~reg0_q ), + .i(\rom|altsyncram_component|auto_generated|q_a [4]), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -209,7 +206,7 @@ defparam \LED[4]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y26_N16 cycloneive_io_obuf \LED[5]~output ( - .i(\LED[5]~reg0_q ), + .i(\rom|altsyncram_component|auto_generated|q_a [5]), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -222,7 +219,7 @@ defparam \LED[5]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y28_N9 cycloneive_io_obuf \LED[6]~output ( - .i(\LED[6]~reg0_q ), + .i(\rom|altsyncram_component|auto_generated|q_a [6]), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -235,7 +232,7 @@ defparam \LED[6]~output .open_drain_output = "false"; // Location: IOOBUF_X0_Y10_N23 cycloneive_io_obuf \LED[7]~output ( - .i(gnd), + .i(\rom|altsyncram_component|auto_generated|q_a [7]), .oe(vcc), .seriesterminationcontrol(16'b0000000000000000), .devoe(devoe), @@ -269,767 +266,10 @@ defparam \CLOCK_50~inputclkctrl .clock_type = "global clock"; defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none"; // synopsys translate_on -// Location: LCCOMB_X39_Y33_N4 -cycloneive_lcell_comb \counter[0]~81 ( -// Equation(s): -// \counter[0]~81_combout = !counter[0] - - .dataa(gnd), - .datab(gnd), - .datac(counter[0]), - .datad(gnd), - .cin(gnd), - .combout(\counter[0]~81_combout ), - .cout()); -// synopsys translate_off -defparam \counter[0]~81 .lut_mask = 16'h0F0F; -defparam \counter[0]~81 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y33_N5 -dffeas \counter[0] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[0]~81_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[0]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[0] .is_wysiwyg = "true"; -defparam \counter[0] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N6 -cycloneive_lcell_comb \counter[1]~27 ( -// Equation(s): -// \counter[1]~27_combout = (counter[1] & (counter[0] $ (VCC))) # (!counter[1] & (counter[0] & VCC)) -// \counter[1]~28 = CARRY((counter[1] & counter[0])) - - .dataa(counter[1]), - .datab(counter[0]), - .datac(gnd), - .datad(vcc), - .cin(gnd), - .combout(\counter[1]~27_combout ), - .cout(\counter[1]~28 )); -// synopsys translate_off -defparam \counter[1]~27 .lut_mask = 16'h6688; -defparam \counter[1]~27 .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X39_Y33_N7 -dffeas \counter[1] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[1]~27_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[1]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[1] .is_wysiwyg = "true"; -defparam \counter[1] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N8 -cycloneive_lcell_comb \counter[2]~29 ( -// Equation(s): -// \counter[2]~29_combout = (counter[2] & (!\counter[1]~28 )) # (!counter[2] & ((\counter[1]~28 ) # (GND))) -// \counter[2]~30 = CARRY((!\counter[1]~28 ) # (!counter[2])) - - .dataa(gnd), - .datab(counter[2]), - .datac(gnd), - .datad(vcc), - .cin(\counter[1]~28 ), - .combout(\counter[2]~29_combout ), - .cout(\counter[2]~30 )); -// synopsys translate_off -defparam \counter[2]~29 .lut_mask = 16'h3C3F; -defparam \counter[2]~29 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N9 -dffeas \counter[2] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[2]~29_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[2]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[2] .is_wysiwyg = "true"; -defparam \counter[2] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N10 -cycloneive_lcell_comb \counter[3]~31 ( -// Equation(s): -// \counter[3]~31_combout = (counter[3] & (\counter[2]~30 $ (GND))) # (!counter[3] & (!\counter[2]~30 & VCC)) -// \counter[3]~32 = CARRY((counter[3] & !\counter[2]~30 )) - - .dataa(counter[3]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\counter[2]~30 ), - .combout(\counter[3]~31_combout ), - .cout(\counter[3]~32 )); -// synopsys translate_off -defparam \counter[3]~31 .lut_mask = 16'hA50A; -defparam \counter[3]~31 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N11 -dffeas \counter[3] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[3]~31_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[3]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[3] .is_wysiwyg = "true"; -defparam \counter[3] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N12 -cycloneive_lcell_comb \counter[4]~33 ( -// Equation(s): -// \counter[4]~33_combout = (counter[4] & (!\counter[3]~32 )) # (!counter[4] & ((\counter[3]~32 ) # (GND))) -// \counter[4]~34 = CARRY((!\counter[3]~32 ) # (!counter[4])) - - .dataa(counter[4]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\counter[3]~32 ), - .combout(\counter[4]~33_combout ), - .cout(\counter[4]~34 )); -// synopsys translate_off -defparam \counter[4]~33 .lut_mask = 16'h5A5F; -defparam \counter[4]~33 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N13 -dffeas \counter[4] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[4]~33_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[4]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[4] .is_wysiwyg = "true"; -defparam \counter[4] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N14 -cycloneive_lcell_comb \counter[5]~35 ( -// Equation(s): -// \counter[5]~35_combout = (counter[5] & (\counter[4]~34 $ (GND))) # (!counter[5] & (!\counter[4]~34 & VCC)) -// \counter[5]~36 = CARRY((counter[5] & !\counter[4]~34 )) - - .dataa(gnd), - .datab(counter[5]), - .datac(gnd), - .datad(vcc), - .cin(\counter[4]~34 ), - .combout(\counter[5]~35_combout ), - .cout(\counter[5]~36 )); -// synopsys translate_off -defparam \counter[5]~35 .lut_mask = 16'hC30C; -defparam \counter[5]~35 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N15 -dffeas \counter[5] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[5]~35_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[5]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[5] .is_wysiwyg = "true"; -defparam \counter[5] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N16 -cycloneive_lcell_comb \counter[6]~37 ( -// Equation(s): -// \counter[6]~37_combout = (counter[6] & (!\counter[5]~36 )) # (!counter[6] & ((\counter[5]~36 ) # (GND))) -// \counter[6]~38 = CARRY((!\counter[5]~36 ) # (!counter[6])) - - .dataa(gnd), - .datab(counter[6]), - .datac(gnd), - .datad(vcc), - .cin(\counter[5]~36 ), - .combout(\counter[6]~37_combout ), - .cout(\counter[6]~38 )); -// synopsys translate_off -defparam \counter[6]~37 .lut_mask = 16'h3C3F; -defparam \counter[6]~37 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N17 -dffeas \counter[6] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[6]~37_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[6]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[6] .is_wysiwyg = "true"; -defparam \counter[6] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N18 -cycloneive_lcell_comb \counter[7]~39 ( -// Equation(s): -// \counter[7]~39_combout = (counter[7] & (\counter[6]~38 $ (GND))) # (!counter[7] & (!\counter[6]~38 & VCC)) -// \counter[7]~40 = CARRY((counter[7] & !\counter[6]~38 )) - - .dataa(gnd), - .datab(counter[7]), - .datac(gnd), - .datad(vcc), - .cin(\counter[6]~38 ), - .combout(\counter[7]~39_combout ), - .cout(\counter[7]~40 )); -// synopsys translate_off -defparam \counter[7]~39 .lut_mask = 16'hC30C; -defparam \counter[7]~39 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N19 -dffeas \counter[7] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[7]~39_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[7]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[7] .is_wysiwyg = "true"; -defparam \counter[7] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N20 -cycloneive_lcell_comb \counter[8]~41 ( -// Equation(s): -// \counter[8]~41_combout = (counter[8] & (!\counter[7]~40 )) # (!counter[8] & ((\counter[7]~40 ) # (GND))) -// \counter[8]~42 = CARRY((!\counter[7]~40 ) # (!counter[8])) - - .dataa(gnd), - .datab(counter[8]), - .datac(gnd), - .datad(vcc), - .cin(\counter[7]~40 ), - .combout(\counter[8]~41_combout ), - .cout(\counter[8]~42 )); -// synopsys translate_off -defparam \counter[8]~41 .lut_mask = 16'h3C3F; -defparam \counter[8]~41 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N21 -dffeas \counter[8] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[8]~41_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[8]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[8] .is_wysiwyg = "true"; -defparam \counter[8] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N22 -cycloneive_lcell_comb \counter[9]~43 ( -// Equation(s): -// \counter[9]~43_combout = (counter[9] & (\counter[8]~42 $ (GND))) # (!counter[9] & (!\counter[8]~42 & VCC)) -// \counter[9]~44 = CARRY((counter[9] & !\counter[8]~42 )) - - .dataa(counter[9]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\counter[8]~42 ), - .combout(\counter[9]~43_combout ), - .cout(\counter[9]~44 )); -// synopsys translate_off -defparam \counter[9]~43 .lut_mask = 16'hA50A; -defparam \counter[9]~43 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N23 -dffeas \counter[9] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[9]~43_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[9]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[9] .is_wysiwyg = "true"; -defparam \counter[9] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N24 -cycloneive_lcell_comb \counter[10]~45 ( -// Equation(s): -// \counter[10]~45_combout = (counter[10] & (!\counter[9]~44 )) # (!counter[10] & ((\counter[9]~44 ) # (GND))) -// \counter[10]~46 = CARRY((!\counter[9]~44 ) # (!counter[10])) - - .dataa(gnd), - .datab(counter[10]), - .datac(gnd), - .datad(vcc), - .cin(\counter[9]~44 ), - .combout(\counter[10]~45_combout ), - .cout(\counter[10]~46 )); -// synopsys translate_off -defparam \counter[10]~45 .lut_mask = 16'h3C3F; -defparam \counter[10]~45 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N25 -dffeas \counter[10] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[10]~45_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[10]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[10] .is_wysiwyg = "true"; -defparam \counter[10] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N26 -cycloneive_lcell_comb \counter[11]~47 ( -// Equation(s): -// \counter[11]~47_combout = (counter[11] & (\counter[10]~46 $ (GND))) # (!counter[11] & (!\counter[10]~46 & VCC)) -// \counter[11]~48 = CARRY((counter[11] & !\counter[10]~46 )) - - .dataa(counter[11]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\counter[10]~46 ), - .combout(\counter[11]~47_combout ), - .cout(\counter[11]~48 )); -// synopsys translate_off -defparam \counter[11]~47 .lut_mask = 16'hA50A; -defparam \counter[11]~47 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N27 -dffeas \counter[11] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[11]~47_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[11]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[11] .is_wysiwyg = "true"; -defparam \counter[11] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N28 -cycloneive_lcell_comb \counter[12]~49 ( -// Equation(s): -// \counter[12]~49_combout = (counter[12] & (!\counter[11]~48 )) # (!counter[12] & ((\counter[11]~48 ) # (GND))) -// \counter[12]~50 = CARRY((!\counter[11]~48 ) # (!counter[12])) - - .dataa(gnd), - .datab(counter[12]), - .datac(gnd), - .datad(vcc), - .cin(\counter[11]~48 ), - .combout(\counter[12]~49_combout ), - .cout(\counter[12]~50 )); -// synopsys translate_off -defparam \counter[12]~49 .lut_mask = 16'h3C3F; -defparam \counter[12]~49 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N29 -dffeas \counter[12] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[12]~49_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[12]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[12] .is_wysiwyg = "true"; -defparam \counter[12] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y33_N30 -cycloneive_lcell_comb \counter[13]~51 ( -// Equation(s): -// \counter[13]~51_combout = (counter[13] & (\counter[12]~50 $ (GND))) # (!counter[13] & (!\counter[12]~50 & VCC)) -// \counter[13]~52 = CARRY((counter[13] & !\counter[12]~50 )) - - .dataa(counter[13]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\counter[12]~50 ), - .combout(\counter[13]~51_combout ), - .cout(\counter[13]~52 )); -// synopsys translate_off -defparam \counter[13]~51 .lut_mask = 16'hA50A; -defparam \counter[13]~51 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y33_N31 -dffeas \counter[13] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[13]~51_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[13]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[13] .is_wysiwyg = "true"; -defparam \counter[13] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y32_N0 -cycloneive_lcell_comb \counter[14]~53 ( -// Equation(s): -// \counter[14]~53_combout = (counter[14] & (!\counter[13]~52 )) # (!counter[14] & ((\counter[13]~52 ) # (GND))) -// \counter[14]~54 = CARRY((!\counter[13]~52 ) # (!counter[14])) - - .dataa(gnd), - .datab(counter[14]), - .datac(gnd), - .datad(vcc), - .cin(\counter[13]~52 ), - .combout(\counter[14]~53_combout ), - .cout(\counter[14]~54 )); -// synopsys translate_off -defparam \counter[14]~53 .lut_mask = 16'h3C3F; -defparam \counter[14]~53 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N1 -dffeas \counter[14] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[14]~53_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[14]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[14] .is_wysiwyg = "true"; -defparam \counter[14] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y32_N2 -cycloneive_lcell_comb \counter[15]~55 ( -// Equation(s): -// \counter[15]~55_combout = (counter[15] & (\counter[14]~54 $ (GND))) # (!counter[15] & (!\counter[14]~54 & VCC)) -// \counter[15]~56 = CARRY((counter[15] & !\counter[14]~54 )) - - .dataa(gnd), - .datab(counter[15]), - .datac(gnd), - .datad(vcc), - .cin(\counter[14]~54 ), - .combout(\counter[15]~55_combout ), - .cout(\counter[15]~56 )); -// synopsys translate_off -defparam \counter[15]~55 .lut_mask = 16'hC30C; -defparam \counter[15]~55 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N3 -dffeas \counter[15] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[15]~55_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[15]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[15] .is_wysiwyg = "true"; -defparam \counter[15] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y32_N4 -cycloneive_lcell_comb \counter[16]~57 ( -// Equation(s): -// \counter[16]~57_combout = (counter[16] & (!\counter[15]~56 )) # (!counter[16] & ((\counter[15]~56 ) # (GND))) -// \counter[16]~58 = CARRY((!\counter[15]~56 ) # (!counter[16])) - - .dataa(gnd), - .datab(counter[16]), - .datac(gnd), - .datad(vcc), - .cin(\counter[15]~56 ), - .combout(\counter[16]~57_combout ), - .cout(\counter[16]~58 )); -// synopsys translate_off -defparam \counter[16]~57 .lut_mask = 16'h3C3F; -defparam \counter[16]~57 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N5 -dffeas \counter[16] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[16]~57_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[16]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[16] .is_wysiwyg = "true"; -defparam \counter[16] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y32_N6 -cycloneive_lcell_comb \counter[17]~59 ( -// Equation(s): -// \counter[17]~59_combout = (counter[17] & (\counter[16]~58 $ (GND))) # (!counter[17] & (!\counter[16]~58 & VCC)) -// \counter[17]~60 = CARRY((counter[17] & !\counter[16]~58 )) - - .dataa(counter[17]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\counter[16]~58 ), - .combout(\counter[17]~59_combout ), - .cout(\counter[17]~60 )); -// synopsys translate_off -defparam \counter[17]~59 .lut_mask = 16'hA50A; -defparam \counter[17]~59 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N7 -dffeas \counter[17] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[17]~59_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[17]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[17] .is_wysiwyg = "true"; -defparam \counter[17] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y32_N8 -cycloneive_lcell_comb \counter[18]~61 ( -// Equation(s): -// \counter[18]~61_combout = (counter[18] & (!\counter[17]~60 )) # (!counter[18] & ((\counter[17]~60 ) # (GND))) -// \counter[18]~62 = CARRY((!\counter[17]~60 ) # (!counter[18])) - - .dataa(gnd), - .datab(counter[18]), - .datac(gnd), - .datad(vcc), - .cin(\counter[17]~60 ), - .combout(\counter[18]~61_combout ), - .cout(\counter[18]~62 )); -// synopsys translate_off -defparam \counter[18]~61 .lut_mask = 16'h3C3F; -defparam \counter[18]~61 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N9 -dffeas \counter[18] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[18]~61_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[18]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[18] .is_wysiwyg = "true"; -defparam \counter[18] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y32_N10 -cycloneive_lcell_comb \counter[19]~63 ( -// Equation(s): -// \counter[19]~63_combout = (counter[19] & (\counter[18]~62 $ (GND))) # (!counter[19] & (!\counter[18]~62 & VCC)) -// \counter[19]~64 = CARRY((counter[19] & !\counter[18]~62 )) - - .dataa(counter[19]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\counter[18]~62 ), - .combout(\counter[19]~63_combout ), - .cout(\counter[19]~64 )); -// synopsys translate_off -defparam \counter[19]~63 .lut_mask = 16'hA50A; -defparam \counter[19]~63 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N11 -dffeas \counter[19] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[19]~63_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[19]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[19] .is_wysiwyg = "true"; -defparam \counter[19] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y32_N12 -cycloneive_lcell_comb \counter[20]~65 ( -// Equation(s): -// \counter[20]~65_combout = (counter[20] & (!\counter[19]~64 )) # (!counter[20] & ((\counter[19]~64 ) # (GND))) -// \counter[20]~66 = CARRY((!\counter[19]~64 ) # (!counter[20])) - - .dataa(counter[20]), - .datab(gnd), - .datac(gnd), - .datad(vcc), - .cin(\counter[19]~64 ), - .combout(\counter[20]~65_combout ), - .cout(\counter[20]~66 )); -// synopsys translate_off -defparam \counter[20]~65 .lut_mask = 16'h5A5F; -defparam \counter[20]~65 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N13 +// Location: FF_X31_Y17_N21 dffeas \counter[20] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[20]~65_combout ), + .d(\Add0~40_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1045,356 +285,28 @@ defparam \counter[20] .is_wysiwyg = "true"; defparam \counter[20] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y32_N14 -cycloneive_lcell_comb \counter[21]~67 ( +// Location: LCCOMB_X31_Y18_N12 +cycloneive_lcell_comb \Add0~0 ( // Equation(s): -// \counter[21]~67_combout = (counter[21] & (\counter[20]~66 $ (GND))) # (!counter[21] & (!\counter[20]~66 & VCC)) -// \counter[21]~68 = CARRY((counter[21] & !\counter[20]~66 )) +// \Add0~0_combout = counter[0] $ (VCC) +// \Add0~1 = CARRY(counter[0]) - .dataa(gnd), - .datab(counter[21]), - .datac(gnd), - .datad(vcc), - .cin(\counter[20]~66 ), - .combout(\counter[21]~67_combout ), - .cout(\counter[21]~68 )); -// synopsys translate_off -defparam \counter[21]~67 .lut_mask = 16'hC30C; -defparam \counter[21]~67 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N15 -dffeas \counter[21] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[21]~67_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[21]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[21] .is_wysiwyg = "true"; -defparam \counter[21] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y32_N4 -cycloneive_lcell_comb \LED[0]~reg0feeder ( -// Equation(s): -// \LED[0]~reg0feeder_combout = counter[21] - - .dataa(gnd), - .datab(gnd), - .datac(counter[21]), - .datad(gnd), - .cin(gnd), - .combout(\LED[0]~reg0feeder_combout ), - .cout()); -// synopsys translate_off -defparam \LED[0]~reg0feeder .lut_mask = 16'hF0F0; -defparam \LED[0]~reg0feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X38_Y32_N5 -dffeas \LED[0]~reg0 ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\LED[0]~reg0feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\LED[0]~reg0_q ), - .prn(vcc)); -// synopsys translate_off -defparam \LED[0]~reg0 .is_wysiwyg = "true"; -defparam \LED[0]~reg0 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y32_N16 -cycloneive_lcell_comb \counter[22]~69 ( -// Equation(s): -// \counter[22]~69_combout = (counter[22] & (!\counter[21]~68 )) # (!counter[22] & ((\counter[21]~68 ) # (GND))) -// \counter[22]~70 = CARRY((!\counter[21]~68 ) # (!counter[22])) - - .dataa(gnd), - .datab(counter[22]), - .datac(gnd), - .datad(vcc), - .cin(\counter[21]~68 ), - .combout(\counter[22]~69_combout ), - .cout(\counter[22]~70 )); -// synopsys translate_off -defparam \counter[22]~69 .lut_mask = 16'h3C3F; -defparam \counter[22]~69 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N17 -dffeas \counter[22] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[22]~69_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[22]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[22] .is_wysiwyg = "true"; -defparam \counter[22] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y32_N12 -cycloneive_lcell_comb \LED[1]~reg0feeder ( -// Equation(s): -// \LED[1]~reg0feeder_combout = counter[22] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(counter[22]), - .cin(gnd), - .combout(\LED[1]~reg0feeder_combout ), - .cout()); -// synopsys translate_off -defparam \LED[1]~reg0feeder .lut_mask = 16'hFF00; -defparam \LED[1]~reg0feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X46_Y32_N13 -dffeas \LED[1]~reg0 ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\LED[1]~reg0feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\LED[1]~reg0_q ), - .prn(vcc)); -// synopsys translate_off -defparam \LED[1]~reg0 .is_wysiwyg = "true"; -defparam \LED[1]~reg0 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y32_N18 -cycloneive_lcell_comb \counter[23]~71 ( -// Equation(s): -// \counter[23]~71_combout = (counter[23] & (\counter[22]~70 $ (GND))) # (!counter[23] & (!\counter[22]~70 & VCC)) -// \counter[23]~72 = CARRY((counter[23] & !\counter[22]~70 )) - - .dataa(gnd), - .datab(counter[23]), - .datac(gnd), - .datad(vcc), - .cin(\counter[22]~70 ), - .combout(\counter[23]~71_combout ), - .cout(\counter[23]~72 )); -// synopsys translate_off -defparam \counter[23]~71 .lut_mask = 16'hC30C; -defparam \counter[23]~71 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N19 -dffeas \counter[23] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[23]~71_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[23]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[23] .is_wysiwyg = "true"; -defparam \counter[23] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X46_Y32_N6 -cycloneive_lcell_comb \LED[2]~reg0feeder ( -// Equation(s): -// \LED[2]~reg0feeder_combout = counter[23] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(counter[23]), - .cin(gnd), - .combout(\LED[2]~reg0feeder_combout ), - .cout()); -// synopsys translate_off -defparam \LED[2]~reg0feeder .lut_mask = 16'hFF00; -defparam \LED[2]~reg0feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X46_Y32_N7 -dffeas \LED[2]~reg0 ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\LED[2]~reg0feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\LED[2]~reg0_q ), - .prn(vcc)); -// synopsys translate_off -defparam \LED[2]~reg0 .is_wysiwyg = "true"; -defparam \LED[2]~reg0 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y32_N20 -cycloneive_lcell_comb \counter[24]~73 ( -// Equation(s): -// \counter[24]~73_combout = (counter[24] & (!\counter[23]~72 )) # (!counter[24] & ((\counter[23]~72 ) # (GND))) -// \counter[24]~74 = CARRY((!\counter[23]~72 ) # (!counter[24])) - - .dataa(gnd), - .datab(counter[24]), - .datac(gnd), - .datad(vcc), - .cin(\counter[23]~72 ), - .combout(\counter[24]~73_combout ), - .cout(\counter[24]~74 )); -// synopsys translate_off -defparam \counter[24]~73 .lut_mask = 16'h3C3F; -defparam \counter[24]~73 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N21 -dffeas \counter[24] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[24]~73_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[24]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[24] .is_wysiwyg = "true"; -defparam \counter[24] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X40_Y32_N4 -cycloneive_lcell_comb \LED[3]~reg0feeder ( -// Equation(s): -// \LED[3]~reg0feeder_combout = counter[24] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(counter[24]), - .cin(gnd), - .combout(\LED[3]~reg0feeder_combout ), - .cout()); -// synopsys translate_off -defparam \LED[3]~reg0feeder .lut_mask = 16'hFF00; -defparam \LED[3]~reg0feeder .sum_lutc_input = "datac"; -// synopsys translate_on - -// Location: FF_X40_Y32_N5 -dffeas \LED[3]~reg0 ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\LED[3]~reg0feeder_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(\LED[3]~reg0_q ), - .prn(vcc)); -// synopsys translate_off -defparam \LED[3]~reg0 .is_wysiwyg = "true"; -defparam \LED[3]~reg0 .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X39_Y32_N22 -cycloneive_lcell_comb \counter[25]~75 ( -// Equation(s): -// \counter[25]~75_combout = (counter[25] & (\counter[24]~74 $ (GND))) # (!counter[25] & (!\counter[24]~74 & VCC)) -// \counter[25]~76 = CARRY((counter[25] & !\counter[24]~74 )) - - .dataa(counter[25]), + .dataa(counter[0]), .datab(gnd), .datac(gnd), .datad(vcc), - .cin(\counter[24]~74 ), - .combout(\counter[25]~75_combout ), - .cout(\counter[25]~76 )); -// synopsys translate_off -defparam \counter[25]~75 .lut_mask = 16'hA50A; -defparam \counter[25]~75 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N23 -dffeas \counter[25] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[25]~75_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[25]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[25] .is_wysiwyg = "true"; -defparam \counter[25] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y32_N18 -cycloneive_lcell_comb \LED[4]~reg0feeder ( -// Equation(s): -// \LED[4]~reg0feeder_combout = counter[25] - - .dataa(gnd), - .datab(gnd), - .datac(gnd), - .datad(counter[25]), .cin(gnd), - .combout(\LED[4]~reg0feeder_combout ), - .cout()); + .combout(\Add0~0_combout ), + .cout(\Add0~1 )); // synopsys translate_off -defparam \LED[4]~reg0feeder .lut_mask = 16'hFF00; -defparam \LED[4]~reg0feeder .sum_lutc_input = "datac"; +defparam \Add0~0 .lut_mask = 16'h55AA; +defparam \Add0~0 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y32_N19 -dffeas \LED[4]~reg0 ( +// Location: FF_X31_Y18_N13 +dffeas \counter[0] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\LED[4]~reg0feeder_combout ), + .d(\Add0~0_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1403,35 +315,35 @@ dffeas \LED[4]~reg0 ( .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\LED[4]~reg0_q ), + .q(counter[0]), .prn(vcc)); // synopsys translate_off -defparam \LED[4]~reg0 .is_wysiwyg = "true"; -defparam \LED[4]~reg0 .power_up = "low"; +defparam \counter[0] .is_wysiwyg = "true"; +defparam \counter[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y32_N24 -cycloneive_lcell_comb \counter[26]~77 ( +// Location: LCCOMB_X31_Y18_N14 +cycloneive_lcell_comb \Add0~2 ( // Equation(s): -// \counter[26]~77_combout = (counter[26] & (!\counter[25]~76 )) # (!counter[26] & ((\counter[25]~76 ) # (GND))) -// \counter[26]~78 = CARRY((!\counter[25]~76 ) # (!counter[26])) +// \Add0~2_combout = (counter[1] & (!\Add0~1 )) # (!counter[1] & ((\Add0~1 ) # (GND))) +// \Add0~3 = CARRY((!\Add0~1 ) # (!counter[1])) .dataa(gnd), - .datab(counter[26]), + .datab(counter[1]), .datac(gnd), .datad(vcc), - .cin(\counter[25]~76 ), - .combout(\counter[26]~77_combout ), - .cout(\counter[26]~78 )); + .cin(\Add0~1 ), + .combout(\Add0~2_combout ), + .cout(\Add0~3 )); // synopsys translate_off -defparam \counter[26]~77 .lut_mask = 16'h3C3F; -defparam \counter[26]~77 .sum_lutc_input = "cin"; +defparam \Add0~2 .lut_mask = 16'h3C3F; +defparam \Add0~2 .sum_lutc_input = "cin"; // synopsys translate_on -// Location: FF_X39_Y32_N25 -dffeas \counter[26] ( +// Location: FF_X31_Y18_N15 +dffeas \counter[1] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[26]~77_combout ), + .d(\Add0~2_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1440,34 +352,819 @@ dffeas \counter[26] ( .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(counter[26]), + .q(counter[1]), .prn(vcc)); // synopsys translate_off -defparam \counter[26] .is_wysiwyg = "true"; -defparam \counter[26] .power_up = "low"; +defparam \counter[1] .is_wysiwyg = "true"; +defparam \counter[1] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X38_Y32_N24 -cycloneive_lcell_comb \LED[5]~reg0feeder ( +// Location: LCCOMB_X31_Y18_N16 +cycloneive_lcell_comb \Add0~4 ( // Equation(s): -// \LED[5]~reg0feeder_combout = counter[26] +// \Add0~4_combout = (counter[2] & (\Add0~3 $ (GND))) # (!counter[2] & (!\Add0~3 & VCC)) +// \Add0~5 = CARRY((counter[2] & !\Add0~3 )) + + .dataa(gnd), + .datab(counter[2]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~3 ), + .combout(\Add0~4_combout ), + .cout(\Add0~5 )); +// synopsys translate_off +defparam \Add0~4 .lut_mask = 16'hC30C; +defparam \Add0~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y18_N17 +dffeas \counter[2] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[2]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[2] .is_wysiwyg = "true"; +defparam \counter[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N18 +cycloneive_lcell_comb \Add0~6 ( +// Equation(s): +// \Add0~6_combout = (counter[3] & (!\Add0~5 )) # (!counter[3] & ((\Add0~5 ) # (GND))) +// \Add0~7 = CARRY((!\Add0~5 ) # (!counter[3])) + + .dataa(gnd), + .datab(counter[3]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~5 ), + .combout(\Add0~6_combout ), + .cout(\Add0~7 )); +// synopsys translate_off +defparam \Add0~6 .lut_mask = 16'h3C3F; +defparam \Add0~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y18_N19 +dffeas \counter[3] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[3]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[3] .is_wysiwyg = "true"; +defparam \counter[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N20 +cycloneive_lcell_comb \Add0~8 ( +// Equation(s): +// \Add0~8_combout = (counter[4] & (\Add0~7 $ (GND))) # (!counter[4] & (!\Add0~7 & VCC)) +// \Add0~9 = CARRY((counter[4] & !\Add0~7 )) + + .dataa(counter[4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add0~7 ), + .combout(\Add0~8_combout ), + .cout(\Add0~9 )); +// synopsys translate_off +defparam \Add0~8 .lut_mask = 16'hA50A; +defparam \Add0~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y18_N21 +dffeas \counter[4] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[4]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[4] .is_wysiwyg = "true"; +defparam \counter[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N22 +cycloneive_lcell_comb \Add0~10 ( +// Equation(s): +// \Add0~10_combout = (counter[5] & (!\Add0~9 )) # (!counter[5] & ((\Add0~9 ) # (GND))) +// \Add0~11 = CARRY((!\Add0~9 ) # (!counter[5])) + + .dataa(gnd), + .datab(counter[5]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~9 ), + .combout(\Add0~10_combout ), + .cout(\Add0~11 )); +// synopsys translate_off +defparam \Add0~10 .lut_mask = 16'h3C3F; +defparam \Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y18_N23 +dffeas \counter[5] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~10_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[5]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[5] .is_wysiwyg = "true"; +defparam \counter[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N24 +cycloneive_lcell_comb \Add0~12 ( +// Equation(s): +// \Add0~12_combout = (counter[6] & (\Add0~11 $ (GND))) # (!counter[6] & (!\Add0~11 & VCC)) +// \Add0~13 = CARRY((counter[6] & !\Add0~11 )) + + .dataa(counter[6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add0~11 ), + .combout(\Add0~12_combout ), + .cout(\Add0~13 )); +// synopsys translate_off +defparam \Add0~12 .lut_mask = 16'hA50A; +defparam \Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y18_N25 +dffeas \counter[6] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~12_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[6]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[6] .is_wysiwyg = "true"; +defparam \counter[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N26 +cycloneive_lcell_comb \Add0~14 ( +// Equation(s): +// \Add0~14_combout = (counter[7] & (!\Add0~13 )) # (!counter[7] & ((\Add0~13 ) # (GND))) +// \Add0~15 = CARRY((!\Add0~13 ) # (!counter[7])) + + .dataa(gnd), + .datab(counter[7]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~13 ), + .combout(\Add0~14_combout ), + .cout(\Add0~15 )); +// synopsys translate_off +defparam \Add0~14 .lut_mask = 16'h3C3F; +defparam \Add0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y18_N27 +dffeas \counter[7] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~14_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[7]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[7] .is_wysiwyg = "true"; +defparam \counter[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N28 +cycloneive_lcell_comb \Add0~16 ( +// Equation(s): +// \Add0~16_combout = (counter[8] & (\Add0~15 $ (GND))) # (!counter[8] & (!\Add0~15 & VCC)) +// \Add0~17 = CARRY((counter[8] & !\Add0~15 )) + + .dataa(gnd), + .datab(counter[8]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~15 ), + .combout(\Add0~16_combout ), + .cout(\Add0~17 )); +// synopsys translate_off +defparam \Add0~16 .lut_mask = 16'hC30C; +defparam \Add0~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y18_N29 +dffeas \counter[8] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~16_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[8]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[8] .is_wysiwyg = "true"; +defparam \counter[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N30 +cycloneive_lcell_comb \Add0~18 ( +// Equation(s): +// \Add0~18_combout = (counter[9] & (!\Add0~17 )) # (!counter[9] & ((\Add0~17 ) # (GND))) +// \Add0~19 = CARRY((!\Add0~17 ) # (!counter[9])) + + .dataa(counter[9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add0~17 ), + .combout(\Add0~18_combout ), + .cout(\Add0~19 )); +// synopsys translate_off +defparam \Add0~18 .lut_mask = 16'h5A5F; +defparam \Add0~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y18_N31 +dffeas \counter[9] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~18_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[9]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[9] .is_wysiwyg = "true"; +defparam \counter[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N0 +cycloneive_lcell_comb \Add0~20 ( +// Equation(s): +// \Add0~20_combout = (counter[10] & (\Add0~19 $ (GND))) # (!counter[10] & (!\Add0~19 & VCC)) +// \Add0~21 = CARRY((counter[10] & !\Add0~19 )) + + .dataa(gnd), + .datab(counter[10]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~19 ), + .combout(\Add0~20_combout ), + .cout(\Add0~21 )); +// synopsys translate_off +defparam \Add0~20 .lut_mask = 16'hC30C; +defparam \Add0~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y17_N1 +dffeas \counter[10] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~20_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[10]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[10] .is_wysiwyg = "true"; +defparam \counter[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N2 +cycloneive_lcell_comb \Add0~22 ( +// Equation(s): +// \Add0~22_combout = (counter[11] & (!\Add0~21 )) # (!counter[11] & ((\Add0~21 ) # (GND))) +// \Add0~23 = CARRY((!\Add0~21 ) # (!counter[11])) + + .dataa(gnd), + .datab(counter[11]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~21 ), + .combout(\Add0~22_combout ), + .cout(\Add0~23 )); +// synopsys translate_off +defparam \Add0~22 .lut_mask = 16'h3C3F; +defparam \Add0~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y17_N3 +dffeas \counter[11] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~22_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[11]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[11] .is_wysiwyg = "true"; +defparam \counter[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N4 +cycloneive_lcell_comb \Add0~24 ( +// Equation(s): +// \Add0~24_combout = (counter[12] & (\Add0~23 $ (GND))) # (!counter[12] & (!\Add0~23 & VCC)) +// \Add0~25 = CARRY((counter[12] & !\Add0~23 )) + + .dataa(gnd), + .datab(counter[12]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~23 ), + .combout(\Add0~24_combout ), + .cout(\Add0~25 )); +// synopsys translate_off +defparam \Add0~24 .lut_mask = 16'hC30C; +defparam \Add0~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y17_N5 +dffeas \counter[12] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~24_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[12]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[12] .is_wysiwyg = "true"; +defparam \counter[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N6 +cycloneive_lcell_comb \Add0~26 ( +// Equation(s): +// \Add0~26_combout = (counter[13] & (!\Add0~25 )) # (!counter[13] & ((\Add0~25 ) # (GND))) +// \Add0~27 = CARRY((!\Add0~25 ) # (!counter[13])) + + .dataa(gnd), + .datab(counter[13]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~25 ), + .combout(\Add0~26_combout ), + .cout(\Add0~27 )); +// synopsys translate_off +defparam \Add0~26 .lut_mask = 16'h3C3F; +defparam \Add0~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y17_N7 +dffeas \counter[13] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~26_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[13]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[13] .is_wysiwyg = "true"; +defparam \counter[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N8 +cycloneive_lcell_comb \Add0~28 ( +// Equation(s): +// \Add0~28_combout = (counter[14] & (\Add0~27 $ (GND))) # (!counter[14] & (!\Add0~27 & VCC)) +// \Add0~29 = CARRY((counter[14] & !\Add0~27 )) + + .dataa(counter[14]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add0~27 ), + .combout(\Add0~28_combout ), + .cout(\Add0~29 )); +// synopsys translate_off +defparam \Add0~28 .lut_mask = 16'hA50A; +defparam \Add0~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y17_N9 +dffeas \counter[14] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~28_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[14]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[14] .is_wysiwyg = "true"; +defparam \counter[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N10 +cycloneive_lcell_comb \Add0~30 ( +// Equation(s): +// \Add0~30_combout = (counter[15] & (!\Add0~29 )) # (!counter[15] & ((\Add0~29 ) # (GND))) +// \Add0~31 = CARRY((!\Add0~29 ) # (!counter[15])) + + .dataa(gnd), + .datab(counter[15]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~29 ), + .combout(\Add0~30_combout ), + .cout(\Add0~31 )); +// synopsys translate_off +defparam \Add0~30 .lut_mask = 16'h3C3F; +defparam \Add0~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y17_N11 +dffeas \counter[15] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~30_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[15]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[15] .is_wysiwyg = "true"; +defparam \counter[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N12 +cycloneive_lcell_comb \Add0~32 ( +// Equation(s): +// \Add0~32_combout = (counter[16] & (\Add0~31 $ (GND))) # (!counter[16] & (!\Add0~31 & VCC)) +// \Add0~33 = CARRY((counter[16] & !\Add0~31 )) + + .dataa(gnd), + .datab(counter[16]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~31 ), + .combout(\Add0~32_combout ), + .cout(\Add0~33 )); +// synopsys translate_off +defparam \Add0~32 .lut_mask = 16'hC30C; +defparam \Add0~32 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y17_N13 +dffeas \counter[16] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~32_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[16]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[16] .is_wysiwyg = "true"; +defparam \counter[16] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N14 +cycloneive_lcell_comb \Add0~34 ( +// Equation(s): +// \Add0~34_combout = (counter[17] & (!\Add0~33 )) # (!counter[17] & ((\Add0~33 ) # (GND))) +// \Add0~35 = CARRY((!\Add0~33 ) # (!counter[17])) + + .dataa(counter[17]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add0~33 ), + .combout(\Add0~34_combout ), + .cout(\Add0~35 )); +// synopsys translate_off +defparam \Add0~34 .lut_mask = 16'h5A5F; +defparam \Add0~34 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y17_N15 +dffeas \counter[17] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~34_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[17]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[17] .is_wysiwyg = "true"; +defparam \counter[17] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N16 +cycloneive_lcell_comb \Add0~36 ( +// Equation(s): +// \Add0~36_combout = (counter[18] & (\Add0~35 $ (GND))) # (!counter[18] & (!\Add0~35 & VCC)) +// \Add0~37 = CARRY((counter[18] & !\Add0~35 )) + + .dataa(counter[18]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add0~35 ), + .combout(\Add0~36_combout ), + .cout(\Add0~37 )); +// synopsys translate_off +defparam \Add0~36 .lut_mask = 16'hA50A; +defparam \Add0~36 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y17_N17 +dffeas \counter[18] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~36_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[18]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[18] .is_wysiwyg = "true"; +defparam \counter[18] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N18 +cycloneive_lcell_comb \Add0~38 ( +// Equation(s): +// \Add0~38_combout = (counter[19] & (!\Add0~37 )) # (!counter[19] & ((\Add0~37 ) # (GND))) +// \Add0~39 = CARRY((!\Add0~37 ) # (!counter[19])) + + .dataa(counter[19]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add0~37 ), + .combout(\Add0~38_combout ), + .cout(\Add0~39 )); +// synopsys translate_off +defparam \Add0~38 .lut_mask = 16'h5A5F; +defparam \Add0~38 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X31_Y17_N19 +dffeas \counter[19] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\Add0~38_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(counter[19]), + .prn(vcc)); +// synopsys translate_off +defparam \counter[19] .is_wysiwyg = "true"; +defparam \counter[19] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N20 +cycloneive_lcell_comb \Add0~40 ( +// Equation(s): +// \Add0~40_combout = \Add0~39 $ (!counter[20]) .dataa(gnd), .datab(gnd), .datac(gnd), - .datad(counter[26]), + .datad(counter[20]), + .cin(\Add0~39 ), + .combout(\Add0~40_combout ), + .cout()); +// synopsys translate_off +defparam \Add0~40 .lut_mask = 16'hF00F; +defparam \Add0~40 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N28 +cycloneive_lcell_comb \Equal0~5 ( +// Equation(s): +// \Equal0~5_combout = (!\Add0~32_combout & (!\Add0~36_combout & (!\Add0~34_combout & !\Add0~38_combout ))) + + .dataa(\Add0~32_combout ), + .datab(\Add0~36_combout ), + .datac(\Add0~34_combout ), + .datad(\Add0~38_combout ), .cin(gnd), - .combout(\LED[5]~reg0feeder_combout ), + .combout(\Equal0~5_combout ), .cout()); // synopsys translate_off -defparam \LED[5]~reg0feeder .lut_mask = 16'hFF00; -defparam \LED[5]~reg0feeder .sum_lutc_input = "datac"; +defparam \Equal0~5 .lut_mask = 16'h0001; +defparam \Equal0~5 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y32_N25 -dffeas \LED[5]~reg0 ( +// Location: LCCOMB_X31_Y18_N6 +cycloneive_lcell_comb \Equal0~1 ( +// Equation(s): +// \Equal0~1_combout = (!\Add0~10_combout & (!\Add0~8_combout & (!\Add0~14_combout & !\Add0~12_combout ))) + + .dataa(\Add0~10_combout ), + .datab(\Add0~8_combout ), + .datac(\Add0~14_combout ), + .datad(\Add0~12_combout ), + .cin(gnd), + .combout(\Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~1 .lut_mask = 16'h0001; +defparam \Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y18_N4 +cycloneive_lcell_comb \Equal0~0 ( +// Equation(s): +// \Equal0~0_combout = (!\Add0~4_combout & (!\Add0~0_combout & (!\Add0~6_combout & !\Add0~2_combout ))) + + .dataa(\Add0~4_combout ), + .datab(\Add0~0_combout ), + .datac(\Add0~6_combout ), + .datad(\Add0~2_combout ), + .cin(gnd), + .combout(\Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~0 .lut_mask = 16'h0001; +defparam \Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N30 +cycloneive_lcell_comb \Equal0~2 ( +// Equation(s): +// \Equal0~2_combout = (!\Add0~22_combout & (!\Add0~16_combout & (!\Add0~20_combout & !\Add0~18_combout ))) + + .dataa(\Add0~22_combout ), + .datab(\Add0~16_combout ), + .datac(\Add0~20_combout ), + .datad(\Add0~18_combout ), + .cin(gnd), + .combout(\Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~2 .lut_mask = 16'h0001; +defparam \Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y17_N30 +cycloneive_lcell_comb \Equal0~3 ( +// Equation(s): +// \Equal0~3_combout = (!\Add0~26_combout & (!\Add0~24_combout & (!\Add0~28_combout & !\Add0~30_combout ))) + + .dataa(\Add0~26_combout ), + .datab(\Add0~24_combout ), + .datac(\Add0~28_combout ), + .datad(\Add0~30_combout ), + .cin(gnd), + .combout(\Equal0~3_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~3 .lut_mask = 16'h0001; +defparam \Equal0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N28 +cycloneive_lcell_comb \Equal0~4 ( +// Equation(s): +// \Equal0~4_combout = (\Equal0~1_combout & (\Equal0~0_combout & (\Equal0~2_combout & \Equal0~3_combout ))) + + .dataa(\Equal0~1_combout ), + .datab(\Equal0~0_combout ), + .datac(\Equal0~2_combout ), + .datad(\Equal0~3_combout ), + .cin(gnd), + .combout(\Equal0~4_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~4 .lut_mask = 16'h8000; +defparam \Equal0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N20 +cycloneive_lcell_comb \address[0]~0 ( +// Equation(s): +// \address[0]~0_combout = address[0] $ (((!\Add0~40_combout & (\Equal0~5_combout & \Equal0~4_combout )))) + + .dataa(\Add0~40_combout ), + .datab(\Equal0~5_combout ), + .datac(address[0]), + .datad(\Equal0~4_combout ), + .cin(gnd), + .combout(\address[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \address[0]~0 .lut_mask = 16'hB4F0; +defparam \address[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N21 +dffeas \address[0] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\LED[5]~reg0feeder_combout ), + .d(\address[0]~0_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1476,70 +1173,68 @@ dffeas \LED[5]~reg0 ( .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\LED[5]~reg0_q ), + .q(address[0]), .prn(vcc)); // synopsys translate_off -defparam \LED[5]~reg0 .is_wysiwyg = "true"; -defparam \LED[5]~reg0 .power_up = "low"; +defparam \address[0] .is_wysiwyg = "true"; +defparam \address[0] .power_up = "low"; // synopsys translate_on -// Location: LCCOMB_X39_Y32_N26 -cycloneive_lcell_comb \counter[27]~79 ( +// Location: LCCOMB_X31_Y17_N26 +cycloneive_lcell_comb \Equal0~6 ( // Equation(s): -// \counter[27]~79_combout = counter[27] $ (!\counter[26]~78 ) - - .dataa(counter[27]), - .datab(gnd), - .datac(gnd), - .datad(gnd), - .cin(\counter[26]~78 ), - .combout(\counter[27]~79_combout ), - .cout()); -// synopsys translate_off -defparam \counter[27]~79 .lut_mask = 16'hA5A5; -defparam \counter[27]~79 .sum_lutc_input = "cin"; -// synopsys translate_on - -// Location: FF_X39_Y32_N27 -dffeas \counter[27] ( - .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\counter[27]~79_combout ), - .asdata(vcc), - .clrn(vcc), - .aload(gnd), - .sclr(gnd), - .sload(gnd), - .ena(vcc), - .devclrn(devclrn), - .devpor(devpor), - .q(counter[27]), - .prn(vcc)); -// synopsys translate_off -defparam \counter[27] .is_wysiwyg = "true"; -defparam \counter[27] .power_up = "low"; -// synopsys translate_on - -// Location: LCCOMB_X38_Y32_N14 -cycloneive_lcell_comb \LED[6]~reg0feeder ( -// Equation(s): -// \LED[6]~reg0feeder_combout = counter[27] +// \Equal0~6_combout = (!\Add0~34_combout & !\Add0~32_combout ) .dataa(gnd), .datab(gnd), - .datac(gnd), - .datad(counter[27]), + .datac(\Add0~34_combout ), + .datad(\Add0~32_combout ), .cin(gnd), - .combout(\LED[6]~reg0feeder_combout ), + .combout(\Equal0~6_combout ), .cout()); // synopsys translate_off -defparam \LED[6]~reg0feeder .lut_mask = 16'hFF00; -defparam \LED[6]~reg0feeder .sum_lutc_input = "datac"; +defparam \Equal0~6 .lut_mask = 16'h000F; +defparam \Equal0~6 .sum_lutc_input = "datac"; // synopsys translate_on -// Location: FF_X38_Y32_N15 -dffeas \LED[6]~reg0 ( +// Location: LCCOMB_X31_Y17_N24 +cycloneive_lcell_comb \Equal0~7 ( +// Equation(s): +// \Equal0~7_combout = (!\Add0~40_combout & (!\Add0~36_combout & (\Equal0~6_combout & !\Add0~38_combout ))) + + .dataa(\Add0~40_combout ), + .datab(\Add0~36_combout ), + .datac(\Equal0~6_combout ), + .datad(\Add0~38_combout ), + .cin(gnd), + .combout(\Equal0~7_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~7 .lut_mask = 16'h0010; +defparam \Equal0~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N10 +cycloneive_lcell_comb \address[1]~1 ( +// Equation(s): +// \address[1]~1_combout = address[1] $ (((address[0] & (\Equal0~4_combout & \Equal0~7_combout )))) + + .dataa(address[0]), + .datab(\Equal0~4_combout ), + .datac(address[1]), + .datad(\Equal0~7_combout ), + .cin(gnd), + .combout(\address[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \address[1]~1 .lut_mask = 16'h78F0; +defparam \address[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N11 +dffeas \address[1] ( .clk(\CLOCK_50~inputclkctrl_outclk ), - .d(\LED[6]~reg0feeder_combout ), + .d(\address[1]~1_combout ), .asdata(vcc), .clrn(vcc), .aload(gnd), @@ -1548,11 +1243,116 @@ dffeas \LED[6]~reg0 ( .ena(vcc), .devclrn(devclrn), .devpor(devpor), - .q(\LED[6]~reg0_q ), + .q(address[1]), .prn(vcc)); // synopsys translate_off -defparam \LED[6]~reg0 .is_wysiwyg = "true"; -defparam \LED[6]~reg0 .power_up = "low"; +defparam \address[1] .is_wysiwyg = "true"; +defparam \address[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N2 +cycloneive_lcell_comb \address[1]~2 ( +// Equation(s): +// \address[1]~2_combout = (address[0] & (\Equal0~5_combout & (!\Add0~40_combout & \Equal0~4_combout ))) + + .dataa(address[0]), + .datab(\Equal0~5_combout ), + .datac(\Add0~40_combout ), + .datad(\Equal0~4_combout ), + .cin(gnd), + .combout(\address[1]~2_combout ), + .cout()); +// synopsys translate_off +defparam \address[1]~2 .lut_mask = 16'h0800; +defparam \address[1]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y17_N16 +cycloneive_lcell_comb \address[2]~3 ( +// Equation(s): +// \address[2]~3_combout = address[2] $ (((address[1] & \address[1]~2_combout ))) + + .dataa(gnd), + .datab(address[1]), + .datac(address[2]), + .datad(\address[1]~2_combout ), + .cin(gnd), + .combout(\address[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \address[2]~3 .lut_mask = 16'h3CF0; +defparam \address[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y17_N17 +dffeas \address[2] ( + .clk(\CLOCK_50~inputclkctrl_outclk ), + .d(\address[2]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(address[2]), + .prn(vcc)); +// synopsys translate_off +defparam \address[2] .is_wysiwyg = "true"; +defparam \address[2] .power_up = "low"; +// synopsys translate_on + +// Location: M9K_X33_Y26_N0 +cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\CLOCK_50~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(vcc), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(18'b000000000000000000), + .portaaddr({address[2],address[1],address[0]}), + .portabyteenamasks(1'b1), + .portbdatain(18'b000000000000000000), + .portbaddr(3'b000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_ro91:auto_generated|ALTSYNCRAM"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 18; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 7; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 3; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 18; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 144'h002040042000900018000600024001080081; // synopsys translate_on assign LED[0] = \LED[0]~output_o ; diff --git a/simulation/modelsim/spectrum_min_1200mv_0c_v_fast.sdo b/simulation/modelsim/spectrum_min_1200mv_0c_v_fast.sdo index dd66449..5ca5f65 100644 --- a/simulation/modelsim/spectrum_min_1200mv_0c_v_fast.sdo +++ b/simulation/modelsim/spectrum_min_1200mv_0c_v_fast.sdo @@ -29,7 +29,7 @@ (DELAYFILE (SDFVERSION "2.1") (DESIGN "spectrum") - (DATE "03/30/2022 11:51:43") + (DATE "03/30/2022 12:38:42") (VENDOR "Altera") (PROGRAM "Quartus II 32-bit") (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") @@ -41,7 +41,7 @@ (INSTANCE LED\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (268:268:268) (309:309:309)) + (PORT i (761:761:761) (843:843:843)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -51,7 +51,7 @@ (INSTANCE LED\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (394:394:394) (447:447:447)) + (PORT i (788:788:788) (884:884:884)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -61,7 +61,7 @@ (INSTANCE LED\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (384:384:384) (435:435:435)) + (PORT i (1023:1023:1023) (1135:1135:1135)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -71,7 +71,7 @@ (INSTANCE LED\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (267:267:267) (309:309:309)) + (PORT i (793:793:793) (868:868:868)) (IOPATH i o (1643:1643:1643) (1588:1588:1588)) ) ) @@ -81,7 +81,7 @@ (INSTANCE LED\[4\]\~output) (DELAY (ABSOLUTE - (PORT i (1373:1373:1373) (1578:1578:1578)) + (PORT i (980:980:980) (1098:1098:1098)) (IOPATH i o (1666:1666:1666) (1600:1600:1600)) ) ) @@ -91,7 +91,7 @@ (INSTANCE LED\[5\]\~output) (DELAY (ABSOLUTE - (PORT i (1355:1355:1355) (1575:1575:1575)) + (PORT i (739:739:739) (841:841:841)) (IOPATH i o (3106:3106:3106) (2841:2841:2841)) ) ) @@ -101,11 +101,21 @@ (INSTANCE LED\[6\]\~output) (DELAY (ABSOLUTE - (PORT i (754:754:754) (885:885:885)) + (PORT i (1028:1028:1028) (1155:1155:1155)) (IOPATH i o (1586:1586:1586) (1541:1541:1541)) ) ) ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE LED\[7\]\~output) + (DELAY + (ABSOLUTE + (PORT i (837:837:837) (953:953:953)) + (IOPATH i o (3106:3106:3106) (2841:2841:2841)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_io_ibuf") (INSTANCE CLOCK_50\~input) @@ -125,11 +135,28 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[0\]\~81) + (CELLTYPE "dffeas") + (INSTANCE counter\[20\]) (DELAY (ABSOLUTE - (IOPATH datac combout (190:190:190) (195:195:195)) + (PORT clk (912:912:912) (916:916:916)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (130:130:130) (179:179:179)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) @@ -138,7 +165,7 @@ (INSTANCE counter\[0\]) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) + (PORT clk (912:912:912) (916:916:916)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -149,16 +176,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[1\]\~27) + (INSTANCE Add0\~2) (DELAY (ABSOLUTE - (PORT dataa (130:130:130) (181:181:181)) (PORT datab (129:129:129) (177:177:177)) - (IOPATH dataa combout (186:186:186) (180:180:180)) - (IOPATH dataa cout (226:226:226) (171:171:171)) - (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab combout (166:166:166) (176:176:176)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) ) ) ) @@ -167,7 +193,7 @@ (INSTANCE counter\[1\]) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) + (PORT clk (912:912:912) (916:916:916)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -178,11 +204,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[2\]\~29) + (INSTANCE Add0\~4) (DELAY (ABSOLUTE - (PORT datab (130:130:130) (177:177:177)) - (IOPATH datab combout (166:166:166) (176:176:176)) + (PORT datab (129:129:129) (177:177:177)) + (IOPATH datab combout (192:192:192) (177:177:177)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) @@ -195,7 +221,7 @@ (INSTANCE counter\[2\]) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) + (PORT clk (912:912:912) (916:916:916)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -206,12 +232,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[3\]\~31) + (INSTANCE Add0\~6) (DELAY (ABSOLUTE - (PORT dataa (130:130:130) (180:180:180)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH dataa cout (226:226:226) (171:171:171)) + (PORT datab (129:129:129) (177:177:177)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -223,7 +249,7 @@ (INSTANCE counter\[3\]) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) + (PORT clk (912:912:912) (916:916:916)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -234,11 +260,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[4\]\~33) + (INSTANCE Add0\~8) (DELAY (ABSOLUTE - (PORT dataa (130:130:130) (180:180:180)) - (IOPATH dataa combout (165:165:165) (173:173:173)) + (PORT dataa (200:200:200) (257:257:257)) + (IOPATH dataa combout (186:186:186) (175:175:175)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) @@ -251,7 +277,7 @@ (INSTANCE counter\[4\]) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) + (PORT clk (912:912:912) (916:916:916)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -262,11 +288,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[5\]\~35) + (INSTANCE Add0\~10) (DELAY (ABSOLUTE - (PORT datab (129:129:129) (177:177:177)) - (IOPATH datab combout (192:192:192) (177:177:177)) + (PORT datab (199:199:199) (255:255:255)) + (IOPATH datab combout (166:166:166) (176:176:176)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) @@ -279,7 +305,7 @@ (INSTANCE counter\[5\]) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) + (PORT clk (912:912:912) (916:916:916)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -290,12 +316,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[6\]\~37) + (INSTANCE Add0\~12) (DELAY (ABSOLUTE - (PORT datab (129:129:129) (177:177:177)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datab cout (227:227:227) (175:175:175)) + (PORT dataa (200:200:200) (257:257:257)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -307,7 +333,7 @@ (INSTANCE counter\[6\]) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) + (PORT clk (912:912:912) (916:916:916)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -318,11 +344,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[7\]\~39) + (INSTANCE Add0\~14) (DELAY (ABSOLUTE - (PORT datab (130:130:130) (177:177:177)) - (IOPATH datab combout (192:192:192) (177:177:177)) + (PORT datab (198:198:198) (255:255:255)) + (IOPATH datab combout (166:166:166) (176:176:176)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) @@ -335,7 +361,7 @@ (INSTANCE counter\[7\]) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) + (PORT clk (912:912:912) (916:916:916)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -346,11 +372,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[8\]\~41) + (INSTANCE Add0\~16) (DELAY (ABSOLUTE - (PORT datab (130:130:130) (177:177:177)) - (IOPATH datab combout (166:166:166) (176:176:176)) + (PORT datab (128:128:128) (176:176:176)) + (IOPATH datab combout (192:192:192) (177:177:177)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) @@ -363,7 +389,7 @@ (INSTANCE counter\[8\]) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) + (PORT clk (912:912:912) (916:916:916)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -374,11 +400,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[9\]\~43) + (INSTANCE Add0\~18) (DELAY (ABSOLUTE - (PORT dataa (131:131:131) (180:180:180)) - (IOPATH dataa combout (186:186:186) (175:175:175)) + (PORT dataa (129:129:129) (179:179:179)) + (IOPATH dataa combout (165:165:165) (173:173:173)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) @@ -391,7 +417,7 @@ (INSTANCE counter\[9\]) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) + (PORT clk (912:912:912) (916:916:916)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -402,11 +428,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[10\]\~45) + (INSTANCE Add0\~20) (DELAY (ABSOLUTE - (PORT datab (130:130:130) (177:177:177)) - (IOPATH datab combout (166:166:166) (176:176:176)) + (PORT datab (128:128:128) (176:176:176)) + (IOPATH datab combout (192:192:192) (177:177:177)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) @@ -419,7 +445,7 @@ (INSTANCE counter\[10\]) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) + (PORT clk (912:912:912) (916:916:916)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -430,12 +456,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[11\]\~47) + (INSTANCE Add0\~22) (DELAY (ABSOLUTE - (PORT dataa (130:130:130) (181:181:181)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH dataa cout (226:226:226) (171:171:171)) + (PORT datab (200:200:200) (254:254:254)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -447,7 +473,7 @@ (INSTANCE counter\[11\]) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) + (PORT clk (912:912:912) (916:916:916)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -458,11 +484,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[12\]\~49) + (INSTANCE Add0\~24) (DELAY (ABSOLUTE - (PORT datab (129:129:129) (177:177:177)) - (IOPATH datab combout (166:166:166) (176:176:176)) + (PORT datab (199:199:199) (254:254:254)) + (IOPATH datab combout (192:192:192) (177:177:177)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) @@ -475,7 +501,7 @@ (INSTANCE counter\[12\]) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (919:919:919)) + (PORT clk (912:912:912) (916:916:916)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -486,12 +512,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[13\]\~51) + (INSTANCE Add0\~26) (DELAY (ABSOLUTE - (PORT dataa (129:129:129) (180:180:180)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH dataa cout (226:226:226) (171:171:171)) + (PORT datab (200:200:200) (254:254:254)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -503,7 +529,7 @@ (INSTANCE counter\[13\]) (DELAY (ABSOLUTE - (PORT clk (1112:1112:1112) (1141:1141:1141)) + (PORT clk (912:912:912) (916:916:916)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -514,12 +540,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[14\]\~53) + (INSTANCE Add0\~28) (DELAY (ABSOLUTE - (PORT datab (129:129:129) (177:177:177)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datab cout (227:227:227) (175:175:175)) + (PORT dataa (199:199:199) (259:259:259)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -531,7 +557,7 @@ (INSTANCE counter\[14\]) (DELAY (ABSOLUTE - (PORT clk (914:914:914) (919:919:919)) + (PORT clk (912:912:912) (916:916:916)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -542,11 +568,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[15\]\~55) + (INSTANCE Add0\~30) (DELAY (ABSOLUTE - (PORT datab (129:129:129) (177:177:177)) - (IOPATH datab combout (192:192:192) (177:177:177)) + (PORT datab (200:200:200) (254:254:254)) + (IOPATH datab combout (166:166:166) (176:176:176)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) @@ -559,7 +585,7 @@ (INSTANCE counter\[15\]) (DELAY (ABSOLUTE - (PORT clk (914:914:914) (919:919:919)) + (PORT clk (912:912:912) (916:916:916)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -570,11 +596,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[16\]\~57) + (INSTANCE Add0\~32) (DELAY (ABSOLUTE - (PORT datab (130:130:130) (178:178:178)) - (IOPATH datab combout (166:166:166) (176:176:176)) + (PORT datab (199:199:199) (257:257:257)) + (IOPATH datab combout (192:192:192) (177:177:177)) (IOPATH datab cout (227:227:227) (175:175:175)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) @@ -587,7 +613,7 @@ (INSTANCE counter\[16\]) (DELAY (ABSOLUTE - (PORT clk (914:914:914) (919:919:919)) + (PORT clk (912:912:912) (916:916:916)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -598,11 +624,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[17\]\~59) + (INSTANCE Add0\~34) (DELAY (ABSOLUTE - (PORT dataa (131:131:131) (181:181:181)) - (IOPATH dataa combout (186:186:186) (175:175:175)) + (PORT dataa (201:201:201) (257:257:257)) + (IOPATH dataa combout (165:165:165) (173:173:173)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) @@ -615,7 +641,7 @@ (INSTANCE counter\[17\]) (DELAY (ABSOLUTE - (PORT clk (1112:1112:1112) (1141:1141:1141)) + (PORT clk (912:912:912) (916:916:916)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -626,12 +652,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[18\]\~61) + (INSTANCE Add0\~36) (DELAY (ABSOLUTE - (PORT datab (130:130:130) (178:178:178)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datab cout (227:227:227) (175:175:175)) + (PORT dataa (201:201:201) (257:257:257)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) (IOPATH cin cout (34:34:34) (34:34:34)) @@ -643,7 +669,7 @@ (INSTANCE counter\[18\]) (DELAY (ABSOLUTE - (PORT clk (1112:1112:1112) (1141:1141:1141)) + (PORT clk (912:912:912) (916:916:916)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -654,11 +680,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[19\]\~63) + (INSTANCE Add0\~38) (DELAY (ABSOLUTE - (PORT dataa (131:131:131) (181:181:181)) - (IOPATH dataa combout (186:186:186) (175:175:175)) + (PORT dataa (200:200:200) (261:261:261)) + (IOPATH dataa combout (165:165:165) (173:173:173)) (IOPATH dataa cout (226:226:226) (171:171:171)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) @@ -671,7 +697,7 @@ (INSTANCE counter\[19\]) (DELAY (ABSOLUTE - (PORT clk (1112:1112:1112) (1141:1141:1141)) + (PORT clk (912:912:912) (916:916:916)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -682,76 +708,132 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[20\]\~65) + (INSTANCE Add0\~40) (DELAY (ABSOLUTE - (PORT dataa (131:131:131) (181:181:181)) - (IOPATH dataa combout (165:165:165) (173:173:173)) - (IOPATH dataa cout (226:226:226) (171:171:171)) + (PORT datad (118:118:118) (154:154:154)) (IOPATH datad combout (68:68:68) (63:63:63)) (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[20\]) - (DELAY - (ABSOLUTE - (PORT clk (1112:1112:1112) (1141:1141:1141)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[21\]\~67) + (INSTANCE Equal0\~5) (DELAY (ABSOLUTE - (PORT datab (142:142:142) (190:190:190)) - (IOPATH datab combout (192:192:192) (177:177:177)) - (IOPATH datab cout (227:227:227) (175:175:175)) + (PORT dataa (110:110:110) (143:143:143)) + (PORT datab (109:109:109) (139:139:139)) + (PORT datac (96:96:96) (120:120:120)) + (PORT datad (95:95:95) (114:114:114)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[21\]) - (DELAY - (ABSOLUTE - (PORT clk (1112:1112:1112) (1141:1141:1141)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE LED\[0\]\~reg0feeder) + (INSTANCE Equal0\~1) (DELAY (ABSOLUTE - (PORT datac (213:213:213) (265:265:265)) + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (91:91:91) (114:114:114)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (175:175:175) (212:212:212)) + (PORT datab (173:173:173) (211:211:211)) + (PORT datac (160:160:160) (194:194:194)) + (PORT datad (162:162:162) (186:186:186)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (228:228:228)) + (PORT datab (336:336:336) (394:394:394)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (293:293:293) (332:332:332)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (107:107:107) (139:139:139)) + (PORT datab (106:106:106) (135:135:135)) + (PORT datac (92:92:92) (114:114:114)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (387:387:387)) + (PORT datab (430:430:430) (498:498:498)) + (PORT datac (88:88:88) (110:110:110)) + (PORT datad (156:156:156) (182:182:182)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (306:306:306) (353:353:353)) + (PORT datab (190:190:190) (228:228:228)) + (PORT datad (98:98:98) (120:120:120)) + (IOPATH dataa combout (159:159:159) (173:173:173)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE LED\[0\]\~reg0) + (INSTANCE address\[0\]) (DELAY (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) + (PORT clk (1110:1110:1110) (1138:1138:1138)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -762,48 +844,96 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[22\]\~69) + (INSTANCE Equal0\~6) (DELAY (ABSOLUTE - (PORT datab (142:142:142) (190:190:190)) + (PORT datac (95:95:95) (120:120:120)) + (PORT datad (97:97:97) (118:118:118)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~7) + (DELAY + (ABSOLUTE + (PORT dataa (187:187:187) (223:223:223)) + (PORT datab (109:109:109) (139:139:139)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (95:95:95) (113:113:113)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (314:314:314) (385:385:385)) + (PORT datab (114:114:114) (147:147:147)) + (PORT datad (169:169:169) (198:198:198)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE address\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1110:1110:1110) (1138:1138:1138)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[1\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (315:315:315) (387:387:387)) + (PORT datab (194:194:194) (233:233:233)) + (PORT datac (295:295:295) (332:332:332)) + (PORT datad (102:102:102) (125:125:125)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT datab (207:207:207) (264:264:264)) + (PORT datad (92:92:92) (109:109:109)) (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[22\]) - (DELAY - (ABSOLUTE - (PORT clk (1112:1112:1112) (1141:1141:1141)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE LED\[1\]\~reg0feeder) - (DELAY - (ABSOLUTE - (PORT datad (427:427:427) (494:494:494)) + (IOPATH datac combout (190:190:190) (195:195:195)) (IOPATH datad combout (68:68:68) (63:63:63)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE LED\[1\]\~reg0) + (INSTANCE address\[2\]) (DELAY (ABSOLUTE - (PORT clk (919:919:919) (924:924:924)) + (PORT clk (1110:1110:1110) (1138:1138:1138)) (PORT d (37:37:37) (50:50:50)) (IOPATH (posedge clk) q (105:105:105) (105:105:105)) ) @@ -813,260 +943,89 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[23\]\~71) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) (DELAY (ABSOLUTE - (PORT datab (142:142:142) (190:190:190)) - (IOPATH datab combout (192:192:192) (177:177:177)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[23\]) - (DELAY - (ABSOLUTE - (PORT clk (1112:1112:1112) (1141:1141:1141)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (PORT d[0] (720:720:720) (839:839:839)) + (PORT d[1] (870:870:870) (1010:1010:1010)) + (PORT d[2] (873:873:873) (1012:1012:1012)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) + (HOLD d (posedge clk) (104:104:104)) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE LED\[2\]\~reg0feeder) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) (DELAY (ABSOLUTE - (PORT datad (416:416:416) (474:474:474)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT clk (1095:1095:1095) (1112:1112:1112)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE LED\[2\]\~reg0) + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (919:919:919) (924:924:924)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (PORT clk (1096:1096:1096) (1113:1113:1113)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1077:1077:1077) (1093:1093:1093)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[24\]\~73) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) (DELAY (ABSOLUTE - (PORT datab (142:142:142) (190:190:190)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) + (PORT clk (617:617:617) (625:625:625)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[24\]) + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1112:1112:1112) (1141:1141:1141)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE LED\[3\]\~reg0feeder) - (DELAY - (ABSOLUTE - (PORT datad (208:208:208) (254:254:254)) - (IOPATH datad combout (68:68:68) (63:63:63)) + (PORT clk (618:618:618) (626:626:626)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE LED\[3\]\~reg0) + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (915:915:915) (920:920:920)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[25\]\~75) - (DELAY - (ABSOLUTE - (PORT dataa (143:143:143) (193:193:193)) - (IOPATH dataa combout (186:186:186) (175:175:175)) - (IOPATH dataa cout (226:226:226) (171:171:171)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[25\]) + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1112:1112:1112) (1141:1141:1141)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (PORT clk (618:618:618) (626:626:626)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE LED\[4\]\~reg0feeder) - (DELAY - (ABSOLUTE - (PORT datad (211:211:211) (260:260:260)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE LED\[4\]\~reg0) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[26\]\~77) - (DELAY - (ABSOLUTE - (PORT datab (142:142:142) (190:190:190)) - (IOPATH datab combout (166:166:166) (176:176:176)) - (IOPATH datab cout (227:227:227) (175:175:175)) - (IOPATH datad combout (68:68:68) (63:63:63)) - (IOPATH cin combout (187:187:187) (204:204:204)) - (IOPATH cin cout (34:34:34) (34:34:34)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[26\]) - (DELAY - (ABSOLUTE - (PORT clk (1112:1112:1112) (1141:1141:1141)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE LED\[5\]\~reg0feeder) - (DELAY - (ABSOLUTE - (PORT datad (321:321:321) (380:380:380)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE LED\[5\]\~reg0) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[27\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (143:143:143) (194:194:194)) - (IOPATH dataa combout (188:188:188) (193:193:193)) - (IOPATH cin combout (187:187:187) (204:204:204)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[27\]) - (DELAY - (ABSOLUTE - (PORT clk (1112:1112:1112) (1141:1141:1141)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE LED\[6\]\~reg0feeder) - (DELAY - (ABSOLUTE - (PORT datad (211:211:211) (260:260:260)) - (IOPATH datad combout (68:68:68) (63:63:63)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE LED\[6\]\~reg0) - (DELAY - (ABSOLUTE - (PORT clk (913:913:913) (917:917:917)) - (PORT d (37:37:37) (50:50:50)) - (IOPATH (posedge clk) q (105:105:105) (105:105:105)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (84:84:84)) - ) ) ) diff --git a/simulation/modelsim/spectrum_modelsim.xrf b/simulation/modelsim/spectrum_modelsim.xrf index d71ae1d..5aff091 100644 --- a/simulation/modelsim/spectrum_modelsim.xrf +++ b/simulation/modelsim/spectrum_modelsim.xrf @@ -1,6 +1,21 @@ vendor_name = ModelSim source_file = 1, /home/benny/work/fpga/projects/spectrum.v +source_file = 1, /home/benny/work/fpga/projects/output_files/led_patterns.mif +source_file = 1, /home/benny/work/fpga/projects/led_patterns.mif +source_file = 1, /home/benny/work/fpga/projects/rom0.qip +source_file = 1, /home/benny/work/fpga/projects/rom0.v source_file = 1, /home/benny/work/fpga/projects/db/spectrum.cbx.xml +source_file = 1, /home/benny/altera/13.1/quartus/libraries/megafunctions/altsyncram.tdf +source_file = 1, /home/benny/altera/13.1/quartus/libraries/megafunctions/stratix_ram_block.inc +source_file = 1, /home/benny/altera/13.1/quartus/libraries/megafunctions/lpm_mux.inc +source_file = 1, /home/benny/altera/13.1/quartus/libraries/megafunctions/lpm_decode.inc +source_file = 1, /home/benny/altera/13.1/quartus/libraries/megafunctions/aglobal131.inc +source_file = 1, /home/benny/altera/13.1/quartus/libraries/megafunctions/a_rdenreg.inc +source_file = 1, /home/benny/altera/13.1/quartus/libraries/megafunctions/altrom.inc +source_file = 1, /home/benny/altera/13.1/quartus/libraries/megafunctions/altram.inc +source_file = 1, /home/benny/altera/13.1/quartus/libraries/megafunctions/altdpram.inc +source_file = 1, /home/benny/altera/13.1/quartus/libraries/megafunctions/cbx.lst +source_file = 1, /home/benny/work/fpga/projects/db/altsyncram_ro91.tdf design_name = spectrum instance = comp, \LED[0]~output , LED[0]~output, spectrum, 1 instance = comp, \LED[1]~output , LED[1]~output, spectrum, 1 @@ -12,73 +27,61 @@ instance = comp, \LED[6]~output , LED[6]~output, spectrum, 1 instance = comp, \LED[7]~output , LED[7]~output, spectrum, 1 instance = comp, \CLOCK_50~input , CLOCK_50~input, spectrum, 1 instance = comp, \CLOCK_50~inputclkctrl , CLOCK_50~inputclkctrl, spectrum, 1 -instance = comp, \counter[0]~81 , counter[0]~81, spectrum, 1 -instance = comp, \counter[0] , counter[0], spectrum, 1 -instance = comp, \counter[1]~27 , counter[1]~27, spectrum, 1 -instance = comp, \counter[1] , counter[1], spectrum, 1 -instance = comp, \counter[2]~29 , counter[2]~29, spectrum, 1 -instance = comp, \counter[2] , counter[2], spectrum, 1 -instance = comp, \counter[3]~31 , counter[3]~31, spectrum, 1 -instance = comp, \counter[3] , counter[3], spectrum, 1 -instance = comp, \counter[4]~33 , counter[4]~33, spectrum, 1 -instance = comp, \counter[4] , counter[4], spectrum, 1 -instance = comp, \counter[5]~35 , counter[5]~35, spectrum, 1 -instance = comp, \counter[5] , counter[5], spectrum, 1 -instance = comp, \counter[6]~37 , counter[6]~37, spectrum, 1 -instance = comp, \counter[6] , counter[6], spectrum, 1 -instance = comp, \counter[7]~39 , counter[7]~39, spectrum, 1 -instance = comp, \counter[7] , counter[7], spectrum, 1 -instance = comp, \counter[8]~41 , counter[8]~41, spectrum, 1 -instance = comp, \counter[8] , counter[8], spectrum, 1 -instance = comp, \counter[9]~43 , counter[9]~43, spectrum, 1 -instance = comp, \counter[9] , counter[9], spectrum, 1 -instance = comp, \counter[10]~45 , counter[10]~45, spectrum, 1 -instance = comp, \counter[10] , counter[10], spectrum, 1 -instance = comp, \counter[11]~47 , counter[11]~47, spectrum, 1 -instance = comp, \counter[11] , counter[11], spectrum, 1 -instance = comp, \counter[12]~49 , counter[12]~49, spectrum, 1 -instance = comp, \counter[12] , counter[12], spectrum, 1 -instance = comp, \counter[13]~51 , counter[13]~51, spectrum, 1 -instance = comp, \counter[13] , counter[13], spectrum, 1 -instance = comp, \counter[14]~53 , counter[14]~53, spectrum, 1 -instance = comp, \counter[14] , counter[14], spectrum, 1 -instance = comp, \counter[15]~55 , counter[15]~55, spectrum, 1 -instance = comp, \counter[15] , counter[15], spectrum, 1 -instance = comp, \counter[16]~57 , counter[16]~57, spectrum, 1 -instance = comp, \counter[16] , counter[16], spectrum, 1 -instance = comp, \counter[17]~59 , counter[17]~59, spectrum, 1 -instance = comp, \counter[17] , counter[17], spectrum, 1 -instance = comp, \counter[18]~61 , counter[18]~61, spectrum, 1 -instance = comp, \counter[18] , counter[18], spectrum, 1 -instance = comp, \counter[19]~63 , counter[19]~63, spectrum, 1 -instance = comp, \counter[19] , counter[19], spectrum, 1 -instance = comp, \counter[20]~65 , counter[20]~65, spectrum, 1 instance = comp, \counter[20] , counter[20], spectrum, 1 -instance = comp, \counter[21]~67 , counter[21]~67, spectrum, 1 -instance = comp, \counter[21] , counter[21], spectrum, 1 -instance = comp, \LED[0]~reg0feeder , LED[0]~reg0feeder, spectrum, 1 -instance = comp, \LED[0]~reg0 , LED[0]~reg0, spectrum, 1 -instance = comp, \counter[22]~69 , counter[22]~69, spectrum, 1 -instance = comp, \counter[22] , counter[22], spectrum, 1 -instance = comp, \LED[1]~reg0feeder , LED[1]~reg0feeder, spectrum, 1 -instance = comp, \LED[1]~reg0 , LED[1]~reg0, spectrum, 1 -instance = comp, \counter[23]~71 , counter[23]~71, spectrum, 1 -instance = comp, \counter[23] , counter[23], spectrum, 1 -instance = comp, \LED[2]~reg0feeder , LED[2]~reg0feeder, spectrum, 1 -instance = comp, \LED[2]~reg0 , LED[2]~reg0, spectrum, 1 -instance = comp, \counter[24]~73 , counter[24]~73, spectrum, 1 -instance = comp, \counter[24] , counter[24], spectrum, 1 -instance = comp, \LED[3]~reg0feeder , LED[3]~reg0feeder, spectrum, 1 -instance = comp, \LED[3]~reg0 , LED[3]~reg0, spectrum, 1 -instance = comp, \counter[25]~75 , counter[25]~75, spectrum, 1 -instance = comp, \counter[25] , counter[25], spectrum, 1 -instance = comp, \LED[4]~reg0feeder , LED[4]~reg0feeder, spectrum, 1 -instance = comp, \LED[4]~reg0 , LED[4]~reg0, spectrum, 1 -instance = comp, \counter[26]~77 , counter[26]~77, spectrum, 1 -instance = comp, \counter[26] , counter[26], spectrum, 1 -instance = comp, \LED[5]~reg0feeder , LED[5]~reg0feeder, spectrum, 1 -instance = comp, \LED[5]~reg0 , LED[5]~reg0, spectrum, 1 -instance = comp, \counter[27]~79 , counter[27]~79, spectrum, 1 -instance = comp, \counter[27] , counter[27], spectrum, 1 -instance = comp, \LED[6]~reg0feeder , LED[6]~reg0feeder, spectrum, 1 -instance = comp, \LED[6]~reg0 , LED[6]~reg0, spectrum, 1 +instance = comp, \Add0~0 , Add0~0, spectrum, 1 +instance = comp, \counter[0] , counter[0], spectrum, 1 +instance = comp, \Add0~2 , Add0~2, spectrum, 1 +instance = comp, \counter[1] , counter[1], spectrum, 1 +instance = comp, \Add0~4 , Add0~4, spectrum, 1 +instance = comp, \counter[2] , counter[2], spectrum, 1 +instance = comp, \Add0~6 , Add0~6, spectrum, 1 +instance = comp, \counter[3] , counter[3], spectrum, 1 +instance = comp, \Add0~8 , Add0~8, spectrum, 1 +instance = comp, \counter[4] , counter[4], spectrum, 1 +instance = comp, \Add0~10 , Add0~10, spectrum, 1 +instance = comp, \counter[5] , counter[5], spectrum, 1 +instance = comp, \Add0~12 , Add0~12, spectrum, 1 +instance = comp, \counter[6] , counter[6], spectrum, 1 +instance = comp, \Add0~14 , Add0~14, spectrum, 1 +instance = comp, \counter[7] , counter[7], spectrum, 1 +instance = comp, \Add0~16 , Add0~16, spectrum, 1 +instance = comp, \counter[8] , counter[8], spectrum, 1 +instance = comp, \Add0~18 , Add0~18, spectrum, 1 +instance = comp, \counter[9] , counter[9], spectrum, 1 +instance = comp, \Add0~20 , Add0~20, spectrum, 1 +instance = comp, \counter[10] , counter[10], spectrum, 1 +instance = comp, \Add0~22 , Add0~22, spectrum, 1 +instance = comp, \counter[11] , counter[11], spectrum, 1 +instance = comp, \Add0~24 , Add0~24, spectrum, 1 +instance = comp, \counter[12] , counter[12], spectrum, 1 +instance = comp, \Add0~26 , Add0~26, spectrum, 1 +instance = comp, \counter[13] , counter[13], spectrum, 1 +instance = comp, \Add0~28 , Add0~28, spectrum, 1 +instance = comp, \counter[14] , counter[14], spectrum, 1 +instance = comp, \Add0~30 , Add0~30, spectrum, 1 +instance = comp, \counter[15] , counter[15], spectrum, 1 +instance = comp, \Add0~32 , Add0~32, spectrum, 1 +instance = comp, \counter[16] , counter[16], spectrum, 1 +instance = comp, \Add0~34 , Add0~34, spectrum, 1 +instance = comp, \counter[17] , counter[17], spectrum, 1 +instance = comp, \Add0~36 , Add0~36, spectrum, 1 +instance = comp, \counter[18] , counter[18], spectrum, 1 +instance = comp, \Add0~38 , Add0~38, spectrum, 1 +instance = comp, \counter[19] , counter[19], spectrum, 1 +instance = comp, \Add0~40 , Add0~40, spectrum, 1 +instance = comp, \Equal0~5 , Equal0~5, spectrum, 1 +instance = comp, \Equal0~1 , Equal0~1, spectrum, 1 +instance = comp, \Equal0~0 , Equal0~0, spectrum, 1 +instance = comp, \Equal0~2 , Equal0~2, spectrum, 1 +instance = comp, \Equal0~3 , Equal0~3, spectrum, 1 +instance = comp, \Equal0~4 , Equal0~4, spectrum, 1 +instance = comp, \address[0]~0 , address[0]~0, spectrum, 1 +instance = comp, \address[0] , address[0], spectrum, 1 +instance = comp, \Equal0~6 , Equal0~6, spectrum, 1 +instance = comp, \Equal0~7 , Equal0~7, spectrum, 1 +instance = comp, \address[1]~1 , address[1]~1, spectrum, 1 +instance = comp, \address[1] , address[1], spectrum, 1 +instance = comp, \address[1]~2 , address[1]~2, spectrum, 1 +instance = comp, \address[2]~3 , address[2]~3, spectrum, 1 +instance = comp, \address[2] , address[2], spectrum, 1 +instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a0 , rom|altsyncram_component|auto_generated|ram_block1a0, spectrum, 1 diff --git a/simulation/modelsim/spectrum_v.sdo b/simulation/modelsim/spectrum_v.sdo index e97f726..7414a00 100644 --- a/simulation/modelsim/spectrum_v.sdo +++ b/simulation/modelsim/spectrum_v.sdo @@ -29,7 +29,7 @@ (DELAYFILE (SDFVERSION "2.1") (DESIGN "spectrum") - (DATE "03/30/2022 11:51:43") + (DATE "03/30/2022 12:38:42") (VENDOR "Altera") (PROGRAM "Quartus II 32-bit") (VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition") @@ -41,7 +41,7 @@ (INSTANCE LED\[0\]\~output) (DELAY (ABSOLUTE - (PORT i (513:513:513) (544:544:544)) + (PORT i (1355:1355:1355) (1339:1339:1339)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -51,7 +51,7 @@ (INSTANCE LED\[1\]\~output) (DELAY (ABSOLUTE - (PORT i (754:754:754) (771:771:771)) + (PORT i (1409:1409:1409) (1443:1443:1443)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -61,7 +61,7 @@ (INSTANCE LED\[2\]\~output) (DELAY (ABSOLUTE - (PORT i (734:734:734) (751:751:751)) + (PORT i (1823:1823:1823) (1829:1829:1829)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -71,7 +71,7 @@ (INSTANCE LED\[3\]\~output) (DELAY (ABSOLUTE - (PORT i (512:512:512) (543:543:543)) + (PORT i (1455:1455:1455) (1423:1423:1423)) (IOPATH i o (2535:2535:2535) (2445:2445:2445)) ) ) @@ -81,7 +81,7 @@ (INSTANCE LED\[4\]\~output) (DELAY (ABSOLUTE - (PORT i (2451:2451:2451) (2550:2550:2550)) + (PORT i (1759:1759:1759) (1776:1776:1776)) (IOPATH i o (2582:2582:2582) (2502:2502:2502)) ) ) @@ -91,7 +91,7 @@ (INSTANCE LED\[5\]\~output) (DELAY (ABSOLUTE - (PORT i (2441:2441:2441) (2543:2543:2543)) + (PORT i (1337:1337:1337) (1367:1367:1367)) (IOPATH i o (4477:4477:4477) (4127:4127:4127)) ) ) @@ -101,11 +101,21 @@ (INSTANCE LED\[6\]\~output) (DELAY (ABSOLUTE - (PORT i (1301:1301:1301) (1440:1440:1440)) + (PORT i (1855:1855:1855) (1871:1871:1871)) (IOPATH i o (2455:2455:2455) (2378:2378:2378)) ) ) ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE LED\[7\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1469:1469:1469) (1548:1548:1548)) + (IOPATH i o (4477:4477:4477) (4127:4127:4127)) + ) + ) + ) (CELL (CELLTYPE "cycloneive_io_ibuf") (INSTANCE CLOCK_50\~input) @@ -125,11 +135,28 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[0\]\~81) + (CELLTYPE "dffeas") + (INSTANCE counter\[20\]) (DELAY (ABSOLUTE - (IOPATH datac combout (353:353:353) (369:369:369)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) + (PORT d (74:74:74) (91:91:91)) + (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (157:157:157)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (330:330:330)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) + (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) @@ -138,7 +165,7 @@ (INSTANCE counter\[0\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -149,16 +176,15 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[1\]\~27) + (INSTANCE Add0\~2) (DELAY (ABSOLUTE - (PORT dataa (243:243:243) (329:329:329)) - (PORT datab (241:241:241) (323:323:323)) - (IOPATH dataa combout (339:339:339) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datab combout (344:344:344) (369:369:369)) + (PORT datab (242:242:242) (324:324:324)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) + (IOPATH cin combout (455:455:455) (437:437:437)) + (IOPATH cin cout (58:58:58) (58:58:58)) ) ) ) @@ -167,7 +193,7 @@ (INSTANCE counter\[1\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -178,11 +204,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[2\]\~29) + (INSTANCE Add0\~4) (DELAY (ABSOLUTE - (PORT datab (242:242:242) (323:323:323)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT datab (242:242:242) (324:324:324)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) @@ -195,7 +221,7 @@ (INSTANCE counter\[2\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -206,12 +232,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[3\]\~31) + (INSTANCE Add0\~6) (DELAY (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (242:242:242) (324:324:324)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -223,7 +249,7 @@ (INSTANCE counter\[3\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -234,11 +260,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[4\]\~33) + (INSTANCE Add0\~8) (DELAY (ABSOLUTE - (PORT dataa (244:244:244) (331:331:331)) - (IOPATH dataa combout (356:356:356) (368:368:368)) + (PORT dataa (386:386:386) (458:458:458)) + (IOPATH dataa combout (354:354:354) (367:367:367)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) @@ -251,7 +277,7 @@ (INSTANCE counter\[4\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -262,11 +288,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[5\]\~35) + (INSTANCE Add0\~10) (DELAY (ABSOLUTE - (PORT datab (242:242:242) (325:325:325)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT datab (380:380:380) (452:452:452)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) @@ -279,7 +305,7 @@ (INSTANCE counter\[5\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -290,12 +316,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[6\]\~37) + (INSTANCE Add0\~12) (DELAY (ABSOLUTE - (PORT datab (242:242:242) (325:325:325)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (386:386:386) (458:458:458)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -307,7 +333,7 @@ (INSTANCE counter\[6\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -318,11 +344,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[7\]\~39) + (INSTANCE Add0\~14) (DELAY (ABSOLUTE - (PORT datab (242:242:242) (325:325:325)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT datab (380:380:380) (450:450:450)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) @@ -335,7 +361,7 @@ (INSTANCE counter\[7\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -346,11 +372,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[8\]\~41) + (INSTANCE Add0\~16) (DELAY (ABSOLUTE - (PORT datab (242:242:242) (325:325:325)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT datab (240:240:240) (322:322:322)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) @@ -363,7 +389,7 @@ (INSTANCE counter\[8\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -374,11 +400,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[9\]\~43) + (INSTANCE Add0\~18) (DELAY (ABSOLUTE - (PORT dataa (244:244:244) (330:330:330)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (PORT dataa (242:242:242) (328:328:328)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) @@ -391,7 +417,7 @@ (INSTANCE counter\[9\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -402,11 +428,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[10\]\~45) + (INSTANCE Add0\~20) (DELAY (ABSOLUTE - (PORT datab (242:242:242) (323:323:323)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT datab (239:239:239) (321:321:321)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) @@ -419,7 +445,7 @@ (INSTANCE counter\[10\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -430,12 +456,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[11\]\~47) + (INSTANCE Add0\~22) (DELAY (ABSOLUTE - (PORT dataa (243:243:243) (329:329:329)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (388:388:388) (452:452:452)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -447,7 +473,7 @@ (INSTANCE counter\[11\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -458,11 +484,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[12\]\~49) + (INSTANCE Add0\~24) (DELAY (ABSOLUTE - (PORT datab (241:241:241) (323:323:323)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT datab (382:382:382) (451:451:451)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) @@ -475,7 +501,7 @@ (INSTANCE counter\[12\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -486,12 +512,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[13\]\~51) + (INSTANCE Add0\~26) (DELAY (ABSOLUTE - (PORT dataa (243:243:243) (329:329:329)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datab (387:387:387) (451:451:451)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -503,7 +529,7 @@ (INSTANCE counter\[13\]) (DELAY (ABSOLUTE - (PORT clk (1898:1898:1898) (1920:1920:1920)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -514,12 +540,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[14\]\~53) + (INSTANCE Add0\~28) (DELAY (ABSOLUTE - (PORT datab (240:240:240) (322:322:322)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (380:380:380) (458:458:458)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -531,7 +557,7 @@ (INSTANCE counter\[14\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -542,11 +568,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[15\]\~55) + (INSTANCE Add0\~30) (DELAY (ABSOLUTE - (PORT datab (241:241:241) (323:323:323)) - (IOPATH datab combout (355:355:355) (369:369:369)) + (PORT datab (387:387:387) (452:452:452)) + (IOPATH datab combout (365:365:365) (373:373:373)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) @@ -559,7 +585,7 @@ (INSTANCE counter\[15\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -570,11 +596,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[16\]\~57) + (INSTANCE Add0\~32) (DELAY (ABSOLUTE - (PORT datab (241:241:241) (323:323:323)) - (IOPATH datab combout (365:365:365) (373:373:373)) + (PORT datab (379:379:379) (454:454:454)) + (IOPATH datab combout (355:355:355) (369:369:369)) (IOPATH datab cout (446:446:446) (318:318:318)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) @@ -587,7 +613,7 @@ (INSTANCE counter\[16\]) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1545:1545:1545)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -598,11 +624,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[17\]\~59) + (INSTANCE Add0\~34) (DELAY (ABSOLUTE - (PORT dataa (244:244:244) (330:330:330)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (PORT dataa (388:388:388) (458:458:458)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) @@ -615,7 +641,7 @@ (INSTANCE counter\[17\]) (DELAY (ABSOLUTE - (PORT clk (1898:1898:1898) (1920:1920:1920)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -626,12 +652,12 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[18\]\~61) + (INSTANCE Add0\~36) (DELAY (ABSOLUTE - (PORT datab (243:243:243) (324:324:324)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (386:386:386) (458:458:458)) + (IOPATH dataa combout (354:354:354) (367:367:367)) + (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) (IOPATH cin cout (58:58:58) (58:58:58)) @@ -643,7 +669,7 @@ (INSTANCE counter\[18\]) (DELAY (ABSOLUTE - (PORT clk (1898:1898:1898) (1920:1920:1920)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -654,11 +680,11 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[19\]\~63) + (INSTANCE Add0\~38) (DELAY (ABSOLUTE - (PORT dataa (245:245:245) (333:333:333)) - (IOPATH dataa combout (354:354:354) (367:367:367)) + (PORT dataa (383:383:383) (460:460:460)) + (IOPATH dataa combout (356:356:356) (368:368:368)) (IOPATH dataa cout (436:436:436) (315:315:315)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) @@ -671,7 +697,7 @@ (INSTANCE counter\[19\]) (DELAY (ABSOLUTE - (PORT clk (1898:1898:1898) (1920:1920:1920)) + (PORT clk (1531:1531:1531) (1544:1544:1544)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -682,128 +708,132 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[20\]\~65) + (INSTANCE Add0\~40) (DELAY (ABSOLUTE - (PORT dataa (245:245:245) (332:332:332)) - (IOPATH dataa combout (356:356:356) (368:368:368)) - (IOPATH dataa cout (436:436:436) (315:315:315)) + (PORT datad (218:218:218) (287:287:287)) (IOPATH datad combout (130:130:130) (120:120:120)) (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[20\]) - (DELAY - (ABSOLUTE - (PORT clk (1898:1898:1898) (1920:1920:1920)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[21\]\~67) + (INSTANCE Equal0\~5) (DELAY (ABSOLUTE - (PORT datab (264:264:264) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (210:210:210) (257:257:257)) + (PORT datab (208:208:208) (249:249:249)) + (PORT datac (181:181:181) (219:219:219)) + (PORT datad (181:181:181) (209:209:209)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[21\]) - (DELAY - (ABSOLUTE - (PORT clk (1898:1898:1898) (1920:1920:1920)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE LED\[0\]\~reg0feeder) + (INSTANCE Equal0\~1) (DELAY (ABSOLUTE - (PORT datac (411:411:411) (472:472:472)) - (IOPATH datac combout (243:243:243) (242:242:242)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE LED\[0\]\~reg0) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[22\]\~69) - (DELAY - (ABSOLUTE - (PORT datab (264:264:264) (347:347:347)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (201:201:201) (245:245:245)) + (PORT datab (199:199:199) (238:238:238)) + (PORT datac (173:173:173) (206:206:206)) + (PORT datad (174:174:174) (200:200:200)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[22\]) - (DELAY - (ABSOLUTE - (PORT clk (1898:1898:1898) (1920:1920:1920)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE LED\[1\]\~reg0feeder) + (INSTANCE Equal0\~0) (DELAY (ABSOLUTE - (PORT datad (808:808:808) (843:843:843)) + (PORT dataa (343:343:343) (371:371:371)) + (PORT datab (336:336:336) (366:366:366)) + (PORT datac (312:312:312) (338:338:338)) + (PORT datad (318:318:318) (328:328:328)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (375:375:375) (396:396:396)) + (PORT datab (637:637:637) (652:652:652)) + (PORT datac (334:334:334) (353:353:353)) + (PORT datad (562:562:562) (570:570:570)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (247:247:247)) + (PORT datab (201:201:201) (241:241:241)) + (PORT datac (174:174:174) (208:208:208)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH dataa combout (350:350:350) (366:366:366)) + (IOPATH datab combout (350:350:350) (368:368:368)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (612:612:612) (640:640:640)) + (PORT datab (820:820:820) (843:843:843)) + (PORT datac (170:170:170) (203:203:203)) + (PORT datad (305:305:305) (321:321:321)) + (IOPATH dataa combout (300:300:300) (307:307:307)) + (IOPATH datab combout (300:300:300) (308:308:308)) + (IOPATH datac combout (241:241:241) (242:242:242)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (601:601:601) (619:619:619)) + (PORT datab (378:378:378) (401:401:401)) + (PORT datad (189:189:189) (221:221:221)) + (IOPATH dataa combout (325:325:325) (320:320:320)) + (IOPATH datab combout (304:304:304) (308:308:308)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE LED\[1\]\~reg0) + (INSTANCE address\[0\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1550:1550:1550)) + (PORT clk (1897:1897:1897) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -814,48 +844,53 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[23\]\~71) + (INSTANCE Equal0\~6) (DELAY (ABSOLUTE - (PORT datab (264:264:264) (347:347:347)) - (IOPATH datab combout (355:355:355) (369:369:369)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT datac (181:181:181) (219:219:219)) + (PORT datad (183:183:183) (214:214:214)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[23\]) - (DELAY - (ABSOLUTE - (PORT clk (1898:1898:1898) (1920:1920:1920)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE LED\[2\]\~reg0feeder) + (INSTANCE Equal0\~7) (DELAY (ABSOLUTE - (PORT datad (771:771:771) (813:813:813)) + (PORT dataa (364:364:364) (391:391:391)) + (PORT datab (207:207:207) (248:248:248)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (181:181:181) (208:208:208)) + (IOPATH dataa combout (337:337:337) (338:338:338)) + (IOPATH datab combout (337:337:337) (348:348:348)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE address\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (595:595:595) (669:669:669)) + (PORT datab (216:216:216) (261:261:261)) + (PORT datad (332:332:332) (350:350:350)) + (IOPATH dataa combout (324:324:324) (328:328:328)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE LED\[2\]\~reg0) + (INSTANCE address\[1\]) (DELAY (ABSOLUTE - (PORT clk (1538:1538:1538) (1550:1550:1550)) + (PORT clk (1897:1897:1897) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -866,48 +901,39 @@ ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[24\]\~73) + (INSTANCE address\[1\]\~2) (DELAY (ABSOLUTE - (PORT datab (264:264:264) (347:347:347)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) + (PORT dataa (597:597:597) (670:670:670)) + (PORT datab (381:381:381) (404:404:404)) + (PORT datac (574:574:574) (583:583:583)) + (PORT datad (191:191:191) (224:224:224)) + (IOPATH dataa combout (300:300:300) (308:308:308)) + (IOPATH datab combout (300:300:300) (311:311:311)) + (IOPATH datac combout (241:241:241) (241:241:241)) (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) ) ) ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[24\]) - (DELAY - (ABSOLUTE - (PORT clk (1898:1898:1898) (1920:1920:1920)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) (CELL (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE LED\[3\]\~reg0feeder) + (INSTANCE address\[2\]\~3) (DELAY (ABSOLUTE - (PORT datad (399:399:399) (452:452:452)) + (PORT datab (398:398:398) (468:468:468)) + (PORT datad (175:175:175) (201:201:201)) + (IOPATH datab combout (333:333:333) (332:332:332)) + (IOPATH datac combout (353:353:353) (369:369:369)) (IOPATH datad combout (130:130:130) (120:120:120)) ) ) ) (CELL (CELLTYPE "dffeas") - (INSTANCE LED\[3\]\~reg0) + (INSTANCE address\[2\]) (DELAY (ABSOLUTE - (PORT clk (1533:1533:1533) (1545:1545:1545)) + (PORT clk (1897:1897:1897) (1919:1919:1919)) (PORT d (74:74:74) (91:91:91)) (IOPATH (posedge clk) q (199:199:199) (199:199:199)) ) @@ -917,156 +943,89 @@ ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[25\]\~75) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) (DELAY (ABSOLUTE - (PORT dataa (266:266:266) (352:352:352)) - (IOPATH dataa combout (354:354:354) (367:367:367)) - (IOPATH dataa cout (436:436:436) (315:315:315)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[25\]) - (DELAY - (ABSOLUTE - (PORT clk (1898:1898:1898) (1920:1920:1920)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (PORT d[0] (1263:1263:1263) (1361:1361:1361)) + (PORT d[1] (1538:1538:1538) (1608:1608:1608)) + (PORT d[2] (1534:1534:1534) (1635:1635:1635)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (HOLD d (posedge clk) (187:187:187)) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE LED\[4\]\~reg0feeder) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) (DELAY (ABSOLUTE - (PORT datad (404:404:404) (467:467:467)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT clk (1857:1857:1857) (1884:1884:1884)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE LED\[4\]\~reg0) + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (PORT clk (1858:1858:1858) (1885:1885:1885)) + (IOPATH (posedge clk) pulse (0:0:0) (2390:2390:2390)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1820:1820:1820) (1847:1847:1847)) + (IOPATH (posedge clk) q (301:301:301) (301:301:301)) ) ) (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) + (SETUP d (posedge clk) (51:51:51)) + (HOLD d (posedge clk) (159:159:159)) ) ) (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[26\]\~77) + (CELLTYPE "cycloneive_ram_register") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) (DELAY (ABSOLUTE - (PORT datab (263:263:263) (345:345:345)) - (IOPATH datab combout (365:365:365) (373:373:373)) - (IOPATH datab cout (446:446:446) (318:318:318)) - (IOPATH datad combout (130:130:130) (120:120:120)) - (IOPATH cin combout (455:455:455) (437:437:437)) - (IOPATH cin cout (58:58:58) (58:58:58)) + (PORT clk (1005:1005:1005) (1010:1010:1010)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[26\]) + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) (DELAY (ABSOLUTE - (PORT clk (1898:1898:1898) (1920:1920:1920)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE LED\[5\]\~reg0feeder) - (DELAY - (ABSOLUTE - (PORT datad (610:610:610) (670:670:670)) - (IOPATH datad combout (130:130:130) (120:120:120)) + (PORT clk (1006:1006:1006) (1011:1011:1011)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE LED\[5\]\~reg0) + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) (DELAY (ABSOLUTE - (PORT clk (1532:1532:1532) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE counter\[27\]\~79) - (DELAY - (ABSOLUTE - (PORT dataa (266:266:266) (353:353:353)) - (IOPATH dataa combout (371:371:371) (376:376:376)) - (IOPATH cin combout (455:455:455) (437:437:437)) + (PORT clk (1006:1006:1006) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) ) (CELL - (CELLTYPE "dffeas") - (INSTANCE counter\[27\]) + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE rom\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) (DELAY (ABSOLUTE - (PORT clk (1898:1898:1898) (1920:1920:1920)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) + (PORT clk (1006:1006:1006) (1011:1011:1011)) + (IOPATH (posedge clk) pulse (0:0:0) (2649:2649:2649)) ) ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) - ) - (CELL - (CELLTYPE "cycloneive_lcell_comb") - (INSTANCE LED\[6\]\~reg0feeder) - (DELAY - (ABSOLUTE - (PORT datad (406:406:406) (467:467:467)) - (IOPATH datad combout (130:130:130) (120:120:120)) - ) - ) - ) - (CELL - (CELLTYPE "dffeas") - (INSTANCE LED\[6\]\~reg0) - (DELAY - (ABSOLUTE - (PORT clk (1532:1532:1532) (1544:1544:1544)) - (PORT d (74:74:74) (91:91:91)) - (IOPATH (posedge clk) q (199:199:199) (199:199:199)) - ) - ) - (TIMINGCHECK - (HOLD d (posedge clk) (157:157:157)) - ) ) ) diff --git a/spectrum.qsf b/spectrum.qsf index f25459a..6f18c4a 100644 --- a/spectrum.qsf +++ b/spectrum.qsf @@ -407,4 +407,7 @@ set_location_assignment PIN_J14 -to GPIO_1[33] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[33] set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" +set_global_assignment -name MIF_FILE output_files/led_patterns.mif +set_global_assignment -name MIF_FILE led_patterns.mif +set_global_assignment -name QIP_FILE rom0.qip set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/spectrum.v b/spectrum.v index 482ac9a..50dc56a 100644 --- a/spectrum.v +++ b/spectrum.v @@ -1,14 +1,24 @@ module spectrum( input CLOCK_50, - output reg[7:0] LED + output wire[7:0] LED ); -reg[27:0] counter; +reg[2:0] address; +wire[7:0] mem_data; + +rom0 rom( + .address(address), + .clock(CLOCK_50), + .q(mem_data) +); +reg[20:0] counter; always @(posedge CLOCK_50) begin - counter <= counter + 1; - LED <= counter[27:21]; + counter = counter + 1; + if (counter == 0) + address = address + 1; end +assign LED = mem_data; endmodule \ No newline at end of file