24 lines
327 B
Verilog
24 lines
327 B
Verilog
module spectrum(
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input CLOCK_50,
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output wire[7:0] LED
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);
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reg[2:0] address;
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wire[7:0] mem_data;
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rom0 rom(
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.address(address),
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.clock(CLOCK_50),
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.q(mem_data)
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);
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reg[20:0] counter;
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always @(posedge CLOCK_50)
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begin
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counter = counter + 1;
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if (counter == 0)
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address = address + 1;
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end
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assign LED = mem_data;
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endmodule |