Analysis & Synthesis report for spectrum Wed Mar 30 11:51:29 2022 Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Analysis & Synthesis Summary 3. Analysis & Synthesis Settings 4. Parallel Compilation 5. Analysis & Synthesis Source Files Read 6. Analysis & Synthesis Resource Usage Summary 7. Analysis & Synthesis Resource Utilization by Entity 8. Registers Removed During Synthesis 9. General Register Statistics 10. Elapsed Time Per Partition 11. Analysis & Synthesis Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. +---------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +------------------------------------+--------------------------------------------+ ; Analysis & Synthesis Status ; Successful - Wed Mar 30 11:51:29 2022 ; ; Quartus II 32-bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ; ; Revision Name ; spectrum ; ; Top-level Entity Name ; spectrum ; ; Family ; Cyclone IV E ; ; Total logic elements ; 35 ; ; Total combinational functions ; 28 ; ; Dedicated logic registers ; 35 ; ; Total registers ; 35 ; ; Total pins ; 9 ; ; Total virtual pins ; 0 ; ; Total memory bits ; 0 ; ; Embedded Multiplier 9-bit elements ; 0 ; ; Total PLLs ; 0 ; +------------------------------------+--------------------------------------------+ +--------------------------------------------------------------------------------+ ; Analysis & Synthesis Settings ; +--------------------------------------------------------------------------------+ Option : Device Setting : EP4CE22F17C6 Default Value : Option : Top-level entity name Setting : spectrum Default Value : spectrum Option : Family name Setting : Cyclone IV E Default Value : Cyclone IV GX Option : Use smart compilation Setting : Off Default Value : Off Option : Enable parallel Assembler and TimeQuest Timing Analyzer during compilation Setting : On Default Value : On Option : Enable compact report table Setting : Off Default Value : Off Option : Restructure Multiplexers Setting : Auto Default Value : Auto Option : Create Debugging Nodes for IP Cores Setting : Off Default Value : Off Option : Preserve fewer node names Setting : On Default Value : On Option : Disable OpenCore Plus hardware evaluation Setting : Off Default Value : Off Option : Verilog Version Setting : Verilog_2001 Default Value : Verilog_2001 Option : VHDL Version Setting : VHDL_1993 Default Value : VHDL_1993 Option : State Machine Processing Setting : Auto Default Value : Auto Option : Safe State Machine Setting : Off Default Value : Off Option : Extract Verilog State Machines Setting : On Default Value : On Option : Extract VHDL State Machines Setting : On Default Value : On Option : Ignore Verilog initial constructs Setting : Off Default Value : Off Option : Iteration limit for constant Verilog loops Setting : 5000 Default Value : 5000 Option : Iteration limit for non-constant Verilog loops Setting : 250 Default Value : 250 Option : Add Pass-Through Logic to Inferred RAMs Setting : On Default Value : On Option : Infer RAMs from Raw Logic Setting : On Default Value : On Option : Parallel Synthesis Setting : On Default Value : On Option : DSP Block Balancing Setting : Auto Default Value : Auto Option : NOT Gate Push-Back Setting : On Default Value : On Option : Power-Up Don't Care Setting : On Default Value : On Option : Remove Redundant Logic Cells Setting : Off Default Value : Off Option : Remove Duplicate Registers Setting : On Default Value : On Option : Ignore CARRY Buffers Setting : Off Default Value : Off Option : Ignore CASCADE Buffers Setting : Off Default Value : Off Option : Ignore GLOBAL Buffers Setting : Off Default Value : Off Option : Ignore ROW GLOBAL Buffers Setting : Off Default Value : Off Option : Ignore LCELL Buffers Setting : Off Default Value : Off Option : Ignore SOFT Buffers Setting : On Default Value : On Option : Limit AHDL Integers to 32 Bits Setting : Off Default Value : Off Option : Optimization Technique Setting : Balanced Default Value : Balanced Option : Carry Chain Length Setting : 70 Default Value : 70 Option : Auto Carry Chains Setting : On Default Value : On Option : Auto Open-Drain Pins Setting : On Default Value : On Option : Perform WYSIWYG Primitive Resynthesis Setting : Off Default Value : Off Option : Auto ROM Replacement Setting : On Default Value : On Option : Auto RAM Replacement Setting : On Default Value : On Option : Auto DSP Block Replacement Setting : On Default Value : On Option : Auto Shift Register Replacement Setting : Auto Default Value : Auto Option : Allow Shift Register Merging across Hierarchies Setting : Auto Default Value : Auto Option : Auto Clock Enable Replacement Setting : On Default Value : On Option : Strict RAM Replacement Setting : Off Default Value : Off Option : Allow Synchronous Control Signals Setting : On Default Value : On Option : Force Use of Synchronous Clear Signals Setting : Off Default Value : Off Option : Auto RAM Block Balancing Setting : On Default Value : On Option : Auto RAM to Logic Cell Conversion Setting : Off Default Value : Off Option : Auto Resource Sharing Setting : Off Default Value : Off Option : Allow Any RAM Size For Recognition Setting : Off Default Value : Off Option : Allow Any ROM Size For Recognition Setting : Off Default Value : Off Option : Allow Any Shift Register Size For Recognition Setting : Off Default Value : Off Option : Use LogicLock Constraints during Resource Balancing Setting : On Default Value : On Option : Ignore translate_off and synthesis_off directives Setting : Off Default Value : Off Option : Timing-Driven Synthesis Setting : On Default Value : On Option : Report Parameter Settings Setting : On Default Value : On Option : Report Source Assignments Setting : On Default Value : On Option : Report Connectivity Checks Setting : On Default Value : On Option : Ignore Maximum Fan-Out Assignments Setting : Off Default Value : Off Option : Synchronization Register Chain Length Setting : 2 Default Value : 2 Option : PowerPlay Power Optimization Setting : Normal compilation Default Value : Normal compilation Option : HDL message level Setting : Level2 Default Value : Level2 Option : Suppress Register Optimization Related Messages Setting : Off Default Value : Off Option : Number of Removed Registers Reported in Synthesis Report Setting : 5000 Default Value : 5000 Option : Number of Swept Nodes Reported in Synthesis Report Setting : 5000 Default Value : 5000 Option : Number of Inverted Registers Reported in Synthesis Report Setting : 100 Default Value : 100 Option : Clock MUX Protection Setting : On Default Value : On Option : Auto Gated Clock Conversion Setting : Off Default Value : Off Option : Block Design Naming Setting : Auto Default Value : Auto Option : SDC constraint protection Setting : Off Default Value : Off Option : Synthesis Effort Setting : Auto Default Value : Auto Option : Shift Register Replacement - Allow Asynchronous Clear Signal Setting : On Default Value : On Option : Pre-Mapping Resynthesis Optimization Setting : Off Default Value : Off Option : Analysis & Synthesis Message Level Setting : Medium Default Value : Medium Option : Disable Register Merging Across Hierarchies Setting : Auto Default Value : Auto Option : Resource Aware Inference For Block RAM Setting : On Default Value : On Option : Synthesis Seed Setting : 1 Default Value : 1 +--------------------------------------------------------------------------------+ Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. +-------------------------------------+ ; Parallel Compilation ; +----------------------------+--------+ ; Processors ; Number ; +----------------------------+--------+ ; Number detected on machine ; 12 ; ; Maximum allowed ; 1 ; +----------------------------+--------+ +--------------------------------------------------------------------------------+ ; Analysis & Synthesis Source Files Read ; +--------------------------------------------------------------------------------+ File Name with User-Entered Path : spectrum.v Used in Netlist : yes File Type : User Verilog HDL File File Name with Absolute Path : /home/benny/work/fpga/projects/spectrum.v Library : +--------------------------------------------------------------------------------+ +--------------------------------------------------------------+ ; Analysis & Synthesis Resource Usage Summary ; +---------------------------------------------+----------------+ ; Resource ; Usage ; +---------------------------------------------+----------------+ ; Estimated Total logic elements ; 35 ; ; ; ; ; Total combinational functions ; 28 ; ; Logic element usage by number of LUT inputs ; ; ; -- 4 input functions ; 0 ; ; -- 3 input functions ; 1 ; ; -- <=2 input functions ; 27 ; ; ; ; ; Logic elements by mode ; ; ; -- normal mode ; 2 ; ; -- arithmetic mode ; 26 ; ; ; ; ; Total registers ; 35 ; ; -- Dedicated logic registers ; 35 ; ; -- I/O registers ; 0 ; ; ; ; ; I/O pins ; 9 ; ; Embedded Multiplier 9-bit elements ; 0 ; ; Maximum fan-out node ; CLOCK_50~input ; ; Maximum fan-out ; 35 ; ; Total fan-out ; 141 ; ; Average fan-out ; 1.74 ; +---------------------------------------------+----------------+ +--------------------------------------------------------------------------------+ ; Analysis & Synthesis Resource Utilization by Entity ; +--------------------------------------------------------------------------------+ Compilation Hierarchy Node : |spectrum LC Combinationals : 28 (28) LC Registers : 35 (35) Memory Bits : 0 DSP Elements : 0 DSP 9x9 : 0 DSP 18x18 : 0 Pins : 9 Virtual Pins : 0 Full Hierarchy Name : |spectrum Library Name : work +--------------------------------------------------------------------------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. +--------------------------------------------------------------------------------+ ; Registers Removed During Synthesis ; +---------------------------------------+----------------------------------------+ ; Register name ; Reason for Removal ; +---------------------------------------+----------------------------------------+ ; LED[7]~reg0 ; Stuck at GND due to stuck port data_in ; ; Total Number of Removed Registers = 1 ; ; +---------------------------------------+----------------------------------------+ +------------------------------------------------------+ ; General Register Statistics ; +----------------------------------------------+-------+ ; Statistic ; Value ; +----------------------------------------------+-------+ ; Total registers ; 35 ; ; Number of registers using Synchronous Clear ; 0 ; ; Number of registers using Synchronous Load ; 0 ; ; Number of registers using Asynchronous Clear ; 0 ; ; Number of registers using Asynchronous Load ; 0 ; ; Number of registers using Clock Enable ; 0 ; ; Number of registers using Preset ; 0 ; +----------------------------------------------+-------+ +-------------------------------+ ; Elapsed Time Per Partition ; +----------------+--------------+ ; Partition Name ; Elapsed Time ; +----------------+--------------+ ; Top ; 00:00:00 ; +----------------+--------------+ +-------------------------------+ ; Analysis & Synthesis Messages ; +-------------------------------+ Info: ******************************************************************* Info: Running Quartus II 32-bit Analysis & Synthesis Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition Info: Processing started: Wed Mar 30 11:51:28 2022 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off spectrum -c spectrum Warning (20028): Parallel compilation is not licensed and has been disabled Info (12021): Found 1 design units, including 1 entities, in source file spectrum.v Info (12023): Found entity 1: spectrum Info (12127): Elaborating entity "spectrum" for the top level hierarchy Warning (10230): Verilog HDL assignment warning at spectrum.v(10): truncated value with size 32 to match size of target (28) Warning (13024): Output pins are stuck at VCC or GND Warning (13410): Pin "LED[7]" is stuck at GND Info (286030): Timing-Driven Synthesis is running Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL Info (21057): Implemented 44 device resources after synthesis - the final resource count might be different Info (21058): Implemented 1 input pins Info (21059): Implemented 8 output pins Info (21061): Implemented 35 logic cells Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 4 warnings Info: Peak virtual memory: 388 megabytes Info: Processing ended: Wed Mar 30 11:51:29 2022 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01