59653 lines
2.6 MiB
Plaintext
59653 lines
2.6 MiB
Plaintext
// Copyright (C) 1991-2013 Altera Corporation
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// Your use of Altera Corporation's design tools, logic functions
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// and other software and tools, and its AMPP partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License
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// Subscription Agreement, Altera MegaCore Function License
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// Agreement, or other applicable license agreement, including,
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// without limitation, that your use is for the sole purpose of
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// programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the
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// applicable agreement for further details.
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// VENDOR "Altera"
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// PROGRAM "Quartus II 32-bit"
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// VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
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// DATE "04/02/2022 15:53:44"
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//
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// Device: Altera EP4CE22F17C6 Package FBGA256
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//
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//
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// This Verilog file should be used for ModelSim-Altera (Verilog) only
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//
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`timescale 1 ps/ 1 ps
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module spectrum (
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LED,
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CLOCK_50,
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KEY,
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PS2_CLK,
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PS2_DAT,
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I2C_SCLK,
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I2C_SDAT,
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AUD_XCK,
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AUD_ADCLRCK,
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AUD_DACLRCK,
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AUD_BCLK,
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AUD_DACDAT,
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AUD_ADCDAT,
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VGA_R,
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VGA_G,
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VGA_B,
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VGA_HS,
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VGA_VS,
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SW,
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GPIO_1,
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buzzer_out,
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raw_loader_in);
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output [7:0] LED;
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input CLOCK_50;
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input [1:0] KEY;
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input PS2_CLK;
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input PS2_DAT;
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inout I2C_SCLK;
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inout I2C_SDAT;
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output AUD_XCK;
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output AUD_ADCLRCK;
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output AUD_DACLRCK;
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output AUD_BCLK;
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output AUD_DACDAT;
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input AUD_ADCDAT;
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output [3:0] VGA_R;
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output [3:0] VGA_G;
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output [3:0] VGA_B;
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output VGA_HS;
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output VGA_VS;
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input [3:0] SW;
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output [33:0] GPIO_1;
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output buzzer_out;
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input raw_loader_in;
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// Design Ports Information
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// LED[0] => Location: PIN_A15, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// LED[1] => Location: PIN_A13, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// LED[2] => Location: PIN_B13, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// LED[3] => Location: PIN_A11, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// LED[4] => Location: PIN_D1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// LED[5] => Location: PIN_F3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// LED[6] => Location: PIN_B1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// LED[7] => Location: PIN_L3, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// AUD_XCK => Location: PIN_A7, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// AUD_ADCLRCK => Location: PIN_E7, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// AUD_DACLRCK => Location: PIN_C6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// AUD_BCLK => Location: PIN_E6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// AUD_DACDAT => Location: PIN_C8, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// VGA_R[0] => Location: PIN_E8, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// VGA_R[1] => Location: PIN_F8, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// VGA_R[2] => Location: PIN_F9, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// VGA_R[3] => Location: PIN_E9, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// VGA_G[0] => Location: PIN_C9, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// VGA_G[1] => Location: PIN_D9, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// VGA_G[2] => Location: PIN_E11, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// VGA_G[3] => Location: PIN_E10, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// VGA_B[0] => Location: PIN_C11, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// VGA_B[1] => Location: PIN_B11, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// VGA_B[2] => Location: PIN_A12, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// VGA_B[3] => Location: PIN_D11, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// VGA_HS => Location: PIN_D12, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// VGA_VS => Location: PIN_B12, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// SW[0] => Location: PIN_M1, I/O Standard: 3.3-V LVTTL, Current Strength: Default
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// SW[3] => Location: PIN_M15, I/O Standard: 3.3-V LVTTL, Current Strength: Default
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// GPIO_1[0] => Location: PIN_F13, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// GPIO_1[1] => Location: PIN_T15, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// GPIO_1[2] => Location: PIN_T14, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// GPIO_1[3] => Location: PIN_T13, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// GPIO_1[4] => Location: PIN_R13, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// GPIO_1[5] => Location: PIN_T12, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// GPIO_1[6] => Location: PIN_R12, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// GPIO_1[7] => Location: PIN_T11, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// GPIO_1[8] => Location: PIN_T10, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// GPIO_1[9] => Location: PIN_R11, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// GPIO_1[10] => Location: PIN_P11, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// GPIO_1[11] => Location: PIN_R10, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// GPIO_1[12] => Location: PIN_N12, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// GPIO_1[13] => Location: PIN_P9, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// GPIO_1[14] => Location: PIN_N9, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// GPIO_1[15] => Location: PIN_N11, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// GPIO_1[16] => Location: PIN_L16, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// GPIO_1[17] => Location: PIN_K16, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// GPIO_1[18] => Location: PIN_R16, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// GPIO_1[19] => Location: PIN_L15, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// GPIO_1[20] => Location: PIN_P15, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// GPIO_1[21] => Location: PIN_P16, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// GPIO_1[22] => Location: PIN_R14, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// GPIO_1[23] => Location: PIN_N16, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// GPIO_1[24] => Location: PIN_N15, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// GPIO_1[25] => Location: PIN_P14, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// GPIO_1[26] => Location: PIN_L14, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// GPIO_1[27] => Location: PIN_N14, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// GPIO_1[28] => Location: PIN_M10, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// GPIO_1[29] => Location: PIN_L13, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// GPIO_1[30] => Location: PIN_J16, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// GPIO_1[31] => Location: PIN_K15, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// GPIO_1[32] => Location: PIN_J13, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// GPIO_1[33] => Location: PIN_J14, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// buzzer_out => Location: PIN_A6, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// I2C_SCLK => Location: PIN_F2, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// I2C_SDAT => Location: PIN_F1, I/O Standard: 3.3-V LVTTL, Current Strength: 8mA
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// SW[1] => Location: PIN_T8, I/O Standard: 3.3-V LVTTL, Current Strength: Default
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// SW[2] => Location: PIN_B9, I/O Standard: 3.3-V LVTTL, Current Strength: Default
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// raw_loader_in => Location: PIN_B6, I/O Standard: 3.3-V LVTTL, Current Strength: Default
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// KEY[0] => Location: PIN_J15, I/O Standard: 3.3-V LVTTL, Current Strength: Default
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// CLOCK_50 => Location: PIN_R8, I/O Standard: 3.3-V LVTTL, Current Strength: Default
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// PS2_DAT => Location: PIN_B7, I/O Standard: 3.3-V LVTTL, Current Strength: Default
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// KEY[1] => Location: PIN_E1, I/O Standard: 3.3-V LVTTL, Current Strength: Default
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// PS2_CLK => Location: PIN_D6, I/O Standard: 3.3-V LVTTL, Current Strength: Default
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// AUD_ADCDAT => Location: PIN_D8, I/O Standard: 3.3-V LVTTL, Current Strength: Default
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wire gnd;
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wire vcc;
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wire unknown;
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assign gnd = 1'b0;
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assign vcc = 1'b1;
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assign unknown = 1'bx;
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tri1 devclrn;
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tri1 devpor;
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tri1 devoe;
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// synopsys translate_off
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initial $sdf_annotate("spectrum_v.sdo");
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// synopsys translate_on
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wire \SW[0]~input_o ;
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wire \SW[3]~input_o ;
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wire \I2C_SCLK~input_o ;
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wire \CLOCK_50~input_o ;
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wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_fbout ;
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wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ;
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wire \ula_|clocks_|counter[0]~0_combout ;
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wire \SW[2]~input_o ;
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wire \ula_|clocks_|clk_cpu~0_combout ;
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wire \ula_|clocks_|clk_cpu~q ;
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wire \ula_|clocks_|clk_cpu~clkctrl_outclk ;
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wire \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ;
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wire \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ;
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wire \KEY[1]~input_o ;
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wire \z80_|interrupts_|nmi_armed~feeder_combout ;
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wire \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ;
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wire \z80_|interrupts_|nmi_armed~q ;
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wire \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ;
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wire \z80_|sequencer_|DFFE_M2_ff~0_combout ;
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wire \z80_|sequencer_|DFFE_M2_ff~q ;
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wire \z80_|sequencer_|DFFE_M3_ff~0_combout ;
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wire \z80_|sequencer_|DFFE_M3_ff~q ;
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wire \z80_|sequencer_|DFFE_M4_ff~0_combout ;
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wire \z80_|sequencer_|DFFE_M4_ff~q ;
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wire \z80_|sequencer_|M5~0_combout ;
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wire \z80_|sequencer_|M5~q ;
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wire \z80_|execute_|ixy_d~5_combout ;
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wire \z80_|execute_|ctl_alu_op_low~22_combout ;
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wire \z80_|resets_|SYNTHESIZED_WIRE_11~combout ;
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wire \z80_|execute_|ctl_ir_we~4_combout ;
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wire \z80_|execute_|ctl_state_iy_set~2_combout ;
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wire \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ;
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wire \z80_|sequencer_|DFFE_T5_ff~q ;
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wire \z80_|execute_|ctl_state_ixiy_we~2_combout ;
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wire \z80_|decode_state_|DFFE_instIY1~q ;
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wire \z80_|decode_state_|use_ixiy~combout ;
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wire \z80_|execute_|ixy_d~4_combout ;
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wire \z80_|execute_|ixy_d~11_combout ;
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wire \z80_|execute_|ixy_d~9_combout ;
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wire \z80_|execute_|ixy_d~7_combout ;
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wire \z80_|execute_|ixy_d~6_combout ;
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wire \z80_|execute_|ixy_d~8_combout ;
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wire \z80_|execute_|ixy_d~12_combout ;
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wire \z80_|pla_decode_|Equal33~0_combout ;
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wire \z80_|pla_decode_|Equal33~1_combout ;
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wire \z80_|pla_decode_|Equal33~2_combout ;
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wire \z80_|pla_decode_|Equal21~0_combout ;
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wire \z80_|pla_decode_|Equal77~0_combout ;
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wire \z80_|pla_decode_|Equal77~1_combout ;
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wire \z80_|pla_decode_|Equal1~7_combout ;
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wire \z80_|pla_decode_|Equal79~0_combout ;
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wire \z80_|interrupts_|iff1~0_combout ;
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wire \z80_|interrupts_|DFFE_instIFF2~0_combout ;
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wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ;
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wire \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ;
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wire \z80_|interrupts_|DFFE_instIFF2~q ;
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wire \z80_|pla_decode_|Equal13~0_combout ;
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wire \z80_|pla_decode_|Equal38~2_combout ;
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wire \z80_|interrupts_|iff1~1_combout ;
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wire \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ;
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wire \z80_|interrupts_|iff1~q ;
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wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ;
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wire \ula_|video_|Add0~0_combout ;
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wire \ula_|video_|vga_hc~3_combout ;
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wire \ula_|video_|Add0~1 ;
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wire \ula_|video_|Add0~2_combout ;
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wire \ula_|video_|Add0~3 ;
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wire \ula_|video_|Add0~4_combout ;
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wire \ula_|video_|Add0~5 ;
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wire \ula_|video_|Add0~6_combout ;
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wire \ula_|video_|Add0~7 ;
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wire \ula_|video_|Add0~8_combout ;
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wire \ula_|video_|Add0~9 ;
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wire \ula_|video_|Add0~10_combout ;
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wire \ula_|video_|vga_hc~0_combout ;
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wire \ula_|video_|Add0~11 ;
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wire \ula_|video_|Add0~12_combout ;
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wire \ula_|video_|Add0~13 ;
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wire \ula_|video_|Add0~14_combout ;
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wire \ula_|video_|Add0~15 ;
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wire \ula_|video_|Add0~16_combout ;
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wire \ula_|video_|vga_hc~2_combout ;
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wire \ula_|video_|Add0~17 ;
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wire \ula_|video_|Add0~18_combout ;
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wire \ula_|video_|vga_hc~1_combout ;
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wire \ula_|video_|Equal0~0_combout ;
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wire \ula_|video_|Equal0~1_combout ;
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wire \ula_|video_|Equal1~0_combout ;
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wire \ula_|video_|Add1~0_combout ;
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wire \ula_|video_|vga_vc[0]~0_combout ;
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wire \ula_|video_|Add1~1 ;
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wire \ula_|video_|Add1~2_combout ;
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wire \ula_|video_|vga_vc[1]~1_combout ;
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wire \ula_|video_|Add1~3 ;
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wire \ula_|video_|Add1~4_combout ;
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wire \ula_|video_|vga_vc[2]~2_combout ;
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wire \ula_|video_|vga_vc[2]~feeder_combout ;
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wire \ula_|video_|Add1~5 ;
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wire \ula_|video_|Add1~6_combout ;
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wire \ula_|video_|vga_vc[3]~3_combout ;
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wire \ula_|video_|Add1~7 ;
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wire \ula_|video_|Add1~8_combout ;
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wire \ula_|video_|vga_vc[4]~5_combout ;
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wire \ula_|video_|Add1~9 ;
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wire \ula_|video_|Add1~11 ;
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wire \ula_|video_|Add1~12_combout ;
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wire \ula_|video_|vga_vc[6]~4_combout ;
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wire \ula_|video_|Add1~13 ;
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wire \ula_|video_|Add1~14_combout ;
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wire \ula_|video_|vga_vc[7]~6_combout ;
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wire \ula_|video_|Add1~15 ;
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wire \ula_|video_|Add1~16_combout ;
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wire \ula_|video_|vga_vc[8]~7_combout ;
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wire \ula_|video_|Add1~17 ;
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wire \ula_|video_|Add1~18_combout ;
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wire \ula_|video_|vga_vc[9]~9_combout ;
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wire \ula_|video_|Equal3~0_combout ;
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wire \ula_|video_|Equal2~0_combout ;
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wire \ula_|video_|Equal3~1_combout ;
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wire \ula_|video_|Add1~10_combout ;
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wire \ula_|video_|vga_vc[5]~8_combout ;
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wire \ula_|video_|Equal2~1_combout ;
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wire \ula_|video_|Equal2~2_combout ;
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wire \SW[1]~input_o ;
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wire \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ;
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wire \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ;
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wire \z80_|interrupts_|int_armed~q ;
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wire \z80_|interrupts_|DFFE_inst44~feeder_combout ;
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wire \z80_|interrupts_|DFFE_inst44~q ;
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wire \z80_|decode_state_|in_halt~0_combout ;
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wire \z80_|decode_state_|in_halt~1_combout ;
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wire \z80_|decode_state_|in_halt~q ;
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wire \z80_|pla_decode_|Equal50~0_combout ;
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wire \z80_|execute_|ixy_d~17_combout ;
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wire \z80_|pla_decode_|Equal44~0_combout ;
|
|
wire \z80_|execute_|ixy_d~16_combout ;
|
|
wire \z80_|pla_decode_|Equal3~1_combout ;
|
|
wire \z80_|execute_|ixy_d~10_combout ;
|
|
wire \z80_|execute_|ixy_d~13_combout ;
|
|
wire \z80_|execute_|ixy_d~14_combout ;
|
|
wire \z80_|pla_decode_|Equal49~0_combout ;
|
|
wire \z80_|execute_|ixy_d~15_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ;
|
|
wire \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ;
|
|
wire \z80_|decode_state_|DFFE_inst4~q ;
|
|
wire \z80_|execute_|ctl_ir_we~5_combout ;
|
|
wire \z80_|execute_|ctl_ir_we~13_combout ;
|
|
wire \z80_|pla_decode_|Equal8~0_combout ;
|
|
wire \z80_|execute_|ctl_mRead~6_combout ;
|
|
wire \z80_|pla_decode_|Equal9~0_combout ;
|
|
wire \z80_|pla_decode_|Equal9~1_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ;
|
|
wire \z80_|pla_decode_|Equal13~1_combout ;
|
|
wire \z80_|pla_decode_|Equal69~0_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ;
|
|
wire \z80_|execute_|ctl_alu_op_low~27_combout ;
|
|
wire \z80_|execute_|ctl_reg_out_lo~2_combout ;
|
|
wire \z80_|execute_|rsel3~combout ;
|
|
wire \z80_|execute_|ctl_ir_we~12_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ;
|
|
wire \z80_|pla_decode_|Equal56~0_combout ;
|
|
wire \z80_|execute_|ctl_alu_op_low~24_combout ;
|
|
wire \z80_|execute_|ctl_alu_op_low~25_combout ;
|
|
wire \z80_|execute_|nextM~2_combout ;
|
|
wire \z80_|execute_|ctl_alu_op1_sel_bus~16_combout ;
|
|
wire \z80_|execute_|ctl_reg_out_lo~3_combout ;
|
|
wire \z80_|pla_decode_|Equal40~0_combout ;
|
|
wire \z80_|pla_decode_|Equal40~1_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ;
|
|
wire \z80_|pla_decode_|Equal3~0_combout ;
|
|
wire \z80_|pla_decode_|Equal39~0_combout ;
|
|
wire \z80_|execute_|ctl_reg_out_lo~4_combout ;
|
|
wire \z80_|execute_|ctl_alu_oe~0_combout ;
|
|
wire \z80_|execute_|comb~0_combout ;
|
|
wire \z80_|pla_decode_|Equal41~0_combout ;
|
|
wire \z80_|pla_decode_|Equal47~0_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~32_combout ;
|
|
wire \z80_|pla_decode_|Equal19~0_combout ;
|
|
wire \z80_|execute_|ctl_reg_out_lo~9_combout ;
|
|
wire \z80_|execute_|ctl_reg_out_lo~5_combout ;
|
|
wire \z80_|execute_|ctl_mWrite~4_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ;
|
|
wire \z80_|execute_|ctl_mRead~34_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ;
|
|
wire \z80_|execute_|ctl_mWrite~5_combout ;
|
|
wire \z80_|execute_|nextM~11_combout ;
|
|
wire \z80_|pla_decode_|Equal20~0_combout ;
|
|
wire \z80_|pla_decode_|Equal13~2_combout ;
|
|
wire \z80_|execute_|ctl_mRead~24_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_sel[0]~27_combout ;
|
|
wire \z80_|pla_decode_|Equal48~0_combout ;
|
|
wire \z80_|pla_decode_|Equal10~0_combout ;
|
|
wire \z80_|pla_decode_|Equal11~0_combout ;
|
|
wire \z80_|pla_decode_|Equal63~0_combout ;
|
|
wire \z80_|execute_|ctl_flags_hf2_we~combout ;
|
|
wire \z80_|execute_|ctl_alu_shift_oe~41_combout ;
|
|
wire \z80_|pla_decode_|Equal68~3_combout ;
|
|
wire \z80_|execute_|ctl_flags_bus~7_combout ;
|
|
wire \z80_|execute_|ctl_flags_bus~8_combout ;
|
|
wire \z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ;
|
|
wire \z80_|execute_|ctl_ir_we~6_combout ;
|
|
wire \z80_|execute_|ctl_ir_we~8_combout ;
|
|
wire \z80_|execute_|ctl_ir_we~14_combout ;
|
|
wire \z80_|execute_|ctl_flags_bus~4_combout ;
|
|
wire \z80_|execute_|ctl_flags_bus~5_combout ;
|
|
wire \z80_|execute_|ctl_mRead~4_combout ;
|
|
wire \z80_|execute_|ctl_flags_bus~6_combout ;
|
|
wire \z80_|execute_|ctl_flags_bus~9_combout ;
|
|
wire \z80_|execute_|ctl_iorw~11_combout ;
|
|
wire \z80_|execute_|ctl_mWrite~17_combout ;
|
|
wire \z80_|execute_|ctl_alu_shift_oe~18_combout ;
|
|
wire \z80_|pla_decode_|Equal37~0_combout ;
|
|
wire \z80_|execute_|ctl_alu_shift_oe~19_combout ;
|
|
wire \z80_|pla_decode_|Equal35~0_combout ;
|
|
wire \z80_|pla_decode_|Equal21~1_combout ;
|
|
wire \z80_|execute_|ctl_alu_shift_oe~17_combout ;
|
|
wire \z80_|execute_|ctl_alu_shift_oe~20_combout ;
|
|
wire \z80_|execute_|ctl_ir_we~9_combout ;
|
|
wire \z80_|execute_|ctl_alu_bs_oe~11_combout ;
|
|
wire \z80_|execute_|ctl_ir_we~15_combout ;
|
|
wire \z80_|execute_|ctl_alu_bs_oe~7_combout ;
|
|
wire \z80_|execute_|ctl_ir_we~7_combout ;
|
|
wire \z80_|pla_decode_|Equal46~0_combout ;
|
|
wire \z80_|execute_|ctl_ir_we~11_combout ;
|
|
wire \z80_|execute_|ctl_bus_db_oe~3_combout ;
|
|
wire \z80_|pla_decode_|Equal52~1_combout ;
|
|
wire \z80_|execute_|ctl_flags_xy_we~21_combout ;
|
|
wire \z80_|execute_|ctl_flags_xy_we~13_combout ;
|
|
wire \z80_|execute_|ctl_state_alu~6_combout ;
|
|
wire \z80_|execute_|ctl_alu_shift_oe~14_combout ;
|
|
wire \z80_|execute_|ctl_flags_xy_we~14_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_sel[0]~24_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_sel~7_combout ;
|
|
wire \z80_|execute_|rsel0~combout ;
|
|
wire \z80_|execute_|ctl_state_alu~3_combout ;
|
|
wire \z80_|execute_|ctl_reg_use_sp~0_combout ;
|
|
wire \z80_|execute_|ctl_state_alu~2_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ;
|
|
wire \z80_|execute_|ctl_reg_out_lo~6_combout ;
|
|
wire \z80_|execute_|ctl_state_alu~5_combout ;
|
|
wire \z80_|execute_|ctl_sw_2u~1_combout ;
|
|
wire \z80_|execute_|ctl_alu_oe~1_combout ;
|
|
wire \z80_|execute_|ctl_mWrite~7_combout ;
|
|
wire \z80_|execute_|ctl_sw_2u~4_combout ;
|
|
wire \z80_|execute_|setM1~57_combout ;
|
|
wire \z80_|execute_|ctl_sw_2u~5_combout ;
|
|
wire \z80_|execute_|ctl_reg_out_lo~7_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~0_combout ;
|
|
wire \z80_|execute_|ctl_bus_inc_oe~41_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~86_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~88_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~36_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~87_combout ;
|
|
wire \z80_|execute_|ctl_bus_inc_oe~26_combout ;
|
|
wire \z80_|execute_|ctl_mWrite~9_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_we~1_combout ;
|
|
wire \z80_|execute_|ctl_bus_inc_oe~42_combout ;
|
|
wire \z80_|pla_decode_|Equal40~2_combout ;
|
|
wire \z80_|execute_|ctl_reg_sel_pc~14_combout ;
|
|
wire \z80_|pla_decode_|Equal55~0_combout ;
|
|
wire \z80_|execute_|ctl_mRead~11_combout ;
|
|
wire \z80_|pla_decode_|Equal6~1_combout ;
|
|
wire \z80_|execute_|setM1~36_combout ;
|
|
wire \z80_|execute_|comb~1_combout ;
|
|
wire \z80_|execute_|ctl_mRead~13_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ;
|
|
wire \z80_|pla_decode_|Equal24~0_combout ;
|
|
wire \z80_|execute_|pc_inc_hold~26_combout ;
|
|
wire \z80_|execute_|setM1~37_combout ;
|
|
wire \z80_|execute_|pc_inc_hold~6_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_hilo~38_combout ;
|
|
wire \z80_|execute_|fMRead~7_combout ;
|
|
wire \z80_|execute_|ctl_mRead~12_combout ;
|
|
wire \z80_|execute_|ctl_bus_inc_oe~31_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ;
|
|
wire \z80_|nM1_int~2_combout ;
|
|
wire \z80_|execute_|ctl_sw_4u~0_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ;
|
|
wire \z80_|execute_|fMRead~6_combout ;
|
|
wire \z80_|execute_|ctl_inc_dec~12_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ;
|
|
wire \z80_|pla_decode_|Equal25~0_combout ;
|
|
wire \z80_|pla_decode_|Equal12~1_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~38_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~82_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ;
|
|
wire \z80_|execute_|ctl_bus_inc_oe~32_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~77_combout ;
|
|
wire \z80_|pla_decode_|Equal29~0_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~78_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~79_combout ;
|
|
wire \z80_|execute_|ctl_mRead~14_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~49_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_sel[1]~5_combout ;
|
|
wire \z80_|execute_|ctl_bus_inc_oe~40_combout ;
|
|
wire \z80_|execute_|ctl_mRead~5_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ;
|
|
wire \z80_|execute_|ctl_bus_inc_oe~36_combout ;
|
|
wire \z80_|execute_|ctl_bus_inc_oe~35_combout ;
|
|
wire \z80_|execute_|ctl_bus_inc_oe~46_combout ;
|
|
wire \z80_|execute_|ctl_bus_inc_oe~33_combout ;
|
|
wire \z80_|execute_|ctl_bus_inc_oe~47_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ;
|
|
wire \z80_|execute_|ctl_bus_inc_oe~45_combout ;
|
|
wire \z80_|execute_|ctl_bus_inc_oe~34_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ;
|
|
wire \z80_|execute_|ctl_mWrite~6_combout ;
|
|
wire \z80_|execute_|ctl_bus_inc_oe~50_combout ;
|
|
wire \z80_|pla_decode_|Equal4~0_combout ;
|
|
wire \z80_|execute_|ctl_bus_inc_oe~48_combout ;
|
|
wire \z80_|execute_|ctl_bus_inc_oe~49_combout ;
|
|
wire \z80_|execute_|ctl_mRead~7_combout ;
|
|
wire \z80_|execute_|ctl_bus_inc_oe~29_combout ;
|
|
wire \z80_|execute_|ctl_alu_core_S~11_combout ;
|
|
wire \z80_|execute_|ctl_bus_inc_oe~27_combout ;
|
|
wire \z80_|execute_|ctl_bus_inc_oe~44_combout ;
|
|
wire \z80_|execute_|ctl_bus_inc_oe~28_combout ;
|
|
wire \z80_|execute_|ctl_bus_inc_oe~30_combout ;
|
|
wire \z80_|execute_|ctl_mRead~3_combout ;
|
|
wire \z80_|execute_|fMRead~3_combout ;
|
|
wire \z80_|execute_|ctl_bus_inc_oe~37_combout ;
|
|
wire \z80_|execute_|ctl_bus_inc_oe~38_combout ;
|
|
wire \z80_|execute_|ctl_bus_inc_oe~39_combout ;
|
|
wire \z80_|execute_|ctl_bus_inc_oe~43_combout ;
|
|
wire \z80_|execute_|ctl_alu_oe~3_combout ;
|
|
wire \z80_|execute_|fMWrite~1_combout ;
|
|
wire \z80_|execute_|ctl_flags_bus~1_combout ;
|
|
wire \z80_|execute_|fMRead~5_combout ;
|
|
wire \z80_|execute_|ctl_mRead~17_combout ;
|
|
wire \z80_|execute_|ctl_iorw~10_combout ;
|
|
wire \z80_|execute_|setM1~47_combout ;
|
|
wire \z80_|execute_|ctl_mWrite~8_combout ;
|
|
wire \z80_|execute_|ctl_al_we~13_combout ;
|
|
wire \z80_|execute_|setM1~48_combout ;
|
|
wire \z80_|execute_|ctl_sw_4d~0_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ;
|
|
wire \z80_|execute_|ctl_mRead~9_combout ;
|
|
wire \z80_|execute_|ctl_flags_sz_we~3_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ;
|
|
wire \z80_|execute_|ctl_flags_alu~9_combout ;
|
|
wire \z80_|execute_|ctl_alu_sel_op2_neg~2_combout ;
|
|
wire \z80_|execute_|ctl_flags_alu~10_combout ;
|
|
wire \z80_|execute_|ctl_flags_xy_we~10_combout ;
|
|
wire \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ;
|
|
wire \z80_|execute_|ctl_flags_xy_we~11_combout ;
|
|
wire \z80_|execute_|ctl_flags_alu~11_combout ;
|
|
wire \z80_|execute_|ctl_reg_use_sp~1_combout ;
|
|
wire \z80_|execute_|ctl_state_alu~4_combout ;
|
|
wire \z80_|execute_|ctl_alu_op2_sel_bus~9_combout ;
|
|
wire \z80_|execute_|ctl_sw_2d~4_combout ;
|
|
wire \z80_|execute_|ctl_flags_sz_we~0_combout ;
|
|
wire \z80_|execute_|ctl_flags_sz_we~4_combout ;
|
|
wire \z80_|execute_|ctl_alu_op_low~47_combout ;
|
|
wire \z80_|execute_|ctl_alu_sel_op2_neg~3_combout ;
|
|
wire \z80_|execute_|ctl_flags_alu~12_combout ;
|
|
wire \z80_|execute_|ctl_alu_op_low~23_combout ;
|
|
wire \z80_|execute_|ctl_flags_xy_we~19_combout ;
|
|
wire \z80_|execute_|ctl_flags_alu~13_combout ;
|
|
wire \z80_|execute_|ctl_reg_out_hi~4_combout ;
|
|
wire \z80_|execute_|ctl_sw_4u~1_combout ;
|
|
wire \z80_|execute_|ctl_alu_op_low~29_combout ;
|
|
wire \z80_|execute_|ctl_flags_alu~14_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ;
|
|
wire \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ;
|
|
wire \z80_|execute_|ctl_flags_use_cf2~13_combout ;
|
|
wire \z80_|execute_|ctl_flags_cf_we~7_combout ;
|
|
wire \z80_|execute_|ctl_pf_sel[0]~2_combout ;
|
|
wire \z80_|execute_|ctl_flags_hf_we~5_combout ;
|
|
wire \z80_|execute_|ctl_flags_pf_we~10_combout ;
|
|
wire \z80_|pla_decode_|Equal68~2_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo[1]~13_combout ;
|
|
wire \z80_|execute_|ctl_flags_pf_we~2_combout ;
|
|
wire \z80_|execute_|ctl_alu_oe~4_combout ;
|
|
wire \z80_|execute_|ctl_flags_xy_we~8_combout ;
|
|
wire \z80_|execute_|ctl_flags_xy_we~20_combout ;
|
|
wire \z80_|execute_|ctl_flags_xy_we~9_combout ;
|
|
wire \z80_|execute_|ctl_flags_sz_we~1_combout ;
|
|
wire \z80_|execute_|ctl_bus_db_oe~1_combout ;
|
|
wire \z80_|execute_|ctl_alu_op2_sel_bus~10_combout ;
|
|
wire \z80_|execute_|ctl_flags_sz_we~2_combout ;
|
|
wire \z80_|execute_|ctl_flags_alu~17_combout ;
|
|
wire \z80_|execute_|ctl_flags_alu~18_combout ;
|
|
wire \z80_|execute_|ctl_flags_alu~6_combout ;
|
|
wire \z80_|execute_|ctl_flags_alu~19_combout ;
|
|
wire \z80_|pla_decode_|Equal1~5_combout ;
|
|
wire \z80_|execute_|ctl_alu_core_R~0_combout ;
|
|
wire \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ;
|
|
wire \z80_|execute_|ctl_alu_core_R~1_combout ;
|
|
wire \z80_|execute_|ctl_flags_alu~7_combout ;
|
|
wire \z80_|reg_control_|reg_sys_we_lo~5_combout ;
|
|
wire \z80_|reg_control_|reg_sys_we_lo~8_combout ;
|
|
wire \z80_|execute_|ctl_flags_alu~8_combout ;
|
|
wire \z80_|execute_|ctl_flags_alu~15_combout ;
|
|
wire \z80_|execute_|ctl_state_alu~7_combout ;
|
|
wire \z80_|execute_|ctl_state_alu~12_combout ;
|
|
wire \z80_|execute_|ctl_state_alu~9_combout ;
|
|
wire \z80_|execute_|ctl_state_alu~10_combout ;
|
|
wire \z80_|execute_|ctl_state_alu~8_combout ;
|
|
wire \z80_|pla_decode_|Equal64~0_combout ;
|
|
wire \z80_|execute_|ctl_pf_sel[0]~3_combout ;
|
|
wire \z80_|pla_decode_|Equal62~2_combout ;
|
|
wire \z80_|execute_|ctl_flags_pf_we~4_combout ;
|
|
wire \z80_|execute_|ctl_alu_shift_oe~46_combout ;
|
|
wire \z80_|execute_|ctl_flags_pf_we~6_combout ;
|
|
wire \z80_|execute_|ctl_flags_pf_we~7_combout ;
|
|
wire \z80_|execute_|ctl_state_alu~11_combout ;
|
|
wire \z80_|pla_decode_|Equal62~3_combout ;
|
|
wire \z80_|execute_|ctl_flags_pf_we~5_combout ;
|
|
wire \z80_|execute_|ctl_flags_pf_we~3_combout ;
|
|
wire \z80_|execute_|ctl_flags_pf_we~8_combout ;
|
|
wire \z80_|execute_|ctl_flags_pf_we~9_combout ;
|
|
wire \z80_|execute_|ctl_alu_core_S~6_combout ;
|
|
wire \z80_|execute_|ctl_alu_core_S~7_combout ;
|
|
wire \z80_|execute_|ctl_alu_res_oe~1_combout ;
|
|
wire \z80_|execute_|ctl_alu_res_oe~0_combout ;
|
|
wire \z80_|execute_|ctl_alu_core_S~4_combout ;
|
|
wire \z80_|execute_|ctl_alu_core_S~5_combout ;
|
|
wire \z80_|execute_|ctl_alu_res_oe~2_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ;
|
|
wire \z80_|reg_control_|reg_sys_we_lo~6_combout ;
|
|
wire \z80_|execute_|ctl_flags_xy_we~12_combout ;
|
|
wire \z80_|execute_|ctl_flags_cf_we~2_combout ;
|
|
wire \z80_|execute_|ctl_alu_res_oe~3_combout ;
|
|
wire \z80_|execute_|ctl_alu_sel_op2_high~combout ;
|
|
wire \z80_|execute_|ctl_alu_op1_sel_zero~4_combout ;
|
|
wire \z80_|execute_|ctl_alu_core_hf~12_combout ;
|
|
wire \z80_|pla_decode_|Equal61~2_combout ;
|
|
wire \z80_|execute_|ctl_alu_sel_op2_neg~4_combout ;
|
|
wire \z80_|execute_|ctl_alu_sel_op2_neg~13_combout ;
|
|
wire \z80_|execute_|ctl_alu_sel_op2_neg~14_combout ;
|
|
wire \z80_|execute_|ctl_alu_sel_op2_neg~18_combout ;
|
|
wire \z80_|execute_|ctl_flags_bus~10_combout ;
|
|
wire \z80_|execute_|ctl_flags_bus~2_combout ;
|
|
wire \z80_|execute_|ctl_flags_bus~0_combout ;
|
|
wire \z80_|execute_|ctl_flags_bus~3_combout ;
|
|
wire \z80_|execute_|fMRead~26_combout ;
|
|
wire \z80_|execute_|ctl_flags_bus~combout ;
|
|
wire \z80_|execute_|ctl_reg_in_lo~9_combout ;
|
|
wire \z80_|execute_|ctl_alu_op1_oe~0_combout ;
|
|
wire \z80_|execute_|ctl_alu_op1_oe~1_combout ;
|
|
wire \z80_|execute_|ctl_alu_bs_oe~6_combout ;
|
|
wire \z80_|execute_|ctl_alu_bs_oe~12_combout ;
|
|
wire \z80_|execute_|ctl_alu_bs_oe~8_combout ;
|
|
wire \z80_|execute_|ctl_alu_bs_oe~9_combout ;
|
|
wire \z80_|execute_|ctl_alu_bs_oe~combout ;
|
|
wire \z80_|execute_|ctl_alu_op2_oe~0_combout ;
|
|
wire \z80_|alu_|db_high[3]~0_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2~combout ;
|
|
wire \z80_|execute_|ctl_alu_shift_oe~15_combout ;
|
|
wire \z80_|execute_|ctl_alu_shift_oe~38_combout ;
|
|
wire \z80_|execute_|ctl_alu_op_low~28_combout ;
|
|
wire \z80_|execute_|ctl_alu_op1_sel_bus~6_combout ;
|
|
wire \z80_|execute_|ctl_alu_shift_oe~37_combout ;
|
|
wire \z80_|execute_|ctl_alu_shift_oe~39_combout ;
|
|
wire \z80_|execute_|ctl_flags_cf2_sel_daa~combout ;
|
|
wire \z80_|execute_|ctl_alu_op1_sel_bus~7_combout ;
|
|
wire \z80_|execute_|ctl_alu_op1_sel_bus~8_combout ;
|
|
wire \z80_|execute_|ctl_alu_op_low~30_combout ;
|
|
wire \z80_|execute_|ctl_alu_op_low~31_combout ;
|
|
wire \z80_|execute_|ctl_mRead~25_combout ;
|
|
wire \z80_|execute_|ctl_alu_shift_oe~40_combout ;
|
|
wire \z80_|execute_|ctl_alu_shift_oe~42_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ;
|
|
wire \z80_|execute_|ctl_alu_op2_sel_bus~4_combout ;
|
|
wire \z80_|execute_|ctl_alu_shift_oe~47_combout ;
|
|
wire \z80_|execute_|ctl_alu_shift_oe~34_combout ;
|
|
wire \z80_|execute_|ctl_alu_shift_oe~35_combout ;
|
|
wire \z80_|execute_|ctl_alu_shift_oe~36_combout ;
|
|
wire \z80_|execute_|ctl_alu_shift_oe~28_combout ;
|
|
wire \z80_|execute_|ctl_alu_shift_oe~44_combout ;
|
|
wire \z80_|execute_|ctl_alu_shift_oe~29_combout ;
|
|
wire \z80_|execute_|ctl_alu_shift_oe~16_combout ;
|
|
wire \z80_|execute_|ctl_alu_shift_oe~27_combout ;
|
|
wire \z80_|execute_|ctl_alu_bs_oe~10_combout ;
|
|
wire \z80_|execute_|ctl_alu_shift_oe~31_combout ;
|
|
wire \z80_|execute_|ctl_alu_shift_oe~30_combout ;
|
|
wire \z80_|execute_|ctl_alu_shift_oe~32_combout ;
|
|
wire \z80_|execute_|ctl_alu_shift_oe~33_combout ;
|
|
wire \z80_|execute_|ctl_alu_shift_oe~21_combout ;
|
|
wire \z80_|execute_|ctl_alu_shift_oe~45_combout ;
|
|
wire \z80_|execute_|ctl_alu_shift_oe~22_combout ;
|
|
wire \z80_|execute_|ctl_alu_shift_oe~23_combout ;
|
|
wire \z80_|execute_|ctl_alu_shift_oe~24_combout ;
|
|
wire \z80_|execute_|ctl_alu_shift_oe~25_combout ;
|
|
wire \z80_|execute_|ctl_alu_shift_oe~26_combout ;
|
|
wire \z80_|execute_|ctl_alu_shift_oe~43_combout ;
|
|
wire \z80_|execute_|ctl_alu_op1_sel_low~combout ;
|
|
wire \z80_|execute_|ctl_alu_op1_sel_zero~5_combout ;
|
|
wire \z80_|execute_|ctl_alu_op1_sel_zero~combout ;
|
|
wire \z80_|execute_|ctl_alu_op1_sel_bus~13_combout ;
|
|
wire \z80_|execute_|ctl_alu_op1_sel_bus~17_combout ;
|
|
wire \z80_|execute_|ctl_alu_op1_sel_bus~14_combout ;
|
|
wire \z80_|execute_|ctl_alu_core_R~3_combout ;
|
|
wire \z80_|execute_|ctl_alu_core_R~4_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ;
|
|
wire \z80_|execute_|ctl_alu_op1_sel_bus~9_combout ;
|
|
wire \z80_|execute_|ctl_alu_op1_sel_bus~10_combout ;
|
|
wire \z80_|execute_|ctl_alu_op1_sel_bus~11_combout ;
|
|
wire \z80_|execute_|ctl_alu_op1_sel_bus~12_combout ;
|
|
wire \z80_|execute_|ctl_alu_op1_sel_bus~15_combout ;
|
|
wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ;
|
|
wire \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~6_combout ;
|
|
wire \z80_|alu_|b2v_op1_latch_mux_low|ena~combout ;
|
|
wire \z80_|alu_|db_low[3]~15_combout ;
|
|
wire \z80_|alu_|db_low[3]~16_combout ;
|
|
wire \z80_|execute_|ctl_alu_op_low~33_combout ;
|
|
wire \z80_|execute_|ctl_alu_op_low~34_combout ;
|
|
wire \z80_|execute_|ctl_alu_op_low~48_combout ;
|
|
wire \z80_|execute_|ctl_alu_op_low~35_combout ;
|
|
wire \z80_|execute_|ctl_alu_op_low~36_combout ;
|
|
wire \z80_|execute_|ctl_alu_op_low~37_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ;
|
|
wire \z80_|execute_|ctl_alu_op_low~38_combout ;
|
|
wire \z80_|execute_|ctl_alu_op_low~39_combout ;
|
|
wire \z80_|execute_|ctl_alu_op_low~40_combout ;
|
|
wire \z80_|execute_|ctl_alu_op_low~41_combout ;
|
|
wire \z80_|execute_|ctl_alu_op_low~combout ;
|
|
wire \z80_|execute_|ctl_alu_oe~5_combout ;
|
|
wire \z80_|execute_|ctl_alu_oe~6_combout ;
|
|
wire \z80_|execute_|ctl_alu_oe~9_combout ;
|
|
wire \z80_|execute_|ctl_alu_core_S~12_combout ;
|
|
wire \z80_|execute_|ctl_alu_oe~10_combout ;
|
|
wire \z80_|execute_|ctl_alu_oe~2_combout ;
|
|
wire \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ;
|
|
wire \z80_|execute_|ctl_reg_in_hi~8_combout ;
|
|
wire \z80_|reg_control_|reg_sys_we_lo~7_combout ;
|
|
wire \z80_|execute_|ctl_alu_oe~7_combout ;
|
|
wire \z80_|execute_|ctl_mWrite~11_combout ;
|
|
wire \z80_|execute_|ctl_bus_db_we~5_combout ;
|
|
wire \z80_|execute_|ctl_alu_oe~8_combout ;
|
|
wire \z80_|execute_|ctl_flags_alu~16_combout ;
|
|
wire \z80_|execute_|ctl_alu_oe~11_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ;
|
|
wire \z80_|execute_|ctl_reg_out_hi~8_combout ;
|
|
wire \z80_|execute_|ctl_reg_out_hi~5_combout ;
|
|
wire \z80_|execute_|ctl_sw_2u~2_combout ;
|
|
wire \z80_|execute_|ctl_sw_2u~0_combout ;
|
|
wire \z80_|execute_|ctl_sw_2u~3_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~33_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_hilo[1]~37_combout ;
|
|
wire \z80_|execute_|ctl_sw_2u~6_combout ;
|
|
wire \z80_|execute_|ctl_reg_out_hi~6_combout ;
|
|
wire \z80_|execute_|ctl_reg_out_hi~7_combout ;
|
|
wire \z80_|execute_|ctl_mRead~2_combout ;
|
|
wire \z80_|execute_|ctl_sw_2d~6_combout ;
|
|
wire \z80_|execute_|ctl_sw_2d~7_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ;
|
|
wire \z80_|execute_|ctl_sw_2d~8_combout ;
|
|
wire \z80_|execute_|ctl_bus_db_oe~7_combout ;
|
|
wire \z80_|execute_|ctl_sw_2d~5_combout ;
|
|
wire \z80_|execute_|ctl_mRead~19_combout ;
|
|
wire \z80_|execute_|ctl_mRead~18_combout ;
|
|
wire \z80_|reg_control_|reg_sys_we_lo~2_combout ;
|
|
wire \z80_|pla_decode_|Equal24~1_combout ;
|
|
wire \z80_|reg_control_|reg_sys_we_lo~3_combout ;
|
|
wire \z80_|reg_control_|reg_sys_we_lo~4_combout ;
|
|
wire \z80_|execute_|ctl_mRead~20_combout ;
|
|
wire \z80_|execute_|ctl_reg_in_hi~5_combout ;
|
|
wire \z80_|execute_|ctl_mRead~22_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ;
|
|
wire \z80_|execute_|ctl_reg_in_hi~6_combout ;
|
|
wire \z80_|execute_|ctl_reg_in_hi~2_combout ;
|
|
wire \z80_|execute_|setM1~30_combout ;
|
|
wire \z80_|execute_|ctl_mRead~23_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_sel[0]~6_combout ;
|
|
wire \z80_|execute_|ctl_reg_in_hi~3_combout ;
|
|
wire \z80_|execute_|ctl_mWrite~10_combout ;
|
|
wire \z80_|execute_|fMRead~18_combout ;
|
|
wire \z80_|reg_control_|reg_sel_pc~0_combout ;
|
|
wire \z80_|reg_control_|reg_sel_pc~1_combout ;
|
|
wire \z80_|reg_control_|reg_sel_pc~2_combout ;
|
|
wire \z80_|execute_|fMRead~19_combout ;
|
|
wire \z80_|execute_|fMRead~20_combout ;
|
|
wire \z80_|execute_|fMRead~21_combout ;
|
|
wire \z80_|execute_|ctl_sw_2d~9_combout ;
|
|
wire \z80_|execute_|ctl_sw_2d~14_combout ;
|
|
wire \z80_|execute_|ctl_sw_1d~8_combout ;
|
|
wire \z80_|execute_|ctl_sw_2d~10_combout ;
|
|
wire \z80_|execute_|ctl_sw_2d~11_combout ;
|
|
wire \z80_|execute_|ctl_sw_2d~12_combout ;
|
|
wire \z80_|execute_|ctl_sw_2d~13_combout ;
|
|
wire \z80_|alu_|db[7]~9_combout ;
|
|
wire \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ;
|
|
wire \z80_|execute_|ctl_alu_op_low~32_combout ;
|
|
wire \z80_|alu_flags_|DFFE_inst_latch_nf~2_combout ;
|
|
wire \z80_|execute_|ctl_flags_xy_we~22_combout ;
|
|
wire \z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ;
|
|
wire \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ;
|
|
wire \z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ;
|
|
wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ;
|
|
wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ;
|
|
wire \z80_|execute_|ctl_alu_core_hf~15_combout ;
|
|
wire \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ;
|
|
wire \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ;
|
|
wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ;
|
|
wire \z80_|execute_|ctl_alu_sel_op2_neg~17_combout ;
|
|
wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ;
|
|
wire \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ;
|
|
wire \z80_|execute_|ctl_flags_nf_we~3_combout ;
|
|
wire \z80_|execute_|ctl_flags_nf_we~0_combout ;
|
|
wire \z80_|pla_decode_|Equal73~2_combout ;
|
|
wire \z80_|pla_decode_|Equal72~2_combout ;
|
|
wire \z80_|execute_|ctl_flags_nf_we~1_combout ;
|
|
wire \z80_|execute_|ctl_flags_nf_we~2_combout ;
|
|
wire \z80_|execute_|ctl_flags_sz_we~5_combout ;
|
|
wire \z80_|execute_|ctl_flags_sz_we~6_combout ;
|
|
wire \z80_|execute_|ctl_flags_nf_we~4_combout ;
|
|
wire \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ;
|
|
wire \z80_|alu_flags_|DFFE_inst_latch_nf~q ;
|
|
wire \z80_|execute_|ctl_flags_hf_cpl~14_combout ;
|
|
wire \z80_|execute_|ctl_flags_hf_cpl~10_combout ;
|
|
wire \z80_|pla_decode_|Equal45~0_combout ;
|
|
wire \z80_|execute_|ctl_flags_hf_cpl~11_combout ;
|
|
wire \z80_|execute_|ctl_flags_hf_cpl~12_combout ;
|
|
wire \z80_|execute_|ctl_flags_hf_cpl~13_combout ;
|
|
wire \z80_|execute_|ctl_alu_core_S~8_combout ;
|
|
wire \z80_|execute_|ctl_alu_core_S~9_combout ;
|
|
wire \z80_|execute_|ctl_alu_core_S~10_combout ;
|
|
wire \z80_|execute_|ctl_alu_core_S~combout ;
|
|
wire \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ;
|
|
wire \z80_|alu_|alu_op1[3]~2_combout ;
|
|
wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_we_lo~2_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_we_lo~3_combout ;
|
|
wire \z80_|execute_|ctl_reg_sel_wz~14_combout ;
|
|
wire \z80_|reg_control_|reg_sys_we_hi~0_combout ;
|
|
wire \z80_|pla_decode_|Equal33~3_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_we~0_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_we~2_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_we~3_combout ;
|
|
wire \z80_|execute_|ctl_reg_in_hi~4_combout ;
|
|
wire \z80_|reg_control_|reg_sys_we_hi~combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_hilo~17_combout ;
|
|
wire \z80_|execute_|ctl_reg_sel_pc~11_combout ;
|
|
wire \z80_|execute_|ctl_reg_sel_pc~12_combout ;
|
|
wire \z80_|execute_|ctl_reg_sel_pc~13_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ;
|
|
wire \z80_|execute_|ctl_reg_sel_wz~6_combout ;
|
|
wire \z80_|execute_|ctl_reg_sel_wz~7_combout ;
|
|
wire \z80_|execute_|ctl_reg_sel_wz~9_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ;
|
|
wire \z80_|execute_|ctl_reg_sel_wz~8_combout ;
|
|
wire \z80_|execute_|ctl_al_we~5_combout ;
|
|
wire \z80_|execute_|ctl_al_we~4_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_hilo[1]~41_combout ;
|
|
wire \z80_|execute_|ctl_reg_sel_wz~10_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_hilo~21_combout ;
|
|
wire \z80_|execute_|ctl_inc_dec~3_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ;
|
|
wire \z80_|execute_|fMRead~2_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_hilo[1]~20_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ;
|
|
wire \z80_|execute_|ctl_reg_sel_wz~13_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ;
|
|
wire \z80_|execute_|ctl_reg_sel_ir~0_combout ;
|
|
wire \z80_|execute_|ctl_reg_sel_ir~1_combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_we_lo~4_combout ;
|
|
wire \z80_|reg_control_|reg_sys_we_lo~combout ;
|
|
wire \z80_|reg_control_|reg_sw_4d_hi~0_combout ;
|
|
wire \z80_|reg_file_|db_hi_as[3]~10_combout ;
|
|
wire \z80_|reg_file_|db_hi_as[3]~11_combout ;
|
|
wire \z80_|execute_|ctl_apin_mux~1_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~37_combout ;
|
|
wire \z80_|execute_|ctl_inc_dec~2_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~40_combout ;
|
|
wire \z80_|execute_|ctl_inc_dec~4_combout ;
|
|
wire \z80_|execute_|ctl_inc_dec~5_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_sel[1]~4_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ;
|
|
wire \z80_|execute_|setM1~42_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo[1]~12_combout ;
|
|
wire \z80_|execute_|ctl_sw_1d~4_combout ;
|
|
wire \z80_|execute_|ctl_sw_4d~3_combout ;
|
|
wire \z80_|execute_|fMRead~9_combout ;
|
|
wire \z80_|execute_|fMRead~10_combout ;
|
|
wire \z80_|execute_|fMRead~8_combout ;
|
|
wire \z80_|execute_|ctl_sw_4d~2_combout ;
|
|
wire \z80_|execute_|ctl_reg_sel_wz~11_combout ;
|
|
wire \z80_|execute_|ctl_reg_sel_wz~12_combout ;
|
|
wire \z80_|execute_|ctl_sw_4d~4_combout ;
|
|
wire \z80_|execute_|ctl_sw_4d~5_combout ;
|
|
wire \z80_|execute_|ctl_al_we~14_combout ;
|
|
wire \z80_|execute_|ctl_al_we~10_combout ;
|
|
wire \z80_|execute_|ctl_al_we~6_combout ;
|
|
wire \z80_|execute_|ctl_al_we~7_combout ;
|
|
wire \z80_|execute_|ctl_al_we~8_combout ;
|
|
wire \z80_|execute_|ctl_al_we~9_combout ;
|
|
wire \z80_|execute_|ctl_al_we~11_combout ;
|
|
wire \z80_|execute_|ctl_al_we~12_combout ;
|
|
wire \z80_|execute_|fIOWrite~0_combout ;
|
|
wire \z80_|execute_|ctl_inc_dec~8_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_we~2_combout ;
|
|
wire \z80_|execute_|ctl_inc_dec~9_combout ;
|
|
wire \z80_|execute_|ctl_apin_mux~0_combout ;
|
|
wire \z80_|execute_|ctl_inc_dec~6_combout ;
|
|
wire \z80_|execute_|ctl_inc_dec~7_combout ;
|
|
wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ;
|
|
wire \z80_|execute_|ctl_reg_sel_wz~21_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_hilo[0]~40_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_hilo[1]~39_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_hilo[0]~13_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ;
|
|
wire \z80_|execute_|setM1~49_combout ;
|
|
wire \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ;
|
|
wire \z80_|execute_|setM1~50_combout ;
|
|
wire \z80_|execute_|ctl_flags_oe~0_combout ;
|
|
wire \z80_|execute_|ctl_flags_oe~1_combout ;
|
|
wire \z80_|execute_|ctl_reg_in_hi~13_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_sel[0]~12_combout ;
|
|
wire \z80_|execute_|ctl_reg_in_hi~7_combout ;
|
|
wire \z80_|execute_|ctl_state_alu~13_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_we~6_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_we~5_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo[1]~17_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ;
|
|
wire \z80_|execute_|ctl_alu_sel_op2_neg~10_combout ;
|
|
wire \z80_|execute_|ctl_sw_1d~9_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_we~9_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_we~4_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_we~7_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_we~3_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ;
|
|
wire \z80_|execute_|ctl_sw_4u~2_combout ;
|
|
wire \z80_|execute_|ctl_sw_4u~3_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_we~8_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo[1]~14_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo[0]~24_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo[0]~46_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo[0]~22_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo[0]~23_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_sel[1]~26_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo[1]~34_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_sel[0]~25_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo[0]~21_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ;
|
|
wire \z80_|pla_decode_|Equal2~2_combout ;
|
|
wire \z80_|pla_decode_|Equal1~6_combout ;
|
|
wire \z80_|reg_control_|bank_exx~2_combout ;
|
|
wire \z80_|reg_control_|bank_exx~q ;
|
|
wire \z80_|reg_control_|bank_hl_de1~0_combout ;
|
|
wire \z80_|reg_control_|bank_hl_de1~q ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_sel[0]~28_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_sel[0]~29_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_sel[0]~30_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_sel[0]~13_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ;
|
|
wire \z80_|execute_|ctl_reg_use_sp~2_combout ;
|
|
wire \z80_|execute_|ctl_reg_use_sp~3_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_sel[0]~14_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_sel[0]~32_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_sel[0]~33_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo[1]~16_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_sel[0]~34_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_sel[0]~35_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_sel[1]~20_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_sel[1]~21_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_sel[1]~22_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_sel[1]~18_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_sel[1]~37_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_sel[1]~19_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_sel[1]~23_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_sel[1]~16_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_sel[1]~17_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_sel[1]~11_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_sel[1]~36_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_sel[1]~8_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_sel[1]~9_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_sel[1]~10_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_sel[1]~15_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_sel[1]~31_combout ;
|
|
wire \z80_|reg_control_|reg_sel_de2~5_combout ;
|
|
wire \z80_|reg_control_|reg_sel_de2~6_combout ;
|
|
wire \z80_|reg_control_|reg_sel_de~0_combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ;
|
|
wire \z80_|reg_control_|bank_hl_de2~0_combout ;
|
|
wire \z80_|reg_control_|bank_hl_de2~q ;
|
|
wire \z80_|reg_control_|reg_sel_de2~4_combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[2]~33_combout ;
|
|
wire \z80_|reg_control_|reg_sel_hl~0_combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ;
|
|
wire \z80_|reg_control_|reg_sel_hl2~0_combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[2]~34_combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[2]~36_combout ;
|
|
wire \z80_|execute_|ctl_reg_sel_wz~15_combout ;
|
|
wire \z80_|execute_|ctl_reg_sel_wz~18_combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[2]~37_combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ;
|
|
wire \z80_|reg_control_|reg_sel_iy~2_combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[2]~38_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ;
|
|
wire \z80_|execute_|ctl_reg_in_hi~9_combout ;
|
|
wire \z80_|execute_|ctl_reg_in_hi~10_combout ;
|
|
wire \z80_|execute_|ctl_reg_in_lo~8_combout ;
|
|
wire \z80_|reg_file_|b2v_latch_sp_lo|latch[2]~feeder_combout ;
|
|
wire \z80_|execute_|ctl_reg_use_sp~4_combout ;
|
|
wire \z80_|execute_|ctl_reg_use_sp~5_combout ;
|
|
wire \z80_|execute_|ctl_reg_use_sp~6_combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ;
|
|
wire \z80_|execute_|ctl_sw_1d~5_combout ;
|
|
wire \z80_|execute_|ctl_im_we~combout ;
|
|
wire \z80_|execute_|ctl_sw_1d~6_combout ;
|
|
wire \z80_|execute_|ctl_sw_1d~7_combout ;
|
|
wire \z80_|reg_file_|db_lo_ds[2]~2_combout ;
|
|
wire \z80_|alu_control_|db[2]~28_combout ;
|
|
wire \z80_|execute_|ctl_reg_in_hi~11_combout ;
|
|
wire \z80_|execute_|ctl_reg_in_hi~12_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[0]~18_combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ;
|
|
wire \z80_|pla_decode_|Equal21~2_combout ;
|
|
wire \z80_|reg_control_|bank_af~0_combout ;
|
|
wire \z80_|reg_control_|bank_af~q ;
|
|
wire \z80_|reg_control_|reg_sel_af~0_combout ;
|
|
wire \z80_|reg_control_|reg_sel_af2~0_combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[0]~17_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[0]~19_combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[0]~16_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[0]~20_combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[2]~34_combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[2]~36_combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[2]~35_combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[2]~33_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[2]~37_combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ;
|
|
wire \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[2]~31_combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ;
|
|
wire \z80_|reg_file_|b2v_latch_af_hi|db[2]~12_combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[2]~32_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[2]~38_combout ;
|
|
wire \z80_|execute_|ctl_inc_dec~11_combout ;
|
|
wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ;
|
|
wire \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ;
|
|
wire \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ;
|
|
wire \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ;
|
|
wire \z80_|execute_|ctl_flags_cf_cpl~4_combout ;
|
|
wire \z80_|execute_|ctl_flags_cf_cpl~5_combout ;
|
|
wire \z80_|execute_|ctl_alu_sel_op2_neg~16_combout ;
|
|
wire \z80_|execute_|ctl_flags_cf_cpl~6_combout ;
|
|
wire \z80_|execute_|ctl_flags_cf_cpl~7_combout ;
|
|
wire \z80_|execute_|ctl_flags_cf_cpl~10_combout ;
|
|
wire \z80_|execute_|ctl_flags_cf_cpl~8_combout ;
|
|
wire \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ;
|
|
wire \z80_|execute_|ctl_alu_op_low~42_combout ;
|
|
wire \z80_|execute_|ctl_flags_cf_cpl~9_combout ;
|
|
wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ;
|
|
wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ;
|
|
wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ;
|
|
wire \z80_|execute_|ctl_mWrite~18_combout ;
|
|
wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ;
|
|
wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ;
|
|
wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ;
|
|
wire \z80_|execute_|ctl_flags_cf_cpl~2_combout ;
|
|
wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ;
|
|
wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ;
|
|
wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ;
|
|
wire \z80_|execute_|ctl_flags_cf2_we~4_combout ;
|
|
wire \z80_|execute_|ctl_flags_cf2_we~2_combout ;
|
|
wire \z80_|execute_|ctl_flags_cf2_we~3_combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[6]~81_combout ;
|
|
wire \z80_|alu_|db_high[2]~8_combout ;
|
|
wire \z80_|alu_|db_high[2]~9_combout ;
|
|
wire \z80_|alu_|db_high[2]~11_combout ;
|
|
wire \z80_|execute_|ctl_alu_op2_sel_lq~combout ;
|
|
wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ;
|
|
wire \z80_|execute_|ctl_alu_op2_sel_bus~5_combout ;
|
|
wire \z80_|execute_|ctl_alu_op2_sel_bus~6_combout ;
|
|
wire \z80_|execute_|ctl_alu_op2_sel_bus~7_combout ;
|
|
wire \z80_|execute_|ctl_alu_op2_sel_bus~8_combout ;
|
|
wire \z80_|execute_|ctl_alu_op2_sel_zero~combout ;
|
|
wire \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ;
|
|
wire \z80_|alu_|b2v_op2_latch_mux_high|ena~combout ;
|
|
wire \z80_|alu_|db_high[2]~10_combout ;
|
|
wire \z80_|alu_|db_high[2]~12_combout ;
|
|
wire \z80_|alu_|db_high[3]~1_combout ;
|
|
wire \z80_|alu_|db_high[2]~13_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[6]~78_combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[6]~79_combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ;
|
|
wire \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[6]~75_combout ;
|
|
wire \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[6]~76_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[6]~77_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[6]~80_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[6]~74_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[6]~73_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[6]~81_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[0]~19_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[0]~18_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[0]~20_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[0]~92_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[0]~21_combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ;
|
|
wire \z80_|reg_file_|db_lo_as[0]~2_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[4]~55_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[4]~56_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[4]~57_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[4]~59_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[4]~58_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[4]~60_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[4]~53_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[4]~54_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[4]~61_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[4]~62_combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ;
|
|
wire \z80_|reg_file_|db_lo_as[4]~13_combout ;
|
|
wire \z80_|reg_file_|db_lo_as[4]~14_combout ;
|
|
wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ;
|
|
wire \z80_|reg_file_|db_lo_as[4]~15_combout ;
|
|
wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[5]~64_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[5]~63_combout ;
|
|
wire \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[5]~65_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[5]~69_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[5]~68_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[5]~66_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[5]~67_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[5]~70_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[5]~71_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[5]~72_combout ;
|
|
wire \z80_|reg_file_|db_lo_as[5]~16_combout ;
|
|
wire \z80_|reg_file_|db_lo_as[5]~17_combout ;
|
|
wire \z80_|reg_file_|db_lo_as[5]~18_combout ;
|
|
wire \z80_|execute_|ctl_inc_dec~10_combout ;
|
|
wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ;
|
|
wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ;
|
|
wire \z80_|reg_file_|db_lo_as[6]~19_combout ;
|
|
wire \z80_|reg_file_|db_lo_as[6]~20_combout ;
|
|
wire \z80_|reg_file_|db_lo_as[6]~21_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[6]~82_combout ;
|
|
wire \z80_|reg_file_|db_lo_ds[6]~0_combout ;
|
|
wire \z80_|sw1_|db_down[6]~1_combout ;
|
|
wire \z80_|execute_|ctl_66_oe~combout ;
|
|
wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4_combout ;
|
|
wire \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ;
|
|
wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~2_combout ;
|
|
wire \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~3_combout ;
|
|
wire \z80_|alu_|alu_op2[1]~1_combout ;
|
|
wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ;
|
|
wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ;
|
|
wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ;
|
|
wire \z80_|execute_|ctl_alu_core_R~5_combout ;
|
|
wire \z80_|execute_|ctl_alu_core_R~2_combout ;
|
|
wire \z80_|execute_|ctl_alu_core_R~combout ;
|
|
wire \z80_|alu_|db_high[0]~20_combout ;
|
|
wire \z80_|alu_|db_high[0]~21_combout ;
|
|
wire \z80_|alu_|db_high[0]~22_combout ;
|
|
wire \z80_|alu_|db_high[0]~23_combout ;
|
|
wire \z80_|alu_|db_high[0]~24_combout ;
|
|
wire \z80_|alu_|db_low[0]~4_combout ;
|
|
wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~2_combout ;
|
|
wire \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~3_combout ;
|
|
wire \z80_|alu_|db_low[0]~5_combout ;
|
|
wire \z80_|alu_|db_low[0]~6_combout ;
|
|
wire \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ;
|
|
wire \z80_|execute_|ctl_flags_hf_we~2_combout ;
|
|
wire \z80_|execute_|ctl_flags_cf_we~3_combout ;
|
|
wire \z80_|execute_|ctl_flags_cf_we~4_combout ;
|
|
wire \z80_|execute_|ctl_flags_cf_we~5_combout ;
|
|
wire \z80_|execute_|ctl_flags_cf_we~6_combout ;
|
|
wire \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ;
|
|
wire \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ;
|
|
wire \z80_|alu_flags_|DFFE_inst_latch_cf~q ;
|
|
wire \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ;
|
|
wire \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ;
|
|
wire \z80_|alu_|db_low[0]~2_combout ;
|
|
wire \z80_|alu_|db_low[0]~3_combout ;
|
|
wire \z80_|alu_|db_low[0]~24_combout ;
|
|
wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~0_combout ;
|
|
wire \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~1_combout ;
|
|
wire \z80_|alu_|alu_op2[0]~3_combout ;
|
|
wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_hilo_pla26M3T5_8~combout ;
|
|
wire \z80_|execute_|ctl_alu_core_hf~14_combout ;
|
|
wire \z80_|execute_|ctl_alu_core_hf~16_combout ;
|
|
wire \z80_|execute_|ctl_alu_core_hf~13_combout ;
|
|
wire \z80_|execute_|ctl_alu_core_hf~17_combout ;
|
|
wire \z80_|execute_|ctl_alu_op_low~44_combout ;
|
|
wire \z80_|execute_|ctl_alu_core_hf~20_combout ;
|
|
wire \z80_|execute_|ctl_alu_core_hf~21_combout ;
|
|
wire \z80_|execute_|ctl_alu_core_hf~18_combout ;
|
|
wire \z80_|execute_|ctl_alu_core_hf~19_combout ;
|
|
wire \z80_|execute_|ctl_alu_core_hf~22_combout ;
|
|
wire \z80_|execute_|ctl_alu_op_low~43_combout ;
|
|
wire \z80_|execute_|ctl_alu_core_hf~24_combout ;
|
|
wire \z80_|execute_|ctl_alu_core_hf~25_combout ;
|
|
wire \z80_|execute_|ctl_alu_core_hf~35_combout ;
|
|
wire \z80_|execute_|ctl_alu_core_hf~23_combout ;
|
|
wire \z80_|execute_|ctl_alu_core_hf~26_combout ;
|
|
wire \z80_|execute_|ctl_alu_core_hf~34_combout ;
|
|
wire \z80_|execute_|ctl_alu_core_hf~27_combout ;
|
|
wire \z80_|execute_|ctl_alu_core_hf~28_combout ;
|
|
wire \z80_|execute_|ctl_alu_core_hf~29_combout ;
|
|
wire \z80_|execute_|ctl_alu_core_hf~30_combout ;
|
|
wire \z80_|execute_|ctl_alu_core_hf~31_combout ;
|
|
wire \z80_|execute_|ctl_alu_core_hf~36_combout ;
|
|
wire \z80_|execute_|ctl_alu_core_hf~37_combout ;
|
|
wire \z80_|execute_|ctl_alu_core_hf~32_combout ;
|
|
wire \z80_|execute_|ctl_alu_core_hf~33_combout ;
|
|
wire \z80_|alu_control_|alu_core_cf_in~0_combout ;
|
|
wire \z80_|alu_|alu_op1[0]~0_combout ;
|
|
wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ;
|
|
wire \z80_|alu_|db_high[0]~25_combout ;
|
|
wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6_combout ;
|
|
wire \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ;
|
|
wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ;
|
|
wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ;
|
|
wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ;
|
|
wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ;
|
|
wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ;
|
|
wire \z80_|alu_|db_high[1]~14_combout ;
|
|
wire \z80_|alu_|db_high[1]~15_combout ;
|
|
wire \z80_|alu_|db_high[1]~16_combout ;
|
|
wire \z80_|alu_|db_high[1]~17_combout ;
|
|
wire \z80_|alu_|db_high[1]~18_combout ;
|
|
wire \z80_|alu_|db_high[1]~19_combout ;
|
|
wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ;
|
|
wire \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ;
|
|
wire \z80_|alu_control_|out[6]~0_combout ;
|
|
wire \z80_|alu_control_|out[6]~1_combout ;
|
|
wire \z80_|alu_control_|out[6]~2_combout ;
|
|
wire \z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ;
|
|
wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ;
|
|
wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ;
|
|
wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ;
|
|
wire \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ;
|
|
wire \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ;
|
|
wire \z80_|execute_|ctl_flags_sz_we~7_combout ;
|
|
wire \z80_|execute_|ctl_flags_sz_we~8_combout ;
|
|
wire \z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ;
|
|
wire \z80_|execute_|setM1~51_combout ;
|
|
wire \z80_|execute_|ctl_flags_oe~2_combout ;
|
|
wire \z80_|execute_|ctl_sw_2u~7_combout ;
|
|
wire \z80_|alu_control_|db[6]~20_combout ;
|
|
wire \z80_|alu_control_|db[6]~21_combout ;
|
|
wire \z80_|execute_|ctl_reg_out_lo~8_combout ;
|
|
wire \z80_|alu_control_|db[6]~10_combout ;
|
|
wire \z80_|alu_control_|db[6]~11_combout ;
|
|
wire \z80_|alu_control_|db[6]~22_combout ;
|
|
wire \z80_|alu_|db[6]~21_combout ;
|
|
wire \z80_|alu_|db[6]~22_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[6]~80_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[6]~79_combout ;
|
|
wire \z80_|reg_file_|b2v_latch_bc_hi|latch[6]~feeder_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[6]~78_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[6]~82_combout ;
|
|
wire \z80_|reg_file_|b2v_latch_hl2_hi|db[6]~5_combout ;
|
|
wire \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[6]~76_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[6]~77_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[6]~83_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[6]~84_combout ;
|
|
wire \z80_|reg_file_|db_hi_as[6]~22_combout ;
|
|
wire \z80_|reg_file_|db_hi_as[6]~23_combout ;
|
|
wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[4]~61_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[4]~62_combout ;
|
|
wire \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[4]~60_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[4]~63_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[4]~64_combout ;
|
|
wire \z80_|reg_file_|b2v_latch_hl2_hi|db[4]~4_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[4]~58_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[4]~59_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[4]~65_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[4]~66_combout ;
|
|
wire \z80_|reg_file_|db_hi_as[4]~16_combout ;
|
|
wire \z80_|reg_file_|db_hi_as[4]~17_combout ;
|
|
wire \z80_|reg_file_|db_hi_as[4]~18_combout ;
|
|
wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ;
|
|
wire \z80_|reg_file_|db_hi_as[6]~24_combout ;
|
|
wire \z80_|address_latch_|b2v_inst_inc_dec|address[15]~0_combout ;
|
|
wire \z80_|address_latch_|b2v_inst_inc_dec|address[15]~1_combout ;
|
|
wire \z80_|reg_file_|db_hi_as[7]~19_combout ;
|
|
wire \z80_|reg_file_|db_hi_as[7]~20_combout ;
|
|
wire \z80_|reg_file_|db_hi_as[7]~21_combout ;
|
|
wire \z80_|reg_file_|b2v_latch_af_hi|db[7]~15_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[7]~72_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[7]~71_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[7]~70_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[7]~69_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[7]~73_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[7]~68_combout ;
|
|
wire \z80_|reg_file_|b2v_latch_de_hi|latch[7]~feeder_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[7]~67_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[7]~74_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[7]~75_combout ;
|
|
wire \z80_|alu_|db[7]~11_combout ;
|
|
wire \z80_|alu_|db[7]~12_combout ;
|
|
wire \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ;
|
|
wire \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ;
|
|
wire \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ;
|
|
wire \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ;
|
|
wire \z80_|alu_flags_|DFFE_inst_latch_cf2~q ;
|
|
wire \z80_|execute_|ctl_flags_use_cf2~8_combout ;
|
|
wire \z80_|execute_|ctl_flags_use_cf2~9_combout ;
|
|
wire \z80_|execute_|ctl_flags_use_cf2~10_combout ;
|
|
wire \z80_|execute_|ctl_flags_use_cf2~11_combout ;
|
|
wire \z80_|execute_|ctl_flags_use_cf2~12_combout ;
|
|
wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ;
|
|
wire \z80_|execute_|ctl_alu_op_low~46_combout ;
|
|
wire \z80_|execute_|ctl_alu_sel_op2_neg~9_combout ;
|
|
wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ;
|
|
wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ;
|
|
wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ;
|
|
wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ;
|
|
wire \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ;
|
|
wire \z80_|execute_|ctl_flags_cf_cpl~3_combout ;
|
|
wire \z80_|alu_flags_|flags_cf~combout ;
|
|
wire \z80_|sw2_|db_up[0]~0_combout ;
|
|
wire \z80_|alu_control_|db[0]~8_combout ;
|
|
wire \z80_|reg_file_|db_lo_as[0]~0_combout ;
|
|
wire \z80_|reg_file_|db_lo_as[0]~1_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~70_combout ;
|
|
wire \z80_|execute_|pc_inc_hold~28_combout ;
|
|
wire \z80_|execute_|pc_inc_hold~15_combout ;
|
|
wire \z80_|execute_|pc_inc_hold~27_combout ;
|
|
wire \z80_|execute_|pc_inc_hold~10_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ;
|
|
wire \z80_|execute_|pc_inc_hold~11_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ;
|
|
wire \z80_|execute_|pc_inc_hold~9_combout ;
|
|
wire \z80_|execute_|pc_inc_hold~12_combout ;
|
|
wire \z80_|execute_|pc_inc_hold~7_combout ;
|
|
wire \z80_|execute_|pc_inc_hold~8_combout ;
|
|
wire \z80_|execute_|pc_inc_hold~13_combout ;
|
|
wire \z80_|execute_|pc_inc_hold~14_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ;
|
|
wire \z80_|execute_|pc_inc_hold~16_combout ;
|
|
wire \z80_|execute_|pc_inc_hold~22_combout ;
|
|
wire \z80_|execute_|pc_inc_hold~23_combout ;
|
|
wire \z80_|execute_|pc_inc_hold~24_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~41_combout ;
|
|
wire \z80_|execute_|pc_inc_hold~21_combout ;
|
|
wire \z80_|execute_|pc_inc_hold~25_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~69_combout ;
|
|
wire \z80_|execute_|pc_inc_hold~17_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~71_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~44_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~42_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~43_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~57_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~54_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~58_combout ;
|
|
wire \z80_|execute_|pc_inc_hold~18_combout ;
|
|
wire \z80_|execute_|pc_inc_hold~19_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~45_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~34_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~35_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~46_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~47_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~48_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~50_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~51_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~85_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~63_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~64_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~65_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~59_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~60_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~61_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~62_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~66_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~53_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~52_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~84_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~55_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~56_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~67_combout ;
|
|
wire \z80_|execute_|pc_inc_hold~20_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~83_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~68_combout ;
|
|
wire \z80_|address_latch_|Q[0]~feeder_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~72_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~73_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~74_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~75_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~76_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~80_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~81_combout ;
|
|
wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ;
|
|
wire \z80_|reg_file_|db_lo_as[0]~3_combout ;
|
|
wire \z80_|reg_file_|b2v_latch_af_lo|latch[0]~feeder_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[0]~13_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[0]~12_combout ;
|
|
wire \z80_|reg_file_|b2v_latch_de_lo|latch[0]~feeder_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[0]~10_combout ;
|
|
wire \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[0]~11_combout ;
|
|
wire \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[0]~14_combout ;
|
|
wire \z80_|reg_file_|b2v_latch_sp_lo|latch[0]~feeder_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[0]~15_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[0]~16_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[0]~17_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[0]~22_combout ;
|
|
wire \z80_|alu_control_|db[0]~9_combout ;
|
|
wire \z80_|alu_control_|db[0]~12_combout ;
|
|
wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[7]~84_combout ;
|
|
wire \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[7]~83_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[7]~88_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[7]~86_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[7]~87_combout ;
|
|
wire \z80_|reg_file_|b2v_latch_wz_lo|db[7]~0_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[7]~89_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[7]~85_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[7]~90_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[7]~91_combout ;
|
|
wire \z80_|reg_file_|db_lo_as[7]~22_combout ;
|
|
wire \z80_|reg_file_|db_lo_as[7]~23_combout ;
|
|
wire \z80_|reg_file_|db_lo_as[7]~24_combout ;
|
|
wire \z80_|address_latch_|Q[7]~feeder_combout ;
|
|
wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ;
|
|
wire \z80_|reg_file_|db_hi_as[0]~4_combout ;
|
|
wire \z80_|reg_file_|db_hi_as[0]~5_combout ;
|
|
wire \z80_|reg_file_|db_hi_as[0]~6_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[0]~23_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[0]~25_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[0]~27_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[0]~24_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[0]~26_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[0]~28_combout ;
|
|
wire \z80_|reg_file_|b2v_latch_af_hi|db[0]~11_combout ;
|
|
wire \z80_|reg_file_|b2v_latch_de_hi|latch[0]~feeder_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[0]~22_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[0]~29_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[0]~30_combout ;
|
|
wire \z80_|alu_|db[0]~13_combout ;
|
|
wire \z80_|alu_|db[0]~14_combout ;
|
|
wire \z80_|alu_|db_low[1]~10_combout ;
|
|
wire \z80_|alu_|db_low[1]~11_combout ;
|
|
wire \z80_|alu_|db_low[1]~8_combout ;
|
|
wire \z80_|alu_|db_low[1]~7_combout ;
|
|
wire \z80_|alu_|result_lo[1]~feeder_combout ;
|
|
wire \z80_|alu_|db_low[1]~9_combout ;
|
|
wire \z80_|alu_|db_low[1]~12_combout ;
|
|
wire \z80_|alu_|db[1]~8_combout ;
|
|
wire \z80_|alu_|db[1]~10_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[1]~12_combout ;
|
|
wire \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[1]~11_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[1]~10_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[1]~13_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[1]~14_combout ;
|
|
wire \z80_|reg_file_|b2v_latch_af_hi|db[1]~10_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[1]~9_combout ;
|
|
wire \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[1]~8_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[1]~15_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[1]~21_combout ;
|
|
wire \z80_|reg_file_|db_hi_as[1]~0_combout ;
|
|
wire \z80_|reg_file_|db_hi_as[1]~1_combout ;
|
|
wire \z80_|reg_file_|db_hi_as[1]~3_combout ;
|
|
wire \z80_|address_latch_|Q[9]~feeder_combout ;
|
|
wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ;
|
|
wire \z80_|reg_file_|db_hi_as[2]~7_combout ;
|
|
wire \z80_|reg_file_|db_hi_as[2]~8_combout ;
|
|
wire \z80_|reg_file_|db_hi_as[2]~9_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[2]~39_combout ;
|
|
wire \z80_|alu_|db[2]~15_combout ;
|
|
wire \z80_|alu_|db[2]~16_combout ;
|
|
wire \z80_|alu_control_|db[2]~27_combout ;
|
|
wire \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ;
|
|
wire \z80_|alu_flags_|flags_hf2~0_combout ;
|
|
wire \z80_|alu_flags_|flags_hf2~q ;
|
|
wire \z80_|alu_control_|db[2]~23_combout ;
|
|
wire \z80_|alu_control_|db[2]~29_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[2]~39_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[2]~35_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[2]~40_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[2]~41_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[2]~42_combout ;
|
|
wire \z80_|reg_file_|db_lo_as[2]~7_combout ;
|
|
wire \z80_|reg_file_|db_lo_as[2]~8_combout ;
|
|
wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ;
|
|
wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ;
|
|
wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ;
|
|
wire \z80_|reg_file_|db_lo_as[2]~9_combout ;
|
|
wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ;
|
|
wire \z80_|reg_file_|db_lo_as[3]~10_combout ;
|
|
wire \z80_|reg_file_|db_lo_as[3]~11_combout ;
|
|
wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ;
|
|
wire \z80_|reg_file_|db_lo_as[3]~12_combout ;
|
|
wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ;
|
|
wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ;
|
|
wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ;
|
|
wire \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ;
|
|
wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ;
|
|
wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ;
|
|
wire \z80_|reg_file_|db_hi_as[3]~12_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[3]~41_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[3]~45_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[3]~44_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[3]~43_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[3]~42_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[3]~46_combout ;
|
|
wire \z80_|reg_file_|b2v_latch_de_hi|latch[3]~feeder_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[3]~40_combout ;
|
|
wire \z80_|reg_file_|b2v_latch_af_hi|db[3]~13_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[3]~47_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[3]~48_combout ;
|
|
wire \z80_|alu_|db[3]~19_combout ;
|
|
wire \z80_|alu_|db[3]~20_combout ;
|
|
wire \z80_|alu_|db_low[2]~21_combout ;
|
|
wire \z80_|alu_|db_low[2]~22_combout ;
|
|
wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ;
|
|
wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~6_combout ;
|
|
wire \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~7_combout ;
|
|
wire \z80_|alu_|db_low[2]~18_combout ;
|
|
wire \z80_|alu_|db_low[2]~19_combout ;
|
|
wire \z80_|alu_|db_low[2]~20_combout ;
|
|
wire \z80_|alu_|db_low[2]~23_combout ;
|
|
wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~7_combout ;
|
|
wire \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~8_combout ;
|
|
wire \z80_|alu_|alu_op1[2]~1_combout ;
|
|
wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ;
|
|
wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ;
|
|
wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ;
|
|
wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ;
|
|
wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ;
|
|
wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ;
|
|
wire \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ;
|
|
wire \z80_|execute_|ctl_flags_hf_we~3_combout ;
|
|
wire \z80_|execute_|ctl_flags_hf_we~4_combout ;
|
|
wire \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ;
|
|
wire \z80_|alu_flags_|DFFE_inst_latch_hf~q ;
|
|
wire \z80_|alu_flags_|flags_hf~combout ;
|
|
wire \z80_|alu_control_|db[4]~30_combout ;
|
|
wire \z80_|alu_control_|db[4]~31_combout ;
|
|
wire \z80_|alu_control_|db[4]~32_combout ;
|
|
wire \z80_|alu_|db[4]~17_combout ;
|
|
wire \z80_|alu_|db[4]~18_combout ;
|
|
wire \z80_|alu_|db_low[3]~13_combout ;
|
|
wire \z80_|alu_|db_low[3]~14_combout ;
|
|
wire \z80_|alu_|db_low[3]~17_combout ;
|
|
wire \z80_|alu_|db_low[3]~25_combout ;
|
|
wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~4_combout ;
|
|
wire \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~5_combout ;
|
|
wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ;
|
|
wire \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ;
|
|
wire \z80_|alu_|alu_op2[3]~2_combout ;
|
|
wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ;
|
|
wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ;
|
|
wire \z80_|alu_|db_high[3]~3_combout ;
|
|
wire \z80_|alu_|db_high[3]~4_combout ;
|
|
wire \z80_|alu_|db_high[3]~5_combout ;
|
|
wire \z80_|alu_|db_high[3]~2_combout ;
|
|
wire \z80_|alu_|db_high[3]~6_combout ;
|
|
wire \z80_|alu_|db_high[3]~7_combout ;
|
|
wire \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ;
|
|
wire \z80_|alu_flags_|DFFE_inst_latch_sf~q ;
|
|
wire \z80_|execute_|ctl_alu_sel_op2_neg~5_combout ;
|
|
wire \z80_|execute_|ctl_alu_sel_op2_neg~7_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ;
|
|
wire \z80_|execute_|ctl_alu_sel_op2_neg~6_combout ;
|
|
wire \z80_|execute_|ctl_alu_sel_op2_neg~8_combout ;
|
|
wire \z80_|execute_|ctl_alu_sel_op2_neg~11_combout ;
|
|
wire \z80_|execute_|ctl_alu_sel_op2_neg~12_combout ;
|
|
wire \z80_|execute_|ctl_alu_sel_op2_neg~15_combout ;
|
|
wire \z80_|alu_|alu_op2[2]~0_combout ;
|
|
wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ;
|
|
wire \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ;
|
|
wire \z80_|alu_control_|DFFE_latch_pf_tmp~q ;
|
|
wire \z80_|alu_|alu_parity_out~0_combout ;
|
|
wire \z80_|alu_|alu_parity_out~1_combout ;
|
|
wire \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ;
|
|
wire \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ;
|
|
wire \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ;
|
|
wire \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ;
|
|
wire \z80_|decode_state_|DFFE_instNonRep~2_combout ;
|
|
wire \z80_|decode_state_|DFFE_instNonRep~1_combout ;
|
|
wire \z80_|decode_state_|DFFE_instNonRep~3_combout ;
|
|
wire \z80_|decode_state_|DFFE_instNonRep~0_combout ;
|
|
wire \z80_|decode_state_|DFFE_instNonRep~4_combout ;
|
|
wire \z80_|decode_state_|DFFE_instNonRep~5_combout ;
|
|
wire \z80_|decode_state_|DFFE_instNonRep~q ;
|
|
wire \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ;
|
|
wire \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ;
|
|
wire \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ;
|
|
wire \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ;
|
|
wire \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ;
|
|
wire \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ;
|
|
wire \z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ;
|
|
wire \z80_|alu_flags_|DFFE_inst_latch_pf~q ;
|
|
wire \z80_|alu_control_|sel[1]~0_combout ;
|
|
wire \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ;
|
|
wire \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ;
|
|
wire \z80_|alu_control_|flags_cond_true~0_combout ;
|
|
wire \z80_|alu_control_|flags_cond_true~q ;
|
|
wire \z80_|execute_|ctl_reg_sel_wz~20_combout ;
|
|
wire \z80_|execute_|ctl_sw_4d~1_combout ;
|
|
wire \z80_|execute_|ctl_sw_4d~6_combout ;
|
|
wire \z80_|reg_file_|db_lo_as[1]~4_combout ;
|
|
wire \z80_|reg_file_|db_lo_as[1]~5_combout ;
|
|
wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ;
|
|
wire \z80_|reg_file_|db_lo_as[1]~6_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[1]~29_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[1]~28_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[1]~26_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[1]~27_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[1]~30_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[1]~24_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[1]~23_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[1]~25_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[1]~31_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[1]~32_combout ;
|
|
wire \z80_|reg_file_|db_lo_ds[1]~1_combout ;
|
|
wire \z80_|alu_control_|db[1]~25_combout ;
|
|
wire \z80_|alu_control_|db[1]~24_combout ;
|
|
wire \z80_|alu_control_|db[1]~26_combout ;
|
|
wire \z80_|bus_control_|db[1]~10_combout ;
|
|
wire \z80_|execute_|nextM~4_combout ;
|
|
wire \z80_|execute_|ctl_iorw~12_combout ;
|
|
wire \z80_|execute_|ctl_iorw~8_combout ;
|
|
wire \z80_|execute_|ctl_iorw~9_combout ;
|
|
wire \z80_|memory_ifc_|DFFE_iorq_ff1~q ;
|
|
wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ;
|
|
wire \z80_|memory_ifc_|wait_iorq~feeder_combout ;
|
|
wire \z80_|memory_ifc_|wait_iorq~q ;
|
|
wire \z80_|memory_ifc_|DFFE_iorq_ff4~q ;
|
|
wire \z80_|memory_ifc_|iorq~0_combout ;
|
|
wire \z80_|memory_ifc_|DFFE_m1_ff1~q ;
|
|
wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ;
|
|
wire \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ;
|
|
wire \z80_|memory_ifc_|DFFE_m1_ff3~q ;
|
|
wire \z80_|memory_ifc_|nRD_out~0_combout ;
|
|
wire \z80_|execute_|fIORead~0_combout ;
|
|
wire \z80_|execute_|fIORead~1_combout ;
|
|
wire \z80_|execute_|fIORead~2_combout ;
|
|
wire \z80_|execute_|fIOWrite~1_combout ;
|
|
wire \z80_|execute_|fIORead~3_combout ;
|
|
wire \z80_|execute_|ctl_mRead~30_combout ;
|
|
wire \z80_|execute_|ctl_mRead~31_combout ;
|
|
wire \z80_|execute_|nextM~3_combout ;
|
|
wire \z80_|execute_|ctl_mRead~29_combout ;
|
|
wire \z80_|execute_|setM1~58_combout ;
|
|
wire \z80_|execute_|setM1~38_combout ;
|
|
wire \z80_|execute_|fMRead~4_combout ;
|
|
wire \z80_|execute_|setM1~39_combout ;
|
|
wire \z80_|execute_|setM1~40_combout ;
|
|
wire \z80_|execute_|ctl_mRead~32_combout ;
|
|
wire \z80_|execute_|ctl_mRead~33_combout ;
|
|
wire \z80_|memory_ifc_|DFFE_mrd_ff1~q ;
|
|
wire \z80_|memory_ifc_|wait_mrd~feeder_combout ;
|
|
wire \z80_|memory_ifc_|wait_mrd~q ;
|
|
wire \z80_|memory_ifc_|DFFE_mrd_ff3~q ;
|
|
wire \z80_|memory_ifc_|nRD_out~1_combout ;
|
|
wire \z80_|memory_ifc_|nRD_out~2_combout ;
|
|
wire \z80_|execute_|fIOWrite~3_combout ;
|
|
wire \z80_|execute_|fIOWrite~4_combout ;
|
|
wire \z80_|execute_|fIOWrite~2_combout ;
|
|
wire \z80_|execute_|fIOWrite~5_combout ;
|
|
wire \z80_|execute_|ctl_mWrite~15_combout ;
|
|
wire \z80_|execute_|ctl_mWrite~12_combout ;
|
|
wire \z80_|execute_|ctl_mWrite~13_combout ;
|
|
wire \z80_|execute_|ctl_mWrite~14_combout ;
|
|
wire \z80_|execute_|ctl_mWrite~16_combout ;
|
|
wire \z80_|memory_ifc_|DFFE_mwr_ff1~q ;
|
|
wire \z80_|memory_ifc_|wait_mwr~feeder_combout ;
|
|
wire \z80_|memory_ifc_|wait_mwr~q ;
|
|
wire \z80_|memory_ifc_|mwr_wr~q ;
|
|
wire \z80_|memory_ifc_|nWR_out~0_combout ;
|
|
wire \Equal2~1_combout ;
|
|
wire \z80_|execute_|fMWrite~3_combout ;
|
|
wire \z80_|execute_|fMWrite~4_combout ;
|
|
wire \z80_|execute_|fMWrite~0_combout ;
|
|
wire \z80_|execute_|fMWrite~2_combout ;
|
|
wire \z80_|pin_control_|bus_db_pin_oe~3_combout ;
|
|
wire \z80_|execute_|fMWrite~8_combout ;
|
|
wire \z80_|execute_|fMWrite~7_combout ;
|
|
wire \z80_|pin_control_|bus_db_pin_oe~16_combout ;
|
|
wire \z80_|pin_control_|bus_db_pin_oe~8_combout ;
|
|
wire \z80_|execute_|fMWrite~6_combout ;
|
|
wire \z80_|pin_control_|bus_db_pin_oe~9_combout ;
|
|
wire \z80_|pin_control_|bus_db_pin_oe~7_combout ;
|
|
wire \z80_|pin_control_|bus_db_pin_oe~10_combout ;
|
|
wire \z80_|pin_control_|bus_db_pin_oe~11_combout ;
|
|
wire \z80_|execute_|fMWrite~5_combout ;
|
|
wire \z80_|pin_control_|bus_db_pin_oe~6_combout ;
|
|
wire \z80_|pin_control_|bus_db_pin_oe~12_combout ;
|
|
wire \z80_|pin_control_|bus_db_pin_oe~4_combout ;
|
|
wire \z80_|pin_control_|bus_db_pin_oe~5_combout ;
|
|
wire \z80_|pin_control_|bus_db_pin_oe~13_combout ;
|
|
wire \z80_|pin_control_|bus_db_pin_oe~14_combout ;
|
|
wire \z80_|pin_control_|bus_db_pin_oe~2_combout ;
|
|
wire \z80_|pin_control_|bus_db_pin_oe~15_combout ;
|
|
wire \z80_|clk_delay_|DFF_inst5~feeder_combout ;
|
|
wire \z80_|clk_delay_|DFF_inst5~q ;
|
|
wire \z80_|memory_ifc_|wait_iorqinta~q ;
|
|
wire \z80_|memory_ifc_|DFFE_intr_ff3~q ;
|
|
wire \z80_|memory_ifc_|nIORQ_out~0_combout ;
|
|
wire \Equal2~0_combout ;
|
|
wire \z80_|execute_|ctl_apin_mux~2_combout ;
|
|
wire \z80_|address_pins_|DFFE_apin_latch[10]~10_combout ;
|
|
wire \z80_|execute_|ctl_apin_mux2~0_combout ;
|
|
wire \z80_|pin_control_|bus_ab_pin_we~0_combout ;
|
|
wire \z80_|pin_control_|bus_ab_pin_we~1_combout ;
|
|
wire \PS2_DAT~input_o ;
|
|
wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ;
|
|
wire \KEY[0]~input_o ;
|
|
wire \reset~combout ;
|
|
wire \reset~clkctrl_outclk ;
|
|
wire \ula_|ps2_keyboard_|bit_count~3_combout ;
|
|
wire \PS2_CLK~input_o ;
|
|
wire \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ;
|
|
wire \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ;
|
|
wire \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ;
|
|
wire \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ;
|
|
wire \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ;
|
|
wire \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ;
|
|
wire \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ;
|
|
wire \ula_|ps2_keyboard_|Equal0~0_combout ;
|
|
wire \ula_|ps2_keyboard_|Equal0~1_combout ;
|
|
wire \ula_|ps2_keyboard_|clk_filter[0]~0_combout ;
|
|
wire \ula_|ps2_keyboard_|ps2_clk_in~0_combout ;
|
|
wire \ula_|ps2_keyboard_|ps2_clk_in~q ;
|
|
wire \ula_|ps2_keyboard_|clk_edge~0_combout ;
|
|
wire \ula_|ps2_keyboard_|clk_edge~q ;
|
|
wire \ula_|ps2_keyboard_|bit_count~1_combout ;
|
|
wire \ula_|ps2_keyboard_|bit_count~2_combout ;
|
|
wire \ula_|ps2_keyboard_|bit_count~0_combout ;
|
|
wire \ula_|ps2_keyboard_|always1~0_combout ;
|
|
wire \ula_|ps2_keyboard_|LessThan0~0_combout ;
|
|
wire \ula_|ps2_keyboard_|shiftreg[0]~0_combout ;
|
|
wire \ula_|ps2_keyboard_|shiftreg[7]~feeder_combout ;
|
|
wire \ula_|ps2_keyboard_|shiftreg[0]~feeder_combout ;
|
|
wire \ula_|ps2_keyboard_|WideXor0~0_combout ;
|
|
wire \ula_|ps2_keyboard_|WideXor0~1_combout ;
|
|
wire \ula_|ps2_keyboard_|WideXor0~2_combout ;
|
|
wire \ula_|ps2_keyboard_|scan_code_ready~0_combout ;
|
|
wire \ula_|ps2_keyboard_|scan_code_ready~q ;
|
|
wire \ula_|zx_keyboard_|Equal0~0_combout ;
|
|
wire \ula_|zx_keyboard_|Equal0~1_combout ;
|
|
wire \ula_|zx_keyboard_|released~0_combout ;
|
|
wire \ula_|zx_keyboard_|released~q ;
|
|
wire \ula_|zx_keyboard_|extended~0_combout ;
|
|
wire \ula_|zx_keyboard_|extended~q ;
|
|
wire \ula_|zx_keyboard_|keys[7][1]~21_combout ;
|
|
wire \ula_|zx_keyboard_|keys[5][4]~22_combout ;
|
|
wire \ula_|zx_keyboard_|keys[1][4]~23_combout ;
|
|
wire \ula_|zx_keyboard_|keys[2][1]~24_combout ;
|
|
wire \ula_|zx_keyboard_|keys[2][1]~25_combout ;
|
|
wire \ula_|zx_keyboard_|keys[2][1]~q ;
|
|
wire \ula_|zx_keyboard_|key_row~0_combout ;
|
|
wire \ula_|zx_keyboard_|keys[3][1]~26_combout ;
|
|
wire \ula_|zx_keyboard_|keys[3][1]~27_combout ;
|
|
wire \ula_|zx_keyboard_|keys[3][1]~28_combout ;
|
|
wire \ula_|zx_keyboard_|keys[3][1]~q ;
|
|
wire \z80_|address_pins_|DFFE_apin_latch[11]~11_combout ;
|
|
wire \z80_|address_pins_|abus[11]~19_combout ;
|
|
wire \ula_|zx_keyboard_|keys[7][4]~17_combout ;
|
|
wire \ula_|zx_keyboard_|keys[6][4]~18_combout ;
|
|
wire \ula_|zx_keyboard_|keys[1][1]~19_combout ;
|
|
wire \ula_|zx_keyboard_|keys[1][1]~20_combout ;
|
|
wire \ula_|zx_keyboard_|keys[1][1]~q ;
|
|
wire \z80_|address_pins_|DFFE_apin_latch[9]~9_combout ;
|
|
wire \z80_|address_pins_|abus[9]~17_combout ;
|
|
wire \ula_|zx_keyboard_|keys[0][0]~13_combout ;
|
|
wire \ula_|zx_keyboard_|shifted~2_combout ;
|
|
wire \ula_|zx_keyboard_|keys[0][1]~14_combout ;
|
|
wire \ula_|zx_keyboard_|keys[0][1]~15_combout ;
|
|
wire \ula_|zx_keyboard_|WideOr17~0_combout ;
|
|
wire \ula_|zx_keyboard_|shifted~5_combout ;
|
|
wire \ula_|zx_keyboard_|shifted~4_combout ;
|
|
wire \ula_|zx_keyboard_|shifted~q ;
|
|
wire \ula_|zx_keyboard_|keys[0][1]~12_combout ;
|
|
wire \ula_|zx_keyboard_|keys[0][1]~16_combout ;
|
|
wire \ula_|zx_keyboard_|keys[0][1]~q ;
|
|
wire \z80_|address_pins_|DFFE_apin_latch[8]~8_combout ;
|
|
wire \z80_|address_pins_|abus[8]~18_combout ;
|
|
wire \D[1]~26_combout ;
|
|
wire \D[1]~27_combout ;
|
|
wire \z80_|address_pins_|DFFE_apin_latch[12]~12_combout ;
|
|
wire \z80_|address_pins_|abus[12]~21_combout ;
|
|
wire \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ;
|
|
wire \z80_|address_pins_|DFFE_apin_latch[13]~13_combout ;
|
|
wire \z80_|address_pins_|abus[13]~20_combout ;
|
|
wire \ula_|zx_keyboard_|keys[5][1]~36_combout ;
|
|
wire \ula_|zx_keyboard_|keys[5][1]~34_combout ;
|
|
wire \ula_|zx_keyboard_|keys[5][1]~35_combout ;
|
|
wire \ula_|zx_keyboard_|keys[5][1]~33_combout ;
|
|
wire \ula_|zx_keyboard_|keys[5][1]~37_combout ;
|
|
wire \ula_|zx_keyboard_|keys[5][1]~q ;
|
|
wire \ula_|zx_keyboard_|keys[4][1]~29_combout ;
|
|
wire \ula_|zx_keyboard_|keys[7][2]~30_combout ;
|
|
wire \ula_|zx_keyboard_|keys[5][2]~31_combout ;
|
|
wire \ula_|zx_keyboard_|keys[4][1]~32_combout ;
|
|
wire \ula_|zx_keyboard_|keys[4][1]~q ;
|
|
wire \D[1]~28_combout ;
|
|
wire \z80_|address_pins_|abus[0]~16_combout ;
|
|
wire \z80_|address_pins_|DFFE_apin_latch[14]~14_combout ;
|
|
wire \z80_|address_pins_|abus[14]~23_combout ;
|
|
wire \ula_|zx_keyboard_|keys[6][1]~40_combout ;
|
|
wire \ula_|zx_keyboard_|keys[6][1]~41_combout ;
|
|
wire \ula_|zx_keyboard_|keys[6][1]~39_combout ;
|
|
wire \ula_|zx_keyboard_|keys[6][1]~38_combout ;
|
|
wire \ula_|zx_keyboard_|keys[6][1]~42_combout ;
|
|
wire \ula_|zx_keyboard_|keys[6][1]~q ;
|
|
wire \ula_|zx_keyboard_|WideOr16~4_combout ;
|
|
wire \ula_|zx_keyboard_|WideOr16~2_combout ;
|
|
wire \ula_|zx_keyboard_|WideOr16~7_combout ;
|
|
wire \ula_|zx_keyboard_|WideOr16~5_combout ;
|
|
wire \ula_|zx_keyboard_|WideOr16~6_combout ;
|
|
wire \ula_|zx_keyboard_|keys[7][1]~43_combout ;
|
|
wire \ula_|zx_keyboard_|keys[7][1]~44_combout ;
|
|
wire \ula_|zx_keyboard_|keys[7][1]~q ;
|
|
wire \z80_|address_pins_|DFFE_apin_latch[15]~15_combout ;
|
|
wire \z80_|address_pins_|abus[15]~22_combout ;
|
|
wire \D[1]~29_combout ;
|
|
wire \D[1]~30_combout ;
|
|
wire \ExtRamWE~0_combout ;
|
|
wire \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ;
|
|
wire \z80_|address_pins_|DFFE_apin_latch[1]~1_combout ;
|
|
wire \z80_|address_pins_|abus[1]~25_combout ;
|
|
wire \z80_|address_pins_|DFFE_apin_latch[2]~2_combout ;
|
|
wire \z80_|address_pins_|abus[2]~26_combout ;
|
|
wire \z80_|address_pins_|DFFE_apin_latch[3]~3_combout ;
|
|
wire \z80_|address_pins_|abus[3]~27_combout ;
|
|
wire \z80_|address_pins_|DFFE_apin_latch[4]~4_combout ;
|
|
wire \z80_|address_pins_|abus[4]~28_combout ;
|
|
wire \z80_|address_pins_|DFFE_apin_latch[5]~5_combout ;
|
|
wire \z80_|address_pins_|abus[5]~29_combout ;
|
|
wire \z80_|address_pins_|DFFE_apin_latch[6]~6_combout ;
|
|
wire \z80_|address_pins_|abus[6]~30_combout ;
|
|
wire \z80_|address_pins_|DFFE_apin_latch[7]~7_combout ;
|
|
wire \z80_|address_pins_|abus[7]~31_combout ;
|
|
wire \z80_|address_pins_|abus[10]~24_combout ;
|
|
wire \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ;
|
|
wire \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ;
|
|
wire \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ;
|
|
wire \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ;
|
|
wire \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ;
|
|
wire \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ;
|
|
wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ;
|
|
wire \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ;
|
|
wire \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ;
|
|
wire \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ;
|
|
wire \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ;
|
|
wire \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ;
|
|
wire \CLOCK_50~inputclkctrl_outclk ;
|
|
wire \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ;
|
|
wire \Selector3~0_combout ;
|
|
wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ;
|
|
wire \~GND~combout ;
|
|
wire \ula_|video_|vram_address[0]~feeder_combout ;
|
|
wire \ula_|video_|vram_address~0_combout ;
|
|
wire \ula_|video_|vram_address[1]~feeder_combout ;
|
|
wire \ula_|video_|vram_address[2]~4_combout ;
|
|
wire \ula_|video_|Add3~0_combout ;
|
|
wire \ula_|video_|Add3~1_combout ;
|
|
wire \ula_|video_|Add4~1 ;
|
|
wire \ula_|video_|Add4~3 ;
|
|
wire \ula_|video_|Add4~5 ;
|
|
wire \ula_|video_|Add4~6_combout ;
|
|
wire \ula_|video_|Add4~7 ;
|
|
wire \ula_|video_|Add4~8_combout ;
|
|
wire \ula_|video_|Add4~9 ;
|
|
wire \ula_|video_|Add4~10_combout ;
|
|
wire \ula_|video_|Add4~0_combout ;
|
|
wire \ula_|video_|Add4~11 ;
|
|
wire \ula_|video_|Add4~12_combout ;
|
|
wire \ula_|video_|Selector6~0_combout ;
|
|
wire \ula_|video_|vram_address[9]~1_combout ;
|
|
wire \ula_|video_|Add4~2_combout ;
|
|
wire \ula_|video_|Add4~13 ;
|
|
wire \ula_|video_|Add4~14_combout ;
|
|
wire \ula_|video_|Selector5~0_combout ;
|
|
wire \ula_|video_|Add4~4_combout ;
|
|
wire \ula_|video_|vram_address[10]~2_combout ;
|
|
wire \ula_|video_|vram_address[10]~3_combout ;
|
|
wire \ula_|video_|Selector3~0_combout ;
|
|
wire \ula_|video_|Selector2~0_combout ;
|
|
wire \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ;
|
|
wire \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ;
|
|
wire \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ;
|
|
wire \Selector1~0_combout ;
|
|
wire \Selector1~1_combout ;
|
|
wire \D[1]~81_combout ;
|
|
wire \D[1]~31_combout ;
|
|
wire \D[1]~32_combout ;
|
|
wire \z80_|pin_control_|bus_db_pin_re~2_combout ;
|
|
wire \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ;
|
|
wire \z80_|bus_control_|db[1]~11_combout ;
|
|
wire \z80_|pla_decode_|Equal2~0_combout ;
|
|
wire \z80_|execute_|ctl_mRead~15_combout ;
|
|
wire \z80_|execute_|ctl_inc_cy~39_combout ;
|
|
wire \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ;
|
|
wire \z80_|execute_|ctl_sw_4u~4_combout ;
|
|
wire \z80_|execute_|ctl_reg_sel_wz~16_combout ;
|
|
wire \z80_|execute_|ctl_reg_sel_wz~17_combout ;
|
|
wire \z80_|execute_|ctl_sw_4u~5_combout ;
|
|
wire \z80_|execute_|ctl_sw_4u~6_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[3]~44_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[3]~43_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[3]~46_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[3]~47_combout ;
|
|
wire \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[3]~49_combout ;
|
|
wire \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[3]~45_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[3]~48_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[3]~50_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[3]~51_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp0[3]~52_combout ;
|
|
wire \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ;
|
|
wire \z80_|execute_|ctl_flags_xy_we~15_combout ;
|
|
wire \z80_|execute_|ctl_flags_xy_we~16_combout ;
|
|
wire \z80_|execute_|ctl_flags_xy_we~17_combout ;
|
|
wire \z80_|execute_|ctl_flags_xy_we~18_combout ;
|
|
wire \z80_|alu_flags_|flags_xf~q ;
|
|
wire \z80_|alu_control_|db[3]~33_combout ;
|
|
wire \z80_|sw1_|db_down[3]~2_combout ;
|
|
wire \z80_|alu_control_|db[3]~34_combout ;
|
|
wire \z80_|alu_control_|db[3]~35_combout ;
|
|
wire \ula_|zx_keyboard_|keys[3][0]~75_combout ;
|
|
wire \ula_|zx_keyboard_|Selector5~0_combout ;
|
|
wire \ula_|zx_keyboard_|Selector5~1_combout ;
|
|
wire \ula_|zx_keyboard_|keys[4][3]~132_combout ;
|
|
wire \ula_|zx_keyboard_|keys[4][3]~106_combout ;
|
|
wire \ula_|zx_keyboard_|keys[4][3]~107_combout ;
|
|
wire \ula_|zx_keyboard_|keys[4][3]~133_combout ;
|
|
wire \ula_|zx_keyboard_|keys[4][3]~108_combout ;
|
|
wire \ula_|zx_keyboard_|keys[4][3]~q ;
|
|
wire \ula_|zx_keyboard_|keys[5][3]~104_combout ;
|
|
wire \ula_|zx_keyboard_|keys[5][3]~105_combout ;
|
|
wire \ula_|zx_keyboard_|keys[5][3]~q ;
|
|
wire \D[3]~55_combout ;
|
|
wire \ula_|zx_keyboard_|keys[6][4]~46_combout ;
|
|
wire \ula_|zx_keyboard_|keys[5][4]~62_combout ;
|
|
wire \ula_|zx_keyboard_|keys[3][3]~102_combout ;
|
|
wire \ula_|zx_keyboard_|keys[3][3]~103_combout ;
|
|
wire \ula_|zx_keyboard_|keys[3][3]~q ;
|
|
wire \ula_|zx_keyboard_|keys[0][4]~96_combout ;
|
|
wire \ula_|zx_keyboard_|keys[2][4]~94_combout ;
|
|
wire \ula_|zx_keyboard_|keys[0][3]~95_combout ;
|
|
wire \ula_|zx_keyboard_|keys[0][3]~97_combout ;
|
|
wire \ula_|zx_keyboard_|keys[0][3]~q ;
|
|
wire \ula_|zx_keyboard_|keys[6][4]~45_combout ;
|
|
wire \ula_|zx_keyboard_|keys[1][3]~92_combout ;
|
|
wire \ula_|zx_keyboard_|keys[1][3]~93_combout ;
|
|
wire \ula_|zx_keyboard_|keys[1][3]~q ;
|
|
wire \D[3]~53_combout ;
|
|
wire \ula_|zx_keyboard_|keys[2][3]~99_combout ;
|
|
wire \ula_|zx_keyboard_|keys[2][3]~100_combout ;
|
|
wire \ula_|zx_keyboard_|keys[2][3]~98_combout ;
|
|
wire \ula_|zx_keyboard_|keys[2][3]~101_combout ;
|
|
wire \ula_|zx_keyboard_|keys[2][3]~q ;
|
|
wire \ula_|zx_keyboard_|key_row~3_combout ;
|
|
wire \D[3]~54_combout ;
|
|
wire \ula_|zx_keyboard_|keys[0][4]~109_combout ;
|
|
wire \ula_|zx_keyboard_|keys[7][2]~60_combout ;
|
|
wire \ula_|zx_keyboard_|keys[7][3]~110_combout ;
|
|
wire \ula_|zx_keyboard_|keys[7][3]~111_combout ;
|
|
wire \ula_|zx_keyboard_|keys[7][3]~112_combout ;
|
|
wire \ula_|zx_keyboard_|keys[7][3]~q ;
|
|
wire \ula_|zx_keyboard_|Selector13~0_combout ;
|
|
wire \ula_|zx_keyboard_|keys[6][3]~113_combout ;
|
|
wire \ula_|zx_keyboard_|keys[6][3]~114_combout ;
|
|
wire \ula_|zx_keyboard_|keys[6][3]~135_combout ;
|
|
wire \ula_|zx_keyboard_|keys[6][3]~136_combout ;
|
|
wire \ula_|zx_keyboard_|keys[6][3]~q ;
|
|
wire \D[3]~56_combout ;
|
|
wire \D[3]~57_combout ;
|
|
wire \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ;
|
|
wire \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ;
|
|
wire \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ;
|
|
wire \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ;
|
|
wire \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ;
|
|
wire \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ;
|
|
wire \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ;
|
|
wire \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ;
|
|
wire \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ;
|
|
wire \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ;
|
|
wire \Selector3~1_combout ;
|
|
wire \Selector3~2_combout ;
|
|
wire \D[3]~85_combout ;
|
|
wire \D[3]~73_combout ;
|
|
wire \D[3]~74_combout ;
|
|
wire \z80_|bus_control_|db[3]~20_combout ;
|
|
wire \z80_|bus_control_|db[3]~21_combout ;
|
|
wire \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ;
|
|
wire \z80_|interrupts_|im2~q ;
|
|
wire \z80_|execute_|ctl_mRead~10_combout ;
|
|
wire \z80_|execute_|ctl_sw_mask543_en~0_combout ;
|
|
wire \z80_|alu_control_|db[7]~16_combout ;
|
|
wire \z80_|alu_control_|db[7]~17_combout ;
|
|
wire \z80_|alu_control_|db[7]~18_combout ;
|
|
wire \z80_|alu_control_|db[7]~19_combout ;
|
|
wire \z80_|bus_control_|db[7]~5_combout ;
|
|
wire \D[5]~67_combout ;
|
|
wire \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ;
|
|
wire \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ;
|
|
wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout ;
|
|
wire \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ;
|
|
wire \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ;
|
|
wire \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout ;
|
|
wire \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ;
|
|
wire \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ;
|
|
wire \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ;
|
|
wire \Mux0~0_combout ;
|
|
wire \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ;
|
|
wire \Mux0~1_combout ;
|
|
wire \D[7]~89_combout ;
|
|
wire \D[7]~72_combout ;
|
|
wire \D[0]~84_combout ;
|
|
wire \D[7]~80_combout ;
|
|
wire \z80_|bus_control_|db[7]~7_combout ;
|
|
wire \z80_|pla_decode_|Equal6~0_combout ;
|
|
wire \z80_|pla_decode_|Equal12~0_combout ;
|
|
wire \z80_|execute_|ctl_mRead~16_combout ;
|
|
wire \z80_|execute_|fMRead~24_combout ;
|
|
wire \z80_|execute_|fMRead~25_combout ;
|
|
wire \z80_|execute_|ctl_mRead~21_combout ;
|
|
wire \z80_|execute_|fMRead~16_combout ;
|
|
wire \z80_|execute_|fMRead~14_combout ;
|
|
wire \z80_|execute_|fMRead~15_combout ;
|
|
wire \z80_|execute_|fMRead~12_combout ;
|
|
wire \z80_|execute_|fMRead~11_combout ;
|
|
wire \z80_|execute_|fMRead~13_combout ;
|
|
wire \z80_|execute_|fMRead~17_combout ;
|
|
wire \z80_|execute_|fMRead~22_combout ;
|
|
wire \z80_|execute_|fMRead~27_combout ;
|
|
wire \z80_|execute_|fMRead~37_combout ;
|
|
wire \z80_|execute_|fMRead~31_combout ;
|
|
wire \z80_|execute_|fMRead~29_combout ;
|
|
wire \z80_|execute_|fMRead~30_combout ;
|
|
wire \z80_|execute_|fMRead~28_combout ;
|
|
wire \z80_|execute_|fMRead~32_combout ;
|
|
wire \z80_|execute_|fMRead~33_combout ;
|
|
wire \z80_|execute_|fMRead~23_combout ;
|
|
wire \z80_|execute_|fMRead~34_combout ;
|
|
wire \z80_|execute_|fMRead~35_combout ;
|
|
wire \z80_|execute_|ctl_reg_sel_pc~19_combout ;
|
|
wire \z80_|execute_|fMRead~36_combout ;
|
|
wire \z80_|pin_control_|bus_db_pin_re~combout ;
|
|
wire \ula_|zx_keyboard_|keys[2][4]~118_combout ;
|
|
wire \ula_|zx_keyboard_|keys[2][4]~119_combout ;
|
|
wire \ula_|zx_keyboard_|keys[2][4]~120_combout ;
|
|
wire \ula_|zx_keyboard_|keys[2][4]~q ;
|
|
wire \ula_|zx_keyboard_|keys[3][4]~129_combout ;
|
|
wire \ula_|zx_keyboard_|keys[3][4]~116_combout ;
|
|
wire \ula_|zx_keyboard_|keys[3][4]~134_combout ;
|
|
wire \ula_|zx_keyboard_|keys[3][4]~117_combout ;
|
|
wire \ula_|zx_keyboard_|keys[3][4]~q ;
|
|
wire \D[4]~60_combout ;
|
|
wire \ula_|zx_keyboard_|Equal0~2_combout ;
|
|
wire \ula_|zx_keyboard_|keys[1][4]~121_combout ;
|
|
wire \ula_|zx_keyboard_|keys[1][4]~q ;
|
|
wire \ula_|zx_keyboard_|keys[0][4]~115_combout ;
|
|
wire \ula_|zx_keyboard_|keys[0][4]~q ;
|
|
wire \ula_|zx_keyboard_|key_row~4_combout ;
|
|
wire \D[4]~61_combout ;
|
|
wire \ula_|zx_keyboard_|keys[4][4]~124_combout ;
|
|
wire \ula_|zx_keyboard_|keys[4][4]~125_combout ;
|
|
wire \ula_|zx_keyboard_|keys[4][4]~126_combout ;
|
|
wire \ula_|zx_keyboard_|keys[4][4]~q ;
|
|
wire \ula_|zx_keyboard_|keys[5][4]~122_combout ;
|
|
wire \ula_|zx_keyboard_|keys[5][4]~123_combout ;
|
|
wire \ula_|zx_keyboard_|keys[5][4]~q ;
|
|
wire \D[4]~62_combout ;
|
|
wire \ula_|zx_keyboard_|keys[7][4]~49_combout ;
|
|
wire \ula_|zx_keyboard_|shifted~3_combout ;
|
|
wire \ula_|zx_keyboard_|keys[7][4]~127_combout ;
|
|
wire \ula_|zx_keyboard_|keys[7][4]~q ;
|
|
wire \ula_|zx_keyboard_|keys[6][4]~128_combout ;
|
|
wire \ula_|zx_keyboard_|keys[6][4]~q ;
|
|
wire \D[4]~63_combout ;
|
|
wire \D[4]~64_combout ;
|
|
wire \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ;
|
|
wire \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ;
|
|
wire \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ;
|
|
wire \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ;
|
|
wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ;
|
|
wire \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ;
|
|
wire \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ;
|
|
wire \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ;
|
|
wire \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ;
|
|
wire \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ;
|
|
wire \Selector4~0_combout ;
|
|
wire \Selector4~1_combout ;
|
|
wire \D[4]~86_combout ;
|
|
wire \D[4]~75_combout ;
|
|
wire \D[4]~76_combout ;
|
|
wire \z80_|bus_control_|db[4]~18_combout ;
|
|
wire \z80_|bus_control_|db[4]~19_combout ;
|
|
wire \z80_|pla_decode_|Equal32~0_combout ;
|
|
wire \z80_|pla_decode_|Equal41~1_combout ;
|
|
wire \z80_|pla_decode_|Equal41~2_combout ;
|
|
wire \z80_|pla_decode_|Equal36~0_combout ;
|
|
wire \z80_|execute_|ctl_state_tbl_cb_set~combout ;
|
|
wire \z80_|execute_|ctl_state_tbl_we~8_combout ;
|
|
wire \z80_|decode_state_|DFFE_instCB~q ;
|
|
wire \z80_|pla_decode_|Equal52~0_combout ;
|
|
wire \z80_|pla_decode_|Equal2~1_combout ;
|
|
wire \z80_|execute_|ctl_state_tbl_ed_set~combout ;
|
|
wire \z80_|decode_state_|DFFE_instED~q ;
|
|
wire \z80_|decode_state_|table_xx~0_combout ;
|
|
wire \z80_|pla_decode_|Equal34~0_combout ;
|
|
wire \z80_|execute_|ctl_reg_sel_pc~6_combout ;
|
|
wire \z80_|execute_|ctl_reg_sel_pc~5_combout ;
|
|
wire \z80_|execute_|ctl_reg_sel_pc~4_combout ;
|
|
wire \z80_|execute_|ctl_reg_sel_pc~2_combout ;
|
|
wire \z80_|execute_|ctl_reg_sel_pc~3_combout ;
|
|
wire \z80_|execute_|ctl_reg_sel_pc~7_combout ;
|
|
wire \z80_|execute_|ctl_reg_sel_pc~8_combout ;
|
|
wire \z80_|execute_|ctl_reg_sel_pc~9_combout ;
|
|
wire \z80_|execute_|ctl_reg_sel_pc~10_combout ;
|
|
wire \z80_|execute_|ctl_reg_sel_pc~16_combout ;
|
|
wire \z80_|execute_|ctl_reg_sel_pc~17_combout ;
|
|
wire \z80_|execute_|ctl_reg_sel_pc~15_combout ;
|
|
wire \z80_|execute_|ctl_reg_sel_pc~18_combout ;
|
|
wire \z80_|execute_|ctl_reg_sel_wz~19_combout ;
|
|
wire \z80_|reg_control_|reg_sel_pc~3_combout ;
|
|
wire \z80_|reg_control_|reg_sel_pc~combout ;
|
|
wire \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ;
|
|
wire \z80_|reg_file_|db_hi_as[0]~2_combout ;
|
|
wire \z80_|reg_file_|db_hi_as[5]~13_combout ;
|
|
wire \z80_|reg_file_|db_hi_as[5]~14_combout ;
|
|
wire \z80_|reg_file_|db_hi_as[5]~15_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[5]~50_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[5]~53_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[5]~54_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[5]~52_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[5]~51_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[5]~55_combout ;
|
|
wire \z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ;
|
|
wire \z80_|reg_file_|b2v_latch_de_hi|latch[5]~feeder_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[5]~49_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[5]~56_combout ;
|
|
wire \z80_|reg_file_|gdfx_temp1[5]~57_combout ;
|
|
wire \z80_|alu_|db[5]~23_combout ;
|
|
wire \z80_|alu_|db[5]~24_combout ;
|
|
wire \z80_|sw1_|db_down[5]~0_combout ;
|
|
wire \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ;
|
|
wire \z80_|alu_flags_|flags_yf~q ;
|
|
wire \z80_|alu_control_|db[5]~13_combout ;
|
|
wire \z80_|alu_control_|db[5]~14_combout ;
|
|
wire \z80_|alu_control_|db[5]~15_combout ;
|
|
wire \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ;
|
|
wire \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ;
|
|
wire \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ;
|
|
wire \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ;
|
|
wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ;
|
|
wire \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ;
|
|
wire \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ;
|
|
wire \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ;
|
|
wire \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ;
|
|
wire \ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ;
|
|
wire \Mux2~0_combout ;
|
|
wire \Mux2~1_combout ;
|
|
wire \D[5]~87_combout ;
|
|
wire \D[5]~68_combout ;
|
|
wire \D[5]~77_combout ;
|
|
wire \z80_|bus_control_|db[5]~14_combout ;
|
|
wire \z80_|bus_control_|db[5]~15_combout ;
|
|
wire \z80_|execute_|ctl_mRead~8_combout ;
|
|
wire \z80_|execute_|ctl_bus_db_we~8_combout ;
|
|
wire \z80_|execute_|ctl_bus_db_we~4_combout ;
|
|
wire \z80_|execute_|ctl_bus_db_we~6_combout ;
|
|
wire \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ;
|
|
wire \z80_|execute_|ctl_bus_db_we~3_combout ;
|
|
wire \z80_|execute_|ctl_bus_db_we~2_combout ;
|
|
wire \z80_|execute_|ctl_bus_db_we~7_combout ;
|
|
wire \ula_|zx_keyboard_|keys[5][0]~66_combout ;
|
|
wire \ula_|zx_keyboard_|keys[5][0]~80_combout ;
|
|
wire \ula_|zx_keyboard_|keys[5][0]~81_combout ;
|
|
wire \ula_|zx_keyboard_|keys[5][0]~82_combout ;
|
|
wire \ula_|zx_keyboard_|keys[5][0]~q ;
|
|
wire \ula_|zx_keyboard_|keys[4][0]~84_combout ;
|
|
wire \ula_|zx_keyboard_|keys[4][0]~83_combout ;
|
|
wire \ula_|zx_keyboard_|keys[4][0]~85_combout ;
|
|
wire \ula_|zx_keyboard_|keys[4][0]~q ;
|
|
wire \D[0]~42_combout ;
|
|
wire \ula_|zx_keyboard_|keys[1][0]~78_combout ;
|
|
wire \ula_|zx_keyboard_|keys[1][0]~79_combout ;
|
|
wire \ula_|zx_keyboard_|keys[1][0]~q ;
|
|
wire \ula_|zx_keyboard_|keys[3][0]~76_combout ;
|
|
wire \ula_|zx_keyboard_|keys[3][0]~q ;
|
|
wire \ula_|zx_keyboard_|keys[2][0]~77_combout ;
|
|
wire \ula_|zx_keyboard_|keys[2][0]~q ;
|
|
wire \D[0]~40_combout ;
|
|
wire \ula_|zx_keyboard_|WideOr0~0_combout ;
|
|
wire \ula_|zx_keyboard_|keys~71_combout ;
|
|
wire \ula_|zx_keyboard_|keys[4][3]~70_combout ;
|
|
wire \ula_|zx_keyboard_|keys[0][0]~72_combout ;
|
|
wire \ula_|zx_keyboard_|WideOr4~0_combout ;
|
|
wire \ula_|zx_keyboard_|keys~73_combout ;
|
|
wire \ula_|zx_keyboard_|keys[0][0]~74_combout ;
|
|
wire \ula_|zx_keyboard_|keys[0][0]~q ;
|
|
wire \ula_|zx_keyboard_|key_row~2_combout ;
|
|
wire \D[0]~41_combout ;
|
|
wire \ula_|zx_keyboard_|keys[6][0]~89_combout ;
|
|
wire \ula_|zx_keyboard_|keys[6][0]~90_combout ;
|
|
wire \ula_|zx_keyboard_|keys[6][0]~91_combout ;
|
|
wire \ula_|zx_keyboard_|keys[6][0]~q ;
|
|
wire \ula_|zx_keyboard_|keys[7][0]~131_combout ;
|
|
wire \ula_|zx_keyboard_|WideOr16~3_combout ;
|
|
wire \ula_|zx_keyboard_|keys[7][0]~86_combout ;
|
|
wire \ula_|zx_keyboard_|keys[7][0]~87_combout ;
|
|
wire \ula_|zx_keyboard_|keys[7][0]~88_combout ;
|
|
wire \ula_|zx_keyboard_|keys[7][0]~q ;
|
|
wire \D[0]~43_combout ;
|
|
wire \D[0]~44_combout ;
|
|
wire \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ;
|
|
wire \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ;
|
|
wire \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ;
|
|
wire \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ;
|
|
wire \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout ;
|
|
wire \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout ;
|
|
wire \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ;
|
|
wire \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ;
|
|
wire \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ;
|
|
wire \Selector2~0_combout ;
|
|
wire \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ;
|
|
wire \Selector2~1_combout ;
|
|
wire \D[0]~83_combout ;
|
|
wire \D[0]~45_combout ;
|
|
wire \D[0]~46_combout ;
|
|
wire \z80_|bus_control_|db[0]~16_combout ;
|
|
wire \z80_|bus_control_|db[0]~17_combout ;
|
|
wire \z80_|pla_decode_|Equal3~2_combout ;
|
|
wire \z80_|pla_decode_|Equal43~0_combout ;
|
|
wire \z80_|interrupts_|test1~2_combout ;
|
|
wire \z80_|interrupts_|test1~3_combout ;
|
|
wire \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ;
|
|
wire \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ;
|
|
wire \z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ;
|
|
wire \z80_|clk_delay_|hold_clk_iorq~combout ;
|
|
wire \z80_|sequencer_|DFFE_T4_ff~q ;
|
|
wire \z80_|execute_|ctl_eval_cond~0_combout ;
|
|
wire \z80_|execute_|ctl_mRead~27_combout ;
|
|
wire \z80_|execute_|ctl_mRead~26_combout ;
|
|
wire \z80_|execute_|ctl_mRead~28_combout ;
|
|
wire \z80_|execute_|nextM~6_combout ;
|
|
wire \z80_|execute_|nextM~7_combout ;
|
|
wire \z80_|execute_|nextM~8_combout ;
|
|
wire \z80_|execute_|nextM~9_combout ;
|
|
wire \z80_|execute_|nextM~10_combout ;
|
|
wire \z80_|execute_|nextM~12_combout ;
|
|
wire \z80_|execute_|nextM~15_combout ;
|
|
wire \z80_|execute_|nextM~13_combout ;
|
|
wire \z80_|execute_|setM1~41_combout ;
|
|
wire \z80_|execute_|nextM~5_combout ;
|
|
wire \z80_|execute_|nextM~14_combout ;
|
|
wire \z80_|sequencer_|ena_M~combout ;
|
|
wire \z80_|sequencer_|DFFE_T1_ff~q ;
|
|
wire \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ;
|
|
wire \z80_|sequencer_|DFFE_T2_ff~q ;
|
|
wire \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ;
|
|
wire \z80_|sequencer_|DFFE_T3_ff~q ;
|
|
wire \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ;
|
|
wire \z80_|execute_|ctl_66_oe~2_combout ;
|
|
wire \z80_|interrupts_|im1~q ;
|
|
wire \z80_|execute_|ctl_bus_ff_oe~0_combout ;
|
|
wire \z80_|execute_|ctl_bus_ff_oe~1_combout ;
|
|
wire \z80_|execute_|ctl_bus_zero_oe~0_combout ;
|
|
wire \z80_|bus_control_|db[0]~4_combout ;
|
|
wire \z80_|bus_control_|db[6]~8_combout ;
|
|
wire \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ;
|
|
wire \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ;
|
|
wire \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ;
|
|
wire \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ;
|
|
wire \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout ;
|
|
wire \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout ;
|
|
wire \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ;
|
|
wire \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ;
|
|
wire \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ;
|
|
wire \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ;
|
|
wire \Selector6~0_combout ;
|
|
wire \Selector6~1_combout ;
|
|
wire \D[6]~88_combout ;
|
|
wire \raw_loader_in~input_o ;
|
|
wire \D[6]~69_combout ;
|
|
wire \D[6]~78_combout ;
|
|
wire \D[6]~79_combout ;
|
|
wire \z80_|bus_control_|db[6]~9_combout ;
|
|
wire \z80_|execute_|ctl_ir_we~10_combout ;
|
|
wire \z80_|execute_|ctl_bus_db_oe~0_combout ;
|
|
wire \z80_|execute_|ctl_bus_db_oe~4_combout ;
|
|
wire \z80_|execute_|ctl_bus_db_oe~2_combout ;
|
|
wire \z80_|execute_|ctl_bus_db_oe~5_combout ;
|
|
wire \z80_|execute_|ctl_bus_db_oe~6_combout ;
|
|
wire \z80_|execute_|ctl_bus_db_oe~combout ;
|
|
wire \z80_|bus_control_|db[0]~6_combout ;
|
|
wire \ula_|zx_keyboard_|keys[7][2]~61_combout ;
|
|
wire \ula_|zx_keyboard_|keys[7][2]~63_combout ;
|
|
wire \ula_|zx_keyboard_|keys[7][2]~64_combout ;
|
|
wire \ula_|zx_keyboard_|keys[7][2]~65_combout ;
|
|
wire \ula_|zx_keyboard_|keys[7][2]~q ;
|
|
wire \ula_|zx_keyboard_|keys[6][2]~67_combout ;
|
|
wire \ula_|zx_keyboard_|keys[6][2]~68_combout ;
|
|
wire \ula_|zx_keyboard_|keys[6][2]~69_combout ;
|
|
wire \ula_|zx_keyboard_|keys[6][2]~q ;
|
|
wire \D[2]~36_combout ;
|
|
wire \ula_|zx_keyboard_|keys[4][2]~58_combout ;
|
|
wire \ula_|zx_keyboard_|keys[4][2]~130_combout ;
|
|
wire \ula_|zx_keyboard_|keys[4][2]~59_combout ;
|
|
wire \ula_|zx_keyboard_|keys[4][2]~q ;
|
|
wire \ula_|zx_keyboard_|keys[5][2]~56_combout ;
|
|
wire \ula_|zx_keyboard_|keys[5][2]~57_combout ;
|
|
wire \ula_|zx_keyboard_|keys[5][2]~q ;
|
|
wire \D[2]~35_combout ;
|
|
wire \ula_|zx_keyboard_|keys[0][2]~54_combout ;
|
|
wire \ula_|zx_keyboard_|keys[0][2]~55_combout ;
|
|
wire \ula_|zx_keyboard_|keys[0][2]~q ;
|
|
wire \ula_|zx_keyboard_|keys[3][2]~50_combout ;
|
|
wire \ula_|zx_keyboard_|keys[3][2]~51_combout ;
|
|
wire \ula_|zx_keyboard_|keys[3][2]~q ;
|
|
wire \ula_|zx_keyboard_|keys[2][2]~52_combout ;
|
|
wire \ula_|zx_keyboard_|keys[2][2]~53_combout ;
|
|
wire \ula_|zx_keyboard_|keys[2][2]~q ;
|
|
wire \D[2]~33_combout ;
|
|
wire \ula_|zx_keyboard_|keys[1][2]~47_combout ;
|
|
wire \ula_|zx_keyboard_|keys[1][2]~48_combout ;
|
|
wire \ula_|zx_keyboard_|keys[1][2]~q ;
|
|
wire \ula_|zx_keyboard_|key_row~1_combout ;
|
|
wire \D[2]~34_combout ;
|
|
wire \D[2]~37_combout ;
|
|
wire \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ;
|
|
wire \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ;
|
|
wire \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ;
|
|
wire \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ;
|
|
wire \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ;
|
|
wire \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout ;
|
|
wire \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ;
|
|
wire \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ;
|
|
wire \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ;
|
|
wire \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ;
|
|
wire \Selector0~0_combout ;
|
|
wire \Selector0~1_combout ;
|
|
wire \D[2]~82_combout ;
|
|
wire \D[2]~38_combout ;
|
|
wire \D[2]~39_combout ;
|
|
wire \z80_|bus_control_|db[2]~12_combout ;
|
|
wire \z80_|bus_control_|db[2]~13_combout ;
|
|
wire \z80_|pla_decode_|Equal1~4_combout ;
|
|
wire \z80_|execute_|ctl_alu_op_low~26_combout ;
|
|
wire \z80_|execute_|ctl_alu_op_low~45_combout ;
|
|
wire \z80_|execute_|setM1~17_combout ;
|
|
wire \z80_|execute_|setM1~18_combout ;
|
|
wire \z80_|execute_|setM1~11_combout ;
|
|
wire \z80_|execute_|setM1~10_combout ;
|
|
wire \z80_|execute_|setM1~12_combout ;
|
|
wire \z80_|execute_|setM1~8_combout ;
|
|
wire \z80_|execute_|setM1~9_combout ;
|
|
wire \z80_|execute_|setM1~13_combout ;
|
|
wire \z80_|execute_|setM1~15_combout ;
|
|
wire \z80_|execute_|setM1~14_combout ;
|
|
wire \z80_|execute_|setM1~16_combout ;
|
|
wire \z80_|execute_|setM1~19_combout ;
|
|
wire \z80_|execute_|setM1~23_combout ;
|
|
wire \z80_|execute_|setM1~22_combout ;
|
|
wire \z80_|execute_|setM1~56_combout ;
|
|
wire \z80_|execute_|setM1~24_combout ;
|
|
wire \z80_|execute_|setM1~25_combout ;
|
|
wire \z80_|execute_|setM1~26_combout ;
|
|
wire \z80_|execute_|setM1~27_combout ;
|
|
wire \z80_|execute_|setM1~28_combout ;
|
|
wire \z80_|execute_|setM1~55_combout ;
|
|
wire \z80_|execute_|setM1~29_combout ;
|
|
wire \z80_|execute_|setM1~31_combout ;
|
|
wire \z80_|execute_|setM1~33_combout ;
|
|
wire \z80_|execute_|setM1~32_combout ;
|
|
wire \z80_|execute_|setM1~34_combout ;
|
|
wire \z80_|execute_|setM1~20_combout ;
|
|
wire \z80_|execute_|setM1~21_combout ;
|
|
wire \z80_|execute_|setM1~35_combout ;
|
|
wire \z80_|execute_|setM1~43_combout ;
|
|
wire \z80_|execute_|setM1~44_combout ;
|
|
wire \z80_|execute_|setM1~45_combout ;
|
|
wire \z80_|execute_|setM1~46_combout ;
|
|
wire \z80_|execute_|setM1~52_combout ;
|
|
wire \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ;
|
|
wire \z80_|sequencer_|T6~q ;
|
|
wire \z80_|execute_|setM1~53_combout ;
|
|
wire \z80_|execute_|setM1~54_combout ;
|
|
wire \z80_|sequencer_|DFFE_M1_ff~0_combout ;
|
|
wire \z80_|sequencer_|DFFE_M1_ff~q ;
|
|
wire \z80_|resets_|x1~0_combout ;
|
|
wire \z80_|fpga_reset~feeder_combout ;
|
|
wire \z80_|fpga_reset~q ;
|
|
wire \z80_|fpga_reset~clkctrl_outclk ;
|
|
wire \z80_|resets_|x1~q ;
|
|
wire \z80_|resets_|x3~combout ;
|
|
wire \z80_|resets_|SYNTHESIZED_WIRE_12~q ;
|
|
wire \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ;
|
|
wire \z80_|resets_|SYNTHESIZED_WIRE_10~q ;
|
|
wire \z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ;
|
|
wire \z80_|resets_|SYNTHESIZED_WIRE_9~q ;
|
|
wire \z80_|resets_|DFFE_intr_ff3~q ;
|
|
wire \z80_|resets_|clrpc_int~0_combout ;
|
|
wire \z80_|resets_|clrpc_int~q ;
|
|
wire \z80_|resets_|clrpc~0_combout ;
|
|
wire \z80_|address_pins_|DFFE_apin_latch[0]~0_combout ;
|
|
wire \D[0]~47_combout ;
|
|
wire \D[0]~48_combout ;
|
|
wire \D[1]~49_combout ;
|
|
wire \D[1]~50_combout ;
|
|
wire \D[2]~51_combout ;
|
|
wire \D[2]~52_combout ;
|
|
wire \D[3]~58_combout ;
|
|
wire \D[3]~59_combout ;
|
|
wire \D[4]~65_combout ;
|
|
wire \D[4]~66_combout ;
|
|
wire \D[6]~70_combout ;
|
|
wire \D[6]~71_combout ;
|
|
wire \z80_|nM1_int~3_combout ;
|
|
wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ;
|
|
wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout ;
|
|
wire \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q ;
|
|
wire \z80_|memory_ifc_|DFFE_mreq_ff2~q ;
|
|
wire \z80_|memory_ifc_|nMREQ_out~0_combout ;
|
|
wire \z80_|memory_ifc_|nMREQ_out~1_combout ;
|
|
wire \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ;
|
|
wire \ula_|i2c_loader_|state.Idle~feeder_combout ;
|
|
wire \ula_|i2c_loader_|divider[0]~15_combout ;
|
|
wire \ula_|i2c_loader_|divider[1]~5_combout ;
|
|
wire \ula_|i2c_loader_|divider[1]~6 ;
|
|
wire \ula_|i2c_loader_|divider[2]~7_combout ;
|
|
wire \ula_|i2c_loader_|divider[2]~8 ;
|
|
wire \ula_|i2c_loader_|divider[3]~9_combout ;
|
|
wire \ula_|i2c_loader_|WideAnd0~0_combout ;
|
|
wire \ula_|i2c_loader_|divider[3]~10 ;
|
|
wire \ula_|i2c_loader_|divider[4]~11_combout ;
|
|
wire \ula_|i2c_loader_|divider[4]~12 ;
|
|
wire \ula_|i2c_loader_|divider[5]~13_combout ;
|
|
wire \ula_|i2c_loader_|WideAnd0~combout ;
|
|
wire \ula_|i2c_loader_|state.Idle~q ;
|
|
wire \ula_|i2c_loader_|phase~0_combout ;
|
|
wire \ula_|i2c_loader_|phase~1_combout ;
|
|
wire \ula_|i2c_loader_|nbit~5_combout ;
|
|
wire \ula_|i2c_loader_|state.Idle~0_combout ;
|
|
wire \ula_|i2c_loader_|Mux42~0_combout ;
|
|
wire \ula_|i2c_loader_|nbit~6_combout ;
|
|
wire \ula_|i2c_loader_|state.Done~0_combout ;
|
|
wire \ula_|i2c_loader_|state.Ack~0_combout ;
|
|
wire \ula_|i2c_loader_|state.Ack~1_combout ;
|
|
wire \ula_|i2c_loader_|state.Ack~q ;
|
|
wire \ula_|i2c_loader_|nbit[0]~2_combout ;
|
|
wire \ula_|i2c_loader_|nbyte~4_combout ;
|
|
wire \ula_|i2c_loader_|thisbyte[0]~7_combout ;
|
|
wire \I2C_SDAT~input_o ;
|
|
wire \ula_|i2c_loader_|nbyte[0]~1_combout ;
|
|
wire \ula_|i2c_loader_|nbyte[0]~2_combout ;
|
|
wire \ula_|i2c_loader_|nbyte[0]~3_combout ;
|
|
wire \ula_|i2c_loader_|nbit[0]~1_combout ;
|
|
wire \ula_|i2c_loader_|nbit[0]~3_combout ;
|
|
wire \ula_|i2c_loader_|nbit[0]~4_combout ;
|
|
wire \ula_|i2c_loader_|nbit~0_combout ;
|
|
wire \ula_|i2c_loader_|state.Done~1_combout ;
|
|
wire \ula_|i2c_loader_|state~27_combout ;
|
|
wire \ula_|i2c_loader_|state~24_combout ;
|
|
wire \ula_|i2c_loader_|state~26_combout ;
|
|
wire \ula_|i2c_loader_|state.Data~0_combout ;
|
|
wire \ula_|i2c_loader_|state.Data~q ;
|
|
wire \ula_|i2c_loader_|state.Done~2_combout ;
|
|
wire \ula_|i2c_loader_|state.Pause~1_combout ;
|
|
wire \ula_|i2c_loader_|thisbyte[0]~8_combout ;
|
|
wire \ula_|i2c_loader_|nbyte[1]~5_combout ;
|
|
wire \ula_|i2c_loader_|thisbyte[0]~18_combout ;
|
|
wire \ula_|i2c_loader_|thisbyte[0]~9 ;
|
|
wire \ula_|i2c_loader_|thisbyte[1]~10_combout ;
|
|
wire \ula_|i2c_loader_|thisbyte[1]~11 ;
|
|
wire \ula_|i2c_loader_|thisbyte[2]~12_combout ;
|
|
wire \ula_|i2c_loader_|thisbyte[2]~13 ;
|
|
wire \ula_|i2c_loader_|thisbyte[3]~14_combout ;
|
|
wire \ula_|i2c_loader_|Equal2~0_combout ;
|
|
wire \ula_|i2c_loader_|thisbyte[3]~15 ;
|
|
wire \ula_|i2c_loader_|thisbyte[4]~16_combout ;
|
|
wire \ula_|i2c_loader_|Equal2~1_combout ;
|
|
wire \ula_|i2c_loader_|state.Pause~0_combout ;
|
|
wire \ula_|i2c_loader_|state.Pause~2_combout ;
|
|
wire \ula_|i2c_loader_|state.Pause~q ;
|
|
wire \ula_|i2c_loader_|state~25_combout ;
|
|
wire \ula_|i2c_loader_|state.Start~q ;
|
|
wire \ula_|i2c_loader_|nbyte~0_combout ;
|
|
wire \ula_|i2c_loader_|state.Stop~0_combout ;
|
|
wire \ula_|i2c_loader_|state.Stop~1_combout ;
|
|
wire \ula_|i2c_loader_|state.Stop~q ;
|
|
wire \ula_|i2c_loader_|scl_out~0_combout ;
|
|
wire \ula_|i2c_loader_|scl_out~_Duplicate_1_q ;
|
|
wire \ula_|i2c_loader_|scl_out~1_combout ;
|
|
wire \ula_|i2c_loader_|scl_out~2_combout ;
|
|
wire \ula_|i2c_loader_|scl_out~q ;
|
|
wire \ula_|i2c_loader_|sda_out~_Duplicate_1_q ;
|
|
wire \ula_|i2c_loader_|shiftreg~4_combout ;
|
|
wire \ula_|i2c_loader_|Mux35~0_combout ;
|
|
wire \ula_|i2c_loader_|shiftreg~13_combout ;
|
|
wire \ula_|i2c_loader_|shiftreg~15_combout ;
|
|
wire \ula_|i2c_loader_|shiftreg~16_combout ;
|
|
wire \ula_|i2c_loader_|shiftreg~17_combout ;
|
|
wire \ula_|i2c_loader_|shiftreg~18_combout ;
|
|
wire \ula_|i2c_loader_|shiftreg~20_combout ;
|
|
wire \ula_|i2c_loader_|shiftreg~21_combout ;
|
|
wire \ula_|i2c_loader_|shiftreg[0]~23_combout ;
|
|
wire \ula_|i2c_loader_|shiftreg[0]~6_combout ;
|
|
wire \ula_|i2c_loader_|shiftreg[0]~7_combout ;
|
|
wire \ula_|i2c_loader_|shiftreg~22_combout ;
|
|
wire \ula_|i2c_loader_|shiftreg[6]~9_combout ;
|
|
wire \ula_|i2c_loader_|shiftreg[6]~10_combout ;
|
|
wire \ula_|i2c_loader_|shiftreg~19_combout ;
|
|
wire \ula_|i2c_loader_|shiftreg~25_combout ;
|
|
wire \ula_|i2c_loader_|shiftreg~12_combout ;
|
|
wire \ula_|i2c_loader_|shiftreg~14_combout ;
|
|
wire \ula_|i2c_loader_|shiftreg~24_combout ;
|
|
wire \ula_|i2c_loader_|shiftreg~11_combout ;
|
|
wire \ula_|i2c_loader_|shiftreg~8_combout ;
|
|
wire \ula_|i2c_loader_|shiftreg[7]~5_combout ;
|
|
wire \ula_|i2c_loader_|sda_out~0_combout ;
|
|
wire \ula_|i2c_loader_|sda_out~1_combout ;
|
|
wire \ula_|i2c_loader_|sda_out~2_combout ;
|
|
wire \ula_|i2c_loader_|sda_out~3_combout ;
|
|
wire \ula_|i2c_loader_|sda_out~4_combout ;
|
|
wire \ula_|i2c_loader_|sda_out~q ;
|
|
wire \ula_|i2s_intf_|mclk_r~0_combout ;
|
|
wire \ula_|i2s_intf_|mclk_r~_Duplicate_1_q ;
|
|
wire \ula_|i2s_intf_|mclk_r~q ;
|
|
wire \ula_|i2s_intf_|Add0~1_cout ;
|
|
wire \ula_|i2s_intf_|Add0~2_combout ;
|
|
wire \ula_|i2s_intf_|lrdivider~2_combout ;
|
|
wire \ula_|i2s_intf_|Add0~3 ;
|
|
wire \ula_|i2s_intf_|Add0~4_combout ;
|
|
wire \ula_|i2s_intf_|lrdivider[2]~8_combout ;
|
|
wire \ula_|i2s_intf_|Add0~5 ;
|
|
wire \ula_|i2s_intf_|Add0~6_combout ;
|
|
wire \ula_|i2s_intf_|lrdivider[3]~7_combout ;
|
|
wire \ula_|i2s_intf_|Add0~7 ;
|
|
wire \ula_|i2s_intf_|Add0~8_combout ;
|
|
wire \ula_|i2s_intf_|lrdivider~1_combout ;
|
|
wire \ula_|i2s_intf_|Add0~9 ;
|
|
wire \ula_|i2s_intf_|Add0~10_combout ;
|
|
wire \ula_|i2s_intf_|lrdivider[5]~6_combout ;
|
|
wire \ula_|i2s_intf_|Equal0~1_combout ;
|
|
wire \ula_|i2s_intf_|Add0~11 ;
|
|
wire \ula_|i2s_intf_|Add0~12_combout ;
|
|
wire \ula_|i2s_intf_|lrdivider[6]~5_combout ;
|
|
wire \ula_|i2s_intf_|Add0~13 ;
|
|
wire \ula_|i2s_intf_|Add0~14_combout ;
|
|
wire \ula_|i2s_intf_|lrdivider[7]~4_combout ;
|
|
wire \ula_|i2s_intf_|Add0~15 ;
|
|
wire \ula_|i2s_intf_|Add0~16_combout ;
|
|
wire \ula_|i2s_intf_|lrdivider~0_combout ;
|
|
wire \ula_|i2s_intf_|Add0~17 ;
|
|
wire \ula_|i2s_intf_|Add0~18_combout ;
|
|
wire \ula_|i2s_intf_|lrdivider[9]~3_combout ;
|
|
wire \ula_|i2s_intf_|Equal0~0_combout ;
|
|
wire \ula_|i2s_intf_|Equal0~2_combout ;
|
|
wire \ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ;
|
|
wire \ula_|i2s_intf_|lrclk_r~0_combout ;
|
|
wire \ula_|i2s_intf_|lrclk_r~q ;
|
|
wire \ula_|i2s_intf_|lrclk_r~_Duplicate_1_q ;
|
|
wire \ula_|i2s_intf_|bitcount[0]~5_combout ;
|
|
wire \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ;
|
|
wire \ula_|i2s_intf_|bclk_r~_Duplicate_1_q ;
|
|
wire \ula_|i2s_intf_|bitcount[4]~15_combout ;
|
|
wire \ula_|i2s_intf_|bitcount[0]~6 ;
|
|
wire \ula_|i2s_intf_|bitcount[1]~7_combout ;
|
|
wire \ula_|i2s_intf_|bitcount[1]~8 ;
|
|
wire \ula_|i2s_intf_|bitcount[2]~9_combout ;
|
|
wire \ula_|i2s_intf_|bitcount[2]~10 ;
|
|
wire \ula_|i2s_intf_|bitcount[3]~11_combout ;
|
|
wire \ula_|i2s_intf_|bitcount[3]~12 ;
|
|
wire \ula_|i2s_intf_|bitcount[4]~13_combout ;
|
|
wire \ula_|i2s_intf_|LessThan0~0_combout ;
|
|
wire \ula_|i2s_intf_|shiftreg[4]~1_combout ;
|
|
wire \ula_|i2s_intf_|Add2~18_combout ;
|
|
wire \ula_|i2s_intf_|Add2~7_cout ;
|
|
wire \ula_|i2s_intf_|Add2~8_combout ;
|
|
wire \ula_|i2s_intf_|Add2~20_combout ;
|
|
wire \ula_|i2s_intf_|Add2~9 ;
|
|
wire \ula_|i2s_intf_|Add2~10_combout ;
|
|
wire \ula_|i2s_intf_|Add2~17_combout ;
|
|
wire \ula_|i2s_intf_|Add2~11 ;
|
|
wire \ula_|i2s_intf_|Add2~12_combout ;
|
|
wire \ula_|i2s_intf_|Add2~19_combout ;
|
|
wire \ula_|i2s_intf_|Add2~13 ;
|
|
wire \ula_|i2s_intf_|Add2~14_combout ;
|
|
wire \ula_|i2s_intf_|Add2~16_combout ;
|
|
wire \ula_|i2s_intf_|Equal1~0_combout ;
|
|
wire \ula_|i2s_intf_|Equal1~1_combout ;
|
|
wire \ula_|i2s_intf_|bclk_r~0_combout ;
|
|
wire \ula_|i2s_intf_|bclk_r~1_combout ;
|
|
wire \ula_|i2s_intf_|bclk_r~q ;
|
|
wire \ula_|always0~2_combout ;
|
|
wire \ula_|always0~3_combout ;
|
|
wire \ula_|i2s_intf_|shiftreg[0]~19_combout ;
|
|
wire \AUD_ADCDAT~input_o ;
|
|
wire \ula_|i2s_intf_|shiftreg[0]~20_combout ;
|
|
wire \ula_|i2s_intf_|shiftreg~18_combout ;
|
|
wire \ula_|i2s_intf_|shiftreg[4]~2_combout ;
|
|
wire \ula_|i2s_intf_|shiftreg~17_combout ;
|
|
wire \ula_|i2s_intf_|shiftreg~16_combout ;
|
|
wire \ula_|i2s_intf_|shiftreg~15_combout ;
|
|
wire \ula_|i2s_intf_|shiftreg~14_combout ;
|
|
wire \ula_|i2s_intf_|shiftreg~13_combout ;
|
|
wire \ula_|i2s_intf_|shiftreg~12_combout ;
|
|
wire \ula_|i2s_intf_|shiftreg~11_combout ;
|
|
wire \ula_|i2s_intf_|shiftreg~10_combout ;
|
|
wire \ula_|i2s_intf_|shiftreg~9_combout ;
|
|
wire \ula_|i2s_intf_|shiftreg~8_combout ;
|
|
wire \ula_|i2s_intf_|shiftreg~7_combout ;
|
|
wire \ula_|i2s_intf_|PCM_INL[14]~0_combout ;
|
|
wire \ula_|i2s_intf_|PCM_INR[14]~0_combout ;
|
|
wire \ula_|pcm_outr~0_combout ;
|
|
wire \ula_|i2s_intf_|shiftreg~6_combout ;
|
|
wire \ula_|i2s_intf_|shiftreg~5_combout ;
|
|
wire \ula_|i2s_intf_|shiftreg~4_combout ;
|
|
wire \ula_|i2s_intf_|shiftreg~3_combout ;
|
|
wire \ula_|i2s_intf_|shiftreg~0_combout ;
|
|
wire \ula_|border[1]~feeder_combout ;
|
|
wire \ula_|video_|LessThan4~0_combout ;
|
|
wire \ula_|video_|screen_en~0_combout ;
|
|
wire \ula_|video_|LessThan6~0_combout ;
|
|
wire \ula_|video_|LessThan6~1_combout ;
|
|
wire \ula_|video_|screen_en~1_combout ;
|
|
wire \ula_|video_|LessThan2~0_combout ;
|
|
wire \ula_|video_|LessThan2~1_combout ;
|
|
wire \ula_|video_|LessThan3~0_combout ;
|
|
wire \ula_|video_|LessThan0~0_combout ;
|
|
wire \ula_|video_|disp_enable~0_combout ;
|
|
wire \ula_|video_|disp_enable~1_combout ;
|
|
wire \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ;
|
|
wire \ula_|video_|attr_prefetch[7]~feeder_combout ;
|
|
wire \ula_|video_|Decoder0~1_combout ;
|
|
wire \ula_|video_|Decoder0~0_combout ;
|
|
wire \ula_|video_|frame[0]~12_combout ;
|
|
wire \ula_|video_|frame[1]~4_combout ;
|
|
wire \ula_|video_|frame[1]~5 ;
|
|
wire \ula_|video_|frame[2]~6_combout ;
|
|
wire \ula_|video_|frame[2]~7 ;
|
|
wire \ula_|video_|frame[3]~8_combout ;
|
|
wire \ula_|video_|frame[3]~9 ;
|
|
wire \ula_|video_|frame[4]~10_combout ;
|
|
wire \ula_|video_|frame[4]~feeder_combout ;
|
|
wire \ula_|video_|inverted~combout ;
|
|
wire \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ;
|
|
wire \ula_|video_|bits_prefetch[6]~feeder_combout ;
|
|
wire \ula_|video_|Decoder0~2_combout ;
|
|
wire \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ;
|
|
wire \ula_|video_|bits_prefetch[4]~feeder_combout ;
|
|
wire \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ;
|
|
wire \ula_|video_|bits_prefetch[5]~feeder_combout ;
|
|
wire \ula_|video_|bits[5]~feeder_combout ;
|
|
wire \ula_|video_|bits_prefetch[7]~feeder_combout ;
|
|
wire \ula_|video_|Mux0~0_combout ;
|
|
wire \ula_|video_|Mux0~1_combout ;
|
|
wire \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ;
|
|
wire \ula_|video_|bits_prefetch[2]~feeder_combout ;
|
|
wire \ula_|video_|bits[2]~feeder_combout ;
|
|
wire \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ;
|
|
wire \ula_|video_|bits_prefetch[0]~feeder_combout ;
|
|
wire \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ;
|
|
wire \ula_|video_|bits_prefetch[1]~feeder_combout ;
|
|
wire \ula_|video_|bits[1]~feeder_combout ;
|
|
wire \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ;
|
|
wire \ula_|video_|bits_prefetch[3]~feeder_combout ;
|
|
wire \ula_|video_|Mux0~2_combout ;
|
|
wire \ula_|video_|Mux0~3_combout ;
|
|
wire \ula_|video_|cindex[1]~0_combout ;
|
|
wire \ula_|video_|attr_prefetch[4]~feeder_combout ;
|
|
wire \ula_|video_|attr_prefetch[1]~feeder_combout ;
|
|
wire \ula_|video_|cindex[1]~1_combout ;
|
|
wire \ula_|video_|VGA_R[0]~0_combout ;
|
|
wire \ula_|video_|attr_prefetch[6]~feeder_combout ;
|
|
wire \ula_|video_|VGA_B[1]~0_combout ;
|
|
wire \ula_|video_|VGA_R[1]~1_combout ;
|
|
wire \ula_|video_|attr_prefetch[5]~feeder_combout ;
|
|
wire \ula_|video_|attr_prefetch[2]~feeder_combout ;
|
|
wire \ula_|video_|cindex[2]~2_combout ;
|
|
wire \ula_|video_|VGA_G[0]~0_combout ;
|
|
wire \ula_|video_|VGA_G[1]~1_combout ;
|
|
wire \ula_|video_|attr_prefetch[0]~feeder_combout ;
|
|
wire \ula_|video_|attr[0]~feeder_combout ;
|
|
wire \ula_|video_|attr_prefetch[3]~feeder_combout ;
|
|
wire \ula_|video_|cindex[0]~3_combout ;
|
|
wire \ula_|video_|VGA_B[0]~1_combout ;
|
|
wire \ula_|video_|VGA_B[1]~2_combout ;
|
|
wire \ula_|video_|Equal0~2_combout ;
|
|
wire \ula_|video_|VGA_HS~_Duplicate_1_q ;
|
|
wire \ula_|video_|Selector0~0_combout ;
|
|
wire \ula_|video_|VGA_HS~q ;
|
|
wire \ula_|video_|VGA_VS~_Duplicate_1_q ;
|
|
wire \ula_|video_|Selector1~0_combout ;
|
|
wire \ula_|video_|VGA_VS~q ;
|
|
wire \z80_|memory_ifc_|q1~feeder_combout ;
|
|
wire \z80_|memory_ifc_|q1~q ;
|
|
wire \z80_|memory_ifc_|q2~q ;
|
|
wire \z80_|memory_ifc_|nRFSH_out~0_combout ;
|
|
wire \z80_|memory_ifc_|nM1_out~combout ;
|
|
wire \ula_|beep~0_combout ;
|
|
wire \ula_|beep~q ;
|
|
wire [0:0] \ram0|altsyncram_component|auto_generated|address_reg_a ;
|
|
wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode244w ;
|
|
wire [2:0] \ula_|border ;
|
|
wire [0:0] \ula_|clocks_|counter ;
|
|
wire [1:0] \ula_|i2c_loader_|nbyte ;
|
|
wire [4:0] \ula_|i2s_intf_|bitcount ;
|
|
wire [4:0] \ula_|video_|frame ;
|
|
wire [7:0] \ula_|video_|attr_prefetch ;
|
|
wire [7:0] \z80_|reg_file_|b2v_latch_af_hi|latch ;
|
|
wire [7:0] \z80_|reg_file_|b2v_latch_bc2_hi|latch ;
|
|
wire [7:0] \z80_|reg_file_|b2v_latch_de2_hi|latch ;
|
|
wire [7:0] \z80_|reg_file_|b2v_latch_hl2_lo|latch ;
|
|
wire [7:0] \z80_|reg_file_|b2v_latch_hl_lo|latch ;
|
|
wire [7:0] \z80_|reg_file_|b2v_latch_ix_lo|latch ;
|
|
wire [7:0] \z80_|reg_file_|b2v_latch_pc_lo|latch ;
|
|
wire [3:0] \z80_|alu_|op1_low ;
|
|
wire [7:0] \z80_|reg_file_|b2v_latch_af2_hi|latch ;
|
|
wire [15:0] \z80_|address_latch_|abusz ;
|
|
wire [7:0] \z80_|data_pins_|SYNTHESIZED_WIRE_0 ;
|
|
wire [0:0] \ram0|altsyncram_component|auto_generated|out_address_reg_a ;
|
|
wire [1:0] \ram1|altsyncram_component|auto_generated|out_address_reg_a ;
|
|
wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode252w ;
|
|
wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode236w ;
|
|
wire [15:0] \ula_|pcm_outl ;
|
|
wire [4:0] \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk ;
|
|
wire [4:0] \ula_|i2c_loader_|thisbyte ;
|
|
wire [1:0] \ula_|i2c_loader_|phase ;
|
|
wire [2:0] \ula_|i2c_loader_|nbit ;
|
|
wire [9:0] \ula_|i2s_intf_|lrdivider ;
|
|
wire [4:0] \ula_|i2s_intf_|bdivider ;
|
|
wire [15:0] \ula_|i2s_intf_|PCM_INL ;
|
|
wire [12:0] \ula_|video_|vram_address ;
|
|
wire [9:0] \ula_|video_|vga_hc ;
|
|
wire [7:0] \ula_|video_|bits ;
|
|
wire [7:0] \ula_|video_|attr ;
|
|
wire [8:0] \ula_|ps2_keyboard_|shiftreg ;
|
|
wire [3:0] \ula_|ps2_keyboard_|bit_count ;
|
|
wire [7:0] \z80_|reg_file_|b2v_latch_af_lo|latch ;
|
|
wire [7:0] \z80_|reg_file_|b2v_latch_bc2_lo|latch ;
|
|
wire [7:0] \z80_|reg_file_|b2v_latch_bc_lo|latch ;
|
|
wire [7:0] \z80_|reg_file_|b2v_latch_de2_lo|latch ;
|
|
wire [7:0] \z80_|reg_file_|b2v_latch_de_lo|latch ;
|
|
wire [7:0] \z80_|reg_file_|b2v_latch_hl_hi|latch ;
|
|
wire [7:0] \z80_|reg_file_|b2v_latch_ir_hi|latch ;
|
|
wire [7:0] \z80_|reg_file_|b2v_latch_ix_hi|latch ;
|
|
wire [7:0] \z80_|reg_file_|b2v_latch_iy_hi|latch ;
|
|
wire [7:0] \z80_|reg_file_|b2v_latch_pc_hi|latch ;
|
|
wire [7:0] \z80_|reg_file_|b2v_latch_sp_hi|latch ;
|
|
wire [7:0] \z80_|reg_file_|b2v_latch_wz_hi|latch ;
|
|
wire [7:0] \z80_|reg_file_|b2v_latch_wz_lo|latch ;
|
|
wire [3:0] \z80_|alu_|result_lo ;
|
|
wire [3:0] \z80_|alu_|op2_high ;
|
|
wire [3:0] \z80_|alu_|op1_high ;
|
|
wire [3:0] \z80_|alu_|b2v_op1_latch_mux_high|Q ;
|
|
wire [15:0] \z80_|address_latch_|Q ;
|
|
wire [15:0] \z80_|address_latch_|b2v_inst_inc_dec|address ;
|
|
wire [15:0] \z80_|address_pins_|DFFE_apin_latch ;
|
|
wire [7:0] \z80_|data_pins_|dout ;
|
|
wire [7:0] \z80_|ir_|opcode ;
|
|
wire [1:0] \ram1|altsyncram_component|auto_generated|address_reg_a ;
|
|
wire [2:0] \ram1|altsyncram_component|auto_generated|decode3|w_anode223w ;
|
|
wire [7:0] \ula_|i2c_loader_|shiftreg ;
|
|
wire [5:0] \ula_|i2c_loader_|divider ;
|
|
wire [17:0] \ula_|i2s_intf_|shiftreg ;
|
|
wire [15:0] \ula_|i2s_intf_|PCM_INR ;
|
|
wire [9:0] \ula_|video_|vga_vc ;
|
|
wire [7:0] \ula_|video_|bits_prefetch ;
|
|
wire [7:0] \ula_|ps2_keyboard_|clk_filter ;
|
|
wire [7:0] \z80_|reg_file_|b2v_latch_af2_lo|latch ;
|
|
wire [7:0] \z80_|reg_file_|b2v_latch_bc_hi|latch ;
|
|
wire [7:0] \z80_|reg_file_|b2v_latch_de_hi|latch ;
|
|
wire [7:0] \z80_|reg_file_|b2v_latch_hl2_hi|latch ;
|
|
wire [7:0] \z80_|reg_file_|b2v_latch_ir_lo|latch ;
|
|
wire [7:0] \z80_|reg_file_|b2v_latch_iy_lo|latch ;
|
|
wire [7:0] \z80_|reg_file_|b2v_latch_sp_lo|latch ;
|
|
wire [3:0] \z80_|alu_|op2_low ;
|
|
|
|
wire [4:0] \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus ;
|
|
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ;
|
|
wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ;
|
|
wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus ;
|
|
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ;
|
|
wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ;
|
|
wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus ;
|
|
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ;
|
|
wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ;
|
|
wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus ;
|
|
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ;
|
|
wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ;
|
|
wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus ;
|
|
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ;
|
|
wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus ;
|
|
wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ;
|
|
wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ;
|
|
wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus ;
|
|
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ;
|
|
wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ;
|
|
wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus ;
|
|
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ;
|
|
wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ;
|
|
wire [0:0] \rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ;
|
|
wire [0:0] \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus ;
|
|
|
|
assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [0] = \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus [0];
|
|
assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [1] = \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus [1];
|
|
assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [2] = \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus [2];
|
|
assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [3] = \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus [3];
|
|
assign \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [4] = \ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus [4];
|
|
|
|
assign \ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0];
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|
assign \ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus [0];
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|
assign \ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0];
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|
assign \ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus [0];
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|
assign \rom|altsyncram_component|auto_generated|ram_block1a9~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0];
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|
assign \rom|altsyncram_component|auto_generated|ram_block1a1~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0];
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|
assign \ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0];
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|
assign \ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0];
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assign \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus [0];
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assign \ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus [0];
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assign \ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0];
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assign \ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0];
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assign \ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus [0];
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assign \rom|altsyncram_component|auto_generated|ram_block1a10~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0];
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assign \rom|altsyncram_component|auto_generated|ram_block1a2~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0];
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assign \ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus [0];
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assign \ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus [0];
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assign \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus [0];
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assign \ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus [0];
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assign \ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0];
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assign \ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0];
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assign \ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus [0];
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assign \rom|altsyncram_component|auto_generated|ram_block1a8~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0];
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assign \rom|altsyncram_component|auto_generated|ram_block1a0~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0];
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assign \ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0];
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assign \ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0];
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assign \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus [0];
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assign \ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0];
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assign \ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus [0];
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assign \ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0];
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assign \ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus [0];
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assign \rom|altsyncram_component|auto_generated|ram_block1a11~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0];
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assign \rom|altsyncram_component|auto_generated|ram_block1a3~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0];
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assign \ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus [0];
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assign \ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus [0];
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assign \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus [0];
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assign \ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus [0];
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assign \ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0];
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assign \ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0];
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assign \ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus [0];
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assign \rom|altsyncram_component|auto_generated|ram_block1a12~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0];
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assign \ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0];
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assign \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus [0];
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assign \rom|altsyncram_component|auto_generated|ram_block1a4~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0];
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assign \ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus [0];
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assign \ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0];
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assign \ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus [0];
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assign \ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0];
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assign \ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus [0];
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assign \rom|altsyncram_component|auto_generated|ram_block1a13~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0];
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assign \rom|altsyncram_component|auto_generated|ram_block1a5~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0];
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assign \ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0];
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assign \ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0];
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assign \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus [0];
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assign \ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus [0];
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assign \ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0];
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assign \ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0];
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assign \ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus [0];
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assign \rom|altsyncram_component|auto_generated|ram_block1a14~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0];
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assign \rom|altsyncram_component|auto_generated|ram_block1a6~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0];
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assign \ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus [0];
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assign \ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus [0];
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assign \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus [0];
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assign \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0];
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|
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assign \ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus [0];
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|
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assign \ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0];
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|
|
assign \ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout = \ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus [0];
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|
|
assign \rom|altsyncram_component|auto_generated|ram_block1a15~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0];
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|
|
assign \rom|altsyncram_component|auto_generated|ram_block1a7~portadataout = \rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0];
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|
|
|
assign \ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus [0];
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|
|
assign \ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout = \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus [0];
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|
|
|
assign \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 = \ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus [0];
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|
|
|
// Location: IOOBUF_X53_Y21_N23
|
|
cycloneive_io_obuf \GPIO_1[0]~output (
|
|
.i(\z80_|address_pins_|DFFE_apin_latch [0]),
|
|
.oe(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(GPIO_1[0]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \GPIO_1[0]~output .bus_hold = "false";
|
|
defparam \GPIO_1[0]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X45_Y0_N16
|
|
cycloneive_io_obuf \GPIO_1[1]~output (
|
|
.i(\z80_|address_pins_|DFFE_apin_latch [1]),
|
|
.oe(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(GPIO_1[1]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \GPIO_1[1]~output .bus_hold = "false";
|
|
defparam \GPIO_1[1]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X45_Y0_N23
|
|
cycloneive_io_obuf \GPIO_1[2]~output (
|
|
.i(\z80_|address_pins_|DFFE_apin_latch [2]),
|
|
.oe(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(GPIO_1[2]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \GPIO_1[2]~output .bus_hold = "false";
|
|
defparam \GPIO_1[2]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X40_Y0_N16
|
|
cycloneive_io_obuf \GPIO_1[3]~output (
|
|
.i(\z80_|address_pins_|DFFE_apin_latch [3]),
|
|
.oe(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(GPIO_1[3]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \GPIO_1[3]~output .bus_hold = "false";
|
|
defparam \GPIO_1[3]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X40_Y0_N23
|
|
cycloneive_io_obuf \GPIO_1[4]~output (
|
|
.i(\z80_|address_pins_|DFFE_apin_latch [4]),
|
|
.oe(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(GPIO_1[4]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \GPIO_1[4]~output .bus_hold = "false";
|
|
defparam \GPIO_1[4]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X36_Y0_N9
|
|
cycloneive_io_obuf \GPIO_1[5]~output (
|
|
.i(\z80_|address_pins_|DFFE_apin_latch [5]),
|
|
.oe(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(GPIO_1[5]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \GPIO_1[5]~output .bus_hold = "false";
|
|
defparam \GPIO_1[5]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X36_Y0_N16
|
|
cycloneive_io_obuf \GPIO_1[6]~output (
|
|
.i(\z80_|address_pins_|DFFE_apin_latch [6]),
|
|
.oe(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(GPIO_1[6]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \GPIO_1[6]~output .bus_hold = "false";
|
|
defparam \GPIO_1[6]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X36_Y0_N23
|
|
cycloneive_io_obuf \GPIO_1[7]~output (
|
|
.i(\z80_|address_pins_|DFFE_apin_latch [7]),
|
|
.oe(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(GPIO_1[7]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \GPIO_1[7]~output .bus_hold = "false";
|
|
defparam \GPIO_1[7]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X34_Y0_N16
|
|
cycloneive_io_obuf \GPIO_1[8]~output (
|
|
.i(\z80_|address_pins_|DFFE_apin_latch [8]),
|
|
.oe(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(GPIO_1[8]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \GPIO_1[8]~output .bus_hold = "false";
|
|
defparam \GPIO_1[8]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X34_Y0_N2
|
|
cycloneive_io_obuf \GPIO_1[9]~output (
|
|
.i(\z80_|address_pins_|DFFE_apin_latch [9]),
|
|
.oe(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(GPIO_1[9]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \GPIO_1[9]~output .bus_hold = "false";
|
|
defparam \GPIO_1[9]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X38_Y0_N2
|
|
cycloneive_io_obuf \GPIO_1[10]~output (
|
|
.i(\z80_|address_pins_|DFFE_apin_latch [10]),
|
|
.oe(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(GPIO_1[10]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \GPIO_1[10]~output .bus_hold = "false";
|
|
defparam \GPIO_1[10]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X34_Y0_N23
|
|
cycloneive_io_obuf \GPIO_1[11]~output (
|
|
.i(\z80_|address_pins_|DFFE_apin_latch [11]),
|
|
.oe(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(GPIO_1[11]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \GPIO_1[11]~output .bus_hold = "false";
|
|
defparam \GPIO_1[11]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X47_Y0_N23
|
|
cycloneive_io_obuf \GPIO_1[12]~output (
|
|
.i(\z80_|address_pins_|DFFE_apin_latch [12]),
|
|
.oe(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(GPIO_1[12]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \GPIO_1[12]~output .bus_hold = "false";
|
|
defparam \GPIO_1[12]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X38_Y0_N9
|
|
cycloneive_io_obuf \GPIO_1[13]~output (
|
|
.i(\z80_|address_pins_|DFFE_apin_latch [13]),
|
|
.oe(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(GPIO_1[13]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \GPIO_1[13]~output .bus_hold = "false";
|
|
defparam \GPIO_1[13]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X29_Y0_N2
|
|
cycloneive_io_obuf \GPIO_1[14]~output (
|
|
.i(\z80_|address_pins_|DFFE_apin_latch [14]),
|
|
.oe(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(GPIO_1[14]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \GPIO_1[14]~output .bus_hold = "false";
|
|
defparam \GPIO_1[14]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X43_Y0_N16
|
|
cycloneive_io_obuf \GPIO_1[15]~output (
|
|
.i(\z80_|address_pins_|DFFE_apin_latch [15]),
|
|
.oe(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(GPIO_1[15]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \GPIO_1[15]~output .bus_hold = "false";
|
|
defparam \GPIO_1[15]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X53_Y11_N9
|
|
cycloneive_io_obuf \GPIO_1[16]~output (
|
|
.i(\D[0]~48_combout ),
|
|
.oe(\D[0]~84_combout ),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(GPIO_1[16]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \GPIO_1[16]~output .bus_hold = "false";
|
|
defparam \GPIO_1[16]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X53_Y12_N2
|
|
cycloneive_io_obuf \GPIO_1[17]~output (
|
|
.i(\D[1]~50_combout ),
|
|
.oe(\D[0]~84_combout ),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(GPIO_1[17]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \GPIO_1[17]~output .bus_hold = "false";
|
|
defparam \GPIO_1[17]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X53_Y8_N23
|
|
cycloneive_io_obuf \GPIO_1[18]~output (
|
|
.i(\D[2]~52_combout ),
|
|
.oe(\D[0]~84_combout ),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(GPIO_1[18]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \GPIO_1[18]~output .bus_hold = "false";
|
|
defparam \GPIO_1[18]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X53_Y11_N2
|
|
cycloneive_io_obuf \GPIO_1[19]~output (
|
|
.i(\D[3]~59_combout ),
|
|
.oe(\D[0]~84_combout ),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(GPIO_1[19]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \GPIO_1[19]~output .bus_hold = "false";
|
|
defparam \GPIO_1[19]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X53_Y6_N16
|
|
cycloneive_io_obuf \GPIO_1[20]~output (
|
|
.i(\D[4]~66_combout ),
|
|
.oe(\D[0]~84_combout ),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(GPIO_1[20]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \GPIO_1[20]~output .bus_hold = "false";
|
|
defparam \GPIO_1[20]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X53_Y7_N9
|
|
cycloneive_io_obuf \GPIO_1[21]~output (
|
|
.i(\D[5]~68_combout ),
|
|
.oe(\D[0]~84_combout ),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(GPIO_1[21]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \GPIO_1[21]~output .bus_hold = "false";
|
|
defparam \GPIO_1[21]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X49_Y0_N2
|
|
cycloneive_io_obuf \GPIO_1[22]~output (
|
|
.i(\D[6]~71_combout ),
|
|
.oe(\D[0]~84_combout ),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(GPIO_1[22]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \GPIO_1[22]~output .bus_hold = "false";
|
|
defparam \GPIO_1[22]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X53_Y9_N23
|
|
cycloneive_io_obuf \GPIO_1[23]~output (
|
|
.i(\D[7]~72_combout ),
|
|
.oe(\D[0]~84_combout ),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(GPIO_1[23]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \GPIO_1[23]~output .bus_hold = "false";
|
|
defparam \GPIO_1[23]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X53_Y6_N23
|
|
cycloneive_io_obuf \GPIO_1[27]~output (
|
|
.i(!\z80_|memory_ifc_|nWR_out~0_combout ),
|
|
.oe(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(GPIO_1[27]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \GPIO_1[27]~output .bus_hold = "false";
|
|
defparam \GPIO_1[27]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X43_Y0_N23
|
|
cycloneive_io_obuf \GPIO_1[28]~output (
|
|
.i(!\z80_|memory_ifc_|nRD_out~2_combout ),
|
|
.oe(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(GPIO_1[28]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \GPIO_1[28]~output .bus_hold = "false";
|
|
defparam \GPIO_1[28]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X53_Y10_N16
|
|
cycloneive_io_obuf \GPIO_1[29]~output (
|
|
.i(!\z80_|memory_ifc_|nIORQ_out~0_combout ),
|
|
.oe(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(GPIO_1[29]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \GPIO_1[29]~output .bus_hold = "false";
|
|
defparam \GPIO_1[29]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X53_Y14_N9
|
|
cycloneive_io_obuf \GPIO_1[30]~output (
|
|
.i(\z80_|memory_ifc_|nMREQ_out~1_combout ),
|
|
.oe(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(GPIO_1[30]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \GPIO_1[30]~output .bus_hold = "false";
|
|
defparam \GPIO_1[30]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X38_Y34_N16
|
|
cycloneive_io_obuf \LED[0]~output (
|
|
.i(\SW[1]~input_o ),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(LED[0]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \LED[0]~output .bus_hold = "false";
|
|
defparam \LED[0]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X49_Y34_N2
|
|
cycloneive_io_obuf \LED[1]~output (
|
|
.i(gnd),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(LED[1]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \LED[1]~output .bus_hold = "false";
|
|
defparam \LED[1]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X49_Y34_N9
|
|
cycloneive_io_obuf \LED[2]~output (
|
|
.i(\SW[2]~input_o ),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(LED[2]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \LED[2]~output .bus_hold = "false";
|
|
defparam \LED[2]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X40_Y34_N2
|
|
cycloneive_io_obuf \LED[3]~output (
|
|
.i(\raw_loader_in~input_o ),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(LED[3]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \LED[3]~output .bus_hold = "false";
|
|
defparam \LED[3]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X0_Y25_N9
|
|
cycloneive_io_obuf \LED[4]~output (
|
|
.i(gnd),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(LED[4]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \LED[4]~output .bus_hold = "false";
|
|
defparam \LED[4]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X0_Y26_N16
|
|
cycloneive_io_obuf \LED[5]~output (
|
|
.i(gnd),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(LED[5]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \LED[5]~output .bus_hold = "false";
|
|
defparam \LED[5]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X0_Y28_N9
|
|
cycloneive_io_obuf \LED[6]~output (
|
|
.i(gnd),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(LED[6]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \LED[6]~output .bus_hold = "false";
|
|
defparam \LED[6]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X0_Y10_N23
|
|
cycloneive_io_obuf \LED[7]~output (
|
|
.i(gnd),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(LED[7]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \LED[7]~output .bus_hold = "false";
|
|
defparam \LED[7]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X20_Y34_N23
|
|
cycloneive_io_obuf \AUD_XCK~output (
|
|
.i(\ula_|i2s_intf_|mclk_r~q ),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(AUD_XCK),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \AUD_XCK~output .bus_hold = "false";
|
|
defparam \AUD_XCK~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X16_Y34_N16
|
|
cycloneive_io_obuf \AUD_ADCLRCK~output (
|
|
.i(\ula_|i2s_intf_|lrclk_r~q ),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(AUD_ADCLRCK),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \AUD_ADCLRCK~output .bus_hold = "false";
|
|
defparam \AUD_ADCLRCK~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X18_Y34_N23
|
|
cycloneive_io_obuf \AUD_DACLRCK~output (
|
|
.i(\ula_|i2s_intf_|lrclk_r~_Duplicate_1_q ),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(AUD_DACLRCK),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \AUD_DACLRCK~output .bus_hold = "false";
|
|
defparam \AUD_DACLRCK~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X14_Y34_N16
|
|
cycloneive_io_obuf \AUD_BCLK~output (
|
|
.i(\ula_|i2s_intf_|bclk_r~q ),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(AUD_BCLK),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \AUD_BCLK~output .bus_hold = "false";
|
|
defparam \AUD_BCLK~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X23_Y34_N16
|
|
cycloneive_io_obuf \AUD_DACDAT~output (
|
|
.i(\ula_|i2s_intf_|shiftreg [17]),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(AUD_DACDAT),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \AUD_DACDAT~output .bus_hold = "false";
|
|
defparam \AUD_DACDAT~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X20_Y34_N9
|
|
cycloneive_io_obuf \VGA_R[0]~output (
|
|
.i(\ula_|video_|VGA_R[0]~0_combout ),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(VGA_R[0]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \VGA_R[0]~output .bus_hold = "false";
|
|
defparam \VGA_R[0]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X20_Y34_N16
|
|
cycloneive_io_obuf \VGA_R[1]~output (
|
|
.i(\ula_|video_|VGA_R[1]~1_combout ),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(VGA_R[1]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \VGA_R[1]~output .bus_hold = "false";
|
|
defparam \VGA_R[1]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X34_Y34_N2
|
|
cycloneive_io_obuf \VGA_R[2]~output (
|
|
.i(\ula_|video_|VGA_R[0]~0_combout ),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(VGA_R[2]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \VGA_R[2]~output .bus_hold = "false";
|
|
defparam \VGA_R[2]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X29_Y34_N16
|
|
cycloneive_io_obuf \VGA_R[3]~output (
|
|
.i(\ula_|video_|VGA_R[0]~0_combout ),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(VGA_R[3]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \VGA_R[3]~output .bus_hold = "false";
|
|
defparam \VGA_R[3]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X31_Y34_N2
|
|
cycloneive_io_obuf \VGA_G[0]~output (
|
|
.i(\ula_|video_|VGA_G[0]~0_combout ),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(VGA_G[0]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \VGA_G[0]~output .bus_hold = "false";
|
|
defparam \VGA_G[0]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X31_Y34_N9
|
|
cycloneive_io_obuf \VGA_G[1]~output (
|
|
.i(\ula_|video_|VGA_G[1]~1_combout ),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(VGA_G[1]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \VGA_G[1]~output .bus_hold = "false";
|
|
defparam \VGA_G[1]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X45_Y34_N9
|
|
cycloneive_io_obuf \VGA_G[2]~output (
|
|
.i(\ula_|video_|VGA_G[0]~0_combout ),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(VGA_G[2]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \VGA_G[2]~output .bus_hold = "false";
|
|
defparam \VGA_G[2]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X45_Y34_N16
|
|
cycloneive_io_obuf \VGA_G[3]~output (
|
|
.i(\ula_|video_|VGA_G[0]~0_combout ),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(VGA_G[3]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \VGA_G[3]~output .bus_hold = "false";
|
|
defparam \VGA_G[3]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X38_Y34_N2
|
|
cycloneive_io_obuf \VGA_B[0]~output (
|
|
.i(\ula_|video_|VGA_B[0]~1_combout ),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(VGA_B[0]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \VGA_B[0]~output .bus_hold = "false";
|
|
defparam \VGA_B[0]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X40_Y34_N9
|
|
cycloneive_io_obuf \VGA_B[1]~output (
|
|
.i(\ula_|video_|VGA_B[1]~2_combout ),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(VGA_B[1]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \VGA_B[1]~output .bus_hold = "false";
|
|
defparam \VGA_B[1]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X43_Y34_N16
|
|
cycloneive_io_obuf \VGA_B[2]~output (
|
|
.i(\ula_|video_|VGA_B[0]~1_combout ),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(VGA_B[2]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \VGA_B[2]~output .bus_hold = "false";
|
|
defparam \VGA_B[2]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X51_Y34_N16
|
|
cycloneive_io_obuf \VGA_B[3]~output (
|
|
.i(\ula_|video_|VGA_B[0]~1_combout ),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(VGA_B[3]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \VGA_B[3]~output .bus_hold = "false";
|
|
defparam \VGA_B[3]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X51_Y34_N23
|
|
cycloneive_io_obuf \VGA_HS~output (
|
|
.i(\ula_|video_|VGA_HS~q ),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(VGA_HS),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \VGA_HS~output .bus_hold = "false";
|
|
defparam \VGA_HS~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X43_Y34_N23
|
|
cycloneive_io_obuf \VGA_VS~output (
|
|
.i(\ula_|video_|VGA_VS~q ),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(VGA_VS),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \VGA_VS~output .bus_hold = "false";
|
|
defparam \VGA_VS~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X53_Y9_N16
|
|
cycloneive_io_obuf \GPIO_1[24]~output (
|
|
.i(vcc),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(GPIO_1[24]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \GPIO_1[24]~output .bus_hold = "false";
|
|
defparam \GPIO_1[24]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X49_Y0_N9
|
|
cycloneive_io_obuf \GPIO_1[25]~output (
|
|
.i(!\z80_|decode_state_|in_halt~q ),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(GPIO_1[25]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \GPIO_1[25]~output .bus_hold = "false";
|
|
defparam \GPIO_1[25]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X53_Y9_N9
|
|
cycloneive_io_obuf \GPIO_1[26]~output (
|
|
.i(!\z80_|memory_ifc_|nRFSH_out~0_combout ),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(GPIO_1[26]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \GPIO_1[26]~output .bus_hold = "false";
|
|
defparam \GPIO_1[26]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X53_Y13_N9
|
|
cycloneive_io_obuf \GPIO_1[31]~output (
|
|
.i(\z80_|memory_ifc_|nM1_out~combout ),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(GPIO_1[31]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \GPIO_1[31]~output .bus_hold = "false";
|
|
defparam \GPIO_1[31]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X53_Y16_N9
|
|
cycloneive_io_obuf \GPIO_1[32]~output (
|
|
.i(gnd),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(GPIO_1[32]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \GPIO_1[32]~output .bus_hold = "false";
|
|
defparam \GPIO_1[32]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X53_Y15_N9
|
|
cycloneive_io_obuf \GPIO_1[33]~output (
|
|
.i(gnd),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(GPIO_1[33]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \GPIO_1[33]~output .bus_hold = "false";
|
|
defparam \GPIO_1[33]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X16_Y34_N2
|
|
cycloneive_io_obuf \buzzer_out~output (
|
|
.i(\ula_|beep~q ),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(buzzer_out),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \buzzer_out~output .bus_hold = "false";
|
|
defparam \buzzer_out~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X0_Y24_N23
|
|
cycloneive_io_obuf \I2C_SCLK~output (
|
|
.i(\ula_|i2c_loader_|scl_out~q ),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(I2C_SCLK),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \I2C_SCLK~output .bus_hold = "false";
|
|
defparam \I2C_SCLK~output .open_drain_output = "true";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X0_Y23_N2
|
|
cycloneive_io_obuf \I2C_SDAT~output (
|
|
.i(\ula_|i2c_loader_|sda_out~q ),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(I2C_SDAT),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \I2C_SDAT~output .bus_hold = "false";
|
|
defparam \I2C_SDAT~output .open_drain_output = "true";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOIBUF_X27_Y0_N22
|
|
cycloneive_io_ibuf \CLOCK_50~input (
|
|
.i(CLOCK_50),
|
|
.ibar(gnd),
|
|
.o(\CLOCK_50~input_o ));
|
|
// synopsys translate_off
|
|
defparam \CLOCK_50~input .bus_hold = "false";
|
|
defparam \CLOCK_50~input .simulate_z_as = "z";
|
|
// synopsys translate_on
|
|
|
|
// Location: PLL_4
|
|
cycloneive_pll \ula_|pll_|altpll_component|auto_generated|pll1 (
|
|
.areset(gnd),
|
|
.pfdena(vcc),
|
|
.fbin(\ula_|pll_|altpll_component|auto_generated|wire_pll1_fbout ),
|
|
.phaseupdown(gnd),
|
|
.phasestep(gnd),
|
|
.scandata(gnd),
|
|
.scanclk(gnd),
|
|
.scanclkena(vcc),
|
|
.configupdate(gnd),
|
|
.clkswitch(gnd),
|
|
.inclk({gnd,\CLOCK_50~input_o }),
|
|
.phasecounterselect(3'b000),
|
|
.phasedone(),
|
|
.scandataout(),
|
|
.scandone(),
|
|
.activeclock(),
|
|
.locked(\ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ),
|
|
.vcooverrange(),
|
|
.vcounderrange(),
|
|
.fbout(\ula_|pll_|altpll_component|auto_generated|wire_pll1_fbout ),
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|pll1_CLK_bus ),
|
|
.clkbad());
|
|
// synopsys translate_off
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .auto_settings = "false";
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .bandwidth_type = "medium";
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .c0_high = 20;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .c0_initial = 1;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .c0_low = 20;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .c0_mode = "even";
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .c0_ph = 0;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .c1_high = 21;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .c1_initial = 1;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .c1_low = 21;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .c1_mode = "even";
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .c1_ph = 0;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .c1_use_casc_in = "off";
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .c2_high = 36;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .c2_initial = 1;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .c2_low = 36;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .c2_mode = "even";
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .c2_ph = 0;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .c2_use_casc_in = "off";
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .c3_high = 0;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .c3_initial = 0;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .c3_low = 0;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .c3_mode = "bypass";
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .c3_ph = 0;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .c3_use_casc_in = "off";
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .c4_high = 0;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .c4_initial = 0;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .c4_low = 0;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .c4_mode = "bypass";
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .c4_ph = 0;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .c4_use_casc_in = "off";
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .charge_pump_current_bits = 1;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .clk0_counter = "c0";
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .clk0_divide_by = 280;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .clk0_duty_cycle = 50;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .clk0_multiply_by = 141;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .clk0_phase_shift = "0";
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .clk1_counter = "c2";
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .clk1_divide_by = 168;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .clk1_duty_cycle = 50;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .clk1_multiply_by = 47;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .clk1_phase_shift = "0";
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .clk2_counter = "c1";
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .clk2_divide_by = 98;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .clk2_duty_cycle = 50;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .clk2_multiply_by = 47;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .clk2_phase_shift = "0";
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .clk3_counter = "unused";
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .clk3_divide_by = 0;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .clk3_duty_cycle = 50;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .clk3_multiply_by = 0;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .clk3_phase_shift = "0";
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .clk4_counter = "unused";
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .clk4_divide_by = 0;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .clk4_duty_cycle = 50;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .clk4_multiply_by = 0;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .clk4_phase_shift = "0";
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .compensate_clock = "clock0";
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .inclk0_input_frequency = 20000;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .inclk1_input_frequency = 0;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .loop_filter_c_bits = 0;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .loop_filter_r_bits = 16;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .m = 141;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .m_initial = 1;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .m_ph = 0;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .n = 7;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .operation_mode = "normal";
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .pfd_max = 200000;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .pfd_min = 3076;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .pll_compensation_delay = 5611;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .self_reset_on_loss_lock = "off";
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .simulation_type = "timing";
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .switch_over_type = "auto";
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .vco_center = 769;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .vco_divide_by = 0;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .vco_frequency_control = "auto";
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .vco_max = 1666;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .vco_min = 769;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .vco_multiply_by = 0;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .vco_phase_shift_step = 124;
|
|
defparam \ula_|pll_|altpll_component|auto_generated|pll1 .vco_post_scale = 1;
|
|
// synopsys translate_on
|
|
|
|
// Location: CLKCTRL_G17
|
|
cycloneive_clkctrl \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl (
|
|
.ena(vcc),
|
|
.inclk({vcc,vcc,vcc,\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [1]}),
|
|
.clkselect(2'b00),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.outclk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ));
|
|
// synopsys translate_off
|
|
defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .clock_type = "global clock";
|
|
defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .ena_register_mode = "none";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y33_N0
|
|
cycloneive_lcell_comb \ula_|clocks_|counter[0]~0 (
|
|
// Equation(s):
|
|
// \ula_|clocks_|counter[0]~0_combout = !\ula_|clocks_|counter [0]
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\ula_|clocks_|counter [0]),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\ula_|clocks_|counter[0]~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|clocks_|counter[0]~0 .lut_mask = 16'h0F0F;
|
|
defparam \ula_|clocks_|counter[0]~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X25_Y33_N1
|
|
dffeas \ula_|clocks_|counter[0] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
|
|
.d(\ula_|clocks_|counter[0]~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|clocks_|counter [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|clocks_|counter[0] .is_wysiwyg = "true";
|
|
defparam \ula_|clocks_|counter[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOIBUF_X25_Y34_N8
|
|
cycloneive_io_ibuf \SW[2]~input (
|
|
.i(SW[2]),
|
|
.ibar(gnd),
|
|
.o(\SW[2]~input_o ));
|
|
// synopsys translate_off
|
|
defparam \SW[2]~input .bus_hold = "false";
|
|
defparam \SW[2]~input .simulate_z_as = "z";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y33_N4
|
|
cycloneive_lcell_comb \ula_|clocks_|clk_cpu~0 (
|
|
// Equation(s):
|
|
// \ula_|clocks_|clk_cpu~0_combout = \ula_|clocks_|clk_cpu~q $ (((\SW[2]~input_o ) # (!\ula_|clocks_|counter [0])))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|clocks_|counter [0]),
|
|
.datac(\ula_|clocks_|clk_cpu~q ),
|
|
.datad(\SW[2]~input_o ),
|
|
.cin(gnd),
|
|
.combout(\ula_|clocks_|clk_cpu~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|clocks_|clk_cpu~0 .lut_mask = 16'h0FC3;
|
|
defparam \ula_|clocks_|clk_cpu~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X25_Y33_N5
|
|
dffeas \ula_|clocks_|clk_cpu (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ),
|
|
.d(\ula_|clocks_|clk_cpu~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|clocks_|clk_cpu~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|clocks_|clk_cpu .is_wysiwyg = "true";
|
|
defparam \ula_|clocks_|clk_cpu .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: CLKCTRL_G12
|
|
cycloneive_clkctrl \ula_|clocks_|clk_cpu~clkctrl (
|
|
.ena(vcc),
|
|
.inclk({vcc,vcc,vcc,\ula_|clocks_|clk_cpu~q }),
|
|
.clkselect(2'b00),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.outclk(\ula_|clocks_|clk_cpu~clkctrl_outclk ));
|
|
// synopsys translate_off
|
|
defparam \ula_|clocks_|clk_cpu~clkctrl .clock_type = "global clock";
|
|
defparam \ula_|clocks_|clk_cpu~clkctrl .ena_register_mode = "none";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y13_N30
|
|
cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_15 (
|
|
// Equation(s):
|
|
// \z80_|sequencer_|SYNTHESIZED_WIRE_15~combout = (\z80_|execute_|setM1~54_combout & (\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|execute_|nextM~14_combout ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|execute_|setM1~54_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.datad(\z80_|execute_|nextM~14_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .lut_mask = 16'h00C0;
|
|
defparam \z80_|sequencer_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: CLKCTRL_G9
|
|
cycloneive_clkctrl \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl (
|
|
.ena(vcc),
|
|
.inclk({vcc,vcc,vcc,\z80_|resets_|SYNTHESIZED_WIRE_12~q }),
|
|
.clkselect(2'b00),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.outclk(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ));
|
|
// synopsys translate_off
|
|
defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clock";
|
|
defparam \z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOIBUF_X0_Y16_N8
|
|
cycloneive_io_ibuf \KEY[1]~input (
|
|
.i(KEY[1]),
|
|
.ibar(gnd),
|
|
.o(\KEY[1]~input_o ));
|
|
// synopsys translate_off
|
|
defparam \KEY[1]~input .bus_hold = "false";
|
|
defparam \KEY[1]~input .simulate_z_as = "z";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y13_N8
|
|
cycloneive_lcell_comb \z80_|interrupts_|nmi_armed~feeder (
|
|
// Equation(s):
|
|
// \z80_|interrupts_|nmi_armed~feeder_combout = VCC
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|interrupts_|nmi_armed~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|interrupts_|nmi_armed~feeder .lut_mask = 16'hFFFF;
|
|
defparam \z80_|interrupts_|nmi_armed~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y13_N4
|
|
cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_9 (
|
|
// Equation(s):
|
|
// \z80_|interrupts_|SYNTHESIZED_WIRE_9~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ),
|
|
.datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .lut_mask = 16'hF0FF;
|
|
defparam \z80_|interrupts_|SYNTHESIZED_WIRE_9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X27_Y13_N9
|
|
dffeas \z80_|interrupts_|nmi_armed (
|
|
.clk(!\KEY[1]~input_o ),
|
|
.d(\z80_|interrupts_|nmi_armed~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_9~combout ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|interrupts_|nmi_armed~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|interrupts_|nmi_armed .is_wysiwyg = "true";
|
|
defparam \z80_|interrupts_|nmi_armed .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y13_N0
|
|
cycloneive_lcell_comb \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder (
|
|
// Equation(s):
|
|
// \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout = \z80_|interrupts_|nmi_armed~q
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|interrupts_|nmi_armed~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder .lut_mask = 16'hFF00;
|
|
defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y13_N22
|
|
cycloneive_lcell_comb \z80_|sequencer_|DFFE_M2_ff~0 (
|
|
// Equation(s):
|
|
// \z80_|sequencer_|DFFE_M2_ff~0_combout = (\z80_|execute_|setM1~54_combout & ((\z80_|execute_|nextM~14_combout & (!\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M2_ff~q )))))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.datab(\z80_|execute_|setM1~54_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_M2_ff~q ),
|
|
.datad(\z80_|execute_|nextM~14_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|sequencer_|DFFE_M2_ff~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|sequencer_|DFFE_M2_ff~0 .lut_mask = 16'h44C0;
|
|
defparam \z80_|sequencer_|DFFE_M2_ff~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X26_Y13_N23
|
|
dffeas \z80_|sequencer_|DFFE_M2_ff (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|sequencer_|DFFE_M2_ff~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|sequencer_|DFFE_M2_ff~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|sequencer_|DFFE_M2_ff .is_wysiwyg = "true";
|
|
defparam \z80_|sequencer_|DFFE_M2_ff .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y13_N6
|
|
cycloneive_lcell_comb \z80_|sequencer_|DFFE_M3_ff~0 (
|
|
// Equation(s):
|
|
// \z80_|sequencer_|DFFE_M3_ff~0_combout = (\z80_|execute_|setM1~54_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M3_ff~q )))))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_M2_ff~q ),
|
|
.datab(\z80_|execute_|setM1~54_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_M3_ff~q ),
|
|
.datad(\z80_|execute_|nextM~14_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|sequencer_|DFFE_M3_ff~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|sequencer_|DFFE_M3_ff~0 .lut_mask = 16'h88C0;
|
|
defparam \z80_|sequencer_|DFFE_M3_ff~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X26_Y13_N7
|
|
dffeas \z80_|sequencer_|DFFE_M3_ff (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|sequencer_|DFFE_M3_ff~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|sequencer_|DFFE_M3_ff~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|sequencer_|DFFE_M3_ff .is_wysiwyg = "true";
|
|
defparam \z80_|sequencer_|DFFE_M3_ff .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y13_N10
|
|
cycloneive_lcell_comb \z80_|sequencer_|DFFE_M4_ff~0 (
|
|
// Equation(s):
|
|
// \z80_|sequencer_|DFFE_M4_ff~0_combout = (\z80_|execute_|setM1~54_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|DFFE_M4_ff~q )))))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_M3_ff~q ),
|
|
.datab(\z80_|execute_|setM1~54_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_M4_ff~q ),
|
|
.datad(\z80_|execute_|nextM~14_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|sequencer_|DFFE_M4_ff~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|sequencer_|DFFE_M4_ff~0 .lut_mask = 16'h88C0;
|
|
defparam \z80_|sequencer_|DFFE_M4_ff~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X26_Y13_N11
|
|
dffeas \z80_|sequencer_|DFFE_M4_ff (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|sequencer_|DFFE_M4_ff~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|sequencer_|DFFE_M4_ff~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|sequencer_|DFFE_M4_ff .is_wysiwyg = "true";
|
|
defparam \z80_|sequencer_|DFFE_M4_ff .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y13_N0
|
|
cycloneive_lcell_comb \z80_|sequencer_|M5~0 (
|
|
// Equation(s):
|
|
// \z80_|sequencer_|M5~0_combout = (\z80_|execute_|setM1~54_combout & ((\z80_|execute_|nextM~14_combout & (\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|execute_|nextM~14_combout & ((\z80_|sequencer_|M5~q )))))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_M4_ff~q ),
|
|
.datab(\z80_|execute_|setM1~54_combout ),
|
|
.datac(\z80_|sequencer_|M5~q ),
|
|
.datad(\z80_|execute_|nextM~14_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|sequencer_|M5~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|sequencer_|M5~0 .lut_mask = 16'h88C0;
|
|
defparam \z80_|sequencer_|M5~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X26_Y13_N1
|
|
dffeas \z80_|sequencer_|M5 (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|sequencer_|M5~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|sequencer_|M5~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|sequencer_|M5 .is_wysiwyg = "true";
|
|
defparam \z80_|sequencer_|M5 .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y11_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ixy_d~5 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ixy_d~5_combout = (\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|sequencer_|DFFE_M3_ff~q ),
|
|
.datac(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ixy_d~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ixy_d~5 .lut_mask = 16'hC0C0;
|
|
defparam \z80_|execute_|ixy_d~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y12_N24
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~22 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op_low~22_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M2_ff~q )
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|sequencer_|DFFE_M2_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op_low~22_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op_low~22 .lut_mask = 16'hAA00;
|
|
defparam \z80_|execute_|ctl_alu_op_low~22 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y16_N30
|
|
cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_11 (
|
|
// Equation(s):
|
|
// \z80_|resets_|SYNTHESIZED_WIRE_11~combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T2_ff~q )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.datad(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .lut_mask = 16'hFF0F;
|
|
defparam \z80_|resets_|SYNTHESIZED_WIRE_11 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y15_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_ir_we~4_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M4_ff~q )
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|sequencer_|DFFE_M4_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_ir_we~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_ir_we~4 .lut_mask = 16'h5500;
|
|
defparam \z80_|execute_|ctl_ir_we~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y16_N6
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_state_iy_set~2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_state_iy_set~2_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~2_combout )))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.datab(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.datac(\z80_|ir_|opcode [5]),
|
|
.datad(\z80_|pla_decode_|Equal3~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_state_iy_set~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_state_iy_set~2 .lut_mask = 16'h2000;
|
|
defparam \z80_|execute_|ctl_state_iy_set~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y13_N18
|
|
cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_16 (
|
|
// Equation(s):
|
|
// \z80_|sequencer_|SYNTHESIZED_WIRE_16~combout = (\z80_|execute_|setM1~54_combout & (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|execute_|nextM~14_combout ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|execute_|setM1~54_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_T4_ff~q ),
|
|
.datad(\z80_|execute_|nextM~14_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .lut_mask = 16'h00C0;
|
|
defparam \z80_|sequencer_|SYNTHESIZED_WIRE_16 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X26_Y13_N19
|
|
dffeas \z80_|sequencer_|DFFE_T5_ff (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|sequencer_|SYNTHESIZED_WIRE_16~combout ),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|clk_delay_|hold_clk_iorq~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|sequencer_|DFFE_T5_ff~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|sequencer_|DFFE_T5_ff .is_wysiwyg = "true";
|
|
defparam \z80_|sequencer_|DFFE_T5_ff .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y16_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_state_ixiy_we~2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_state_ixiy_we~2_combout = (\z80_|execute_|ixy_d~15_combout & ((\z80_|sequencer_|DFFE_T5_ff~q ) # ((!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )))) # (!\z80_|execute_|ixy_d~15_combout &
|
|
// (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q )))
|
|
|
|
.dataa(\z80_|execute_|ixy_d~15_combout ),
|
|
.datab(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.datac(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.datad(\z80_|sequencer_|DFFE_T5_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_state_ixiy_we~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_state_ixiy_we~2 .lut_mask = 16'hBA30;
|
|
defparam \z80_|execute_|ctl_state_ixiy_we~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X26_Y16_N7
|
|
dffeas \z80_|decode_state_|DFFE_instIY1 (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|execute_|ctl_state_iy_set~2_combout ),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|decode_state_|DFFE_instIY1~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|decode_state_|DFFE_instIY1 .is_wysiwyg = "true";
|
|
defparam \z80_|decode_state_|DFFE_instIY1 .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y16_N10
|
|
cycloneive_lcell_comb \z80_|decode_state_|use_ixiy (
|
|
// Equation(s):
|
|
// \z80_|decode_state_|use_ixiy~combout = (\z80_|decode_state_|DFFE_inst4~q ) # (\z80_|decode_state_|DFFE_instIY1~q )
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|decode_state_|DFFE_inst4~q ),
|
|
.datac(gnd),
|
|
.datad(\z80_|decode_state_|DFFE_instIY1~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|decode_state_|use_ixiy~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|decode_state_|use_ixiy .lut_mask = 16'hFFCC;
|
|
defparam \z80_|decode_state_|use_ixiy .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y12_N28
|
|
cycloneive_lcell_comb \z80_|execute_|ixy_d~4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ixy_d~4_combout = (!\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.datac(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datad(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ixy_d~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ixy_d~4 .lut_mask = 16'h0030;
|
|
defparam \z80_|execute_|ixy_d~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y12_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ixy_d~11 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ixy_d~11_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|execute_|ixy_d~4_combout ))))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T4_ff~q ),
|
|
.datab(\z80_|sequencer_|DFFE_M3_ff~q ),
|
|
.datac(\z80_|sequencer_|DFFE_T5_ff~q ),
|
|
.datad(\z80_|execute_|ixy_d~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ixy_d~11_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ixy_d~11 .lut_mask = 16'hC8CC;
|
|
defparam \z80_|execute_|ixy_d~11 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y14_N6
|
|
cycloneive_lcell_comb \z80_|execute_|ixy_d~9 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ixy_d~9_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M3_ff~q )
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T4_ff~q ),
|
|
.datab(gnd),
|
|
.datac(\z80_|sequencer_|DFFE_M3_ff~q ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ixy_d~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ixy_d~9 .lut_mask = 16'hA0A0;
|
|
defparam \z80_|execute_|ixy_d~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y15_N28
|
|
cycloneive_lcell_comb \z80_|execute_|ixy_d~7 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ixy_d~7_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M3_ff~q )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datad(\z80_|sequencer_|DFFE_M3_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ixy_d~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ixy_d~7 .lut_mask = 16'h0F00;
|
|
defparam \z80_|execute_|ixy_d~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y13_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ixy_d~6 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ixy_d~6_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M3_ff~q )
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.datab(gnd),
|
|
.datac(\z80_|sequencer_|DFFE_M3_ff~q ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ixy_d~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ixy_d~6 .lut_mask = 16'hA0A0;
|
|
defparam \z80_|execute_|ixy_d~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y13_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ixy_d~8 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ixy_d~8_combout = (\z80_|sequencer_|DFFE_T5_ff~q & \z80_|sequencer_|DFFE_M3_ff~q )
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|sequencer_|DFFE_T5_ff~q ),
|
|
.datac(gnd),
|
|
.datad(\z80_|sequencer_|DFFE_M3_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ixy_d~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ixy_d~8 .lut_mask = 16'hCC00;
|
|
defparam \z80_|execute_|ixy_d~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y18_N24
|
|
cycloneive_lcell_comb \z80_|execute_|ixy_d~12 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ixy_d~12_combout = (!\z80_|execute_|ixy_d~9_combout & (!\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ixy_d~6_combout & !\z80_|execute_|ixy_d~8_combout )))
|
|
|
|
.dataa(\z80_|execute_|ixy_d~9_combout ),
|
|
.datab(\z80_|execute_|ixy_d~7_combout ),
|
|
.datac(\z80_|execute_|ixy_d~6_combout ),
|
|
.datad(\z80_|execute_|ixy_d~8_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ixy_d~12_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ixy_d~12 .lut_mask = 16'h0001;
|
|
defparam \z80_|execute_|ixy_d~12 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y13_N24
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal33~0 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal33~0_combout = (\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [0] & \z80_|ir_|opcode [1]))
|
|
|
|
.dataa(\z80_|ir_|opcode [2]),
|
|
.datab(\z80_|ir_|opcode [0]),
|
|
.datac(gnd),
|
|
.datad(\z80_|ir_|opcode [1]),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal33~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal33~0 .lut_mask = 16'h2200;
|
|
defparam \z80_|pla_decode_|Equal33~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y17_N12
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal33~1 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal33~1_combout = (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3]))
|
|
|
|
.dataa(\z80_|ir_|opcode [5]),
|
|
.datab(\z80_|ir_|opcode [4]),
|
|
.datac(gnd),
|
|
.datad(\z80_|ir_|opcode [3]),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal33~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal33~1 .lut_mask = 16'h0088;
|
|
defparam \z80_|pla_decode_|Equal33~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y15_N24
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal33~2 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal33~2_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal33~1_combout ))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal33~0_combout ),
|
|
.datab(\z80_|pla_decode_|Equal6~0_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|pla_decode_|Equal33~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal33~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal33~2 .lut_mask = 16'h8800;
|
|
defparam \z80_|pla_decode_|Equal33~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y19_N16
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal21~0 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal21~0_combout = (\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3])
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|ir_|opcode [4]),
|
|
.datac(gnd),
|
|
.datad(\z80_|ir_|opcode [3]),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal21~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal21~0 .lut_mask = 16'h00CC;
|
|
defparam \z80_|pla_decode_|Equal21~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y16_N12
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal77~0 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal77~0_combout = (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6])))
|
|
|
|
.dataa(\z80_|decode_state_|DFFE_instCB~q ),
|
|
.datab(\z80_|decode_state_|DFFE_instED~q ),
|
|
.datac(\z80_|ir_|opcode [7]),
|
|
.datad(\z80_|ir_|opcode [6]),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal77~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal77~0 .lut_mask = 16'h0100;
|
|
defparam \z80_|pla_decode_|Equal77~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y16_N16
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal77~1 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal77~1_combout = (\z80_|pla_decode_|Equal21~0_combout & (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal77~0_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal21~0_combout ),
|
|
.datab(\z80_|ir_|opcode [5]),
|
|
.datac(\z80_|pla_decode_|Equal33~0_combout ),
|
|
.datad(\z80_|pla_decode_|Equal77~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal77~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal77~1 .lut_mask = 16'h8000;
|
|
defparam \z80_|pla_decode_|Equal77~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y13_N26
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal1~7 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal1~7_combout = (\z80_|ir_|opcode [0] & (\z80_|ir_|opcode [6] & (!\z80_|decode_state_|table_xx~0_combout & \z80_|ir_|opcode [7])))
|
|
|
|
.dataa(\z80_|ir_|opcode [0]),
|
|
.datab(\z80_|ir_|opcode [6]),
|
|
.datac(\z80_|decode_state_|table_xx~0_combout ),
|
|
.datad(\z80_|ir_|opcode [7]),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal1~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal1~7 .lut_mask = 16'h0800;
|
|
defparam \z80_|pla_decode_|Equal1~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y17_N26
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal79~0 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal79~0_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|ir_|opcode [4])))
|
|
|
|
.dataa(\z80_|ir_|opcode [5]),
|
|
.datab(\z80_|pla_decode_|Equal2~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal1~7_combout ),
|
|
.datad(\z80_|ir_|opcode [4]),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal79~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal79~0 .lut_mask = 16'h8000;
|
|
defparam \z80_|pla_decode_|Equal79~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y17_N12
|
|
cycloneive_lcell_comb \z80_|interrupts_|iff1~0 (
|
|
// Equation(s):
|
|
// \z80_|interrupts_|iff1~0_combout = (\z80_|pla_decode_|Equal79~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|ir_|opcode [3]))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|interrupts_|iff1~q )))) #
|
|
// (!\z80_|pla_decode_|Equal79~0_combout & (((\z80_|interrupts_|iff1~q ))))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal79~0_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ),
|
|
.datac(\z80_|interrupts_|iff1~q ),
|
|
.datad(\z80_|ir_|opcode [3]),
|
|
.cin(gnd),
|
|
.combout(\z80_|interrupts_|iff1~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|interrupts_|iff1~0 .lut_mask = 16'hF870;
|
|
defparam \z80_|interrupts_|iff1~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y17_N30
|
|
cycloneive_lcell_comb \z80_|interrupts_|DFFE_instIFF2~0 (
|
|
// Equation(s):
|
|
// \z80_|interrupts_|DFFE_instIFF2~0_combout = (\z80_|pla_decode_|Equal79~0_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|ir_|opcode [3]))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|interrupts_|DFFE_instIFF2~q
|
|
// )))) # (!\z80_|pla_decode_|Equal79~0_combout & (((\z80_|interrupts_|DFFE_instIFF2~q ))))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal79~0_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ),
|
|
.datac(\z80_|interrupts_|DFFE_instIFF2~q ),
|
|
.datad(\z80_|ir_|opcode [3]),
|
|
.cin(gnd),
|
|
.combout(\z80_|interrupts_|DFFE_instIFF2~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|interrupts_|DFFE_instIFF2~0 .lut_mask = 16'hF870;
|
|
defparam \z80_|interrupts_|DFFE_instIFF2~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y11_N24
|
|
cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_12 (
|
|
// Equation(s):
|
|
// \z80_|interrupts_|SYNTHESIZED_WIRE_12~combout = ((\z80_|interrupts_|DFFE_inst44~q & !\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )
|
|
|
|
.dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.datab(\z80_|interrupts_|DFFE_inst44~q ),
|
|
.datac(gnd),
|
|
.datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|interrupts_|SYNTHESIZED_WIRE_12~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .lut_mask = 16'h55DD;
|
|
defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: CLKCTRL_G16
|
|
cycloneive_clkctrl \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl (
|
|
.ena(vcc),
|
|
.inclk({vcc,vcc,vcc,\z80_|interrupts_|SYNTHESIZED_WIRE_12~combout }),
|
|
.clkselect(2'b00),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.outclk(\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ));
|
|
// synopsys translate_off
|
|
defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .clock_type = "global clock";
|
|
defparam \z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl .ena_register_mode = "none";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X29_Y17_N31
|
|
dffeas \z80_|interrupts_|DFFE_instIFF2 (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|interrupts_|DFFE_instIFF2~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|interrupts_|DFFE_instIFF2~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|interrupts_|DFFE_instIFF2 .is_wysiwyg = "true";
|
|
defparam \z80_|interrupts_|DFFE_instIFF2 .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y13_N6
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal13~0 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal13~0_combout = (\z80_|decode_state_|DFFE_instED~q & (!\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6]))
|
|
|
|
.dataa(\z80_|decode_state_|DFFE_instED~q ),
|
|
.datab(gnd),
|
|
.datac(\z80_|ir_|opcode [7]),
|
|
.datad(\z80_|ir_|opcode [6]),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal13~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal13~0 .lut_mask = 16'h0A00;
|
|
defparam \z80_|pla_decode_|Equal13~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y16_N12
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal38~2 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal38~2_combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0])))
|
|
|
|
.dataa(\z80_|ir_|opcode [2]),
|
|
.datab(\z80_|pla_decode_|Equal13~0_combout ),
|
|
.datac(\z80_|ir_|opcode [1]),
|
|
.datad(\z80_|ir_|opcode [0]),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal38~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal38~2 .lut_mask = 16'h0800;
|
|
defparam \z80_|pla_decode_|Equal38~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y17_N0
|
|
cycloneive_lcell_comb \z80_|interrupts_|iff1~1 (
|
|
// Equation(s):
|
|
// \z80_|interrupts_|iff1~1_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal38~2_combout & ((\z80_|interrupts_|DFFE_instIFF2~q ))) # (!\z80_|pla_decode_|Equal38~2_combout & (\z80_|interrupts_|iff1~0_combout )))) #
|
|
// (!\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|interrupts_|iff1~0_combout ))
|
|
|
|
.dataa(\z80_|interrupts_|iff1~0_combout ),
|
|
.datab(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.datac(\z80_|interrupts_|DFFE_instIFF2~q ),
|
|
.datad(\z80_|pla_decode_|Equal38~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|interrupts_|iff1~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|interrupts_|iff1~1 .lut_mask = 16'hE2AA;
|
|
defparam \z80_|interrupts_|iff1~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y13_N20
|
|
cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_15 (
|
|
// Equation(s):
|
|
// \z80_|interrupts_|SYNTHESIZED_WIRE_15~combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|interrupts_|DFFE_inst44~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))
|
|
|
|
.dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ),
|
|
.datab(gnd),
|
|
.datac(\z80_|interrupts_|DFFE_inst44~q ),
|
|
.datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .lut_mask = 16'hFAFF;
|
|
defparam \z80_|interrupts_|SYNTHESIZED_WIRE_15 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X29_Y17_N1
|
|
dffeas \z80_|interrupts_|iff1 (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|interrupts_|iff1~1_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_15~combout ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|interrupts_|iff1~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|interrupts_|iff1 .is_wysiwyg = "true";
|
|
defparam \z80_|interrupts_|iff1 .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: CLKCTRL_G18
|
|
cycloneive_clkctrl \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl (
|
|
.ena(vcc),
|
|
.inclk({vcc,vcc,vcc,\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [0]}),
|
|
.clkselect(2'b00),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.outclk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ));
|
|
// synopsys translate_off
|
|
defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .clock_type = "global clock";
|
|
defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y32_N6
|
|
cycloneive_lcell_comb \ula_|video_|Add0~0 (
|
|
// Equation(s):
|
|
// \ula_|video_|Add0~0_combout = \ula_|video_|vga_hc [0] $ (VCC)
|
|
// \ula_|video_|Add0~1 = CARRY(\ula_|video_|vga_hc [0])
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|video_|vga_hc [0]),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|Add0~0_combout ),
|
|
.cout(\ula_|video_|Add0~1 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Add0~0 .lut_mask = 16'h33CC;
|
|
defparam \ula_|video_|Add0~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y32_N28
|
|
cycloneive_lcell_comb \ula_|video_|vga_hc~3 (
|
|
// Equation(s):
|
|
// \ula_|video_|vga_hc~3_combout = (\ula_|video_|Add0~0_combout & \ula_|video_|Equal1~0_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|video_|Add0~0_combout ),
|
|
.datac(gnd),
|
|
.datad(\ula_|video_|Equal1~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|vga_hc~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vga_hc~3 .lut_mask = 16'hCC00;
|
|
defparam \ula_|video_|vga_hc~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y32_N13
|
|
dffeas \ula_|video_|vga_hc[0] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\ula_|video_|vga_hc~3_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|vga_hc [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vga_hc[0] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|vga_hc[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y32_N8
|
|
cycloneive_lcell_comb \ula_|video_|Add0~2 (
|
|
// Equation(s):
|
|
// \ula_|video_|Add0~2_combout = (\ula_|video_|vga_hc [1] & (!\ula_|video_|Add0~1 )) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|Add0~1 ) # (GND)))
|
|
// \ula_|video_|Add0~3 = CARRY((!\ula_|video_|Add0~1 ) # (!\ula_|video_|vga_hc [1]))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|video_|vga_hc [1]),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\ula_|video_|Add0~1 ),
|
|
.combout(\ula_|video_|Add0~2_combout ),
|
|
.cout(\ula_|video_|Add0~3 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Add0~2 .lut_mask = 16'h3C3F;
|
|
defparam \ula_|video_|Add0~2 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y32_N25
|
|
dffeas \ula_|video_|vga_hc[1] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\ula_|video_|Add0~2_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|vga_hc [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vga_hc[1] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|vga_hc[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y32_N10
|
|
cycloneive_lcell_comb \ula_|video_|Add0~4 (
|
|
// Equation(s):
|
|
// \ula_|video_|Add0~4_combout = (\ula_|video_|vga_hc [2] & (\ula_|video_|Add0~3 $ (GND))) # (!\ula_|video_|vga_hc [2] & (!\ula_|video_|Add0~3 & VCC))
|
|
// \ula_|video_|Add0~5 = CARRY((\ula_|video_|vga_hc [2] & !\ula_|video_|Add0~3 ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|video_|vga_hc [2]),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\ula_|video_|Add0~3 ),
|
|
.combout(\ula_|video_|Add0~4_combout ),
|
|
.cout(\ula_|video_|Add0~5 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Add0~4 .lut_mask = 16'hC30C;
|
|
defparam \ula_|video_|Add0~4 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y32_N3
|
|
dffeas \ula_|video_|vga_hc[2] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\ula_|video_|Add0~4_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|vga_hc [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vga_hc[2] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|vga_hc[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y32_N12
|
|
cycloneive_lcell_comb \ula_|video_|Add0~6 (
|
|
// Equation(s):
|
|
// \ula_|video_|Add0~6_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|Add0~5 )) # (!\ula_|video_|vga_hc [3] & ((\ula_|video_|Add0~5 ) # (GND)))
|
|
// \ula_|video_|Add0~7 = CARRY((!\ula_|video_|Add0~5 ) # (!\ula_|video_|vga_hc [3]))
|
|
|
|
.dataa(\ula_|video_|vga_hc [3]),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\ula_|video_|Add0~5 ),
|
|
.combout(\ula_|video_|Add0~6_combout ),
|
|
.cout(\ula_|video_|Add0~7 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Add0~6 .lut_mask = 16'h5A5F;
|
|
defparam \ula_|video_|Add0~6 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y32_N21
|
|
dffeas \ula_|video_|vga_hc[3] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\ula_|video_|Add0~6_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|vga_hc [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vga_hc[3] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|vga_hc[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y32_N14
|
|
cycloneive_lcell_comb \ula_|video_|Add0~8 (
|
|
// Equation(s):
|
|
// \ula_|video_|Add0~8_combout = (\ula_|video_|vga_hc [4] & (\ula_|video_|Add0~7 $ (GND))) # (!\ula_|video_|vga_hc [4] & (!\ula_|video_|Add0~7 & VCC))
|
|
// \ula_|video_|Add0~9 = CARRY((\ula_|video_|vga_hc [4] & !\ula_|video_|Add0~7 ))
|
|
|
|
.dataa(\ula_|video_|vga_hc [4]),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\ula_|video_|Add0~7 ),
|
|
.combout(\ula_|video_|Add0~8_combout ),
|
|
.cout(\ula_|video_|Add0~9 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Add0~8 .lut_mask = 16'hA50A;
|
|
defparam \ula_|video_|Add0~8 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y32_N3
|
|
dffeas \ula_|video_|vga_hc[4] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\ula_|video_|Add0~8_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|vga_hc [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vga_hc[4] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|vga_hc[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y32_N16
|
|
cycloneive_lcell_comb \ula_|video_|Add0~10 (
|
|
// Equation(s):
|
|
// \ula_|video_|Add0~10_combout = (\ula_|video_|vga_hc [5] & (!\ula_|video_|Add0~9 )) # (!\ula_|video_|vga_hc [5] & ((\ula_|video_|Add0~9 ) # (GND)))
|
|
// \ula_|video_|Add0~11 = CARRY((!\ula_|video_|Add0~9 ) # (!\ula_|video_|vga_hc [5]))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|video_|vga_hc [5]),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\ula_|video_|Add0~9 ),
|
|
.combout(\ula_|video_|Add0~10_combout ),
|
|
.cout(\ula_|video_|Add0~11 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Add0~10 .lut_mask = 16'h3C3F;
|
|
defparam \ula_|video_|Add0~10 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y32_N26
|
|
cycloneive_lcell_comb \ula_|video_|vga_hc~0 (
|
|
// Equation(s):
|
|
// \ula_|video_|vga_hc~0_combout = (\ula_|video_|Add0~10_combout & \ula_|video_|Equal1~0_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|video_|Add0~10_combout ),
|
|
.datac(gnd),
|
|
.datad(\ula_|video_|Equal1~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|vga_hc~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vga_hc~0 .lut_mask = 16'hCC00;
|
|
defparam \ula_|video_|vga_hc~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y32_N29
|
|
dffeas \ula_|video_|vga_hc[5] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\ula_|video_|vga_hc~0_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|vga_hc [5]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vga_hc[5] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|vga_hc[5] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y32_N18
|
|
cycloneive_lcell_comb \ula_|video_|Add0~12 (
|
|
// Equation(s):
|
|
// \ula_|video_|Add0~12_combout = (\ula_|video_|vga_hc [6] & (\ula_|video_|Add0~11 $ (GND))) # (!\ula_|video_|vga_hc [6] & (!\ula_|video_|Add0~11 & VCC))
|
|
// \ula_|video_|Add0~13 = CARRY((\ula_|video_|vga_hc [6] & !\ula_|video_|Add0~11 ))
|
|
|
|
.dataa(\ula_|video_|vga_hc [6]),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\ula_|video_|Add0~11 ),
|
|
.combout(\ula_|video_|Add0~12_combout ),
|
|
.cout(\ula_|video_|Add0~13 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Add0~12 .lut_mask = 16'hA50A;
|
|
defparam \ula_|video_|Add0~12 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y32_N5
|
|
dffeas \ula_|video_|vga_hc[6] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\ula_|video_|Add0~12_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|vga_hc [6]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vga_hc[6] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|vga_hc[6] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y32_N20
|
|
cycloneive_lcell_comb \ula_|video_|Add0~14 (
|
|
// Equation(s):
|
|
// \ula_|video_|Add0~14_combout = (\ula_|video_|vga_hc [7] & (!\ula_|video_|Add0~13 )) # (!\ula_|video_|vga_hc [7] & ((\ula_|video_|Add0~13 ) # (GND)))
|
|
// \ula_|video_|Add0~15 = CARRY((!\ula_|video_|Add0~13 ) # (!\ula_|video_|vga_hc [7]))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|video_|vga_hc [7]),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\ula_|video_|Add0~13 ),
|
|
.combout(\ula_|video_|Add0~14_combout ),
|
|
.cout(\ula_|video_|Add0~15 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Add0~14 .lut_mask = 16'h3C3F;
|
|
defparam \ula_|video_|Add0~14 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y32_N27
|
|
dffeas \ula_|video_|vga_hc[7] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\ula_|video_|Add0~14_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|vga_hc [7]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vga_hc[7] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|vga_hc[7] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y32_N22
|
|
cycloneive_lcell_comb \ula_|video_|Add0~16 (
|
|
// Equation(s):
|
|
// \ula_|video_|Add0~16_combout = (\ula_|video_|vga_hc [8] & (\ula_|video_|Add0~15 $ (GND))) # (!\ula_|video_|vga_hc [8] & (!\ula_|video_|Add0~15 & VCC))
|
|
// \ula_|video_|Add0~17 = CARRY((\ula_|video_|vga_hc [8] & !\ula_|video_|Add0~15 ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|video_|vga_hc [8]),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\ula_|video_|Add0~15 ),
|
|
.combout(\ula_|video_|Add0~16_combout ),
|
|
.cout(\ula_|video_|Add0~17 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Add0~16 .lut_mask = 16'hC30C;
|
|
defparam \ula_|video_|Add0~16 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y32_N2
|
|
cycloneive_lcell_comb \ula_|video_|vga_hc~2 (
|
|
// Equation(s):
|
|
// \ula_|video_|vga_hc~2_combout = (\ula_|video_|Add0~16_combout & \ula_|video_|Equal1~0_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|video_|Add0~16_combout ),
|
|
.datac(gnd),
|
|
.datad(\ula_|video_|Equal1~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|vga_hc~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vga_hc~2 .lut_mask = 16'hCC00;
|
|
defparam \ula_|video_|vga_hc~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y32_N27
|
|
dffeas \ula_|video_|vga_hc[8] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\ula_|video_|vga_hc~2_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|vga_hc [8]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vga_hc[8] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|vga_hc[8] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y32_N24
|
|
cycloneive_lcell_comb \ula_|video_|Add0~18 (
|
|
// Equation(s):
|
|
// \ula_|video_|Add0~18_combout = \ula_|video_|Add0~17 $ (\ula_|video_|vga_hc [9])
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\ula_|video_|vga_hc [9]),
|
|
.cin(\ula_|video_|Add0~17 ),
|
|
.combout(\ula_|video_|Add0~18_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Add0~18 .lut_mask = 16'h0FF0;
|
|
defparam \ula_|video_|Add0~18 .sum_lutc_input = "cin";
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|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y32_N4
|
|
cycloneive_lcell_comb \ula_|video_|vga_hc~1 (
|
|
// Equation(s):
|
|
// \ula_|video_|vga_hc~1_combout = (\ula_|video_|Add0~18_combout & \ula_|video_|Equal1~0_combout )
|
|
|
|
.dataa(\ula_|video_|Add0~18_combout ),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\ula_|video_|Equal1~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|vga_hc~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vga_hc~1 .lut_mask = 16'hAA00;
|
|
defparam \ula_|video_|vga_hc~1 .sum_lutc_input = "datac";
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|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y32_N1
|
|
dffeas \ula_|video_|vga_hc[9] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\ula_|video_|vga_hc~1_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|vga_hc [9]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
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|
defparam \ula_|video_|vga_hc[9] .is_wysiwyg = "true";
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|
defparam \ula_|video_|vga_hc[9] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y31_N14
|
|
cycloneive_lcell_comb \ula_|video_|Equal0~0 (
|
|
// Equation(s):
|
|
// \ula_|video_|Equal0~0_combout = (!\ula_|video_|vga_hc [1] & (!\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [2] & !\ula_|video_|vga_hc [0])))
|
|
|
|
.dataa(\ula_|video_|vga_hc [1]),
|
|
.datab(\ula_|video_|vga_hc [3]),
|
|
.datac(\ula_|video_|vga_hc [2]),
|
|
.datad(\ula_|video_|vga_hc [0]),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|Equal0~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Equal0~0 .lut_mask = 16'h0001;
|
|
defparam \ula_|video_|Equal0~0 .sum_lutc_input = "datac";
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|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y31_N24
|
|
cycloneive_lcell_comb \ula_|video_|Equal0~1 (
|
|
// Equation(s):
|
|
// \ula_|video_|Equal0~1_combout = (!\ula_|video_|vga_hc [4] & (!\ula_|video_|vga_hc [7] & (\ula_|video_|Equal0~0_combout & \ula_|video_|vga_hc [5])))
|
|
|
|
.dataa(\ula_|video_|vga_hc [4]),
|
|
.datab(\ula_|video_|vga_hc [7]),
|
|
.datac(\ula_|video_|Equal0~0_combout ),
|
|
.datad(\ula_|video_|vga_hc [5]),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|Equal0~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Equal0~1 .lut_mask = 16'h1000;
|
|
defparam \ula_|video_|Equal0~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y31_N8
|
|
cycloneive_lcell_comb \ula_|video_|Equal1~0 (
|
|
// Equation(s):
|
|
// \ula_|video_|Equal1~0_combout = ((\ula_|video_|vga_hc [6]) # ((!\ula_|video_|Equal0~1_combout ) # (!\ula_|video_|vga_hc [8]))) # (!\ula_|video_|vga_hc [9])
|
|
|
|
.dataa(\ula_|video_|vga_hc [9]),
|
|
.datab(\ula_|video_|vga_hc [6]),
|
|
.datac(\ula_|video_|vga_hc [8]),
|
|
.datad(\ula_|video_|Equal0~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|Equal1~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Equal1~0 .lut_mask = 16'hDFFF;
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|
defparam \ula_|video_|Equal1~0 .sum_lutc_input = "datac";
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|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y31_N2
|
|
cycloneive_lcell_comb \ula_|video_|Add1~0 (
|
|
// Equation(s):
|
|
// \ula_|video_|Add1~0_combout = \ula_|video_|vga_vc [0] $ (VCC)
|
|
// \ula_|video_|Add1~1 = CARRY(\ula_|video_|vga_vc [0])
|
|
|
|
.dataa(\ula_|video_|vga_vc [0]),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|Add1~0_combout ),
|
|
.cout(\ula_|video_|Add1~1 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Add1~0 .lut_mask = 16'h55AA;
|
|
defparam \ula_|video_|Add1~0 .sum_lutc_input = "datac";
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|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y31_N28
|
|
cycloneive_lcell_comb \ula_|video_|vga_vc[0]~0 (
|
|
// Equation(s):
|
|
// \ula_|video_|vga_vc[0]~0_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [0]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~0_combout ))))
|
|
|
|
.dataa(\ula_|video_|Equal1~0_combout ),
|
|
.datab(\ula_|video_|Equal3~1_combout ),
|
|
.datac(\ula_|video_|Add1~0_combout ),
|
|
.datad(\ula_|video_|vga_vc [0]),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|vga_vc[0]~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vga_vc[0]~0 .lut_mask = 16'h3210;
|
|
defparam \ula_|video_|vga_vc[0]~0 .sum_lutc_input = "datac";
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|
// synopsys translate_on
|
|
|
|
// Location: FF_X36_Y32_N29
|
|
dffeas \ula_|video_|vga_vc[0] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\ula_|video_|vga_vc[0]~0_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|vga_vc [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vga_vc[0] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|vga_vc[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y31_N4
|
|
cycloneive_lcell_comb \ula_|video_|Add1~2 (
|
|
// Equation(s):
|
|
// \ula_|video_|Add1~2_combout = (\ula_|video_|vga_vc [1] & (!\ula_|video_|Add1~1 )) # (!\ula_|video_|vga_vc [1] & ((\ula_|video_|Add1~1 ) # (GND)))
|
|
// \ula_|video_|Add1~3 = CARRY((!\ula_|video_|Add1~1 ) # (!\ula_|video_|vga_vc [1]))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|video_|vga_vc [1]),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\ula_|video_|Add1~1 ),
|
|
.combout(\ula_|video_|Add1~2_combout ),
|
|
.cout(\ula_|video_|Add1~3 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Add1~2 .lut_mask = 16'h3C3F;
|
|
defparam \ula_|video_|Add1~2 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y32_N10
|
|
cycloneive_lcell_comb \ula_|video_|vga_vc[1]~1 (
|
|
// Equation(s):
|
|
// \ula_|video_|vga_vc[1]~1_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [1]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~2_combout ))))
|
|
|
|
.dataa(\ula_|video_|Equal1~0_combout ),
|
|
.datab(\ula_|video_|Add1~2_combout ),
|
|
.datac(\ula_|video_|vga_vc [1]),
|
|
.datad(\ula_|video_|Equal3~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|vga_vc[1]~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vga_vc[1]~1 .lut_mask = 16'h00E4;
|
|
defparam \ula_|video_|vga_vc[1]~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X36_Y32_N11
|
|
dffeas \ula_|video_|vga_vc[1] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|vga_vc[1]~1_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|vga_vc [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vga_vc[1] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|vga_vc[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y31_N6
|
|
cycloneive_lcell_comb \ula_|video_|Add1~4 (
|
|
// Equation(s):
|
|
// \ula_|video_|Add1~4_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add1~3 $ (GND))) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add1~3 & VCC))
|
|
// \ula_|video_|Add1~5 = CARRY((\ula_|video_|vga_vc [2] & !\ula_|video_|Add1~3 ))
|
|
|
|
.dataa(\ula_|video_|vga_vc [2]),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\ula_|video_|Add1~3 ),
|
|
.combout(\ula_|video_|Add1~4_combout ),
|
|
.cout(\ula_|video_|Add1~5 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Add1~4 .lut_mask = 16'hA50A;
|
|
defparam \ula_|video_|Add1~4 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y31_N22
|
|
cycloneive_lcell_comb \ula_|video_|vga_vc[2]~2 (
|
|
// Equation(s):
|
|
// \ula_|video_|vga_vc[2]~2_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [2])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~4_combout )))))
|
|
|
|
.dataa(\ula_|video_|Equal1~0_combout ),
|
|
.datab(\ula_|video_|Equal3~1_combout ),
|
|
.datac(\ula_|video_|vga_vc [2]),
|
|
.datad(\ula_|video_|Add1~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|vga_vc[2]~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vga_vc[2]~2 .lut_mask = 16'h3120;
|
|
defparam \ula_|video_|vga_vc[2]~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y32_N24
|
|
cycloneive_lcell_comb \ula_|video_|vga_vc[2]~feeder (
|
|
// Equation(s):
|
|
// \ula_|video_|vga_vc[2]~feeder_combout = \ula_|video_|vga_vc[2]~2_combout
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\ula_|video_|vga_vc[2]~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|vga_vc[2]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vga_vc[2]~feeder .lut_mask = 16'hFF00;
|
|
defparam \ula_|video_|vga_vc[2]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X36_Y32_N25
|
|
dffeas \ula_|video_|vga_vc[2] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|vga_vc[2]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|vga_vc [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vga_vc[2] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|vga_vc[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y31_N8
|
|
cycloneive_lcell_comb \ula_|video_|Add1~6 (
|
|
// Equation(s):
|
|
// \ula_|video_|Add1~6_combout = (\ula_|video_|vga_vc [3] & (!\ula_|video_|Add1~5 )) # (!\ula_|video_|vga_vc [3] & ((\ula_|video_|Add1~5 ) # (GND)))
|
|
// \ula_|video_|Add1~7 = CARRY((!\ula_|video_|Add1~5 ) # (!\ula_|video_|vga_vc [3]))
|
|
|
|
.dataa(\ula_|video_|vga_vc [3]),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\ula_|video_|Add1~5 ),
|
|
.combout(\ula_|video_|Add1~6_combout ),
|
|
.cout(\ula_|video_|Add1~7 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Add1~6 .lut_mask = 16'h5A5F;
|
|
defparam \ula_|video_|Add1~6 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y31_N24
|
|
cycloneive_lcell_comb \ula_|video_|vga_vc[3]~3 (
|
|
// Equation(s):
|
|
// \ula_|video_|vga_vc[3]~3_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & (\ula_|video_|vga_vc [3])) # (!\ula_|video_|Equal1~0_combout & ((\ula_|video_|Add1~6_combout )))))
|
|
|
|
.dataa(\ula_|video_|vga_vc [3]),
|
|
.datab(\ula_|video_|Equal3~1_combout ),
|
|
.datac(\ula_|video_|Add1~6_combout ),
|
|
.datad(\ula_|video_|Equal1~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|vga_vc[3]~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vga_vc[3]~3 .lut_mask = 16'h2230;
|
|
defparam \ula_|video_|vga_vc[3]~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X36_Y32_N31
|
|
dffeas \ula_|video_|vga_vc[3] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\ula_|video_|vga_vc[3]~3_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|vga_vc [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vga_vc[3] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|vga_vc[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y31_N10
|
|
cycloneive_lcell_comb \ula_|video_|Add1~8 (
|
|
// Equation(s):
|
|
// \ula_|video_|Add1~8_combout = (\ula_|video_|vga_vc [4] & (\ula_|video_|Add1~7 $ (GND))) # (!\ula_|video_|vga_vc [4] & (!\ula_|video_|Add1~7 & VCC))
|
|
// \ula_|video_|Add1~9 = CARRY((\ula_|video_|vga_vc [4] & !\ula_|video_|Add1~7 ))
|
|
|
|
.dataa(\ula_|video_|vga_vc [4]),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\ula_|video_|Add1~7 ),
|
|
.combout(\ula_|video_|Add1~8_combout ),
|
|
.cout(\ula_|video_|Add1~9 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Add1~8 .lut_mask = 16'hA50A;
|
|
defparam \ula_|video_|Add1~8 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y32_N6
|
|
cycloneive_lcell_comb \ula_|video_|vga_vc[4]~5 (
|
|
// Equation(s):
|
|
// \ula_|video_|vga_vc[4]~5_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [4]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~8_combout ))))
|
|
|
|
.dataa(\ula_|video_|Equal3~1_combout ),
|
|
.datab(\ula_|video_|Add1~8_combout ),
|
|
.datac(\ula_|video_|vga_vc [4]),
|
|
.datad(\ula_|video_|Equal1~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|vga_vc[4]~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vga_vc[4]~5 .lut_mask = 16'h5044;
|
|
defparam \ula_|video_|vga_vc[4]~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y32_N7
|
|
dffeas \ula_|video_|vga_vc[4] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|vga_vc[4]~5_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|vga_vc [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vga_vc[4] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|vga_vc[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y31_N12
|
|
cycloneive_lcell_comb \ula_|video_|Add1~10 (
|
|
// Equation(s):
|
|
// \ula_|video_|Add1~10_combout = (\ula_|video_|vga_vc [5] & (!\ula_|video_|Add1~9 )) # (!\ula_|video_|vga_vc [5] & ((\ula_|video_|Add1~9 ) # (GND)))
|
|
// \ula_|video_|Add1~11 = CARRY((!\ula_|video_|Add1~9 ) # (!\ula_|video_|vga_vc [5]))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|video_|vga_vc [5]),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\ula_|video_|Add1~9 ),
|
|
.combout(\ula_|video_|Add1~10_combout ),
|
|
.cout(\ula_|video_|Add1~11 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Add1~10 .lut_mask = 16'h3C3F;
|
|
defparam \ula_|video_|Add1~10 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y31_N14
|
|
cycloneive_lcell_comb \ula_|video_|Add1~12 (
|
|
// Equation(s):
|
|
// \ula_|video_|Add1~12_combout = (\ula_|video_|vga_vc [6] & (\ula_|video_|Add1~11 $ (GND))) # (!\ula_|video_|vga_vc [6] & (!\ula_|video_|Add1~11 & VCC))
|
|
// \ula_|video_|Add1~13 = CARRY((\ula_|video_|vga_vc [6] & !\ula_|video_|Add1~11 ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|video_|vga_vc [6]),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\ula_|video_|Add1~11 ),
|
|
.combout(\ula_|video_|Add1~12_combout ),
|
|
.cout(\ula_|video_|Add1~13 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Add1~12 .lut_mask = 16'hC30C;
|
|
defparam \ula_|video_|Add1~12 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y32_N0
|
|
cycloneive_lcell_comb \ula_|video_|vga_vc[6]~4 (
|
|
// Equation(s):
|
|
// \ula_|video_|vga_vc[6]~4_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [6]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~12_combout ))))
|
|
|
|
.dataa(\ula_|video_|Equal3~1_combout ),
|
|
.datab(\ula_|video_|Add1~12_combout ),
|
|
.datac(\ula_|video_|vga_vc [6]),
|
|
.datad(\ula_|video_|Equal1~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|vga_vc[6]~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vga_vc[6]~4 .lut_mask = 16'h5044;
|
|
defparam \ula_|video_|vga_vc[6]~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y32_N1
|
|
dffeas \ula_|video_|vga_vc[6] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|vga_vc[6]~4_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|vga_vc [6]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vga_vc[6] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|vga_vc[6] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y31_N16
|
|
cycloneive_lcell_comb \ula_|video_|Add1~14 (
|
|
// Equation(s):
|
|
// \ula_|video_|Add1~14_combout = (\ula_|video_|vga_vc [7] & (!\ula_|video_|Add1~13 )) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|Add1~13 ) # (GND)))
|
|
// \ula_|video_|Add1~15 = CARRY((!\ula_|video_|Add1~13 ) # (!\ula_|video_|vga_vc [7]))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|video_|vga_vc [7]),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\ula_|video_|Add1~13 ),
|
|
.combout(\ula_|video_|Add1~14_combout ),
|
|
.cout(\ula_|video_|Add1~15 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Add1~14 .lut_mask = 16'h3C3F;
|
|
defparam \ula_|video_|Add1~14 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y32_N8
|
|
cycloneive_lcell_comb \ula_|video_|vga_vc[7]~6 (
|
|
// Equation(s):
|
|
// \ula_|video_|vga_vc[7]~6_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [7]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~14_combout ))))
|
|
|
|
.dataa(\ula_|video_|Equal3~1_combout ),
|
|
.datab(\ula_|video_|Add1~14_combout ),
|
|
.datac(\ula_|video_|vga_vc [7]),
|
|
.datad(\ula_|video_|Equal1~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|vga_vc[7]~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vga_vc[7]~6 .lut_mask = 16'h5044;
|
|
defparam \ula_|video_|vga_vc[7]~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y32_N9
|
|
dffeas \ula_|video_|vga_vc[7] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|vga_vc[7]~6_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|vga_vc [7]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vga_vc[7] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|vga_vc[7] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y31_N18
|
|
cycloneive_lcell_comb \ula_|video_|Add1~16 (
|
|
// Equation(s):
|
|
// \ula_|video_|Add1~16_combout = (\ula_|video_|vga_vc [8] & (\ula_|video_|Add1~15 $ (GND))) # (!\ula_|video_|vga_vc [8] & (!\ula_|video_|Add1~15 & VCC))
|
|
// \ula_|video_|Add1~17 = CARRY((\ula_|video_|vga_vc [8] & !\ula_|video_|Add1~15 ))
|
|
|
|
.dataa(\ula_|video_|vga_vc [8]),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\ula_|video_|Add1~15 ),
|
|
.combout(\ula_|video_|Add1~16_combout ),
|
|
.cout(\ula_|video_|Add1~17 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Add1~16 .lut_mask = 16'hA50A;
|
|
defparam \ula_|video_|Add1~16 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y32_N0
|
|
cycloneive_lcell_comb \ula_|video_|vga_vc[8]~7 (
|
|
// Equation(s):
|
|
// \ula_|video_|vga_vc[8]~7_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [8]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~16_combout ))))
|
|
|
|
.dataa(\ula_|video_|Equal1~0_combout ),
|
|
.datab(\ula_|video_|Add1~16_combout ),
|
|
.datac(\ula_|video_|vga_vc [8]),
|
|
.datad(\ula_|video_|Equal3~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|vga_vc[8]~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vga_vc[8]~7 .lut_mask = 16'h00E4;
|
|
defparam \ula_|video_|vga_vc[8]~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X36_Y32_N1
|
|
dffeas \ula_|video_|vga_vc[8] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|vga_vc[8]~7_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|vga_vc [8]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vga_vc[8] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|vga_vc[8] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y31_N20
|
|
cycloneive_lcell_comb \ula_|video_|Add1~18 (
|
|
// Equation(s):
|
|
// \ula_|video_|Add1~18_combout = \ula_|video_|Add1~17 $ (\ula_|video_|vga_vc [9])
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\ula_|video_|vga_vc [9]),
|
|
.cin(\ula_|video_|Add1~17 ),
|
|
.combout(\ula_|video_|Add1~18_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Add1~18 .lut_mask = 16'h0FF0;
|
|
defparam \ula_|video_|Add1~18 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y32_N28
|
|
cycloneive_lcell_comb \ula_|video_|vga_vc[9]~9 (
|
|
// Equation(s):
|
|
// \ula_|video_|vga_vc[9]~9_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [9]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~18_combout ))))
|
|
|
|
.dataa(\ula_|video_|Add1~18_combout ),
|
|
.datab(\ula_|video_|Equal1~0_combout ),
|
|
.datac(\ula_|video_|vga_vc [9]),
|
|
.datad(\ula_|video_|Equal3~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|vga_vc[9]~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vga_vc[9]~9 .lut_mask = 16'h00E2;
|
|
defparam \ula_|video_|vga_vc[9]~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y32_N29
|
|
dffeas \ula_|video_|vga_vc[9] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|vga_vc[9]~9_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|vga_vc [9]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vga_vc[9] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|vga_vc[9] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y30_N0
|
|
cycloneive_lcell_comb \ula_|video_|Equal3~0 (
|
|
// Equation(s):
|
|
// \ula_|video_|Equal3~0_combout = (\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [3] & (\ula_|video_|vga_vc [2] & !\ula_|video_|vga_vc [1])))
|
|
|
|
.dataa(\ula_|video_|vga_vc [0]),
|
|
.datab(\ula_|video_|vga_vc [3]),
|
|
.datac(\ula_|video_|vga_vc [2]),
|
|
.datad(\ula_|video_|vga_vc [1]),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|Equal3~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Equal3~0 .lut_mask = 16'h0080;
|
|
defparam \ula_|video_|Equal3~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y32_N2
|
|
cycloneive_lcell_comb \ula_|video_|Equal2~0 (
|
|
// Equation(s):
|
|
// \ula_|video_|Equal2~0_combout = (!\ula_|video_|vga_vc [6] & (!\ula_|video_|vga_vc [8] & (!\ula_|video_|vga_vc [4] & !\ula_|video_|vga_vc [7])))
|
|
|
|
.dataa(\ula_|video_|vga_vc [6]),
|
|
.datab(\ula_|video_|vga_vc [8]),
|
|
.datac(\ula_|video_|vga_vc [4]),
|
|
.datad(\ula_|video_|vga_vc [7]),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|Equal2~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Equal2~0 .lut_mask = 16'h0001;
|
|
defparam \ula_|video_|Equal2~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y32_N10
|
|
cycloneive_lcell_comb \ula_|video_|Equal3~1 (
|
|
// Equation(s):
|
|
// \ula_|video_|Equal3~1_combout = (!\ula_|video_|vga_vc [5] & (\ula_|video_|vga_vc [9] & (\ula_|video_|Equal3~0_combout & \ula_|video_|Equal2~0_combout )))
|
|
|
|
.dataa(\ula_|video_|vga_vc [5]),
|
|
.datab(\ula_|video_|vga_vc [9]),
|
|
.datac(\ula_|video_|Equal3~0_combout ),
|
|
.datad(\ula_|video_|Equal2~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|Equal3~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Equal3~1 .lut_mask = 16'h4000;
|
|
defparam \ula_|video_|Equal3~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y32_N30
|
|
cycloneive_lcell_comb \ula_|video_|vga_vc[5]~8 (
|
|
// Equation(s):
|
|
// \ula_|video_|vga_vc[5]~8_combout = (!\ula_|video_|Equal3~1_combout & ((\ula_|video_|Equal1~0_combout & ((\ula_|video_|vga_vc [5]))) # (!\ula_|video_|Equal1~0_combout & (\ula_|video_|Add1~10_combout ))))
|
|
|
|
.dataa(\ula_|video_|Equal3~1_combout ),
|
|
.datab(\ula_|video_|Add1~10_combout ),
|
|
.datac(\ula_|video_|vga_vc [5]),
|
|
.datad(\ula_|video_|Equal1~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|vga_vc[5]~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vga_vc[5]~8 .lut_mask = 16'h5044;
|
|
defparam \ula_|video_|vga_vc[5]~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y32_N31
|
|
dffeas \ula_|video_|vga_vc[5] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|vga_vc[5]~8_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|vga_vc [5]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vga_vc[5] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|vga_vc[5] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y31_N26
|
|
cycloneive_lcell_comb \ula_|video_|Equal2~1 (
|
|
// Equation(s):
|
|
// \ula_|video_|Equal2~1_combout = (!\ula_|video_|vga_vc [2] & (!\ula_|video_|vga_vc [9] & (!\ula_|video_|vga_vc [3] & !\ula_|video_|vga_vc [0])))
|
|
|
|
.dataa(\ula_|video_|vga_vc [2]),
|
|
.datab(\ula_|video_|vga_vc [9]),
|
|
.datac(\ula_|video_|vga_vc [3]),
|
|
.datad(\ula_|video_|vga_vc [0]),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|Equal2~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Equal2~1 .lut_mask = 16'h0001;
|
|
defparam \ula_|video_|Equal2~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y32_N24
|
|
cycloneive_lcell_comb \ula_|video_|Equal2~2 (
|
|
// Equation(s):
|
|
// \ula_|video_|Equal2~2_combout = (!\ula_|video_|vga_vc [5] & (\ula_|video_|Equal2~1_combout & \ula_|video_|Equal2~0_combout ))
|
|
|
|
.dataa(\ula_|video_|vga_vc [5]),
|
|
.datab(\ula_|video_|Equal2~1_combout ),
|
|
.datac(gnd),
|
|
.datad(\ula_|video_|Equal2~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|Equal2~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Equal2~2 .lut_mask = 16'h4400;
|
|
defparam \ula_|video_|Equal2~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOIBUF_X27_Y0_N15
|
|
cycloneive_io_ibuf \SW[1]~input (
|
|
.i(SW[1]),
|
|
.ibar(gnd),
|
|
.o(\SW[1]~input_o ));
|
|
// synopsys translate_off
|
|
defparam \SW[1]~input .bus_hold = "false";
|
|
defparam \SW[1]~input .simulate_z_as = "z";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y33_N2
|
|
cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 (
|
|
// Equation(s):
|
|
// \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout = (!\ula_|video_|vga_vc [1] & (!\ula_|video_|vga_hc [8] & (!\ula_|video_|vga_hc [9] & !\SW[1]~input_o )))
|
|
|
|
.dataa(\ula_|video_|vga_vc [1]),
|
|
.datab(\ula_|video_|vga_hc [8]),
|
|
.datac(\ula_|video_|vga_hc [9]),
|
|
.datad(\SW[1]~input_o ),
|
|
.cin(gnd),
|
|
.combout(\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 .lut_mask = 16'h0001;
|
|
defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y33_N20
|
|
cycloneive_lcell_comb \z80_|interrupts_|SYNTHESIZED_WIRE_13 (
|
|
// Equation(s):
|
|
// \z80_|interrupts_|SYNTHESIZED_WIRE_13~combout = (\z80_|interrupts_|iff1~q & (\ula_|video_|Equal2~2_combout & (!\ula_|video_|vga_hc [7] & \z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout )))
|
|
|
|
.dataa(\z80_|interrupts_|iff1~q ),
|
|
.datab(\ula_|video_|Equal2~2_combout ),
|
|
.datac(\ula_|video_|vga_hc [7]),
|
|
.datad(\z80_|interrupts_|SYNTHESIZED_WIRE_13~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h0800;
|
|
defparam \z80_|interrupts_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y33_N21
|
|
dffeas \z80_|interrupts_|int_armed (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|interrupts_|SYNTHESIZED_WIRE_13~combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\z80_|interrupts_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|interrupts_|int_armed~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|interrupts_|int_armed .is_wysiwyg = "true";
|
|
defparam \z80_|interrupts_|int_armed .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y13_N30
|
|
cycloneive_lcell_comb \z80_|interrupts_|DFFE_inst44~feeder (
|
|
// Equation(s):
|
|
// \z80_|interrupts_|DFFE_inst44~feeder_combout = \z80_|interrupts_|int_armed~q
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|interrupts_|int_armed~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|interrupts_|DFFE_inst44~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|interrupts_|DFFE_inst44~feeder .lut_mask = 16'hFF00;
|
|
defparam \z80_|interrupts_|DFFE_inst44~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X28_Y13_N31
|
|
dffeas \z80_|interrupts_|DFFE_inst44 (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|interrupts_|DFFE_inst44~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|interrupts_|test1~3_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|interrupts_|DFFE_inst44~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|interrupts_|DFFE_inst44 .is_wysiwyg = "true";
|
|
defparam \z80_|interrupts_|DFFE_inst44 .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y13_N4
|
|
cycloneive_lcell_comb \z80_|decode_state_|in_halt~0 (
|
|
// Equation(s):
|
|
// \z80_|decode_state_|in_halt~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|interrupts_|DFFE_inst44~q & \z80_|decode_state_|in_halt~q ))
|
|
|
|
.dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ),
|
|
.datab(gnd),
|
|
.datac(\z80_|interrupts_|DFFE_inst44~q ),
|
|
.datad(\z80_|decode_state_|in_halt~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|decode_state_|in_halt~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|decode_state_|in_halt~0 .lut_mask = 16'h0500;
|
|
defparam \z80_|decode_state_|in_halt~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y16_N24
|
|
cycloneive_lcell_comb \z80_|decode_state_|in_halt~1 (
|
|
// Equation(s):
|
|
// \z80_|decode_state_|in_halt~1_combout = (\z80_|decode_state_|in_halt~0_combout ) # ((\z80_|pla_decode_|Equal77~1_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & !\z80_|decode_state_|in_halt~q )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal77~1_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ),
|
|
.datac(\z80_|decode_state_|in_halt~q ),
|
|
.datad(\z80_|decode_state_|in_halt~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|decode_state_|in_halt~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|decode_state_|in_halt~1 .lut_mask = 16'hFF08;
|
|
defparam \z80_|decode_state_|in_halt~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X28_Y16_N25
|
|
dffeas \z80_|decode_state_|in_halt (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|decode_state_|in_halt~1_combout ),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|decode_state_|in_halt~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|decode_state_|in_halt .is_wysiwyg = "true";
|
|
defparam \z80_|decode_state_|in_halt .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y16_N8
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal50~0 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal50~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal33~1_combout & \z80_|pla_decode_|Equal77~0_combout ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|decode_state_|in_halt~q ),
|
|
.datac(\z80_|pla_decode_|Equal33~1_combout ),
|
|
.datad(\z80_|pla_decode_|Equal77~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal50~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal50~0 .lut_mask = 16'h3000;
|
|
defparam \z80_|pla_decode_|Equal50~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y16_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ixy_d~17 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ixy_d~17_combout = (\z80_|decode_state_|DFFE_instIY1~q & (((!\z80_|pla_decode_|Equal33~2_combout & !\z80_|pla_decode_|Equal50~0_combout )))) # (!\z80_|decode_state_|DFFE_instIY1~q & (((!\z80_|pla_decode_|Equal33~2_combout &
|
|
// !\z80_|pla_decode_|Equal50~0_combout )) # (!\z80_|decode_state_|DFFE_inst4~q )))
|
|
|
|
.dataa(\z80_|decode_state_|DFFE_instIY1~q ),
|
|
.datab(\z80_|decode_state_|DFFE_inst4~q ),
|
|
.datac(\z80_|pla_decode_|Equal33~2_combout ),
|
|
.datad(\z80_|pla_decode_|Equal50~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ixy_d~17_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ixy_d~17 .lut_mask = 16'h111F;
|
|
defparam \z80_|execute_|ixy_d~17 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y16_N0
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal44~0 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal44~0_combout = (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|decode_state_|DFFE_instED~q & (\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6])))
|
|
|
|
.dataa(\z80_|decode_state_|DFFE_instCB~q ),
|
|
.datab(\z80_|decode_state_|DFFE_instED~q ),
|
|
.datac(\z80_|ir_|opcode [7]),
|
|
.datad(\z80_|ir_|opcode [6]),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal44~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal44~0 .lut_mask = 16'h0010;
|
|
defparam \z80_|pla_decode_|Equal44~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y16_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ixy_d~16 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ixy_d~16_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal44~0_combout & ((\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q ))))
|
|
|
|
.dataa(\z80_|decode_state_|DFFE_instIY1~q ),
|
|
.datab(\z80_|decode_state_|DFFE_inst4~q ),
|
|
.datac(\z80_|pla_decode_|Equal33~0_combout ),
|
|
.datad(\z80_|pla_decode_|Equal44~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ixy_d~16_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ixy_d~16 .lut_mask = 16'hE000;
|
|
defparam \z80_|execute_|ixy_d~16 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y13_N24
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal3~1 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal3~1_combout = (\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1])
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|ir_|opcode [2]),
|
|
.datad(\z80_|ir_|opcode [1]),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal3~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal3~1 .lut_mask = 16'h00F0;
|
|
defparam \z80_|pla_decode_|Equal3~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y15_N26
|
|
cycloneive_lcell_comb \z80_|execute_|ixy_d~10 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ixy_d~10_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal33~1_combout ),
|
|
.datab(\z80_|pla_decode_|Equal3~1_combout ),
|
|
.datac(\z80_|decode_state_|use_ixiy~combout ),
|
|
.datad(\z80_|pla_decode_|Equal6~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ixy_d~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ixy_d~10 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|ixy_d~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y15_N2
|
|
cycloneive_lcell_comb \z80_|execute_|ixy_d~13 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ixy_d~13_combout = (\z80_|execute_|ixy_d~16_combout ) # ((\z80_|execute_|ixy_d~10_combout ) # (\z80_|pla_decode_|Equal41~2_combout ))
|
|
|
|
.dataa(\z80_|execute_|ixy_d~16_combout ),
|
|
.datab(\z80_|execute_|ixy_d~10_combout ),
|
|
.datac(\z80_|pla_decode_|Equal41~2_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ixy_d~13_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ixy_d~13 .lut_mask = 16'hFEFE;
|
|
defparam \z80_|execute_|ixy_d~13 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y15_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ixy_d~14 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ixy_d~14_combout = (\z80_|execute_|ixy_d~12_combout & (((\z80_|execute_|ixy_d~17_combout & !\z80_|execute_|ixy_d~13_combout )) # (!\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|execute_|ixy_d~12_combout &
|
|
// (((\z80_|execute_|ixy_d~17_combout & !\z80_|execute_|ixy_d~13_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ixy_d~12_combout ),
|
|
.datab(\z80_|execute_|ixy_d~5_combout ),
|
|
.datac(\z80_|execute_|ixy_d~17_combout ),
|
|
.datad(\z80_|execute_|ixy_d~13_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ixy_d~14_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ixy_d~14 .lut_mask = 16'h22F2;
|
|
defparam \z80_|execute_|ixy_d~14 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y16_N10
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal49~0 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal49~0_combout = (!\z80_|decode_state_|in_halt~q & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal77~0_combout ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|decode_state_|in_halt~q ),
|
|
.datac(\z80_|pla_decode_|Equal33~0_combout ),
|
|
.datad(\z80_|pla_decode_|Equal77~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal49~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal49~0 .lut_mask = 16'h3000;
|
|
defparam \z80_|pla_decode_|Equal49~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y15_N6
|
|
cycloneive_lcell_comb \z80_|execute_|ixy_d~15 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ixy_d~15_combout = ((\z80_|decode_state_|use_ixiy~combout & (\z80_|execute_|ixy_d~11_combout & \z80_|pla_decode_|Equal49~0_combout ))) # (!\z80_|execute_|ixy_d~14_combout )
|
|
|
|
.dataa(\z80_|decode_state_|use_ixiy~combout ),
|
|
.datab(\z80_|execute_|ixy_d~11_combout ),
|
|
.datac(\z80_|execute_|ixy_d~14_combout ),
|
|
.datad(\z80_|pla_decode_|Equal49~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ixy_d~15_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ixy_d~15 .lut_mask = 16'h8F0F;
|
|
defparam \z80_|execute_|ixy_d~15 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y18_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout = (\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T5_ff~q )
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|execute_|ixy_d~15_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_T5_ff~q ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .lut_mask = 16'hC0C0;
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y16_N28
|
|
cycloneive_lcell_comb \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 (
|
|
// Equation(s):
|
|
// \z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (((!\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (!\z80_|ir_|opcode [5] &
|
|
// ((\z80_|pla_decode_|Equal3~2_combout ))))
|
|
|
|
.dataa(\z80_|ir_|opcode [5]),
|
|
.datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ),
|
|
.datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ),
|
|
.datad(\z80_|pla_decode_|Equal3~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h3530;
|
|
defparam \z80_|decode_state_|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X26_Y16_N29
|
|
dffeas \z80_|decode_state_|DFFE_inst4 (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|decode_state_|SYNTHESIZED_WIRE_0~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|execute_|ctl_state_ixiy_we~2_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|decode_state_|DFFE_inst4~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|decode_state_|DFFE_inst4 .is_wysiwyg = "true";
|
|
defparam \z80_|decode_state_|DFFE_inst4 .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y16_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~5 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_ir_we~5_combout = (\z80_|decode_state_|DFFE_instCB~q & (!\z80_|decode_state_|DFFE_inst4~q & !\z80_|decode_state_|DFFE_instIY1~q ))
|
|
|
|
.dataa(\z80_|decode_state_|DFFE_instCB~q ),
|
|
.datab(\z80_|decode_state_|DFFE_inst4~q ),
|
|
.datac(gnd),
|
|
.datad(\z80_|decode_state_|DFFE_instIY1~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_ir_we~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_ir_we~5 .lut_mask = 16'h0022;
|
|
defparam \z80_|execute_|ctl_ir_we~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y17_N18
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~13 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_ir_we~13_combout = ((\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|execute_|ctl_ir_we~5_combout )))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )
|
|
|
|
.dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ),
|
|
.datab(\z80_|pla_decode_|Equal41~2_combout ),
|
|
.datac(\z80_|execute_|ctl_ir_we~4_combout ),
|
|
.datad(\z80_|execute_|ctl_ir_we~5_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_ir_we~13_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_ir_we~13 .lut_mask = 16'hF5D5;
|
|
defparam \z80_|execute_|ctl_ir_we~13 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X30_Y17_N31
|
|
dffeas \z80_|ir_|opcode[3] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|bus_control_|db[3]~21_combout ),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|execute_|ctl_ir_we~13_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|ir_|opcode [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|ir_|opcode[3] .is_wysiwyg = "true";
|
|
defparam \z80_|ir_|opcode[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y16_N26
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal8~0 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal8~0_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0]))
|
|
|
|
.dataa(\z80_|ir_|opcode [2]),
|
|
.datab(gnd),
|
|
.datac(\z80_|ir_|opcode [1]),
|
|
.datad(\z80_|ir_|opcode [0]),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal8~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal8~0 .lut_mask = 16'h5000;
|
|
defparam \z80_|pla_decode_|Equal8~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y17_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_mRead~6 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mRead~6_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal8~0_combout & \z80_|pla_decode_|Equal13~0_combout ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|ir_|opcode [3]),
|
|
.datac(\z80_|pla_decode_|Equal8~0_combout ),
|
|
.datad(\z80_|pla_decode_|Equal13~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mRead~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mRead~6 .lut_mask = 16'h3000;
|
|
defparam \z80_|execute_|ctl_mRead~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y19_N10
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal9~0 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal9~0_combout = (!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3])
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|ir_|opcode [4]),
|
|
.datac(gnd),
|
|
.datad(\z80_|ir_|opcode [3]),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal9~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal9~0 .lut_mask = 16'h0033;
|
|
defparam \z80_|pla_decode_|Equal9~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y17_N6
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal9~1 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal9~1_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal9~0_combout )))
|
|
|
|
.dataa(\z80_|ir_|opcode [5]),
|
|
.datab(\z80_|pla_decode_|Equal2~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal1~7_combout ),
|
|
.datad(\z80_|pla_decode_|Equal9~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal9~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal9~1 .lut_mask = 16'h8000;
|
|
defparam \z80_|pla_decode_|Equal9~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y12_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal9~1_combout & \z80_|sequencer_|M5~q ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datac(\z80_|pla_decode_|Equal9~1_combout ),
|
|
.datad(\z80_|sequencer_|M5~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .lut_mask = 16'h3000;
|
|
defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y15_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~28 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo[0]~28_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_ir_we~4_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~8_combout ),
|
|
.datac(\z80_|execute_|ctl_mRead~6_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .lut_mask = 16'h0057;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[0]~28 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y16_N6
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal13~1 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal13~1_combout = (\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0]))
|
|
|
|
.dataa(\z80_|ir_|opcode [2]),
|
|
.datab(gnd),
|
|
.datac(\z80_|ir_|opcode [1]),
|
|
.datad(\z80_|ir_|opcode [0]),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal13~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal13~1 .lut_mask = 16'hA000;
|
|
defparam \z80_|pla_decode_|Equal13~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y17_N2
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal69~0 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal69~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|ir_|opcode [4] & \z80_|pla_decode_|Equal13~1_combout )))
|
|
|
|
.dataa(\z80_|ir_|opcode [5]),
|
|
.datab(\z80_|pla_decode_|Equal13~0_combout ),
|
|
.datac(\z80_|ir_|opcode [4]),
|
|
.datad(\z80_|pla_decode_|Equal13~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal69~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal69~0 .lut_mask = 16'h4000;
|
|
defparam \z80_|pla_decode_|Equal69~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y13_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|ir_|opcode [0])))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal1~4_combout ),
|
|
.datab(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal13~0_combout ),
|
|
.datad(\z80_|ir_|opcode [0]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y13_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~27 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op_low~27_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal6~0_combout & ((!\z80_|pla_decode_|Equal21~0_combout ) # (!\z80_|ir_|opcode [5]))))
|
|
|
|
.dataa(\z80_|ir_|opcode [5]),
|
|
.datab(\z80_|pla_decode_|Equal3~1_combout ),
|
|
.datac(\z80_|pla_decode_|Equal21~0_combout ),
|
|
.datad(\z80_|pla_decode_|Equal6~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op_low~27_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op_low~27 .lut_mask = 16'h4C00;
|
|
defparam \z80_|execute_|ctl_alu_op_low~27 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y17_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_out_lo~2_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal69~0_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout ))))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal69~0_combout ),
|
|
.datab(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op_low~27_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_out_lo~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_out_lo~2 .lut_mask = 16'hFCF8;
|
|
defparam \z80_|execute_|ctl_reg_out_lo~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y17_N10
|
|
cycloneive_lcell_comb \z80_|execute_|rsel3 (
|
|
// Equation(s):
|
|
// \z80_|execute_|rsel3~combout = \z80_|ir_|opcode [3] $ (((\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4])))
|
|
|
|
.dataa(\z80_|ir_|opcode [5]),
|
|
.datab(gnd),
|
|
.datac(\z80_|ir_|opcode [4]),
|
|
.datad(\z80_|ir_|opcode [3]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|rsel3~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|rsel3 .lut_mask = 16'h5FA0;
|
|
defparam \z80_|execute_|rsel3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y17_N24
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~12 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_ir_we~12_combout = (\z80_|execute_|ctl_ir_we~5_combout & (!\z80_|ir_|opcode [7] & (\z80_|pla_decode_|Equal33~0_combout & \z80_|ir_|opcode [6])))
|
|
|
|
.dataa(\z80_|execute_|ctl_ir_we~5_combout ),
|
|
.datab(\z80_|ir_|opcode [7]),
|
|
.datac(\z80_|pla_decode_|Equal33~0_combout ),
|
|
.datad(\z80_|ir_|opcode [6]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_ir_we~12_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_ir_we~12 .lut_mask = 16'h2000;
|
|
defparam \z80_|execute_|ctl_ir_we~12 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y15_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_ir_we~12_combout & \z80_|sequencer_|DFFE_T3_ff~q ))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_M2_ff~q ),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_ir_we~12_combout ),
|
|
.datad(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .lut_mask = 16'hA000;
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y16_N2
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal56~0 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal56~0_combout = (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal1~4_combout & \z80_|ir_|opcode [0])))
|
|
|
|
.dataa(\z80_|ir_|opcode [3]),
|
|
.datab(\z80_|pla_decode_|Equal6~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal1~4_combout ),
|
|
.datad(\z80_|ir_|opcode [0]),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal56~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal56~0 .lut_mask = 16'h8000;
|
|
defparam \z80_|pla_decode_|Equal56~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y19_N16
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~24 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op_low~24_combout = (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal13~0_combout & \z80_|ir_|opcode [3])))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal2~0_combout ),
|
|
.datab(\z80_|ir_|opcode [0]),
|
|
.datac(\z80_|pla_decode_|Equal13~0_combout ),
|
|
.datad(\z80_|ir_|opcode [3]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op_low~24_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op_low~24 .lut_mask = 16'h2000;
|
|
defparam \z80_|execute_|ctl_alu_op_low~24 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y17_N18
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~25 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op_low~25_combout = (!\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [3])))
|
|
|
|
.dataa(\z80_|ir_|opcode [0]),
|
|
.datab(\z80_|pla_decode_|Equal2~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal13~0_combout ),
|
|
.datad(\z80_|ir_|opcode [3]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op_low~25_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op_low~25 .lut_mask = 16'h0040;
|
|
defparam \z80_|execute_|ctl_alu_op_low~25 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y19_N16
|
|
cycloneive_lcell_comb \z80_|execute_|nextM~2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|nextM~2_combout = (!\z80_|pla_decode_|Equal56~0_combout & (!\z80_|execute_|ctl_alu_op_low~24_combout & !\z80_|execute_|ctl_alu_op_low~25_combout ))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal56~0_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_alu_op_low~24_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op_low~25_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|nextM~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|nextM~2 .lut_mask = 16'h0005;
|
|
defparam \z80_|execute_|nextM~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y15_N24
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~16 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op1_sel_bus~16_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T3_ff~q ))))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_M2_ff~q ),
|
|
.datab(\z80_|execute_|nextM~2_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.datad(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .lut_mask = 16'h3320;
|
|
defparam \z80_|execute_|ctl_alu_op1_sel_bus~16 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y15_N18
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~3 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_out_lo~3_combout = (\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ) # ((\z80_|execute_|ctl_reg_out_lo~2_combout & \z80_|execute_|rsel3~combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_out_lo~2_combout ),
|
|
.datab(\z80_|execute_|rsel3~combout ),
|
|
.datac(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_out_lo~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_out_lo~3 .lut_mask = 16'hFFF8;
|
|
defparam \z80_|execute_|ctl_reg_out_lo~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y13_N22
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal40~0 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal40~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1]))
|
|
|
|
.dataa(\z80_|ir_|opcode [0]),
|
|
.datab(gnd),
|
|
.datac(\z80_|ir_|opcode [2]),
|
|
.datad(\z80_|ir_|opcode [1]),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal40~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal40~0 .lut_mask = 16'h0005;
|
|
defparam \z80_|pla_decode_|Equal40~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y13_N18
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal40~1 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal40~1_combout = (\z80_|pla_decode_|Equal40~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|ir_|opcode [5]))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal40~0_combout ),
|
|
.datab(\z80_|pla_decode_|Equal6~0_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|ir_|opcode [5]),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal40~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal40~1 .lut_mask = 16'h8800;
|
|
defparam \z80_|pla_decode_|Equal40~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y16_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal1~7_combout )))
|
|
|
|
.dataa(\z80_|ir_|opcode [3]),
|
|
.datab(\z80_|pla_decode_|Equal3~1_combout ),
|
|
.datac(\z80_|execute_|ixy_d~7_combout ),
|
|
.datad(\z80_|pla_decode_|Equal1~7_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .lut_mask = 16'h4000;
|
|
defparam \z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y17_N24
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal3~0 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal3~0_combout = (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3])
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|ir_|opcode [4]),
|
|
.datac(gnd),
|
|
.datad(\z80_|ir_|opcode [3]),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal3~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal3~0 .lut_mask = 16'hCC00;
|
|
defparam \z80_|pla_decode_|Equal3~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y13_N20
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal39~0 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal39~0_combout = (\z80_|pla_decode_|Equal40~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~0_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal40~0_combout ),
|
|
.datab(\z80_|pla_decode_|Equal6~0_combout ),
|
|
.datac(\z80_|ir_|opcode [5]),
|
|
.datad(\z80_|pla_decode_|Equal3~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal39~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal39~0 .lut_mask = 16'h0800;
|
|
defparam \z80_|pla_decode_|Equal39~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y18_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_out_lo~4_combout = (\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ) # ((\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal40~1_combout ) # (\z80_|pla_decode_|Equal39~0_combout ))))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal40~1_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_sel_pla23pla16M3T1_5~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal39~0_combout ),
|
|
.datad(\z80_|execute_|ixy_d~9_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_out_lo~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_out_lo~4 .lut_mask = 16'hFECC;
|
|
defparam \z80_|execute_|ctl_reg_out_lo~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y18_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~0 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_oe~0_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|M5~q )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datad(\z80_|sequencer_|M5~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_oe~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_oe~0 .lut_mask = 16'h0F00;
|
|
defparam \z80_|execute_|ctl_alu_oe~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y12_N16
|
|
cycloneive_lcell_comb \z80_|execute_|comb~0 (
|
|
// Equation(s):
|
|
// \z80_|execute_|comb~0_combout = (\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1])
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|ir_|opcode [2]),
|
|
.datad(\z80_|ir_|opcode [1]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|comb~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|comb~0 .lut_mask = 16'hF000;
|
|
defparam \z80_|execute_|comb~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y17_N28
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal41~0 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal41~0_combout = (\z80_|ir_|opcode [6] & \z80_|ir_|opcode [7])
|
|
|
|
.dataa(\z80_|ir_|opcode [6]),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|ir_|opcode [7]),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal41~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal41~0 .lut_mask = 16'hAA00;
|
|
defparam \z80_|pla_decode_|Equal41~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y13_N30
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal47~0 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal47~0_combout = (\z80_|ir_|opcode [0] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|execute_|comb~0_combout & \z80_|pla_decode_|Equal41~0_combout )))
|
|
|
|
.dataa(\z80_|ir_|opcode [0]),
|
|
.datab(\z80_|decode_state_|table_xx~0_combout ),
|
|
.datac(\z80_|execute_|comb~0_combout ),
|
|
.datad(\z80_|pla_decode_|Equal41~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal47~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal47~0 .lut_mask = 16'h2000;
|
|
defparam \z80_|pla_decode_|Equal47~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y18_N26
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~32 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~32_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|execute_|ctl_alu_oe~0_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ixy_d~7_combout &
|
|
// (((!\z80_|execute_|ctl_alu_oe~0_combout )) # (!\z80_|pla_decode_|Equal34~0_combout )))
|
|
|
|
.dataa(\z80_|execute_|ixy_d~7_combout ),
|
|
.datab(\z80_|pla_decode_|Equal34~0_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_oe~0_combout ),
|
|
.datad(\z80_|pla_decode_|Equal47~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~32_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~32 .lut_mask = 16'h153F;
|
|
defparam \z80_|execute_|ctl_inc_cy~32 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y17_N22
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal19~0 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal19~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal32~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~1_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal1~7_combout ),
|
|
.datab(\z80_|pla_decode_|Equal32~0_combout ),
|
|
.datac(\z80_|ir_|opcode [5]),
|
|
.datad(\z80_|pla_decode_|Equal3~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal19~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal19~0 .lut_mask = 16'h0800;
|
|
defparam \z80_|pla_decode_|Equal19~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y18_N28
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~9 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_out_lo~9_combout = (\z80_|execute_|ctl_inc_cy~32_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|sequencer_|M5~q )) # (!\z80_|pla_decode_|Equal19~0_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_inc_cy~32_combout ),
|
|
.datab(\z80_|pla_decode_|Equal19~0_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datad(\z80_|sequencer_|M5~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_out_lo~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_out_lo~9 .lut_mask = 16'hA2AA;
|
|
defparam \z80_|execute_|ctl_reg_out_lo~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y15_N28
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~5 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_out_lo~5_combout = ((\z80_|execute_|ctl_reg_out_lo~3_combout ) # ((\z80_|execute_|ctl_reg_out_lo~4_combout ) # (!\z80_|execute_|ctl_reg_out_lo~9_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_out_lo~3_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_out_lo~4_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_out_lo~9_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_out_lo~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_out_lo~5 .lut_mask = 16'hFDFF;
|
|
defparam \z80_|execute_|ctl_reg_out_lo~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y13_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mWrite~4_combout = (\z80_|decode_state_|DFFE_instED~q & (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6])))
|
|
|
|
.dataa(\z80_|decode_state_|DFFE_instED~q ),
|
|
.datab(\z80_|ir_|opcode [5]),
|
|
.datac(\z80_|ir_|opcode [7]),
|
|
.datad(\z80_|ir_|opcode [6]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mWrite~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mWrite~4 .lut_mask = 16'h0080;
|
|
defparam \z80_|execute_|ctl_mWrite~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y17_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_alu_op_low~22_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal2~0_combout ),
|
|
.datab(\z80_|execute_|ctl_mWrite~4_combout ),
|
|
.datac(\z80_|ir_|opcode [0]),
|
|
.datad(\z80_|execute_|ctl_alu_op_low~22_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .lut_mask = 16'h0800;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y16_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_mRead~34 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mRead~34_combout = (\z80_|ir_|opcode [0] & (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & \z80_|execute_|ctl_mWrite~4_combout )))
|
|
|
|
.dataa(\z80_|ir_|opcode [0]),
|
|
.datab(\z80_|ir_|opcode [2]),
|
|
.datac(\z80_|ir_|opcode [1]),
|
|
.datad(\z80_|execute_|ctl_mWrite~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mRead~34_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mRead~34 .lut_mask = 16'h2000;
|
|
defparam \z80_|execute_|ctl_mRead~34 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y19_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|ixy_d~15_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|sequencer_|DFFE_T4_ff~q ),
|
|
.datad(\z80_|execute_|ixy_d~15_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .lut_mask = 16'hF000;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y17_N16
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~36 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo[1]~36_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_mRead~34_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~34_combout ),
|
|
.datac(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .lut_mask = 16'h0015;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~36 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y13_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~5 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mWrite~5_combout = (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_T4_ff~q )
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|sequencer_|DFFE_M2_ff~q ),
|
|
.datac(\z80_|sequencer_|DFFE_T4_ff~q ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mWrite~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mWrite~5 .lut_mask = 16'hC0C0;
|
|
defparam \z80_|execute_|ctl_mWrite~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y18_N6
|
|
cycloneive_lcell_comb \z80_|execute_|nextM~11 (
|
|
// Equation(s):
|
|
// \z80_|execute_|nextM~11_combout = ((!\z80_|execute_|ctl_alu_op_low~25_combout & (!\z80_|execute_|ctl_alu_op_low~24_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ctl_mWrite~5_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op_low~25_combout ),
|
|
.datab(\z80_|execute_|ctl_mWrite~5_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_op_low~24_combout ),
|
|
.datad(\z80_|pla_decode_|Equal56~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|nextM~11_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|nextM~11 .lut_mask = 16'h3337;
|
|
defparam \z80_|execute_|nextM~11 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y16_N26
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal20~0 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal20~0_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|execute_|comb~0_combout & !\z80_|ir_|opcode [5])))
|
|
|
|
.dataa(\z80_|ir_|opcode [0]),
|
|
.datab(\z80_|pla_decode_|Equal6~0_combout ),
|
|
.datac(\z80_|execute_|comb~0_combout ),
|
|
.datad(\z80_|ir_|opcode [5]),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal20~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal20~0 .lut_mask = 16'h0080;
|
|
defparam \z80_|pla_decode_|Equal20~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y17_N10
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal13~2 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal13~2_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [4] & \z80_|pla_decode_|Equal13~1_combout )))
|
|
|
|
.dataa(\z80_|ir_|opcode [5]),
|
|
.datab(\z80_|pla_decode_|Equal13~0_combout ),
|
|
.datac(\z80_|ir_|opcode [4]),
|
|
.datad(\z80_|pla_decode_|Equal13~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal13~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal13~2 .lut_mask = 16'h0800;
|
|
defparam \z80_|pla_decode_|Equal13~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y18_N28
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_mRead~24 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mRead~24_combout = (\z80_|pla_decode_|Equal13~2_combout & !\z80_|ir_|opcode [3])
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|pla_decode_|Equal13~2_combout ),
|
|
.datad(\z80_|ir_|opcode [3]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mRead~24_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mRead~24 .lut_mask = 16'h00F0;
|
|
defparam \z80_|execute_|ctl_mRead~24 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y17_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~27 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_sel[0]~27_combout = (\z80_|pla_decode_|Equal20~0_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_mRead~24_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal20~0_combout &
|
|
// (((!\z80_|execute_|ctl_mRead~24_combout ) # (!\z80_|execute_|ixy_d~6_combout ))))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal20~0_combout ),
|
|
.datab(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.datac(\z80_|execute_|ixy_d~6_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~24_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .lut_mask = 16'h0777;
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[0]~27 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y17_N20
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal48~0 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal48~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [4] & \z80_|pla_decode_|Equal13~1_combout )))
|
|
|
|
.dataa(\z80_|ir_|opcode [5]),
|
|
.datab(\z80_|pla_decode_|Equal13~0_combout ),
|
|
.datac(\z80_|ir_|opcode [4]),
|
|
.datad(\z80_|pla_decode_|Equal13~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal48~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal48~0 .lut_mask = 16'h0400;
|
|
defparam \z80_|pla_decode_|Equal48~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y16_N2
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal10~0 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal10~0_combout = (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~4_combout & (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [0])))
|
|
|
|
.dataa(\z80_|ir_|opcode [1]),
|
|
.datab(\z80_|execute_|ctl_mWrite~4_combout ),
|
|
.datac(\z80_|ir_|opcode [2]),
|
|
.datad(\z80_|ir_|opcode [0]),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal10~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal10~0 .lut_mask = 16'h0400;
|
|
defparam \z80_|pla_decode_|Equal10~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y16_N0
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal11~0 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal11~0_combout = (!\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~4_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [0])))
|
|
|
|
.dataa(\z80_|ir_|opcode [1]),
|
|
.datab(\z80_|execute_|ctl_mWrite~4_combout ),
|
|
.datac(\z80_|ir_|opcode [2]),
|
|
.datad(\z80_|ir_|opcode [0]),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal11~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal11~0 .lut_mask = 16'h0004;
|
|
defparam \z80_|pla_decode_|Equal11~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y16_N24
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal63~0 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal63~0_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|execute_|comb~0_combout & \z80_|ir_|opcode [5])))
|
|
|
|
.dataa(\z80_|ir_|opcode [0]),
|
|
.datab(\z80_|pla_decode_|Equal6~0_combout ),
|
|
.datac(\z80_|execute_|comb~0_combout ),
|
|
.datad(\z80_|ir_|opcode [5]),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal63~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal63~0 .lut_mask = 16'h8000;
|
|
defparam \z80_|pla_decode_|Equal63~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y19_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf2_we (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_hf2_we~combout = (\z80_|pla_decode_|Equal63~0_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3])))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal63~0_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ),
|
|
.datac(\z80_|ir_|opcode [4]),
|
|
.datad(\z80_|ir_|opcode [3]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_hf2_we~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_hf2_we .lut_mask = 16'h0008;
|
|
defparam \z80_|execute_|ctl_flags_hf2_we .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y19_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~41 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_shift_oe~41_combout = (!\z80_|execute_|ctl_flags_hf2_we~combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal10~0_combout ),
|
|
.datab(\z80_|pla_decode_|Equal11~0_combout ),
|
|
.datac(\z80_|execute_|ctl_flags_hf2_we~combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_shift_oe~41_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~41 .lut_mask = 16'h010F;
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~41 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y13_N2
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal68~3 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal68~3_combout = (\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [0])))
|
|
|
|
.dataa(\z80_|ir_|opcode [2]),
|
|
.datab(\z80_|ir_|opcode [1]),
|
|
.datac(\z80_|pla_decode_|Equal13~0_combout ),
|
|
.datad(\z80_|ir_|opcode [0]),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal68~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal68~3 .lut_mask = 16'h0020;
|
|
defparam \z80_|pla_decode_|Equal68~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y13_N28
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~7 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_bus~7_combout = (\z80_|execute_|ctl_alu_op_low~27_combout ) # ((\z80_|pla_decode_|Equal68~3_combout ) # ((\z80_|pla_decode_|Equal21~0_combout & \z80_|pla_decode_|Equal63~0_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op_low~27_combout ),
|
|
.datab(\z80_|pla_decode_|Equal68~3_combout ),
|
|
.datac(\z80_|pla_decode_|Equal21~0_combout ),
|
|
.datad(\z80_|pla_decode_|Equal63~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_bus~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_bus~7 .lut_mask = 16'hFEEE;
|
|
defparam \z80_|execute_|ctl_flags_bus~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y19_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~8 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_bus~8_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_alu_op_low~25_combout ) # ((\z80_|execute_|ctl_flags_bus~7_combout ) # (\z80_|pla_decode_|Equal20~0_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op_low~25_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_bus~7_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ),
|
|
.datad(\z80_|pla_decode_|Equal20~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_bus~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_bus~8 .lut_mask = 16'hF0E0;
|
|
defparam \z80_|execute_|ctl_flags_bus~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y19_N18
|
|
cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~9 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|DFFE_inst_latch_nf~9_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_alu_op_low~24_combout & !\z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op_low~24_combout ),
|
|
.datab(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.datac(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.datad(\z80_|pla_decode_|Equal56~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_nf~9 .lut_mask = 16'hCFDF;
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_nf~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y17_N18
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~6 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_ir_we~6_combout = (!\z80_|ir_|opcode [6] & !\z80_|ir_|opcode [7])
|
|
|
|
.dataa(\z80_|ir_|opcode [6]),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|ir_|opcode [7]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_ir_we~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_ir_we~6 .lut_mask = 16'h0055;
|
|
defparam \z80_|execute_|ctl_ir_we~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y17_N6
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~8 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_ir_we~8_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|execute_|ctl_ir_we~6_combout & ((!\z80_|decode_state_|DFFE_instCB~q ) # (!\z80_|pla_decode_|Equal33~0_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_ir_we~5_combout ),
|
|
.datab(\z80_|execute_|ctl_ir_we~6_combout ),
|
|
.datac(\z80_|pla_decode_|Equal33~0_combout ),
|
|
.datad(\z80_|decode_state_|DFFE_instCB~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_ir_we~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_ir_we~8 .lut_mask = 16'h0888;
|
|
defparam \z80_|execute_|ctl_ir_we~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y17_N2
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~14 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_ir_we~14_combout = (\z80_|execute_|ctl_ir_we~5_combout & (!\z80_|ir_|opcode [7] & (\z80_|pla_decode_|Equal33~0_combout & !\z80_|ir_|opcode [6])))
|
|
|
|
.dataa(\z80_|execute_|ctl_ir_we~5_combout ),
|
|
.datab(\z80_|ir_|opcode [7]),
|
|
.datac(\z80_|pla_decode_|Equal33~0_combout ),
|
|
.datad(\z80_|ir_|opcode [6]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_ir_we~14_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_ir_we~14 .lut_mask = 16'h0020;
|
|
defparam \z80_|execute_|ctl_ir_we~14 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y19_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_bus~4_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~14_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q )
|
|
|
|
.dataa(\z80_|execute_|ctl_ir_we~8_combout ),
|
|
.datab(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.datac(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.datad(\z80_|execute_|ctl_ir_we~14_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_bus~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_bus~4 .lut_mask = 16'hF3F7;
|
|
defparam \z80_|execute_|ctl_flags_bus~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y15_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~5 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_bus~5_combout = (\z80_|execute_|ixy_d~10_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & ((\z80_|pla_decode_|Equal32~0_combout ) # (\z80_|pla_decode_|Equal3~0_combout ))))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal32~0_combout ),
|
|
.datab(\z80_|pla_decode_|Equal63~0_combout ),
|
|
.datac(\z80_|execute_|ixy_d~10_combout ),
|
|
.datad(\z80_|pla_decode_|Equal3~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_bus~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_bus~5 .lut_mask = 16'hFCF8;
|
|
defparam \z80_|execute_|ctl_flags_bus~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y15_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_mRead~4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mRead~4_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal33~1_combout ),
|
|
.datab(\z80_|pla_decode_|Equal3~1_combout ),
|
|
.datac(\z80_|decode_state_|use_ixiy~combout ),
|
|
.datad(\z80_|pla_decode_|Equal6~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mRead~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mRead~4 .lut_mask = 16'h0800;
|
|
defparam \z80_|execute_|ctl_mRead~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y19_N28
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~6 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_bus~6_combout = ((!\z80_|execute_|ctl_flags_bus~5_combout & (!\z80_|pla_decode_|Equal13~2_combout & !\z80_|execute_|ctl_mRead~4_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_bus~5_combout ),
|
|
.datab(\z80_|pla_decode_|Equal13~2_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_bus~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_bus~6 .lut_mask = 16'h0F1F;
|
|
defparam \z80_|execute_|ctl_flags_bus~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y19_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~9 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_bus~9_combout = (!\z80_|execute_|ctl_flags_bus~8_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout & (\z80_|execute_|ctl_flags_bus~4_combout & \z80_|execute_|ctl_flags_bus~6_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_bus~8_combout ),
|
|
.datab(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ),
|
|
.datac(\z80_|execute_|ctl_flags_bus~4_combout ),
|
|
.datad(\z80_|execute_|ctl_flags_bus~6_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_bus~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_bus~9 .lut_mask = 16'h4000;
|
|
defparam \z80_|execute_|ctl_flags_bus~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y16_N18
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_iorw~11 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_iorw~11_combout = (!\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0])))
|
|
|
|
.dataa(\z80_|ir_|opcode [2]),
|
|
.datab(\z80_|pla_decode_|Equal13~0_combout ),
|
|
.datac(\z80_|ir_|opcode [1]),
|
|
.datad(\z80_|ir_|opcode [0]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_iorw~11_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_iorw~11 .lut_mask = 16'h0004;
|
|
defparam \z80_|execute_|ctl_iorw~11 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y16_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~17 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mWrite~17_combout = (\z80_|ir_|opcode [1] & (\z80_|execute_|ctl_mWrite~4_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [0])))
|
|
|
|
.dataa(\z80_|ir_|opcode [1]),
|
|
.datab(\z80_|execute_|ctl_mWrite~4_combout ),
|
|
.datac(\z80_|ir_|opcode [2]),
|
|
.datad(\z80_|ir_|opcode [0]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mWrite~17_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mWrite~17 .lut_mask = 16'h0008;
|
|
defparam \z80_|execute_|ctl_mWrite~17 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y14_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~18 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_shift_oe~18_combout = ((!\z80_|execute_|ctl_iorw~11_combout & (!\z80_|execute_|ctl_mWrite~17_combout & !\z80_|execute_|ctl_mRead~34_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_iorw~11_combout ),
|
|
.datab(\z80_|execute_|ctl_mWrite~17_combout ),
|
|
.datac(\z80_|execute_|ctl_mRead~34_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_shift_oe~18_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~18 .lut_mask = 16'h01FF;
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~18 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y13_N14
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal37~0 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal37~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal1~4_combout & \z80_|pla_decode_|Equal41~0_combout )))
|
|
|
|
.dataa(\z80_|ir_|opcode [0]),
|
|
.datab(\z80_|decode_state_|table_xx~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal1~4_combout ),
|
|
.datad(\z80_|pla_decode_|Equal41~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal37~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal37~0 .lut_mask = 16'h1000;
|
|
defparam \z80_|pla_decode_|Equal37~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y18_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~19 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_shift_oe~19_combout = (\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # ((\z80_|pla_decode_|Equal40~1_combout ) # (\z80_|pla_decode_|Equal34~0_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal41~2_combout ),
|
|
.datab(\z80_|pla_decode_|Equal37~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal40~1_combout ),
|
|
.datad(\z80_|pla_decode_|Equal34~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_shift_oe~19_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~19 .lut_mask = 16'hFFFE;
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~19 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y13_N0
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal35~0 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal35~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal2~0_combout & \z80_|pla_decode_|Equal41~0_combout )))
|
|
|
|
.dataa(\z80_|ir_|opcode [0]),
|
|
.datab(\z80_|decode_state_|table_xx~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal2~0_combout ),
|
|
.datad(\z80_|pla_decode_|Equal41~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal35~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal35~0 .lut_mask = 16'h1000;
|
|
defparam \z80_|pla_decode_|Equal35~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y13_N0
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal21~1 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal21~1_combout = (\z80_|pla_decode_|Equal40~0_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal21~0_combout & !\z80_|ir_|opcode [5])))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal40~0_combout ),
|
|
.datab(\z80_|pla_decode_|Equal6~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal21~0_combout ),
|
|
.datad(\z80_|ir_|opcode [5]),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal21~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal21~1 .lut_mask = 16'h0080;
|
|
defparam \z80_|pla_decode_|Equal21~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y18_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~17 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_shift_oe~17_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal21~1_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )
|
|
|
|
.dataa(\z80_|pla_decode_|Equal39~0_combout ),
|
|
.datab(\z80_|pla_decode_|Equal35~0_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ),
|
|
.datad(\z80_|pla_decode_|Equal21~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_shift_oe~17_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~17 .lut_mask = 16'h0F1F;
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~17 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y18_N28
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~20 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_shift_oe~20_combout = (\z80_|execute_|ctl_alu_shift_oe~18_combout & (\z80_|execute_|ctl_alu_shift_oe~17_combout & ((!\z80_|execute_|ctl_alu_shift_oe~19_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_shift_oe~18_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ),
|
|
.datac(\z80_|execute_|ctl_alu_shift_oe~19_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_shift_oe~17_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_shift_oe~20_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~20 .lut_mask = 16'h2A00;
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~20 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y17_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~9 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_ir_we~9_combout = (\z80_|pla_decode_|Equal41~0_combout & (\z80_|execute_|ctl_ir_we~5_combout & ((!\z80_|decode_state_|DFFE_instCB~q ) # (!\z80_|pla_decode_|Equal33~0_combout ))))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal33~0_combout ),
|
|
.datab(\z80_|pla_decode_|Equal41~0_combout ),
|
|
.datac(\z80_|execute_|ctl_ir_we~5_combout ),
|
|
.datad(\z80_|decode_state_|DFFE_instCB~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_ir_we~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_ir_we~9 .lut_mask = 16'h40C0;
|
|
defparam \z80_|execute_|ctl_ir_we~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y20_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~11 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_bs_oe~11_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q ))
|
|
|
|
.dataa(\z80_|execute_|ctl_ir_we~12_combout ),
|
|
.datab(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.datac(\z80_|execute_|ctl_ir_we~9_combout ),
|
|
.datad(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_bs_oe~11_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_bs_oe~11 .lut_mask = 16'hCDFF;
|
|
defparam \z80_|execute_|ctl_alu_bs_oe~11 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y17_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~15 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_ir_we~15_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|ir_|opcode [7] & (\z80_|pla_decode_|Equal33~0_combout & \z80_|ir_|opcode [6])))
|
|
|
|
.dataa(\z80_|execute_|ctl_ir_we~5_combout ),
|
|
.datab(\z80_|ir_|opcode [7]),
|
|
.datac(\z80_|pla_decode_|Equal33~0_combout ),
|
|
.datad(\z80_|ir_|opcode [6]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_ir_we~15_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_ir_we~15 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|ctl_ir_we~15 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y20_N28
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~7 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_bs_oe~7_combout = (\z80_|execute_|ctl_alu_bs_oe~11_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ),
|
|
.datab(\z80_|execute_|ctl_ir_we~10_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_bs_oe~11_combout ),
|
|
.datad(\z80_|execute_|ctl_ir_we~15_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_bs_oe~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_bs_oe~7 .lut_mask = 16'h5070;
|
|
defparam \z80_|execute_|ctl_alu_bs_oe~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y17_N16
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~7 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_ir_we~7_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|ir_|opcode [7] & (\z80_|pla_decode_|Equal33~0_combout & !\z80_|ir_|opcode [6])))
|
|
|
|
.dataa(\z80_|execute_|ctl_ir_we~5_combout ),
|
|
.datab(\z80_|ir_|opcode [7]),
|
|
.datac(\z80_|pla_decode_|Equal33~0_combout ),
|
|
.datad(\z80_|ir_|opcode [6]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_ir_we~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_ir_we~7 .lut_mask = 16'h0080;
|
|
defparam \z80_|execute_|ctl_ir_we~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y13_N4
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal46~0 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal46~0_combout = (\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [0] & (\z80_|decode_state_|DFFE_instCB~q & \z80_|ir_|opcode [1])))
|
|
|
|
.dataa(\z80_|ir_|opcode [2]),
|
|
.datab(\z80_|ir_|opcode [0]),
|
|
.datac(\z80_|decode_state_|DFFE_instCB~q ),
|
|
.datad(\z80_|ir_|opcode [1]),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal46~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal46~0 .lut_mask = 16'h2000;
|
|
defparam \z80_|pla_decode_|Equal46~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y17_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~11 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_ir_we~11_combout = (\z80_|ir_|opcode [6] & (!\z80_|ir_|opcode [7] & (\z80_|execute_|ctl_ir_we~5_combout & !\z80_|pla_decode_|Equal46~0_combout )))
|
|
|
|
.dataa(\z80_|ir_|opcode [6]),
|
|
.datab(\z80_|ir_|opcode [7]),
|
|
.datac(\z80_|execute_|ctl_ir_we~5_combout ),
|
|
.datad(\z80_|pla_decode_|Equal46~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_ir_we~11_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_ir_we~11 .lut_mask = 16'h0020;
|
|
defparam \z80_|execute_|ctl_ir_we~11 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y19_N28
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~3 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_bus_db_oe~3_combout = (\z80_|execute_|ctl_alu_bs_oe~7_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_bs_oe~7_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ),
|
|
.datac(\z80_|execute_|ctl_ir_we~7_combout ),
|
|
.datad(\z80_|execute_|ctl_ir_we~11_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_bus_db_oe~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_bus_db_oe~3 .lut_mask = 16'h222A;
|
|
defparam \z80_|execute_|ctl_bus_db_oe~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y16_N6
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal52~1 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal52~1_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|DFFE_instED~q & (\z80_|pla_decode_|Equal41~0_combout & !\z80_|decode_state_|DFFE_instCB~q )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal33~0_combout ),
|
|
.datab(\z80_|decode_state_|DFFE_instED~q ),
|
|
.datac(\z80_|pla_decode_|Equal41~0_combout ),
|
|
.datad(\z80_|decode_state_|DFFE_instCB~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal52~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal52~1 .lut_mask = 16'h0020;
|
|
defparam \z80_|pla_decode_|Equal52~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y16_N26
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~21 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_xy_we~21_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|pla_decode_|Equal44~0_combout & !\z80_|pla_decode_|Equal52~1_combout ))) # (!\z80_|sequencer_|DFFE_T3_ff~q )
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.datab(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.datac(\z80_|pla_decode_|Equal44~0_combout ),
|
|
.datad(\z80_|pla_decode_|Equal52~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_xy_we~21_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_xy_we~21 .lut_mask = 16'hDDDF;
|
|
defparam \z80_|execute_|ctl_flags_xy_we~21 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y19_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~13 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_xy_we~13_combout = (\z80_|execute_|ctl_flags_bus~9_combout & (\z80_|execute_|ctl_alu_shift_oe~20_combout & (\z80_|execute_|ctl_bus_db_oe~3_combout & \z80_|execute_|ctl_flags_xy_we~21_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_bus~9_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_shift_oe~20_combout ),
|
|
.datac(\z80_|execute_|ctl_bus_db_oe~3_combout ),
|
|
.datad(\z80_|execute_|ctl_flags_xy_we~21_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_xy_we~13_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_xy_we~13 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|ctl_flags_xy_we~13 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y16_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~6 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_state_alu~6_combout = (!\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal44~0_combout )))
|
|
|
|
.dataa(\z80_|decode_state_|DFFE_instIY1~q ),
|
|
.datab(\z80_|decode_state_|DFFE_inst4~q ),
|
|
.datac(\z80_|pla_decode_|Equal33~0_combout ),
|
|
.datad(\z80_|pla_decode_|Equal44~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_state_alu~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_state_alu~6 .lut_mask = 16'h1000;
|
|
defparam \z80_|execute_|ctl_state_alu~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y13_N24
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~14 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_shift_oe~14_combout = (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T2_ff~q )
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_M4_ff~q ),
|
|
.datab(gnd),
|
|
.datac(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_shift_oe~14_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~14 .lut_mask = 16'hA0A0;
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~14 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y19_N24
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~14 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_xy_we~14_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & (\z80_|execute_|ctl_flags_xy_we~13_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_shift_oe~41_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_xy_we~13_combout ),
|
|
.datac(\z80_|execute_|ctl_state_alu~6_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_xy_we~14_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_xy_we~14 .lut_mask = 16'h0888;
|
|
defparam \z80_|execute_|ctl_flags_xy_we~14 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y19_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~24 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_sel[0]~24_combout = (\z80_|execute_|ctl_flags_xy_we~14_combout & (((!\z80_|pla_decode_|Equal48~0_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal48~0_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ),
|
|
.datac(\z80_|pla_decode_|Equal69~0_combout ),
|
|
.datad(\z80_|execute_|ctl_flags_xy_we~14_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .lut_mask = 16'h3700;
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[0]~24 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y19_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~37 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo[1]~37_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout & (\z80_|execute_|nextM~11_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & \z80_|execute_|ctl_reg_gp_sel[0]~24_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ),
|
|
.datab(\z80_|execute_|nextM~11_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~37 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y13_N16
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel~7 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_sel~7_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal33~0_combout & \z80_|pla_decode_|Equal41~0_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.datab(\z80_|decode_state_|table_xx~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal33~0_combout ),
|
|
.datad(\z80_|pla_decode_|Equal41~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_sel~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_sel~7 .lut_mask = 16'h2000;
|
|
defparam \z80_|execute_|ctl_reg_gp_sel~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y14_N26
|
|
cycloneive_lcell_comb \z80_|execute_|rsel0 (
|
|
// Equation(s):
|
|
// \z80_|execute_|rsel0~combout = \z80_|ir_|opcode [0] $ (((\z80_|ir_|opcode [1] & \z80_|ir_|opcode [2])))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|ir_|opcode [1]),
|
|
.datac(\z80_|ir_|opcode [2]),
|
|
.datad(\z80_|ir_|opcode [0]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|rsel0~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|rsel0 .lut_mask = 16'h3FC0;
|
|
defparam \z80_|execute_|rsel0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y19_N16
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~3 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_state_alu~3_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M2_ff~q )
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datab(gnd),
|
|
.datac(\z80_|sequencer_|DFFE_M2_ff~q ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_state_alu~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_state_alu~3 .lut_mask = 16'h5050;
|
|
defparam \z80_|execute_|ctl_state_alu~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y18_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~0 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_use_sp~0_combout = ((!\z80_|execute_|ctl_alu_op_low~24_combout & (!\z80_|execute_|ctl_alu_op_low~25_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ctl_state_alu~3_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_state_alu~3_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_op_low~24_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_op_low~25_combout ),
|
|
.datad(\z80_|pla_decode_|Equal56~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_use_sp~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_use_sp~0 .lut_mask = 16'h5557;
|
|
defparam \z80_|execute_|ctl_reg_use_sp~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y13_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_state_alu~2_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M2_ff~q )
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.datac(gnd),
|
|
.datad(\z80_|sequencer_|DFFE_M2_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_state_alu~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_state_alu~2 .lut_mask = 16'hCC00;
|
|
defparam \z80_|execute_|ctl_state_alu~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y19_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout = (\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T2_ff~q )
|
|
|
|
.dataa(\z80_|execute_|ixy_d~15_combout ),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .lut_mask = 16'hAA00;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y18_N18
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~30 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo[0]~30_combout = (\z80_|execute_|ctl_reg_use_sp~0_combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_mRead~34_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_mRead~34_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_use_sp~0_combout ),
|
|
.datac(\z80_|execute_|ctl_state_alu~2_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .lut_mask = 16'h004C;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[0]~30 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y18_N6
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~12 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~5_combout )
|
|
|
|
.dataa(\z80_|pla_decode_|Equal39~0_combout ),
|
|
.datab(\z80_|pla_decode_|Equal21~1_combout ),
|
|
.datac(\z80_|execute_|ixy_d~5_combout ),
|
|
.datad(\z80_|pla_decode_|Equal40~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .lut_mask = 16'h0F1F;
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[0]~12 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y17_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~6 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_out_lo~6_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|pla_decode_|Equal47~0_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ),
|
|
.datab(\z80_|pla_decode_|Equal47~0_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_out_lo~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_out_lo~6 .lut_mask = 16'h20A0;
|
|
defparam \z80_|execute_|ctl_reg_out_lo~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y13_N18
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~5 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_state_alu~5_combout = (!\z80_|decode_state_|table_xx~0_combout & (!\z80_|pla_decode_|Equal33~0_combout & (\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6])))
|
|
|
|
.dataa(\z80_|decode_state_|table_xx~0_combout ),
|
|
.datab(\z80_|pla_decode_|Equal33~0_combout ),
|
|
.datac(\z80_|ir_|opcode [7]),
|
|
.datad(\z80_|ir_|opcode [6]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_state_alu~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_state_alu~5 .lut_mask = 16'h0010;
|
|
defparam \z80_|execute_|ctl_state_alu~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y17_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~1 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_sw_2u~1_combout = ((!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_state_alu~5_combout & !\z80_|execute_|ctl_ir_we~11_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_ir_we~8_combout ),
|
|
.datab(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.datac(\z80_|execute_|ctl_state_alu~5_combout ),
|
|
.datad(\z80_|execute_|ctl_ir_we~11_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_sw_2u~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_sw_2u~1 .lut_mask = 16'h3337;
|
|
defparam \z80_|execute_|ctl_sw_2u~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y16_N6
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~1 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_oe~1_combout = (\z80_|pla_decode_|Equal77~0_combout & ((\z80_|decode_state_|in_halt~q ) # ((!\z80_|pla_decode_|Equal33~0_combout & !\z80_|pla_decode_|Equal33~1_combout ))))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal33~0_combout ),
|
|
.datab(\z80_|decode_state_|in_halt~q ),
|
|
.datac(\z80_|pla_decode_|Equal33~1_combout ),
|
|
.datad(\z80_|pla_decode_|Equal77~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_oe~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_oe~1 .lut_mask = 16'hCD00;
|
|
defparam \z80_|execute_|ctl_alu_oe~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y16_N18
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~7 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mWrite~7_combout = (\z80_|pla_decode_|Equal77~0_combout & (\z80_|pla_decode_|Equal33~1_combout & (!\z80_|decode_state_|use_ixiy~combout & !\z80_|decode_state_|in_halt~q )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal77~0_combout ),
|
|
.datab(\z80_|pla_decode_|Equal33~1_combout ),
|
|
.datac(\z80_|decode_state_|use_ixiy~combout ),
|
|
.datad(\z80_|decode_state_|in_halt~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mWrite~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mWrite~7 .lut_mask = 16'h0008;
|
|
defparam \z80_|execute_|ctl_mWrite~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y14_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_sw_2u~4_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_alu_oe~1_combout & (!\z80_|execute_|ctl_mWrite~7_combout ))) # (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_ir_we~4_combout ) #
|
|
// (!\z80_|execute_|ctl_mWrite~7_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_oe~1_combout ),
|
|
.datab(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.datac(\z80_|execute_|ctl_mWrite~7_combout ),
|
|
.datad(\z80_|execute_|ctl_ir_we~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_sw_2u~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_sw_2u~4 .lut_mask = 16'h0737;
|
|
defparam \z80_|execute_|ctl_sw_2u~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y14_N28
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~57 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~57_combout = ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|sequencer_|DFFE_T4_ff~q )
|
|
|
|
.dataa(\z80_|execute_|ctl_ir_we~9_combout ),
|
|
.datab(\z80_|sequencer_|DFFE_T4_ff~q ),
|
|
.datac(\z80_|execute_|ctl_ir_we~10_combout ),
|
|
.datad(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~57_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~57 .lut_mask = 16'hFF37;
|
|
defparam \z80_|execute_|setM1~57 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y15_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~5 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_sw_2u~5_combout = (\z80_|execute_|ctl_sw_2u~1_combout & (\z80_|execute_|ctl_sw_2u~4_combout & \z80_|execute_|setM1~57_combout ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|execute_|ctl_sw_2u~1_combout ),
|
|
.datac(\z80_|execute_|ctl_sw_2u~4_combout ),
|
|
.datad(\z80_|execute_|setM1~57_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_sw_2u~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_sw_2u~5 .lut_mask = 16'hC000;
|
|
defparam \z80_|execute_|ctl_sw_2u~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y15_N26
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~7 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_out_lo~7_combout = (\z80_|execute_|ctl_reg_out_lo~6_combout & (((!\z80_|execute_|ctl_reg_gp_sel~7_combout & \z80_|execute_|ctl_sw_2u~5_combout )) # (!\z80_|execute_|rsel0~combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_sel~7_combout ),
|
|
.datab(\z80_|execute_|rsel0~combout ),
|
|
.datac(\z80_|execute_|ctl_reg_out_lo~6_combout ),
|
|
.datad(\z80_|execute_|ctl_sw_2u~5_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_out_lo~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_out_lo~7 .lut_mask = 16'h7030;
|
|
defparam \z80_|execute_|ctl_reg_out_lo~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y18_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~0 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~0_combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & !\z80_|ir_|opcode [0])))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ),
|
|
.datab(\z80_|pla_decode_|Equal2~0_combout ),
|
|
.datac(\z80_|execute_|ctl_mWrite~4_combout ),
|
|
.datad(\z80_|ir_|opcode [0]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~0 .lut_mask = 16'h0080;
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y18_N28
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~41 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_bus_inc_oe~41_combout = (\z80_|execute_|ixy_d~9_combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (((!\z80_|pla_decode_|Equal11~0_combout )) #
|
|
// (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ),
|
|
.datab(\z80_|execute_|ixy_d~9_combout ),
|
|
.datac(\z80_|pla_decode_|Equal10~0_combout ),
|
|
.datad(\z80_|pla_decode_|Equal11~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_bus_inc_oe~41_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~41 .lut_mask = 16'h113F;
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~41 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y18_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~86 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~86_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal19~0_combout )
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_M4_ff~q ),
|
|
.datab(\z80_|pla_decode_|Equal19~0_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.datad(\z80_|sequencer_|M5~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~86_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~86 .lut_mask = 16'h3F7F;
|
|
defparam \z80_|execute_|ctl_inc_cy~86 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y18_N6
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~88 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~88_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal34~0_combout )
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_M4_ff~q ),
|
|
.datab(\z80_|pla_decode_|Equal34~0_combout ),
|
|
.datac(\z80_|sequencer_|M5~q ),
|
|
.datad(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~88_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~88 .lut_mask = 16'h37FF;
|
|
defparam \z80_|execute_|ctl_inc_cy~88 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y18_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~36 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~36_combout = (\z80_|execute_|ctl_inc_cy~88_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|pla_decode_|Equal47~0_combout )))
|
|
|
|
.dataa(\z80_|execute_|ixy_d~5_combout ),
|
|
.datab(\z80_|pla_decode_|Equal47~0_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_op_low~22_combout ),
|
|
.datad(\z80_|execute_|ctl_inc_cy~88_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~36_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~36 .lut_mask = 16'h3700;
|
|
defparam \z80_|execute_|ctl_inc_cy~36 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y18_N24
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~87 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~87_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|pla_decode_|Equal9~1_combout )
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_M4_ff~q ),
|
|
.datab(\z80_|sequencer_|M5~q ),
|
|
.datac(\z80_|pla_decode_|Equal9~1_combout ),
|
|
.datad(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~87_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~87 .lut_mask = 16'h1FFF;
|
|
defparam \z80_|execute_|ctl_inc_cy~87 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y18_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~26 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_bus_inc_oe~26_combout = (\z80_|execute_|ctl_inc_cy~86_combout & (\z80_|execute_|ctl_inc_cy~36_combout & \z80_|execute_|ctl_inc_cy~87_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_inc_cy~86_combout ),
|
|
.datab(\z80_|execute_|ctl_inc_cy~36_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|execute_|ctl_inc_cy~87_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_bus_inc_oe~26_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~26 .lut_mask = 16'h8800;
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~26 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y19_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~9 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mWrite~9_combout = (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M4_ff~q )
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|sequencer_|DFFE_T4_ff~q ),
|
|
.datac(\z80_|sequencer_|DFFE_M4_ff~q ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mWrite~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mWrite~9 .lut_mask = 16'hC0C0;
|
|
defparam \z80_|execute_|ctl_mWrite~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y18_N18
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~1 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_we~1_combout = (\z80_|pla_decode_|Equal10~0_combout & (((\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (\z80_|execute_|ctl_mWrite~9_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout & (\z80_|execute_|ctl_mRead~34_combout
|
|
// & ((\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (\z80_|execute_|ctl_mWrite~9_combout ))))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal10~0_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~34_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ),
|
|
.datad(\z80_|execute_|ctl_mWrite~9_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_we~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_we~1 .lut_mask = 16'hEEE0;
|
|
defparam \z80_|execute_|ctl_reg_sys_we~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y18_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~42 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_bus_inc_oe~42_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~0_combout & (\z80_|execute_|ctl_bus_inc_oe~41_combout & (\z80_|execute_|ctl_bus_inc_oe~26_combout & !\z80_|execute_|ctl_reg_sys_we~1_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_sys_hilo_pla91pla21M4T2_3~0_combout ),
|
|
.datab(\z80_|execute_|ctl_bus_inc_oe~41_combout ),
|
|
.datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sys_we~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_bus_inc_oe~42_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~42 .lut_mask = 16'h0040;
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~42 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y16_N22
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal40~2 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal40~2_combout = (!\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0])))
|
|
|
|
.dataa(\z80_|ir_|opcode [2]),
|
|
.datab(\z80_|pla_decode_|Equal6~0_combout ),
|
|
.datac(\z80_|ir_|opcode [1]),
|
|
.datad(\z80_|ir_|opcode [0]),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal40~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal40~2 .lut_mask = 16'h0004;
|
|
defparam \z80_|pla_decode_|Equal40~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y16_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~14 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sel_pc~14_combout = (!\z80_|pla_decode_|Equal52~1_combout & (((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal40~2_combout )) # (!\z80_|pla_decode_|Equal21~0_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal52~1_combout ),
|
|
.datab(\z80_|pla_decode_|Equal21~0_combout ),
|
|
.datac(\z80_|ir_|opcode [5]),
|
|
.datad(\z80_|pla_decode_|Equal40~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sel_pc~14_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sel_pc~14 .lut_mask = 16'h5155;
|
|
defparam \z80_|execute_|ctl_reg_sel_pc~14 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y16_N28
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal55~0 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal55~0_combout = (!\z80_|ir_|opcode [2] & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0]))
|
|
|
|
.dataa(\z80_|ir_|opcode [2]),
|
|
.datab(gnd),
|
|
.datac(\z80_|ir_|opcode [1]),
|
|
.datad(\z80_|ir_|opcode [0]),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal55~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal55~0 .lut_mask = 16'h0050;
|
|
defparam \z80_|pla_decode_|Equal55~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y12_N18
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_mRead~11 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mRead~11_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|ir_|opcode [3])))
|
|
|
|
.dataa(\z80_|ir_|opcode [5]),
|
|
.datab(\z80_|pla_decode_|Equal6~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal55~0_combout ),
|
|
.datad(\z80_|ir_|opcode [3]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mRead~11_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mRead~11 .lut_mask = 16'h4000;
|
|
defparam \z80_|execute_|ctl_mRead~11 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y16_N4
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal6~1 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal6~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal1~4_combout & \z80_|ir_|opcode [0])))
|
|
|
|
.dataa(\z80_|ir_|opcode [3]),
|
|
.datab(\z80_|pla_decode_|Equal6~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal1~4_combout ),
|
|
.datad(\z80_|ir_|opcode [0]),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal6~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal6~1 .lut_mask = 16'h4000;
|
|
defparam \z80_|pla_decode_|Equal6~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y16_N0
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~36 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~36_combout = (!\z80_|pla_decode_|Equal6~1_combout & (((!\z80_|ir_|opcode [5] & !\z80_|pla_decode_|Equal3~0_combout )) # (!\z80_|pla_decode_|Equal40~2_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal6~1_combout ),
|
|
.datab(\z80_|ir_|opcode [5]),
|
|
.datac(\z80_|pla_decode_|Equal3~0_combout ),
|
|
.datad(\z80_|pla_decode_|Equal40~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~36_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~36 .lut_mask = 16'h0155;
|
|
defparam \z80_|execute_|setM1~36 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y13_N2
|
|
cycloneive_lcell_comb \z80_|execute_|comb~1 (
|
|
// Equation(s):
|
|
// \z80_|execute_|comb~1_combout = (\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4])
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|ir_|opcode [5]),
|
|
.datac(gnd),
|
|
.datad(\z80_|ir_|opcode [4]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|comb~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|comb~1 .lut_mask = 16'hCC00;
|
|
defparam \z80_|execute_|comb~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y13_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_mRead~13 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mRead~13_combout = (\z80_|execute_|comb~1_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal55~0_combout )))
|
|
|
|
.dataa(\z80_|execute_|comb~1_combout ),
|
|
.datab(\z80_|pla_decode_|Equal6~0_combout ),
|
|
.datac(\z80_|ir_|opcode [3]),
|
|
.datad(\z80_|pla_decode_|Equal55~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mRead~13_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mRead~13 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|ctl_mRead~13 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y16_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~11 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_hilo[1]~11_combout = (!\z80_|pla_decode_|Equal41~2_combout & (!\z80_|execute_|ctl_mRead~13_combout & (!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~6_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal41~2_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~13_combout ),
|
|
.datac(\z80_|execute_|ctl_mRead~8_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~6_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~11 .lut_mask = 16'h0001;
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~11 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y16_N28
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal24~0 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal24~0_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|pla_decode_|Equal2~0_combout & !\z80_|ir_|opcode [5])))
|
|
|
|
.dataa(\z80_|ir_|opcode [0]),
|
|
.datab(\z80_|pla_decode_|Equal52~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal2~0_combout ),
|
|
.datad(\z80_|ir_|opcode [5]),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal24~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal24~0 .lut_mask = 16'h0080;
|
|
defparam \z80_|pla_decode_|Equal24~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y16_N12
|
|
cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~26 (
|
|
// Equation(s):
|
|
// \z80_|execute_|pc_inc_hold~26_combout = (!\z80_|pla_decode_|Equal35~0_combout & ((\z80_|ir_|opcode [4]) # ((\z80_|ir_|opcode [3]) # (!\z80_|pla_decode_|Equal24~0_combout ))))
|
|
|
|
.dataa(\z80_|ir_|opcode [4]),
|
|
.datab(\z80_|ir_|opcode [3]),
|
|
.datac(\z80_|pla_decode_|Equal35~0_combout ),
|
|
.datad(\z80_|pla_decode_|Equal24~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|pc_inc_hold~26_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|pc_inc_hold~26 .lut_mask = 16'h0E0F;
|
|
defparam \z80_|execute_|pc_inc_hold~26 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y16_N6
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~37 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~37_combout = (!\z80_|pla_decode_|Equal19~0_combout & (\z80_|execute_|setM1~36_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~11_combout & \z80_|execute_|pc_inc_hold~26_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal19~0_combout ),
|
|
.datab(\z80_|execute_|setM1~36_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ),
|
|
.datad(\z80_|execute_|pc_inc_hold~26_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~37_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~37 .lut_mask = 16'h4000;
|
|
defparam \z80_|execute_|setM1~37 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y16_N28
|
|
cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~6 (
|
|
// Equation(s):
|
|
// \z80_|execute_|pc_inc_hold~6_combout = (!\z80_|pla_decode_|Equal33~2_combout & (((!\z80_|pla_decode_|Equal50~0_combout & !\z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|decode_state_|use_ixiy~combout )))
|
|
|
|
.dataa(\z80_|decode_state_|use_ixiy~combout ),
|
|
.datab(\z80_|pla_decode_|Equal50~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal33~2_combout ),
|
|
.datad(\z80_|pla_decode_|Equal49~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|pc_inc_hold~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|pc_inc_hold~6 .lut_mask = 16'h0507;
|
|
defparam \z80_|execute_|pc_inc_hold~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y12_N2
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~38 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_hilo~38_combout = (\z80_|execute_|pc_inc_hold~6_combout & (((!\z80_|pla_decode_|Equal33~1_combout ) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal55~0_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal55~0_combout ),
|
|
.datab(\z80_|pla_decode_|Equal6~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal33~1_combout ),
|
|
.datad(\z80_|execute_|pc_inc_hold~6_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_hilo~38_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo~38 .lut_mask = 16'h7F00;
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo~38 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y12_N26
|
|
cycloneive_lcell_comb \z80_|execute_|fMRead~7 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fMRead~7_combout = (\z80_|execute_|ctl_reg_sel_pc~14_combout & (!\z80_|execute_|ctl_mRead~11_combout & (\z80_|execute_|setM1~37_combout & \z80_|execute_|ctl_reg_sys_hilo~38_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_sel_pc~14_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~11_combout ),
|
|
.datac(\z80_|execute_|setM1~37_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sys_hilo~38_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fMRead~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fMRead~7 .lut_mask = 16'h2000;
|
|
defparam \z80_|execute_|fMRead~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y15_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_mRead~12 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mRead~12_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|pla_decode_|Equal33~1_combout ))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal33~0_combout ),
|
|
.datab(\z80_|pla_decode_|Equal6~0_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|pla_decode_|Equal33~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mRead~12_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mRead~12 .lut_mask = 16'h0088;
|
|
defparam \z80_|execute_|ctl_mRead~12 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y17_N28
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~31 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_bus_inc_oe~31_combout = (!\z80_|execute_|ctl_mRead~12_combout & ((\z80_|ir_|opcode [3]) # ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal12~0_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_mRead~12_combout ),
|
|
.datab(\z80_|ir_|opcode [3]),
|
|
.datac(\z80_|pla_decode_|Equal12~0_combout ),
|
|
.datad(\z80_|ir_|opcode [5]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_bus_inc_oe~31_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~31 .lut_mask = 16'h5545;
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~31 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y13_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal6~0_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal33~1_combout ),
|
|
.datab(\z80_|pla_decode_|Equal55~0_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ),
|
|
.datad(\z80_|pla_decode_|Equal6~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y20_N12
|
|
cycloneive_lcell_comb \z80_|nM1_int~2 (
|
|
// Equation(s):
|
|
// \z80_|nM1_int~2_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & !\z80_|sequencer_|DFFE_T1_ff~q )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.datad(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|nM1_int~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|nM1_int~2 .lut_mask = 16'h000F;
|
|
defparam \z80_|nM1_int~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y17_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~0 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_sw_4u~0_combout = (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|M5~q )
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.datac(gnd),
|
|
.datad(\z80_|sequencer_|M5~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_sw_4u~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_sw_4u~0 .lut_mask = 16'hCC00;
|
|
defparam \z80_|execute_|ctl_sw_4u~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y16_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~10 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_hilo[1]~10_combout = (\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_alu_shift_oe~14_combout & (!\z80_|execute_|ctl_sw_4u~0_combout ))) # (!\z80_|execute_|ctl_mRead~8_combout &
|
|
// (((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout )) # (!\z80_|execute_|ctl_mRead~6_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_mRead~8_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ),
|
|
.datac(\z80_|execute_|ctl_sw_4u~0_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~6_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .lut_mask = 16'h0357;
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y13_N4
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|
cycloneive_lcell_comb \z80_|execute_|fMRead~6 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fMRead~6_combout = (\z80_|execute_|ctl_mRead~13_combout & (!\z80_|execute_|ctl_alu_shift_oe~14_combout & ((!\z80_|execute_|ctl_alu_op_low~22_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) #
|
|
// (!\z80_|execute_|ctl_mRead~13_combout & (((!\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_mRead~13_combout ),
|
|
.datab(\z80_|execute_|ctl_state_alu~6_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_op_low~22_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fMRead~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fMRead~6 .lut_mask = 16'h153F;
|
|
defparam \z80_|execute_|fMRead~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y17_N26
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~12 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_dec~12_combout = (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~17_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q )
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_M4_ff~q ),
|
|
.datab(\z80_|pla_decode_|Equal11~0_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_T4_ff~q ),
|
|
.datad(\z80_|execute_|ctl_mWrite~17_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_dec~12_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_dec~12 .lut_mask = 16'h5F7F;
|
|
defparam \z80_|execute_|ctl_inc_dec~12 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y13_N26
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|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~15 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_hilo[1]~15_combout = (!\z80_|nM1_int~2_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & (\z80_|execute_|fMRead~6_combout & \z80_|execute_|ctl_inc_dec~12_combout )))
|
|
|
|
.dataa(\z80_|nM1_int~2_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ),
|
|
.datac(\z80_|execute_|fMRead~6_combout ),
|
|
.datad(\z80_|execute_|ctl_inc_dec~12_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .lut_mask = 16'h4000;
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~15 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y13_N28
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal25~0 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal25~0_combout = (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal55~0_combout )))
|
|
|
|
.dataa(\z80_|ir_|opcode [4]),
|
|
.datab(\z80_|pla_decode_|Equal6~0_combout ),
|
|
.datac(\z80_|ir_|opcode [5]),
|
|
.datad(\z80_|pla_decode_|Equal55~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal25~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal25~0 .lut_mask = 16'h4000;
|
|
defparam \z80_|pla_decode_|Equal25~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y16_N16
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal12~1 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal12~1_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal2~0_combout & !\z80_|ir_|opcode [0])))
|
|
|
|
.dataa(\z80_|ir_|opcode [3]),
|
|
.datab(\z80_|pla_decode_|Equal6~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal2~0_combout ),
|
|
.datad(\z80_|ir_|opcode [0]),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal12~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal12~1 .lut_mask = 16'h0040;
|
|
defparam \z80_|pla_decode_|Equal12~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y17_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~38 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~38_combout = ((\z80_|pla_decode_|Equal12~1_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|ctl_sw_4u~0_combout ))) # (!\z80_|pla_decode_|Equal25~0_combout )
|
|
|
|
.dataa(\z80_|pla_decode_|Equal25~0_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ),
|
|
.datac(\z80_|pla_decode_|Equal12~1_combout ),
|
|
.datad(\z80_|execute_|ctl_sw_4u~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~38_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~38 .lut_mask = 16'hF5F7;
|
|
defparam \z80_|execute_|ctl_inc_cy~38 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y15_N26
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~82 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~82_combout = ((!\z80_|sequencer_|DFFE_M2_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q )
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.datab(\z80_|pla_decode_|Equal13~2_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|sequencer_|DFFE_M2_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~82_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~82 .lut_mask = 16'h77FF;
|
|
defparam \z80_|execute_|ctl_inc_cy~82 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y13_N6
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~14 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout = (\z80_|execute_|ctl_inc_cy~38_combout & (\z80_|execute_|ctl_inc_cy~39_combout & (\z80_|execute_|ctl_reg_sel_pc~10_combout & \z80_|execute_|ctl_inc_cy~82_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_inc_cy~38_combout ),
|
|
.datab(\z80_|execute_|ctl_inc_cy~39_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_sel_pc~10_combout ),
|
|
.datad(\z80_|execute_|ctl_inc_cy~82_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~14 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y13_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~16 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_hilo[1]~16_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout &
|
|
// \z80_|execute_|ctl_reg_sys_hilo[1]~14_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ),
|
|
.datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ),
|
|
.datac(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~16 .lut_mask = 16'h1000;
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~16 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y12_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~32 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_bus_inc_oe~32_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout & (((\z80_|execute_|fMRead~7_combout & \z80_|execute_|ctl_bus_inc_oe~31_combout )) # (!\z80_|execute_|ctl_alu_op_low~22_combout )))
|
|
|
|
.dataa(\z80_|execute_|fMRead~7_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_op_low~22_combout ),
|
|
.datac(\z80_|execute_|ctl_bus_inc_oe~31_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_bus_inc_oe~32_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~32 .lut_mask = 16'hB300;
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~32 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y14_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~77 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~77_combout = (\z80_|execute_|ixy_d~5_combout & (((!\z80_|pla_decode_|Equal37~0_combout & !\z80_|pla_decode_|Equal38~2_combout )))) # (!\z80_|execute_|ixy_d~5_combout & (((!\z80_|pla_decode_|Equal37~0_combout &
|
|
// !\z80_|pla_decode_|Equal38~2_combout )) # (!\z80_|execute_|ctl_alu_op_low~22_combout )))
|
|
|
|
.dataa(\z80_|execute_|ixy_d~5_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_op_low~22_combout ),
|
|
.datac(\z80_|pla_decode_|Equal37~0_combout ),
|
|
.datad(\z80_|pla_decode_|Equal38~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~77_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~77 .lut_mask = 16'h111F;
|
|
defparam \z80_|execute_|ctl_inc_cy~77 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y17_N4
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal29~0 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal29~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal32~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal1~4_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal1~7_combout ),
|
|
.datab(\z80_|pla_decode_|Equal32~0_combout ),
|
|
.datac(\z80_|ir_|opcode [5]),
|
|
.datad(\z80_|pla_decode_|Equal1~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal29~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal29~0 .lut_mask = 16'h0800;
|
|
defparam \z80_|pla_decode_|Equal29~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y14_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~78 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~78_combout = (\z80_|execute_|ctl_inc_cy~77_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|pla_decode_|Equal29~0_combout )))
|
|
|
|
.dataa(\z80_|execute_|ixy_d~5_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_op_low~22_combout ),
|
|
.datac(\z80_|execute_|ctl_inc_cy~77_combout ),
|
|
.datad(\z80_|pla_decode_|Equal29~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~78_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~78 .lut_mask = 16'h10F0;
|
|
defparam \z80_|execute_|ctl_inc_cy~78 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y17_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~79 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~79_combout = (\z80_|execute_|ctl_inc_cy~78_combout & (((!\z80_|execute_|ctl_sw_4u~0_combout & !\z80_|execute_|ctl_alu_shift_oe~14_combout )) # (!\z80_|pla_decode_|Equal47~0_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_sw_4u~0_combout ),
|
|
.datab(\z80_|pla_decode_|Equal47~0_combout ),
|
|
.datac(\z80_|execute_|ctl_inc_cy~78_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~79_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~79 .lut_mask = 16'h3070;
|
|
defparam \z80_|execute_|ctl_inc_cy~79 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y16_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_mRead~14 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mRead~14_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal1~4_combout )))
|
|
|
|
.dataa(\z80_|ir_|opcode [3]),
|
|
.datab(\z80_|pla_decode_|Equal52~0_combout ),
|
|
.datac(\z80_|ir_|opcode [0]),
|
|
.datad(\z80_|pla_decode_|Equal1~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mRead~14_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mRead~14 .lut_mask = 16'h4000;
|
|
defparam \z80_|execute_|ctl_mRead~14 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y18_N16
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~49 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~49_combout = (\z80_|execute_|ixy_d~5_combout & (!\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_mRead~14_combout ))) # (!\z80_|execute_|ixy_d~5_combout & (((!\z80_|pla_decode_|Equal9~1_combout &
|
|
// !\z80_|execute_|ctl_mRead~14_combout )) # (!\z80_|execute_|ctl_alu_op_low~22_combout )))
|
|
|
|
.dataa(\z80_|execute_|ixy_d~5_combout ),
|
|
.datab(\z80_|pla_decode_|Equal9~1_combout ),
|
|
.datac(\z80_|execute_|ctl_mRead~14_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op_low~22_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~49_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~49 .lut_mask = 16'h0357;
|
|
defparam \z80_|execute_|ctl_inc_cy~49 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y18_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~5 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_sel[1]~5_combout = ((!\z80_|pla_decode_|Equal11~0_combout & (!\z80_|execute_|ctl_mRead~34_combout & !\z80_|pla_decode_|Equal10~0_combout ))) # (!\z80_|execute_|ctl_alu_op_low~22_combout )
|
|
|
|
.dataa(\z80_|pla_decode_|Equal11~0_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~34_combout ),
|
|
.datac(\z80_|pla_decode_|Equal10~0_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op_low~22_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .lut_mask = 16'h01FF;
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[1]~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y18_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~40 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_bus_inc_oe~40_combout = (\z80_|execute_|ctl_inc_cy~79_combout & (\z80_|execute_|ctl_inc_cy~49_combout & \z80_|execute_|ctl_reg_gp_sel[1]~5_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_inc_cy~79_combout ),
|
|
.datab(\z80_|execute_|ctl_inc_cy~49_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_bus_inc_oe~40_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~40 .lut_mask = 16'h8080;
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~40 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y15_N18
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|
cycloneive_lcell_comb \z80_|execute_|ctl_mRead~5 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mRead~5_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal33~1_combout & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal33~0_combout ),
|
|
.datab(\z80_|pla_decode_|Equal33~1_combout ),
|
|
.datac(\z80_|decode_state_|use_ixiy~combout ),
|
|
.datad(\z80_|pla_decode_|Equal6~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mRead~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mRead~5 .lut_mask = 16'h0800;
|
|
defparam \z80_|execute_|ctl_mRead~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y16_N26
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~44 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo[1]~44_combout = (\z80_|decode_state_|DFFE_inst4~q ) # ((\z80_|decode_state_|DFFE_instIY1~q ) # ((!\z80_|pla_decode_|Equal49~0_combout & !\z80_|pla_decode_|Equal50~0_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal49~0_combout ),
|
|
.datab(\z80_|decode_state_|DFFE_inst4~q ),
|
|
.datac(\z80_|pla_decode_|Equal50~0_combout ),
|
|
.datad(\z80_|decode_state_|DFFE_instIY1~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .lut_mask = 16'hFFCD;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~44 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y17_N2
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~36 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_bus_inc_oe~36_combout = (\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_mRead~5_combout ),
|
|
.datab(\z80_|execute_|ctl_ir_we~11_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_bus_inc_oe~36_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~36 .lut_mask = 16'hFFEF;
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~36 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y17_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~35 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_bus_inc_oe~35_combout = (\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mRead~8_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_state_alu~6_combout ),
|
|
.datab(\z80_|pla_decode_|Equal13~2_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|execute_|ctl_mRead~8_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_bus_inc_oe~35_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~35 .lut_mask = 16'hFFEE;
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~35 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y17_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~46 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_bus_inc_oe~46_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|execute_|ctl_bus_inc_oe~36_combout ) # (\z80_|execute_|ctl_bus_inc_oe~35_combout ))))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datab(\z80_|execute_|ctl_bus_inc_oe~36_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_M4_ff~q ),
|
|
.datad(\z80_|execute_|ctl_bus_inc_oe~35_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_bus_inc_oe~46_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~46 .lut_mask = 16'h5040;
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~46 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y11_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~33 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_bus_inc_oe~33_combout = (\z80_|execute_|pc_inc_hold~26_combout & (!\z80_|pla_decode_|Equal6~1_combout & ((!\z80_|pla_decode_|Equal33~2_combout ) # (!\z80_|decode_state_|use_ixiy~combout ))))
|
|
|
|
.dataa(\z80_|decode_state_|use_ixiy~combout ),
|
|
.datab(\z80_|execute_|pc_inc_hold~26_combout ),
|
|
.datac(\z80_|pla_decode_|Equal6~1_combout ),
|
|
.datad(\z80_|pla_decode_|Equal33~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_bus_inc_oe~33_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~33 .lut_mask = 16'h040C;
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~33 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y17_N18
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~47 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_bus_inc_oe~47_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((!\z80_|execute_|ctl_bus_inc_oe~33_combout ) # (!\z80_|execute_|nextM~2_combout ))))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.datab(\z80_|execute_|nextM~2_combout ),
|
|
.datac(\z80_|execute_|ctl_bus_inc_oe~33_combout ),
|
|
.datad(\z80_|sequencer_|DFFE_M3_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_bus_inc_oe~47_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~47 .lut_mask = 16'h2A00;
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~47 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y12_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout = (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal8~0_combout & (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal6~0_combout ),
|
|
.datab(\z80_|pla_decode_|Equal8~0_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_T5_ff~q ),
|
|
.datad(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .lut_mask = 16'h0080;
|
|
defparam \z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y18_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~45 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_bus_inc_oe~45_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|pla_decode_|Equal11~0_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal11~0_combout ),
|
|
.datab(\z80_|sequencer_|DFFE_M3_ff~q ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ),
|
|
.datad(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_bus_inc_oe~45_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~45 .lut_mask = 16'h070F;
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~45 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y17_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~34 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_bus_inc_oe~34_combout = ((\z80_|execute_|ctl_alu_oe~0_combout & ((\z80_|execute_|ctl_mRead~4_combout ) # (\z80_|execute_|ctl_mRead~8_combout )))) # (!\z80_|execute_|ctl_bus_inc_oe~45_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_bus_inc_oe~45_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~4_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_oe~0_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~8_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_bus_inc_oe~34_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~34 .lut_mask = 16'hF5D5;
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~34 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y18_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout = (\z80_|pla_decode_|Equal9~1_combout & (\z80_|sequencer_|M5~q & \z80_|sequencer_|DFFE_T4_ff~q ))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal9~1_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|sequencer_|M5~q ),
|
|
.datad(\z80_|sequencer_|DFFE_T4_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .lut_mask = 16'hA000;
|
|
defparam \z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y16_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~6 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mWrite~6_combout = (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal52~0_combout & \z80_|ir_|opcode [0])))
|
|
|
|
.dataa(\z80_|ir_|opcode [3]),
|
|
.datab(\z80_|pla_decode_|Equal3~1_combout ),
|
|
.datac(\z80_|pla_decode_|Equal52~0_combout ),
|
|
.datad(\z80_|ir_|opcode [0]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mWrite~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mWrite~6 .lut_mask = 16'h4000;
|
|
defparam \z80_|execute_|ctl_mWrite~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y12_N6
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~50 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_bus_inc_oe~50_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mWrite~6_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q )
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_M2_ff~q ),
|
|
.datab(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.datac(\z80_|sequencer_|DFFE_M3_ff~q ),
|
|
.datad(\z80_|execute_|ctl_mWrite~6_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_bus_inc_oe~50_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~50 .lut_mask = 16'h37FF;
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~50 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y13_N12
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal4~0 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal4~0_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|ir_|opcode [3] & \z80_|execute_|comb~1_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal1~4_combout ),
|
|
.datab(\z80_|pla_decode_|Equal1~7_combout ),
|
|
.datac(\z80_|ir_|opcode [3]),
|
|
.datad(\z80_|execute_|comb~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal4~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal4~0 .lut_mask = 16'h8000;
|
|
defparam \z80_|pla_decode_|Equal4~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y12_N26
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~48 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_bus_inc_oe~48_combout = (\z80_|execute_|ctl_bus_inc_oe~50_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal4~0_combout )) # (!\z80_|sequencer_|DFFE_T5_ff~q )))
|
|
|
|
.dataa(\z80_|execute_|ctl_bus_inc_oe~50_combout ),
|
|
.datab(\z80_|sequencer_|DFFE_T5_ff~q ),
|
|
.datac(\z80_|pla_decode_|Equal4~0_combout ),
|
|
.datad(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_bus_inc_oe~48_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~48 .lut_mask = 16'hAA2A;
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~48 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y14_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~49 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_bus_inc_oe~49_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q ))) # (!\z80_|execute_|ctl_mRead~6_combout )
|
|
|
|
.dataa(\z80_|sequencer_|M5~q ),
|
|
.datab(\z80_|execute_|ctl_mRead~6_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_M4_ff~q ),
|
|
.datad(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_bus_inc_oe~49_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~49 .lut_mask = 16'hFF37;
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~49 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y13_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_mRead~7 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mRead~7_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal6~0_combout ))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal33~1_combout ),
|
|
.datab(\z80_|pla_decode_|Equal55~0_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|pla_decode_|Equal6~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mRead~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mRead~7 .lut_mask = 16'h8800;
|
|
defparam \z80_|execute_|ctl_mRead~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y15_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~29 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_bus_inc_oe~29_combout = (\z80_|execute_|ixy_d~5_combout & (!\z80_|execute_|ctl_mWrite~17_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|execute_|ctl_mRead~7_combout )))) # (!\z80_|execute_|ixy_d~5_combout &
|
|
// (((!\z80_|execute_|ctl_ir_we~4_combout )) # (!\z80_|execute_|ctl_mRead~7_combout )))
|
|
|
|
.dataa(\z80_|execute_|ixy_d~5_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~7_combout ),
|
|
.datac(\z80_|execute_|ctl_mWrite~17_combout ),
|
|
.datad(\z80_|execute_|ctl_ir_we~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_bus_inc_oe~29_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~29 .lut_mask = 16'h135F;
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~29 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y17_N26
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~11 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_core_S~11_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|M5~q ))
|
|
|
|
.dataa(\z80_|execute_|ctl_ir_we~9_combout ),
|
|
.datab(\z80_|execute_|ctl_ir_we~15_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datad(\z80_|sequencer_|M5~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_core_S~11_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_core_S~11 .lut_mask = 16'hF1FF;
|
|
defparam \z80_|execute_|ctl_alu_core_S~11 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y17_N24
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~27 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_bus_inc_oe~27_combout = (\z80_|execute_|ctl_alu_oe~0_combout & (!\z80_|execute_|ctl_ir_we~14_combout & ((!\z80_|execute_|ctl_ir_we~8_combout )))) # (!\z80_|execute_|ctl_alu_oe~0_combout & (((!\z80_|execute_|ixy_d~7_combout )) #
|
|
// (!\z80_|execute_|ctl_ir_we~14_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_oe~0_combout ),
|
|
.datab(\z80_|execute_|ctl_ir_we~14_combout ),
|
|
.datac(\z80_|execute_|ixy_d~7_combout ),
|
|
.datad(\z80_|execute_|ctl_ir_we~8_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_bus_inc_oe~27_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~27 .lut_mask = 16'h1537;
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~27 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y19_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~44 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_bus_inc_oe~44_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|sequencer_|M5~q ))
|
|
|
|
.dataa(\z80_|execute_|ctl_ir_we~10_combout ),
|
|
.datab(\z80_|execute_|ctl_ir_we~7_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datad(\z80_|sequencer_|M5~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_bus_inc_oe~44_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~44 .lut_mask = 16'hF1FF;
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~44 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y17_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~28 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_bus_inc_oe~28_combout = (\z80_|execute_|ctl_alu_core_S~11_combout & (\z80_|execute_|ctl_bus_inc_oe~27_combout & \z80_|execute_|ctl_bus_inc_oe~44_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_core_S~11_combout ),
|
|
.datab(\z80_|execute_|ctl_bus_inc_oe~27_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|execute_|ctl_bus_inc_oe~44_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_bus_inc_oe~28_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~28 .lut_mask = 16'h8800;
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~28 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y16_N24
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~30 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_bus_inc_oe~30_combout = (\z80_|execute_|ctl_bus_inc_oe~49_combout & (\z80_|execute_|ctl_bus_inc_oe~29_combout & \z80_|execute_|ctl_bus_inc_oe~28_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_bus_inc_oe~49_combout ),
|
|
.datab(\z80_|execute_|ctl_bus_inc_oe~29_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|execute_|ctl_bus_inc_oe~28_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_bus_inc_oe~30_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~30 .lut_mask = 16'h8800;
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~30 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y17_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_mRead~3 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mRead~3_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal2~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal21~0_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal1~7_combout ),
|
|
.datab(\z80_|pla_decode_|Equal2~0_combout ),
|
|
.datac(\z80_|ir_|opcode [5]),
|
|
.datad(\z80_|pla_decode_|Equal21~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mRead~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mRead~3 .lut_mask = 16'h0800;
|
|
defparam \z80_|execute_|ctl_mRead~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y17_N22
|
|
cycloneive_lcell_comb \z80_|execute_|fMRead~3 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fMRead~3_combout = ((!\z80_|pla_decode_|Equal33~0_combout ) # (!\z80_|ir_|opcode [7])) # (!\z80_|execute_|ctl_ir_we~5_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_ir_we~5_combout ),
|
|
.datab(\z80_|ir_|opcode [7]),
|
|
.datac(\z80_|pla_decode_|Equal33~0_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fMRead~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fMRead~3 .lut_mask = 16'h7F7F;
|
|
defparam \z80_|execute_|fMRead~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y17_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~37 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_bus_inc_oe~37_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~3_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # (!\z80_|execute_|fMRead~3_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_mRead~3_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~4_combout ),
|
|
.datac(\z80_|execute_|ixy_d~7_combout ),
|
|
.datad(\z80_|execute_|fMRead~3_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_bus_inc_oe~37_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~37 .lut_mask = 16'hE0F0;
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~37 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y17_N6
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~38 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_bus_inc_oe~38_combout = (\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # (((\z80_|execute_|ctl_bus_inc_oe~37_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~30_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~48_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ),
|
|
.datab(\z80_|execute_|ctl_bus_inc_oe~48_combout ),
|
|
.datac(\z80_|execute_|ctl_bus_inc_oe~30_combout ),
|
|
.datad(\z80_|execute_|ctl_bus_inc_oe~37_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_bus_inc_oe~38_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~38 .lut_mask = 16'hFFBF;
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~38 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y17_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~39 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_bus_inc_oe~39_combout = (\z80_|execute_|ctl_bus_inc_oe~46_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~47_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~34_combout ) # (\z80_|execute_|ctl_bus_inc_oe~38_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_bus_inc_oe~46_combout ),
|
|
.datab(\z80_|execute_|ctl_bus_inc_oe~47_combout ),
|
|
.datac(\z80_|execute_|ctl_bus_inc_oe~34_combout ),
|
|
.datad(\z80_|execute_|ctl_bus_inc_oe~38_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_bus_inc_oe~39_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~39 .lut_mask = 16'hFFFE;
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~39 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y12_N28
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_bus_inc_oe~43 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_bus_inc_oe~43_combout = (((\z80_|execute_|ctl_bus_inc_oe~39_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~40_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~32_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_bus_inc_oe~42_combout ),
|
|
.datab(\z80_|execute_|ctl_bus_inc_oe~32_combout ),
|
|
.datac(\z80_|execute_|ctl_bus_inc_oe~40_combout ),
|
|
.datad(\z80_|execute_|ctl_bus_inc_oe~39_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_bus_inc_oe~43_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~43 .lut_mask = 16'hFF7F;
|
|
defparam \z80_|execute_|ctl_bus_inc_oe~43 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y16_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~3 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_oe~3_combout = (\z80_|decode_state_|in_halt~q ) # (((!\z80_|pla_decode_|Equal33~0_combout & !\z80_|pla_decode_|Equal33~1_combout )) # (!\z80_|pla_decode_|Equal77~0_combout ))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal33~0_combout ),
|
|
.datab(\z80_|decode_state_|in_halt~q ),
|
|
.datac(\z80_|pla_decode_|Equal33~1_combout ),
|
|
.datad(\z80_|pla_decode_|Equal77~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_oe~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_oe~3 .lut_mask = 16'hCDFF;
|
|
defparam \z80_|execute_|ctl_alu_oe~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y14_N8
|
|
cycloneive_lcell_comb \z80_|execute_|fMWrite~1 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fMWrite~1_combout = (!\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~7_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_ir_we~15_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~4_combout ),
|
|
.datac(\z80_|execute_|ctl_ir_we~14_combout ),
|
|
.datad(\z80_|execute_|ctl_ir_we~7_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fMWrite~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fMWrite~1 .lut_mask = 16'h0001;
|
|
defparam \z80_|execute_|fMWrite~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y12_N28
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~1 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_bus~1_combout = ((\z80_|ir_|opcode [2]) # (\z80_|ir_|opcode [1])) # (!\z80_|execute_|ctl_mWrite~4_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|execute_|ctl_mWrite~4_combout ),
|
|
.datac(\z80_|ir_|opcode [2]),
|
|
.datad(\z80_|ir_|opcode [1]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_bus~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_bus~1 .lut_mask = 16'hFFF3;
|
|
defparam \z80_|execute_|ctl_flags_bus~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y18_N20
|
|
cycloneive_lcell_comb \z80_|execute_|fMRead~5 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fMRead~5_combout = (!\z80_|pla_decode_|Equal13~2_combout & (\z80_|execute_|ctl_flags_bus~1_combout & !\z80_|execute_|ctl_state_alu~6_combout ))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal13~2_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_bus~1_combout ),
|
|
.datac(\z80_|execute_|ctl_state_alu~6_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fMRead~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fMRead~5 .lut_mask = 16'h0404;
|
|
defparam \z80_|execute_|fMRead~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y14_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_mRead~17 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mRead~17_combout = (\z80_|execute_|fMWrite~1_combout & (!\z80_|execute_|ctl_ir_we~12_combout & \z80_|execute_|fMRead~5_combout ))
|
|
|
|
.dataa(\z80_|execute_|fMWrite~1_combout ),
|
|
.datab(\z80_|execute_|ctl_ir_we~12_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|execute_|fMRead~5_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mRead~17_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mRead~17 .lut_mask = 16'h2200;
|
|
defparam \z80_|execute_|ctl_mRead~17 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y16_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_iorw~10 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_iorw~10_combout = (!\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0])))
|
|
|
|
.dataa(\z80_|ir_|opcode [2]),
|
|
.datab(\z80_|pla_decode_|Equal13~0_combout ),
|
|
.datac(\z80_|ir_|opcode [1]),
|
|
.datad(\z80_|ir_|opcode [0]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_iorw~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_iorw~10 .lut_mask = 16'h0400;
|
|
defparam \z80_|execute_|ctl_iorw~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y14_N28
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~47 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~47_combout = (!\z80_|execute_|ctl_iorw~11_combout & (!\z80_|execute_|ctl_mRead~11_combout & (\z80_|execute_|ctl_mRead~17_combout & !\z80_|execute_|ctl_iorw~10_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_iorw~11_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~11_combout ),
|
|
.datac(\z80_|execute_|ctl_mRead~17_combout ),
|
|
.datad(\z80_|execute_|ctl_iorw~10_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~47_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~47 .lut_mask = 16'h0010;
|
|
defparam \z80_|execute_|setM1~47 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y13_N24
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~8 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mWrite~8_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal55~0_combout )))
|
|
|
|
.dataa(\z80_|ir_|opcode [5]),
|
|
.datab(\z80_|pla_decode_|Equal6~0_combout ),
|
|
.datac(\z80_|ir_|opcode [3]),
|
|
.datad(\z80_|pla_decode_|Equal55~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mWrite~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mWrite~8 .lut_mask = 16'h0400;
|
|
defparam \z80_|execute_|ctl_mWrite~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y12_N6
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_al_we~13 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_al_we~13_combout = ((\z80_|ir_|opcode [2]) # (!\z80_|ir_|opcode [1])) # (!\z80_|execute_|ctl_mWrite~4_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|execute_|ctl_mWrite~4_combout ),
|
|
.datac(\z80_|ir_|opcode [2]),
|
|
.datad(\z80_|ir_|opcode [1]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_al_we~13_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_al_we~13 .lut_mask = 16'hF3FF;
|
|
defparam \z80_|execute_|ctl_al_we~13 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y12_N12
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~48 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~48_combout = (\z80_|execute_|setM1~47_combout & (!\z80_|execute_|ctl_mWrite~8_combout & \z80_|execute_|ctl_al_we~13_combout ))
|
|
|
|
.dataa(\z80_|execute_|setM1~47_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_mWrite~8_combout ),
|
|
.datad(\z80_|execute_|ctl_al_we~13_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~48_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~48 .lut_mask = 16'h0A00;
|
|
defparam \z80_|execute_|setM1~48 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y12_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~0 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_sw_4d~0_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((!\z80_|decode_state_|use_ixiy~combout & !\z80_|execute_|ctl_alu_oe~3_combout )) # (!\z80_|execute_|setM1~48_combout )))
|
|
|
|
.dataa(\z80_|decode_state_|use_ixiy~combout ),
|
|
.datab(\z80_|execute_|ctl_state_alu~3_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_oe~3_combout ),
|
|
.datad(\z80_|execute_|setM1~48_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_sw_4d~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_sw_4d~0 .lut_mask = 16'h04CC;
|
|
defparam \z80_|execute_|ctl_sw_4d~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y14_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal48~0_combout & !\z80_|sequencer_|DFFE_M1_ff~q ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|sequencer_|DFFE_T4_ff~q ),
|
|
.datac(\z80_|pla_decode_|Equal48~0_combout ),
|
|
.datad(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .lut_mask = 16'h00C0;
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y12_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_mRead~9 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mRead~9_combout = (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|sequencer_|DFFE_T5_ff~q ),
|
|
.datad(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mRead~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mRead~9 .lut_mask = 16'h00F0;
|
|
defparam \z80_|execute_|ctl_mRead~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y18_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~3 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_sz_we~3_combout = (\z80_|pla_decode_|Equal10~0_combout & (!\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|pla_decode_|Equal21~1_combout )))) # (!\z80_|pla_decode_|Equal10~0_combout &
|
|
// (((!\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|pla_decode_|Equal21~1_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal10~0_combout ),
|
|
.datab(\z80_|pla_decode_|Equal21~1_combout ),
|
|
.datac(\z80_|execute_|ctl_mRead~9_combout ),
|
|
.datad(\z80_|execute_|ixy_d~7_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_sz_we~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_sz_we~3 .lut_mask = 16'h153F;
|
|
defparam \z80_|execute_|ctl_flags_sz_we~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y15_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|pla_decode_|Equal11~0_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datad(\z80_|sequencer_|DFFE_M3_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .lut_mask = 16'h0C00;
|
|
defparam \z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y14_N28
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~9 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_alu~9_combout = (((!\z80_|execute_|ixy_d~6_combout & !\z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_mWrite~4_combout )) # (!\z80_|pla_decode_|Equal8~0_combout )
|
|
|
|
.dataa(\z80_|execute_|ixy_d~6_combout ),
|
|
.datab(\z80_|pla_decode_|Equal8~0_combout ),
|
|
.datac(\z80_|nM1_int~2_combout ),
|
|
.datad(\z80_|execute_|ctl_mWrite~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_alu~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_alu~9 .lut_mask = 16'h37FF;
|
|
defparam \z80_|execute_|ctl_flags_alu~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y18_N16
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_sel_op2_neg~2_combout = ((!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~8_combout )
|
|
|
|
.dataa(\z80_|execute_|ixy_d~8_combout ),
|
|
.datab(\z80_|pla_decode_|Equal21~1_combout ),
|
|
.datac(\z80_|pla_decode_|Equal39~0_combout ),
|
|
.datad(\z80_|pla_decode_|Equal40~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_sel_op2_neg~2 .lut_mask = 16'h5557;
|
|
defparam \z80_|execute_|ctl_alu_sel_op2_neg~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y14_N18
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~10 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_alu~10_combout = (\z80_|execute_|ctl_flags_sz_we~3_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout & (\z80_|execute_|ctl_flags_alu~9_combout & \z80_|execute_|ctl_alu_sel_op2_neg~2_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_sz_we~3_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ),
|
|
.datac(\z80_|execute_|ctl_flags_alu~9_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_alu~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_alu~10 .lut_mask = 16'h2000;
|
|
defparam \z80_|execute_|ctl_flags_alu~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y18_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~10 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_xy_we~10_combout = (((!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4])) # (!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal63~0_combout )
|
|
|
|
.dataa(\z80_|pla_decode_|Equal63~0_combout ),
|
|
.datab(\z80_|nM1_int~2_combout ),
|
|
.datac(\z80_|ir_|opcode [3]),
|
|
.datad(\z80_|ir_|opcode [4]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_xy_we~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_xy_we~10 .lut_mask = 16'h777F;
|
|
defparam \z80_|execute_|ctl_flags_xy_we~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y15_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla11M1T1_11 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|pla_decode_|Equal10~0_combout ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.datac(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datad(\z80_|pla_decode_|Equal10~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .lut_mask = 16'h0300;
|
|
defparam \z80_|execute_|ctl_pf_sel_pla11M1T1_11 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y18_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~11 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_xy_we~11_combout = (\z80_|execute_|ctl_flags_xy_we~10_combout & (!\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout & ((!\z80_|sequencer_|DFFE_T5_ff~q ) # (!\z80_|execute_|ixy_d~15_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_xy_we~10_combout ),
|
|
.datab(\z80_|execute_|ixy_d~15_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_T5_ff~q ),
|
|
.datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_xy_we~11_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_xy_we~11 .lut_mask = 16'h002A;
|
|
defparam \z80_|execute_|ctl_flags_xy_we~11 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y18_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~11 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_alu~11_combout = (\z80_|execute_|ctl_flags_alu~10_combout & (\z80_|execute_|ctl_flags_xy_we~11_combout & ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|execute_|ixy_d~15_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_alu~10_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_xy_we~11_combout ),
|
|
.datac(\z80_|execute_|ixy_d~15_combout ),
|
|
.datad(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_alu~11_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_alu~11 .lut_mask = 16'h0888;
|
|
defparam \z80_|execute_|ctl_flags_alu~11 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y18_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~1 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_use_sp~1_combout = (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|nextM~11_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_reg_use_sp~0_combout ),
|
|
.datad(\z80_|execute_|nextM~11_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_use_sp~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_use_sp~1 .lut_mask = 16'hF000;
|
|
defparam \z80_|execute_|ctl_reg_use_sp~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y15_N16
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_state_alu~4_combout = (\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|sequencer_|DFFE_M4_ff~q ),
|
|
.datad(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_state_alu~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_state_alu~4 .lut_mask = 16'hF000;
|
|
defparam \z80_|execute_|ctl_state_alu~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y15_N2
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~9 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op2_sel_bus~9_combout = (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|pla_decode_|Equal10~0_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q )
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_M2_ff~q ),
|
|
.datab(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.datac(\z80_|pla_decode_|Equal11~0_combout ),
|
|
.datad(\z80_|pla_decode_|Equal10~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .lut_mask = 16'h777F;
|
|
defparam \z80_|execute_|ctl_alu_op2_sel_bus~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y18_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_sw_2d~4_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_mRead~4_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_state_alu~4_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~4_combout ),
|
|
.datac(\z80_|execute_|ctl_state_alu~2_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_sw_2d~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_sw_2d~4 .lut_mask = 16'h3700;
|
|
defparam \z80_|execute_|ctl_sw_2d~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y19_N24
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~0 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_sz_we~0_combout = (\z80_|execute_|ctl_mWrite~9_combout & (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout )))) # (!\z80_|execute_|ctl_mWrite~9_combout & (((!\z80_|execute_|ctl_ir_we~12_combout ))
|
|
// # (!\z80_|execute_|ctl_mWrite~5_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_mWrite~5_combout ),
|
|
.datab(\z80_|execute_|ctl_mWrite~9_combout ),
|
|
.datac(\z80_|execute_|ctl_ir_we~12_combout ),
|
|
.datad(\z80_|execute_|ctl_ir_we~11_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_sz_we~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_sz_we~0 .lut_mask = 16'h131F;
|
|
defparam \z80_|execute_|ctl_flags_sz_we~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y19_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_sz_we~4_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|nM1_int~2_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ),
|
|
.datab(\z80_|execute_|ctl_ir_we~12_combout ),
|
|
.datac(\z80_|execute_|ctl_ir_we~11_combout ),
|
|
.datad(\z80_|nM1_int~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_sz_we~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_sz_we~4 .lut_mask = 16'h02AA;
|
|
defparam \z80_|execute_|ctl_flags_sz_we~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y16_N16
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~47 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op_low~47_combout = (\z80_|pla_decode_|Equal8~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_M3_ff~q )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal8~0_combout ),
|
|
.datab(\z80_|execute_|ctl_mWrite~4_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.datad(\z80_|sequencer_|DFFE_M3_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op_low~47_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op_low~47 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|ctl_alu_op_low~47 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y17_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~3 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_sel_op2_neg~3_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout & (((!\z80_|pla_decode_|Equal21~1_combout & !\z80_|execute_|ctl_mRead~34_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal21~1_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~34_combout ),
|
|
.datac(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T2_3~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_sel_op2_neg~3 .lut_mask = 16'h001F;
|
|
defparam \z80_|execute_|ctl_alu_sel_op2_neg~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y17_N16
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~12 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_alu~12_combout = (!\z80_|execute_|ctl_alu_op_low~47_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op_low~47_combout ),
|
|
.datab(\z80_|pla_decode_|Equal20~0_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ),
|
|
.datad(\z80_|nM1_int~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_alu~12_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_alu~12 .lut_mask = 16'h1050;
|
|
defparam \z80_|execute_|ctl_flags_alu~12 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y19_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~23 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op_low~23_combout = (((!\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal63~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.datab(\z80_|ir_|opcode [4]),
|
|
.datac(\z80_|pla_decode_|Equal63~0_combout ),
|
|
.datad(\z80_|ir_|opcode [3]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op_low~23_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op_low~23 .lut_mask = 16'h5F7F;
|
|
defparam \z80_|execute_|ctl_alu_op_low~23 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y19_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~19 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_xy_we~19_combout = (\z80_|execute_|ctl_alu_op_low~23_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|pla_decode_|Equal20~0_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q )))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T4_ff~q ),
|
|
.datab(\z80_|execute_|ctl_alu_op_low~23_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.datad(\z80_|pla_decode_|Equal20~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_xy_we~19_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_xy_we~19 .lut_mask = 16'hC4CC;
|
|
defparam \z80_|execute_|ctl_flags_xy_we~19 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y18_N16
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~13 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_alu~13_combout = (\z80_|execute_|ctl_sw_2d~4_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & (\z80_|execute_|ctl_flags_alu~12_combout & \z80_|execute_|ctl_flags_xy_we~19_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_sw_2d~4_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_sz_we~4_combout ),
|
|
.datac(\z80_|execute_|ctl_flags_alu~12_combout ),
|
|
.datad(\z80_|execute_|ctl_flags_xy_we~19_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_alu~13_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_alu~13 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|ctl_flags_alu~13 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y18_N18
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_out_hi~4_combout = ((!\z80_|pla_decode_|Equal40~1_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal39~0_combout ))) # (!\z80_|execute_|ixy_d~9_combout )
|
|
|
|
.dataa(\z80_|pla_decode_|Equal40~1_combout ),
|
|
.datab(\z80_|pla_decode_|Equal21~1_combout ),
|
|
.datac(\z80_|pla_decode_|Equal39~0_combout ),
|
|
.datad(\z80_|execute_|ixy_d~9_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_out_hi~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_out_hi~4 .lut_mask = 16'h01FF;
|
|
defparam \z80_|execute_|ctl_reg_out_hi~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y18_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~1 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_sw_4u~1_combout = (\z80_|execute_|ctl_reg_out_hi~4_combout & \z80_|execute_|ctl_reg_sys_hilo[0]~12_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_reg_out_hi~4_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_sw_4u~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_sw_4u~1 .lut_mask = 16'hF000;
|
|
defparam \z80_|execute_|ctl_sw_4u~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y19_N28
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~29 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op_low~29_combout = ((!\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ixy_d~15_combout )
|
|
|
|
.dataa(\z80_|execute_|ixy_d~15_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|sequencer_|DFFE_T4_ff~q ),
|
|
.datad(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op_low~29_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op_low~29 .lut_mask = 16'h555F;
|
|
defparam \z80_|execute_|ctl_alu_op_low~29 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y18_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~14 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_alu~14_combout = (\z80_|execute_|ctl_reg_use_sp~1_combout & (\z80_|execute_|ctl_flags_alu~13_combout & (\z80_|execute_|ctl_sw_4u~1_combout & \z80_|execute_|ctl_alu_op_low~29_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_use_sp~1_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_alu~13_combout ),
|
|
.datac(\z80_|execute_|ctl_sw_4u~1_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op_low~29_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_alu~14_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_alu~14 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|ctl_flags_alu~14 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y18_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout = (\z80_|pla_decode_|Equal63~0_combout & (\z80_|nM1_int~2_combout & (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4])))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal63~0_combout ),
|
|
.datab(\z80_|nM1_int~2_combout ),
|
|
.datac(\z80_|ir_|opcode [3]),
|
|
.datad(\z80_|ir_|opcode [4]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .lut_mask = 16'h0008;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y17_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla82M1T1_16 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout = (!\z80_|ir_|opcode [0] & (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|pla_decode_|Equal3~1_combout )))
|
|
|
|
.dataa(\z80_|ir_|opcode [0]),
|
|
.datab(\z80_|nM1_int~2_combout ),
|
|
.datac(\z80_|pla_decode_|Equal13~0_combout ),
|
|
.datad(\z80_|pla_decode_|Equal3~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .lut_mask = 16'h4000;
|
|
defparam \z80_|execute_|ctl_pf_sel_pla82M1T1_16 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y14_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~13 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_use_cf2~13_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|execute_|ctl_mRead~4_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q )
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T4_ff~q ),
|
|
.datab(\z80_|execute_|ctl_mRead~4_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_M4_ff~q ),
|
|
.datad(\z80_|sequencer_|DFFE_M2_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_use_cf2~13_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_use_cf2~13 .lut_mask = 16'h777F;
|
|
defparam \z80_|execute_|ctl_flags_use_cf2~13 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y18_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~7 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_cf_we~7_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|pla_decode_|Equal13~0_combout ) # (!\z80_|pla_decode_|Equal55~0_combout ))) # (!\z80_|sequencer_|DFFE_M3_ff~q )
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_M3_ff~q ),
|
|
.datab(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datac(\z80_|pla_decode_|Equal55~0_combout ),
|
|
.datad(\z80_|pla_decode_|Equal13~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_cf_we~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_cf_we~7 .lut_mask = 16'hDFFF;
|
|
defparam \z80_|execute_|ctl_flags_cf_we~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y18_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_pf_sel[0]~2_combout = (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (\z80_|execute_|ctl_flags_use_cf2~13_combout & \z80_|execute_|ctl_flags_cf_we~7_combout ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ),
|
|
.datac(\z80_|execute_|ctl_flags_use_cf2~13_combout ),
|
|
.datad(\z80_|execute_|ctl_flags_cf_we~7_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_pf_sel[0]~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_pf_sel[0]~2 .lut_mask = 16'h3000;
|
|
defparam \z80_|execute_|ctl_pf_sel[0]~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y17_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~5 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_hf_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~27_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|execute_|ctl_ir_we~8_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_ir_we~8_combout ),
|
|
.datab(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datac(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.datad(\z80_|execute_|ctl_bus_inc_oe~27_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_hf_we~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_hf_we~5 .lut_mask = 16'hFD00;
|
|
defparam \z80_|execute_|ctl_flags_hf_we~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y18_N2
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~10 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_pf_we~10_combout = (\z80_|execute_|ctl_flags_hf_we~5_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal13~2_combout ),
|
|
.datab(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datac(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.datad(\z80_|execute_|ctl_flags_hf_we~5_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_pf_we~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_pf_we~10 .lut_mask = 16'hFD00;
|
|
defparam \z80_|execute_|ctl_flags_pf_we~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y16_N8
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal68~2 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal68~2_combout = (\z80_|ir_|opcode [6] & (\z80_|decode_state_|DFFE_instED~q & (!\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [0])))
|
|
|
|
.dataa(\z80_|ir_|opcode [6]),
|
|
.datab(\z80_|decode_state_|DFFE_instED~q ),
|
|
.datac(\z80_|ir_|opcode [7]),
|
|
.datad(\z80_|ir_|opcode [0]),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal68~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal68~2 .lut_mask = 16'h0008;
|
|
defparam \z80_|pla_decode_|Equal68~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y19_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~13 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo[1]~13_combout = ((!\z80_|execute_|ctl_alu_op_low~27_combout & ((!\z80_|pla_decode_|Equal68~2_combout ) # (!\z80_|pla_decode_|Equal1~4_combout )))) # (!\z80_|nM1_int~2_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op_low~27_combout ),
|
|
.datab(\z80_|pla_decode_|Equal1~4_combout ),
|
|
.datac(\z80_|nM1_int~2_combout ),
|
|
.datad(\z80_|pla_decode_|Equal68~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo[1]~13_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~13 .lut_mask = 16'h1F5F;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~13 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y18_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_pf_we~2_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (\z80_|execute_|ctl_pf_sel[0]~2_combout & (\z80_|execute_|ctl_flags_pf_we~10_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~13_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ),
|
|
.datab(\z80_|execute_|ctl_pf_sel[0]~2_combout ),
|
|
.datac(\z80_|execute_|ctl_flags_pf_we~10_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_hilo[1]~13_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_pf_we~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_pf_we~2 .lut_mask = 16'h4000;
|
|
defparam \z80_|execute_|ctl_flags_pf_we~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y17_N18
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_oe~4_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_mWrite~17_combout & ((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_mRead~9_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout &
|
|
// (((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_mRead~9_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_state_alu~2_combout ),
|
|
.datab(\z80_|execute_|ctl_mWrite~17_combout ),
|
|
.datac(\z80_|execute_|ctl_mRead~9_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~34_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_oe~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_oe~4 .lut_mask = 16'h0777;
|
|
defparam \z80_|execute_|ctl_alu_oe~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y18_N16
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~8 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_xy_we~8_combout = (!\z80_|execute_|ctl_reg_gp_sel~7_combout & \z80_|execute_|setM1~18_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_sel~7_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|setM1~18_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_xy_we~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_xy_we~8 .lut_mask = 16'h5050;
|
|
defparam \z80_|execute_|ctl_flags_xy_we~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y19_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~20 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_xy_we~20_combout = (((!\z80_|pla_decode_|Equal13~0_combout ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|pla_decode_|Equal55~0_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q )
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.datab(\z80_|pla_decode_|Equal55~0_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_M2_ff~q ),
|
|
.datad(\z80_|pla_decode_|Equal13~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_xy_we~20_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_xy_we~20 .lut_mask = 16'h7FFF;
|
|
defparam \z80_|execute_|ctl_flags_xy_we~20 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y18_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~9 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_xy_we~9_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (\z80_|execute_|ctl_alu_oe~4_combout & (\z80_|execute_|ctl_flags_xy_we~8_combout & \z80_|execute_|ctl_flags_xy_we~20_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_pf_we~2_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_oe~4_combout ),
|
|
.datac(\z80_|execute_|ctl_flags_xy_we~8_combout ),
|
|
.datad(\z80_|execute_|ctl_flags_xy_we~20_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_xy_we~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_xy_we~9 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|ctl_flags_xy_we~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y14_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~1 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_sz_we~1_combout = ((!\z80_|execute_|ctl_state_alu~5_combout & (!\z80_|execute_|ctl_state_alu~6_combout & !\z80_|pla_decode_|Equal52~1_combout ))) # (!\z80_|nM1_int~2_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_state_alu~5_combout ),
|
|
.datab(\z80_|nM1_int~2_combout ),
|
|
.datac(\z80_|execute_|ctl_state_alu~6_combout ),
|
|
.datad(\z80_|pla_decode_|Equal52~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_sz_we~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_sz_we~1 .lut_mask = 16'h3337;
|
|
defparam \z80_|execute_|ctl_flags_sz_we~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y18_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~1 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_bus_db_oe~1_combout = (!\z80_|pla_decode_|Equal21~1_combout & (!\z80_|pla_decode_|Equal39~0_combout & !\z80_|pla_decode_|Equal40~1_combout ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|pla_decode_|Equal21~1_combout ),
|
|
.datac(\z80_|pla_decode_|Equal39~0_combout ),
|
|
.datad(\z80_|pla_decode_|Equal40~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_bus_db_oe~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_bus_db_oe~1 .lut_mask = 16'h0003;
|
|
defparam \z80_|execute_|ctl_bus_db_oe~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y19_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~10 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op2_sel_bus~10_combout = (\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ixy_d~15_combout & ((\z80_|execute_|ctl_bus_db_oe~1_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q ))))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_M3_ff~q ),
|
|
.datab(\z80_|execute_|ctl_bus_db_oe~1_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datad(\z80_|execute_|ixy_d~15_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .lut_mask = 16'hF0FD;
|
|
defparam \z80_|execute_|ctl_alu_op2_sel_bus~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y18_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_sz_we~2_combout = (\z80_|execute_|ctl_flags_xy_we~9_combout & (\z80_|execute_|ctl_flags_sz_we~1_combout & \z80_|execute_|ctl_alu_op2_sel_bus~10_combout ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|execute_|ctl_flags_xy_we~9_combout ),
|
|
.datac(\z80_|execute_|ctl_flags_sz_we~1_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_sz_we~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_sz_we~2 .lut_mask = 16'hC000;
|
|
defparam \z80_|execute_|ctl_flags_sz_we~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y17_N6
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~17 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_alu~17_combout = (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~8_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q )
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.datab(\z80_|execute_|ctl_ir_we~14_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_M4_ff~q ),
|
|
.datad(\z80_|execute_|ctl_ir_we~8_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_alu~17_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_alu~17 .lut_mask = 16'h5F7F;
|
|
defparam \z80_|execute_|ctl_flags_alu~17 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y19_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~18 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_alu~18_combout = (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q )
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.datab(\z80_|sequencer_|DFFE_M4_ff~q ),
|
|
.datac(\z80_|execute_|ctl_ir_we~7_combout ),
|
|
.datad(\z80_|execute_|ctl_ir_we~10_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_alu~18_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_alu~18 .lut_mask = 16'h777F;
|
|
defparam \z80_|execute_|ctl_flags_alu~18 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y19_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~6 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_alu~6_combout = (\z80_|execute_|ctl_flags_alu~18_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_ir_we~15_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_alu~18_combout ),
|
|
.datac(\z80_|execute_|ctl_ir_we~9_combout ),
|
|
.datad(\z80_|execute_|ctl_state_alu~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_alu~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_alu~6 .lut_mask = 16'h04CC;
|
|
defparam \z80_|execute_|ctl_flags_alu~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y19_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~19 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_alu~19_combout = (((!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_mWrite~17_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q )
|
|
|
|
.dataa(\z80_|execute_|ctl_ir_we~14_combout ),
|
|
.datab(\z80_|sequencer_|DFFE_T4_ff~q ),
|
|
.datac(\z80_|sequencer_|DFFE_M2_ff~q ),
|
|
.datad(\z80_|execute_|ctl_mWrite~17_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_alu~19_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_alu~19 .lut_mask = 16'h3F7F;
|
|
defparam \z80_|execute_|ctl_flags_alu~19 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y14_N24
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal1~5 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal1~5_combout = (!\z80_|ir_|opcode [5] & \z80_|ir_|opcode [4])
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|ir_|opcode [5]),
|
|
.datad(\z80_|ir_|opcode [4]),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal1~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal1~5 .lut_mask = 16'h0F00;
|
|
defparam \z80_|pla_decode_|Equal1~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y19_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~0 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_core_R~0_combout = (\z80_|pla_decode_|Equal1~5_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal13~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal1~5_combout ),
|
|
.datab(\z80_|pla_decode_|Equal13~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal13~1_combout ),
|
|
.datad(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_core_R~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_core_R~0 .lut_mask = 16'h0080;
|
|
defparam \z80_|execute_|ctl_alu_core_R~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y19_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|pla_decode_|Equal11~0_combout ))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.datab(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datac(\z80_|pla_decode_|Equal11~0_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 .lut_mask = 16'h1010;
|
|
defparam \z80_|execute_|ctl_pf_sel_pla12M1T1_12~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y19_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~1 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_core_R~1_combout = (\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_core_R~0_combout ),
|
|
.datab(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datac(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ),
|
|
.datad(\z80_|sequencer_|DFFE_T4_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_core_R~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_core_R~1 .lut_mask = 16'hFAF2;
|
|
defparam \z80_|execute_|ctl_alu_core_R~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y18_N24
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~7 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_alu~7_combout = ((\z80_|execute_|ctl_alu_core_R~1_combout ) # ((\z80_|pla_decode_|Equal56~0_combout & \z80_|execute_|ixy_d~7_combout ))) # (!\z80_|execute_|ctl_flags_alu~19_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_alu~19_combout ),
|
|
.datab(\z80_|pla_decode_|Equal56~0_combout ),
|
|
.datac(\z80_|execute_|ixy_d~7_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_core_R~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_alu~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_alu~7 .lut_mask = 16'hFFD5;
|
|
defparam \z80_|execute_|ctl_flags_alu~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y18_N12
|
|
cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~5 (
|
|
// Equation(s):
|
|
// \z80_|reg_control_|reg_sys_we_lo~5_combout = ((!\z80_|pla_decode_|Equal39~0_combout & (!\z80_|pla_decode_|Equal21~1_combout & !\z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ixy_d~6_combout )
|
|
|
|
.dataa(\z80_|pla_decode_|Equal39~0_combout ),
|
|
.datab(\z80_|pla_decode_|Equal21~1_combout ),
|
|
.datac(\z80_|execute_|ixy_d~6_combout ),
|
|
.datad(\z80_|pla_decode_|Equal40~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_control_|reg_sys_we_lo~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_control_|reg_sys_we_lo~5 .lut_mask = 16'h0F1F;
|
|
defparam \z80_|reg_control_|reg_sys_we_lo~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y19_N28
|
|
cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~8 (
|
|
// Equation(s):
|
|
// \z80_|reg_control_|reg_sys_we_lo~8_combout = (\z80_|reg_control_|reg_sys_we_lo~5_combout & (((!\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|pla_decode_|Equal56~0_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q )))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_M2_ff~q ),
|
|
.datab(\z80_|pla_decode_|Equal56~0_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.datad(\z80_|reg_control_|reg_sys_we_lo~5_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_control_|reg_sys_we_lo~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_control_|reg_sys_we_lo~8 .lut_mask = 16'h7F00;
|
|
defparam \z80_|reg_control_|reg_sys_we_lo~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y18_N24
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~8 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_alu~8_combout = (((\z80_|execute_|ctl_flags_alu~7_combout ) # (!\z80_|reg_control_|reg_sys_we_lo~8_combout )) # (!\z80_|execute_|ctl_flags_alu~6_combout )) # (!\z80_|execute_|ctl_flags_alu~17_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_alu~17_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_alu~6_combout ),
|
|
.datac(\z80_|execute_|ctl_flags_alu~7_combout ),
|
|
.datad(\z80_|reg_control_|reg_sys_we_lo~8_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_alu~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_alu~8 .lut_mask = 16'hF7FF;
|
|
defparam \z80_|execute_|ctl_flags_alu~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y18_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~15 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_alu~15_combout = (((\z80_|execute_|ctl_flags_alu~8_combout ) # (!\z80_|execute_|ctl_flags_sz_we~2_combout )) # (!\z80_|execute_|ctl_flags_alu~14_combout )) # (!\z80_|execute_|ctl_flags_alu~11_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_alu~11_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_alu~14_combout ),
|
|
.datac(\z80_|execute_|ctl_flags_sz_we~2_combout ),
|
|
.datad(\z80_|execute_|ctl_flags_alu~8_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_alu~15_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_alu~15 .lut_mask = 16'hFF7F;
|
|
defparam \z80_|execute_|ctl_flags_alu~15 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y16_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~7 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_state_alu~7_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_state_alu~6_combout & ((!\z80_|pla_decode_|Equal52~1_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout &
|
|
// (((!\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|execute_|ctl_state_alu~6_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_state_alu~2_combout ),
|
|
.datab(\z80_|execute_|ctl_state_alu~6_combout ),
|
|
.datac(\z80_|execute_|ctl_state_alu~4_combout ),
|
|
.datad(\z80_|pla_decode_|Equal52~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_state_alu~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_state_alu~7 .lut_mask = 16'h1537;
|
|
defparam \z80_|execute_|ctl_state_alu~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y16_N24
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~12 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_state_alu~12_combout = (\z80_|execute_|ctl_state_alu~7_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal52~1_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal52~1_combout ),
|
|
.datab(\z80_|execute_|ctl_state_alu~7_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_T4_ff~q ),
|
|
.datad(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_state_alu~12_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_state_alu~12 .lut_mask = 16'hCC4C;
|
|
defparam \z80_|execute_|ctl_state_alu~12 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y19_N6
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~9 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_state_alu~9_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q ))))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T4_ff~q ),
|
|
.datab(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.datac(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datad(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_state_alu~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_state_alu~9 .lut_mask = 16'h00EF;
|
|
defparam \z80_|execute_|ctl_state_alu~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y19_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~10 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_state_alu~10_combout = (\z80_|execute_|ctl_state_alu~9_combout & ((\z80_|execute_|ctl_state_alu~5_combout ) # ((\z80_|pla_decode_|Equal52~1_combout & \z80_|execute_|ctl_state_alu~3_combout )))) #
|
|
// (!\z80_|execute_|ctl_state_alu~9_combout & (((\z80_|pla_decode_|Equal52~1_combout & \z80_|execute_|ctl_state_alu~3_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_state_alu~9_combout ),
|
|
.datab(\z80_|execute_|ctl_state_alu~5_combout ),
|
|
.datac(\z80_|pla_decode_|Equal52~1_combout ),
|
|
.datad(\z80_|execute_|ctl_state_alu~3_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_state_alu~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_state_alu~10 .lut_mask = 16'hF888;
|
|
defparam \z80_|execute_|ctl_state_alu~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y19_N18
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~8 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_state_alu~8_combout = (\z80_|pla_decode_|Equal52~1_combout & (((\z80_|nM1_int~2_combout )) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))) # (!\z80_|pla_decode_|Equal52~1_combout & (\z80_|execute_|ctl_state_alu~6_combout &
|
|
// ((\z80_|nM1_int~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal52~1_combout ),
|
|
.datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ),
|
|
.datac(\z80_|execute_|ctl_state_alu~6_combout ),
|
|
.datad(\z80_|nM1_int~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_state_alu~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_state_alu~8 .lut_mask = 16'hFA32;
|
|
defparam \z80_|execute_|ctl_state_alu~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y19_N12
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal64~0 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal64~0_combout = (!\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~10_combout ) # (\z80_|execute_|ctl_state_alu~8_combout )) # (!\z80_|execute_|ctl_state_alu~12_combout )))
|
|
|
|
.dataa(\z80_|ir_|opcode [5]),
|
|
.datab(\z80_|execute_|ctl_state_alu~12_combout ),
|
|
.datac(\z80_|execute_|ctl_state_alu~10_combout ),
|
|
.datad(\z80_|execute_|ctl_state_alu~8_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal64~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal64~0 .lut_mask = 16'h5551;
|
|
defparam \z80_|pla_decode_|Equal64~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y19_N2
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel[0]~3 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_pf_sel[0]~3_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )) # (!\z80_|pla_decode_|Equal64~0_combout )
|
|
|
|
.dataa(\z80_|pla_decode_|Equal64~0_combout ),
|
|
.datab(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datac(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_pf_sel[0]~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_pf_sel[0]~3 .lut_mask = 16'hFDFD;
|
|
defparam \z80_|execute_|ctl_pf_sel[0]~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y19_N22
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal62~2 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal62~2_combout = (\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_state_alu~10_combout ) # (\z80_|execute_|ctl_state_alu~8_combout )) # (!\z80_|execute_|ctl_state_alu~12_combout )))
|
|
|
|
.dataa(\z80_|ir_|opcode [5]),
|
|
.datab(\z80_|execute_|ctl_state_alu~12_combout ),
|
|
.datac(\z80_|execute_|ctl_state_alu~10_combout ),
|
|
.datad(\z80_|execute_|ctl_state_alu~8_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal62~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal62~2 .lut_mask = 16'hAAA2;
|
|
defparam \z80_|pla_decode_|Equal62~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y19_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_pf_we~4_combout = (((\z80_|ir_|opcode [3] & \z80_|ir_|opcode [4])) # (!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal62~2_combout )
|
|
|
|
.dataa(\z80_|ir_|opcode [3]),
|
|
.datab(\z80_|ir_|opcode [4]),
|
|
.datac(\z80_|pla_decode_|Equal62~2_combout ),
|
|
.datad(\z80_|nM1_int~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_pf_we~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_pf_we~4 .lut_mask = 16'h8FFF;
|
|
defparam \z80_|execute_|ctl_flags_pf_we~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y20_N6
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~46 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_shift_oe~46_combout = (\z80_|execute_|ctl_alu_shift_oe~41_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # ((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|pla_decode_|Equal48~0_combout ))))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.datab(\z80_|pla_decode_|Equal48~0_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_shift_oe~41_combout ),
|
|
.datad(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_shift_oe~46_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~46 .lut_mask = 16'hB0F0;
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~46 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y20_N16
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~6 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_pf_we~6_combout = (\z80_|pla_decode_|Equal69~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q ))))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal69~0_combout ),
|
|
.datab(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.datac(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.datad(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_pf_we~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_pf_we~6 .lut_mask = 16'h080A;
|
|
defparam \z80_|execute_|ctl_flags_pf_we~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y20_N2
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~7 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_pf_we~7_combout = (\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_flags_pf_we~6_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|nM1_int~2_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_mRead~34_combout ),
|
|
.datab(\z80_|nM1_int~2_combout ),
|
|
.datac(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ),
|
|
.datad(\z80_|execute_|ctl_flags_pf_we~6_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_pf_we~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_pf_we~7 .lut_mask = 16'hFFF8;
|
|
defparam \z80_|execute_|ctl_flags_pf_we~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y19_N28
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~11 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_state_alu~11_combout = ((\z80_|execute_|ctl_state_alu~10_combout ) # ((\z80_|execute_|ctl_reg_gp_sel~7_combout ) # (\z80_|execute_|ctl_state_alu~8_combout ))) # (!\z80_|execute_|ctl_state_alu~7_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_state_alu~7_combout ),
|
|
.datab(\z80_|execute_|ctl_state_alu~10_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_sel~7_combout ),
|
|
.datad(\z80_|execute_|ctl_state_alu~8_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_state_alu~11_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_state_alu~11 .lut_mask = 16'hFFFD;
|
|
defparam \z80_|execute_|ctl_state_alu~11 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y17_N26
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal62~3 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal62~3_combout = (\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_state_alu~11_combout & \z80_|ir_|opcode [3])))
|
|
|
|
.dataa(\z80_|ir_|opcode [5]),
|
|
.datab(\z80_|ir_|opcode [4]),
|
|
.datac(\z80_|execute_|ctl_state_alu~11_combout ),
|
|
.datad(\z80_|ir_|opcode [3]),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal62~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal62~3 .lut_mask = 16'h8000;
|
|
defparam \z80_|pla_decode_|Equal62~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y20_N26
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~5 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_pf_we~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_mWrite~17_combout ) # ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|pla_decode_|Equal62~3_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_mWrite~17_combout ),
|
|
.datab(\z80_|nM1_int~2_combout ),
|
|
.datac(\z80_|pla_decode_|Equal11~0_combout ),
|
|
.datad(\z80_|pla_decode_|Equal62~3_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_pf_we~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_pf_we~5 .lut_mask = 16'hCCC8;
|
|
defparam \z80_|execute_|ctl_flags_pf_we~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y20_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~3 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_pf_we~3_combout = (\z80_|execute_|ctl_flags_pf_we~2_combout & (((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|nM1_int~2_combout )))
|
|
|
|
.dataa(\z80_|nM1_int~2_combout ),
|
|
.datab(\z80_|execute_|ctl_ir_we~12_combout ),
|
|
.datac(\z80_|execute_|ctl_flags_pf_we~2_combout ),
|
|
.datad(\z80_|execute_|ctl_ir_we~11_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_pf_we~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_pf_we~3 .lut_mask = 16'h5070;
|
|
defparam \z80_|execute_|ctl_flags_pf_we~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y20_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~8 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_pf_we~8_combout = ((\z80_|execute_|ctl_flags_pf_we~7_combout ) # ((\z80_|execute_|ctl_flags_pf_we~5_combout ) # (!\z80_|execute_|ctl_flags_pf_we~3_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_shift_oe~46_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_pf_we~7_combout ),
|
|
.datac(\z80_|execute_|ctl_flags_pf_we~5_combout ),
|
|
.datad(\z80_|execute_|ctl_flags_pf_we~3_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_pf_we~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_pf_we~8 .lut_mask = 16'hFDFF;
|
|
defparam \z80_|execute_|ctl_flags_pf_we~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y19_N6
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_pf_we~9 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_pf_we~9_combout = (((\z80_|execute_|ctl_flags_pf_we~8_combout ) # (!\z80_|execute_|ctl_flags_pf_we~4_combout )) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout )) # (!\z80_|execute_|ctl_flags_xy_we~13_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_xy_we~13_combout ),
|
|
.datab(\z80_|execute_|ctl_pf_sel[0]~3_combout ),
|
|
.datac(\z80_|execute_|ctl_flags_pf_we~4_combout ),
|
|
.datad(\z80_|execute_|ctl_flags_pf_we~8_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_pf_we~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_pf_we~9 .lut_mask = 16'hFF7F;
|
|
defparam \z80_|execute_|ctl_flags_pf_we~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y20_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~6 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_core_S~6_combout = (\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_mWrite~5_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_ir_we~9_combout )))) # (!\z80_|execute_|ctl_ir_we~15_combout &
|
|
// (((!\z80_|nM1_int~2_combout ) # (!\z80_|execute_|ctl_ir_we~9_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_ir_we~15_combout ),
|
|
.datab(\z80_|execute_|ctl_mWrite~5_combout ),
|
|
.datac(\z80_|execute_|ctl_ir_we~9_combout ),
|
|
.datad(\z80_|nM1_int~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_core_S~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_core_S~6 .lut_mask = 16'h0777;
|
|
defparam \z80_|execute_|ctl_alu_core_S~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y20_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~7 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_core_S~7_combout = (\z80_|execute_|ctl_alu_core_S~6_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_alu_oe~0_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_ir_we~15_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_oe~0_combout ),
|
|
.datac(\z80_|execute_|ctl_ir_we~9_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_core_S~6_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_core_S~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_core_S~7 .lut_mask = 16'h3700;
|
|
defparam \z80_|execute_|ctl_alu_core_S~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y20_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~1 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_res_oe~1_combout = (\z80_|execute_|ctl_alu_core_S~7_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|nM1_int~2_combout )))
|
|
|
|
.dataa(\z80_|nM1_int~2_combout ),
|
|
.datab(\z80_|pla_decode_|Equal11~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal69~0_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_core_S~7_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_res_oe~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_res_oe~1 .lut_mask = 16'h5700;
|
|
defparam \z80_|execute_|ctl_alu_res_oe~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y17_N26
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~0 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_res_oe~0_combout = (\z80_|pla_decode_|Equal8~0_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal55~0_combout )))) # (!\z80_|pla_decode_|Equal8~0_combout &
|
|
// (((\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal55~0_combout ))))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal8~0_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~9_combout ),
|
|
.datac(\z80_|nM1_int~2_combout ),
|
|
.datad(\z80_|pla_decode_|Equal55~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_res_oe~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_res_oe~0 .lut_mask = 16'hF888;
|
|
defparam \z80_|execute_|ctl_alu_res_oe~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y20_N24
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_core_S~4_combout = (\z80_|execute_|ctl_ir_we~7_combout & (!\z80_|execute_|ctl_mWrite~5_combout & ((!\z80_|execute_|ctl_ir_we~10_combout ) # (!\z80_|nM1_int~2_combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout &
|
|
// (((!\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|nM1_int~2_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_ir_we~7_combout ),
|
|
.datab(\z80_|nM1_int~2_combout ),
|
|
.datac(\z80_|execute_|ctl_mWrite~5_combout ),
|
|
.datad(\z80_|execute_|ctl_ir_we~10_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_core_S~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_core_S~4 .lut_mask = 16'h135F;
|
|
defparam \z80_|execute_|ctl_alu_core_S~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y20_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~5 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_core_S~5_combout = (\z80_|execute_|ctl_alu_core_S~4_combout & (((!\z80_|execute_|ctl_ir_we~7_combout & !\z80_|execute_|ctl_ir_we~10_combout )) # (!\z80_|execute_|ctl_alu_oe~0_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_ir_we~7_combout ),
|
|
.datab(\z80_|execute_|ctl_ir_we~10_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_oe~0_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_core_S~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_core_S~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_core_S~5 .lut_mask = 16'h1F00;
|
|
defparam \z80_|execute_|ctl_alu_core_S~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y20_N26
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_res_oe~2_combout = (\z80_|execute_|ctl_alu_res_oe~1_combout & (\z80_|execute_|ctl_alu_core_S~5_combout & ((!\z80_|execute_|ctl_mWrite~4_combout ) # (!\z80_|execute_|ctl_alu_res_oe~0_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_res_oe~1_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_res_oe~0_combout ),
|
|
.datac(\z80_|execute_|ctl_mWrite~4_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_core_S~5_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_res_oe~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_res_oe~2 .lut_mask = 16'h2A00;
|
|
defparam \z80_|execute_|ctl_alu_res_oe~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y17_N26
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout = (\z80_|pla_decode_|Equal2~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & (!\z80_|ir_|opcode [0] & \z80_|execute_|ctl_state_alu~2_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal2~0_combout ),
|
|
.datab(\z80_|execute_|ctl_mWrite~4_combout ),
|
|
.datac(\z80_|ir_|opcode [0]),
|
|
.datad(\z80_|execute_|ctl_state_alu~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .lut_mask = 16'h0800;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y19_N18
|
|
cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~6 (
|
|
// Equation(s):
|
|
// \z80_|reg_control_|reg_sys_we_lo~6_combout = (\z80_|reg_control_|reg_sys_we_lo~5_combout & (\z80_|execute_|ctl_flags_xy_we~20_combout & ((!\z80_|pla_decode_|Equal56~0_combout ) # (!\z80_|execute_|ctl_alu_op_low~22_combout ))))
|
|
|
|
.dataa(\z80_|reg_control_|reg_sys_we_lo~5_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_op_low~22_combout ),
|
|
.datac(\z80_|pla_decode_|Equal56~0_combout ),
|
|
.datad(\z80_|execute_|ctl_flags_xy_we~20_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_control_|reg_sys_we_lo~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_control_|reg_sys_we_lo~6 .lut_mask = 16'h2A00;
|
|
defparam \z80_|reg_control_|reg_sys_we_lo~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y19_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~12 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_xy_we~12_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|pla_decode_|Equal56~0_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout )))) # (!\z80_|execute_|ixy_d~7_combout &
|
|
// (((!\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal20~0_combout )))
|
|
|
|
.dataa(\z80_|execute_|ixy_d~7_combout ),
|
|
.datab(\z80_|pla_decode_|Equal20~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal56~0_combout ),
|
|
.datad(\z80_|nM1_int~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_xy_we~12_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_xy_we~12 .lut_mask = 16'h135F;
|
|
defparam \z80_|execute_|ctl_flags_xy_we~12 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y18_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_cf_we~2_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & (\z80_|reg_control_|reg_sys_we_lo~6_combout & (\z80_|execute_|ctl_flags_sz_we~1_combout & \z80_|execute_|ctl_flags_xy_we~12_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ),
|
|
.datab(\z80_|reg_control_|reg_sys_we_lo~6_combout ),
|
|
.datac(\z80_|execute_|ctl_flags_sz_we~1_combout ),
|
|
.datad(\z80_|execute_|ctl_flags_xy_we~12_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_cf_we~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_cf_we~2 .lut_mask = 16'h4000;
|
|
defparam \z80_|execute_|ctl_flags_cf_we~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y18_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_res_oe~3 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_res_oe~3_combout = (\z80_|execute_|ctl_flags_alu~11_combout & (\z80_|execute_|ctl_alu_res_oe~2_combout & (\z80_|execute_|ctl_flags_cf_we~2_combout & \z80_|execute_|ctl_flags_pf_we~3_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_alu~11_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_res_oe~2_combout ),
|
|
.datac(\z80_|execute_|ctl_flags_cf_we~2_combout ),
|
|
.datad(\z80_|execute_|ctl_flags_pf_we~3_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_res_oe~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_res_oe~3 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|ctl_alu_res_oe~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y18_N24
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_high (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_sel_op2_high~combout = ((\z80_|pla_decode_|Equal13~2_combout & (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_M3_ff~q ))) # (!\z80_|execute_|ctl_alu_res_oe~3_combout )
|
|
|
|
.dataa(\z80_|pla_decode_|Equal13~2_combout ),
|
|
.datab(\z80_|sequencer_|DFFE_T4_ff~q ),
|
|
.datac(\z80_|execute_|ctl_alu_res_oe~3_combout ),
|
|
.datad(\z80_|sequencer_|DFFE_M3_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_sel_op2_high~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_sel_op2_high .lut_mask = 16'h8F0F;
|
|
defparam \z80_|execute_|ctl_alu_sel_op2_high .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y17_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op1_sel_zero~4_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [0])))
|
|
|
|
.dataa(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.datab(\z80_|pla_decode_|Equal3~1_combout ),
|
|
.datac(\z80_|pla_decode_|Equal13~0_combout ),
|
|
.datad(\z80_|ir_|opcode [0]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .lut_mask = 16'h0080;
|
|
defparam \z80_|execute_|ctl_alu_op1_sel_zero~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y16_N26
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~12 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_core_hf~12_combout = ((!\z80_|pla_decode_|Equal3~0_combout & ((\z80_|ir_|opcode [5]) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~11_combout )
|
|
|
|
.dataa(\z80_|pla_decode_|Equal3~0_combout ),
|
|
.datab(\z80_|pla_decode_|Equal21~0_combout ),
|
|
.datac(\z80_|ir_|opcode [5]),
|
|
.datad(\z80_|execute_|ctl_state_alu~11_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_core_hf~12_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_core_hf~12 .lut_mask = 16'h51FF;
|
|
defparam \z80_|execute_|ctl_alu_core_hf~12 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y16_N10
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal61~2 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal61~2_combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal6~0_combout & (!\z80_|ir_|opcode [1] & \z80_|ir_|opcode [0])))
|
|
|
|
.dataa(\z80_|ir_|opcode [2]),
|
|
.datab(\z80_|pla_decode_|Equal6~0_combout ),
|
|
.datac(\z80_|ir_|opcode [1]),
|
|
.datad(\z80_|ir_|opcode [0]),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal61~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal61~2 .lut_mask = 16'h0800;
|
|
defparam \z80_|pla_decode_|Equal61~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y17_N16
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_sel_op2_neg~4_combout = (((!\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|nM1_int~2_combout )) # (!\z80_|pla_decode_|Equal32~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.datab(\z80_|nM1_int~2_combout ),
|
|
.datac(\z80_|pla_decode_|Equal63~0_combout ),
|
|
.datad(\z80_|pla_decode_|Equal32~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .lut_mask = 16'h1FFF;
|
|
defparam \z80_|execute_|ctl_alu_sel_op2_neg~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y15_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~13 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_sel_op2_neg~13_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|pla_decode_|Equal61~2_combout )))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_M2_ff~q ),
|
|
.datab(\z80_|pla_decode_|Equal61~2_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ),
|
|
.datad(\z80_|sequencer_|DFFE_M4_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .lut_mask = 16'h3070;
|
|
defparam \z80_|execute_|ctl_alu_sel_op2_neg~13 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y20_N28
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~14 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_sel_op2_neg~14_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~4_combout & (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (\z80_|execute_|ctl_alu_core_hf~12_combout & \z80_|execute_|ctl_alu_sel_op2_neg~13_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ),
|
|
.datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ),
|
|
.datac(\z80_|execute_|ctl_alu_core_hf~12_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .lut_mask = 16'h1000;
|
|
defparam \z80_|execute_|ctl_alu_sel_op2_neg~14 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y19_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~18 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_sel_op2_neg~18_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~14_combout & (((!\z80_|execute_|ctl_mWrite~17_combout ) # (!\z80_|sequencer_|DFFE_M2_ff~q )) # (!\z80_|sequencer_|DFFE_T4_ff~q )))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ),
|
|
.datab(\z80_|sequencer_|DFFE_T4_ff~q ),
|
|
.datac(\z80_|sequencer_|DFFE_M2_ff~q ),
|
|
.datad(\z80_|execute_|ctl_mWrite~17_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_sel_op2_neg~18 .lut_mask = 16'h2AAA;
|
|
defparam \z80_|execute_|ctl_alu_sel_op2_neg~18 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y19_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~10 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_bus~10_combout = (\z80_|execute_|ctl_flags_bus~9_combout & (\z80_|execute_|ctl_alu_shift_oe~20_combout & \z80_|execute_|ctl_bus_db_oe~3_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_bus~9_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_shift_oe~20_combout ),
|
|
.datac(\z80_|execute_|ctl_bus_db_oe~3_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_bus~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_bus~10 .lut_mask = 16'h8080;
|
|
defparam \z80_|execute_|ctl_flags_bus~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y16_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_bus~2_combout = (\z80_|pla_decode_|Equal44~0_combout ) # ((\z80_|pla_decode_|Equal52~0_combout & \z80_|pla_decode_|Equal33~0_combout ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|pla_decode_|Equal44~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal52~0_combout ),
|
|
.datad(\z80_|pla_decode_|Equal33~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_bus~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_bus~2 .lut_mask = 16'hFCCC;
|
|
defparam \z80_|execute_|ctl_flags_bus~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y17_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~0 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_bus~0_combout = (\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal13~1_combout ) # (!\z80_|pla_decode_|Equal13~0_combout ))
|
|
|
|
.dataa(\z80_|ir_|opcode [5]),
|
|
.datab(\z80_|pla_decode_|Equal13~0_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|pla_decode_|Equal13~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_bus~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_bus~0 .lut_mask = 16'hBBFF;
|
|
defparam \z80_|execute_|ctl_flags_bus~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y19_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus~3 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_bus~3_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_flags_bus~2_combout ) # ((!\z80_|execute_|ctl_flags_bus~0_combout ) # (!\z80_|execute_|ctl_flags_bus~1_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_bus~2_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_bus~1_combout ),
|
|
.datac(\z80_|execute_|ctl_flags_bus~0_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_bus~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_bus~3 .lut_mask = 16'hBF00;
|
|
defparam \z80_|execute_|ctl_flags_bus~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y19_N10
|
|
cycloneive_lcell_comb \z80_|execute_|fMRead~26 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fMRead~26_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout )))) # (!\z80_|execute_|ctl_ir_we~12_combout
|
|
// & (((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_ir_we~12_combout ),
|
|
.datab(\z80_|execute_|ctl_state_alu~2_combout ),
|
|
.datac(\z80_|execute_|ctl_state_alu~6_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fMRead~26_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fMRead~26 .lut_mask = 16'h0777;
|
|
defparam \z80_|execute_|fMRead~26 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y19_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_bus (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_bus~combout = ((\z80_|execute_|ctl_flags_bus~3_combout ) # ((\z80_|execute_|ctl_flags_hf2_we~combout ) # (!\z80_|execute_|fMRead~26_combout ))) # (!\z80_|execute_|ctl_flags_bus~10_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_bus~10_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_bus~3_combout ),
|
|
.datac(\z80_|execute_|ctl_flags_hf2_we~combout ),
|
|
.datad(\z80_|execute_|fMRead~26_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_bus~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_bus .lut_mask = 16'hFDFF;
|
|
defparam \z80_|execute_|ctl_flags_bus .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y15_N26
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~9 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_in_lo~9_combout = ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q ))) # (!\z80_|pla_decode_|Equal47~0_combout )
|
|
|
|
.dataa(\z80_|pla_decode_|Equal47~0_combout ),
|
|
.datab(\z80_|sequencer_|DFFE_M4_ff~q ),
|
|
.datac(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datad(\z80_|sequencer_|M5~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_in_lo~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_in_lo~9 .lut_mask = 16'hF5F7;
|
|
defparam \z80_|execute_|ctl_reg_in_lo~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y18_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~0 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op1_oe~0_combout = ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ),
|
|
.datab(\z80_|execute_|ctl_66_oe~2_combout ),
|
|
.datac(\z80_|pla_decode_|Equal13~2_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op1_oe~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op1_oe~0 .lut_mask = 16'hFDDD;
|
|
defparam \z80_|execute_|ctl_alu_op1_oe~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y18_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_oe~1 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op1_oe~1_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_alu_op1_oe~0_combout ) # ((\z80_|nM1_int~2_combout & \z80_|execute_|ctl_alu_oe~1_combout )))
|
|
|
|
.dataa(\z80_|nM1_int~2_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_oe~1_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op1_oe~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op1_oe~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op1_oe~1 .lut_mask = 16'hFFF8;
|
|
defparam \z80_|execute_|ctl_alu_op1_oe~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y19_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~6 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_bs_oe~6_combout = ((!\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~9_combout & !\z80_|execute_|ctl_ir_we~15_combout ))) # (!\z80_|execute_|ctl_ir_we~4_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_ir_we~12_combout ),
|
|
.datab(\z80_|execute_|ctl_ir_we~4_combout ),
|
|
.datac(\z80_|execute_|ctl_ir_we~9_combout ),
|
|
.datad(\z80_|execute_|ctl_ir_we~15_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_bs_oe~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_bs_oe~6 .lut_mask = 16'h3337;
|
|
defparam \z80_|execute_|ctl_alu_bs_oe~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y19_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~12 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_bs_oe~12_combout = (\z80_|execute_|ctl_ir_we~11_combout & ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|sequencer_|DFFE_M4_ff~q ))))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datab(\z80_|execute_|ctl_ir_we~11_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_M4_ff~q ),
|
|
.datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_bs_oe~12_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_bs_oe~12 .lut_mask = 16'hCC40;
|
|
defparam \z80_|execute_|ctl_alu_bs_oe~12 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y19_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~8 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_bs_oe~8_combout = ((\z80_|execute_|ctl_alu_bs_oe~12_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~7_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~6_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_bs_oe~6_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_alu_bs_oe~12_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_bs_oe~7_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_bs_oe~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_bs_oe~8 .lut_mask = 16'hF5FF;
|
|
defparam \z80_|execute_|ctl_alu_bs_oe~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y19_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~9 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_bs_oe~9_combout = (\z80_|execute_|ctl_ir_we~7_combout & (((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # (\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_ir_we~7_combout & (\z80_|execute_|ctl_ir_we~10_combout
|
|
// & ((\z80_|execute_|ctl_ir_we~4_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_ir_we~10_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ),
|
|
.datac(\z80_|execute_|ctl_ir_we~7_combout ),
|
|
.datad(\z80_|execute_|ctl_ir_we~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_bs_oe~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_bs_oe~9 .lut_mask = 16'hFAC0;
|
|
defparam \z80_|execute_|ctl_alu_bs_oe~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y19_N18
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_bs_oe~combout = (\z80_|execute_|ctl_alu_bs_oe~8_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~9_combout ) # ((\z80_|execute_|ctl_ir_we~4_combout & \z80_|pla_decode_|Equal41~2_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_bs_oe~8_combout ),
|
|
.datab(\z80_|execute_|ctl_ir_we~4_combout ),
|
|
.datac(\z80_|pla_decode_|Equal41~2_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_bs_oe~9_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_bs_oe~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_bs_oe .lut_mask = 16'hFFEA;
|
|
defparam \z80_|execute_|ctl_alu_bs_oe .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y18_N6
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_oe~0 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op2_oe~0_combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # ((!\z80_|ir_|opcode [3] & \z80_|execute_|ixy_d~5_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_ir_we~4_combout ),
|
|
.datab(\z80_|ir_|opcode [3]),
|
|
.datac(\z80_|pla_decode_|Equal13~2_combout ),
|
|
.datad(\z80_|execute_|ixy_d~5_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op2_oe~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op2_oe~0 .lut_mask = 16'hB0A0;
|
|
defparam \z80_|execute_|ctl_alu_op2_oe~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y18_N12
|
|
cycloneive_lcell_comb \z80_|alu_|db_high[3]~0 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_high[3]~0_combout = (\z80_|execute_|ctl_alu_op1_oe~1_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~combout ) # ((\z80_|execute_|ctl_alu_op2_oe~0_combout ) # (!\z80_|execute_|ctl_alu_res_oe~3_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op1_oe~1_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_bs_oe~combout ),
|
|
.datac(\z80_|execute_|ctl_alu_res_oe~3_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op2_oe~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_high[3]~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_high[3]~0 .lut_mask = 16'hFFEF;
|
|
defparam \z80_|alu_|db_high[3]~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y19_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2~combout = (\z80_|pla_decode_|Equal1~5_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal13~1_combout & \z80_|pla_decode_|Equal13~0_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal1~5_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ),
|
|
.datac(\z80_|pla_decode_|Equal13~1_combout ),
|
|
.datad(\z80_|pla_decode_|Equal13~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y15_N28
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~15 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_shift_oe~15_combout = (!\z80_|pla_decode_|Equal33~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal6~0_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal33~1_combout ),
|
|
.datab(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal3~1_combout ),
|
|
.datad(\z80_|pla_decode_|Equal6~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_shift_oe~15_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~15 .lut_mask = 16'h4000;
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~15 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y18_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~38 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_shift_oe~38_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((!\z80_|execute_|ctl_state_alu~4_combout & !\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_mRead~4_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_state_alu~4_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~4_combout ),
|
|
.datac(\z80_|execute_|ctl_state_alu~2_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_shift_oe~15_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_shift_oe~38_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~38 .lut_mask = 16'h0037;
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~38 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y19_N28
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~28 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op_low~28_combout = (\z80_|pla_decode_|Equal1~5_combout & (\z80_|pla_decode_|Equal13~0_combout & (\z80_|pla_decode_|Equal13~1_combout & \z80_|execute_|ctl_eval_cond~0_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal1~5_combout ),
|
|
.datab(\z80_|pla_decode_|Equal13~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal13~1_combout ),
|
|
.datad(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op_low~28_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op_low~28 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|ctl_alu_op_low~28 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y19_N16
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~6 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op1_sel_bus~6_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2~combout & (!\z80_|execute_|ctl_alu_op1_sel_bus~16_combout & (\z80_|execute_|ctl_alu_shift_oe~38_combout & !\z80_|execute_|ctl_alu_op_low~28_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_hilo_pla83M1T3_2~combout ),
|
|
.datab(\z80_|execute_|ctl_alu_op1_sel_bus~16_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op_low~28_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .lut_mask = 16'h0010;
|
|
defparam \z80_|execute_|ctl_alu_op1_sel_bus~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y19_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~37 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_shift_oe~37_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_alu_oe~1_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & \z80_|execute_|ctl_ir_we~11_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ),
|
|
.datac(\z80_|execute_|ctl_ir_we~11_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_oe~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_shift_oe~37_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~37 .lut_mask = 16'hAA20;
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~37 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y19_N6
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~39 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_shift_oe~39_combout = ((\z80_|execute_|ctl_alu_shift_oe~37_combout ) # ((\z80_|execute_|ctl_state_alu~6_combout & \z80_|execute_|ctl_alu_shift_oe~14_combout ))) # (!\z80_|execute_|ctl_alu_op1_sel_bus~6_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_state_alu~6_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_shift_oe~37_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_shift_oe~39_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~39 .lut_mask = 16'hFBF3;
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~39 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y18_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_daa (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_cf2_sel_daa~combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal63~0_combout & (!\z80_|ir_|opcode [3] & !\z80_|ir_|opcode [4])))
|
|
|
|
.dataa(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.datab(\z80_|pla_decode_|Equal63~0_combout ),
|
|
.datac(\z80_|ir_|opcode [3]),
|
|
.datad(\z80_|ir_|opcode [4]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_cf2_sel_daa .lut_mask = 16'h0008;
|
|
defparam \z80_|execute_|ctl_flags_cf2_sel_daa .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y17_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~7 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op1_sel_bus~7_combout = (\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|ctl_ir_we~14_combout )))) # (!\z80_|execute_|ctl_ir_we~8_combout
|
|
// & (((!\z80_|execute_|ctl_mWrite~5_combout )) # (!\z80_|execute_|ctl_ir_we~14_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_ir_we~8_combout ),
|
|
.datab(\z80_|execute_|ctl_ir_we~14_combout ),
|
|
.datac(\z80_|execute_|ctl_mWrite~5_combout ),
|
|
.datad(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .lut_mask = 16'h153F;
|
|
defparam \z80_|execute_|ctl_alu_op1_sel_bus~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y17_N26
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~8 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op1_sel_bus~8_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~7_combout & (\z80_|execute_|ctl_flags_alu~17_combout & ((!\z80_|pla_decode_|Equal20~0_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op1_sel_bus~7_combout ),
|
|
.datab(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal20~0_combout ),
|
|
.datad(\z80_|execute_|ctl_flags_alu~17_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .lut_mask = 16'h2A00;
|
|
defparam \z80_|execute_|ctl_alu_op1_sel_bus~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y18_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~30 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op_low~30_combout = ((!\z80_|execute_|ixy_d~7_combout & ((\z80_|ir_|opcode [3]) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal13~2_combout )
|
|
|
|
.dataa(\z80_|pla_decode_|Equal13~2_combout ),
|
|
.datab(\z80_|execute_|ixy_d~7_combout ),
|
|
.datac(\z80_|execute_|ixy_d~6_combout ),
|
|
.datad(\z80_|ir_|opcode [3]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op_low~30_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op_low~30 .lut_mask = 16'h7757;
|
|
defparam \z80_|execute_|ctl_alu_op_low~30 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y18_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~31 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op_low~31_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (\z80_|execute_|ctl_alu_op1_sel_bus~8_combout & \z80_|execute_|ctl_alu_op_low~30_combout ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ),
|
|
.datac(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op_low~30_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op_low~31_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op_low~31 .lut_mask = 16'h3000;
|
|
defparam \z80_|execute_|ctl_alu_op_low~31 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y17_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_mRead~25 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mRead~25_combout = (\z80_|pla_decode_|Equal13~2_combout & \z80_|ir_|opcode [3])
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|pla_decode_|Equal13~2_combout ),
|
|
.datad(\z80_|ir_|opcode [3]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mRead~25_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mRead~25 .lut_mask = 16'hF000;
|
|
defparam \z80_|execute_|ctl_mRead~25 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y20_N24
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~40 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_shift_oe~40_combout = ((\z80_|execute_|ixy_d~9_combout & ((\z80_|execute_|ctl_mRead~25_combout ) # (\z80_|execute_|ctl_mRead~24_combout )))) # (!\z80_|execute_|ctl_flags_xy_we~21_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_mRead~25_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_xy_we~21_combout ),
|
|
.datac(\z80_|execute_|ixy_d~9_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~24_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_shift_oe~40_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~40 .lut_mask = 16'hF3B3;
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~40 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y20_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~42 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_shift_oe~42_combout = ((\z80_|execute_|ctl_alu_shift_oe~39_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~40_combout ) # (!\z80_|execute_|ctl_alu_op_low~31_combout ))) # (!\z80_|execute_|ctl_alu_shift_oe~46_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_shift_oe~46_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_shift_oe~39_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_op_low~31_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_shift_oe~40_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_shift_oe~42_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~42 .lut_mask = 16'hFFDF;
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~42 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y16_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout = (!\z80_|pla_decode_|Equal33~0_combout & (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal44~0_combout & !\z80_|sequencer_|DFFE_M1_ff~q )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal33~0_combout ),
|
|
.datab(\z80_|sequencer_|DFFE_T4_ff~q ),
|
|
.datac(\z80_|pla_decode_|Equal44~0_combout ),
|
|
.datad(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .lut_mask = 16'h0040;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y18_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op2_sel_bus~4_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~9_combout & (\z80_|execute_|ctl_state_alu~7_combout & (!\z80_|execute_|ctl_reg_gp_sel~7_combout & !\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ),
|
|
.datab(\z80_|execute_|ctl_state_alu~7_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_sel~7_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op2_sel_bus~4 .lut_mask = 16'h0008;
|
|
defparam \z80_|execute_|ctl_alu_op2_sel_bus~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y19_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~47 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_shift_oe~47_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|execute_|ctl_ir_we~7_combout & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|sequencer_|DFFE_M1_ff~q )))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.datab(\z80_|execute_|ctl_ir_we~7_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_M2_ff~q ),
|
|
.datad(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_shift_oe~47_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~47 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~47 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y19_N26
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~34 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_shift_oe~34_combout = (\z80_|execute_|ctl_ir_we~10_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ctl_alu_shift_oe~47_combout )))) #
|
|
// (!\z80_|execute_|ctl_ir_we~10_combout & (((\z80_|execute_|ctl_alu_shift_oe~47_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_ir_we~10_combout ),
|
|
.datab(\z80_|execute_|ctl_state_alu~4_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_shift_oe~47_combout ),
|
|
.datad(\z80_|execute_|ctl_ir_we~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_shift_oe~34_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~34 .lut_mask = 16'h50F8;
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~34 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y19_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~35 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_shift_oe~35_combout = (!\z80_|execute_|ctl_alu_bs_oe~8_combout & ((\z80_|execute_|ctl_alu_shift_oe~34_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & \z80_|execute_|ctl_ir_we~10_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_bs_oe~8_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_shift_oe~34_combout ),
|
|
.datac(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.datad(\z80_|execute_|ctl_ir_we~10_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_shift_oe~35_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~35 .lut_mask = 16'h5444;
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~35 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y19_N26
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~36 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_shift_oe~36_combout = (((\z80_|execute_|ctl_alu_shift_oe~35_combout ) # (!\z80_|execute_|ctl_flags_bus~9_combout )) # (!\z80_|execute_|ctl_reg_use_sp~1_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_use_sp~1_combout ),
|
|
.datac(\z80_|execute_|ctl_flags_bus~9_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_shift_oe~35_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_shift_oe~36_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~36 .lut_mask = 16'hFF7F;
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~36 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y16_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~28 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_shift_oe~28_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|ctl_ir_we~7_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_bus_db_oe~1_combout )))) # (!\z80_|execute_|ctl_state_alu~4_combout
|
|
// & (\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_bus_db_oe~1_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_state_alu~4_combout ),
|
|
.datab(\z80_|execute_|ixy_d~7_combout ),
|
|
.datac(\z80_|execute_|ctl_ir_we~7_combout ),
|
|
.datad(\z80_|execute_|ctl_bus_db_oe~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_shift_oe~28_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~28 .lut_mask = 16'hA0EC;
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~28 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y16_N16
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~44 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_shift_oe~44_combout = (!\z80_|execute_|ctl_alu_op_low~26_combout & (((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op_low~26_combout ),
|
|
.datab(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.datac(\z80_|sequencer_|DFFE_M3_ff~q ),
|
|
.datad(\z80_|execute_|ctl_mRead~34_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_shift_oe~44_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~44 .lut_mask = 16'h1555;
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~44 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y16_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~29 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_shift_oe~29_combout = (\z80_|execute_|ctl_alu_shift_oe~28_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~44_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~20_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_shift_oe~28_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_alu_shift_oe~20_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_shift_oe~44_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_shift_oe~29_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~29 .lut_mask = 16'hAFFF;
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~29 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y19_N26
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~16 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_shift_oe~16_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & \z80_|execute_|ixy_d~15_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datad(\z80_|execute_|ixy_d~15_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_shift_oe~16_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~16 .lut_mask = 16'h0F00;
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~16 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y19_N16
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~27 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_shift_oe~27_combout = (!\z80_|execute_|ctl_alu_bs_oe~combout & ((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ) # (\z80_|execute_|ctl_alu_shift_oe~16_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ),
|
|
.datab(\z80_|execute_|ctl_alu_bs_oe~combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ),
|
|
.datad(\z80_|execute_|ctl_alu_shift_oe~16_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_shift_oe~27_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~27 .lut_mask = 16'h3332;
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~27 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y19_N16
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_bs_oe~10 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_bs_oe~10_combout = ((\z80_|execute_|ctl_alu_bs_oe~9_combout ) # ((\z80_|execute_|ctl_alu_bs_oe~12_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~7_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~6_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_bs_oe~6_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_bs_oe~9_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_bs_oe~12_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_bs_oe~7_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_bs_oe~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_bs_oe~10 .lut_mask = 16'hFDFF;
|
|
defparam \z80_|execute_|ctl_alu_bs_oe~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y17_N28
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~31 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_shift_oe~31_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & (\z80_|execute_|ctl_sw_4u~1_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ),
|
|
.datab(\z80_|pla_decode_|Equal47~0_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ),
|
|
.datad(\z80_|execute_|ctl_sw_4u~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_shift_oe~31_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~31 .lut_mask = 16'h7000;
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~31 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y17_N2
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~30 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_shift_oe~30_combout = (\z80_|execute_|ctl_mWrite~5_combout & (!\z80_|execute_|ctl_mWrite~17_combout & ((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) #
|
|
// (!\z80_|execute_|ctl_mWrite~5_combout & (((!\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_mWrite~5_combout ),
|
|
.datab(\z80_|execute_|ctl_mWrite~17_combout ),
|
|
.datac(\z80_|execute_|ctl_state_alu~2_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~34_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_shift_oe~30_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~30 .lut_mask = 16'h0777;
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~30 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y17_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~32 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_shift_oe~32_combout = (\z80_|execute_|ctl_alu_shift_oe~31_combout & (\z80_|execute_|ctl_alu_shift_oe~30_combout & ((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_mRead~9_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_mRead~9_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_shift_oe~31_combout ),
|
|
.datac(\z80_|pla_decode_|Equal47~0_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_shift_oe~30_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_shift_oe~32_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~32 .lut_mask = 16'h4C00;
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~32 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y19_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~33 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_shift_oe~33_combout = (\z80_|execute_|ctl_alu_shift_oe~27_combout ) # ((!\z80_|execute_|ctl_alu_bs_oe~10_combout & ((\z80_|execute_|ctl_alu_shift_oe~29_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~32_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_shift_oe~29_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_shift_oe~27_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_bs_oe~10_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_shift_oe~32_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_shift_oe~33_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~33 .lut_mask = 16'hCECF;
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~33 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y20_N26
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~21 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_shift_oe~21_combout = (\z80_|execute_|ctl_ir_we~15_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((!\z80_|execute_|ctl_ir_we~4_combout & \z80_|execute_|ctl_state_alu~4_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_ir_we~15_combout ),
|
|
.datab(\z80_|execute_|ctl_ir_we~4_combout ),
|
|
.datac(\z80_|execute_|ctl_state_alu~4_combout ),
|
|
.datad(\z80_|execute_|ctl_state_alu~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_shift_oe~21_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~21 .lut_mask = 16'hAA20;
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~21 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y20_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~45 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_shift_oe~45_combout = (\z80_|execute_|ctl_alu_shift_oe~21_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|sequencer_|DFFE_T3_ff~q )))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.datab(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.datac(\z80_|execute_|ctl_alu_shift_oe~21_combout ),
|
|
.datad(\z80_|execute_|ctl_ir_we~15_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_shift_oe~45_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~45 .lut_mask = 16'hD0F0;
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~45 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y20_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~22 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_shift_oe~22_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_alu_shift_oe~45_combout ) # (\z80_|execute_|ctl_state_alu~4_combout )))) #
|
|
// (!\z80_|execute_|ctl_ir_we~9_combout & (\z80_|execute_|ctl_alu_shift_oe~45_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_shift_oe~45_combout ),
|
|
.datab(\z80_|execute_|ctl_ir_we~4_combout ),
|
|
.datac(\z80_|execute_|ctl_ir_we~9_combout ),
|
|
.datad(\z80_|execute_|ctl_state_alu~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_shift_oe~22_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~22 .lut_mask = 16'h3A2A;
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~22 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y20_N2
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~23 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_shift_oe~23_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_alu_shift_oe~22_combout ) # (\z80_|execute_|ctl_eval_cond~0_combout )))) #
|
|
// (!\z80_|execute_|ctl_ir_we~9_combout & (\z80_|execute_|ctl_alu_shift_oe~22_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_ir_we~9_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_shift_oe~22_combout ),
|
|
.datac(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_shift_oe~23_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~23 .lut_mask = 16'h44EC;
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~23 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y20_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~24 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_shift_oe~24_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mWrite~9_combout ) # (\z80_|execute_|ctl_alu_shift_oe~23_combout )))) #
|
|
// (!\z80_|execute_|ctl_ir_we~12_combout & (((\z80_|execute_|ctl_alu_shift_oe~23_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_ir_we~12_combout ),
|
|
.datab(\z80_|execute_|ctl_ir_we~4_combout ),
|
|
.datac(\z80_|execute_|ctl_mWrite~9_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_shift_oe~23_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_shift_oe~24_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~24 .lut_mask = 16'h7720;
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~24 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y20_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~25 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_shift_oe~25_combout = (\z80_|execute_|ctl_ir_we~12_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_alu_shift_oe~24_combout )))) #
|
|
// (!\z80_|execute_|ctl_ir_we~12_combout & (((\z80_|execute_|ctl_alu_shift_oe~24_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ),
|
|
.datab(\z80_|execute_|ctl_mWrite~5_combout ),
|
|
.datac(\z80_|execute_|ctl_ir_we~12_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_shift_oe~24_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_shift_oe~25_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~25 .lut_mask = 16'h5F40;
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~25 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y19_N6
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~26 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_shift_oe~26_combout = (!\z80_|execute_|ctl_alu_bs_oe~12_combout & ((\z80_|execute_|ctl_alu_shift_oe~25_combout ) # ((\z80_|execute_|ctl_mWrite~9_combout & \z80_|execute_|ctl_ir_we~11_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_mWrite~9_combout ),
|
|
.datab(\z80_|execute_|ctl_ir_we~11_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_shift_oe~25_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_bs_oe~12_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_shift_oe~26_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~26 .lut_mask = 16'h00F8;
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~26 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y19_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_shift_oe~43 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_shift_oe~43_combout = (\z80_|execute_|ctl_alu_shift_oe~42_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~36_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~33_combout ) # (\z80_|execute_|ctl_alu_shift_oe~26_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_shift_oe~42_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_shift_oe~36_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_shift_oe~33_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_shift_oe~26_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_shift_oe~43_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~43 .lut_mask = 16'hFFFE;
|
|
defparam \z80_|execute_|ctl_alu_shift_oe~43 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y19_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_low (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op1_sel_low~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|ir_|opcode [3]))))
|
|
|
|
.dataa(\z80_|execute_|ixy_d~7_combout ),
|
|
.datab(\z80_|execute_|ixy_d~9_combout ),
|
|
.datac(\z80_|pla_decode_|Equal13~2_combout ),
|
|
.datad(\z80_|ir_|opcode [3]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op1_sel_low~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op1_sel_low .lut_mask = 16'hC0E0;
|
|
defparam \z80_|execute_|ctl_alu_op1_sel_low .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y17_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero~5 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op1_sel_zero~5_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal63~0_combout & !\z80_|ir_|opcode [4])))
|
|
|
|
.dataa(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.datab(\z80_|ir_|opcode [3]),
|
|
.datac(\z80_|pla_decode_|Equal63~0_combout ),
|
|
.datad(\z80_|ir_|opcode [4]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .lut_mask = 16'h0080;
|
|
defparam \z80_|execute_|ctl_alu_op1_sel_zero~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y17_N6
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_zero (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op1_sel_zero~combout = (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~5_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ),
|
|
.datab(\z80_|execute_|ctl_66_oe~2_combout ),
|
|
.datac(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op1_sel_zero~5_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op1_sel_zero~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op1_sel_zero .lut_mask = 16'hFFFE;
|
|
defparam \z80_|execute_|ctl_alu_op1_sel_zero .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y17_N16
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~13 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op1_sel_bus~13_combout = (!\z80_|execute_|ctl_alu_op_low~26_combout & (((!\z80_|pla_decode_|Equal41~2_combout & !\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op_low~26_combout ),
|
|
.datab(\z80_|pla_decode_|Equal41~2_combout ),
|
|
.datac(\z80_|execute_|ctl_ir_we~4_combout ),
|
|
.datad(\z80_|execute_|ctl_ir_we~11_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .lut_mask = 16'h0515;
|
|
defparam \z80_|execute_|ctl_alu_op1_sel_bus~13 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y19_N18
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~17 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op1_sel_bus~17_combout = (\z80_|execute_|ctl_flags_xy_we~14_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|pla_decode_|Equal48~0_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal48~0_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_xy_we~14_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.datad(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op1_sel_bus~17_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op1_sel_bus~17 .lut_mask = 16'hCC4C;
|
|
defparam \z80_|execute_|ctl_alu_op1_sel_bus~17 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y19_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~14 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op1_sel_bus~14_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~13_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~17_combout & (\z80_|execute_|ctl_bus_db_oe~0_combout & \z80_|execute_|ctl_alu_op1_sel_bus~8_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op1_sel_bus~13_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_op1_sel_bus~17_combout ),
|
|
.datac(\z80_|execute_|ctl_bus_db_oe~0_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|ctl_alu_op1_sel_bus~14 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y20_N16
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~3 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_core_R~3_combout = (\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ctl_ir_we~15_combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )))) # (!\z80_|execute_|ctl_ir_we~9_combout
|
|
// & (((!\z80_|execute_|ctl_ir_we~15_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_ir_we~9_combout ),
|
|
.datab(\z80_|execute_|ctl_state_alu~2_combout ),
|
|
.datac(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.datad(\z80_|execute_|ctl_ir_we~15_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_core_R~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_core_R~3 .lut_mask = 16'h135F;
|
|
defparam \z80_|execute_|ctl_alu_core_R~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y20_N6
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_core_R~4_combout = (\z80_|execute_|ctl_alu_core_R~3_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~9_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_ir_we~15_combout ),
|
|
.datab(\z80_|execute_|ctl_state_alu~4_combout ),
|
|
.datac(\z80_|execute_|ctl_ir_we~9_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_core_R~3_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_core_R~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_core_R~4 .lut_mask = 16'h3700;
|
|
defparam \z80_|execute_|ctl_alu_core_R~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y19_N20
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cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 (
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// Equation(s):
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// \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|execute_|ctl_ir_we~11_combout & \z80_|sequencer_|DFFE_T4_ff~q ))
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.dataa(\z80_|sequencer_|DFFE_M1_ff~q ),
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.datab(\z80_|execute_|ctl_ir_we~11_combout ),
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|
.datac(gnd),
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|
.datad(\z80_|sequencer_|DFFE_T4_ff~q ),
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|
.cin(gnd),
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.combout(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ),
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|
.cout());
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|
// synopsys translate_off
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defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .lut_mask = 16'h4400;
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defparam \z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4 .sum_lutc_input = "datac";
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// synopsys translate_on
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// Location: LCCOMB_X24_Y20_N8
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cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~9 (
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|
// Equation(s):
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// \z80_|execute_|ctl_alu_op1_sel_bus~9_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_ir_we~10_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_ir_we~7_combout )))) #
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// (!\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_ir_we~7_combout ))))
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.dataa(\z80_|execute_|ctl_eval_cond~0_combout ),
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.datab(\z80_|execute_|ctl_ir_we~10_combout ),
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.datac(\z80_|execute_|ctl_ir_we~7_combout ),
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.datad(\z80_|execute_|ctl_state_alu~2_combout ),
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.cin(gnd),
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.combout(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ),
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.cout());
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// synopsys translate_off
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defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .lut_mask = 16'h0777;
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defparam \z80_|execute_|ctl_alu_op1_sel_bus~9 .sum_lutc_input = "datac";
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// synopsys translate_on
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// Location: LCCOMB_X23_Y19_N2
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cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~10 (
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// Equation(s):
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// \z80_|execute_|ctl_alu_op1_sel_bus~10_combout = (!\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout & (\z80_|execute_|ctl_flags_sz_we~0_combout & (\z80_|execute_|ctl_flags_alu~18_combout & \z80_|execute_|ctl_alu_op1_sel_bus~9_combout
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// )))
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.dataa(\z80_|execute_|ctl_reg_gp_hilo_nuse_ixiypla72npla55M1T4_4~combout ),
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.datab(\z80_|execute_|ctl_flags_sz_we~0_combout ),
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.datac(\z80_|execute_|ctl_flags_alu~18_combout ),
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.datad(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ),
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.cin(gnd),
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.combout(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ),
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.cout());
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// synopsys translate_off
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defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .lut_mask = 16'h4000;
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defparam \z80_|execute_|ctl_alu_op1_sel_bus~10 .sum_lutc_input = "datac";
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// synopsys translate_on
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// Location: LCCOMB_X27_Y20_N30
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cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~11 (
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// Equation(s):
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// \z80_|execute_|ctl_alu_op1_sel_bus~11_combout = (((\z80_|execute_|ctl_alu_oe~1_combout & \z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_core_R~4_combout )
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.dataa(\z80_|execute_|ctl_alu_oe~1_combout ),
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.datab(\z80_|execute_|ctl_eval_cond~0_combout ),
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.datac(\z80_|execute_|ctl_alu_core_R~4_combout ),
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.datad(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ),
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.cin(gnd),
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.combout(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ),
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.cout());
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// synopsys translate_off
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defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .lut_mask = 16'h8FFF;
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defparam \z80_|execute_|ctl_alu_op1_sel_bus~11 .sum_lutc_input = "datac";
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// synopsys translate_on
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// Location: LCCOMB_X30_Y19_N18
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cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~12 (
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// Equation(s):
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// \z80_|execute_|ctl_alu_op1_sel_bus~12_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ) # ((\z80_|execute_|ixy_d~15_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (\z80_|sequencer_|DFFE_T4_ff~q ))))
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.dataa(\z80_|execute_|ixy_d~15_combout ),
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.datab(\z80_|sequencer_|DFFE_T2_ff~q ),
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.datac(\z80_|sequencer_|DFFE_T4_ff~q ),
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.datad(\z80_|execute_|ctl_alu_op1_sel_bus~11_combout ),
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.cin(gnd),
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.combout(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ),
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.cout());
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// synopsys translate_off
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defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .lut_mask = 16'hFFA8;
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defparam \z80_|execute_|ctl_alu_op1_sel_bus~12 .sum_lutc_input = "datac";
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// synopsys translate_on
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// Location: LCCOMB_X30_Y19_N0
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cycloneive_lcell_comb \z80_|execute_|ctl_alu_op1_sel_bus~15 (
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// Equation(s):
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// \z80_|execute_|ctl_alu_op1_sel_bus~15_combout = ((\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~32_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ))) # (!\z80_|execute_|ctl_alu_op1_sel_bus~14_combout )
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.dataa(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ),
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.datab(\z80_|execute_|ctl_alu_op1_sel_bus~12_combout ),
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.datac(\z80_|execute_|ctl_alu_op1_sel_bus~6_combout ),
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.datad(\z80_|execute_|ctl_alu_shift_oe~32_combout ),
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.cin(gnd),
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.combout(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ),
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.cout());
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// synopsys translate_off
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defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .lut_mask = 16'hDFFF;
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defparam \z80_|execute_|ctl_alu_op1_sel_bus~15 .sum_lutc_input = "datac";
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// synopsys translate_on
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// Location: LCCOMB_X32_Y17_N6
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cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 (
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// Equation(s):
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// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & ((\z80_|alu_|db_low[3]~17_combout ) # ((!\z80_|alu_|db_high[3]~0_combout & !\z80_|execute_|ctl_alu_shift_oe~43_combout ))))
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.dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ),
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.datab(\z80_|alu_|db_high[3]~0_combout ),
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.datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ),
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.datad(\z80_|alu_|db_low[3]~17_combout ),
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.cin(gnd),
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.combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ),
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.cout());
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// synopsys translate_off
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defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .lut_mask = 16'hAA02;
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defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9 .sum_lutc_input = "datac";
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// synopsys translate_on
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// Location: LCCOMB_X32_Y17_N4
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cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~6 (
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// Equation(s):
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// \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~6_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & ((\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ) # ((\z80_|alu_|db_high[3]~7_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout ))))
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.dataa(\z80_|alu_|db_high[3]~7_combout ),
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.datab(\z80_|execute_|ctl_alu_op1_sel_low~combout ),
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.datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ),
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.datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~9_combout ),
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.cin(gnd),
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.combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~6_combout ),
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.cout());
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// synopsys translate_off
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defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~6 .lut_mask = 16'h0F08;
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defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[3]~6 .sum_lutc_input = "datac";
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// synopsys translate_on
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// Location: LCCOMB_X32_Y17_N30
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cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|ena (
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// Equation(s):
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// \z80_|alu_|b2v_op1_latch_mux_low|ena~combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~combout ) # (\z80_|execute_|ctl_alu_op1_sel_low~combout ))
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.dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ),
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.datab(gnd),
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.datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ),
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.datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ),
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.cin(gnd),
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.combout(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ),
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.cout());
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// synopsys translate_off
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defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .lut_mask = 16'hFFFA;
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defparam \z80_|alu_|b2v_op1_latch_mux_low|ena .sum_lutc_input = "datac";
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// synopsys translate_on
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// Location: FF_X32_Y17_N5
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dffeas \z80_|alu_|op1_low[3] (
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.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
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.d(\z80_|alu_|b2v_op1_latch_mux_low|Q[3]~6_combout ),
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.asdata(vcc),
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.clrn(vcc),
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.aload(gnd),
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.sclr(gnd),
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.sload(gnd),
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.ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ),
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.devclrn(devclrn),
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.devpor(devpor),
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.q(\z80_|alu_|op1_low [3]),
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.prn(vcc));
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// synopsys translate_off
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defparam \z80_|alu_|op1_low[3] .is_wysiwyg = "true";
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defparam \z80_|alu_|op1_low[3] .power_up = "low";
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// synopsys translate_on
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|
// Location: LCCOMB_X31_Y17_N4
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cycloneive_lcell_comb \z80_|alu_|db_low[3]~15 (
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|
// Equation(s):
|
|
// \z80_|alu_|db_low[3]~15_combout = (\z80_|execute_|ctl_alu_op2_oe~0_combout & (\z80_|alu_|op2_low [3] & ((\z80_|alu_|op1_low [3]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout & (((\z80_|alu_|op1_low [3]))
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// # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))
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.dataa(\z80_|execute_|ctl_alu_op2_oe~0_combout ),
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.datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ),
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.datac(\z80_|alu_|op2_low [3]),
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|
.datad(\z80_|alu_|op1_low [3]),
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|
.cin(gnd),
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|
.combout(\z80_|alu_|db_low[3]~15_combout ),
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|
.cout());
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|
// synopsys translate_off
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|
defparam \z80_|alu_|db_low[3]~15 .lut_mask = 16'hF531;
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defparam \z80_|alu_|db_low[3]~15 .sum_lutc_input = "datac";
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|
// synopsys translate_on
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|
|
// Location: LCCOMB_X30_Y17_N24
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cycloneive_lcell_comb \z80_|alu_|db_low[3]~16 (
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|
// Equation(s):
|
|
// \z80_|alu_|db_low[3]~16_combout = (\z80_|alu_|db_low[3]~15_combout & (((\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout & !\z80_|bus_control_|db[5]~15_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout )))
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.dataa(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ),
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.datab(\z80_|bus_control_|db[5]~15_combout ),
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|
.datac(\z80_|execute_|ctl_alu_bs_oe~combout ),
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.datad(\z80_|alu_|db_low[3]~15_combout ),
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|
.cin(gnd),
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|
.combout(\z80_|alu_|db_low[3]~16_combout ),
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|
.cout());
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|
// synopsys translate_off
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|
defparam \z80_|alu_|db_low[3]~16 .lut_mask = 16'h2F00;
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|
defparam \z80_|alu_|db_low[3]~16 .sum_lutc_input = "datac";
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|
// synopsys translate_on
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|
|
|
// Location: LCCOMB_X26_Y18_N16
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|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~33 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op_low~33_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_alu_op_low~24_combout ) # (\z80_|pla_decode_|Equal56~0_combout )))) # (!\z80_|execute_|ctl_state_alu~3_combout &
|
|
// (\z80_|execute_|ctl_mWrite~5_combout & ((\z80_|execute_|ctl_alu_op_low~24_combout ) # (\z80_|pla_decode_|Equal56~0_combout ))))
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.dataa(\z80_|execute_|ctl_state_alu~3_combout ),
|
|
.datab(\z80_|execute_|ctl_mWrite~5_combout ),
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|
.datac(\z80_|execute_|ctl_alu_op_low~24_combout ),
|
|
.datad(\z80_|pla_decode_|Equal56~0_combout ),
|
|
.cin(gnd),
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|
.combout(\z80_|execute_|ctl_alu_op_low~33_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op_low~33 .lut_mask = 16'hEEE0;
|
|
defparam \z80_|execute_|ctl_alu_op_low~33 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y20_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~34 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op_low~34_combout = (\z80_|execute_|ctl_alu_op_low~33_combout ) # (((\z80_|execute_|ctl_alu_op_low~28_combout ) # (!\z80_|execute_|ctl_alu_op2_sel_bus~4_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout ))
|
|
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.dataa(\z80_|execute_|ctl_alu_op_low~33_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_shift_oe~38_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op_low~28_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op_low~34_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op_low~34 .lut_mask = 16'hFFBF;
|
|
defparam \z80_|execute_|ctl_alu_op_low~34 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y19_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~48 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op_low~48_combout = (((!\z80_|sequencer_|DFFE_T4_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|execute_|ctl_alu_op_low~25_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q )
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T4_ff~q ),
|
|
.datab(\z80_|sequencer_|DFFE_M2_ff~q ),
|
|
.datac(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datad(\z80_|execute_|ctl_alu_op_low~25_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op_low~48_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op_low~48 .lut_mask = 16'h73FF;
|
|
defparam \z80_|execute_|ctl_alu_op_low~48 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y20_N16
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~35 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op_low~35_combout = (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # (((\z80_|execute_|ctl_alu_op_low~22_combout & \z80_|execute_|ctl_mWrite~17_combout )) # (!\z80_|execute_|ctl_alu_op_low~45_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_op_low~22_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_op_low~45_combout ),
|
|
.datad(\z80_|execute_|ctl_mWrite~17_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op_low~35_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op_low~35 .lut_mask = 16'hEFAF;
|
|
defparam \z80_|execute_|ctl_alu_op_low~35 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y20_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~36 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op_low~36_combout = (((\z80_|execute_|ctl_alu_op_low~35_combout ) # (!\z80_|execute_|ctl_alu_core_R~4_combout )) # (!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout )) # (!\z80_|execute_|ctl_alu_op_low~23_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op_low~23_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_core_R~4_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op_low~35_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op_low~36_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op_low~36 .lut_mask = 16'hFF7F;
|
|
defparam \z80_|execute_|ctl_alu_op_low~36 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y20_N26
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~37 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op_low~37_combout = (\z80_|execute_|ctl_alu_op_low~34_combout ) # (((\z80_|execute_|ctl_alu_op_low~36_combout ) # (!\z80_|execute_|ctl_alu_op_low~48_combout )) # (!\z80_|execute_|ctl_alu_op_low~31_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op_low~34_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_op_low~31_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_op_low~48_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op_low~36_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op_low~37_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op_low~37 .lut_mask = 16'hFFBF;
|
|
defparam \z80_|execute_|ctl_alu_op_low~37 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y19_N26
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout = (\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal21~1_combout & !\z80_|sequencer_|DFFE_M1_ff~q ))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T4_ff~q ),
|
|
.datab(\z80_|pla_decode_|Equal21~1_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .lut_mask = 16'h0088;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y20_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~38 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op_low~38_combout = (\z80_|execute_|ixy_d~5_combout & (((\z80_|execute_|ctl_mRead~34_combout ) # (\z80_|pla_decode_|Equal39~0_combout )))) # (!\z80_|execute_|ixy_d~5_combout & (\z80_|execute_|ctl_eval_cond~0_combout &
|
|
// (\z80_|execute_|ctl_mRead~34_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.datab(\z80_|execute_|ixy_d~5_combout ),
|
|
.datac(\z80_|execute_|ctl_mRead~34_combout ),
|
|
.datad(\z80_|pla_decode_|Equal39~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op_low~38_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op_low~38 .lut_mask = 16'hECE0;
|
|
defparam \z80_|execute_|ctl_alu_op_low~38 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y18_N26
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~39 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op_low~39_combout = (\z80_|execute_|ixy_d~9_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # ((\z80_|pla_decode_|Equal40~1_combout )))) # (!\z80_|execute_|ixy_d~9_combout & (((\z80_|execute_|ixy_d~5_combout &
|
|
// \z80_|pla_decode_|Equal40~1_combout ))))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal39~0_combout ),
|
|
.datab(\z80_|execute_|ixy_d~9_combout ),
|
|
.datac(\z80_|execute_|ixy_d~5_combout ),
|
|
.datad(\z80_|pla_decode_|Equal40~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op_low~39_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op_low~39 .lut_mask = 16'hFC88;
|
|
defparam \z80_|execute_|ctl_alu_op_low~39 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y20_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~40 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op_low~40_combout = (\z80_|execute_|ctl_alu_op_low~37_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # ((\z80_|execute_|ctl_alu_op_low~38_combout ) # (\z80_|execute_|ctl_alu_op_low~39_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op_low~37_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ),
|
|
.datac(\z80_|execute_|ctl_alu_op_low~38_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op_low~39_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op_low~40_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op_low~40 .lut_mask = 16'hFFFE;
|
|
defparam \z80_|execute_|ctl_alu_op_low~40 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y16_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~41 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op_low~41_combout = (\z80_|execute_|ctl_alu_op_low~40_combout ) # ((\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ixy_d~9_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ixy_d~5_combout ),
|
|
.datab(\z80_|pla_decode_|Equal21~1_combout ),
|
|
.datac(\z80_|execute_|ixy_d~9_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op_low~40_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op_low~41_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op_low~41 .lut_mask = 16'hFFC8;
|
|
defparam \z80_|execute_|ctl_alu_op_low~41 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y16_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op_low~combout = (\z80_|execute_|ctl_alu_op_low~41_combout ) # ((\z80_|execute_|ixy_d~15_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q ))))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T4_ff~q ),
|
|
.datab(\z80_|execute_|ctl_alu_op_low~41_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.datad(\z80_|execute_|ixy_d~15_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op_low~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op_low .lut_mask = 16'hFECC;
|
|
defparam \z80_|execute_|ctl_alu_op_low .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X31_Y16_N25
|
|
dffeas \z80_|alu_|result_lo[3] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|execute_|ctl_alu_op_low~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|alu_|result_lo [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|result_lo[3] .is_wysiwyg = "true";
|
|
defparam \z80_|alu_|result_lo[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y18_N2
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~5 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_oe~5_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout & (!\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|pla_decode_|Equal20~0_combout ))))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal20~0_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ),
|
|
.datac(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ),
|
|
.datad(\z80_|nM1_int~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_oe~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_oe~5 .lut_mask = 16'h0103;
|
|
defparam \z80_|execute_|ctl_alu_oe~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y20_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~6 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_oe~6_combout = (\z80_|execute_|ctl_alu_oe~5_combout & (((!\z80_|execute_|ctl_mRead~24_combout & !\z80_|execute_|ctl_mRead~25_combout )) # (!\z80_|nM1_int~2_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_mRead~24_combout ),
|
|
.datab(\z80_|nM1_int~2_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_oe~5_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~25_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_oe~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_oe~6 .lut_mask = 16'h3070;
|
|
defparam \z80_|execute_|ctl_alu_oe~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y20_N18
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~9 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_oe~9_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_mWrite~17_combout ) # ((\z80_|execute_|ctl_alu_oe~1_combout ) # (\z80_|pla_decode_|Equal69~0_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_mWrite~17_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_oe~1_combout ),
|
|
.datac(\z80_|pla_decode_|Equal69~0_combout ),
|
|
.datad(\z80_|nM1_int~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_oe~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_oe~9 .lut_mask = 16'hFE00;
|
|
defparam \z80_|execute_|ctl_alu_oe~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y20_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~12 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_core_S~12_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # ((\z80_|sequencer_|DFFE_T1_ff~q ) # ((!\z80_|execute_|ctl_ir_we~12_combout & !\z80_|execute_|ctl_ir_we~11_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_ir_we~12_combout ),
|
|
.datab(\z80_|execute_|ctl_ir_we~11_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.datad(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_core_S~12_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_core_S~12 .lut_mask = 16'hFFF1;
|
|
defparam \z80_|execute_|ctl_alu_core_S~12 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y20_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~10 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_oe~10_combout = ((\z80_|execute_|ctl_alu_oe~9_combout ) # ((!\z80_|execute_|ctl_alu_core_S~12_combout ) # (!\z80_|execute_|ctl_alu_oe~4_combout ))) # (!\z80_|execute_|ctl_alu_oe~6_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_oe~6_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_oe~9_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_oe~4_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_core_S~12_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_oe~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_oe~10 .lut_mask = 16'hDFFF;
|
|
defparam \z80_|execute_|ctl_alu_oe~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y18_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_oe~2_combout = ((!\z80_|execute_|ctl_alu_op_low~25_combout & (!\z80_|execute_|ctl_alu_op_low~24_combout & !\z80_|pla_decode_|Equal56~0_combout ))) # (!\z80_|execute_|ixy_d~7_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op_low~25_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_op_low~24_combout ),
|
|
.datac(\z80_|execute_|ixy_d~7_combout ),
|
|
.datad(\z80_|pla_decode_|Equal56~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_oe~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_oe~2 .lut_mask = 16'h0F1F;
|
|
defparam \z80_|execute_|ctl_alu_oe~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y16_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout = (!\z80_|pla_decode_|Equal33~1_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|nM1_int~2_combout & \z80_|pla_decode_|Equal6~0_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal33~1_combout ),
|
|
.datab(\z80_|pla_decode_|Equal3~1_combout ),
|
|
.datac(\z80_|nM1_int~2_combout ),
|
|
.datad(\z80_|pla_decode_|Equal6~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .lut_mask = 16'h4000;
|
|
defparam \z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y14_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~15 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo[1]~15_combout = ((!\z80_|execute_|ctl_ir_we~9_combout & (!\z80_|execute_|ctl_ir_we~8_combout & !\z80_|execute_|ctl_ir_we~10_combout ))) # (!\z80_|nM1_int~2_combout )
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|
|
|
.dataa(\z80_|execute_|ctl_ir_we~9_combout ),
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|
.datab(\z80_|execute_|ctl_ir_we~8_combout ),
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|
.datac(\z80_|execute_|ctl_ir_we~10_combout ),
|
|
.datad(\z80_|nM1_int~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~15 .lut_mask = 16'h01FF;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~15 .sum_lutc_input = "datac";
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|
// synopsys translate_on
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|
|
|
// Location: LCCOMB_X29_Y15_N30
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|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~8 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_in_hi~8_combout = (!\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout & \z80_|execute_|ctl_flags_sz_we~1_combout )))
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|
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|
.dataa(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ),
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|
.datab(\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ),
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|
.datac(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ),
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|
.datad(\z80_|execute_|ctl_flags_sz_we~1_combout ),
|
|
.cin(gnd),
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|
.combout(\z80_|execute_|ctl_reg_in_hi~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_in_hi~8 .lut_mask = 16'h0400;
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|
defparam \z80_|execute_|ctl_reg_in_hi~8 .sum_lutc_input = "datac";
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|
// synopsys translate_on
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|
|
|
// Location: LCCOMB_X28_Y18_N6
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cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~7 (
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|
// Equation(s):
|
|
// \z80_|reg_control_|reg_sys_we_lo~7_combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q )))
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|
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.dataa(\z80_|sequencer_|DFFE_T3_ff~q ),
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|
.datab(\z80_|reg_control_|reg_sys_we_lo~6_combout ),
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|
.datac(\z80_|execute_|ixy_d~15_combout ),
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|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_control_|reg_sys_we_lo~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
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|
defparam \z80_|reg_control_|reg_sys_we_lo~7 .lut_mask = 16'h4C4C;
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|
defparam \z80_|reg_control_|reg_sys_we_lo~7 .sum_lutc_input = "datac";
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|
// synopsys translate_on
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|
|
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// Location: LCCOMB_X28_Y14_N26
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cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~7 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_oe~7_combout = (\z80_|execute_|ctl_reg_in_hi~8_combout & (\z80_|reg_control_|reg_sys_we_lo~7_combout & ((!\z80_|pla_decode_|Equal13~2_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout ))))
|
|
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.dataa(\z80_|execute_|ctl_ir_we~4_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_in_hi~8_combout ),
|
|
.datac(\z80_|pla_decode_|Equal13~2_combout ),
|
|
.datad(\z80_|reg_control_|reg_sys_we_lo~7_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_oe~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_oe~7 .lut_mask = 16'h4C00;
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|
defparam \z80_|execute_|ctl_alu_oe~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
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|
|
|
// Location: LCCOMB_X24_Y17_N8
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|
cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~11 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mWrite~11_combout = (\z80_|execute_|ctl_flags_use_cf2~13_combout & (((!\z80_|execute_|ctl_ir_we~15_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_mWrite~5_combout )))
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|
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.dataa(\z80_|execute_|ctl_mWrite~5_combout ),
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|
.datab(\z80_|execute_|ctl_ir_we~15_combout ),
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|
.datac(\z80_|execute_|ctl_ir_we~7_combout ),
|
|
.datad(\z80_|execute_|ctl_flags_use_cf2~13_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mWrite~11_combout ),
|
|
.cout());
|
|
// synopsys translate_off
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|
defparam \z80_|execute_|ctl_mWrite~11 .lut_mask = 16'h5700;
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|
defparam \z80_|execute_|ctl_mWrite~11 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
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|
|
|
// Location: LCCOMB_X28_Y17_N28
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|
cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~5 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_bus_db_we~5_combout = (\z80_|execute_|ctl_bus_inc_oe~28_combout & (\z80_|execute_|ctl_mWrite~11_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~24_combout ))))
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|
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|
.dataa(\z80_|execute_|ctl_bus_inc_oe~28_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~24_combout ),
|
|
.datac(\z80_|execute_|ixy_d~5_combout ),
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|
.datad(\z80_|execute_|ctl_mWrite~11_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_bus_db_we~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_bus_db_we~5 .lut_mask = 16'h2A00;
|
|
defparam \z80_|execute_|ctl_bus_db_we~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y14_N16
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|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~8 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_oe~8_combout = (\z80_|execute_|ctl_reg_in_lo~9_combout & (\z80_|execute_|ctl_alu_oe~2_combout & (\z80_|execute_|ctl_alu_oe~7_combout & \z80_|execute_|ctl_bus_db_we~5_combout )))
|
|
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|
.dataa(\z80_|execute_|ctl_reg_in_lo~9_combout ),
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|
.datab(\z80_|execute_|ctl_alu_oe~2_combout ),
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|
.datac(\z80_|execute_|ctl_alu_oe~7_combout ),
|
|
.datad(\z80_|execute_|ctl_bus_db_we~5_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_oe~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_oe~8 .lut_mask = 16'h8000;
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|
defparam \z80_|execute_|ctl_alu_oe~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y18_N10
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|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_alu~16 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_alu~16_combout = (\z80_|execute_|ctl_flags_alu~10_combout & (!\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout & (\z80_|execute_|ctl_flags_xy_we~10_combout & !\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout )))
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|
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|
.dataa(\z80_|execute_|ctl_flags_alu~10_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ),
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|
.datac(\z80_|execute_|ctl_flags_xy_we~10_combout ),
|
|
.datad(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_alu~16_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_alu~16 .lut_mask = 16'h0020;
|
|
defparam \z80_|execute_|ctl_flags_alu~16 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y14_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_oe~11 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_oe~11_combout = (\z80_|execute_|ctl_alu_oe~10_combout ) # (((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|execute_|ctl_flags_alu~16_combout )) # (!\z80_|execute_|ctl_alu_oe~8_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_oe~10_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_oe~8_combout ),
|
|
.datac(\z80_|execute_|ctl_flags_alu~16_combout ),
|
|
.datad(\z80_|execute_|ctl_66_oe~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_oe~11_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_oe~11 .lut_mask = 16'hFFBF;
|
|
defparam \z80_|execute_|ctl_alu_oe~11 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y19_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~48 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo[1]~48_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|pla_decode_|Equal21~1_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal21~1_combout ),
|
|
.datab(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ),
|
|
.datad(\z80_|sequencer_|DFFE_T4_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .lut_mask = 16'hD0F0;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~48 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y15_N26
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~8 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_out_hi~8_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_ir_we~12_combout ) # (!\z80_|execute_|nextM~2_combout ))))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.datab(\z80_|execute_|nextM~2_combout ),
|
|
.datac(\z80_|execute_|ctl_ir_we~12_combout ),
|
|
.datad(\z80_|sequencer_|DFFE_M2_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_out_hi~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_out_hi~8 .lut_mask = 16'hA200;
|
|
defparam \z80_|execute_|ctl_reg_out_hi~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y15_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~5 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_out_hi~5_combout = (\z80_|execute_|ctl_reg_out_lo~2_combout & (\z80_|execute_|rsel3~combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|execute_|ctl_mRead~3_combout )))) # (!\z80_|execute_|ctl_reg_out_lo~2_combout &
|
|
// (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~3_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_out_lo~2_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~3_combout ),
|
|
.datac(\z80_|execute_|ixy_d~7_combout ),
|
|
.datad(\z80_|execute_|rsel3~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_out_hi~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_out_hi~5 .lut_mask = 16'h3F15;
|
|
defparam \z80_|execute_|ctl_reg_out_hi~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y15_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_sw_2u~2_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (!\z80_|execute_|ctl_mWrite~8_combout & ((!\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_eval_cond~0_combout &
|
|
// (((!\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.datab(\z80_|execute_|ctl_mWrite~8_combout ),
|
|
.datac(\z80_|execute_|ctl_ir_we~4_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~7_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_sw_2u~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_sw_2u~2 .lut_mask = 16'h0777;
|
|
defparam \z80_|execute_|ctl_sw_2u~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y15_N16
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~0 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_sw_2u~0_combout = (\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|execute_|ctl_mWrite~6_combout & ((!\z80_|pla_decode_|Equal9~1_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_state_alu~3_combout &
|
|
// (((!\z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_state_alu~3_combout ),
|
|
.datab(\z80_|execute_|ctl_ir_we~4_combout ),
|
|
.datac(\z80_|pla_decode_|Equal9~1_combout ),
|
|
.datad(\z80_|execute_|ctl_mWrite~6_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_sw_2u~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_sw_2u~0 .lut_mask = 16'h153F;
|
|
defparam \z80_|execute_|ctl_sw_2u~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y15_N26
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~3 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_sw_2u~3_combout = (\z80_|execute_|ctl_sw_2u~2_combout & (\z80_|execute_|ctl_sw_2u~0_combout & ((!\z80_|execute_|ctl_mRead~6_combout ) # (!\z80_|execute_|ctl_alu_oe~0_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_oe~0_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~6_combout ),
|
|
.datac(\z80_|execute_|ctl_sw_2u~2_combout ),
|
|
.datad(\z80_|execute_|ctl_sw_2u~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_sw_2u~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_sw_2u~3 .lut_mask = 16'h7000;
|
|
defparam \z80_|execute_|ctl_sw_2u~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y15_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~47 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo[1]~47_combout = (\z80_|execute_|ctl_sw_2u~3_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|sequencer_|M5~q )))
|
|
|
|
.dataa(\z80_|sequencer_|M5~q ),
|
|
.datab(\z80_|execute_|ctl_sw_2u~3_combout ),
|
|
.datac(\z80_|execute_|ctl_mRead~8_combout ),
|
|
.datad(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .lut_mask = 16'hCC4C;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~47 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y18_N16
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~33 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~33_combout = (\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ctl_state_alu~3_combout &
|
|
// (((!\z80_|execute_|ctl_ir_we~4_combout )) # (!\z80_|pla_decode_|Equal34~0_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_state_alu~3_combout ),
|
|
.datab(\z80_|pla_decode_|Equal34~0_combout ),
|
|
.datac(\z80_|execute_|ctl_ir_we~4_combout ),
|
|
.datad(\z80_|pla_decode_|Equal47~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~33_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~33 .lut_mask = 16'h153F;
|
|
defparam \z80_|execute_|ctl_inc_cy~33 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y18_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~37 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_hilo[1]~37_combout = (\z80_|execute_|ctl_inc_cy~33_combout & (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_M4_ff~q ),
|
|
.datab(\z80_|pla_decode_|Equal19~0_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datad(\z80_|execute_|ctl_inc_cy~33_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~37 .lut_mask = 16'hF700;
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~37 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y15_N16
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~6 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_sw_2u~6_combout = (\z80_|execute_|ctl_reg_gp_sel~7_combout & (\z80_|ir_|opcode [0] $ ((!\z80_|execute_|comb~0_combout )))) # (!\z80_|execute_|ctl_reg_gp_sel~7_combout & (!\z80_|execute_|ctl_sw_2u~5_combout & (\z80_|ir_|opcode [0] $
|
|
// (!\z80_|execute_|comb~0_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_sel~7_combout ),
|
|
.datab(\z80_|ir_|opcode [0]),
|
|
.datac(\z80_|execute_|comb~0_combout ),
|
|
.datad(\z80_|execute_|ctl_sw_2u~5_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_sw_2u~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_sw_2u~6 .lut_mask = 16'h82C3;
|
|
defparam \z80_|execute_|ctl_sw_2u~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y15_N16
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~6 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_out_hi~6_combout = (\z80_|execute_|ctl_reg_out_hi~5_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout & !\z80_|execute_|ctl_sw_2u~6_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_out_hi~5_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout ),
|
|
.datad(\z80_|execute_|ctl_sw_2u~6_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_out_hi~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_out_hi~6 .lut_mask = 16'h0080;
|
|
defparam \z80_|execute_|ctl_reg_out_hi~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y15_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_hi~7 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_out_hi~7_combout = (((\z80_|execute_|ctl_reg_out_hi~8_combout ) # (!\z80_|execute_|ctl_reg_out_hi~6_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_out_hi~4_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_out_hi~8_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_out_hi~6_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_out_hi~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_out_hi~7 .lut_mask = 16'hF7FF;
|
|
defparam \z80_|execute_|ctl_reg_out_hi~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y17_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_mRead~2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mRead~2_combout = (\z80_|pla_decode_|Equal3~0_combout & (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal2~0_combout & !\z80_|ir_|opcode [5])))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal3~0_combout ),
|
|
.datab(\z80_|pla_decode_|Equal1~7_combout ),
|
|
.datac(\z80_|pla_decode_|Equal2~0_combout ),
|
|
.datad(\z80_|ir_|opcode [5]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mRead~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mRead~2 .lut_mask = 16'h0080;
|
|
defparam \z80_|execute_|ctl_mRead~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y18_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~6 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_sw_2d~6_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ixy_d~6_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout &
|
|
// (((!\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|pla_decode_|Equal47~0_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal9~1_combout ),
|
|
.datab(\z80_|pla_decode_|Equal47~0_combout ),
|
|
.datac(\z80_|execute_|ctl_mRead~9_combout ),
|
|
.datad(\z80_|execute_|ixy_d~6_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_sw_2d~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_sw_2d~6 .lut_mask = 16'h153F;
|
|
defparam \z80_|execute_|ctl_sw_2d~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y16_N2
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~7 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_sw_2d~7_combout = (\z80_|execute_|ctl_sw_2d~6_combout & (((!\z80_|execute_|ctl_mRead~2_combout & !\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|nM1_int~2_combout )))
|
|
|
|
.dataa(\z80_|nM1_int~2_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~2_combout ),
|
|
.datac(\z80_|pla_decode_|Equal6~1_combout ),
|
|
.datad(\z80_|execute_|ctl_sw_2d~6_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_sw_2d~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_sw_2d~7 .lut_mask = 16'h5700;
|
|
defparam \z80_|execute_|ctl_sw_2d~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y17_N28
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout = (\z80_|nM1_int~2_combout & (\z80_|pla_decode_|Equal1~4_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [0])))
|
|
|
|
.dataa(\z80_|nM1_int~2_combout ),
|
|
.datab(\z80_|pla_decode_|Equal1~4_combout ),
|
|
.datac(\z80_|pla_decode_|Equal13~0_combout ),
|
|
.datad(\z80_|ir_|opcode [0]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .lut_mask = 16'h0080;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y16_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~8 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_sw_2d~8_combout = (\z80_|execute_|ctl_flags_sz_we~0_combout & (\z80_|execute_|ctl_sw_2d~7_combout & (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & \z80_|execute_|ctl_alu_shift_oe~44_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ),
|
|
.datab(\z80_|execute_|ctl_sw_2d~7_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ),
|
|
.datad(\z80_|execute_|ctl_alu_shift_oe~44_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_sw_2d~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_sw_2d~8 .lut_mask = 16'h0800;
|
|
defparam \z80_|execute_|ctl_sw_2d~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y20_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~7 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_bus_db_oe~7_combout = (\z80_|execute_|ctl_flags_alu~19_combout & (((!\z80_|execute_|ctl_mRead~25_combout & !\z80_|execute_|ctl_mRead~24_combout )) # (!\z80_|execute_|ixy_d~9_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_mRead~25_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_alu~19_combout ),
|
|
.datac(\z80_|execute_|ixy_d~9_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~24_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_bus_db_oe~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_bus_db_oe~7 .lut_mask = 16'h0C4C;
|
|
defparam \z80_|execute_|ctl_bus_db_oe~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y16_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~5 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_sw_2d~5_combout = (\z80_|execute_|ctl_bus_db_oe~7_combout & (((!\z80_|pla_decode_|Equal13~2_combout & \z80_|execute_|ctl_bus_db_oe~1_combout )) # (!\z80_|execute_|ixy_d~7_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal13~2_combout ),
|
|
.datab(\z80_|execute_|ctl_bus_db_oe~7_combout ),
|
|
.datac(\z80_|execute_|ixy_d~7_combout ),
|
|
.datad(\z80_|execute_|ctl_bus_db_oe~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_sw_2d~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_sw_2d~5 .lut_mask = 16'h4C0C;
|
|
defparam \z80_|execute_|ctl_sw_2d~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y16_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_mRead~19 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mRead~19_combout = (\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|pla_decode_|Equal9~1_combout ) # ((!\z80_|pla_decode_|Equal12~1_combout & \z80_|pla_decode_|Equal25~0_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal12~1_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~15_combout ),
|
|
.datac(\z80_|pla_decode_|Equal9~1_combout ),
|
|
.datad(\z80_|pla_decode_|Equal25~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mRead~19_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mRead~19 .lut_mask = 16'hFDFC;
|
|
defparam \z80_|execute_|ctl_mRead~19 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y16_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_mRead~18 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mRead~18_combout = (\z80_|execute_|ctl_mRead~8_combout ) # ((\z80_|execute_|ctl_mRead~13_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # (\z80_|execute_|ctl_mRead~6_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_mRead~8_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~13_combout ),
|
|
.datac(\z80_|execute_|ctl_mRead~7_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~6_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mRead~18_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mRead~18 .lut_mask = 16'hFFFE;
|
|
defparam \z80_|execute_|ctl_mRead~18 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y13_N26
|
|
cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~2 (
|
|
// Equation(s):
|
|
// \z80_|reg_control_|reg_sys_we_lo~2_combout = (\z80_|pla_decode_|Equal35~0_combout ) # ((\z80_|pla_decode_|Equal34~0_combout ) # ((\z80_|pla_decode_|Equal37~0_combout ) # (\z80_|pla_decode_|Equal38~2_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal35~0_combout ),
|
|
.datab(\z80_|pla_decode_|Equal34~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal37~0_combout ),
|
|
.datad(\z80_|pla_decode_|Equal38~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_control_|reg_sys_we_lo~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_control_|reg_sys_we_lo~2 .lut_mask = 16'hFFFE;
|
|
defparam \z80_|reg_control_|reg_sys_we_lo~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y17_N2
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal24~1 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal24~1_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal9~0_combout )))
|
|
|
|
.dataa(\z80_|ir_|opcode [5]),
|
|
.datab(\z80_|pla_decode_|Equal2~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal1~7_combout ),
|
|
.datad(\z80_|pla_decode_|Equal9~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal24~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal24~1 .lut_mask = 16'h4000;
|
|
defparam \z80_|pla_decode_|Equal24~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y13_N12
|
|
cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~3 (
|
|
// Equation(s):
|
|
// \z80_|reg_control_|reg_sys_we_lo~3_combout = (\z80_|pla_decode_|Equal29~0_combout ) # ((\z80_|pla_decode_|Equal19~0_combout ) # ((\z80_|reg_control_|reg_sys_we_lo~2_combout ) # (\z80_|pla_decode_|Equal24~1_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal29~0_combout ),
|
|
.datab(\z80_|pla_decode_|Equal19~0_combout ),
|
|
.datac(\z80_|reg_control_|reg_sys_we_lo~2_combout ),
|
|
.datad(\z80_|pla_decode_|Equal24~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_control_|reg_sys_we_lo~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_control_|reg_sys_we_lo~3 .lut_mask = 16'hFFFE;
|
|
defparam \z80_|reg_control_|reg_sys_we_lo~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y18_N2
|
|
cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo~4 (
|
|
// Equation(s):
|
|
// \z80_|reg_control_|reg_sys_we_lo~4_combout = (\z80_|reg_control_|reg_sys_we_lo~3_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) #
|
|
// (!\z80_|reg_control_|reg_sys_we_lo~3_combout & (((!\z80_|execute_|ctl_state_alu~4_combout )) # (!\z80_|pla_decode_|Equal47~0_combout )))
|
|
|
|
.dataa(\z80_|reg_control_|reg_sys_we_lo~3_combout ),
|
|
.datab(\z80_|pla_decode_|Equal47~0_combout ),
|
|
.datac(\z80_|execute_|ctl_state_alu~2_combout ),
|
|
.datad(\z80_|execute_|ctl_state_alu~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_control_|reg_sys_we_lo~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_control_|reg_sys_we_lo~4 .lut_mask = 16'h135F;
|
|
defparam \z80_|reg_control_|reg_sys_we_lo~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y15_N24
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_mRead~20 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mRead~20_combout = (\z80_|reg_control_|reg_sys_we_lo~4_combout & (((!\z80_|execute_|ctl_mRead~19_combout & !\z80_|execute_|ctl_mRead~18_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_mRead~19_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~18_combout ),
|
|
.datac(\z80_|execute_|ctl_state_alu~2_combout ),
|
|
.datad(\z80_|reg_control_|reg_sys_we_lo~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mRead~20_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mRead~20 .lut_mask = 16'h1F00;
|
|
defparam \z80_|execute_|ctl_mRead~20 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y13_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~5 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_in_hi~5_combout = ((!\z80_|execute_|ctl_mRead~13_combout & (!\z80_|execute_|ctl_mRead~15_combout & !\z80_|execute_|ctl_mRead~16_combout ))) # (!\z80_|execute_|ixy_d~6_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_mRead~13_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~15_combout ),
|
|
.datac(\z80_|execute_|ixy_d~6_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~16_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_in_hi~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_in_hi~5 .lut_mask = 16'h0F1F;
|
|
defparam \z80_|execute_|ctl_reg_in_hi~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y17_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_mRead~22 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mRead~22_combout = (\z80_|execute_|ctl_mRead~20_combout & (\z80_|execute_|ctl_reg_in_hi~5_combout & ((!\z80_|execute_|ctl_mRead~16_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_state_alu~4_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~20_combout ),
|
|
.datac(\z80_|execute_|ctl_mRead~16_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_in_hi~5_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mRead~22_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mRead~22 .lut_mask = 16'h4C00;
|
|
defparam \z80_|execute_|ctl_mRead~22 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y16_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout = (\z80_|execute_|ixy_d~6_combout & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal52~0_combout & !\z80_|ir_|opcode [0])))
|
|
|
|
.dataa(\z80_|execute_|ixy_d~6_combout ),
|
|
.datab(\z80_|pla_decode_|Equal3~1_combout ),
|
|
.datac(\z80_|pla_decode_|Equal52~0_combout ),
|
|
.datad(\z80_|ir_|opcode [0]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .lut_mask = 16'h0080;
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y12_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~6 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_in_hi~6_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ixy_d~6_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal35~0_combout ),
|
|
.datab(\z80_|execute_|ixy_d~6_combout ),
|
|
.datac(\z80_|pla_decode_|Equal19~0_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_in_hi~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_in_hi~6 .lut_mask = 16'h0037;
|
|
defparam \z80_|execute_|ctl_reg_in_hi~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y12_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_in_hi~2_combout = (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|M5~q )
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|sequencer_|M5~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_in_hi~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_in_hi~2 .lut_mask = 16'hAA00;
|
|
defparam \z80_|execute_|ctl_reg_in_hi~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y13_N30
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~30 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~30_combout = (\z80_|execute_|ixy_d~6_combout & (!\z80_|execute_|ctl_mRead~14_combout & ((!\z80_|execute_|ctl_mRead~15_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|execute_|ixy_d~6_combout &
|
|
// (((!\z80_|execute_|ctl_mRead~15_combout )) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))
|
|
|
|
.dataa(\z80_|execute_|ixy_d~6_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_in_hi~2_combout ),
|
|
.datac(\z80_|execute_|ctl_mRead~14_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~15_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~30_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~30 .lut_mask = 16'h135F;
|
|
defparam \z80_|execute_|setM1~30 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y13_N24
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_mRead~23 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mRead~23_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|execute_|ctl_mRead~14_combout & ((!\z80_|execute_|ctl_mRead~15_combout ) # (!\z80_|execute_|ctl_state_alu~4_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout
|
|
// & (((!\z80_|execute_|ctl_mRead~15_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_state_alu~2_combout ),
|
|
.datab(\z80_|execute_|ctl_state_alu~4_combout ),
|
|
.datac(\z80_|execute_|ctl_mRead~14_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~15_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mRead~23_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mRead~23 .lut_mask = 16'h135F;
|
|
defparam \z80_|execute_|ctl_mRead~23 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y15_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~6 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_sel[0]~6_combout = (\z80_|execute_|setM1~30_combout & (\z80_|execute_|ctl_mRead~23_combout & ((!\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|ixy_d~7_combout ))))
|
|
|
|
.dataa(\z80_|execute_|setM1~30_combout ),
|
|
.datab(\z80_|execute_|ixy_d~7_combout ),
|
|
.datac(\z80_|execute_|ctl_mRead~23_combout ),
|
|
.datad(\z80_|pla_decode_|Equal6~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .lut_mask = 16'h20A0;
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[0]~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y16_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~3 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_in_hi~3_combout = ((!\z80_|execute_|ctl_mRead~7_combout & (!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~6_combout ))) # (!\z80_|execute_|ixy_d~6_combout )
|
|
|
|
.dataa(\z80_|execute_|ixy_d~6_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~7_combout ),
|
|
.datac(\z80_|execute_|ctl_mRead~8_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~6_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_in_hi~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_in_hi~3 .lut_mask = 16'h5557;
|
|
defparam \z80_|execute_|ctl_reg_in_hi~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y18_N26
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~10 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mWrite~10_combout = (\z80_|execute_|ctl_flags_alu~17_combout & (\z80_|execute_|ctl_flags_alu~6_combout & \z80_|execute_|ctl_reg_in_hi~3_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_alu~17_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_alu~6_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|execute_|ctl_reg_in_hi~3_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mWrite~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mWrite~10 .lut_mask = 16'h8800;
|
|
defparam \z80_|execute_|ctl_mWrite~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y18_N26
|
|
cycloneive_lcell_comb \z80_|execute_|fMRead~18 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fMRead~18_combout = (\z80_|execute_|ctl_ir_we~15_combout & (!\z80_|execute_|ctl_state_alu~2_combout & ((!\z80_|execute_|ctl_mRead~16_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|execute_|ctl_ir_we~15_combout &
|
|
// (((!\z80_|execute_|ctl_mRead~16_combout )) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_ir_we~15_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_in_hi~2_combout ),
|
|
.datac(\z80_|execute_|ctl_state_alu~2_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~16_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fMRead~18_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fMRead~18 .lut_mask = 16'h135F;
|
|
defparam \z80_|execute_|fMRead~18 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y16_N14
|
|
cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~0 (
|
|
// Equation(s):
|
|
// \z80_|reg_control_|reg_sel_pc~0_combout = ((!\z80_|pla_decode_|Equal37~0_combout & ((!\z80_|pla_decode_|Equal24~0_combout ) # (!\z80_|pla_decode_|Equal9~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout )
|
|
|
|
.dataa(\z80_|pla_decode_|Equal37~0_combout ),
|
|
.datab(\z80_|pla_decode_|Equal9~0_combout ),
|
|
.datac(\z80_|execute_|ixy_d~6_combout ),
|
|
.datad(\z80_|pla_decode_|Equal24~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_control_|reg_sel_pc~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_control_|reg_sel_pc~0 .lut_mask = 16'h1F5F;
|
|
defparam \z80_|reg_control_|reg_sel_pc~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y13_N8
|
|
cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~1 (
|
|
// Equation(s):
|
|
// \z80_|reg_control_|reg_sel_pc~1_combout = (\z80_|pla_decode_|Equal29~0_combout & (!\z80_|execute_|ixy_d~6_combout & ((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|pla_decode_|Equal29~0_combout &
|
|
// (((!\z80_|execute_|ctl_reg_in_hi~2_combout ) # (!\z80_|pla_decode_|Equal47~0_combout ))))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal29~0_combout ),
|
|
.datab(\z80_|execute_|ixy_d~6_combout ),
|
|
.datac(\z80_|pla_decode_|Equal47~0_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_in_hi~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_control_|reg_sel_pc~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_control_|reg_sel_pc~1 .lut_mask = 16'h0777;
|
|
defparam \z80_|reg_control_|reg_sel_pc~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y13_N18
|
|
cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~2 (
|
|
// Equation(s):
|
|
// \z80_|reg_control_|reg_sel_pc~2_combout = (\z80_|reg_control_|reg_sel_pc~0_combout & (\z80_|reg_control_|reg_sel_pc~1_combout & ((!\z80_|pla_decode_|Equal38~2_combout ) # (!\z80_|execute_|ixy_d~6_combout ))))
|
|
|
|
.dataa(\z80_|reg_control_|reg_sel_pc~0_combout ),
|
|
.datab(\z80_|execute_|ixy_d~6_combout ),
|
|
.datac(\z80_|reg_control_|reg_sel_pc~1_combout ),
|
|
.datad(\z80_|pla_decode_|Equal38~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_control_|reg_sel_pc~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_control_|reg_sel_pc~2 .lut_mask = 16'h20A0;
|
|
defparam \z80_|reg_control_|reg_sel_pc~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y18_N18
|
|
cycloneive_lcell_comb \z80_|execute_|fMRead~19 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fMRead~19_combout = (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_state_alu~7_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_ir_we~7_combout ))))
|
|
|
|
.dataa(\z80_|reg_control_|reg_sel_pc~2_combout ),
|
|
.datab(\z80_|execute_|ctl_ir_we~7_combout ),
|
|
.datac(\z80_|execute_|ctl_state_alu~2_combout ),
|
|
.datad(\z80_|execute_|ctl_state_alu~7_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fMRead~19_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fMRead~19 .lut_mask = 16'h2A00;
|
|
defparam \z80_|execute_|fMRead~19 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y18_N24
|
|
cycloneive_lcell_comb \z80_|execute_|fMRead~20 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fMRead~20_combout = (\z80_|execute_|ctl_mWrite~10_combout & (\z80_|execute_|ctl_sw_2d~4_combout & (\z80_|execute_|fMRead~18_combout & \z80_|execute_|fMRead~19_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_mWrite~10_combout ),
|
|
.datab(\z80_|execute_|ctl_sw_2d~4_combout ),
|
|
.datac(\z80_|execute_|fMRead~18_combout ),
|
|
.datad(\z80_|execute_|fMRead~19_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fMRead~20_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fMRead~20 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|fMRead~20 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y15_N16
|
|
cycloneive_lcell_comb \z80_|execute_|fMRead~21 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fMRead~21_combout = (\z80_|execute_|ctl_mRead~22_combout & (\z80_|execute_|ctl_reg_in_hi~6_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & \z80_|execute_|fMRead~20_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_mRead~22_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_in_hi~6_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ),
|
|
.datad(\z80_|execute_|fMRead~20_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fMRead~21_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fMRead~21 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|fMRead~21 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y12_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~9 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_sw_2d~9_combout = (\z80_|execute_|ctl_sw_2d~8_combout & (\z80_|execute_|ctl_sw_2d~5_combout & (!\z80_|execute_|ctl_alu_shift_oe~16_combout & \z80_|execute_|fMRead~21_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_sw_2d~8_combout ),
|
|
.datab(\z80_|execute_|ctl_sw_2d~5_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_shift_oe~16_combout ),
|
|
.datad(\z80_|execute_|fMRead~21_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_sw_2d~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_sw_2d~9 .lut_mask = 16'h0800;
|
|
defparam \z80_|execute_|ctl_sw_2d~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y16_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~14 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_sw_2d~14_combout = (!\z80_|execute_|ctl_mRead~12_combout & (((\z80_|decode_state_|in_halt~q ) # (!\z80_|pla_decode_|Equal77~0_combout )) # (!\z80_|pla_decode_|Equal33~0_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal33~0_combout ),
|
|
.datab(\z80_|decode_state_|in_halt~q ),
|
|
.datac(\z80_|execute_|ctl_mRead~12_combout ),
|
|
.datad(\z80_|pla_decode_|Equal77~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_sw_2d~14_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_sw_2d~14 .lut_mask = 16'h0D0F;
|
|
defparam \z80_|execute_|ctl_sw_2d~14 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y17_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~8 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_sw_1d~8_combout = (((\z80_|ir_|opcode [5] & !\z80_|ir_|opcode [4])) # (!\z80_|ir_|opcode [3])) # (!\z80_|pla_decode_|Equal12~0_combout )
|
|
|
|
.dataa(\z80_|ir_|opcode [5]),
|
|
.datab(\z80_|ir_|opcode [4]),
|
|
.datac(\z80_|pla_decode_|Equal12~0_combout ),
|
|
.datad(\z80_|ir_|opcode [3]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_sw_1d~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_sw_1d~8 .lut_mask = 16'h2FFF;
|
|
defparam \z80_|execute_|ctl_sw_1d~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y16_N2
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~10 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_sw_2d~10_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|rsel3~combout & \z80_|execute_|ctl_iorw~10_combout )) # (!\z80_|execute_|nextM~2_combout )))
|
|
|
|
.dataa(\z80_|execute_|rsel3~combout ),
|
|
.datab(\z80_|execute_|ctl_iorw~10_combout ),
|
|
.datac(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.datad(\z80_|execute_|nextM~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_sw_2d~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_sw_2d~10 .lut_mask = 16'h80F0;
|
|
defparam \z80_|execute_|ctl_sw_2d~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y16_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~11 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_sw_2d~11_combout = (\z80_|execute_|ctl_sw_2d~10_combout ) # ((\z80_|nM1_int~2_combout & ((!\z80_|execute_|ctl_sw_1d~8_combout ) # (!\z80_|execute_|ctl_sw_2d~14_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_sw_2d~14_combout ),
|
|
.datab(\z80_|execute_|ctl_sw_1d~8_combout ),
|
|
.datac(\z80_|nM1_int~2_combout ),
|
|
.datad(\z80_|execute_|ctl_sw_2d~10_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_sw_2d~11_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_sw_2d~11 .lut_mask = 16'hFF70;
|
|
defparam \z80_|execute_|ctl_sw_2d~11 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y18_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~12 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_sw_2d~12_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|rsel3~combout & ((\z80_|execute_|ctl_alu_shift_oe~15_combout ) # (\z80_|execute_|ctl_alu_op_low~28_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_op_low~28_combout ),
|
|
.datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ),
|
|
.datad(\z80_|execute_|rsel3~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_sw_2d~12_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_sw_2d~12 .lut_mask = 16'hFEF0;
|
|
defparam \z80_|execute_|ctl_sw_2d~12 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y16_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_sw_2d~13 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_sw_2d~13_combout = ((\z80_|execute_|ctl_sw_2d~11_combout ) # ((\z80_|execute_|ctl_sw_2d~12_combout ) # (!\z80_|execute_|ctl_reg_out_lo~7_combout ))) # (!\z80_|execute_|ctl_sw_2d~9_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_sw_2d~9_combout ),
|
|
.datab(\z80_|execute_|ctl_sw_2d~11_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_out_lo~7_combout ),
|
|
.datad(\z80_|execute_|ctl_sw_2d~12_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_sw_2d~13_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_sw_2d~13 .lut_mask = 16'hFFDF;
|
|
defparam \z80_|execute_|ctl_sw_2d~13 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y15_N8
|
|
cycloneive_lcell_comb \z80_|alu_|db[7]~9 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db[7]~9_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout ) # ((\z80_|execute_|ctl_sw_2d~13_combout ) # (\z80_|execute_|ctl_alu_oe~11_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_sw_2d~13_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_oe~11_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db[7]~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db[7]~9 .lut_mask = 16'hFFFA;
|
|
defparam \z80_|alu_|db[7]~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y14_N0
|
|
cycloneive_lcell_comb \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 (
|
|
// Equation(s):
|
|
// \z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout = (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (((!\z80_|pla_decode_|Equal47~0_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q )))
|
|
|
|
.dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ),
|
|
.datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ),
|
|
.datac(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ),
|
|
.datad(\z80_|pla_decode_|Equal47~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .lut_mask = 16'h1333;
|
|
defparam \z80_|alu_control_|SYNTHESIZED_WIRE_2~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y18_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout = (\z80_|ir_|opcode [3] & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal63~0_combout & \z80_|ir_|opcode [4])))
|
|
|
|
.dataa(\z80_|ir_|opcode [3]),
|
|
.datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ),
|
|
.datac(\z80_|pla_decode_|Equal63~0_combout ),
|
|
.datad(\z80_|ir_|opcode [4]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .lut_mask = 16'h2000;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y16_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~32 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op_low~32_combout = (((!\z80_|pla_decode_|Equal3~0_combout & !\z80_|pla_decode_|Equal21~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout )
|
|
|
|
.dataa(\z80_|pla_decode_|Equal63~0_combout ),
|
|
.datab(\z80_|pla_decode_|Equal3~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal21~0_combout ),
|
|
.datad(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op_low~32_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op_low~32 .lut_mask = 16'h57FF;
|
|
defparam \z80_|execute_|ctl_alu_op_low~32 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y19_N2
|
|
cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~2 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|DFFE_inst_latch_nf~2_combout = ((!\z80_|pla_decode_|Equal20~0_combout & ((!\z80_|pla_decode_|Equal68~2_combout ) # (!\z80_|pla_decode_|Equal1~4_combout )))) # (!\z80_|nM1_int~2_combout )
|
|
|
|
.dataa(\z80_|pla_decode_|Equal20~0_combout ),
|
|
.datab(\z80_|pla_decode_|Equal1~4_combout ),
|
|
.datac(\z80_|nM1_int~2_combout ),
|
|
.datad(\z80_|pla_decode_|Equal68~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|DFFE_inst_latch_nf~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_nf~2 .lut_mask = 16'h1F5F;
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_nf~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y19_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~22 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_xy_we~22_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((\z80_|sequencer_|DFFE_T1_ff~q ) # (!\z80_|ir_|opcode [4])) # (!\z80_|pla_decode_|Equal63~0_combout ))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.datab(\z80_|pla_decode_|Equal63~0_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datad(\z80_|ir_|opcode [4]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_xy_we~22_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_xy_we~22 .lut_mask = 16'hFBFF;
|
|
defparam \z80_|execute_|ctl_flags_xy_we~22 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y19_N28
|
|
cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~3 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|DFFE_inst_latch_nf~3_combout = (\z80_|execute_|ctl_alu_op_low~32_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~2_combout & \z80_|execute_|ctl_flags_xy_we~22_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op_low~32_combout ),
|
|
.datab(\z80_|alu_flags_|DFFE_inst_latch_nf~2_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|execute_|ctl_flags_xy_we~22_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_nf~3 .lut_mask = 16'h8800;
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_nf~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y18_N2
|
|
cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~4 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|DFFE_inst_latch_nf~4_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout & (\z80_|execute_|ctl_flags_pf_we~10_combout & (\z80_|execute_|ctl_alu_op1_sel_bus~8_combout & \z80_|execute_|ctl_alu_op_low~45_combout )))
|
|
|
|
.dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~3_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_pf_we~10_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op_low~45_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .lut_mask = 16'h8000;
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_nf~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y19_N16
|
|
cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~5 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|DFFE_inst_latch_nf~5_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout & (((!\z80_|pla_decode_|Equal21~0_combout & !\z80_|pla_decode_|Equal32~0_combout )) # (!\z80_|pla_decode_|Equal62~2_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal21~0_combout ),
|
|
.datab(\z80_|pla_decode_|Equal32~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal62~2_combout ),
|
|
.datad(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .lut_mask = 16'h1F00;
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_nf~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y19_N8
|
|
cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout = (\z80_|execute_|ctl_alu_shift_oe~38_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|ctl_ir_we~11_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q )))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T4_ff~q ),
|
|
.datab(\z80_|execute_|ctl_alu_shift_oe~38_combout ),
|
|
.datac(\z80_|execute_|ctl_ir_we~11_combout ),
|
|
.datad(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .lut_mask = 16'hCC4C;
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~12 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y19_N2
|
|
cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout & (\z80_|execute_|ctl_flags_sz_we~4_combout & ((!\z80_|pla_decode_|Equal62~2_combout ) # (!\z80_|pla_decode_|Equal9~0_combout ))))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal9~0_combout ),
|
|
.datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~12_combout ),
|
|
.datac(\z80_|pla_decode_|Equal62~2_combout ),
|
|
.datad(\z80_|execute_|ctl_flags_sz_we~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .lut_mask = 16'h4C00;
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~13 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y19_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~15 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_core_hf~15_combout = (\z80_|ir_|opcode [5]) # (((!\z80_|pla_decode_|Equal32~0_combout & !\z80_|pla_decode_|Equal9~0_combout )) # (!\z80_|execute_|ctl_state_alu~11_combout ))
|
|
|
|
.dataa(\z80_|ir_|opcode [5]),
|
|
.datab(\z80_|execute_|ctl_state_alu~11_combout ),
|
|
.datac(\z80_|pla_decode_|Equal32~0_combout ),
|
|
.datad(\z80_|pla_decode_|Equal9~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_core_hf~15_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_core_hf~15 .lut_mask = 16'hBBBF;
|
|
defparam \z80_|execute_|ctl_alu_core_hf~15 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y19_N8
|
|
cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~6 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|DFFE_inst_latch_nf~6_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout & \z80_|execute_|ctl_alu_core_hf~15_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_core_hf~15_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .lut_mask = 16'hC0C0;
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_nf~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y19_N10
|
|
cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~7 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|DFFE_inst_latch_nf~7_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout & !\z80_|execute_|ctl_alu_core_R~1_combout )))
|
|
|
|
.dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~5_combout ),
|
|
.datab(\z80_|alu_flags_|DFFE_inst_latch_nf~9_combout ),
|
|
.datac(\z80_|alu_flags_|DFFE_inst_latch_nf~6_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_core_R~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .lut_mask = 16'h0080;
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_nf~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y19_N2
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [3])))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal55~0_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ),
|
|
.datac(\z80_|pla_decode_|Equal13~0_combout ),
|
|
.datad(\z80_|ir_|opcode [3]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .lut_mask = 16'h0080;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y19_N20
|
|
cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout = (\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ) # ((\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|pla_decode_|Equal61~2_combout ))))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal10~0_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_hilo_nop3pla68M1T3_2~combout ),
|
|
.datac(\z80_|nM1_int~2_combout ),
|
|
.datad(\z80_|pla_decode_|Equal61~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .lut_mask = 16'hFCEC;
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y13_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~17 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_sel_op2_neg~17_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & \z80_|pla_decode_|Equal6~0_combout )))
|
|
|
|
.dataa(\z80_|ir_|opcode [0]),
|
|
.datab(\z80_|pla_decode_|Equal3~1_combout ),
|
|
.datac(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.datad(\z80_|pla_decode_|Equal6~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|ctl_alu_sel_op2_neg~17 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y19_N18
|
|
cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ) # ((\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ) # ((\z80_|alu_control_|db[1]~26_combout & \z80_|execute_|ctl_flags_bus~combout )))
|
|
|
|
.dataa(\z80_|alu_control_|db[1]~26_combout ),
|
|
.datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~0_combout ),
|
|
.datac(\z80_|execute_|ctl_flags_bus~combout ),
|
|
.datad(\z80_|execute_|ctl_alu_sel_op2_neg~17_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .lut_mask = 16'hFFEC;
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y19_N4
|
|
cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ) # ((\z80_|alu_|db_high[3]~7_combout & \z80_|execute_|ctl_flags_alu~15_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~14_combout )
|
|
|
|
.dataa(\z80_|alu_|db_high[3]~7_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_alu~15_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_sel_op2_neg~14_combout ),
|
|
.datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .lut_mask = 16'hFF8F;
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_5~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y19_N26
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~3 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_nf_we~3_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal10~0_combout ) # ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|pla_decode_|Equal61~2_combout ))))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal10~0_combout ),
|
|
.datab(\z80_|pla_decode_|Equal11~0_combout ),
|
|
.datac(\z80_|nM1_int~2_combout ),
|
|
.datad(\z80_|pla_decode_|Equal61~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_nf_we~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_nf_we~3 .lut_mask = 16'hF0E0;
|
|
defparam \z80_|execute_|ctl_flags_nf_we~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y20_N18
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~0 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_nf_we~0_combout = (\z80_|pla_decode_|Equal61~2_combout & (!\z80_|execute_|ctl_eval_cond~0_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|execute_|ctl_mRead~34_combout )))) # (!\z80_|pla_decode_|Equal61~2_combout &
|
|
// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|ctl_mRead~34_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal61~2_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~34_combout ),
|
|
.datac(\z80_|execute_|ixy_d~5_combout ),
|
|
.datad(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_nf_we~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_nf_we~0 .lut_mask = 16'h153F;
|
|
defparam \z80_|execute_|ctl_flags_nf_we~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y17_N0
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal73~2 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal73~2_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|execute_|ctl_state_alu~11_combout & \z80_|ir_|opcode [3])))
|
|
|
|
.dataa(\z80_|ir_|opcode [5]),
|
|
.datab(\z80_|ir_|opcode [4]),
|
|
.datac(\z80_|execute_|ctl_state_alu~11_combout ),
|
|
.datad(\z80_|ir_|opcode [3]),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal73~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal73~2 .lut_mask = 16'h2000;
|
|
defparam \z80_|pla_decode_|Equal73~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y19_N26
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal72~2 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal72~2_combout = (\z80_|ir_|opcode [5] & (\z80_|execute_|ctl_state_alu~11_combout & (\z80_|ir_|opcode [4] & !\z80_|ir_|opcode [3])))
|
|
|
|
.dataa(\z80_|ir_|opcode [5]),
|
|
.datab(\z80_|execute_|ctl_state_alu~11_combout ),
|
|
.datac(\z80_|ir_|opcode [4]),
|
|
.datad(\z80_|ir_|opcode [3]),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal72~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal72~2 .lut_mask = 16'h0080;
|
|
defparam \z80_|pla_decode_|Equal72~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y20_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~1 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_nf_we~1_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout & (\z80_|execute_|ctl_flags_nf_we~0_combout & (!\z80_|pla_decode_|Equal73~2_combout & !\z80_|pla_decode_|Equal72~2_combout )))
|
|
|
|
.dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_nf_we~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal73~2_combout ),
|
|
.datad(\z80_|pla_decode_|Equal72~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_nf_we~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_nf_we~1 .lut_mask = 16'h0008;
|
|
defparam \z80_|execute_|ctl_flags_nf_we~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y19_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_nf_we~2_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~18_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout & (\z80_|execute_|ctl_alu_core_hf~15_combout & \z80_|execute_|ctl_flags_nf_we~1_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ),
|
|
.datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_core_hf~15_combout ),
|
|
.datad(\z80_|execute_|ctl_flags_nf_we~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_nf_we~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_nf_we~2 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|ctl_flags_nf_we~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y12_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~5 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_sz_we~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q ))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T4_ff~q ),
|
|
.datab(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datac(gnd),
|
|
.datad(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_sz_we~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_sz_we~5 .lut_mask = 16'hFFBB;
|
|
defparam \z80_|execute_|ctl_flags_sz_we~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y12_N2
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~6 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_sz_we~6_combout = (\z80_|execute_|ctl_flags_sz_we~5_combout & ((\z80_|execute_|ctl_alu_core_R~0_combout ) # ((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) #
|
|
// (!\z80_|execute_|ctl_flags_sz_we~5_combout & (((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_sz_we~5_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_core_R~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal48~0_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_sz_we~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_sz_we~6 .lut_mask = 16'hF888;
|
|
defparam \z80_|execute_|ctl_flags_sz_we~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y19_N6
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_nf_we~4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_nf_we~4_combout = (\z80_|execute_|ctl_flags_nf_we~3_combout ) # (((\z80_|execute_|ctl_flags_sz_we~6_combout ) # (!\z80_|execute_|ctl_flags_xy_we~14_combout )) # (!\z80_|execute_|ctl_flags_nf_we~2_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_nf_we~3_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_nf_we~2_combout ),
|
|
.datac(\z80_|execute_|ctl_flags_sz_we~6_combout ),
|
|
.datad(\z80_|execute_|ctl_flags_xy_we~14_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_nf_we~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_nf_we~4 .lut_mask = 16'hFBFF;
|
|
defparam \z80_|execute_|ctl_flags_nf_we~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y19_N24
|
|
cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_nf~8 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|DFFE_inst_latch_nf~8_combout = (\z80_|execute_|ctl_flags_nf_we~4_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ))) # (!\z80_|execute_|ctl_flags_nf_we~4_combout &
|
|
// (((\z80_|alu_flags_|DFFE_inst_latch_nf~q ))))
|
|
|
|
.dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~7_combout ),
|
|
.datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_5~2_combout ),
|
|
.datac(\z80_|alu_flags_|DFFE_inst_latch_nf~q ),
|
|
.datad(\z80_|execute_|ctl_flags_nf_we~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .lut_mask = 16'h88F0;
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_nf~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X26_Y19_N25
|
|
dffeas \z80_|alu_flags_|DFFE_inst_latch_nf (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|alu_flags_|DFFE_inst_latch_nf~8_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|alu_flags_|DFFE_inst_latch_nf~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_nf .is_wysiwyg = "true";
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_nf .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y13_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~14 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_hf_cpl~14_combout = (\z80_|ir_|opcode [4]) # (!\z80_|pla_decode_|Equal63~0_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|pla_decode_|Equal63~0_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|ir_|opcode [4]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_hf_cpl~14_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_hf_cpl~14 .lut_mask = 16'hFF33;
|
|
defparam \z80_|execute_|ctl_flags_hf_cpl~14 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y13_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~10 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_hf_cpl~10_combout = (\z80_|execute_|ctl_flags_hf_cpl~14_combout & (!\z80_|execute_|ctl_alu_op_low~27_combout & (!\z80_|execute_|ctl_state_alu~5_combout & !\z80_|pla_decode_|Equal68~3_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_hf_cpl~14_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_op_low~27_combout ),
|
|
.datac(\z80_|execute_|ctl_state_alu~5_combout ),
|
|
.datad(\z80_|pla_decode_|Equal68~3_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_hf_cpl~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_hf_cpl~10 .lut_mask = 16'h0002;
|
|
defparam \z80_|execute_|ctl_flags_hf_cpl~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y13_N2
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal45~0 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal45~0_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|ir_|opcode [2] & (!\z80_|ir_|opcode [1] & \z80_|pla_decode_|Equal6~0_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal33~1_combout ),
|
|
.datab(\z80_|ir_|opcode [2]),
|
|
.datac(\z80_|ir_|opcode [1]),
|
|
.datad(\z80_|pla_decode_|Equal6~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal45~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal45~0 .lut_mask = 16'h0800;
|
|
defparam \z80_|pla_decode_|Equal45~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y14_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~11 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_hf_cpl~11_combout = (\z80_|execute_|ctl_state_alu~6_combout ) # ((\z80_|pla_decode_|Equal52~1_combout ) # ((\z80_|pla_decode_|Equal45~0_combout & !\z80_|decode_state_|use_ixiy~combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_state_alu~6_combout ),
|
|
.datab(\z80_|pla_decode_|Equal45~0_combout ),
|
|
.datac(\z80_|decode_state_|use_ixiy~combout ),
|
|
.datad(\z80_|pla_decode_|Equal52~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_hf_cpl~11_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_hf_cpl~11 .lut_mask = 16'hFFAE;
|
|
defparam \z80_|execute_|ctl_flags_hf_cpl~11 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y14_N26
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~12 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_hf_cpl~12_combout = ((\z80_|execute_|ctl_alu_op_low~25_combout ) # ((\z80_|pla_decode_|Equal10~0_combout ) # (\z80_|execute_|ctl_flags_hf_cpl~11_combout ))) # (!\z80_|execute_|ctl_flags_hf_cpl~10_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_hf_cpl~10_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_op_low~25_combout ),
|
|
.datac(\z80_|pla_decode_|Equal10~0_combout ),
|
|
.datad(\z80_|execute_|ctl_flags_hf_cpl~11_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_hf_cpl~12_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_hf_cpl~12 .lut_mask = 16'hFFFD;
|
|
defparam \z80_|execute_|ctl_flags_hf_cpl~12 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y14_N2
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_cpl~13 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_hf_cpl~13_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|execute_|ctl_flags_hf_cpl~12_combout & \z80_|sequencer_|DFFE_T2_ff~q )))
|
|
|
|
.dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ),
|
|
.datab(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.datac(\z80_|execute_|ctl_flags_hf_cpl~12_combout ),
|
|
.datad(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_hf_cpl~13_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_hf_cpl~13 .lut_mask = 16'h2000;
|
|
defparam \z80_|execute_|ctl_flags_hf_cpl~13 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y17_N24
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~8 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_core_S~8_combout = (\z80_|execute_|ctl_alu_core_S~6_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~4_combout & (\z80_|execute_|ctl_alu_core_S~11_combout & !\z80_|execute_|ctl_alu_core_R~1_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_core_S~6_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_sel_op2_neg~4_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_core_S~11_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_core_R~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_core_S~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_core_S~8 .lut_mask = 16'h0080;
|
|
defparam \z80_|execute_|ctl_alu_core_S~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y20_N28
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~9 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_core_S~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout & (\z80_|execute_|ctl_alu_core_S~8_combout & !\z80_|pla_decode_|Equal72~2_combout ))
|
|
|
|
.dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_alu_core_S~8_combout ),
|
|
.datad(\z80_|pla_decode_|Equal72~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_core_S~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_core_S~9 .lut_mask = 16'h00A0;
|
|
defparam \z80_|execute_|ctl_alu_core_S~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y20_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S~10 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_core_S~10_combout = (((!\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ) # (!\z80_|execute_|ctl_alu_core_S~12_combout )) # (!\z80_|execute_|ctl_alu_core_R~4_combout )) # (!\z80_|execute_|ctl_alu_core_S~5_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_core_S~5_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_core_R~4_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_core_S~12_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op1_sel_bus~10_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_core_S~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_core_S~10 .lut_mask = 16'h7FFF;
|
|
defparam \z80_|execute_|ctl_alu_core_S~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y20_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_S (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_core_S~combout = ((\z80_|execute_|ctl_alu_core_S~10_combout ) # ((\z80_|pla_decode_|Equal9~0_combout & \z80_|pla_decode_|Equal62~2_combout ))) # (!\z80_|execute_|ctl_alu_core_S~9_combout )
|
|
|
|
.dataa(\z80_|pla_decode_|Equal9~0_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_core_S~9_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_core_S~10_combout ),
|
|
.datad(\z80_|pla_decode_|Equal62~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_core_S~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_core_S .lut_mask = 16'hFBF3;
|
|
defparam \z80_|execute_|ctl_alu_core_S .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y17_N12
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[3] (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_op1_latch_mux_high|Q [3] = (\z80_|alu_|db_high[3]~7_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|execute_|ctl_alu_op1_sel_bus~15_combout ))
|
|
|
|
.dataa(\z80_|alu_|db_high[3]~7_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .lut_mask = 16'h0A00;
|
|
defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[3] .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y17_N8
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|ena~0 (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # (\z80_|execute_|ctl_alu_op1_sel_zero~combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .lut_mask = 16'hFAFA;
|
|
defparam \z80_|alu_|b2v_op1_latch_mux_high|ena~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y17_N13
|
|
dffeas \z80_|alu_|op1_high[3] (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|alu_|b2v_op1_latch_mux_high|Q [3]),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|alu_|op1_high [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|op1_high[3] .is_wysiwyg = "true";
|
|
defparam \z80_|alu_|op1_high[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y17_N14
|
|
cycloneive_lcell_comb \z80_|alu_|alu_op1[3]~2 (
|
|
// Equation(s):
|
|
// \z80_|alu_|alu_op1[3]~2_combout = (\z80_|execute_|ctl_alu_op_low~41_combout & (((\z80_|alu_|op1_low [3])))) # (!\z80_|execute_|ctl_alu_op_low~41_combout & ((\z80_|execute_|ctl_alu_op_low~29_combout & (\z80_|alu_|op1_high [3])) #
|
|
// (!\z80_|execute_|ctl_alu_op_low~29_combout & ((\z80_|alu_|op1_low [3])))))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op_low~41_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_op_low~29_combout ),
|
|
.datac(\z80_|alu_|op1_high [3]),
|
|
.datad(\z80_|alu_|op1_low [3]),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|alu_op1[3]~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|alu_op1[3]~2 .lut_mask = 16'hFB40;
|
|
defparam \z80_|alu_|alu_op1[3]~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y17_N12
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # ((\z80_|alu_|alu_op1[3]~2_combout & \z80_|alu_|alu_op2[3]~2_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_core_S~combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|alu_|alu_op1[3]~2_combout ),
|
|
.datad(\z80_|alu_|alu_op2[3]~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hFAAA;
|
|
defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y17_N28
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_we_lo~2_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|ir_|opcode [5]))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|pla_decode_|Equal55~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal6~0_combout ),
|
|
.datad(\z80_|ir_|opcode [5]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_we_lo~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_we_lo~2 .lut_mask = 16'hC000;
|
|
defparam \z80_|execute_|ctl_reg_sys_we_lo~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y17_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~3 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_we_lo~3_combout = (\z80_|pla_decode_|Equal9~1_combout ) # ((\z80_|execute_|ctl_reg_sys_we_lo~2_combout ) # ((\z80_|pla_decode_|Equal8~0_combout & \z80_|pla_decode_|Equal13~0_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal8~0_combout ),
|
|
.datab(\z80_|pla_decode_|Equal9~1_combout ),
|
|
.datac(\z80_|pla_decode_|Equal13~0_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sys_we_lo~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_we_lo~3 .lut_mask = 16'hFFEC;
|
|
defparam \z80_|execute_|ctl_reg_sys_we_lo~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y12_N18
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~14 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sel_wz~14_combout = (((!\z80_|pla_decode_|Equal35~0_combout & !\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ixy_d~6_combout )
|
|
|
|
.dataa(\z80_|pla_decode_|Equal35~0_combout ),
|
|
.datab(\z80_|execute_|ixy_d~6_combout ),
|
|
.datac(\z80_|pla_decode_|Equal34~0_combout ),
|
|
.datad(\z80_|alu_control_|flags_cond_true~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sel_wz~14_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sel_wz~14 .lut_mask = 16'h37FF;
|
|
defparam \z80_|execute_|ctl_reg_sel_wz~14 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y12_N8
|
|
cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi~0 (
|
|
// Equation(s):
|
|
// \z80_|reg_control_|reg_sys_we_hi~0_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|execute_|ctl_reg_sys_we_lo~3_combout ) # (\z80_|pla_decode_|Equal19~0_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~14_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ),
|
|
.datab(\z80_|execute_|ixy_d~6_combout ),
|
|
.datac(\z80_|pla_decode_|Equal19~0_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sel_wz~14_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_control_|reg_sys_we_hi~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_control_|reg_sys_we_hi~0 .lut_mask = 16'hC8FF;
|
|
defparam \z80_|reg_control_|reg_sys_we_hi~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y15_N20
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal33~3 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal33~3_combout = (\z80_|pla_decode_|Equal33~0_combout & (\z80_|pla_decode_|Equal33~1_combout & (\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal6~0_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal33~0_combout ),
|
|
.datab(\z80_|pla_decode_|Equal33~1_combout ),
|
|
.datac(\z80_|decode_state_|use_ixiy~combout ),
|
|
.datad(\z80_|pla_decode_|Equal6~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal33~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal33~3 .lut_mask = 16'h8000;
|
|
defparam \z80_|pla_decode_|Equal33~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y11_N18
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~0 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_we~0_combout = (\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal6~1_combout ) # (!\z80_|execute_|pc_inc_hold~26_combout ))))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal33~3_combout ),
|
|
.datab(\z80_|execute_|ixy_d~5_combout ),
|
|
.datac(\z80_|pla_decode_|Equal6~1_combout ),
|
|
.datad(\z80_|execute_|pc_inc_hold~26_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_we~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_we~0 .lut_mask = 16'hC8CC;
|
|
defparam \z80_|execute_|ctl_reg_sys_we~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y18_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_we~2_combout = (!\z80_|execute_|ctl_reg_sys_we~1_combout & (((!\z80_|pla_decode_|Equal11~0_combout & !\z80_|execute_|ctl_mWrite~17_combout )) # (!\z80_|execute_|ctl_alu_shift_oe~14_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal11~0_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_sys_we~1_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ),
|
|
.datad(\z80_|execute_|ctl_mWrite~17_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_we~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_we~2 .lut_mask = 16'h0313;
|
|
defparam \z80_|execute_|ctl_reg_sys_we~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y12_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we~3 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_we~3_combout = (\z80_|execute_|ctl_reg_sys_we~0_combout ) # (((\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # (!\z80_|execute_|ctl_reg_sys_we~2_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~32_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_sys_we~0_combout ),
|
|
.datab(\z80_|execute_|ctl_bus_inc_oe~32_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sys_we~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_we~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_we~3 .lut_mask = 16'hFBFF;
|
|
defparam \z80_|execute_|ctl_reg_sys_we~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y14_N2
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_in_hi~4_combout = (\z80_|reg_control_|reg_sel_pc~2_combout & (\z80_|execute_|ctl_alu_oe~2_combout & (!\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout & \z80_|execute_|ctl_alu_sel_op2_neg~2_combout )))
|
|
|
|
.dataa(\z80_|reg_control_|reg_sel_pc~2_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_oe~2_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ),
|
|
.datad(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_in_hi~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_in_hi~4 .lut_mask = 16'h0800;
|
|
defparam \z80_|execute_|ctl_reg_in_hi~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y14_N4
|
|
cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_hi (
|
|
// Equation(s):
|
|
// \z80_|reg_control_|reg_sys_we_hi~combout = (\z80_|reg_control_|reg_sys_we_hi~0_combout ) # ((\z80_|execute_|ctl_reg_sys_we~3_combout ) # (!\z80_|execute_|ctl_reg_in_hi~4_combout ))
|
|
|
|
.dataa(\z80_|reg_control_|reg_sys_we_hi~0_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_sys_we~3_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|execute_|ctl_reg_in_hi~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_control_|reg_sys_we_hi~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_control_|reg_sys_we_hi .lut_mask = 16'hEEFF;
|
|
defparam \z80_|reg_control_|reg_sys_we_hi .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y12_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~18 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_hilo[1]~18_combout = (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q ))))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.datab(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datac(\z80_|sequencer_|DFFE_M4_ff~q ),
|
|
.datad(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .lut_mask = 16'hF0B0;
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~18 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y12_N18
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~17 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_hilo~17_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|execute_|ctl_mRead~12_combout & ((\z80_|sequencer_|DFFE_T2_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q ))))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.datab(\z80_|sequencer_|DFFE_M2_ff~q ),
|
|
.datac(\z80_|execute_|ctl_mRead~12_combout ),
|
|
.datad(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_hilo~17_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo~17 .lut_mask = 16'h80C0;
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo~17 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y12_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~11 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sel_pc~11_combout = (!\z80_|execute_|ctl_reg_sys_hilo~17_combout & (((!\z80_|execute_|ctl_mRead~34_combout & !\z80_|pla_decode_|Equal10~0_combout )) # (!\z80_|execute_|ctl_mWrite~9_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_mWrite~9_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~34_combout ),
|
|
.datac(\z80_|pla_decode_|Equal10~0_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sys_hilo~17_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sel_pc~11_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sel_pc~11 .lut_mask = 16'h0057;
|
|
defparam \z80_|execute_|ctl_reg_sel_pc~11 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y12_N16
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~12 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sel_pc~12_combout = (\z80_|execute_|ctl_reg_sel_pc~11_combout & (((\z80_|execute_|ctl_flags_bus~1_combout & \z80_|execute_|ctl_al_we~13_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~18_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_bus~1_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_sel_pc~11_combout ),
|
|
.datad(\z80_|execute_|ctl_al_we~13_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sel_pc~12_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sel_pc~12 .lut_mask = 16'hD050;
|
|
defparam \z80_|execute_|ctl_reg_sel_pc~12 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y12_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~13 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sel_pc~13_combout = (\z80_|execute_|setM1~54_combout & (\z80_|execute_|ctl_reg_sel_pc~12_combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|pla_decode_|Equal6~1_combout ))))
|
|
|
|
.dataa(\z80_|execute_|setM1~54_combout ),
|
|
.datab(\z80_|pla_decode_|Equal6~1_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_sel_pc~12_combout ),
|
|
.datad(\z80_|execute_|ixy_d~7_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sel_pc~13_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sel_pc~13 .lut_mask = 16'h20A0;
|
|
defparam \z80_|execute_|ctl_reg_sel_pc~13 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y16_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout = (\z80_|execute_|ixy_d~6_combout & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & \z80_|ir_|opcode [0])))
|
|
|
|
.dataa(\z80_|execute_|ixy_d~6_combout ),
|
|
.datab(\z80_|pla_decode_|Equal52~0_combout ),
|
|
.datac(\z80_|execute_|comb~0_combout ),
|
|
.datad(\z80_|ir_|opcode [0]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y15_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~6 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sel_wz~6_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (((!\z80_|execute_|ctl_mRead~8_combout & !\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_mRead~8_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~6_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ),
|
|
.datad(\z80_|execute_|ctl_state_alu~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sel_wz~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sel_wz~6 .lut_mask = 16'h010F;
|
|
defparam \z80_|execute_|ctl_reg_sel_wz~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y12_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~7 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sel_wz~7_combout = (\z80_|execute_|ctl_reg_sel_wz~6_combout & (((!\z80_|pla_decode_|Equal34~0_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal34~0_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_in_hi~2_combout ),
|
|
.datac(\z80_|pla_decode_|Equal19~0_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sel_wz~6_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sel_wz~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sel_wz~7 .lut_mask = 16'h3700;
|
|
defparam \z80_|execute_|ctl_reg_sel_wz~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y14_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~9 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sel_wz~9_combout = (\z80_|execute_|ctl_bus_db_oe~0_combout & (\z80_|execute_|ctl_reg_in_hi~3_combout & (\z80_|execute_|ctl_reg_sel_wz~7_combout & \z80_|execute_|ctl_reg_in_hi~4_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_in_hi~3_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_sel_wz~7_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_in_hi~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sel_wz~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sel_wz~9 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|ctl_reg_sel_wz~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y16_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~25 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_hilo[1]~25_combout = (!\z80_|pla_decode_|Equal35~0_combout & (!\z80_|pla_decode_|Equal24~1_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~11_combout & !\z80_|pla_decode_|Equal19~0_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal35~0_combout ),
|
|
.datab(\z80_|pla_decode_|Equal24~1_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_sys_hilo[1]~11_combout ),
|
|
.datad(\z80_|pla_decode_|Equal19~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .lut_mask = 16'h0010;
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~25 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y15_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~8 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sel_wz~8_combout = (!\z80_|execute_|ctl_mRead~15_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_mRead~15_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|pla_decode_|Equal12~1_combout ),
|
|
.datad(\z80_|pla_decode_|Equal25~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sel_wz~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sel_wz~8 .lut_mask = 16'h5055;
|
|
defparam \z80_|execute_|ctl_reg_sel_wz~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y12_N26
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_al_we~5 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_al_we~5_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout & (!\z80_|pla_decode_|Equal34~0_combout & (\z80_|execute_|ctl_reg_sel_wz~8_combout & !\z80_|execute_|ctl_mRead~7_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ),
|
|
.datab(\z80_|pla_decode_|Equal34~0_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_sel_wz~8_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~7_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_al_we~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_al_we~5 .lut_mask = 16'h0020;
|
|
defparam \z80_|execute_|ctl_al_we~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y15_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_al_we~4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_al_we~4_combout = (!\z80_|execute_|ctl_mRead~2_combout & (!\z80_|execute_|ixy_d~10_combout & (!\z80_|execute_|ixy_d~16_combout & !\z80_|execute_|ctl_mRead~3_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_mRead~2_combout ),
|
|
.datab(\z80_|execute_|ixy_d~10_combout ),
|
|
.datac(\z80_|execute_|ixy_d~16_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~3_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_al_we~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_al_we~4 .lut_mask = 16'h0001;
|
|
defparam \z80_|execute_|ctl_al_we~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y12_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~41 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_hilo[1]~41_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_al_we~4_combout ))))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal34~0_combout ),
|
|
.datab(\z80_|sequencer_|DFFE_M2_ff~q ),
|
|
.datac(\z80_|execute_|ctl_al_we~4_combout ),
|
|
.datad(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_hilo[1]~41_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~41 .lut_mask = 16'h008C;
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~41 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y15_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~10 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sel_wz~10_combout = (!\z80_|execute_|ctl_ir_we~8_combout & (!\z80_|execute_|ctl_mRead~13_combout & !\z80_|execute_|ctl_ir_we~14_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_ir_we~8_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_mRead~13_combout ),
|
|
.datad(\z80_|execute_|ctl_ir_we~14_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sel_wz~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sel_wz~10 .lut_mask = 16'h0005;
|
|
defparam \z80_|execute_|ctl_reg_sel_wz~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y13_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo~21 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_hilo~21_combout = (\z80_|ir_|opcode [5]) # ((!\z80_|pla_decode_|Equal6~0_combout ) # (!\z80_|pla_decode_|Equal55~0_combout ))
|
|
|
|
.dataa(\z80_|ir_|opcode [5]),
|
|
.datab(\z80_|pla_decode_|Equal55~0_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|pla_decode_|Equal6~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_hilo~21_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo~21 .lut_mask = 16'hBBFF;
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo~21 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y13_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~3 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_dec~3_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q )
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_M3_ff~q ),
|
|
.datab(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.datac(gnd),
|
|
.datad(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_dec~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_dec~3 .lut_mask = 16'h7755;
|
|
defparam \z80_|execute_|ctl_inc_dec~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y13_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~22 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_hilo[1]~22_combout = (\z80_|execute_|ctl_reg_sys_hilo~21_combout & (((\z80_|execute_|ctl_inc_dec~3_combout ) # (!\z80_|pla_decode_|Equal33~3_combout )))) # (!\z80_|execute_|ctl_reg_sys_hilo~21_combout &
|
|
// (!\z80_|execute_|ctl_alu_op_low~22_combout & ((\z80_|execute_|ctl_inc_dec~3_combout ) # (!\z80_|pla_decode_|Equal33~3_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_sys_hilo~21_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_op_low~22_combout ),
|
|
.datac(\z80_|pla_decode_|Equal33~3_combout ),
|
|
.datad(\z80_|execute_|ctl_inc_dec~3_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .lut_mask = 16'hBB0B;
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~22 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y15_N2
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~23 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_hilo[1]~23_combout = (!\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout & ((\z80_|execute_|ctl_reg_sel_wz~10_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout
|
|
// ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_sel_wz~10_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_sys_hilo_nuse_ixiypla72pla55M2T3_3~combout ),
|
|
.datac(\z80_|execute_|ctl_ir_we~4_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sys_hilo[1]~22_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .lut_mask = 16'h2300;
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~23 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y11_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~24 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_hilo[1]~24_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout & (((!\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|pc_inc_hold~26_combout )) # (!\z80_|execute_|ixy_d~5_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal6~1_combout ),
|
|
.datab(\z80_|execute_|pc_inc_hold~26_combout ),
|
|
.datac(\z80_|execute_|ixy_d~5_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sys_hilo[1]~23_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .lut_mask = 16'h4F00;
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~24 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y15_N6
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~19 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_hilo[1]~19_combout = (!\z80_|execute_|ctl_reg_sel_wz~8_combout & ((\z80_|execute_|ctl_state_alu~3_combout ) # ((\z80_|execute_|ctl_alu_oe~0_combout ) # (\z80_|execute_|ctl_ir_we~4_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_state_alu~3_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_oe~0_combout ),
|
|
.datac(\z80_|execute_|ctl_ir_we~4_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sel_wz~8_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .lut_mask = 16'h00FE;
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~19 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y11_N28
|
|
cycloneive_lcell_comb \z80_|execute_|fMRead~2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fMRead~2_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|DFFE_M2_ff~q )
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datab(gnd),
|
|
.datac(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.datad(\z80_|sequencer_|DFFE_M2_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fMRead~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fMRead~2 .lut_mask = 16'h0AFF;
|
|
defparam \z80_|execute_|fMRead~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y11_N24
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~20 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_hilo[1]~20_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout & ((\z80_|execute_|fMRead~2_combout ) # ((\z80_|execute_|pc_inc_hold~6_combout & !\z80_|execute_|ctl_mRead~7_combout ))))
|
|
|
|
.dataa(\z80_|execute_|pc_inc_hold~6_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_sys_hilo[1]~19_combout ),
|
|
.datac(\z80_|execute_|ctl_mRead~7_combout ),
|
|
.datad(\z80_|execute_|fMRead~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_hilo[1]~20_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~20 .lut_mask = 16'h3302;
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~20 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y16_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~26 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_hilo[1]~26_combout = (!\z80_|pla_decode_|Equal52~1_combout & (!\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ctl_bus_db_oe~1_combout ))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal52~1_combout ),
|
|
.datab(\z80_|pla_decode_|Equal6~1_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|execute_|ctl_bus_db_oe~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .lut_mask = 16'h1100;
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~26 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y11_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~27 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_hilo[1]~27_combout = (!\z80_|execute_|fMRead~2_combout & ((!\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ),
|
|
.datab(\z80_|execute_|fMRead~2_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|execute_|ctl_reg_sys_hilo[1]~25_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .lut_mask = 16'h1133;
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~27 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y11_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~28 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_hilo[1]~28_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~20_combout & (!\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout & \z80_|resets_|SYNTHESIZED_WIRE_11~combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~24_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_sys_hilo[1]~20_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_sys_hilo[1]~27_combout ),
|
|
.datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .lut_mask = 16'h0800;
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~28 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y12_N24
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~29 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout = (!\z80_|execute_|ctl_reg_sys_hilo[1]~41_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout & ((\z80_|execute_|ctl_al_we~5_combout ) # (!\z80_|execute_|ixy_d~7_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_al_we~5_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_sys_hilo[1]~41_combout ),
|
|
.datac(\z80_|execute_|ixy_d~7_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sys_hilo[1]~28_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~29 .lut_mask = 16'h2300;
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~29 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y12_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~30 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_hilo[1]~30_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout & (\z80_|execute_|ctl_reg_sel_pc~13_combout & (\z80_|execute_|ctl_reg_sel_wz~9_combout & \z80_|execute_|ctl_reg_sys_hilo[1]~29_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~16_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_sel_pc~13_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_sel_wz~9_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sys_hilo[1]~29_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~30 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y12_N26
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~13 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sel_wz~13_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ixy_d~6_combout & ((!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & (((!\z80_|pla_decode_|Equal19~0_combout )) #
|
|
// (!\z80_|execute_|ixy_d~6_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal9~1_combout ),
|
|
.datab(\z80_|execute_|ixy_d~6_combout ),
|
|
.datac(\z80_|pla_decode_|Equal19~0_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_in_hi~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sel_wz~13_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sel_wz~13 .lut_mask = 16'h1537;
|
|
defparam \z80_|execute_|ctl_reg_sel_wz~13 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y12_N28
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~32 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_hilo[1]~32_combout = ((\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ) # ((\z80_|pla_decode_|Equal35~0_combout & \z80_|execute_|ixy_d~6_combout ))) # (!\z80_|execute_|ctl_reg_in_lo~9_combout )
|
|
|
|
.dataa(\z80_|pla_decode_|Equal35~0_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_in_lo~9_combout ),
|
|
.datac(\z80_|execute_|ixy_d~6_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .lut_mask = 16'hFFB3;
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~32 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y19_N24
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~33 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_hilo[1]~33_combout = (!\z80_|ir_|opcode [3] & ((\z80_|execute_|ctl_alu_op_low~28_combout ) # ((\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|ctl_eval_cond~0_combout ))))
|
|
|
|
.dataa(\z80_|ir_|opcode [3]),
|
|
.datab(\z80_|execute_|ctl_alu_op_low~28_combout ),
|
|
.datac(\z80_|pla_decode_|Equal48~0_combout ),
|
|
.datad(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .lut_mask = 16'h5444;
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~33 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y19_N6
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~34 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_hilo[1]~34_combout = (((\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ) # (\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_out_hi~4_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_sys_hilo[1]~32_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sys_hilo[1]~33_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .lut_mask = 16'hFFF7;
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~34 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y12_N24
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~35 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout = (((\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_in_hi~5_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_sel_wz~13_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sys_hilo[1]~34_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .lut_mask = 16'hFF7F;
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~35 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y12_N22
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_73 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_73~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ))
|
|
|
|
.dataa(\z80_|reg_control_|reg_sel_pc~combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|reg_control_|reg_sys_we_hi~combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .lut_mask = 16'hA000;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_73 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y14_N5
|
|
dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[3] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_file_|db_hi_as[3]~12_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y12_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~0 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sel_ir~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.datac(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.datad(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sel_ir~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sel_ir~0 .lut_mask = 16'h0F0C;
|
|
defparam \z80_|execute_|ctl_reg_sel_ir~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y12_N2
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_ir~1 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sel_ir~1_combout = (\z80_|execute_|ctl_reg_sel_ir~0_combout ) # (((\z80_|execute_|ctl_eval_cond~0_combout & !\z80_|execute_|ctl_flags_bus~0_combout )) # (!\z80_|execute_|ctl_reg_in_lo~9_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_bus~0_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_sel_ir~0_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_in_lo~9_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sel_ir~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sel_ir~1 .lut_mask = 16'hF2FF;
|
|
defparam \z80_|execute_|ctl_reg_sel_ir~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y12_N16
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_60 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_60~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (!\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sel_ir~1_combout ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ),
|
|
.datac(\z80_|reg_control_|reg_sys_we_hi~combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .lut_mask = 16'h0C00;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_60 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y12_N20
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_61 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_61~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sel_ir~1_combout ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ),
|
|
.datac(\z80_|reg_control_|reg_sys_we_hi~combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .lut_mask = 16'hC000;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_61 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y14_N15
|
|
dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[3] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|db_hi_as[3]~12_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y14_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_we_lo~4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_we_lo~4_combout = (\z80_|execute_|ctl_reg_sys_we_lo~3_combout & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|sequencer_|DFFE_M2_ff~q ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|execute_|ctl_reg_sys_we_lo~3_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.datad(\z80_|sequencer_|DFFE_M2_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_we_lo~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_we_lo~4 .lut_mask = 16'hC000;
|
|
defparam \z80_|execute_|ctl_reg_sys_we_lo~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y14_N22
|
|
cycloneive_lcell_comb \z80_|reg_control_|reg_sys_we_lo (
|
|
// Equation(s):
|
|
// \z80_|reg_control_|reg_sys_we_lo~combout = ((\z80_|execute_|ctl_reg_sys_we_lo~4_combout ) # ((\z80_|execute_|ctl_reg_sys_we~3_combout ) # (!\z80_|reg_control_|reg_sys_we_lo~4_combout ))) # (!\z80_|reg_control_|reg_sys_we_lo~7_combout )
|
|
|
|
.dataa(\z80_|reg_control_|reg_sys_we_lo~7_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_sys_we_lo~4_combout ),
|
|
.datac(\z80_|reg_control_|reg_sys_we_lo~4_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sys_we~3_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_control_|reg_sys_we_lo~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_control_|reg_sys_we_lo .lut_mask = 16'hFFDF;
|
|
defparam \z80_|reg_control_|reg_sys_we_lo .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y12_N2
|
|
cycloneive_lcell_comb \z80_|reg_control_|reg_sw_4d_hi~0 (
|
|
// Equation(s):
|
|
// \z80_|reg_control_|reg_sw_4d_hi~0_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_control_|reg_sys_we_lo~combout ) # (!\z80_|execute_|ctl_reg_sel_ir~1_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_sw_4d~6_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ),
|
|
.datac(\z80_|reg_control_|reg_sys_we_lo~combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_control_|reg_sw_4d_hi~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_control_|reg_sw_4d_hi~0 .lut_mask = 16'hA2AA;
|
|
defparam \z80_|reg_control_|reg_sw_4d_hi~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y14_N14
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~10 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_hi_as[3]~10_combout = (\z80_|reg_file_|gdfx_temp1[3]~48_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))) # (!\z80_|reg_file_|gdfx_temp1[3]~48_combout &
|
|
// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|gdfx_temp1[3]~48_combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [3]),
|
|
.datad(\z80_|reg_control_|reg_sw_4d_hi~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_hi_as[3]~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_hi_as[3]~10 .lut_mask = 16'hA2F3;
|
|
defparam \z80_|reg_file_|db_hi_as[3]~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y14_N26
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~11 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_hi_as[3]~11_combout = (\z80_|reg_file_|db_hi_as[3]~10_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout )))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [3]),
|
|
.datad(\z80_|reg_file_|db_hi_as[3]~10_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_hi_as[3]~11_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_hi_as[3]~11 .lut_mask = 16'hF300;
|
|
defparam \z80_|reg_file_|db_hi_as[3]~11 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y13_N14
|
|
cycloneive_lcell_comb \z80_|address_latch_|abusz[11] (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|abusz [11] = (\z80_|reg_file_|db_hi_as[3]~12_combout & !\z80_|resets_|clrpc~0_combout )
|
|
|
|
.dataa(\z80_|reg_file_|db_hi_as[3]~12_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|resets_|clrpc~0_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|abusz [11]),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|abusz[11] .lut_mask = 16'h0A0A;
|
|
defparam \z80_|address_latch_|abusz[11] .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y12_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~1 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_apin_mux~1_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (\z80_|sequencer_|DFFE_M2_ff~q )))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_M3_ff~q ),
|
|
.datab(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datac(\z80_|sequencer_|DFFE_M2_ff~q ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_apin_mux~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_apin_mux~1 .lut_mask = 16'h3232;
|
|
defparam \z80_|execute_|ctl_apin_mux~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y18_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~37 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~37_combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|pla_decode_|Equal47~0_combout & ((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout
|
|
// & (((!\z80_|execute_|ctl_state_alu~4_combout ) # (!\z80_|pla_decode_|Equal34~0_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_state_alu~2_combout ),
|
|
.datab(\z80_|pla_decode_|Equal47~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal34~0_combout ),
|
|
.datad(\z80_|execute_|ctl_state_alu~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~37_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~37 .lut_mask = 16'h0777;
|
|
defparam \z80_|execute_|ctl_inc_cy~37 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y18_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_dec~2_combout = (\z80_|execute_|ctl_inc_cy~37_combout & (((!\z80_|pla_decode_|Equal9~1_combout & !\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal9~1_combout ),
|
|
.datab(\z80_|execute_|ctl_state_alu~4_combout ),
|
|
.datac(\z80_|pla_decode_|Equal19~0_combout ),
|
|
.datad(\z80_|execute_|ctl_inc_cy~37_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_dec~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_dec~2 .lut_mask = 16'h3700;
|
|
defparam \z80_|execute_|ctl_inc_dec~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y18_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~40 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~40_combout = (\z80_|pla_decode_|Equal34~0_combout & (!\z80_|execute_|ixy_d~9_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|pla_decode_|Equal47~0_combout )))) # (!\z80_|pla_decode_|Equal34~0_combout &
|
|
// (((!\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|pla_decode_|Equal47~0_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal34~0_combout ),
|
|
.datab(\z80_|pla_decode_|Equal47~0_combout ),
|
|
.datac(\z80_|execute_|ctl_mRead~9_combout ),
|
|
.datad(\z80_|execute_|ixy_d~9_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~40_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~40 .lut_mask = 16'h153F;
|
|
defparam \z80_|execute_|ctl_inc_cy~40 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y18_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_dec~4_combout = (\z80_|execute_|ctl_inc_cy~40_combout & (((!\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|pla_decode_|Equal19~0_combout )) # (!\z80_|sequencer_|DFFE_M3_ff~q )))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_M3_ff~q ),
|
|
.datab(\z80_|execute_|ctl_inc_cy~40_combout ),
|
|
.datac(\z80_|pla_decode_|Equal19~0_combout ),
|
|
.datad(\z80_|sequencer_|DFFE_T4_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_dec~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_dec~4 .lut_mask = 16'h4CCC;
|
|
defparam \z80_|execute_|ctl_inc_dec~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y18_N16
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~5 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_dec~5_combout = (\z80_|execute_|ctl_inc_dec~2_combout & (\z80_|execute_|ctl_inc_dec~4_combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal9~1_combout ))))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal9~1_combout ),
|
|
.datab(\z80_|execute_|ctl_inc_dec~2_combout ),
|
|
.datac(\z80_|execute_|ctl_inc_dec~4_combout ),
|
|
.datad(\z80_|execute_|ixy_d~9_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_dec~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_dec~5 .lut_mask = 16'h40C0;
|
|
defparam \z80_|execute_|ctl_inc_dec~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y17_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_sel[1]~4_combout = (\z80_|execute_|ctl_inc_dec~5_combout & (((!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ctl_mRead~9_combout )) # (!\z80_|execute_|ctl_mWrite~6_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_state_alu~2_combout ),
|
|
.datab(\z80_|execute_|ctl_mWrite~6_combout ),
|
|
.datac(\z80_|execute_|ctl_inc_dec~5_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~9_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .lut_mask = 16'h3070;
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[1]~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y12_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|pla_decode_|Equal2~1_combout & (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1])))
|
|
|
|
.dataa(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.datab(\z80_|pla_decode_|Equal2~1_combout ),
|
|
.datac(\z80_|ir_|opcode [2]),
|
|
.datad(\z80_|ir_|opcode [1]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .lut_mask = 16'h0008;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y12_N18
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~42 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~42_combout = (!\z80_|pla_decode_|Equal4~0_combout & ((!\z80_|pla_decode_|Equal8~0_combout ) # (!\z80_|pla_decode_|Equal6~0_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal6~0_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|pla_decode_|Equal4~0_combout ),
|
|
.datad(\z80_|pla_decode_|Equal8~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~42_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~42 .lut_mask = 16'h050F;
|
|
defparam \z80_|execute_|setM1~42 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y12_N16
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~12 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo[1]~12_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & (!\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout & ((\z80_|execute_|setM1~42_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ),
|
|
.datab(\z80_|execute_|setM1~42_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_sel_pla12M3T1_2~combout ),
|
|
.datad(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo[1]~12_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~12 .lut_mask = 16'h0405;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~12 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y15_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_sw_1d~4_combout = (\z80_|execute_|ixy_d~7_combout & (!\z80_|execute_|ctl_mRead~2_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_mRead~3_combout )))) # (!\z80_|execute_|ixy_d~7_combout &
|
|
// (((!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|execute_|ctl_mRead~3_combout )))
|
|
|
|
.dataa(\z80_|execute_|ixy_d~7_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~3_combout ),
|
|
.datac(\z80_|execute_|ctl_state_alu~2_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_sw_1d~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_sw_1d~4 .lut_mask = 16'h153F;
|
|
defparam \z80_|execute_|ctl_sw_1d~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y14_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~3 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_sw_4d~3_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~12_combout & \z80_|execute_|ctl_sw_1d~4_combout ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_hilo[1]~12_combout ),
|
|
.datad(\z80_|execute_|ctl_sw_1d~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_sw_4d~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_sw_4d~3 .lut_mask = 16'hC000;
|
|
defparam \z80_|execute_|ctl_sw_4d~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y14_N8
|
|
cycloneive_lcell_comb \z80_|execute_|fMRead~9 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fMRead~9_combout = (\z80_|execute_|ctl_mRead~14_combout & (((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_state_alu~3_combout )))) # (!\z80_|execute_|ctl_mRead~14_combout & (((!\z80_|execute_|ixy_d~7_combout &
|
|
// !\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|pla_decode_|Equal37~0_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_mRead~14_combout ),
|
|
.datab(\z80_|pla_decode_|Equal37~0_combout ),
|
|
.datac(\z80_|execute_|ixy_d~7_combout ),
|
|
.datad(\z80_|execute_|ctl_state_alu~3_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fMRead~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fMRead~9 .lut_mask = 16'h111F;
|
|
defparam \z80_|execute_|fMRead~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y14_N2
|
|
cycloneive_lcell_comb \z80_|execute_|fMRead~10 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fMRead~10_combout = (\z80_|execute_|fMRead~9_combout & (((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|pla_decode_|Equal38~2_combout )))
|
|
|
|
.dataa(\z80_|execute_|ixy_d~7_combout ),
|
|
.datab(\z80_|execute_|fMRead~9_combout ),
|
|
.datac(\z80_|pla_decode_|Equal38~2_combout ),
|
|
.datad(\z80_|execute_|ctl_state_alu~3_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fMRead~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fMRead~10 .lut_mask = 16'h0C4C;
|
|
defparam \z80_|execute_|fMRead~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y14_N24
|
|
cycloneive_lcell_comb \z80_|execute_|fMRead~8 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fMRead~8_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_state_alu~3_combout & (!\z80_|execute_|ixy_d~7_combout ))) # (!\z80_|pla_decode_|Equal9~1_combout & (((!\z80_|execute_|ctl_state_alu~3_combout &
|
|
// !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal29~0_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal9~1_combout ),
|
|
.datab(\z80_|execute_|ctl_state_alu~3_combout ),
|
|
.datac(\z80_|execute_|ixy_d~7_combout ),
|
|
.datad(\z80_|pla_decode_|Equal29~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fMRead~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fMRead~8 .lut_mask = 16'h0357;
|
|
defparam \z80_|execute_|fMRead~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y14_N2
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_sw_4d~2_combout = (\z80_|execute_|fMRead~10_combout & (\z80_|execute_|fMRead~8_combout & \z80_|execute_|ctl_reg_in_lo~9_combout ))
|
|
|
|
.dataa(\z80_|execute_|fMRead~10_combout ),
|
|
.datab(\z80_|execute_|fMRead~8_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|execute_|ctl_reg_in_lo~9_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_sw_4d~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_sw_4d~2 .lut_mask = 16'h8800;
|
|
defparam \z80_|execute_|ctl_sw_4d~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y15_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~11 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sel_wz~11_combout = (\z80_|execute_|ctl_reg_sel_wz~8_combout & (((\z80_|execute_|ctl_reg_sel_wz~10_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout )))) # (!\z80_|execute_|ctl_reg_sel_wz~8_combout &
|
|
// (!\z80_|execute_|ctl_alu_oe~0_combout & (!\z80_|execute_|ctl_ir_we~4_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_sel_wz~8_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_oe~0_combout ),
|
|
.datac(\z80_|execute_|ctl_ir_we~4_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sel_wz~10_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sel_wz~11_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sel_wz~11 .lut_mask = 16'hAB0B;
|
|
defparam \z80_|execute_|ctl_reg_sel_wz~11 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y12_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~12 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sel_wz~12_combout = (\z80_|execute_|ctl_reg_sel_wz~9_combout & \z80_|execute_|ctl_reg_sel_wz~11_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_reg_sel_wz~9_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sel_wz~11_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sel_wz~12_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sel_wz~12 .lut_mask = 16'hF000;
|
|
defparam \z80_|execute_|ctl_reg_sel_wz~12 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y13_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_sw_4d~4_combout = (\z80_|pla_decode_|Equal9~1_combout & (!\z80_|execute_|ctl_reg_in_hi~2_combout & ((\z80_|execute_|ctl_flags_bus~1_combout ) # (!\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout &
|
|
// (((\z80_|execute_|ctl_flags_bus~1_combout )) # (!\z80_|execute_|ixy_d~6_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal9~1_combout ),
|
|
.datab(\z80_|execute_|ixy_d~6_combout ),
|
|
.datac(\z80_|execute_|ctl_flags_bus~1_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_in_hi~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_sw_4d~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_sw_4d~4 .lut_mask = 16'h51F3;
|
|
defparam \z80_|execute_|ctl_sw_4d~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y12_N24
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~5 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_sw_4d~5_combout = (\z80_|execute_|ctl_sw_4d~3_combout & (\z80_|execute_|ctl_sw_4d~2_combout & (\z80_|execute_|ctl_reg_sel_wz~12_combout & \z80_|execute_|ctl_sw_4d~4_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_sw_4d~3_combout ),
|
|
.datab(\z80_|execute_|ctl_sw_4d~2_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_sel_wz~12_combout ),
|
|
.datad(\z80_|execute_|ctl_sw_4d~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_sw_4d~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_sw_4d~5 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|ctl_sw_4d~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y12_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_al_we~14 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_al_we~14_combout = (!\z80_|execute_|ctl_mRead~5_combout & ((\z80_|ir_|opcode [2]) # ((!\z80_|ir_|opcode [1]) # (!\z80_|execute_|ctl_mWrite~4_combout ))))
|
|
|
|
.dataa(\z80_|ir_|opcode [2]),
|
|
.datab(\z80_|execute_|ctl_mWrite~4_combout ),
|
|
.datac(\z80_|execute_|ctl_mRead~5_combout ),
|
|
.datad(\z80_|ir_|opcode [1]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_al_we~14_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_al_we~14 .lut_mask = 16'h0B0F;
|
|
defparam \z80_|execute_|ctl_al_we~14 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y12_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_al_we~10 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_al_we~10_combout = ((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~5_combout )) # (!\z80_|execute_|ctl_al_we~14_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_al_we~14_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|pla_decode_|Equal33~3_combout ),
|
|
.datad(\z80_|execute_|ctl_al_we~5_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_al_we~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_al_we~10 .lut_mask = 16'hF5FF;
|
|
defparam \z80_|execute_|ctl_al_we~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y12_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_al_we~6 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_al_we~6_combout = (\z80_|execute_|ctl_ir_we~4_combout & (((!\z80_|execute_|ctl_al_we~13_combout )) # (!\z80_|execute_|ctl_flags_bus~1_combout ))) # (!\z80_|execute_|ctl_ir_we~4_combout & (\z80_|execute_|ctl_state_alu~4_combout &
|
|
// ((!\z80_|execute_|ctl_al_we~13_combout ) # (!\z80_|execute_|ctl_flags_bus~1_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_ir_we~4_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_bus~1_combout ),
|
|
.datac(\z80_|execute_|ctl_state_alu~4_combout ),
|
|
.datad(\z80_|execute_|ctl_al_we~13_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_al_we~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_al_we~6 .lut_mask = 16'h32FA;
|
|
defparam \z80_|execute_|ctl_al_we~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y13_N6
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_al_we~7 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_al_we~7_combout = ((\z80_|execute_|ctl_al_we~6_combout ) # ((\z80_|pla_decode_|Equal35~0_combout & \z80_|execute_|ixy_d~6_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )
|
|
|
|
.dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ),
|
|
.datab(\z80_|execute_|ctl_al_we~6_combout ),
|
|
.datac(\z80_|pla_decode_|Equal35~0_combout ),
|
|
.datad(\z80_|execute_|ixy_d~6_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_al_we~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_al_we~7 .lut_mask = 16'hFDDD;
|
|
defparam \z80_|execute_|ctl_al_we~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y12_N18
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_al_we~8 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_al_we~8_combout = (((!\z80_|execute_|ctl_al_we~4_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~31_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout )) # (!\z80_|execute_|ctl_alu_oe~3_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_oe~3_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_sys_hilo[1]~26_combout ),
|
|
.datac(\z80_|execute_|ctl_bus_inc_oe~31_combout ),
|
|
.datad(\z80_|execute_|ctl_al_we~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_al_we~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_al_we~8 .lut_mask = 16'h7FFF;
|
|
defparam \z80_|execute_|ctl_al_we~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y12_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_al_we~9 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_al_we~9_combout = (\z80_|execute_|ctl_al_we~7_combout ) # ((\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|execute_|ctl_al_we~8_combout ) # (!\z80_|execute_|setM1~47_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_al_we~7_combout ),
|
|
.datab(\z80_|execute_|ctl_state_alu~3_combout ),
|
|
.datac(\z80_|execute_|setM1~47_combout ),
|
|
.datad(\z80_|execute_|ctl_al_we~8_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_al_we~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_al_we~9 .lut_mask = 16'hEEAE;
|
|
defparam \z80_|execute_|ctl_al_we~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y12_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_al_we~11 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_al_we~11_combout = ((\z80_|execute_|ctl_al_we~9_combout ) # ((\z80_|execute_|ctl_apin_mux~1_combout & \z80_|execute_|ctl_al_we~10_combout ))) # (!\z80_|execute_|ctl_sw_4d~5_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_apin_mux~1_combout ),
|
|
.datab(\z80_|execute_|ctl_sw_4d~5_combout ),
|
|
.datac(\z80_|execute_|ctl_al_we~10_combout ),
|
|
.datad(\z80_|execute_|ctl_al_we~9_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_al_we~11_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_al_we~11 .lut_mask = 16'hFFB3;
|
|
defparam \z80_|execute_|ctl_al_we~11 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y12_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_al_we~12 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_al_we~12_combout = ((\z80_|execute_|ctl_al_we~11_combout ) # ((\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ixy_d~7_combout ))) # (!\z80_|execute_|setM1~54_combout )
|
|
|
|
.dataa(\z80_|execute_|setM1~54_combout ),
|
|
.datab(\z80_|pla_decode_|Equal6~1_combout ),
|
|
.datac(\z80_|execute_|ctl_al_we~11_combout ),
|
|
.datad(\z80_|execute_|ixy_d~7_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_al_we~12_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_al_we~12 .lut_mask = 16'hFDF5;
|
|
defparam \z80_|execute_|ctl_al_we~12 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y13_N15
|
|
dffeas \z80_|address_latch_|Q[11] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|address_latch_|abusz [11]),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|execute_|ctl_al_we~12_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|address_latch_|Q [11]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|Q[11] .is_wysiwyg = "true";
|
|
defparam \z80_|address_latch_|Q[11] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y19_N24
|
|
cycloneive_lcell_comb \z80_|execute_|fIOWrite~0 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fIOWrite~0_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q ))) # (!\z80_|sequencer_|DFFE_M2_ff~q )
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datab(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.datac(\z80_|sequencer_|DFFE_M2_ff~q ),
|
|
.datad(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fIOWrite~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fIOWrite~0 .lut_mask = 16'h0F2F;
|
|
defparam \z80_|execute_|fIOWrite~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y17_N24
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~8 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_dec~8_combout = (\z80_|execute_|ctl_mWrite~6_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((!\z80_|execute_|ctl_inc_dec~3_combout ) # (!\z80_|execute_|fIOWrite~0_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_mRead~9_combout ),
|
|
.datab(\z80_|execute_|fIOWrite~0_combout ),
|
|
.datac(\z80_|execute_|ctl_mWrite~6_combout ),
|
|
.datad(\z80_|execute_|ctl_inc_dec~3_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_dec~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_dec~8 .lut_mask = 16'hB0F0;
|
|
defparam \z80_|execute_|ctl_inc_dec~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y18_N6
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_we~2_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & (\z80_|execute_|ctl_bus_inc_oe~45_combout & ((!\z80_|execute_|ctl_mWrite~17_combout ) # (!\z80_|execute_|ixy_d~5_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ixy_d~5_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ),
|
|
.datac(\z80_|execute_|ctl_bus_inc_oe~45_combout ),
|
|
.datad(\z80_|execute_|ctl_mWrite~17_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_we~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_we~2 .lut_mask = 16'h40C0;
|
|
defparam \z80_|execute_|ctl_reg_gp_we~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y17_N6
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~9 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_dec~9_combout = ((\z80_|execute_|ctl_inc_dec~8_combout ) # ((!\z80_|execute_|ctl_reg_gp_we~2_combout & \z80_|ir_|opcode [3]))) # (!\z80_|execute_|ctl_inc_dec~12_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_inc_dec~12_combout ),
|
|
.datab(\z80_|execute_|ctl_inc_dec~8_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_we~2_combout ),
|
|
.datad(\z80_|ir_|opcode [3]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_dec~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_dec~9 .lut_mask = 16'hDFDD;
|
|
defparam \z80_|execute_|ctl_inc_dec~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y11_N22
|
|
cycloneive_lcell_comb \z80_|address_latch_|abusz[1] (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|abusz [1] = (\z80_|reg_file_|db_lo_as[1]~6_combout & !\z80_|resets_|clrpc~0_combout )
|
|
|
|
.dataa(\z80_|reg_file_|db_lo_as[1]~6_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|resets_|clrpc~0_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|abusz [1]),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|abusz[1] .lut_mask = 16'h0A0A;
|
|
defparam \z80_|address_latch_|abusz[1] .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y11_N23
|
|
dffeas \z80_|address_latch_|Q[1] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|address_latch_|abusz [1]),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|execute_|ctl_al_we~12_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|address_latch_|Q [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|Q[1] .is_wysiwyg = "true";
|
|
defparam \z80_|address_latch_|Q[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y18_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~0 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_apin_mux~0_combout = (\z80_|execute_|ctl_inc_cy~32_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout & ((!\z80_|pla_decode_|Equal19~0_combout ) # (!\z80_|execute_|ctl_alu_oe~0_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_inc_cy~32_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_sys_hilo[1]~37_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_oe~0_combout ),
|
|
.datad(\z80_|pla_decode_|Equal19~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_apin_mux~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_apin_mux~0 .lut_mask = 16'h0888;
|
|
defparam \z80_|execute_|ctl_apin_mux~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y12_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~6 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_dec~6_combout = (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout & (\z80_|execute_|ctl_apin_mux~0_combout & ((!\z80_|pla_decode_|Equal9~1_combout ) # (!\z80_|execute_|ctl_ir_we~4_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_ir_we~4_combout ),
|
|
.datab(\z80_|pla_decode_|Equal9~1_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ),
|
|
.datad(\z80_|execute_|ctl_apin_mux~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_dec~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_dec~6 .lut_mask = 16'h0700;
|
|
defparam \z80_|execute_|ctl_inc_dec~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y11_N28
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~7 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_dec~7_combout = (!\z80_|execute_|ctl_bus_inc_oe~42_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_inc_dec~5_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_bus_inc_oe~42_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_dec~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_dec~7 .lut_mask = 16'h5F5F;
|
|
defparam \z80_|execute_|ctl_inc_dec~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y11_N6
|
|
cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout = \z80_|address_latch_|Q [1] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_inc_dec~9_combout ),
|
|
.datab(\z80_|address_latch_|Q [1]),
|
|
.datac(\z80_|execute_|ctl_inc_dec~6_combout ),
|
|
.datad(\z80_|execute_|ctl_inc_dec~7_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h3363;
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y16_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~21 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sel_wz~21_combout = (\z80_|reg_control_|reg_sys_we_lo~6_combout & (\z80_|execute_|ctl_mRead~20_combout & ((!\z80_|execute_|ixy_d~15_combout ) # (!\z80_|sequencer_|DFFE_T3_ff~q ))))
|
|
|
|
.dataa(\z80_|reg_control_|reg_sys_we_lo~6_combout ),
|
|
.datab(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.datac(\z80_|execute_|ixy_d~15_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~20_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sel_wz~21_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sel_wz~21 .lut_mask = 16'h2A00;
|
|
defparam \z80_|execute_|ctl_reg_sel_wz~21 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y12_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~40 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_hilo[0]~40_combout = (\z80_|execute_|ctl_reg_sel_wz~20_combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|M5~q & \z80_|pla_decode_|Equal9~1_combout )))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.datab(\z80_|sequencer_|M5~q ),
|
|
.datac(\z80_|execute_|ctl_reg_sel_wz~20_combout ),
|
|
.datad(\z80_|pla_decode_|Equal9~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_hilo[0]~40_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[0]~40 .lut_mask = 16'hF8F0;
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[0]~40 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y19_N26
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~39 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_hilo[1]~39_combout = (\z80_|execute_|ctl_alu_op_low~28_combout ) # ((\z80_|sequencer_|DFFE_T4_ff~q & (\z80_|pla_decode_|Equal48~0_combout & !\z80_|sequencer_|DFFE_M1_ff~q )))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T4_ff~q ),
|
|
.datab(\z80_|execute_|ctl_alu_op_low~28_combout ),
|
|
.datac(\z80_|pla_decode_|Equal48~0_combout ),
|
|
.datad(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_hilo[1]~39_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~39 .lut_mask = 16'hCCEC;
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~39 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y19_N2
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~13 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_hilo[0]~13_combout = (((\z80_|execute_|ctl_reg_sys_hilo[1]~39_combout & \z80_|ir_|opcode [3])) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout )) # (!\z80_|execute_|ctl_reg_out_lo~9_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~39_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_out_lo~9_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ),
|
|
.datad(\z80_|ir_|opcode [3]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_hilo[0]~13_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[0]~13 .lut_mask = 16'hBF3F;
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[0]~13 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y12_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[0]~31 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_hilo[0]~31_combout = (((\z80_|execute_|ctl_reg_sys_hilo[0]~40_combout ) # (\z80_|execute_|ctl_reg_sys_hilo[0]~13_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~21_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~30_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_sel_wz~21_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_sys_hilo[0]~40_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sys_hilo[0]~13_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[0]~31 .lut_mask = 16'hFFF7;
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[0]~31 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y12_N12
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_63 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_63~combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout & (\z80_|reg_control_|reg_sys_we_lo~combout & \z80_|execute_|ctl_reg_sel_ir~1_combout ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ),
|
|
.datac(\z80_|reg_control_|reg_sys_we_lo~combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .lut_mask = 16'hC000;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_63 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y12_N9
|
|
dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[2] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_file_|db_lo_as[2]~9_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y13_N4
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~49 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~49_combout = (!\z80_|execute_|ctl_ir_we~11_combout & (!\z80_|pla_decode_|Equal69~0_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal21~0_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_ir_we~11_combout ),
|
|
.datab(\z80_|pla_decode_|Equal21~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal69~0_combout ),
|
|
.datad(\z80_|pla_decode_|Equal63~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~49_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~49 .lut_mask = 16'h0105;
|
|
defparam \z80_|execute_|setM1~49 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y14_N28
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout = (!\z80_|pla_decode_|Equal20~0_combout & !\z80_|execute_|ctl_ir_we~8_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|pla_decode_|Equal20~0_combout ),
|
|
.datad(\z80_|execute_|ctl_ir_we~8_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .lut_mask = 16'h000F;
|
|
defparam \z80_|execute_|ctl_flags_cf2_sel_shift~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y13_N26
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~50 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~50_combout = (\z80_|execute_|ctl_flags_hf_cpl~10_combout & (\z80_|execute_|nextM~2_combout & (\z80_|execute_|setM1~49_combout & \z80_|execute_|ctl_flags_cf2_sel_shift~2_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_hf_cpl~10_combout ),
|
|
.datab(\z80_|execute_|nextM~2_combout ),
|
|
.datac(\z80_|execute_|setM1~49_combout ),
|
|
.datad(\z80_|execute_|ctl_flags_cf2_sel_shift~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~50_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~50 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|setM1~50 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y14_N26
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~0 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_oe~0_combout = (!\z80_|execute_|ctl_iorw~11_combout & (!\z80_|execute_|ctl_mRead~4_combout & (!\z80_|execute_|ctl_ir_we~14_combout & !\z80_|execute_|ctl_ir_we~12_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_iorw~11_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~4_combout ),
|
|
.datac(\z80_|execute_|ctl_ir_we~14_combout ),
|
|
.datad(\z80_|execute_|ctl_ir_we~12_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_oe~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_oe~0 .lut_mask = 16'h0001;
|
|
defparam \z80_|execute_|ctl_flags_oe~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y12_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~1 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_oe~1_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|execute_|ctl_flags_bus~1_combout & (\z80_|execute_|ctl_flags_oe~0_combout & !\z80_|pla_decode_|Equal13~2_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_al_we~13_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_bus~1_combout ),
|
|
.datac(\z80_|execute_|ctl_flags_oe~0_combout ),
|
|
.datad(\z80_|pla_decode_|Equal13~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_oe~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_oe~1 .lut_mask = 16'h0080;
|
|
defparam \z80_|execute_|ctl_flags_oe~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y15_N2
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~13 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_in_hi~13_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((!\z80_|execute_|ctl_flags_oe~1_combout ) # (!\z80_|execute_|setM1~50_combout ))))
|
|
|
|
.dataa(\z80_|execute_|setM1~50_combout ),
|
|
.datab(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.datac(\z80_|execute_|ctl_flags_oe~1_combout ),
|
|
.datad(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_in_hi~13_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_in_hi~13 .lut_mask = 16'h004C;
|
|
defparam \z80_|execute_|ctl_reg_in_hi~13 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y16_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~12 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_sel[0]~12_combout = (!\z80_|execute_|ctl_mRead~12_combout & (!\z80_|execute_|ctl_alu_oe~1_combout & !\z80_|pla_decode_|Equal49~0_combout ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|execute_|ctl_mRead~12_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_oe~1_combout ),
|
|
.datad(\z80_|pla_decode_|Equal49~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[0]~12 .lut_mask = 16'h0003;
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[0]~12 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y15_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~7 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_in_hi~7_combout = (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal69~0_combout ) # ((!\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout ))))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal69~0_combout ),
|
|
.datab(\z80_|execute_|ctl_sw_1d~8_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ),
|
|
.datad(\z80_|nM1_int~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_in_hi~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_in_hi~7 .lut_mask = 16'hBF00;
|
|
defparam \z80_|execute_|ctl_reg_in_hi~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y15_N16
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_state_alu~13 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_state_alu~13_combout = (\z80_|sequencer_|DFFE_M1_ff~q ) # (((!\z80_|execute_|ctl_state_alu~6_combout & !\z80_|pla_decode_|Equal52~1_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q ))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.datab(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.datac(\z80_|execute_|ctl_state_alu~6_combout ),
|
|
.datad(\z80_|pla_decode_|Equal52~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_state_alu~13_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_state_alu~13 .lut_mask = 16'hBBBF;
|
|
defparam \z80_|execute_|ctl_state_alu~13 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y15_N28
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~6 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_we~6_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & (!\z80_|execute_|ctl_reg_in_hi~13_combout & (!\z80_|execute_|ctl_reg_in_hi~7_combout & \z80_|execute_|ctl_state_alu~13_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ),
|
|
.datab(\z80_|execute_|ctl_reg_in_hi~13_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_in_hi~7_combout ),
|
|
.datad(\z80_|execute_|ctl_state_alu~13_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_we~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_we~6 .lut_mask = 16'h0100;
|
|
defparam \z80_|execute_|ctl_reg_gp_we~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y15_N24
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~5 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_we~5_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout & (((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_hilo_pla27npla34M1T1_3~combout ),
|
|
.datab(\z80_|execute_|ctl_state_alu~4_combout ),
|
|
.datac(\z80_|pla_decode_|Equal12~1_combout ),
|
|
.datad(\z80_|pla_decode_|Equal25~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_we~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_we~5 .lut_mask = 16'h5155;
|
|
defparam \z80_|execute_|ctl_reg_gp_we~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y17_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~17 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo[1]~17_combout = ((!\z80_|execute_|ctl_mRead~2_combout & ((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|pla_decode_|Equal63~0_combout )))) # (!\z80_|nM1_int~2_combout )
|
|
|
|
.dataa(\z80_|pla_decode_|Equal63~0_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~2_combout ),
|
|
.datac(\z80_|nM1_int~2_combout ),
|
|
.datad(\z80_|pla_decode_|Equal32~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo[1]~17_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~17 .lut_mask = 16'h1F3F;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~17 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y20_N28
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~18 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~17_combout & (\z80_|execute_|ctl_pf_sel[0]~3_combout & (\z80_|execute_|ctl_flags_pf_we~4_combout & \z80_|execute_|ctl_alu_oe~6_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~17_combout ),
|
|
.datab(\z80_|execute_|ctl_pf_sel[0]~3_combout ),
|
|
.datac(\z80_|execute_|ctl_flags_pf_we~4_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_oe~6_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~18 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y17_N2
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~10 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_sel_op2_neg~10_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout & (((!\z80_|execute_|ctl_mRead~34_combout & !\z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_mRead~9_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~34_combout ),
|
|
.datac(\z80_|pla_decode_|Equal21~1_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~9_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .lut_mask = 16'h0155;
|
|
defparam \z80_|execute_|ctl_alu_sel_op2_neg~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y15_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~9 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_sw_1d~9_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|pla_decode_|Equal6~1_combout ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datac(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.datad(\z80_|pla_decode_|Equal6~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_sw_1d~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_sw_1d~9 .lut_mask = 16'h0300;
|
|
defparam \z80_|execute_|ctl_sw_1d~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y15_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~9 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_we~9_combout = (!\z80_|execute_|ctl_sw_1d~9_combout & (((!\z80_|execute_|ctl_mRead~16_combout ) # (!\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q )))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.datab(\z80_|sequencer_|M5~q ),
|
|
.datac(\z80_|execute_|ctl_sw_1d~9_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~16_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_we~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_we~9 .lut_mask = 16'h070F;
|
|
defparam \z80_|execute_|ctl_reg_gp_we~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y15_N18
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_we~4_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~10_combout & \z80_|execute_|ctl_reg_gp_we~9_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|execute_|ctl_reg_gp_we~9_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_we~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_we~4 .lut_mask = 16'h8800;
|
|
defparam \z80_|execute_|ctl_reg_gp_we~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y15_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~7 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_we~7_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & (\z80_|execute_|ctl_reg_gp_we~6_combout & (\z80_|execute_|ctl_reg_gp_we~5_combout & \z80_|execute_|ctl_reg_gp_we~4_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_we~6_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_we~5_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_we~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_we~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_we~7 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|ctl_reg_gp_we~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y18_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~3 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_we~3_combout = (\z80_|execute_|ctl_inc_cy~78_combout & (\z80_|execute_|ctl_bus_inc_oe~48_combout & (\z80_|execute_|ctl_bus_inc_oe~26_combout & \z80_|execute_|ctl_inc_cy~49_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_inc_cy~78_combout ),
|
|
.datab(\z80_|execute_|ctl_bus_inc_oe~48_combout ),
|
|
.datac(\z80_|execute_|ctl_bus_inc_oe~26_combout ),
|
|
.datad(\z80_|execute_|ctl_inc_cy~49_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_we~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_we~3 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|ctl_reg_gp_we~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y14_N16
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~32 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo[1]~32_combout = (\z80_|execute_|ctl_reg_gp_we~2_combout & (!\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout & ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal10~0_combout ))))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal10~0_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_we~2_combout ),
|
|
.datac(\z80_|execute_|ixy_d~9_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~32 .lut_mask = 16'h004C;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~32 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y14_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_sw_4u~2_combout = (\z80_|execute_|nextM~2_combout & (((!\z80_|execute_|ixy_d~9_combout )) # (!\z80_|pla_decode_|Equal11~0_combout ))) # (!\z80_|execute_|nextM~2_combout & (!\z80_|execute_|ixy_d~5_combout &
|
|
// ((!\z80_|execute_|ixy_d~9_combout ) # (!\z80_|pla_decode_|Equal11~0_combout ))))
|
|
|
|
.dataa(\z80_|execute_|nextM~2_combout ),
|
|
.datab(\z80_|pla_decode_|Equal11~0_combout ),
|
|
.datac(\z80_|execute_|ixy_d~9_combout ),
|
|
.datad(\z80_|execute_|ixy_d~5_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_sw_4u~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_sw_4u~2 .lut_mask = 16'h2A3F;
|
|
defparam \z80_|execute_|ctl_sw_4u~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y14_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~3 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_sw_4u~3_combout = (\z80_|execute_|ctl_reg_gp_we~3_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout & \z80_|execute_|ctl_sw_4u~2_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_we~3_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ),
|
|
.datac(\z80_|execute_|ctl_sw_4u~2_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_sw_4u~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_sw_4u~3 .lut_mask = 16'h8080;
|
|
defparam \z80_|execute_|ctl_sw_4u~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y15_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_we~8 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_we~8_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # (((!\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~3_combout )) # (!\z80_|execute_|ctl_reg_gp_we~7_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_we~7_combout ),
|
|
.datac(\z80_|execute_|ctl_sw_4u~3_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_we~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_we~8 .lut_mask = 16'hBFFF;
|
|
defparam \z80_|execute_|ctl_reg_gp_we~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y15_N16
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~14 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo[1]~14_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~13_combout & ((\z80_|pla_decode_|Equal33~1_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~15_combout &
|
|
// !\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~13_combout ),
|
|
.datab(\z80_|pla_decode_|Equal33~1_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_shift_oe~15_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_hilo_pla27pla34M1T4nop4op5nop3_2~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo[1]~14_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~14 .lut_mask = 16'h888A;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~14 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y15_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~24 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo[0]~24_combout = (\z80_|execute_|rsel3~combout & (((\z80_|nM1_int~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~12_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~14_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~14_combout ),
|
|
.datab(\z80_|nM1_int~2_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ),
|
|
.datad(\z80_|execute_|rsel3~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo[0]~24_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[0]~24 .lut_mask = 16'h5D00;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[0]~24 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y15_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout = (\z80_|sequencer_|DFFE_M4_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & (!\z80_|pla_decode_|Equal12~1_combout & \z80_|pla_decode_|Equal25~0_combout )))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_M4_ff~q ),
|
|
.datab(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.datac(\z80_|pla_decode_|Equal12~1_combout ),
|
|
.datad(\z80_|pla_decode_|Equal25~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .lut_mask = 16'h0800;
|
|
defparam \z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y15_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~25 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo[0]~25_combout = (\z80_|execute_|ctl_ir_we~7_combout ) # ((\z80_|execute_|ctl_ir_we~15_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo~21_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_ir_we~7_combout ),
|
|
.datab(\z80_|execute_|ctl_ir_we~15_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sys_hilo~21_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .lut_mask = 16'hEFFF;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[0]~25 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y15_N18
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~26 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo[0]~26_combout = (\z80_|execute_|ctl_state_alu~3_combout & ((\z80_|execute_|ctl_iorw~10_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ) # (\z80_|execute_|ctl_state_alu~6_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_iorw~10_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_hilo[0]~25_combout ),
|
|
.datac(\z80_|execute_|ctl_state_alu~6_combout ),
|
|
.datad(\z80_|execute_|ctl_state_alu~3_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .lut_mask = 16'hFE00;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[0]~26 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y12_N26
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~46 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo[0]~46_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # ((\z80_|sequencer_|DFFE_M3_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ))))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_M3_ff~q ),
|
|
.datab(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.datac(\z80_|execute_|nextM~2_combout ),
|
|
.datad(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo[0]~46_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[0]~46 .lut_mask = 16'h0E0C;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[0]~46 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y12_N2
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~27 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo[0]~27_combout = ((\z80_|execute_|ctl_reg_gp_hilo[0]~46_combout ) # ((\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ixy_d~7_combout ))) # (!\z80_|execute_|ctl_mRead~23_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_mRead~23_combout ),
|
|
.datab(\z80_|pla_decode_|Equal6~1_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_hilo[0]~46_combout ),
|
|
.datad(\z80_|execute_|ixy_d~7_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .lut_mask = 16'hFDF5;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[0]~27 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y15_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~29 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo[0]~29_combout = (\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ) #
|
|
// (!\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_sel_pla30npla13M4T3_5~combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_hilo[0]~26_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_hilo[0]~28_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_hilo[0]~27_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .lut_mask = 16'hFFEF;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[0]~29 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y12_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~22 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo[0]~22_combout = (\z80_|execute_|ixy_d~7_combout & (((\z80_|execute_|ctl_mWrite~6_combout ) # (\z80_|execute_|ctl_mRead~5_combout )) # (!\z80_|execute_|ctl_al_we~13_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_al_we~13_combout ),
|
|
.datab(\z80_|execute_|ctl_mWrite~6_combout ),
|
|
.datac(\z80_|execute_|ctl_mRead~5_combout ),
|
|
.datad(\z80_|execute_|ixy_d~7_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo[0]~22_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[0]~22 .lut_mask = 16'hFD00;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[0]~22 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y15_N6
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~23 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo[0]~23_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~22_combout ) # ((!\z80_|execute_|ctl_flags_oe~1_combout & ((\z80_|execute_|ctl_state_alu~3_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_state_alu~3_combout ),
|
|
.datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ),
|
|
.datac(\z80_|execute_|ctl_flags_oe~1_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_hilo[0]~22_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo[0]~23_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[0]~23 .lut_mask = 16'hFF0B;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[0]~23 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y15_N2
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~31 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo[0]~31_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~24_combout ) # (((\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ) # (\z80_|execute_|ctl_reg_gp_hilo[0]~23_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~24_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_hilo[0]~30_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_hilo[0]~29_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_hilo[0]~23_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .lut_mask = 16'hFFFB;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[0]~31 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y14_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~33 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo[1]~33_combout = (\z80_|execute_|ixy_d~6_combout & (((!\z80_|pla_decode_|Equal10~0_combout & !\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ixy_d~6_combout & (((!\z80_|pla_decode_|Equal11~0_combout )) #
|
|
// (!\z80_|execute_|ixy_d~9_combout )))
|
|
|
|
.dataa(\z80_|execute_|ixy_d~9_combout ),
|
|
.datab(\z80_|execute_|ixy_d~6_combout ),
|
|
.datac(\z80_|pla_decode_|Equal10~0_combout ),
|
|
.datad(\z80_|pla_decode_|Equal11~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~33 .lut_mask = 16'h113F;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~33 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y14_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~26 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_sel[1]~26_combout = (\z80_|execute_|ctl_reg_gp_we~3_combout & (\z80_|execute_|fMRead~8_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & \z80_|execute_|fMRead~10_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_we~3_combout ),
|
|
.datab(\z80_|execute_|fMRead~8_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ),
|
|
.datad(\z80_|execute_|fMRead~10_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[1]~26 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y14_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~34 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo[1]~34_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~12_combout & \z80_|execute_|ctl_reg_gp_sel[1]~26_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~33_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_hilo[1]~32_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_hilo[1]~12_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo[1]~34_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~34 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~34 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y15_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~25 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_sel[0]~25_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & (\z80_|execute_|ctl_state_alu~13_combout & \z80_|execute_|ctl_reg_gp_sel[0]~24_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ),
|
|
.datab(\z80_|execute_|ctl_state_alu~13_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_sel[0]~24_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .lut_mask = 16'h4040;
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[0]~25 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y15_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~20 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout = (\z80_|execute_|ctl_reg_gp_sel~7_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ) # (!\z80_|execute_|ctl_sw_2u~5_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_sel~7_combout ),
|
|
.datab(\z80_|execute_|ctl_sw_2u~5_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .lut_mask = 16'hBBFF;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~20 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y15_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~21 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo[0]~21_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout & ((\z80_|execute_|rsel0~combout ) # ((!\z80_|execute_|setM1~50_combout & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) #
|
|
// (!\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout & (((!\z80_|execute_|setM1~50_combout & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ),
|
|
.datab(\z80_|execute_|rsel0~combout ),
|
|
.datac(\z80_|execute_|setM1~50_combout ),
|
|
.datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo[0]~21_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[0]~21 .lut_mask = 16'h888F;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[0]~21 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y15_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[0]~35 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo[0]~35_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ) # (((\z80_|execute_|ctl_reg_gp_hilo[0]~21_combout ) # (!\z80_|execute_|ctl_reg_gp_sel[0]~25_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~34_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~31_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_hilo[1]~34_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_hilo[0]~21_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[0]~35 .lut_mask = 16'hFFBF;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[0]~35 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y17_N14
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal2~2 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal2~2_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal32~0_combout )))
|
|
|
|
.dataa(\z80_|ir_|opcode [5]),
|
|
.datab(\z80_|pla_decode_|Equal2~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal1~7_combout ),
|
|
.datad(\z80_|pla_decode_|Equal32~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal2~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal2~2 .lut_mask = 16'h8000;
|
|
defparam \z80_|pla_decode_|Equal2~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y13_N14
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal1~6 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal1~6_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal1~5_combout & \z80_|pla_decode_|Equal1~7_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal1~4_combout ),
|
|
.datab(\z80_|ir_|opcode [3]),
|
|
.datac(\z80_|pla_decode_|Equal1~5_combout ),
|
|
.datad(\z80_|pla_decode_|Equal1~7_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal1~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal1~6 .lut_mask = 16'h8000;
|
|
defparam \z80_|pla_decode_|Equal1~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y15_N20
|
|
cycloneive_lcell_comb \z80_|reg_control_|bank_exx~2 (
|
|
// Equation(s):
|
|
// \z80_|reg_control_|bank_exx~2_combout = \z80_|reg_control_|bank_exx~q $ (((\z80_|pla_decode_|Equal1~6_combout & (\z80_|sequencer_|DFFE_T2_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q ))))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal1~6_combout ),
|
|
.datab(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.datac(\z80_|reg_control_|bank_exx~q ),
|
|
.datad(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_control_|bank_exx~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_control_|bank_exx~2 .lut_mask = 16'hF078;
|
|
defparam \z80_|reg_control_|bank_exx~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X30_Y15_N21
|
|
dffeas \z80_|reg_control_|bank_exx (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_control_|bank_exx~2_combout ),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_control_|bank_exx~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_control_|bank_exx .is_wysiwyg = "true";
|
|
defparam \z80_|reg_control_|bank_exx .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y15_N6
|
|
cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de1~0 (
|
|
// Equation(s):
|
|
// \z80_|reg_control_|bank_hl_de1~0_combout = \z80_|reg_control_|bank_hl_de1~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal2~2_combout & !\z80_|reg_control_|bank_exx~q ))))
|
|
|
|
.dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ),
|
|
.datab(\z80_|pla_decode_|Equal2~2_combout ),
|
|
.datac(\z80_|reg_control_|bank_hl_de1~q ),
|
|
.datad(\z80_|reg_control_|bank_exx~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_control_|bank_hl_de1~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_control_|bank_hl_de1~0 .lut_mask = 16'hF0B4;
|
|
defparam \z80_|reg_control_|bank_hl_de1~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X30_Y15_N7
|
|
dffeas \z80_|reg_control_|bank_hl_de1 (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_control_|bank_hl_de1~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_control_|bank_hl_de1~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_control_|bank_hl_de1 .is_wysiwyg = "true";
|
|
defparam \z80_|reg_control_|bank_hl_de1 .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y16_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~19 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo[1]~19_combout = (\z80_|execute_|ctl_sw_1d~4_combout & (((\z80_|execute_|ctl_sw_1d~8_combout & !\z80_|pla_decode_|Equal69~0_combout )) # (!\z80_|nM1_int~2_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_sw_1d~4_combout ),
|
|
.datab(\z80_|nM1_int~2_combout ),
|
|
.datac(\z80_|execute_|ctl_sw_1d~8_combout ),
|
|
.datad(\z80_|pla_decode_|Equal69~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .lut_mask = 16'h22A2;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~19 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y15_N28
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~28 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_sel[0]~28_combout = (!\z80_|execute_|ctl_reg_gp_sel~7_combout & \z80_|execute_|ctl_sw_2u~2_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_sel~7_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_sw_2u~2_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .lut_mask = 16'h5050;
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[0]~28 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y15_N24
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~29 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_sel[0]~29_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~28_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~27_combout & !\z80_|execute_|ctl_reg_in_hi~13_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_sel[0]~28_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_sel[0]~27_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_in_hi~13_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .lut_mask = 16'h0080;
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[0]~29 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y15_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~30 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_sel[0]~30_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~25_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~29_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~26_combout & \z80_|execute_|ctl_reg_gp_hilo[1]~18_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_sel[0]~25_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_sel[0]~29_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_hilo[1]~18_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[0]~30 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y15_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~13 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_sel[0]~13_combout = (!\z80_|execute_|ctl_sw_1d~9_combout & (((!\z80_|execute_|ctl_state_alu~3_combout & !\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mWrite~6_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_state_alu~3_combout ),
|
|
.datab(\z80_|execute_|ctl_mWrite~6_combout ),
|
|
.datac(\z80_|execute_|ixy_d~7_combout ),
|
|
.datad(\z80_|execute_|ctl_sw_1d~9_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_sel[0]~13_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[0]~13 .lut_mask = 16'h0037;
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[0]~13 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y15_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~45 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo[1]~45_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~14_combout & ((\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ) # ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|sequencer_|DFFE_T1_ff~q ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~14_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_sel[0]~12_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.datad(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .lut_mask = 16'hAAA8;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~45 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y12_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_use_sp~2_combout = (((!\z80_|execute_|ctl_mRead~9_combout & !\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal8~0_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_mRead~9_combout ),
|
|
.datab(\z80_|pla_decode_|Equal8~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal6~0_combout ),
|
|
.datad(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_use_sp~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_use_sp~2 .lut_mask = 16'h3F7F;
|
|
defparam \z80_|execute_|ctl_reg_use_sp~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y18_N28
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~3 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_use_sp~3_combout = (\z80_|execute_|nextM~11_combout & (\z80_|execute_|ctl_bus_inc_oe~49_combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|ctl_reg_use_sp~2_combout )))
|
|
|
|
.dataa(\z80_|execute_|nextM~11_combout ),
|
|
.datab(\z80_|execute_|ctl_bus_inc_oe~49_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_use_sp~0_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_use_sp~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_use_sp~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_use_sp~3 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|ctl_reg_use_sp~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y15_N6
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~14 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_sel[0]~14_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~13_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~6_combout & \z80_|execute_|ctl_reg_use_sp~3_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_sel[0]~13_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_sel[0]~6_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_use_sp~3_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[0]~14 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[0]~14 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y15_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~32 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_sel[0]~32_combout = (\z80_|ir_|opcode [4] & (((!\z80_|execute_|ctl_reg_sys_hilo~21_combout & \z80_|execute_|ctl_state_alu~3_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~14_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ),
|
|
.datab(\z80_|ir_|opcode [4]),
|
|
.datac(\z80_|execute_|ctl_reg_sys_hilo~21_combout ),
|
|
.datad(\z80_|execute_|ctl_state_alu~3_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .lut_mask = 16'h4C44;
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[0]~32 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y15_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~33 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_sel[0]~33_combout = (\z80_|execute_|ixy_d~7_combout & (((\z80_|execute_|ctl_mRead~3_combout ) # (\z80_|pla_decode_|Equal11~0_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (\z80_|execute_|ixy_d~5_combout &
|
|
// ((\z80_|pla_decode_|Equal11~0_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ixy_d~5_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~3_combout ),
|
|
.datac(\z80_|execute_|ixy_d~7_combout ),
|
|
.datad(\z80_|pla_decode_|Equal11~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .lut_mask = 16'hFAC0;
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[0]~33 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y15_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~16 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo[1]~16_combout = (\z80_|execute_|setM1~57_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout & (\z80_|execute_|ctl_sw_2u~4_combout & \z80_|execute_|ctl_sw_2u~1_combout )))
|
|
|
|
.dataa(\z80_|execute_|setM1~57_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_hilo[1]~15_combout ),
|
|
.datac(\z80_|execute_|ctl_sw_2u~4_combout ),
|
|
.datad(\z80_|execute_|ctl_sw_2u~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo[1]~16_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~16 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~16 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y15_N18
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~34 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_sel[0]~34_combout = (\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~16_combout & \z80_|ir_|opcode [1]))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|execute_|ctl_reg_gp_sel[0]~33_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_hilo[1]~16_combout ),
|
|
.datad(\z80_|ir_|opcode [1]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .lut_mask = 16'hCFCC;
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[0]~34 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y15_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[0]~35 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_sel[0]~35_combout = ((\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ) # (\z80_|execute_|ctl_reg_gp_sel[0]~34_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .lut_mask = 16'hFFF5;
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[0]~35 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y12_N24
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~20 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_sel[1]~20_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|pla_decode_|Equal4~0_combout ) # ((\z80_|pla_decode_|Equal1~4_combout & \z80_|pla_decode_|Equal2~1_combout ))))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal4~0_combout ),
|
|
.datab(\z80_|pla_decode_|Equal1~4_combout ),
|
|
.datac(\z80_|pla_decode_|Equal2~1_combout ),
|
|
.datad(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[1]~20 .lut_mask = 16'hEA00;
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[1]~20 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y15_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~21 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_sel[1]~21_combout = (!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|execute_|ctl_state_alu~2_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ixy_d~5_combout ),
|
|
.datab(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.datac(\z80_|execute_|ctl_state_alu~2_combout ),
|
|
.datad(\z80_|execute_|nextM~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[1]~21 .lut_mask = 16'h00FE;
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[1]~21 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y15_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~22 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_sel[1]~22_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|ctl_state_alu~2_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_sel[1]~20_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~34_combout ),
|
|
.datac(\z80_|execute_|ctl_state_alu~2_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_sel[1]~21_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[1]~22 .lut_mask = 16'hFFEA;
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[1]~22 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y16_N16
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~18 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_sel[1]~18_combout = (\z80_|execute_|ctl_mWrite~17_combout ) # ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|pla_decode_|Equal21~0_combout & \z80_|pla_decode_|Equal24~0_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_mWrite~17_combout ),
|
|
.datab(\z80_|pla_decode_|Equal21~0_combout ),
|
|
.datac(\z80_|execute_|ctl_mRead~5_combout ),
|
|
.datad(\z80_|pla_decode_|Equal24~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .lut_mask = 16'hFEFA;
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[1]~18 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y18_N24
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~37 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_sel[1]~37_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~5_combout & (((!\z80_|execute_|ctl_mWrite~17_combout ) # (!\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.datab(\z80_|sequencer_|DFFE_M3_ff~q ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_sel[1]~5_combout ),
|
|
.datad(\z80_|execute_|ctl_mWrite~17_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .lut_mask = 16'h70F0;
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[1]~37 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y15_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~19 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_sel[1]~19_combout = ((\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~18_combout & \z80_|execute_|ixy_d~7_combout ))) # (!\z80_|execute_|ctl_reg_gp_sel[1]~37_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_sel[1]~18_combout ),
|
|
.datab(\z80_|execute_|ixy_d~7_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_sel[1]~37_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T4_2~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .lut_mask = 16'hFF8F;
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[1]~19 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y15_N24
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~23 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_sel[1]~23_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ) # ((!\z80_|execute_|ctl_reg_gp_hilo[1]~16_combout & \z80_|ir_|opcode [2])))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_sel[1]~22_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_sel[1]~19_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_hilo[1]~16_combout ),
|
|
.datad(\z80_|ir_|opcode [2]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .lut_mask = 16'hEFEE;
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[1]~23 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y14_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~16 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_sel[1]~16_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout )) # (!\z80_|execute_|ctl_mRead~17_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_mRead~17_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ),
|
|
.datac(\z80_|execute_|ctl_mRead~34_combout ),
|
|
.datad(\z80_|execute_|ctl_state_alu~3_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .lut_mask = 16'hF700;
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[1]~16 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y16_N24
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~17 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_sel[1]~17_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ) # ((\z80_|execute_|ixy_d~15_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q ))))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T4_ff~q ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_sel[1]~16_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.datad(\z80_|execute_|ixy_d~15_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .lut_mask = 16'hFECC;
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[1]~17 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y13_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~11 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_sel[1]~11_combout = (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|decode_state_|DFFE_instED~q & ((\z80_|sequencer_|DFFE_M4_ff~q ) # (\z80_|sequencer_|M5~q ))))
|
|
|
|
.dataa(\z80_|decode_state_|DFFE_instCB~q ),
|
|
.datab(\z80_|sequencer_|DFFE_M4_ff~q ),
|
|
.datac(\z80_|decode_state_|DFFE_instED~q ),
|
|
.datad(\z80_|sequencer_|M5~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .lut_mask = 16'h0504;
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[1]~11 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y13_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~36 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_sel[1]~36_combout = (\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_reg_gp_sel[1]~11_combout & !\z80_|ir_|opcode [4])))
|
|
|
|
.dataa(\z80_|ir_|opcode [1]),
|
|
.datab(\z80_|ir_|opcode [2]),
|
|
.datac(\z80_|execute_|ctl_reg_gp_sel[1]~11_combout ),
|
|
.datad(\z80_|ir_|opcode [4]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[1]~36 .lut_mask = 16'h0020;
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[1]~36 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y15_N2
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~8 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_sel[1]~8_combout = (\z80_|ir_|opcode [7] & (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|ir_|opcode [3] & \z80_|ir_|opcode [6])))
|
|
|
|
.dataa(\z80_|ir_|opcode [7]),
|
|
.datab(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datac(\z80_|ir_|opcode [3]),
|
|
.datad(\z80_|ir_|opcode [6]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .lut_mask = 16'h0200;
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[1]~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y15_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~9 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_sel[1]~9_combout = (\z80_|ir_|opcode [3] & (((\z80_|sequencer_|DFFE_T3_ff~q )))) # (!\z80_|ir_|opcode [3] & (((!\z80_|pla_decode_|Equal12~0_combout & \z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_T1_ff~q )))
|
|
|
|
.dataa(\z80_|ir_|opcode [3]),
|
|
.datab(\z80_|pla_decode_|Equal12~0_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datad(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .lut_mask = 16'hBF05;
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[1]~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y15_N18
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~10 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_sel[1]~10_combout = (\z80_|ir_|opcode [0] & (\z80_|execute_|ctl_reg_gp_sel[1]~8_combout )) # (!\z80_|ir_|opcode [0] & (((\z80_|execute_|ctl_reg_gp_sel[1]~9_combout & \z80_|execute_|ctl_ir_we~6_combout ))))
|
|
|
|
.dataa(\z80_|ir_|opcode [0]),
|
|
.datab(\z80_|execute_|ctl_reg_gp_sel[1]~8_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_sel[1]~9_combout ),
|
|
.datad(\z80_|execute_|ctl_ir_we~6_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .lut_mask = 16'hD888;
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[1]~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y15_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~15 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_sel[1]~15_combout = (\z80_|ir_|opcode [5] & (((\z80_|execute_|ctl_reg_gp_sel[1]~36_combout & \z80_|execute_|ctl_reg_gp_sel[1]~10_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~14_combout )))
|
|
|
|
.dataa(\z80_|ir_|opcode [5]),
|
|
.datab(\z80_|execute_|ctl_reg_gp_sel[0]~14_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_sel[1]~36_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_sel[1]~10_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .lut_mask = 16'hA222;
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[1]~15 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y15_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel[1]~31 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_sel[1]~31_combout = ((\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ) # ((\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ) # (\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ))) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_sel[1]~23_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_sel[1]~17_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_sel[1]~15_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .lut_mask = 16'hFFFD;
|
|
defparam \z80_|execute_|ctl_reg_gp_sel[1]~31 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y16_N24
|
|
cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~5 (
|
|
// Equation(s):
|
|
// \z80_|reg_control_|reg_sel_de2~5_combout = (!\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout )))
|
|
|
|
.dataa(\z80_|decode_state_|DFFE_instIY1~q ),
|
|
.datab(\z80_|decode_state_|DFFE_inst4~q ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_control_|reg_sel_de2~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_control_|reg_sel_de2~5 .lut_mask = 16'h0100;
|
|
defparam \z80_|reg_control_|reg_sel_de2~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y15_N28
|
|
cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~6 (
|
|
// Equation(s):
|
|
// \z80_|reg_control_|reg_sel_de2~6_combout = (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (((\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ) # (\z80_|execute_|ctl_reg_gp_sel[0]~32_combout )) # (!\z80_|execute_|ctl_reg_gp_sel[0]~30_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_sel[0]~30_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_sel[0]~34_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_sel[0]~32_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_control_|reg_sel_de2~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_control_|reg_sel_de2~6 .lut_mask = 16'h00FD;
|
|
defparam \z80_|reg_control_|reg_sel_de2~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y15_N24
|
|
cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de~0 (
|
|
// Equation(s):
|
|
// \z80_|reg_control_|reg_sel_de~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~5_combout )) # (!\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~6_combout )))))
|
|
|
|
.dataa(\z80_|reg_control_|bank_hl_de1~q ),
|
|
.datab(\z80_|reg_control_|bank_exx~q ),
|
|
.datac(\z80_|reg_control_|reg_sel_de2~5_combout ),
|
|
.datad(\z80_|reg_control_|reg_sel_de2~6_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_control_|reg_sel_de~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_control_|reg_sel_de~0 .lut_mask = 16'h3120;
|
|
defparam \z80_|reg_control_|reg_sel_de~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y11_N14
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_50 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_50~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & \z80_|reg_control_|reg_sel_de~0_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ),
|
|
.datad(\z80_|reg_control_|reg_sel_de~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .lut_mask = 16'h5000;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_50 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y15_N22
|
|
cycloneive_lcell_comb \z80_|reg_control_|bank_hl_de2~0 (
|
|
// Equation(s):
|
|
// \z80_|reg_control_|bank_hl_de2~0_combout = \z80_|reg_control_|bank_hl_de2~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal2~2_combout & \z80_|reg_control_|bank_exx~q ))))
|
|
|
|
.dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ),
|
|
.datab(\z80_|pla_decode_|Equal2~2_combout ),
|
|
.datac(\z80_|reg_control_|bank_hl_de2~q ),
|
|
.datad(\z80_|reg_control_|bank_exx~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_control_|bank_hl_de2~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_control_|bank_hl_de2~0 .lut_mask = 16'hB4F0;
|
|
defparam \z80_|reg_control_|bank_hl_de2~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X30_Y15_N23
|
|
dffeas \z80_|reg_control_|bank_hl_de2 (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_control_|bank_hl_de2~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_control_|bank_hl_de2~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_control_|bank_hl_de2 .is_wysiwyg = "true";
|
|
defparam \z80_|reg_control_|bank_hl_de2 .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y15_N16
|
|
cycloneive_lcell_comb \z80_|reg_control_|reg_sel_de2~4 (
|
|
// Equation(s):
|
|
// \z80_|reg_control_|reg_sel_de2~4_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~5_combout )) # (!\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~6_combout )))))
|
|
|
|
.dataa(\z80_|reg_control_|bank_hl_de2~q ),
|
|
.datab(\z80_|reg_control_|bank_exx~q ),
|
|
.datac(\z80_|reg_control_|reg_sel_de2~5_combout ),
|
|
.datad(\z80_|reg_control_|reg_sel_de2~6_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_control_|reg_sel_de2~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_control_|reg_sel_de2~4 .lut_mask = 16'hC480;
|
|
defparam \z80_|reg_control_|reg_sel_de2~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y11_N24
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_46 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_46~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & \z80_|reg_control_|reg_sel_de2~4_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ),
|
|
.datad(\z80_|reg_control_|reg_sel_de2~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .lut_mask = 16'h5000;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_46 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y11_N22
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_47 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_47~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & \z80_|reg_control_|reg_sel_de2~4_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ),
|
|
.datad(\z80_|reg_control_|reg_sel_de2~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .lut_mask = 16'hA000;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X31_Y11_N1
|
|
dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[2] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y11_N16
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_51 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_51~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & \z80_|reg_control_|reg_sel_de~0_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ),
|
|
.datad(\z80_|reg_control_|reg_sel_de~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .lut_mask = 16'hA000;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_51 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X31_Y11_N7
|
|
dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[2] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_de_lo|latch [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_de_lo|latch[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y11_N0
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~33 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[2]~33_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [2]),
|
|
.datad(\z80_|reg_file_|b2v_latch_de_lo|latch [2]),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[2]~33_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[2]~33 .lut_mask = 16'hF351;
|
|
defparam \z80_|reg_file_|gdfx_temp0[2]~33 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y15_N8
|
|
cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl~0 (
|
|
// Equation(s):
|
|
// \z80_|reg_control_|reg_sel_hl~0_combout = (!\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de1~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))) # (!\z80_|reg_control_|bank_hl_de1~q & (\z80_|reg_control_|reg_sel_de2~5_combout ))))
|
|
|
|
.dataa(\z80_|reg_control_|bank_hl_de1~q ),
|
|
.datab(\z80_|reg_control_|bank_exx~q ),
|
|
.datac(\z80_|reg_control_|reg_sel_de2~5_combout ),
|
|
.datad(\z80_|reg_control_|reg_sel_de2~6_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_control_|reg_sel_hl~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_control_|reg_sel_hl~0 .lut_mask = 16'h3210;
|
|
defparam \z80_|reg_control_|reg_sel_hl~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y12_N26
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_59 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_59~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|reg_control_|reg_sel_hl~0_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_we~8_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|reg_control_|reg_sel_hl~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .lut_mask = 16'h8800;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_59 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X30_Y12_N31
|
|
dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[2] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y15_N30
|
|
cycloneive_lcell_comb \z80_|reg_control_|reg_sel_hl2~0 (
|
|
// Equation(s):
|
|
// \z80_|reg_control_|reg_sel_hl2~0_combout = (\z80_|reg_control_|bank_exx~q & ((\z80_|reg_control_|bank_hl_de2~q & ((\z80_|reg_control_|reg_sel_de2~6_combout ))) # (!\z80_|reg_control_|bank_hl_de2~q & (\z80_|reg_control_|reg_sel_de2~5_combout ))))
|
|
|
|
.dataa(\z80_|reg_control_|bank_hl_de2~q ),
|
|
.datab(\z80_|reg_control_|bank_exx~q ),
|
|
.datac(\z80_|reg_control_|reg_sel_de2~5_combout ),
|
|
.datad(\z80_|reg_control_|reg_sel_de2~6_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_control_|reg_sel_hl2~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_control_|reg_sel_hl2~0 .lut_mask = 16'hC840;
|
|
defparam \z80_|reg_control_|reg_sel_hl2~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y12_N4
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_54 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_54~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|reg_control_|reg_sel_hl2~0_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_we~8_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|reg_control_|reg_sel_hl2~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .lut_mask = 16'h2200;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_54 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y12_N18
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_55 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_55~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|reg_control_|reg_sel_hl2~0_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_we~8_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|reg_control_|reg_sel_hl2~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .lut_mask = 16'h8800;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_55 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X30_Y12_N25
|
|
dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y12_N20
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_58 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_58~combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|reg_control_|reg_sel_hl~0_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_reg_gp_we~8_combout ),
|
|
.datad(\z80_|reg_control_|reg_sel_hl~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .lut_mask = 16'h0A00;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_58 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y12_N24
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~34 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[2]~34_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [2] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [2] &
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [2]),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [2]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[2]~34_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[2]~34 .lut_mask = 16'hA2F3;
|
|
defparam \z80_|reg_file_|gdfx_temp0[2]~34 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y13_N2
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_we~8_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .lut_mask = 16'h0C0C;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y16_N0
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout = (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout )))
|
|
|
|
.dataa(\z80_|reg_control_|bank_exx~q ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ),
|
|
.datac(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .lut_mask = 16'h0020;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_38~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y13_N22
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_we~8_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .lut_mask = 16'hC0C0;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y16_N18
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout = (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout )))
|
|
|
|
.dataa(\z80_|reg_control_|bank_exx~q ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ),
|
|
.datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .lut_mask = 16'h0010;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_43~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y14_N29
|
|
dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[2] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y16_N12
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout = (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout )))
|
|
|
|
.dataa(\z80_|reg_control_|bank_exx~q ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ),
|
|
.datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .lut_mask = 16'h0020;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_39~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y14_N7
|
|
dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y16_N16
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout = (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & !\z80_|execute_|ctl_reg_gp_sel[1]~31_combout )))
|
|
|
|
.dataa(\z80_|reg_control_|bank_exx~q ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ),
|
|
.datac(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .lut_mask = 16'h0010;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_42~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y14_N6
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~36 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[2]~36_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ),
|
|
.datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [2]),
|
|
.datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [2]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[2]~36_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[2]~36 .lut_mask = 16'hC4F5;
|
|
defparam \z80_|reg_file_|gdfx_temp0[2]~36 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y12_N2
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~15 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sel_wz~15_combout = (((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~14_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~13_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_sel_wz~13_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_in_hi~5_combout ),
|
|
.datac(\z80_|execute_|ctl_66_oe~2_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sel_wz~14_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sel_wz~15_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sel_wz~15 .lut_mask = 16'hF7FF;
|
|
defparam \z80_|execute_|ctl_reg_sel_wz~15 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y12_N16
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~18 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sel_wz~18_combout = (((\z80_|execute_|ctl_reg_sel_wz~15_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~12_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~21_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~17_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_sel_wz~21_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_sel_wz~12_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sel_wz~15_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sel_wz~18_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sel_wz~18 .lut_mask = 16'hFF7F;
|
|
defparam \z80_|execute_|ctl_reg_sel_wz~18 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y12_N0
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_83 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_83~combout = (\z80_|execute_|ctl_reg_sel_wz~18_combout & (\z80_|reg_control_|reg_sys_we_lo~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_sel_wz~18_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|reg_control_|reg_sys_we_lo~combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .lut_mask = 16'hA000;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_83 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y13_N5
|
|
dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[2] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y12_N8
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_82 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_82~combout = (\z80_|execute_|ctl_reg_sel_wz~18_combout & (!\z80_|reg_control_|reg_sys_we_lo~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_sel_wz~18_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|reg_control_|reg_sys_we_lo~combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .lut_mask = 16'h0A00;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_82 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y13_N4
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~37 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[2]~37_combout = (\z80_|reg_file_|gdfx_temp0[2]~36_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|reg_file_|gdfx_temp0[2]~36_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [2]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[2]~37_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[2]~37 .lut_mask = 16'hC0CC;
|
|
defparam \z80_|reg_file_|gdfx_temp0[2]~37 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y16_N6
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & (\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ),
|
|
.datab(\z80_|decode_state_|DFFE_inst4~q ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .lut_mask = 16'h0080;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_66~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y16_N14
|
|
cycloneive_lcell_comb \z80_|reg_control_|reg_sel_iy~2 (
|
|
// Equation(s):
|
|
// \z80_|reg_control_|reg_sel_iy~2_combout = (\z80_|decode_state_|DFFE_instIY1~q & (!\z80_|decode_state_|DFFE_inst4~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout )))
|
|
|
|
.dataa(\z80_|decode_state_|DFFE_instIY1~q ),
|
|
.datab(\z80_|decode_state_|DFFE_inst4~q ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_control_|reg_sel_iy~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_control_|reg_sel_iy~2 .lut_mask = 16'h0200;
|
|
defparam \z80_|reg_control_|reg_sel_iy~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y12_N10
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_71 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_71~combout = (\z80_|reg_control_|reg_sel_iy~2_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & \z80_|execute_|ctl_reg_gp_we~8_combout ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|reg_control_|reg_sel_iy~2_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_we~8_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .lut_mask = 16'hC000;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_71 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X31_Y12_N3
|
|
dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[2] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y16_N28
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|decode_state_|DFFE_inst4~q )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ),
|
|
.datad(\z80_|decode_state_|DFFE_inst4~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .lut_mask = 16'h2000;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_67~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X31_Y12_N1
|
|
dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[2] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y12_N12
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_70 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_70~combout = (\z80_|reg_control_|reg_sel_iy~2_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|reg_control_|reg_sel_iy~2_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_we~8_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .lut_mask = 16'h00C0;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_70 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y12_N0
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~38 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[2]~38_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ),
|
|
.datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [2]),
|
|
.datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [2]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[2]~38_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[2]~38 .lut_mask = 16'hC4F5;
|
|
defparam \z80_|reg_file_|gdfx_temp0[2]~38 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y16_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout = (\z80_|execute_|ctl_state_alu~2_combout & (!\z80_|ir_|opcode [3] & (\z80_|ir_|opcode [4] & \z80_|pla_decode_|Equal24~0_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_state_alu~2_combout ),
|
|
.datab(\z80_|ir_|opcode [3]),
|
|
.datac(\z80_|ir_|opcode [4]),
|
|
.datad(\z80_|pla_decode_|Equal24~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .lut_mask = 16'h2000;
|
|
defparam \z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y14_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~9 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_in_hi~9_combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ixy_d~7_combout ) # (!\z80_|execute_|ctl_mRead~2_combout )))) # (!\z80_|pla_decode_|Equal47~0_combout
|
|
// & (((!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|execute_|ctl_mRead~2_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal47~0_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~2_combout ),
|
|
.datac(\z80_|execute_|ixy_d~7_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_in_hi~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_in_hi~9 .lut_mask = 16'h153F;
|
|
defparam \z80_|execute_|ctl_reg_in_hi~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y14_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~10 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_in_hi~10_combout = (\z80_|execute_|ctl_reg_gp_we~7_combout & (\z80_|execute_|ctl_reg_in_hi~8_combout & \z80_|execute_|ctl_reg_in_hi~9_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_we~7_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_reg_in_hi~8_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_in_hi~9_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_in_hi~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_in_hi~10 .lut_mask = 16'hA000;
|
|
defparam \z80_|execute_|ctl_reg_in_hi~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y14_N24
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_lo~8 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_in_lo~8_combout = (\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ) # (((!\z80_|execute_|ctl_reg_in_hi~10_combout ) # (!\z80_|execute_|ctl_reg_in_lo~9_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~21_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_sel_pla37pla28M2T3_4~combout ),
|
|
.datab(\z80_|execute_|ctl_reg_sel_wz~21_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_in_lo~9_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_in_hi~10_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_in_lo~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_in_lo~8 .lut_mask = 16'hBFFF;
|
|
defparam \z80_|execute_|ctl_reg_in_lo~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y12_N0
|
|
cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_sp_lo|latch[2]~feeder (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|b2v_latch_sp_lo|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp0[2]~42_combout
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|reg_file_|gdfx_temp0[2]~42_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|b2v_latch_sp_lo|latch[2]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2]~feeder .lut_mask = 16'hFF00;
|
|
defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y15_N18
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_use_sp~4_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|pla_decode_|Equal6~1_combout & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q ))))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.datab(\z80_|sequencer_|DFFE_M3_ff~q ),
|
|
.datac(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datad(\z80_|pla_decode_|Equal6~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_use_sp~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_use_sp~4 .lut_mask = 16'h0D00;
|
|
defparam \z80_|execute_|ctl_reg_use_sp~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y15_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~5 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_use_sp~5_combout = (\z80_|execute_|ctl_reg_use_sp~4_combout ) # ((\z80_|execute_|ctl_mRead~15_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) # (\z80_|execute_|ctl_state_alu~4_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_mRead~15_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_use_sp~4_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_in_hi~2_combout ),
|
|
.datad(\z80_|execute_|ctl_state_alu~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_use_sp~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_use_sp~5 .lut_mask = 16'hEEEC;
|
|
defparam \z80_|execute_|ctl_reg_use_sp~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y15_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_use_sp~6 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_use_sp~6_combout = (\z80_|execute_|ctl_reg_use_sp~5_combout ) # ((!\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ) # (!\z80_|execute_|ctl_reg_use_sp~3_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_use_sp~5_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_use_sp~3_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_sel[1]~26_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_use_sp~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_use_sp~6 .lut_mask = 16'hBFBF;
|
|
defparam \z80_|execute_|ctl_reg_use_sp~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y16_N14
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ),
|
|
.datac(\z80_|reg_file_|SYNTHESIZED_WIRE_71~2_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .lut_mask = 16'h8000;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_79~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y12_N1
|
|
dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[2] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_file_|b2v_latch_sp_lo|latch[2]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y16_N28
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~5 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_sw_1d~5_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_mRead~12_combout ) # ((\z80_|pla_decode_|Equal49~0_combout ) # (!\z80_|execute_|ctl_sw_1d~8_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_mRead~12_combout ),
|
|
.datab(\z80_|nM1_int~2_combout ),
|
|
.datac(\z80_|execute_|ctl_sw_1d~8_combout ),
|
|
.datad(\z80_|pla_decode_|Equal49~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_sw_1d~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_sw_1d~5 .lut_mask = 16'hCC8C;
|
|
defparam \z80_|execute_|ctl_sw_1d~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y19_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_im_we (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_im_we~combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal13~0_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal33~0_combout ),
|
|
.datab(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.datac(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.datad(\z80_|pla_decode_|Equal13~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_im_we~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_im_we .lut_mask = 16'h2000;
|
|
defparam \z80_|execute_|ctl_im_we .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y16_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~6 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_sw_1d~6_combout = (\z80_|execute_|ctl_sw_1d~4_combout & (!\z80_|execute_|ctl_sw_1d~5_combout & (\z80_|execute_|ctl_sw_2d~9_combout & !\z80_|execute_|ctl_im_we~combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_sw_1d~4_combout ),
|
|
.datab(\z80_|execute_|ctl_sw_1d~5_combout ),
|
|
.datac(\z80_|execute_|ctl_sw_2d~9_combout ),
|
|
.datad(\z80_|execute_|ctl_im_we~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_sw_1d~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_sw_1d~6 .lut_mask = 16'h0020;
|
|
defparam \z80_|execute_|ctl_sw_1d~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y14_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_sw_1d~7 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_sw_1d~7_combout = ((\z80_|execute_|ctl_66_oe~2_combout & !\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q )) # (!\z80_|execute_|ctl_sw_1d~6_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_66_oe~2_combout ),
|
|
.datab(\z80_|execute_|ctl_sw_1d~6_combout ),
|
|
.datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_sw_1d~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_sw_1d~7 .lut_mask = 16'h3B3B;
|
|
defparam \z80_|execute_|ctl_sw_1d~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y14_N18
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[2]~2 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_lo_ds[2]~2_combout = (\z80_|reg_file_|gdfx_temp0[2]~42_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~5_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout & \z80_|execute_|ctl_reg_out_lo~7_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_out_lo~5_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_out_lo~7_combout ),
|
|
.datad(\z80_|reg_file_|gdfx_temp0[2]~42_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_lo_ds[2]~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_lo_ds[2]~2 .lut_mask = 16'hFF40;
|
|
defparam \z80_|reg_file_|db_lo_ds[2]~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y14_N8
|
|
cycloneive_lcell_comb \z80_|alu_control_|db[2]~28 (
|
|
// Equation(s):
|
|
// \z80_|alu_control_|db[2]~28_combout = (\z80_|reg_file_|db_lo_ds[2]~2_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[2]~13_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_sw_mask543_en~0_combout ),
|
|
.datab(\z80_|bus_control_|db[2]~13_combout ),
|
|
.datac(\z80_|execute_|ctl_sw_1d~7_combout ),
|
|
.datad(\z80_|reg_file_|db_lo_ds[2]~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_control_|db[2]~28_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_control_|db[2]~28 .lut_mask = 16'h4F00;
|
|
defparam \z80_|alu_control_|db[2]~28 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y12_N6
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~11 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_in_hi~11_combout = (((\z80_|execute_|ixy_d~6_combout & \z80_|pla_decode_|Equal9~1_combout )) # (!\z80_|execute_|ctl_reg_in_hi~5_combout )) # (!\z80_|execute_|ctl_reg_in_hi~6_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_in_hi~6_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_in_hi~5_combout ),
|
|
.datac(\z80_|execute_|ixy_d~6_combout ),
|
|
.datad(\z80_|pla_decode_|Equal9~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_in_hi~11_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_in_hi~11 .lut_mask = 16'hF777;
|
|
defparam \z80_|execute_|ctl_reg_in_hi~11 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y14_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_in_hi~12 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_in_hi~12_combout = (((\z80_|execute_|ctl_reg_in_hi~11_combout ) # (!\z80_|execute_|ctl_reg_in_hi~4_combout )) # (!\z80_|execute_|ctl_reg_in_hi~3_combout )) # (!\z80_|execute_|ctl_reg_in_hi~10_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_in_hi~10_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_in_hi~3_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_in_hi~11_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_in_hi~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_in_hi~12_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_in_hi~12 .lut_mask = 16'hF7FF;
|
|
defparam \z80_|execute_|ctl_reg_in_hi~12 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y15_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~42 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo[1]~42_combout = ((\z80_|execute_|ctl_state_alu~3_combout & ((!\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ) # (!\z80_|execute_|setM1~48_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~34_combout )
|
|
|
|
.dataa(\z80_|execute_|setM1~48_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ),
|
|
.datac(\z80_|execute_|ctl_state_alu~3_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_hilo[1]~34_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .lut_mask = 16'h70FF;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~42 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y15_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~39 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo[1]~39_combout = ((\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mRead~3_combout ) # (!\z80_|execute_|ctl_al_we~14_combout )))) # (!\z80_|execute_|setM1~30_combout )
|
|
|
|
.dataa(\z80_|execute_|ixy_d~7_combout ),
|
|
.datab(\z80_|execute_|setM1~30_combout ),
|
|
.datac(\z80_|execute_|ctl_mRead~3_combout ),
|
|
.datad(\z80_|execute_|ctl_al_we~14_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .lut_mask = 16'hB3BB;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~39 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y15_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~38 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo[1]~38_combout = ((!\z80_|execute_|nextM~2_combout & ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ctl_state_alu~2_combout )))) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout )
|
|
|
|
.dataa(\z80_|execute_|ixy_d~5_combout ),
|
|
.datab(\z80_|execute_|ctl_state_alu~2_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_hilo[1]~19_combout ),
|
|
.datad(\z80_|execute_|nextM~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~38 .lut_mask = 16'h0FEF;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~38 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y15_N2
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~40 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo[1]~40_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ) # ((!\z80_|execute_|rsel3~combout & !\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~39_combout ),
|
|
.datab(\z80_|execute_|rsel3~combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_hilo[1]~38_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_hilo[1]~45_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .lut_mask = 16'hFAFB;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~40 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y15_N26
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~41 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo[1]~41_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ) # (((!\z80_|execute_|rsel0~combout & \z80_|execute_|ctl_reg_gp_hilo[1]~20_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~40_combout ),
|
|
.datab(\z80_|execute_|rsel0~combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_hilo[1]~47_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_hilo[1]~20_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .lut_mask = 16'hBFAF;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~41 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y15_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_hilo[1]~43 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_hilo[1]~43_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ) # (((\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ) # (!\z80_|execute_|ctl_reg_gp_we~4_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~42_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_hilo[1]~48_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_hilo[1]~41_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_we~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .lut_mask = 16'hFBFF;
|
|
defparam \z80_|execute_|ctl_reg_gp_hilo[1]~43 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y16_N12
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_we~8_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .lut_mask = 16'h00F0;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y16_N14
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & (\z80_|decode_state_|DFFE_inst4~q & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ),
|
|
.datac(\z80_|decode_state_|DFFE_inst4~q ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .lut_mask = 16'h0080;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_64~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y16_N30
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout = (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_use_sp~6_combout ),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .lut_mask = 16'h8000;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_76~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y16_N14
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_68 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_68~combout = (\z80_|reg_control_|reg_sel_iy~2_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|reg_control_|reg_sel_iy~2_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_we~8_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .lut_mask = 16'h00C0;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_68 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y15_N0
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout = (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout )))
|
|
|
|
.dataa(\z80_|reg_control_|bank_exx~q ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ),
|
|
.datac(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .lut_mask = 16'h0010;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_40~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y16_N8
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout = (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout )))
|
|
|
|
.dataa(\z80_|reg_control_|bank_exx~q ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .lut_mask = 16'h0200;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_36~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y16_N16
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~18 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ),
|
|
.datac(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[0]~18_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[0]~18 .lut_mask = 16'hFEFE;
|
|
defparam \z80_|reg_file_|gdfx_temp1[0]~18 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y12_N26
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_80 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_80~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (!\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sel_wz~18_combout ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ),
|
|
.datac(\z80_|reg_control_|reg_sys_we_hi~combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .lut_mask = 16'h0C00;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_80 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y13_N14
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal21~2 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal21~2_combout = (\z80_|pla_decode_|Equal40~0_combout & (\z80_|pla_decode_|Equal6~0_combout & !\z80_|ir_|opcode [5]))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal40~0_combout ),
|
|
.datab(\z80_|pla_decode_|Equal6~0_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|ir_|opcode [5]),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal21~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal21~2 .lut_mask = 16'h0088;
|
|
defparam \z80_|pla_decode_|Equal21~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y13_N4
|
|
cycloneive_lcell_comb \z80_|reg_control_|bank_af~0 (
|
|
// Equation(s):
|
|
// \z80_|reg_control_|bank_af~0_combout = \z80_|reg_control_|bank_af~q $ (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|pla_decode_|Equal32~0_combout & \z80_|pla_decode_|Equal21~2_combout ))))
|
|
|
|
.dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ),
|
|
.datab(\z80_|pla_decode_|Equal32~0_combout ),
|
|
.datac(\z80_|reg_control_|bank_af~q ),
|
|
.datad(\z80_|pla_decode_|Equal21~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_control_|bank_af~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_control_|bank_af~0 .lut_mask = 16'hB4F0;
|
|
defparam \z80_|reg_control_|bank_af~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X24_Y13_N5
|
|
dffeas \z80_|reg_control_|bank_af (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_control_|bank_af~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_control_|bank_af~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_control_|bank_af .is_wysiwyg = "true";
|
|
defparam \z80_|reg_control_|bank_af .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y16_N24
|
|
cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af~0 (
|
|
// Equation(s):
|
|
// \z80_|reg_control_|reg_sel_af~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (!\z80_|reg_control_|bank_af~q & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ),
|
|
.datac(\z80_|reg_control_|bank_af~q ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_control_|reg_sel_af~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_control_|reg_sel_af~0 .lut_mask = 16'h0400;
|
|
defparam \z80_|reg_control_|reg_sel_af~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y16_N10
|
|
cycloneive_lcell_comb \z80_|reg_control_|reg_sel_af2~0 (
|
|
// Equation(s):
|
|
// \z80_|reg_control_|reg_sel_af2~0_combout = (!\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & (\z80_|reg_control_|bank_af~q & \z80_|execute_|ctl_reg_gp_sel[0]~35_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ),
|
|
.datac(\z80_|reg_control_|bank_af~q ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_control_|reg_sel_af2~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_control_|reg_sel_af2~0 .lut_mask = 16'h4000;
|
|
defparam \z80_|reg_control_|reg_sel_af2~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y16_N4
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_28 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_28~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & !\z80_|execute_|ctl_reg_gp_we~8_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|reg_control_|reg_sel_af2~0_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_we~8_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .lut_mask = 16'h00A0;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_28 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y16_N18
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~17 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[0]~17_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout & \z80_|reg_control_|reg_sel_af~0_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_68~2_combout ),
|
|
.datac(\z80_|reg_control_|reg_sel_af~0_combout ),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[0]~17_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[0]~17 .lut_mask = 16'hFFEA;
|
|
defparam \z80_|reg_file_|gdfx_temp1[0]~17 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y16_N20
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~19 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[0]~19_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~18_combout ) # (\z80_|reg_file_|gdfx_temp1[0]~17_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ),
|
|
.datac(\z80_|reg_file_|gdfx_temp1[0]~18_combout ),
|
|
.datad(\z80_|reg_file_|gdfx_temp1[0]~17_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[0]~19_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[0]~19 .lut_mask = 16'hFFFE;
|
|
defparam \z80_|reg_file_|gdfx_temp1[0]~19 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y14_N0
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_52 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_52~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|reg_control_|reg_sel_hl2~0_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_reg_gp_we~8_combout ),
|
|
.datad(\z80_|reg_control_|reg_sel_hl2~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .lut_mask = 16'h0A00;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_52 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y16_N28
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_44 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_44~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|reg_control_|reg_sel_de2~4_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ),
|
|
.datad(\z80_|reg_control_|reg_sel_de2~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .lut_mask = 16'h5000;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y16_N30
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_48 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_48~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|reg_control_|reg_sel_de~0_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ),
|
|
.datad(\z80_|reg_control_|reg_sel_de~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .lut_mask = 16'h5000;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_48 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y16_N20
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_56 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_56~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|reg_control_|reg_sel_hl~0_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ),
|
|
.datad(\z80_|reg_control_|reg_sel_hl~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .lut_mask = 16'h5000;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_56 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y16_N2
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~16 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[0]~16_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ),
|
|
.datac(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[0]~16_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[0]~16 .lut_mask = 16'hFFFE;
|
|
defparam \z80_|reg_file_|gdfx_temp1[0]~16 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y16_N6
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~20 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[0]~20_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~19_combout ) # ((\z80_|reg_file_|gdfx_temp1[0]~16_combout ) # (\z80_|execute_|ctl_sw_4u~6_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp1[0]~19_combout ),
|
|
.datac(\z80_|reg_file_|gdfx_temp1[0]~16_combout ),
|
|
.datad(\z80_|execute_|ctl_sw_4u~6_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[0]~20_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[0]~20 .lut_mask = 16'hFFFE;
|
|
defparam \z80_|reg_file_|gdfx_temp1[0]~20 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y16_N6
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|execute_|ctl_reg_gp_we~8_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_we~8_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .lut_mask = 16'hF000;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y16_N4
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|decode_state_|DFFE_inst4~q & (\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & !\z80_|execute_|ctl_reg_gp_sel[0]~35_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ),
|
|
.datab(\z80_|decode_state_|DFFE_inst4~q ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .lut_mask = 16'h0080;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_65~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y16_N7
|
|
dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[2] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y16_N8
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_69 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_69~combout = (\z80_|reg_control_|reg_sel_iy~2_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|execute_|ctl_reg_gp_we~8_combout ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|reg_control_|reg_sel_iy~2_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_we~8_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .lut_mask = 16'hC000;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_69 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y16_N25
|
|
dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[2] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y16_N6
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~34 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[2]~34_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [2]),
|
|
.datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [2]),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[2]~34_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[2]~34 .lut_mask = 16'hF351;
|
|
defparam \z80_|reg_file_|gdfx_temp1[2]~34 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y16_N2
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|execute_|ctl_reg_use_sp~6_combout & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_use_sp~6_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .lut_mask = 16'h8000;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_77~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y15_N15
|
|
dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[2] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_file_|gdfx_temp1[2]~39_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y12_N30
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_81 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_81~combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout & (\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sel_wz~18_combout ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ),
|
|
.datac(\z80_|reg_control_|reg_sys_we_hi~combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .lut_mask = 16'hC000;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_81 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y15_N9
|
|
dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[2] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y15_N8
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~36 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[2]~36_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ),
|
|
.datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [2]),
|
|
.datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [2]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[2]~36_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[2]~36 .lut_mask = 16'hC4F5;
|
|
defparam \z80_|reg_file_|gdfx_temp1[2]~36 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y16_N18
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_29 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_29~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & (\z80_|reg_control_|reg_sel_af2~0_combout & \z80_|execute_|ctl_reg_gp_we~8_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|reg_control_|reg_sel_af2~0_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_we~8_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .lut_mask = 16'hA000;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_29 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y16_N25
|
|
dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[2] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y16_N24
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~35 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[2]~35_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[2]~16_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) #
|
|
// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ),
|
|
.datab(\z80_|alu_|db[2]~16_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [2]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[2]~35_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[2]~35 .lut_mask = 16'hD0DD;
|
|
defparam \z80_|reg_file_|gdfx_temp1[2]~35 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y16_N22
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout = (\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout )))
|
|
|
|
.dataa(\z80_|reg_control_|bank_exx~q ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'h0200;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y16_N31
|
|
dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y16_N20
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout = (!\z80_|reg_control_|bank_exx~q & (!\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_sel[1]~31_combout & \z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout )))
|
|
|
|
.dataa(\z80_|reg_control_|bank_exx~q ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_69~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .lut_mask = 16'h0100;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_41~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y16_N13
|
|
dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[2] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y16_N30
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~33 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[2]~33_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [2]),
|
|
.datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [2]),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[2]~33_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[2]~33 .lut_mask = 16'hF531;
|
|
defparam \z80_|reg_file_|gdfx_temp1[2]~33 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y14_N8
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~37 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[2]~37_combout = (\z80_|reg_file_|gdfx_temp1[2]~34_combout & (\z80_|reg_file_|gdfx_temp1[2]~36_combout & (\z80_|reg_file_|gdfx_temp1[2]~35_combout & \z80_|reg_file_|gdfx_temp1[2]~33_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|gdfx_temp1[2]~34_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp1[2]~36_combout ),
|
|
.datac(\z80_|reg_file_|gdfx_temp1[2]~35_combout ),
|
|
.datad(\z80_|reg_file_|gdfx_temp1[2]~33_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[2]~37_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[2]~37 .lut_mask = 16'h8000;
|
|
defparam \z80_|reg_file_|gdfx_temp1[2]~37 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y15_N20
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_45 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_45~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|reg_control_|reg_sel_de2~4_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|reg_control_|reg_sel_de2~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .lut_mask = 16'h8800;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_45 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y15_N31
|
|
dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[2] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y15_N12
|
|
cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout = \z80_|reg_file_|gdfx_temp1[2]~39_combout
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|reg_file_|gdfx_temp1[2]~39_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder .lut_mask = 16'hFF00;
|
|
defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y16_N24
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_49 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_49~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|reg_control_|reg_sel_de~0_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ),
|
|
.datad(\z80_|reg_control_|reg_sel_de~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .lut_mask = 16'hA000;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_49 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y15_N13
|
|
dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[2] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_file_|b2v_latch_de_hi|latch[2]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_de_hi|latch [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_de_hi|latch[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y15_N30
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~31 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[2]~31_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [2]),
|
|
.datad(\z80_|reg_file_|b2v_latch_de_hi|latch [2]),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[2]~31_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[2]~31 .lut_mask = 16'hF351;
|
|
defparam \z80_|reg_file_|gdfx_temp1[2]~31 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y15_N2
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_33 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_33~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|reg_control_|reg_sel_af~0_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|reg_control_|reg_sel_af~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .lut_mask = 16'h8800;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_33 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X36_Y15_N31
|
|
dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[2] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_af_hi|latch [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_af_hi|latch[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y15_N30
|
|
cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[2]~12 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|b2v_latch_af_hi|db[2]~12_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [2]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_af_hi|latch [2]),
|
|
.datad(\z80_|reg_control_|reg_sel_af~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|b2v_latch_af_hi|db[2]~12_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~12 .lut_mask = 16'hFBFF;
|
|
defparam \z80_|reg_file_|b2v_latch_af_hi|db[2]~12 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y16_N26
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_57 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_57~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|reg_control_|reg_sel_hl~0_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ),
|
|
.datad(\z80_|reg_control_|reg_sel_hl~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .lut_mask = 16'hA000;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_57 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y14_N21
|
|
dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[2] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y14_N2
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_53 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_53~combout = (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & (\z80_|execute_|ctl_reg_gp_we~8_combout & \z80_|reg_control_|reg_sel_hl2~0_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_reg_gp_we~8_combout ),
|
|
.datad(\z80_|reg_control_|reg_sel_hl2~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .lut_mask = 16'hA000;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_53 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y14_N7
|
|
dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[2]~39_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y14_N6
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~32 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[2]~32_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [2] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ),
|
|
.datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [2]),
|
|
.datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [2]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[2]~32_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[2]~32 .lut_mask = 16'hD0DD;
|
|
defparam \z80_|reg_file_|gdfx_temp1[2]~32 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y14_N0
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~38 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[2]~38_combout = (\z80_|reg_file_|gdfx_temp1[2]~37_combout & (\z80_|reg_file_|gdfx_temp1[2]~31_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[2]~12_combout & \z80_|reg_file_|gdfx_temp1[2]~32_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|gdfx_temp1[2]~37_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp1[2]~31_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_af_hi|db[2]~12_combout ),
|
|
.datad(\z80_|reg_file_|gdfx_temp1[2]~32_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[2]~38_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[2]~38 .lut_mask = 16'h8000;
|
|
defparam \z80_|reg_file_|gdfx_temp1[2]~38 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y11_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~11 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_dec~11_combout = (((\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_inc_dec~6_combout ),
|
|
.datab(\z80_|execute_|ctl_bus_inc_oe~42_combout ),
|
|
.datac(\z80_|execute_|ctl_inc_dec~5_combout ),
|
|
.datad(\z80_|execute_|ctl_inc_dec~9_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_dec~11_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_dec~11 .lut_mask = 16'hFF7F;
|
|
defparam \z80_|execute_|ctl_inc_dec~11 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y13_N8
|
|
cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout = \z80_|address_latch_|Q [9] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout )
|
|
|
|
.dataa(\z80_|address_latch_|Q [9]),
|
|
.datab(gnd),
|
|
.datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .lut_mask = 16'h5A5A;
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y14_N31
|
|
dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[1] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_file_|db_hi_as[1]~3_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y17_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~5 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_cf2_sel_shift~5_combout = (\z80_|sequencer_|DFFE_T4_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|pla_decode_|Equal20~0_combout ) # (\z80_|execute_|ctl_ir_we~8_combout ))))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal20~0_combout ),
|
|
.datab(\z80_|sequencer_|DFFE_T4_ff~q ),
|
|
.datac(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.datad(\z80_|execute_|ctl_ir_we~8_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .lut_mask = 16'h0C08;
|
|
defparam \z80_|execute_|ctl_flags_cf2_sel_shift~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y17_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~3 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout = (\z80_|execute_|ctl_state_alu~4_combout ) # ((\z80_|decode_state_|DFFE_instCB~q & (\z80_|pla_decode_|Equal33~0_combout & \z80_|execute_|ctl_mWrite~5_combout )))
|
|
|
|
.dataa(\z80_|decode_state_|DFFE_instCB~q ),
|
|
.datab(\z80_|pla_decode_|Equal33~0_combout ),
|
|
.datac(\z80_|execute_|ctl_mWrite~5_combout ),
|
|
.datad(\z80_|execute_|ctl_state_alu~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .lut_mask = 16'hFF80;
|
|
defparam \z80_|execute_|ctl_flags_cf2_sel_shift~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y17_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_sel_shift~4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_cf2_sel_shift~4_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ) # ((\z80_|execute_|ctl_ir_we~6_combout & (\z80_|execute_|ctl_ir_we~5_combout & \z80_|execute_|ctl_flags_cf2_sel_shift~3_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_cf2_sel_shift~5_combout ),
|
|
.datab(\z80_|execute_|ctl_ir_we~6_combout ),
|
|
.datac(\z80_|execute_|ctl_ir_we~5_combout ),
|
|
.datad(\z80_|execute_|ctl_flags_cf2_sel_shift~3_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .lut_mask = 16'hEAAA;
|
|
defparam \z80_|execute_|ctl_flags_cf2_sel_shift~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y19_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_cf_cpl~4_combout = (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [0] & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal3~1_combout ),
|
|
.datab(\z80_|pla_decode_|Equal13~0_combout ),
|
|
.datac(\z80_|ir_|opcode [0]),
|
|
.datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_cf_cpl~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_cf_cpl~4 .lut_mask = 16'h0008;
|
|
defparam \z80_|execute_|ctl_flags_cf_cpl~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y19_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~5 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_cf_cpl~5_combout = ((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_state_alu~5_combout ) # (\z80_|execute_|ctl_alu_op_low~25_combout )))) # (!\z80_|execute_|ctl_state_alu~13_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_state_alu~5_combout ),
|
|
.datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ),
|
|
.datac(\z80_|execute_|ctl_alu_op_low~25_combout ),
|
|
.datad(\z80_|execute_|ctl_state_alu~13_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_cf_cpl~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_cf_cpl~5 .lut_mask = 16'h32FF;
|
|
defparam \z80_|execute_|ctl_flags_cf_cpl~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y19_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~16 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_sel_op2_neg~16_combout = (\z80_|pla_decode_|Equal9~0_combout & (\z80_|pla_decode_|Equal63~0_combout & ((\z80_|execute_|ctl_eval_cond~0_combout ) # (\z80_|nM1_int~2_combout ))))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal9~0_combout ),
|
|
.datab(\z80_|pla_decode_|Equal63~0_combout ),
|
|
.datac(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.datad(\z80_|nM1_int~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .lut_mask = 16'h8880;
|
|
defparam \z80_|execute_|ctl_alu_sel_op2_neg~16 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y19_N24
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~6 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_cf_cpl~6_combout = (\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf_cpl~4_combout ) # ((\z80_|execute_|ctl_flags_cf_cpl~5_combout )))) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~q &
|
|
// (((\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ))))
|
|
|
|
.dataa(\z80_|alu_flags_|DFFE_inst_latch_nf~q ),
|
|
.datab(\z80_|execute_|ctl_flags_cf_cpl~4_combout ),
|
|
.datac(\z80_|execute_|ctl_flags_cf_cpl~5_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_sel_op2_neg~16_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_cf_cpl~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_cf_cpl~6 .lut_mask = 16'hFDA8;
|
|
defparam \z80_|execute_|ctl_flags_cf_cpl~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y19_N6
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~7 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_cf_cpl~7_combout = (\z80_|execute_|ctl_flags_cf_cpl~6_combout ) # ((\z80_|pla_decode_|Equal9~0_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & \z80_|pla_decode_|Equal62~2_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal9~0_combout ),
|
|
.datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ),
|
|
.datac(\z80_|pla_decode_|Equal62~2_combout ),
|
|
.datad(\z80_|execute_|ctl_flags_cf_cpl~6_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_cf_cpl~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_cf_cpl~7 .lut_mask = 16'hFF20;
|
|
defparam \z80_|execute_|ctl_flags_cf_cpl~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y20_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~10 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_cf_cpl~10_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|execute_|ctl_alu_op_low~25_combout )))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ),
|
|
.datac(\z80_|sequencer_|DFFE_M2_ff~q ),
|
|
.datad(\z80_|execute_|ctl_alu_op_low~25_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_cf_cpl~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_cf_cpl~10 .lut_mask = 16'hDCCC;
|
|
defparam \z80_|execute_|ctl_flags_cf_cpl~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y20_N18
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~8 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_cf_cpl~8_combout = (\z80_|execute_|ctl_flags_cf_cpl~10_combout ) # ((\z80_|execute_|ctl_alu_op_low~34_combout & (\z80_|execute_|ctl_alu_op_low~25_combout & \z80_|execute_|ctl_alu_op_low~22_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op_low~34_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_op_low~25_combout ),
|
|
.datac(\z80_|execute_|ctl_flags_cf_cpl~10_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op_low~22_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_cf_cpl~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_cf_cpl~8 .lut_mask = 16'hF8F0;
|
|
defparam \z80_|execute_|ctl_flags_cf_cpl~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y18_N6
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ixy_d~7_combout & (!\z80_|ir_|opcode [3] & \z80_|pla_decode_|Equal13~0_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal55~0_combout ),
|
|
.datab(\z80_|execute_|ixy_d~7_combout ),
|
|
.datac(\z80_|ir_|opcode [3]),
|
|
.datad(\z80_|pla_decode_|Equal13~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .lut_mask = 16'h0800;
|
|
defparam \z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y20_N24
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~42 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op_low~42_combout = (\z80_|execute_|ctl_alu_op_low~34_combout ) # (!\z80_|execute_|ctl_alu_op_low~48_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_alu_op_low~48_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op_low~34_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op_low~42_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op_low~42 .lut_mask = 16'hFF0F;
|
|
defparam \z80_|execute_|ctl_alu_op_low~42 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y20_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~9 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_cf_cpl~9_combout = (\z80_|execute_|ctl_flags_cf_cpl~7_combout ) # ((\z80_|execute_|ctl_flags_cf_cpl~8_combout ) # ((\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout & \z80_|execute_|ctl_alu_op_low~42_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_cf_cpl~7_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_cf_cpl~8_combout ),
|
|
.datac(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op_low~42_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_cf_cpl~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_cf_cpl~9 .lut_mask = 16'hFEEE;
|
|
defparam \z80_|execute_|ctl_flags_cf_cpl~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y17_N12
|
|
cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout = (\z80_|execute_|ctl_alu_op_low~40_combout & (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ixy_d~6_combout ) # (\z80_|execute_|ctl_mRead~9_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op_low~40_combout ),
|
|
.datab(\z80_|pla_decode_|Equal21~1_combout ),
|
|
.datac(\z80_|execute_|ixy_d~6_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~9_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .lut_mask = 16'h8880;
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y20_N24
|
|
cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout = ((!\z80_|pla_decode_|Equal39~0_combout & ((!\z80_|pla_decode_|Equal40~2_combout ) # (!\z80_|ir_|opcode [5])))) # (!\z80_|execute_|ixy_d~6_combout )
|
|
|
|
.dataa(\z80_|execute_|ixy_d~6_combout ),
|
|
.datab(\z80_|ir_|opcode [5]),
|
|
.datac(\z80_|pla_decode_|Equal40~2_combout ),
|
|
.datad(\z80_|pla_decode_|Equal39~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .lut_mask = 16'h557F;
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y20_N22
|
|
cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout = (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout & ((\z80_|execute_|ctl_alu_op_low~37_combout ) # (\z80_|execute_|ctl_alu_op_low~38_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op_low~37_combout ),
|
|
.datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~6_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_op_low~38_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .lut_mask = 16'h3232;
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y15_N16
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~18 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mWrite~18_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|pla_decode_|Equal11~0_combout & \z80_|sequencer_|DFFE_T3_ff~q ))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_M2_ff~q ),
|
|
.datab(gnd),
|
|
.datac(\z80_|pla_decode_|Equal11~0_combout ),
|
|
.datad(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mWrite~18_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mWrite~18 .lut_mask = 16'hA000;
|
|
defparam \z80_|execute_|ctl_mWrite~18 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y19_N14
|
|
cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout = (!\z80_|execute_|ctl_mWrite~18_combout & (((!\z80_|execute_|ctl_mWrite~17_combout & !\z80_|pla_decode_|Equal61~2_combout )) # (!\z80_|nM1_int~2_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_mWrite~17_combout ),
|
|
.datab(\z80_|pla_decode_|Equal61~2_combout ),
|
|
.datac(\z80_|nM1_int~2_combout ),
|
|
.datad(\z80_|execute_|ctl_mWrite~18_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 .lut_mask = 16'h001F;
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y20_N16
|
|
cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout = (\z80_|nM1_int~2_combout & (!\z80_|execute_|ctl_mRead~34_combout & ((!\z80_|pla_decode_|Equal56~0_combout ) # (!\z80_|execute_|ctl_state_alu~3_combout )))) # (!\z80_|nM1_int~2_combout &
|
|
// (((!\z80_|pla_decode_|Equal56~0_combout ) # (!\z80_|execute_|ctl_state_alu~3_combout ))))
|
|
|
|
.dataa(\z80_|nM1_int~2_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~34_combout ),
|
|
.datac(\z80_|execute_|ctl_state_alu~3_combout ),
|
|
.datad(\z80_|pla_decode_|Equal56~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 .lut_mask = 16'h0777;
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y20_N10
|
|
cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout = (\z80_|execute_|ctl_alu_core_R~4_combout & (\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_core_R~4_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_sys_hilo[0]~12_combout ),
|
|
.datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~1_combout ),
|
|
.datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 .lut_mask = 16'h8000;
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y20_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_cf_cpl~2_combout = (\z80_|execute_|ctl_alu_op_low~37_combout & (((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|ixy_d~6_combout )) # (!\z80_|execute_|ctl_alu_oe~4_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op_low~37_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~34_combout ),
|
|
.datac(\z80_|execute_|ixy_d~6_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_oe~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_cf_cpl~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_cf_cpl~2 .lut_mask = 16'h80AA;
|
|
defparam \z80_|execute_|ctl_flags_cf_cpl~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y20_N2
|
|
cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~3_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~13_combout & (\z80_|execute_|ctl_alu_core_S~7_combout & !\z80_|execute_|ctl_alu_core_R~1_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_sel_op2_neg~13_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_core_S~7_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_core_R~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h0080;
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y20_N6
|
|
cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout & (!\z80_|execute_|ctl_flags_cf_cpl~2_combout & (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout )))
|
|
|
|
.dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~3_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_cf_cpl~2_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT2_2~combout ),
|
|
.datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .lut_mask = 16'h0200;
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y20_N12
|
|
cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout = (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout & (\z80_|execute_|ctl_flags_nf_we~1_combout & (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout )))
|
|
|
|
.dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~5_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_nf_we~1_combout ),
|
|
.datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~7_combout ),
|
|
.datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .lut_mask = 16'h0400;
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y15_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_cf2_we~4_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T3_ff~q & ((\z80_|pla_decode_|Equal11~0_combout ) # (\z80_|pla_decode_|Equal10~0_combout ))))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_M2_ff~q ),
|
|
.datab(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.datac(\z80_|pla_decode_|Equal11~0_combout ),
|
|
.datad(\z80_|pla_decode_|Equal10~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_cf2_we~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_cf2_we~4 .lut_mask = 16'h8880;
|
|
defparam \z80_|execute_|ctl_flags_cf2_we~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y18_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_cf2_we~2_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~38_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ),
|
|
.datac(\z80_|execute_|ctl_alu_op1_sel_bus~8_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_shift_oe~38_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_cf2_we~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_cf2_we~2 .lut_mask = 16'hCFFF;
|
|
defparam \z80_|execute_|ctl_flags_cf2_we~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y18_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf2_we~3 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_cf2_we~3_combout = (\z80_|execute_|ctl_flags_cf2_we~4_combout ) # ((\z80_|execute_|ctl_flags_cf2_we~2_combout ) # ((\z80_|execute_|ixy_d~15_combout & \z80_|sequencer_|DFFE_T3_ff~q )))
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_cf2_we~4_combout ),
|
|
.datab(\z80_|execute_|ixy_d~15_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.datad(\z80_|execute_|ctl_flags_cf2_we~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_cf2_we~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_cf2_we~3 .lut_mask = 16'hFFEA;
|
|
defparam \z80_|execute_|ctl_flags_cf2_we~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X36_Y15_N13
|
|
dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[6] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_file_|gdfx_temp1[6]~84_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_af_hi|latch [6]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_af_hi|latch[6] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y15_N8
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_32 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_32~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout & \z80_|reg_control_|reg_sel_af~0_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|reg_control_|reg_sel_af~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_32 .lut_mask = 16'h4400;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_32 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y15_N21
|
|
dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[6] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[6] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y15_N27
|
|
dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[6] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[6] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y15_N26
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~81 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[6]~81_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ),
|
|
.datab(\z80_|reg_file_|b2v_latch_wz_hi|latch [6]),
|
|
.datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [6]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[6]~81_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[6]~81 .lut_mask = 16'hD0DD;
|
|
defparam \z80_|reg_file_|gdfx_temp1[6]~81 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y16_N22
|
|
cycloneive_lcell_comb \z80_|alu_|db_high[2]~8 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_high[2]~8_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[7]~12_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[5]~24_combout ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|alu_|db[5]~24_combout ),
|
|
.datac(\z80_|alu_|db[7]~12_combout ),
|
|
.datad(\z80_|ir_|opcode [3]),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_high[2]~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_high[2]~8 .lut_mask = 16'hF0CC;
|
|
defparam \z80_|alu_|db_high[2]~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y16_N28
|
|
cycloneive_lcell_comb \z80_|alu_|db_high[2]~9 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_high[2]~9_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[2]~8_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[6]~22_combout ))) #
|
|
// (!\z80_|execute_|ctl_alu_shift_oe~43_combout )
|
|
|
|
.dataa(\z80_|alu_|db[6]~22_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ),
|
|
.datac(\z80_|alu_|db_high[2]~8_combout ),
|
|
.datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_high[2]~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_high[2]~9 .lut_mask = 16'hF3BB;
|
|
defparam \z80_|alu_|db_high[2]~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y17_N14
|
|
cycloneive_lcell_comb \z80_|alu_|db_high[2]~11 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_high[2]~11_combout = (\z80_|bus_control_|db[4]~19_combout & (!\z80_|bus_control_|db[3]~21_combout & \z80_|bus_control_|db[5]~15_combout ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|bus_control_|db[4]~19_combout ),
|
|
.datac(\z80_|bus_control_|db[3]~21_combout ),
|
|
.datad(\z80_|bus_control_|db[5]~15_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_high[2]~11_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_high[2]~11 .lut_mask = 16'h0C00;
|
|
defparam \z80_|alu_|db_high[2]~11 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y17_N18
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[2] (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_op1_latch_mux_high|Q [2] = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & (\z80_|alu_|db_high[2]~13_combout & \z80_|execute_|ctl_alu_op1_sel_bus~15_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op1_sel_zero~combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|alu_|db_high[2]~13_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .lut_mask = 16'h5000;
|
|
defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[2] .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y17_N19
|
|
dffeas \z80_|alu_|op1_high[2] (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|alu_|b2v_op1_latch_mux_high|Q [2]),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|alu_|op1_high [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|op1_high[2] .is_wysiwyg = "true";
|
|
defparam \z80_|alu_|op1_high[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y18_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_lq (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op2_sel_lq~combout = (\z80_|pla_decode_|Equal13~2_combout & ((\z80_|execute_|ixy_d~7_combout ) # ((\z80_|execute_|ixy_d~6_combout & !\z80_|ir_|opcode [3]))))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal13~2_combout ),
|
|
.datab(\z80_|execute_|ixy_d~7_combout ),
|
|
.datac(\z80_|execute_|ixy_d~6_combout ),
|
|
.datad(\z80_|ir_|opcode [3]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op2_sel_lq~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op2_sel_lq .lut_mask = 16'h88A8;
|
|
defparam \z80_|execute_|ctl_alu_op2_sel_lq .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y18_N6
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & \z80_|alu_|db_low[2]~23_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ),
|
|
.datad(\z80_|alu_|db_low[2]~23_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 .lut_mask = 16'hF000;
|
|
defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y19_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~5 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op2_sel_bus~5_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|ctl_alu_core_R~0_combout & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T3_ff~q ))))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T4_ff~q ),
|
|
.datab(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ),
|
|
.datad(\z80_|execute_|ctl_alu_core_R~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op2_sel_bus~5 .lut_mask = 16'hFEF0;
|
|
defparam \z80_|execute_|ctl_alu_op2_sel_bus~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y17_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~6 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op2_sel_bus~6_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ) # ((\z80_|execute_|ctl_alu_op_low~47_combout ) # ((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal13~2_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op2_sel_bus~5_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ),
|
|
.datac(\z80_|pla_decode_|Equal13~2_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op_low~47_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .lut_mask = 16'hFFEA;
|
|
defparam \z80_|execute_|ctl_alu_op2_sel_bus~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y18_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~7 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op2_sel_bus~7_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~4_combout & (\z80_|execute_|ctl_reg_use_sp~0_combout & \z80_|execute_|nextM~11_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op2_sel_bus~4_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_reg_use_sp~0_combout ),
|
|
.datad(\z80_|execute_|nextM~11_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .lut_mask = 16'hA000;
|
|
defparam \z80_|execute_|ctl_alu_op2_sel_bus~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y19_N2
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_bus~8 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op2_sel_bus~8_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ) # (((!\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ) # (!\z80_|execute_|ctl_alu_op1_sel_bus~14_combout )) # (!\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op2_sel_bus~6_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_op2_sel_bus~10_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_op1_sel_bus~14_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op2_sel_bus~7_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .lut_mask = 16'hBFFF;
|
|
defparam \z80_|execute_|ctl_alu_op2_sel_bus~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y19_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op2_sel_zero (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op2_sel_zero~combout = (((\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ) # (!\z80_|execute_|ctl_alu_shift_oe~38_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_hilo[1]~36_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_out_hi~4_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_shift_oe~38_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_hilo_pla26M1T4_3~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op2_sel_zero~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op2_sel_zero .lut_mask = 16'hFF7F;
|
|
defparam \z80_|execute_|ctl_alu_op2_sel_zero .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y18_N10
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ) # ((\z80_|alu_|db_high[2]~13_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout ))))
|
|
|
|
.dataa(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~2_combout ),
|
|
.datab(\z80_|alu_|db_high[2]~13_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op2_sel_zero~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .lut_mask = 16'h00EA;
|
|
defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y18_N0
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|ena (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_op2_latch_mux_high|ena~combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout ) # ((\z80_|execute_|ctl_alu_op2_sel_zero~combout ) # (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op2_sel_lq~combout ),
|
|
.datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ),
|
|
.datac(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .lut_mask = 16'hFEFE;
|
|
defparam \z80_|alu_|b2v_op2_latch_mux_high|ena .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y18_N11
|
|
dffeas \z80_|alu_|op2_high[2] (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|alu_|b2v_op2_latch_mux_high|Q[2]~3_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|alu_|op2_high [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|op2_high[2] .is_wysiwyg = "true";
|
|
defparam \z80_|alu_|op2_high[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y17_N28
|
|
cycloneive_lcell_comb \z80_|alu_|db_high[2]~10 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_high[2]~10_combout = (\z80_|alu_|op1_high [2] & (((\z80_|alu_|op2_high [2]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|alu_|op1_high [2] & (!\z80_|execute_|ctl_alu_op1_oe~1_combout & ((\z80_|alu_|op2_high [2]) #
|
|
// (!\z80_|execute_|ctl_alu_op2_oe~0_combout ))))
|
|
|
|
.dataa(\z80_|alu_|op1_high [2]),
|
|
.datab(\z80_|execute_|ctl_alu_op1_oe~1_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ),
|
|
.datad(\z80_|alu_|op2_high [2]),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_high[2]~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_high[2]~10 .lut_mask = 16'hBB0B;
|
|
defparam \z80_|alu_|db_high[2]~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y17_N16
|
|
cycloneive_lcell_comb \z80_|alu_|db_high[2]~12 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_high[2]~12_combout = (\z80_|alu_|db_high[2]~9_combout & (\z80_|alu_|db_high[2]~10_combout & ((\z80_|alu_|db_high[2]~11_combout ) # (!\z80_|execute_|ctl_alu_bs_oe~combout ))))
|
|
|
|
.dataa(\z80_|alu_|db_high[2]~9_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_bs_oe~combout ),
|
|
.datac(\z80_|alu_|db_high[2]~11_combout ),
|
|
.datad(\z80_|alu_|db_high[2]~10_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_high[2]~12_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_high[2]~12 .lut_mask = 16'hA200;
|
|
defparam \z80_|alu_|db_high[2]~12 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y16_N6
|
|
cycloneive_lcell_comb \z80_|alu_|db_high[3]~1 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_high[3]~1_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout ) # (\z80_|alu_|db_high[3]~0_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|alu_|db_high[3]~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_high[3]~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_high[3]~1 .lut_mask = 16'hFFCC;
|
|
defparam \z80_|alu_|db_high[3]~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y16_N0
|
|
cycloneive_lcell_comb \z80_|alu_|db_high[2]~13 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_high[2]~13_combout = ((\z80_|alu_|db_high[2]~12_combout & ((\z80_|execute_|ctl_alu_res_oe~3_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_res_oe~3_combout ),
|
|
.datab(\z80_|alu_|db_high[2]~12_combout ),
|
|
.datac(\z80_|alu_|db_high[3]~1_combout ),
|
|
.datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_high[2]~13_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_high[2]~13 .lut_mask = 16'hCF8F;
|
|
defparam \z80_|alu_|db_high[2]~13 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X31_Y12_N29
|
|
dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[6] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[6] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X31_Y12_N19
|
|
dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[6] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[6] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y12_N18
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~78 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[6]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [6]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ),
|
|
.datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [6]),
|
|
.datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [6]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[6]~78_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[6]~78 .lut_mask = 16'hC4F5;
|
|
defparam \z80_|reg_file_|gdfx_temp0[6]~78 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y16_N26
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout = (\z80_|execute_|ctl_reg_use_sp~6_combout & (\z80_|execute_|ctl_reg_gp_sel[0]~35_combout & (\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout & \z80_|execute_|ctl_reg_gp_sel[1]~31_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_use_sp~6_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_sel[0]~35_combout ),
|
|
.datac(\z80_|reg_file_|SYNTHESIZED_WIRE_70~2_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_sel[1]~31_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .lut_mask = 16'h8000;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_78~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y12_N5
|
|
dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[6] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[6] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y12_N4
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~79 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[6]~79_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [6] & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[6]~22_combout ) # ((!\z80_|execute_|ctl_reg_in_lo~8_combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ),
|
|
.datab(\z80_|alu_control_|db[6]~22_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [6]),
|
|
.datad(\z80_|execute_|ctl_reg_in_lo~8_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[6]~79_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[6]~79 .lut_mask = 16'hC4F5;
|
|
defparam \z80_|reg_file_|gdfx_temp0[6]~79 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y13_N10
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_34 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_34~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|reg_control_|reg_sel_af~0_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .lut_mask = 16'h5000;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y13_N18
|
|
cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder .lut_mask = 16'hFF00;
|
|
defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y13_N0
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_35 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_35~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|reg_control_|reg_sel_af~0_combout & \z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|reg_control_|reg_sel_af~0_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hA000;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X31_Y13_N19
|
|
dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[6] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_file_|b2v_latch_af_lo|latch[6]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_af_lo|latch [6]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_af_lo|latch[6] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y13_N14
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_31 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_31~combout = (\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & \z80_|reg_control_|reg_sel_af2~0_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ),
|
|
.datac(\z80_|reg_control_|reg_sel_af2~0_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .lut_mask = 16'h8080;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_31 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X31_Y13_N21
|
|
dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[6] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[6] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y13_N28
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_30 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_30~combout = (!\z80_|execute_|ctl_reg_gp_we~8_combout & (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & \z80_|reg_control_|reg_sel_af2~0_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ),
|
|
.datac(\z80_|reg_control_|reg_sel_af2~0_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .lut_mask = 16'h4040;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_30 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y13_N20
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~75 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[6]~75_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (\z80_|reg_file_|b2v_latch_af_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_af2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (((\z80_|reg_file_|b2v_latch_af2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ),
|
|
.datab(\z80_|reg_file_|b2v_latch_af_lo|latch [6]),
|
|
.datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [6]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[6]~75_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[6]~75 .lut_mask = 16'hD0DD;
|
|
defparam \z80_|reg_file_|gdfx_temp0[6]~75 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y14_N20
|
|
cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp0[6]~82_combout
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder .lut_mask = 16'hFF00;
|
|
defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y14_N21
|
|
dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[6] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_file_|b2v_latch_bc_lo|latch[6]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[6] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y14_N31
|
|
dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[6] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y14_N30
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~76 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [6]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ),
|
|
.datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [6]),
|
|
.datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [6]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[6]~76_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[6]~76 .lut_mask = 16'hC4F5;
|
|
defparam \z80_|reg_file_|gdfx_temp0[6]~76 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y13_N21
|
|
dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[6] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[6] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y13_N20
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~77 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[6]~77_combout = (\z80_|reg_file_|gdfx_temp0[6]~76_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))
|
|
|
|
.dataa(\z80_|reg_file_|gdfx_temp0[6]~76_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [6]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[6]~77_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[6]~77 .lut_mask = 16'hA0AA;
|
|
defparam \z80_|reg_file_|gdfx_temp0[6]~77 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y12_N12
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~80 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[6]~80_combout = (\z80_|reg_file_|gdfx_temp0[6]~78_combout & (\z80_|reg_file_|gdfx_temp0[6]~79_combout & (\z80_|reg_file_|gdfx_temp0[6]~75_combout & \z80_|reg_file_|gdfx_temp0[6]~77_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|gdfx_temp0[6]~78_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp0[6]~79_combout ),
|
|
.datac(\z80_|reg_file_|gdfx_temp0[6]~75_combout ),
|
|
.datad(\z80_|reg_file_|gdfx_temp0[6]~77_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[6]~80_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[6]~80 .lut_mask = 16'h8000;
|
|
defparam \z80_|reg_file_|gdfx_temp0[6]~80 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X29_Y12_N1
|
|
dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[6] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[6] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X29_Y12_N3
|
|
dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[6] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y12_N2
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~74 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[6]~74_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [6] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ),
|
|
.datab(\z80_|reg_file_|b2v_latch_hl_lo|latch [6]),
|
|
.datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [6]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[6]~74_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[6]~74 .lut_mask = 16'hD0DD;
|
|
defparam \z80_|reg_file_|gdfx_temp0[6]~74 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X30_Y11_N13
|
|
dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[6] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_de_lo|latch [6]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_de_lo|latch[6] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X30_Y11_N11
|
|
dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[6] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[6]~82_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[6] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y11_N10
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~73 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[6]~73_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [6] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [6] &
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [6]),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [6]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[6]~73_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[6]~73 .lut_mask = 16'hB0BB;
|
|
defparam \z80_|reg_file_|gdfx_temp0[6]~73 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y12_N22
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~81 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[6]~81_combout = (\z80_|reg_file_|gdfx_temp0[6]~80_combout & (\z80_|reg_file_|gdfx_temp0[6]~74_combout & \z80_|reg_file_|gdfx_temp0[6]~73_combout ))
|
|
|
|
.dataa(\z80_|reg_file_|gdfx_temp0[6]~80_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp0[6]~74_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|reg_file_|gdfx_temp0[6]~73_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[6]~81_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[6]~81 .lut_mask = 16'h8800;
|
|
defparam \z80_|reg_file_|gdfx_temp0[6]~81 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y12_N24
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~19 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[0]~19_combout = (\z80_|execute_|ctl_sw_4u~6_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ) # (\z80_|execute_|ctl_reg_in_lo~8_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_sw_4u~6_combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ),
|
|
.datac(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_in_lo~8_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[0]~19_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[0]~19 .lut_mask = 16'hFFFE;
|
|
defparam \z80_|reg_file_|gdfx_temp0[0]~19 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y12_N18
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~18 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[0]~18_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ),
|
|
.datac(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[0]~18_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[0]~18 .lut_mask = 16'hFFFE;
|
|
defparam \z80_|reg_file_|gdfx_temp0[0]~18 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y12_N30
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~20 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[0]~20_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~19_combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ) # (\z80_|reg_file_|gdfx_temp0[0]~18_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp0[0]~19_combout ),
|
|
.datac(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ),
|
|
.datad(\z80_|reg_file_|gdfx_temp0[0]~18_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[0]~20_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[0]~20 .lut_mask = 16'hFFFE;
|
|
defparam \z80_|reg_file_|gdfx_temp0[0]~20 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y12_N10
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~92 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[0]~92_combout = (\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout & (!\z80_|execute_|ctl_reg_gp_we~8_combout & ((\z80_|reg_control_|reg_sel_hl2~0_combout ) # (\z80_|reg_control_|reg_sel_hl~0_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ),
|
|
.datab(\z80_|reg_control_|reg_sel_hl2~0_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_we~8_combout ),
|
|
.datad(\z80_|reg_control_|reg_sel_hl~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[0]~92_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[0]~92 .lut_mask = 16'h0A08;
|
|
defparam \z80_|reg_file_|gdfx_temp0[0]~92 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y11_N12
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~21 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[0]~21_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ) # ((\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ) # ((\z80_|reg_file_|gdfx_temp0[0]~20_combout ) # (\z80_|reg_file_|gdfx_temp0[0]~92_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ),
|
|
.datac(\z80_|reg_file_|gdfx_temp0[0]~20_combout ),
|
|
.datad(\z80_|reg_file_|gdfx_temp0[0]~92_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[0]~21_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[0]~21 .lut_mask = 16'hFFFE;
|
|
defparam \z80_|reg_file_|gdfx_temp0[0]~21 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y12_N4
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_74 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_74~combout = (\z80_|reg_control_|reg_sel_pc~combout & (!\z80_|reg_control_|reg_sys_we_lo~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ))
|
|
|
|
.dataa(\z80_|reg_control_|reg_sel_pc~combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|reg_control_|reg_sys_we_lo~combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .lut_mask = 16'h0A00;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_74 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y12_N6
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_62 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_62~combout = (\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout & (!\z80_|reg_control_|reg_sys_we_lo~combout & \z80_|execute_|ctl_reg_sel_ir~1_combout ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ),
|
|
.datac(\z80_|reg_control_|reg_sys_we_lo~combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sel_ir~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .lut_mask = 16'h0C00;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_62 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y12_N26
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~2 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_lo_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ) # ((\z80_|execute_|ctl_sw_4d~6_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~43_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ),
|
|
.datab(\z80_|execute_|ctl_sw_4d~6_combout ),
|
|
.datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_lo_as[0]~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_lo_as[0]~2 .lut_mask = 16'hFFFE;
|
|
defparam \z80_|reg_file_|db_lo_as[0]~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y12_N13
|
|
dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[4] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_file_|db_lo_as[4]~15_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X31_Y12_N9
|
|
dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[4] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y12_N3
|
|
dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[4] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y12_N8
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~55 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[4]~55_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_sp_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [4]),
|
|
.datad(\z80_|reg_file_|b2v_latch_sp_lo|latch [4]),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[4]~55_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[4]~55 .lut_mask = 16'hF531;
|
|
defparam \z80_|reg_file_|gdfx_temp0[4]~55 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X31_Y12_N23
|
|
dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[4] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y12_N22
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~56 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[4]~56_combout = (\z80_|reg_file_|gdfx_temp0[4]~55_combout & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|reg_file_|gdfx_temp0[4]~55_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [4]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[4]~56_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[4]~56 .lut_mask = 16'hC0CC;
|
|
defparam \z80_|reg_file_|gdfx_temp0[4]~56 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X30_Y12_N13
|
|
dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[4] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X30_Y12_N23
|
|
dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y12_N22
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~57 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[4]~57_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [4] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [4] &
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [4]),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [4]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[4]~57_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[4]~57 .lut_mask = 16'hA2F3;
|
|
defparam \z80_|reg_file_|gdfx_temp0[4]~57 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y14_N5
|
|
dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[4] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y14_N11
|
|
dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y14_N10
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~59 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[4]~59_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [4]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ),
|
|
.datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [4]),
|
|
.datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [4]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[4]~59_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[4]~59 .lut_mask = 16'hC4F5;
|
|
defparam \z80_|reg_file_|gdfx_temp0[4]~59 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X31_Y13_N17
|
|
dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[4] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_af_lo|latch [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_af_lo|latch[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X31_Y13_N31
|
|
dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[4] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y13_N30
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~58 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[4]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (\z80_|reg_file_|b2v_latch_af_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_af2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout & (((\z80_|reg_file_|b2v_latch_af2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ),
|
|
.datab(\z80_|reg_file_|b2v_latch_af_lo|latch [4]),
|
|
.datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [4]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[4]~58_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[4]~58 .lut_mask = 16'hD0DD;
|
|
defparam \z80_|reg_file_|gdfx_temp0[4]~58 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y13_N1
|
|
dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[4] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y13_N0
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~60 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[4]~60_combout = (\z80_|reg_file_|gdfx_temp0[4]~59_combout & (\z80_|reg_file_|gdfx_temp0[4]~58_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|gdfx_temp0[4]~59_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp0[4]~58_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [4]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[4]~60_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[4]~60 .lut_mask = 16'h8088;
|
|
defparam \z80_|reg_file_|gdfx_temp0[4]~60 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X31_Y11_N23
|
|
dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[4] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X31_Y11_N17
|
|
dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[4] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[4]~62_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_de_lo|latch [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_de_lo|latch[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y11_N22
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~53 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[4]~53_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [4] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [4]),
|
|
.datad(\z80_|reg_file_|b2v_latch_de_lo|latch [4]),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[4]~53_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[4]~53 .lut_mask = 16'hF351;
|
|
defparam \z80_|reg_file_|gdfx_temp0[4]~53 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y13_N22
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~54 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[4]~54_combout = (\z80_|reg_file_|gdfx_temp0[4]~53_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|alu_control_|db[4]~32_combout ),
|
|
.datad(\z80_|reg_file_|gdfx_temp0[4]~53_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[4]~54_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[4]~54 .lut_mask = 16'hF500;
|
|
defparam \z80_|reg_file_|gdfx_temp0[4]~54 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y13_N8
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~61 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[4]~61_combout = (\z80_|reg_file_|gdfx_temp0[4]~56_combout & (\z80_|reg_file_|gdfx_temp0[4]~57_combout & (\z80_|reg_file_|gdfx_temp0[4]~60_combout & \z80_|reg_file_|gdfx_temp0[4]~54_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|gdfx_temp0[4]~56_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp0[4]~57_combout ),
|
|
.datac(\z80_|reg_file_|gdfx_temp0[4]~60_combout ),
|
|
.datad(\z80_|reg_file_|gdfx_temp0[4]~54_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[4]~61_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[4]~61 .lut_mask = 16'h8000;
|
|
defparam \z80_|reg_file_|gdfx_temp0[4]~61 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y12_N8
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[4]~62 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[4]~62_combout = ((\z80_|reg_file_|gdfx_temp0[4]~61_combout & ((\z80_|reg_file_|db_lo_as[4]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout )
|
|
|
|
.dataa(\z80_|reg_file_|gdfx_temp0[4]~61_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ),
|
|
.datac(\z80_|execute_|ctl_sw_4u~6_combout ),
|
|
.datad(\z80_|reg_file_|db_lo_as[4]~15_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[4]~62_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[4]~62 .lut_mask = 16'hBB3B;
|
|
defparam \z80_|reg_file_|gdfx_temp0[4]~62 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y12_N10
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_75 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_75~combout = (\z80_|reg_control_|reg_sel_pc~combout & (\z80_|reg_control_|reg_sys_we_lo~combout & \z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ))
|
|
|
|
.dataa(\z80_|reg_control_|reg_sel_pc~combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|reg_control_|reg_sys_we_lo~combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .lut_mask = 16'hA000;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_75 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y12_N3
|
|
dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[4] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|db_lo_as[4]~15_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y12_N2
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~13 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_lo_as[4]~13_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[4]~62_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) #
|
|
// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_sw_4d~6_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp0[4]~62_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [4]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_lo_as[4]~13_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_lo_as[4]~13 .lut_mask = 16'hD0DD;
|
|
defparam \z80_|reg_file_|db_lo_as[4]~13 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y12_N18
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~14 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_lo_as[4]~14_combout = (\z80_|reg_file_|db_lo_as[4]~13_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout )))
|
|
|
|
.dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [4]),
|
|
.datab(\z80_|reg_file_|db_lo_as[4]~13_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_lo_as[4]~14_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_lo_as[4]~14 .lut_mask = 16'h88CC;
|
|
defparam \z80_|reg_file_|db_lo_as[4]~14 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y12_N16
|
|
cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout = \z80_|address_latch_|Q [4] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|address_latch_|Q [4]),
|
|
.datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .lut_mask = 16'h0FF0;
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y12_N12
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[4]~15 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_lo_as[4]~15_combout = ((\z80_|reg_file_|db_lo_as[4]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ),
|
|
.datab(\z80_|reg_file_|db_lo_as[4]~14_combout ),
|
|
.datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ),
|
|
.datad(\z80_|reg_file_|db_lo_as[0]~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_lo_as[4]~15_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_lo_as[4]~15 .lut_mask = 16'hC4FF;
|
|
defparam \z80_|reg_file_|db_lo_as[4]~15 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y10_N12
|
|
cycloneive_lcell_comb \z80_|address_latch_|abusz[4] (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|abusz [4] = (\z80_|reg_file_|db_lo_as[4]~15_combout & !\z80_|resets_|clrpc~0_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|reg_file_|db_lo_as[4]~15_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|resets_|clrpc~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|abusz [4]),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|abusz[4] .lut_mask = 16'h00CC;
|
|
defparam \z80_|address_latch_|abusz[4] .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y10_N13
|
|
dffeas \z80_|address_latch_|Q[4] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|address_latch_|abusz [4]),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|execute_|ctl_al_we~12_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|address_latch_|Q [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|Q[4] .is_wysiwyg = "true";
|
|
defparam \z80_|address_latch_|Q[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y12_N20
|
|
cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout = \z80_|address_latch_|Q [5] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|execute_|ctl_inc_dec~11_combout $ (\z80_|address_latch_|Q
|
|
// [4])))))
|
|
|
|
.dataa(\z80_|execute_|ctl_inc_dec~11_combout ),
|
|
.datab(\z80_|address_latch_|Q [4]),
|
|
.datac(\z80_|address_latch_|Q [5]),
|
|
.datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .lut_mask = 16'h96F0;
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X36_Y12_N29
|
|
dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[5] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_file_|db_lo_as[5]~18_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[5] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X30_Y12_N17
|
|
dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[5] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[5] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X30_Y12_N15
|
|
dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[5] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y12_N14
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~64 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[5]~64_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [5] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [5] &
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [5]),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [5]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[5]~64_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[5]~64 .lut_mask = 16'hA2F3;
|
|
defparam \z80_|reg_file_|gdfx_temp0[5]~64 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X31_Y11_N27
|
|
dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[5] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[5] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X31_Y11_N25
|
|
dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[5] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_de_lo|latch [5]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_de_lo|latch[5] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y11_N26
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~63 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[5]~63_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [5]),
|
|
.datad(\z80_|reg_file_|b2v_latch_de_lo|latch [5]),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[5]~63_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[5]~63 .lut_mask = 16'hF351;
|
|
defparam \z80_|reg_file_|gdfx_temp0[5]~63 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y11_N17
|
|
dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[5] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[5] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y11_N18
|
|
cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp0[5]~72_combout
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|reg_file_|gdfx_temp0[5]~72_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder .lut_mask = 16'hFF00;
|
|
defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y11_N19
|
|
dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[5] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_file_|b2v_latch_af_lo|latch[5]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_af_lo|latch [5]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_af_lo|latch[5] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y11_N16
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~65 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[5]~65_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [5]),
|
|
.datad(\z80_|reg_file_|b2v_latch_af_lo|latch [5]),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[5]~65_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[5]~65 .lut_mask = 16'hF531;
|
|
defparam \z80_|reg_file_|gdfx_temp0[5]~65 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X31_Y12_N21
|
|
dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[5] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_file_|gdfx_temp0[5]~72_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[5] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y12_N23
|
|
dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[5] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[5] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y12_N22
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~69 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[5]~69_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ),
|
|
.datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [5]),
|
|
.datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [5]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[5]~69_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[5]~69 .lut_mask = 16'hC4F5;
|
|
defparam \z80_|reg_file_|gdfx_temp0[5]~69 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y13_N29
|
|
dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[5] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[5] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y14_N27
|
|
dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[5] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[5] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y14_N26
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~68 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[5]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [5] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ),
|
|
.datab(\z80_|reg_file_|b2v_latch_ix_lo|latch [5]),
|
|
.datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [5]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[5]~68_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[5]~68 .lut_mask = 16'hD0DD;
|
|
defparam \z80_|reg_file_|gdfx_temp0[5]~68 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y13_N3
|
|
dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[5] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[5] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y14_N17
|
|
dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[5]~72_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[5] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y14_N16
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~66 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[5]~66_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [5] & ((\z80_|alu_control_|db[5]~15_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|alu_control_|db[5]~15_combout ) # ((!\z80_|execute_|ctl_reg_in_lo~8_combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ),
|
|
.datab(\z80_|alu_control_|db[5]~15_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [5]),
|
|
.datad(\z80_|execute_|ctl_reg_in_lo~8_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[5]~66_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[5]~66 .lut_mask = 16'hC4F5;
|
|
defparam \z80_|reg_file_|gdfx_temp0[5]~66 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y13_N2
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~67 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[5]~67_combout = (\z80_|reg_file_|gdfx_temp0[5]~66_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [5]),
|
|
.datad(\z80_|reg_file_|gdfx_temp0[5]~66_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[5]~67_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[5]~67 .lut_mask = 16'hF300;
|
|
defparam \z80_|reg_file_|gdfx_temp0[5]~67 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y13_N26
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~70 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[5]~70_combout = (\z80_|reg_file_|gdfx_temp0[5]~65_combout & (\z80_|reg_file_|gdfx_temp0[5]~69_combout & (\z80_|reg_file_|gdfx_temp0[5]~68_combout & \z80_|reg_file_|gdfx_temp0[5]~67_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|gdfx_temp0[5]~65_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp0[5]~69_combout ),
|
|
.datac(\z80_|reg_file_|gdfx_temp0[5]~68_combout ),
|
|
.datad(\z80_|reg_file_|gdfx_temp0[5]~67_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[5]~70_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[5]~70 .lut_mask = 16'h8000;
|
|
defparam \z80_|reg_file_|gdfx_temp0[5]~70 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y12_N6
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~71 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[5]~71_combout = (\z80_|reg_file_|gdfx_temp0[5]~64_combout & (\z80_|reg_file_|gdfx_temp0[5]~63_combout & \z80_|reg_file_|gdfx_temp0[5]~70_combout ))
|
|
|
|
.dataa(\z80_|reg_file_|gdfx_temp0[5]~64_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp0[5]~63_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|reg_file_|gdfx_temp0[5]~70_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[5]~71_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[5]~71 .lut_mask = 16'h8800;
|
|
defparam \z80_|reg_file_|gdfx_temp0[5]~71 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y12_N20
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[5]~72 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[5]~72_combout = ((\z80_|reg_file_|gdfx_temp0[5]~71_combout & ((\z80_|reg_file_|db_lo_as[5]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout )
|
|
|
|
.dataa(\z80_|reg_file_|gdfx_temp0[5]~71_combout ),
|
|
.datab(\z80_|reg_file_|db_lo_as[5]~18_combout ),
|
|
.datac(\z80_|reg_file_|gdfx_temp0[0]~21_combout ),
|
|
.datad(\z80_|execute_|ctl_sw_4u~6_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[5]~72_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[5]~72 .lut_mask = 16'h8FAF;
|
|
defparam \z80_|reg_file_|gdfx_temp0[5]~72 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X36_Y12_N7
|
|
dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[5] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|db_lo_as[5]~18_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[5] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y12_N6
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~16 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_lo_as[5]~16_combout = (\z80_|reg_file_|gdfx_temp0[5]~72_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[5]~72_combout &
|
|
// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|gdfx_temp0[5]~72_combout ),
|
|
.datab(\z80_|execute_|ctl_sw_4d~6_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [5]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_lo_as[5]~16_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_lo_as[5]~16 .lut_mask = 16'hB0BB;
|
|
defparam \z80_|reg_file_|db_lo_as[5]~16 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y12_N14
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~17 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_lo_as[5]~17_combout = (\z80_|reg_file_|db_lo_as[5]~16_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout )))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|reg_file_|b2v_latch_ir_lo|latch [5]),
|
|
.datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ),
|
|
.datad(\z80_|reg_file_|db_lo_as[5]~16_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_lo_as[5]~17_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_lo_as[5]~17 .lut_mask = 16'hCF00;
|
|
defparam \z80_|reg_file_|db_lo_as[5]~17 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y12_N28
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[5]~18 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_lo_as[5]~18_combout = ((\z80_|reg_file_|db_lo_as[5]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout )
|
|
|
|
.dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ),
|
|
.datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ),
|
|
.datac(\z80_|reg_file_|db_lo_as[5]~17_combout ),
|
|
.datad(\z80_|execute_|ctl_bus_inc_oe~43_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_lo_as[5]~18_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_lo_as[5]~18 .lut_mask = 16'hD5F5;
|
|
defparam \z80_|reg_file_|db_lo_as[5]~18 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y10_N8
|
|
cycloneive_lcell_comb \z80_|address_latch_|abusz[5] (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|abusz [5] = (\z80_|reg_file_|db_lo_as[5]~18_combout & !\z80_|resets_|clrpc~0_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|reg_file_|db_lo_as[5]~18_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|resets_|clrpc~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|abusz [5]),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|abusz[5] .lut_mask = 16'h00CC;
|
|
defparam \z80_|address_latch_|abusz[5] .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y10_N9
|
|
dffeas \z80_|address_latch_|Q[5] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|address_latch_|abusz [5]),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|execute_|ctl_al_we~12_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|address_latch_|Q [5]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|Q[5] .is_wysiwyg = "true";
|
|
defparam \z80_|address_latch_|Q[5] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y11_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_dec~10 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_dec~10_combout = (\z80_|execute_|ctl_inc_dec~9_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_inc_dec~6_combout ),
|
|
.datad(\z80_|execute_|ctl_inc_dec~9_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_dec~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_dec~10 .lut_mask = 16'hFF0F;
|
|
defparam \z80_|execute_|ctl_inc_dec~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y11_N30
|
|
cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout = \z80_|address_latch_|Q [5] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout )))
|
|
|
|
.dataa(\z80_|address_latch_|Q [5]),
|
|
.datab(\z80_|execute_|ctl_bus_inc_oe~42_combout ),
|
|
.datac(\z80_|execute_|ctl_inc_dec~10_combout ),
|
|
.datad(\z80_|execute_|ctl_inc_dec~5_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 .lut_mask = 16'h5955;
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y11_N8
|
|
cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout = \z80_|address_latch_|Q [4] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout )) # (!\z80_|execute_|ctl_inc_dec~5_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_inc_dec~5_combout ),
|
|
.datab(\z80_|execute_|ctl_bus_inc_oe~42_combout ),
|
|
.datac(\z80_|execute_|ctl_inc_dec~10_combout ),
|
|
.datad(\z80_|address_latch_|Q [4]),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .lut_mask = 16'h08F7;
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y10_N20
|
|
cycloneive_lcell_comb \z80_|address_latch_|abusz[6] (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|abusz [6] = (\z80_|reg_file_|db_lo_as[6]~21_combout & !\z80_|resets_|clrpc~0_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|reg_file_|db_lo_as[6]~21_combout ),
|
|
.datad(\z80_|resets_|clrpc~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|abusz [6]),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|abusz[6] .lut_mask = 16'h00F0;
|
|
defparam \z80_|address_latch_|abusz[6] .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y10_N21
|
|
dffeas \z80_|address_latch_|Q[6] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|address_latch_|abusz [6]),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|execute_|ctl_al_we~12_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|address_latch_|Q [6]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|Q[6] .is_wysiwyg = "true";
|
|
defparam \z80_|address_latch_|Q[6] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y11_N20
|
|
cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[6] (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|b2v_inst_inc_dec|address [6] = \z80_|address_latch_|Q [6] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout &
|
|
// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ))))
|
|
|
|
.dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ),
|
|
.datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ),
|
|
.datac(\z80_|address_latch_|Q [6]),
|
|
.datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|b2v_inst_inc_dec|address [6]),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .lut_mask = 16'h78F0;
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|address[6] .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X36_Y12_N25
|
|
dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[6] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_file_|db_lo_as[6]~21_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[6] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X36_Y12_N11
|
|
dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[6] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|db_lo_as[6]~21_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[6] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y12_N10
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~19 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_lo_as[6]~19_combout = (\z80_|reg_file_|gdfx_temp0[6]~82_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) # (!\z80_|reg_file_|gdfx_temp0[6]~82_combout &
|
|
// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|gdfx_temp0[6]~82_combout ),
|
|
.datab(\z80_|execute_|ctl_sw_4d~6_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [6]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_lo_as[6]~19_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_lo_as[6]~19 .lut_mask = 16'hB0BB;
|
|
defparam \z80_|reg_file_|db_lo_as[6]~19 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y12_N22
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~20 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_lo_as[6]~20_combout = (\z80_|reg_file_|db_lo_as[6]~19_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout )))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|reg_file_|b2v_latch_ir_lo|latch [6]),
|
|
.datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ),
|
|
.datad(\z80_|reg_file_|db_lo_as[6]~19_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_lo_as[6]~20_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_lo_as[6]~20 .lut_mask = 16'hCF00;
|
|
defparam \z80_|reg_file_|db_lo_as[6]~20 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y12_N24
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[6]~21 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_lo_as[6]~21_combout = ((\z80_|reg_file_|db_lo_as[6]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [6]) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout )
|
|
|
|
.dataa(\z80_|reg_file_|db_lo_as[0]~2_combout ),
|
|
.datab(\z80_|address_latch_|b2v_inst_inc_dec|address [6]),
|
|
.datac(\z80_|reg_file_|db_lo_as[6]~20_combout ),
|
|
.datad(\z80_|execute_|ctl_bus_inc_oe~43_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_lo_as[6]~21_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_lo_as[6]~21 .lut_mask = 16'hD5F5;
|
|
defparam \z80_|reg_file_|db_lo_as[6]~21 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y12_N26
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[6]~82 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[6]~82_combout = ((\z80_|reg_file_|gdfx_temp0[6]~81_combout & ((\z80_|reg_file_|db_lo_as[6]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_sw_4u~6_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp0[6]~81_combout ),
|
|
.datac(\z80_|reg_file_|gdfx_temp0[0]~21_combout ),
|
|
.datad(\z80_|reg_file_|db_lo_as[6]~21_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[6]~82_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[6]~82 .lut_mask = 16'hCF4F;
|
|
defparam \z80_|reg_file_|gdfx_temp0[6]~82 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y14_N10
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[6]~0 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_lo_ds[6]~0_combout = (\z80_|reg_file_|gdfx_temp0[6]~82_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~5_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout & \z80_|execute_|ctl_reg_out_lo~7_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_out_lo~5_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_out_lo~7_combout ),
|
|
.datad(\z80_|reg_file_|gdfx_temp0[6]~82_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_lo_ds[6]~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_lo_ds[6]~0 .lut_mask = 16'hFF40;
|
|
defparam \z80_|reg_file_|db_lo_ds[6]~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y14_N28
|
|
cycloneive_lcell_comb \z80_|sw1_|db_down[6]~1 (
|
|
// Equation(s):
|
|
// \z80_|sw1_|db_down[6]~1_combout = ((\z80_|bus_control_|db[6]~9_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|bus_control_|db[6]~9_combout ),
|
|
.datac(\z80_|execute_|ctl_sw_1d~7_combout ),
|
|
.datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|sw1_|db_down[6]~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|sw1_|db_down[6]~1 .lut_mask = 16'h0FCF;
|
|
defparam \z80_|sw1_|db_down[6]~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y14_N18
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_66_oe (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_66_oe~combout = (\z80_|pla_decode_|Equal47~0_combout & (!\z80_|sequencer_|DFFE_M1_ff~q & (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & \z80_|sequencer_|DFFE_T3_ff~q )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal47~0_combout ),
|
|
.datab(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ),
|
|
.datad(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_66_oe~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_66_oe .lut_mask = 16'h2000;
|
|
defparam \z80_|execute_|ctl_66_oe .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y17_N24
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[1] (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_op1_latch_mux_high|Q [1] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|db_high[1]~19_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ),
|
|
.datad(\z80_|alu_|db_high[1]~19_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .lut_mask = 16'h0A00;
|
|
defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[1] .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y17_N25
|
|
dffeas \z80_|alu_|op1_high[1] (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|alu_|b2v_op1_latch_mux_high|Q [1]),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|alu_|op1_high [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|op1_high[1] .is_wysiwyg = "true";
|
|
defparam \z80_|alu_|op1_high[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y18_N8
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4 (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4_combout = (\z80_|alu_|db_low[1]~12_combout & \z80_|execute_|ctl_alu_op2_sel_lq~combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|alu_|db_low[1]~12_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4 .lut_mask = 16'hC0C0;
|
|
defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y18_N16
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_high[1]~19_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ),
|
|
.datab(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~4_combout ),
|
|
.datac(\z80_|alu_|db_high[1]~19_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op2_sel_zero~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 .lut_mask = 16'h00EC;
|
|
defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y18_N17
|
|
dffeas \z80_|alu_|op2_high[1] (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|alu_|b2v_op2_latch_mux_high|Q[1]~5_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|alu_|op2_high [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|op2_high[1] .is_wysiwyg = "true";
|
|
defparam \z80_|alu_|op2_high[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y18_N18
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~2 (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~2_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [1]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [1]))))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op2_sel_lq~combout ),
|
|
.datab(\z80_|alu_|op1_high [1]),
|
|
.datac(\z80_|execute_|ctl_alu_op_low~combout ),
|
|
.datad(\z80_|alu_|op1_low [1]),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~2 .lut_mask = 16'hA808;
|
|
defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y18_N14
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~3 (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~3_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~2_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_low[1]~12_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ),
|
|
.datac(\z80_|alu_|db_low[1]~12_combout ),
|
|
.datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~3 .lut_mask = 16'h3320;
|
|
defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[1]~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y18_N15
|
|
dffeas \z80_|alu_|op2_low[1] (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|alu_|b2v_op2_latch_mux_low|Q[1]~3_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|alu_|op2_low [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|op2_low[1] .is_wysiwyg = "true";
|
|
defparam \z80_|alu_|op2_low[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y18_N16
|
|
cycloneive_lcell_comb \z80_|alu_|alu_op2[1]~1 (
|
|
// Equation(s):
|
|
// \z80_|alu_|alu_op2[1]~1_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [1])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [1])))))
|
|
|
|
.dataa(\z80_|alu_|op2_high [1]),
|
|
.datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ),
|
|
.datac(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ),
|
|
.datad(\z80_|alu_|op2_low [1]),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|alu_op2[1]~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|alu_op2[1]~1 .lut_mask = 16'h4B78;
|
|
defparam \z80_|alu_|alu_op2[1]~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y18_N0
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout = (!\z80_|alu_|alu_op2[1]~1_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high
|
|
// [1])))))
|
|
|
|
.dataa(\z80_|alu_|op1_low [1]),
|
|
.datab(\z80_|alu_|op1_high [1]),
|
|
.datac(\z80_|execute_|ctl_alu_op_low~combout ),
|
|
.datad(\z80_|alu_|alu_op2[1]~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'h0053;
|
|
defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y18_N30
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0 (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout = (\z80_|alu_|alu_op2[1]~1_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [1])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [1])))))
|
|
|
|
.dataa(\z80_|alu_|op1_low [1]),
|
|
.datab(\z80_|alu_|op1_high [1]),
|
|
.datac(\z80_|execute_|ctl_alu_op_low~combout ),
|
|
.datad(\z80_|alu_|alu_op2[1]~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0 .lut_mask = 16'hAC00;
|
|
defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y18_N14
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_alu_core_S~combout ),
|
|
.datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hFFF0;
|
|
defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y20_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~5 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_core_R~5_combout = (\z80_|execute_|ctl_alu_core_S~8_combout & (\z80_|execute_|ctl_alu_core_R~4_combout & (\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout & !\z80_|pla_decode_|Equal72~2_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_core_S~8_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_core_R~4_combout ),
|
|
.datac(\z80_|alu_flags_|DFFE_inst_latch_nf~4_combout ),
|
|
.datad(\z80_|pla_decode_|Equal72~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_core_R~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_core_R~5 .lut_mask = 16'h0080;
|
|
defparam \z80_|execute_|ctl_alu_core_R~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y14_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R~2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_core_R~2_combout = (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|nM1_int~2_combout & ((\z80_|pla_decode_|Equal8~0_combout ) # (\z80_|pla_decode_|Equal55~0_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_mWrite~4_combout ),
|
|
.datab(\z80_|pla_decode_|Equal8~0_combout ),
|
|
.datac(\z80_|nM1_int~2_combout ),
|
|
.datad(\z80_|pla_decode_|Equal55~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_core_R~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_core_R~2 .lut_mask = 16'hA080;
|
|
defparam \z80_|execute_|ctl_alu_core_R~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y20_N26
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_R (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_core_R~combout = (((\z80_|pla_decode_|Equal73~2_combout ) # (\z80_|execute_|ctl_alu_core_R~2_combout )) # (!\z80_|execute_|ctl_alu_core_S~9_combout )) # (!\z80_|execute_|ctl_alu_core_R~4_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_core_R~4_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_core_S~9_combout ),
|
|
.datac(\z80_|pla_decode_|Equal73~2_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_core_R~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_core_R~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_core_R .lut_mask = 16'hFFF7;
|
|
defparam \z80_|execute_|ctl_alu_core_R .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y17_N8
|
|
cycloneive_lcell_comb \z80_|alu_|db_high[0]~20 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_high[0]~20_combout = ((!\z80_|bus_control_|db[3]~21_combout & (\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[4]~19_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout )
|
|
|
|
.dataa(\z80_|bus_control_|db[3]~21_combout ),
|
|
.datab(\z80_|bus_control_|db[5]~15_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_bs_oe~combout ),
|
|
.datad(\z80_|bus_control_|db[4]~19_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_high[0]~20_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_high[0]~20 .lut_mask = 16'h0F4F;
|
|
defparam \z80_|alu_|db_high[0]~20 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y17_N26
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_high|Q[0] (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_op1_latch_mux_high|Q [0] = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|db_high[0]~25_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ),
|
|
.datad(\z80_|alu_|db_high[0]~25_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .lut_mask = 16'h0A00;
|
|
defparam \z80_|alu_|b2v_op1_latch_mux_high|Q[0] .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y17_N27
|
|
dffeas \z80_|alu_|op1_high[0] (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|alu_|b2v_op1_latch_mux_high|Q [0]),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|alu_|b2v_op1_latch_mux_high|ena~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|alu_|op1_high [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|op1_high[0] .is_wysiwyg = "true";
|
|
defparam \z80_|alu_|op1_high[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y18_N30
|
|
cycloneive_lcell_comb \z80_|alu_|db_high[0]~21 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_high[0]~21_combout = (\z80_|execute_|ctl_alu_op1_oe~1_combout & (\z80_|alu_|op1_high [0] & ((\z80_|alu_|op2_high [0]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout & (((\z80_|alu_|op2_high
|
|
// [0]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op1_oe~1_combout ),
|
|
.datab(\z80_|alu_|op1_high [0]),
|
|
.datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ),
|
|
.datad(\z80_|alu_|op2_high [0]),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_high[0]~21_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_high[0]~21 .lut_mask = 16'hDD0D;
|
|
defparam \z80_|alu_|db_high[0]~21 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y16_N2
|
|
cycloneive_lcell_comb \z80_|alu_|db_high[0]~22 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_high[0]~22_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_|db[5]~24_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[3]~20_combout ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|alu_|db[3]~20_combout ),
|
|
.datac(\z80_|alu_|db[5]~24_combout ),
|
|
.datad(\z80_|ir_|opcode [3]),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_high[0]~22_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_high[0]~22 .lut_mask = 16'hF0CC;
|
|
defparam \z80_|alu_|db_high[0]~22 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y16_N20
|
|
cycloneive_lcell_comb \z80_|alu_|db_high[0]~23 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_high[0]~23_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[0]~22_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[4]~18_combout ))
|
|
|
|
.dataa(\z80_|alu_|db[4]~18_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|alu_|db_high[0]~22_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_high[0]~23_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_high[0]~23 .lut_mask = 16'hEE22;
|
|
defparam \z80_|alu_|db_high[0]~23 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y16_N26
|
|
cycloneive_lcell_comb \z80_|alu_|db_high[0]~24 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_high[0]~24_combout = (\z80_|alu_|db_high[0]~20_combout & (\z80_|alu_|db_high[0]~21_combout & ((\z80_|alu_|db_high[0]~23_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout ))))
|
|
|
|
.dataa(\z80_|alu_|db_high[0]~20_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_shift_oe~43_combout ),
|
|
.datac(\z80_|alu_|db_high[0]~21_combout ),
|
|
.datad(\z80_|alu_|db_high[0]~23_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_high[0]~24_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_high[0]~24 .lut_mask = 16'hA020;
|
|
defparam \z80_|alu_|db_high[0]~24 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y17_N4
|
|
cycloneive_lcell_comb \z80_|alu_|db_low[0]~4 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_low[0]~4_combout = ((!\z80_|bus_control_|db[3]~21_combout & (!\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[4]~19_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout )
|
|
|
|
.dataa(\z80_|bus_control_|db[3]~21_combout ),
|
|
.datab(\z80_|bus_control_|db[5]~15_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_bs_oe~combout ),
|
|
.datad(\z80_|bus_control_|db[4]~19_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_low[0]~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_low[0]~4 .lut_mask = 16'h0F1F;
|
|
defparam \z80_|alu_|db_low[0]~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X31_Y18_N27
|
|
dffeas \z80_|alu_|result_lo[0] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|execute_|ctl_alu_op_low~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|alu_|result_lo [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|result_lo[0] .is_wysiwyg = "true";
|
|
defparam \z80_|alu_|result_lo[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y17_N20
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~2 (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~2_combout = (\z80_|alu_|db_low[0]~24_combout & ((\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ) # ((\z80_|alu_|db_high[0]~25_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) #
|
|
// (!\z80_|alu_|db_low[0]~24_combout & (\z80_|alu_|db_high[0]~25_combout & ((\z80_|execute_|ctl_alu_op1_sel_low~combout ))))
|
|
|
|
.dataa(\z80_|alu_|db_low[0]~24_combout ),
|
|
.datab(\z80_|alu_|db_high[0]~25_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~2 .lut_mask = 16'hECA0;
|
|
defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y17_N0
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~3 (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~3_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~2_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ),
|
|
.datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~3 .lut_mask = 16'h0F00;
|
|
defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[0]~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y17_N1
|
|
dffeas \z80_|alu_|op1_low[0] (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|alu_|b2v_op1_latch_mux_low|Q[0]~3_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|alu_|op1_low [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|op1_low[0] .is_wysiwyg = "true";
|
|
defparam \z80_|alu_|op1_low[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y18_N24
|
|
cycloneive_lcell_comb \z80_|alu_|db_low[0]~5 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_low[0]~5_combout = (\z80_|execute_|ctl_alu_op1_oe~1_combout & (\z80_|alu_|op1_low [0] & ((\z80_|alu_|op2_low [0]) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout )))) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout & (((\z80_|alu_|op2_low [0]) #
|
|
// (!\z80_|execute_|ctl_alu_op2_oe~0_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op1_oe~1_combout ),
|
|
.datab(\z80_|alu_|op1_low [0]),
|
|
.datac(\z80_|execute_|ctl_alu_op2_oe~0_combout ),
|
|
.datad(\z80_|alu_|op2_low [0]),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_low[0]~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_low[0]~5 .lut_mask = 16'hDD0D;
|
|
defparam \z80_|alu_|db_low[0]~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y18_N26
|
|
cycloneive_lcell_comb \z80_|alu_|db_low[0]~6 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_low[0]~6_combout = (\z80_|alu_|db_low[0]~4_combout & (\z80_|alu_|db_low[0]~5_combout & ((\z80_|execute_|ctl_alu_res_oe~3_combout ) # (\z80_|alu_|result_lo [0]))))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_res_oe~3_combout ),
|
|
.datab(\z80_|alu_|db_low[0]~4_combout ),
|
|
.datac(\z80_|alu_|result_lo [0]),
|
|
.datad(\z80_|alu_|db_low[0]~5_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_low[0]~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_low[0]~6 .lut_mask = 16'hC800;
|
|
defparam \z80_|alu_|db_low[0]~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y16_N30
|
|
cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~1 (
|
|
// Equation(s):
|
|
// \z80_|alu_control_|b2v_inst_shift_mux|out~1_combout = (\z80_|ir_|opcode [5] & (\z80_|alu_|db[7]~12_combout & (\z80_|ir_|opcode [3]))) # (!\z80_|ir_|opcode [5] & ((\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~14_combout ))) # (!\z80_|ir_|opcode [3] &
|
|
// (\z80_|alu_|db[7]~12_combout ))))
|
|
|
|
.dataa(\z80_|alu_|db[7]~12_combout ),
|
|
.datab(\z80_|ir_|opcode [5]),
|
|
.datac(\z80_|ir_|opcode [3]),
|
|
.datad(\z80_|alu_|db[0]~14_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .lut_mask = 16'hB282;
|
|
defparam \z80_|alu_control_|b2v_inst_shift_mux|out~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y18_N24
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_hf_we~2_combout = (\z80_|execute_|ctl_flags_hf_we~5_combout & (\z80_|execute_|ctl_flags_xy_we~13_combout & ((!\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (!\z80_|execute_|ctl_state_alu~6_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_state_alu~6_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_hf_we~5_combout ),
|
|
.datac(\z80_|execute_|ctl_flags_xy_we~13_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_shift_oe~14_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_hf_we~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_hf_we~2 .lut_mask = 16'h40C0;
|
|
defparam \z80_|execute_|ctl_flags_hf_we~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y18_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~3 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_cf_we~3_combout = (\z80_|execute_|ctl_flags_hf2_we~combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & ((!\z80_|execute_|ctl_flags_bus~1_combout ) # (!\z80_|execute_|ctl_flags_bus~0_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_bus~0_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ),
|
|
.datac(\z80_|execute_|ctl_flags_hf2_we~combout ),
|
|
.datad(\z80_|execute_|ctl_flags_bus~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_cf_we~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_cf_we~3 .lut_mask = 16'hF4FC;
|
|
defparam \z80_|execute_|ctl_flags_cf_we~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y18_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_cf_we~4_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ) # ((\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ixy_d~6_combout & \z80_|execute_|ctl_mRead~34_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ),
|
|
.datab(\z80_|execute_|ixy_d~6_combout ),
|
|
.datac(\z80_|execute_|ctl_mRead~34_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_cf_we~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_cf_we~4 .lut_mask = 16'hFFEA;
|
|
defparam \z80_|execute_|ctl_flags_cf_we~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y18_N18
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~5 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_cf_we~5_combout = ((\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # (\z80_|execute_|ctl_flags_cf_we~4_combout ))) # (!\z80_|execute_|ctl_flags_cf_we~7_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_cf_we~7_combout ),
|
|
.datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ),
|
|
.datad(\z80_|execute_|ctl_flags_cf_we~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_cf_we~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_cf_we~5 .lut_mask = 16'hFFFD;
|
|
defparam \z80_|execute_|ctl_flags_cf_we~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y18_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_we~6 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_cf_we~6_combout = (((\z80_|execute_|ctl_flags_cf_we~3_combout ) # (\z80_|execute_|ctl_flags_cf_we~5_combout )) # (!\z80_|execute_|ctl_flags_hf_we~2_combout )) # (!\z80_|execute_|ctl_flags_cf_we~2_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_cf_we~2_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_hf_we~2_combout ),
|
|
.datac(\z80_|execute_|ctl_flags_cf_we~3_combout ),
|
|
.datad(\z80_|execute_|ctl_flags_cf_we~5_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_cf_we~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_cf_we~6 .lut_mask = 16'hFFF7;
|
|
defparam \z80_|execute_|ctl_flags_cf_we~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y18_N16
|
|
cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~0 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|DFFE_inst_latch_cf~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[0]~12_combout )))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout
|
|
// & ((\z80_|execute_|ctl_flags_alu~15_combout ) # ((\z80_|execute_|ctl_flags_bus~combout & \z80_|alu_control_|db[0]~12_combout ))))
|
|
|
|
.dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_bus~combout ),
|
|
.datac(\z80_|execute_|ctl_flags_alu~15_combout ),
|
|
.datad(\z80_|alu_control_|db[0]~12_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .lut_mask = 16'hDC50;
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_cf~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y18_N18
|
|
cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~1 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|DFFE_inst_latch_cf~1_combout = (\z80_|execute_|ctl_flags_cf_we~6_combout & ((\z80_|execute_|ctl_flags_cf2_we~3_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ))) # (!\z80_|execute_|ctl_flags_cf2_we~3_combout &
|
|
// (\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout )))) # (!\z80_|execute_|ctl_flags_cf_we~6_combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf~q ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_cf_we~6_combout ),
|
|
.datab(\z80_|alu_flags_|DFFE_inst_latch_cf~0_combout ),
|
|
.datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ),
|
|
.datad(\z80_|execute_|ctl_flags_cf2_we~3_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .lut_mask = 16'hF0D8;
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_cf~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X29_Y18_N19
|
|
dffeas \z80_|alu_flags_|DFFE_inst_latch_cf (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|alu_flags_|DFFE_inst_latch_cf~1_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|alu_flags_|DFFE_inst_latch_cf~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_cf .is_wysiwyg = "true";
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_cf .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y16_N4
|
|
cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~0 (
|
|
// Equation(s):
|
|
// \z80_|alu_control_|b2v_inst_shift_mux|out~0_combout = (\z80_|ir_|opcode [4] & ((\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3]))) # (!\z80_|ir_|opcode [5] & (\z80_|alu_flags_|DFFE_inst_latch_cf~q ))))
|
|
|
|
.dataa(\z80_|ir_|opcode [4]),
|
|
.datab(\z80_|ir_|opcode [5]),
|
|
.datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ),
|
|
.datad(\z80_|ir_|opcode [3]),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .lut_mask = 16'h20A8;
|
|
defparam \z80_|alu_control_|b2v_inst_shift_mux|out~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y16_N8
|
|
cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_shift_mux|out~2 (
|
|
// Equation(s):
|
|
// \z80_|alu_control_|b2v_inst_shift_mux|out~2_combout = (\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ) # ((\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout & !\z80_|ir_|opcode [4]))
|
|
|
|
.dataa(\z80_|alu_control_|b2v_inst_shift_mux|out~1_combout ),
|
|
.datab(\z80_|alu_control_|b2v_inst_shift_mux|out~0_combout ),
|
|
.datac(\z80_|ir_|opcode [4]),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .lut_mask = 16'hCECE;
|
|
defparam \z80_|alu_control_|b2v_inst_shift_mux|out~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y16_N14
|
|
cycloneive_lcell_comb \z80_|alu_|db_low[0]~2 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_low[0]~2_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[1]~10_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout )))
|
|
|
|
.dataa(\z80_|alu_|db[1]~10_combout ),
|
|
.datab(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|ir_|opcode [3]),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_low[0]~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_low[0]~2 .lut_mask = 16'hAACC;
|
|
defparam \z80_|alu_|db_low[0]~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y16_N20
|
|
cycloneive_lcell_comb \z80_|alu_|db_low[0]~3 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_low[0]~3_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_low[0]~2_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[0]~14_combout )))) #
|
|
// (!\z80_|execute_|ctl_alu_shift_oe~43_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_shift_oe~43_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ),
|
|
.datac(\z80_|alu_|db_low[0]~2_combout ),
|
|
.datad(\z80_|alu_|db[0]~14_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_low[0]~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_low[0]~3 .lut_mask = 16'hF7D5;
|
|
defparam \z80_|alu_|db_low[0]~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y16_N16
|
|
cycloneive_lcell_comb \z80_|alu_|db_low[0]~24 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_low[0]~24_combout = (\z80_|alu_|db_low[0]~6_combout & ((\z80_|alu_|db_low[0]~3_combout ) # ((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~0_combout )))) # (!\z80_|alu_|db_low[0]~6_combout &
|
|
// (((!\z80_|execute_|ctl_alu_shift_oe~43_combout & !\z80_|alu_|db_high[3]~0_combout ))))
|
|
|
|
.dataa(\z80_|alu_|db_low[0]~6_combout ),
|
|
.datab(\z80_|alu_|db_low[0]~3_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ),
|
|
.datad(\z80_|alu_|db_high[3]~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_low[0]~24_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_low[0]~24 .lut_mask = 16'h888F;
|
|
defparam \z80_|alu_|db_low[0]~24 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y18_N2
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~0 (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [0]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [0]))))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op_low~combout ),
|
|
.datab(\z80_|alu_|op1_high [0]),
|
|
.datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ),
|
|
.datad(\z80_|alu_|op1_low [0]),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~0 .lut_mask = 16'hE040;
|
|
defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y18_N4
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~1 (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~0_combout ) # ((\z80_|alu_|db_low[0]~24_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout ))))
|
|
|
|
.dataa(\z80_|alu_|db_low[0]~24_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ),
|
|
.datac(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ),
|
|
.datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~1 .lut_mask = 16'h3320;
|
|
defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[0]~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y18_N5
|
|
dffeas \z80_|alu_|op2_low[0] (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|alu_|b2v_op2_latch_mux_low|Q[0]~1_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|alu_|op2_low [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|op2_low[0] .is_wysiwyg = "true";
|
|
defparam \z80_|alu_|op2_low[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y18_N6
|
|
cycloneive_lcell_comb \z80_|alu_|alu_op2[0]~3 (
|
|
// Equation(s):
|
|
// \z80_|alu_|alu_op2[0]~3_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [0])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [0])))))
|
|
|
|
.dataa(\z80_|alu_|op2_high [0]),
|
|
.datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ),
|
|
.datac(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ),
|
|
.datad(\z80_|alu_|op2_low [0]),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|alu_op2[0]~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|alu_op2[0]~3 .lut_mask = 16'h4B78;
|
|
defparam \z80_|alu_|alu_op2[0]~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y18_N0
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout = ((!\z80_|execute_|ctl_alu_core_S~combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout )) # (!\z80_|execute_|ctl_alu_core_R~5_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_core_S~combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_alu_core_R~5_combout ),
|
|
.datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .lut_mask = 16'h0F5F;
|
|
defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y16_N2
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla26M3T5_8 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_hilo_pla26M3T5_8~combout = (\z80_|sequencer_|DFFE_T5_ff~q & (\z80_|pla_decode_|Equal21~1_combout & \z80_|sequencer_|DFFE_M3_ff~q ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|sequencer_|DFFE_T5_ff~q ),
|
|
.datac(\z80_|pla_decode_|Equal21~1_combout ),
|
|
.datad(\z80_|sequencer_|DFFE_M3_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_hilo_pla26M3T5_8~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo_pla26M3T5_8 .lut_mask = 16'hC000;
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo_pla26M3T5_8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y16_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~14 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_core_hf~14_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla26M3T5_8~combout ) # ((\z80_|sequencer_|DFFE_T3_ff~q & (!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|ixy_d~15_combout )))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.datab(\z80_|execute_|ctl_reg_sys_hilo_pla26M3T5_8~combout ),
|
|
.datac(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.datad(\z80_|execute_|ixy_d~15_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_core_hf~14_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_core_hf~14 .lut_mask = 16'hCECC;
|
|
defparam \z80_|execute_|ctl_alu_core_hf~14 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y16_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~16 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_core_hf~16_combout = ((\z80_|execute_|ctl_alu_core_hf~14_combout ) # (!\z80_|execute_|ctl_alu_core_hf~15_combout )) # (!\z80_|execute_|ctl_alu_core_hf~12_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_core_hf~12_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_alu_core_hf~15_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_core_hf~14_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_core_hf~16_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_core_hf~16 .lut_mask = 16'hFF5F;
|
|
defparam \z80_|execute_|ctl_alu_core_hf~16 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y17_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~13 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_core_hf~13_combout = (\z80_|pla_decode_|Equal21~1_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((!\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ixy_d~6_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ixy_d~5_combout ),
|
|
.datab(\z80_|pla_decode_|Equal21~1_combout ),
|
|
.datac(\z80_|execute_|ixy_d~6_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~9_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_core_hf~13_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_core_hf~13 .lut_mask = 16'hCC40;
|
|
defparam \z80_|execute_|ctl_alu_core_hf~13 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y16_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~17 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_core_hf~17_combout = (\z80_|execute_|ctl_alu_core_hf~16_combout & (((\z80_|execute_|ctl_alu_core_hf~13_combout & !\z80_|execute_|ctl_alu_op_low~40_combout )) # (!\z80_|execute_|ctl_alu_op_low~41_combout ))) #
|
|
// (!\z80_|execute_|ctl_alu_core_hf~16_combout & (\z80_|execute_|ctl_alu_core_hf~13_combout & ((!\z80_|execute_|ctl_alu_op_low~40_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_core_hf~16_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_core_hf~13_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_op_low~41_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op_low~40_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_core_hf~17_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_core_hf~17 .lut_mask = 16'h0ACE;
|
|
defparam \z80_|execute_|ctl_alu_core_hf~17 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y20_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~44 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op_low~44_combout = (\z80_|execute_|ctl_alu_op_low~38_combout ) # ((\z80_|execute_|ctl_alu_op_low~42_combout ) # ((\z80_|execute_|ctl_alu_op_low~36_combout ) # (!\z80_|execute_|ctl_alu_op_low~31_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op_low~38_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_op_low~42_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_op_low~31_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op_low~36_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op_low~44_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op_low~44 .lut_mask = 16'hFFEF;
|
|
defparam \z80_|execute_|ctl_alu_op_low~44 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y17_N28
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~20 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_core_hf~20_combout = (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # ((!\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ixy_d~6_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ixy_d~5_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~34_combout ),
|
|
.datac(\z80_|execute_|ixy_d~6_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~9_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_core_hf~20_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_core_hf~20 .lut_mask = 16'hCC40;
|
|
defparam \z80_|execute_|ctl_alu_core_hf~20 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y17_N18
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~21 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_core_hf~21_combout = (\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ) # ((\z80_|execute_|ctl_alu_core_hf~20_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_mRead~34_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_hilo_pla91pla21M2T3_4~combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~34_combout ),
|
|
.datac(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_core_hf~20_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_core_hf~21_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_core_hf~21 .lut_mask = 16'hBFAA;
|
|
defparam \z80_|execute_|ctl_alu_core_hf~21 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y18_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~18 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_core_hf~18_combout = (\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & (((!\z80_|pla_decode_|Equal32~0_combout ) # (!\z80_|execute_|ctl_eval_cond~0_combout )) # (!\z80_|pla_decode_|Equal63~0_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal63~0_combout ),
|
|
.datab(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ),
|
|
.datac(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.datad(\z80_|pla_decode_|Equal32~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_core_hf~18_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_core_hf~18 .lut_mask = 16'h4CCC;
|
|
defparam \z80_|execute_|ctl_alu_core_hf~18 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y18_N16
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~19 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_core_hf~19_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ) # ((\z80_|execute_|ctl_alu_core_hf~18_combout & !\z80_|execute_|ctl_flags_cf2_sel_daa~combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ),
|
|
.datac(\z80_|execute_|ctl_alu_core_hf~18_combout ),
|
|
.datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_core_hf~19_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_core_hf~19 .lut_mask = 16'hEEFE;
|
|
defparam \z80_|execute_|ctl_alu_core_hf~19 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y20_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~22 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_core_hf~22_combout = (\z80_|execute_|ctl_alu_op_low~37_combout & (!\z80_|execute_|ctl_alu_op_low~42_combout & ((\z80_|execute_|ctl_alu_core_hf~19_combout )))) # (!\z80_|execute_|ctl_alu_op_low~37_combout &
|
|
// ((\z80_|execute_|ctl_alu_core_hf~21_combout ) # ((!\z80_|execute_|ctl_alu_op_low~42_combout & \z80_|execute_|ctl_alu_core_hf~19_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op_low~37_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_op_low~42_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_core_hf~21_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_core_hf~19_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_core_hf~22_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_core_hf~22 .lut_mask = 16'h7350;
|
|
defparam \z80_|execute_|ctl_alu_core_hf~22 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y18_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~43 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op_low~43_combout = ((\z80_|execute_|ctl_alu_op_low~28_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ) # (!\z80_|execute_|ctl_state_alu~12_combout ))) # (!\z80_|execute_|ctl_alu_op2_sel_bus~9_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op2_sel_bus~9_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_op_low~28_combout ),
|
|
.datac(\z80_|execute_|ctl_state_alu~12_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_hilo_pla65npla52M1T4_4~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op_low~43_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op_low~43 .lut_mask = 16'hFFDF;
|
|
defparam \z80_|execute_|ctl_alu_op_low~43 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y20_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~24 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_core_hf~24_combout = (\z80_|execute_|ctl_state_alu~2_combout & (\z80_|pla_decode_|Equal11~0_combout )) # (!\z80_|execute_|ctl_state_alu~2_combout & (\z80_|execute_|ixy_d~7_combout & ((\z80_|pla_decode_|Equal11~0_combout ) #
|
|
// (\z80_|pla_decode_|Equal10~0_combout ))))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal11~0_combout ),
|
|
.datab(\z80_|execute_|ixy_d~7_combout ),
|
|
.datac(\z80_|pla_decode_|Equal10~0_combout ),
|
|
.datad(\z80_|execute_|ctl_state_alu~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_core_hf~24_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_core_hf~24 .lut_mask = 16'hAAC8;
|
|
defparam \z80_|execute_|ctl_alu_core_hf~24 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y20_N2
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~25 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_core_hf~25_combout = (!\z80_|execute_|ctl_alu_op_low~28_combout & (!\z80_|execute_|ctl_mWrite~18_combout & ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # (\z80_|execute_|ctl_alu_core_hf~24_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op_low~28_combout ),
|
|
.datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ),
|
|
.datac(\z80_|execute_|ctl_mWrite~18_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_core_hf~24_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_core_hf~25_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_core_hf~25 .lut_mask = 16'h0504;
|
|
defparam \z80_|execute_|ctl_alu_core_hf~25 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y19_N18
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~35 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_core_hf~35_combout = (\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & \z80_|execute_|ctl_alu_op_low~25_combout )))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datab(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.datac(\z80_|sequencer_|DFFE_M2_ff~q ),
|
|
.datad(\z80_|execute_|ctl_alu_op_low~25_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_core_hf~35_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_core_hf~35 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|ctl_alu_core_hf~35 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y20_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~23 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_core_hf~23_combout = (!\z80_|execute_|ctl_alu_op_low~34_combout & ((\z80_|execute_|ctl_alu_core_hf~35_combout ) # ((\z80_|execute_|ixy_d~7_combout & \z80_|execute_|ctl_alu_op_low~24_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op_low~34_combout ),
|
|
.datab(\z80_|execute_|ixy_d~7_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_core_hf~35_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op_low~24_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_core_hf~23_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_core_hf~23 .lut_mask = 16'h5450;
|
|
defparam \z80_|execute_|ctl_alu_core_hf~23 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y18_N26
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~26 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_core_hf~26_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (((\z80_|decode_state_|use_ixiy~combout ) # (!\z80_|execute_|ctl_state_alu~2_combout )) # (!\z80_|pla_decode_|Equal45~0_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal45~0_combout ),
|
|
.datab(\z80_|decode_state_|use_ixiy~combout ),
|
|
.datac(\z80_|execute_|ctl_state_alu~2_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_shift_oe~15_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_core_hf~26_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_core_hf~26 .lut_mask = 16'h00DF;
|
|
defparam \z80_|execute_|ctl_alu_core_hf~26 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y18_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~34 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_core_hf~34_combout = (\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|execute_|ctl_mRead~4_combout & ((\z80_|execute_|ctl_state_alu~4_combout )))) # (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M2_ff~q ) #
|
|
// ((\z80_|execute_|ctl_mRead~4_combout & \z80_|execute_|ctl_state_alu~4_combout ))))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datab(\z80_|execute_|ctl_mRead~4_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_M2_ff~q ),
|
|
.datad(\z80_|execute_|ctl_state_alu~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_core_hf~34_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_core_hf~34 .lut_mask = 16'hDC50;
|
|
defparam \z80_|execute_|ctl_alu_core_hf~34 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y18_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~27 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_core_hf~27_combout = (\z80_|execute_|ctl_alu_op_low~22_combout & (((\z80_|execute_|ctl_alu_op_low~24_combout )))) # (!\z80_|execute_|ctl_alu_op_low~22_combout & (\z80_|execute_|ixy_d~7_combout &
|
|
// (!\z80_|execute_|ctl_mWrite~5_combout )))
|
|
|
|
.dataa(\z80_|execute_|ixy_d~7_combout ),
|
|
.datab(\z80_|execute_|ctl_mWrite~5_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_op_low~24_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op_low~22_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_core_hf~27_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_core_hf~27 .lut_mask = 16'hF022;
|
|
defparam \z80_|execute_|ctl_alu_core_hf~27 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y18_N2
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~28 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_core_hf~28_combout = (!\z80_|execute_|ctl_alu_core_hf~34_combout & ((\z80_|pla_decode_|Equal56~0_combout & ((\z80_|execute_|ctl_alu_core_hf~27_combout ) # (\z80_|execute_|ctl_alu_op_low~22_combout ))) #
|
|
// (!\z80_|pla_decode_|Equal56~0_combout & (\z80_|execute_|ctl_alu_core_hf~27_combout & \z80_|execute_|ctl_alu_op_low~22_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_core_hf~34_combout ),
|
|
.datab(\z80_|pla_decode_|Equal56~0_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_core_hf~27_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op_low~22_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_core_hf~28_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_core_hf~28 .lut_mask = 16'h5440;
|
|
defparam \z80_|execute_|ctl_alu_core_hf~28 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y18_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~29 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_core_hf~29_combout = (\z80_|execute_|ctl_mRead~4_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # ((!\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|ctl_mWrite~9_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_state_alu~4_combout ),
|
|
.datab(\z80_|execute_|ctl_mWrite~9_combout ),
|
|
.datac(\z80_|execute_|ctl_mRead~4_combout ),
|
|
.datad(\z80_|execute_|ctl_mWrite~5_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_core_hf~29_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_core_hf~29 .lut_mask = 16'hF040;
|
|
defparam \z80_|execute_|ctl_alu_core_hf~29 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y18_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~30 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_core_hf~30_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ctl_alu_core_hf~26_combout & ((\z80_|execute_|ctl_alu_core_hf~28_combout ) # (\z80_|execute_|ctl_alu_core_hf~29_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_core_hf~26_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_core_hf~28_combout ),
|
|
.datac(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ),
|
|
.datad(\z80_|execute_|ctl_alu_core_hf~29_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_core_hf~30_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_core_hf~30 .lut_mask = 16'hFAF8;
|
|
defparam \z80_|execute_|ctl_alu_core_hf~30 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y20_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~31 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_core_hf~31_combout = (\z80_|execute_|ctl_alu_core_hf~25_combout ) # ((\z80_|execute_|ctl_alu_core_hf~23_combout ) # ((!\z80_|execute_|ctl_alu_op_low~43_combout & \z80_|execute_|ctl_alu_core_hf~30_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op_low~43_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_core_hf~25_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_core_hf~23_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_core_hf~30_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_core_hf~31_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_core_hf~31 .lut_mask = 16'hFDFC;
|
|
defparam \z80_|execute_|ctl_alu_core_hf~31 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y18_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~36 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_core_hf~36_combout = (\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ixy_d~9_combout ))
|
|
|
|
.dataa(\z80_|execute_|ixy_d~8_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ixy_d~6_combout ),
|
|
.datad(\z80_|execute_|ixy_d~9_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_core_hf~36_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_core_hf~36 .lut_mask = 16'hF0FA;
|
|
defparam \z80_|execute_|ctl_alu_core_hf~36 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y18_N2
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~37 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_core_hf~37_combout = (\z80_|execute_|ctl_alu_core_hf~36_combout & ((\z80_|pla_decode_|Equal39~0_combout ) # ((!\z80_|execute_|ixy_d~5_combout & \z80_|pla_decode_|Equal40~1_combout ))))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal39~0_combout ),
|
|
.datab(\z80_|execute_|ixy_d~5_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_core_hf~36_combout ),
|
|
.datad(\z80_|pla_decode_|Equal40~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_core_hf~37_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_core_hf~37 .lut_mask = 16'hB0A0;
|
|
defparam \z80_|execute_|ctl_alu_core_hf~37 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y20_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~32 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_core_hf~32_combout = (\z80_|execute_|ctl_alu_core_hf~22_combout ) # ((\z80_|execute_|ctl_alu_core_hf~31_combout ) # ((!\z80_|execute_|ctl_alu_op_low~44_combout & \z80_|execute_|ctl_alu_core_hf~37_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op_low~44_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_core_hf~22_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_core_hf~31_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_core_hf~37_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_core_hf~32_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_core_hf~32 .lut_mask = 16'hFDFC;
|
|
defparam \z80_|execute_|ctl_alu_core_hf~32 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y16_N18
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_core_hf~33 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_core_hf~33_combout = (\z80_|execute_|ctl_alu_core_hf~17_combout ) # ((\z80_|execute_|ctl_alu_core_hf~32_combout ) # ((!\z80_|execute_|ctl_alu_op_low~combout & \z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op_low~combout ),
|
|
.datab(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ),
|
|
.datac(\z80_|execute_|ctl_alu_core_hf~17_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_core_hf~32_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_core_hf~33_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_core_hf~33 .lut_mask = 16'hFFF4;
|
|
defparam \z80_|execute_|ctl_alu_core_hf~33 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y14_N22
|
|
cycloneive_lcell_comb \z80_|alu_control_|alu_core_cf_in~0 (
|
|
// Equation(s):
|
|
// \z80_|alu_control_|alu_core_cf_in~0_combout = (\z80_|execute_|ctl_alu_core_hf~33_combout & (\z80_|alu_flags_|flags_hf~combout )) # (!\z80_|execute_|ctl_alu_core_hf~33_combout & ((\z80_|alu_flags_|flags_cf~combout )))
|
|
|
|
.dataa(\z80_|alu_flags_|flags_hf~combout ),
|
|
.datab(\z80_|alu_flags_|flags_cf~combout ),
|
|
.datac(\z80_|execute_|ctl_alu_core_hf~33_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_control_|alu_core_cf_in~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_control_|alu_core_cf_in~0 .lut_mask = 16'hACAC;
|
|
defparam \z80_|alu_control_|alu_core_cf_in~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y18_N12
|
|
cycloneive_lcell_comb \z80_|alu_|alu_op1[0]~0 (
|
|
// Equation(s):
|
|
// \z80_|alu_|alu_op1[0]~0_combout = (\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [0]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [0]))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op_low~combout ),
|
|
.datab(\z80_|alu_|op1_high [0]),
|
|
.datac(gnd),
|
|
.datad(\z80_|alu_|op1_low [0]),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|alu_op1[0]~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|alu_op1[0]~0 .lut_mask = 16'hEE44;
|
|
defparam \z80_|alu_|alu_op1[0]~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y18_N8
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout = (\z80_|alu_|alu_op2[0]~3_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_control_|alu_core_cf_in~0_combout & \z80_|alu_|alu_op1[0]~0_combout ))))
|
|
// # (!\z80_|alu_|alu_op2[0]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_control_|alu_core_cf_in~0_combout ) # (\z80_|alu_|alu_op1[0]~0_combout ))))
|
|
|
|
.dataa(\z80_|alu_|alu_op2[0]~3_combout ),
|
|
.datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_1~combout ),
|
|
.datac(\z80_|alu_control_|alu_core_cf_in~0_combout ),
|
|
.datad(\z80_|alu_|alu_op1[0]~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .lut_mask = 16'hECC8;
|
|
defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y16_N30
|
|
cycloneive_lcell_comb \z80_|alu_|db_high[0]~25 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_high[0]~25_combout = ((\z80_|alu_|db_high[0]~24_combout & ((\z80_|execute_|ctl_alu_res_oe~3_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout )
|
|
|
|
.dataa(\z80_|alu_|db_high[0]~24_combout ),
|
|
.datab(\z80_|alu_|db_high[3]~1_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_res_oe~3_combout ),
|
|
.datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_high[0]~25_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_high[0]~25 .lut_mask = 16'hBBB3;
|
|
defparam \z80_|alu_|db_high[0]~25 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y18_N26
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6 (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|alu_|db_low[0]~24_combout ) # ((\z80_|alu_|db_high[0]~25_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))) #
|
|
// (!\z80_|execute_|ctl_alu_op2_sel_lq~combout & (\z80_|alu_|db_high[0]~25_combout & (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op2_sel_lq~combout ),
|
|
.datab(\z80_|alu_|db_high[0]~25_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ),
|
|
.datad(\z80_|alu_|db_low[0]~24_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6 .lut_mask = 16'hEAC0;
|
|
defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y18_N2
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ),
|
|
.datac(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~6_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 .lut_mask = 16'h3030;
|
|
defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y18_N3
|
|
dffeas \z80_|alu_|op2_high[0] (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|alu_|b2v_op2_latch_mux_high|Q[0]~7_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|alu_|op2_high [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|op2_high[0] .is_wysiwyg = "true";
|
|
defparam \z80_|alu_|op2_high[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y18_N18
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout = (\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_high [0])) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_low [0])))
|
|
|
|
.dataa(\z80_|alu_|op2_high [0]),
|
|
.datab(\z80_|execute_|ctl_alu_sel_op2_high~combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|alu_|op2_low [0]),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'hBB88;
|
|
defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y18_N16
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout = (\z80_|alu_control_|alu_core_cf_in~0_combout & ((\z80_|alu_|alu_op1[0]~0_combout ) # (\z80_|execute_|ctl_alu_sel_op2_neg~15_combout $
|
|
// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout )))) # (!\z80_|alu_control_|alu_core_cf_in~0_combout & (\z80_|alu_|alu_op1[0]~0_combout & (\z80_|execute_|ctl_alu_sel_op2_neg~15_combout $
|
|
// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ),
|
|
.datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~0_combout ),
|
|
.datac(\z80_|alu_control_|alu_core_cf_in~0_combout ),
|
|
.datad(\z80_|alu_|alu_op1[0]~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hF660;
|
|
defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y18_N10
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|execute_|ctl_alu_core_S~combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|execute_|ctl_alu_core_R~combout ),
|
|
.datac(\z80_|execute_|ctl_alu_core_S~combout ),
|
|
.datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|SYNTHESIZED_WIRE_10~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .lut_mask = 16'hCCCF;
|
|
defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y18_N22
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ) #
|
|
// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout )
|
|
|
|
.dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ),
|
|
.datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_core_R~5_combout ),
|
|
.datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .lut_mask = 16'h3F2F;
|
|
defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y18_N28
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout & (((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout )) #
|
|
// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout & (((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout &
|
|
// !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ))))
|
|
|
|
.dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ),
|
|
.datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_8~0_combout ),
|
|
.datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_1~combout ),
|
|
.datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .lut_mask = 16'h50FC;
|
|
defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y17_N6
|
|
cycloneive_lcell_comb \z80_|alu_|db_high[1]~14 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_high[1]~14_combout = ((\z80_|bus_control_|db[3]~21_combout & (\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[4]~19_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout )
|
|
|
|
.dataa(\z80_|bus_control_|db[3]~21_combout ),
|
|
.datab(\z80_|bus_control_|db[5]~15_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_bs_oe~combout ),
|
|
.datad(\z80_|bus_control_|db[4]~19_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_high[1]~14_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_high[1]~14 .lut_mask = 16'h0F8F;
|
|
defparam \z80_|alu_|db_high[1]~14 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y18_N18
|
|
cycloneive_lcell_comb \z80_|alu_|db_high[1]~15 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_high[1]~15_combout = (\z80_|execute_|ctl_alu_op2_oe~0_combout & (\z80_|alu_|op2_high [1] & ((\z80_|alu_|op1_high [1]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_high
|
|
// [1]) # ((!\z80_|execute_|ctl_alu_op1_oe~1_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op2_oe~0_combout ),
|
|
.datab(\z80_|alu_|op1_high [1]),
|
|
.datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ),
|
|
.datad(\z80_|alu_|op2_high [1]),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_high[1]~15_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_high[1]~15 .lut_mask = 16'hCF45;
|
|
defparam \z80_|alu_|db_high[1]~15 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y15_N18
|
|
cycloneive_lcell_comb \z80_|alu_|db_high[1]~16 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_high[1]~16_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~22_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[4]~18_combout )))
|
|
|
|
.dataa(\z80_|alu_|db[6]~22_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|ir_|opcode [3]),
|
|
.datad(\z80_|alu_|db[4]~18_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_high[1]~16_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_high[1]~16 .lut_mask = 16'hAFA0;
|
|
defparam \z80_|alu_|db_high[1]~16 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y13_N12
|
|
cycloneive_lcell_comb \z80_|alu_|db_high[1]~17 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_high[1]~17_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[1]~16_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[5]~24_combout ))
|
|
|
|
.dataa(\z80_|alu_|db[5]~24_combout ),
|
|
.datab(\z80_|alu_|db_high[1]~16_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_high[1]~17_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_high[1]~17 .lut_mask = 16'hCCAA;
|
|
defparam \z80_|alu_|db_high[1]~17 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y16_N6
|
|
cycloneive_lcell_comb \z80_|alu_|db_high[1]~18 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_high[1]~18_combout = (\z80_|alu_|db_high[1]~14_combout & (\z80_|alu_|db_high[1]~15_combout & ((\z80_|alu_|db_high[1]~17_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout ))))
|
|
|
|
.dataa(\z80_|alu_|db_high[1]~14_combout ),
|
|
.datab(\z80_|alu_|db_high[1]~15_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ),
|
|
.datad(\z80_|alu_|db_high[1]~17_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_high[1]~18_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_high[1]~18 .lut_mask = 16'h8808;
|
|
defparam \z80_|alu_|db_high[1]~18 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y16_N8
|
|
cycloneive_lcell_comb \z80_|alu_|db_high[1]~19 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_high[1]~19_combout = ((\z80_|alu_|db_high[1]~18_combout & ((\z80_|execute_|ctl_alu_res_oe~3_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_res_oe~3_combout ),
|
|
.datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ),
|
|
.datac(\z80_|alu_|db_high[3]~1_combout ),
|
|
.datad(\z80_|alu_|db_high[1]~18_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_high[1]~19_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_high[1]~19 .lut_mask = 16'hEF0F;
|
|
defparam \z80_|alu_|db_high[1]~19 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y17_N16
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4 (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & ((\z80_|alu_|db_low[1]~12_combout ) # ((\z80_|execute_|ctl_alu_op1_sel_low~combout & \z80_|alu_|db_high[1]~19_combout )))) #
|
|
// (!\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (\z80_|execute_|ctl_alu_op1_sel_low~combout & ((\z80_|alu_|db_high[1]~19_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_op1_sel_low~combout ),
|
|
.datac(\z80_|alu_|db_low[1]~12_combout ),
|
|
.datad(\z80_|alu_|db_high[1]~19_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4 .lut_mask = 16'hECA0;
|
|
defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y17_N22
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ),
|
|
.datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .lut_mask = 16'h0F00;
|
|
defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y17_N23
|
|
dffeas \z80_|alu_|op1_low[1] (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|alu_|b2v_op1_latch_mux_low|Q[1]~5_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|alu_|op1_low [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|op1_low[1] .is_wysiwyg = "true";
|
|
defparam \z80_|alu_|op1_low[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y17_N14
|
|
cycloneive_lcell_comb \z80_|alu_control_|out[6]~0 (
|
|
// Equation(s):
|
|
// \z80_|alu_control_|out[6]~0_combout = (\z80_|alu_|op1_low [3] & ((\z80_|alu_|op1_low [1]) # (\z80_|alu_|op1_low [2])))
|
|
|
|
.dataa(\z80_|alu_|op1_low [1]),
|
|
.datab(gnd),
|
|
.datac(\z80_|alu_|op1_low [3]),
|
|
.datad(\z80_|alu_|op1_low [2]),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_control_|out[6]~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_control_|out[6]~0 .lut_mask = 16'hF0A0;
|
|
defparam \z80_|alu_control_|out[6]~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y14_N22
|
|
cycloneive_lcell_comb \z80_|alu_control_|out[6]~1 (
|
|
// Equation(s):
|
|
// \z80_|alu_control_|out[6]~1_combout = (\z80_|alu_|op1_high [2]) # ((\z80_|alu_|op1_high [1]) # ((\z80_|alu_control_|out[6]~0_combout & \z80_|alu_|op1_high [0])))
|
|
|
|
.dataa(\z80_|alu_|op1_high [2]),
|
|
.datab(\z80_|alu_control_|out[6]~0_combout ),
|
|
.datac(\z80_|alu_|op1_high [0]),
|
|
.datad(\z80_|alu_|op1_high [1]),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_control_|out[6]~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_control_|out[6]~1 .lut_mask = 16'hFFEA;
|
|
defparam \z80_|alu_control_|out[6]~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y14_N4
|
|
cycloneive_lcell_comb \z80_|alu_control_|out[6]~2 (
|
|
// Equation(s):
|
|
// \z80_|alu_control_|out[6]~2_combout = (\z80_|execute_|ctl_66_oe~combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_cf~q ) # ((\z80_|alu_control_|out[6]~1_combout & \z80_|alu_|op1_high [3])))
|
|
|
|
.dataa(\z80_|alu_control_|out[6]~1_combout ),
|
|
.datab(\z80_|execute_|ctl_66_oe~combout ),
|
|
.datac(\z80_|alu_flags_|DFFE_inst_latch_cf~q ),
|
|
.datad(\z80_|alu_|op1_high [3]),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_control_|out[6]~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_control_|out[6]~2 .lut_mask = 16'hFEFC;
|
|
defparam \z80_|alu_control_|out[6]~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y16_N6
|
|
cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_12 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout = (\z80_|alu_control_|db[6]~22_combout & \z80_|execute_|ctl_flags_bus~combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|alu_control_|db[6]~22_combout ),
|
|
.datad(\z80_|execute_|ctl_flags_bus~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_12 .lut_mask = 16'hF000;
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_12 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y16_N0
|
|
cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # (((!\z80_|pla_decode_|Equal13~0_combout ) # (!\z80_|execute_|ixy_d~7_combout )) # (!\z80_|pla_decode_|Equal55~0_combout ))
|
|
|
|
.dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ),
|
|
.datab(\z80_|pla_decode_|Equal55~0_combout ),
|
|
.datac(\z80_|execute_|ixy_d~7_combout ),
|
|
.datad(\z80_|pla_decode_|Equal13~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .lut_mask = 16'hBFFF;
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y17_N28
|
|
cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout = (!\z80_|alu_|db_high[3]~7_combout & (!\z80_|alu_|db_high[0]~25_combout & (!\z80_|alu_|db_high[2]~13_combout & !\z80_|alu_|db_high[1]~19_combout )))
|
|
|
|
.dataa(\z80_|alu_|db_high[3]~7_combout ),
|
|
.datab(\z80_|alu_|db_high[0]~25_combout ),
|
|
.datac(\z80_|alu_|db_high[2]~13_combout ),
|
|
.datad(\z80_|alu_|db_high[1]~19_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 .lut_mask = 16'h0001;
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y16_N4
|
|
cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout = (\z80_|alu_|db_high[3]~1_combout & (!\z80_|alu_|db_low[1]~12_combout & ((!\z80_|alu_|db_low[0]~3_combout ) # (!\z80_|alu_|db_low[0]~6_combout ))))
|
|
|
|
.dataa(\z80_|alu_|db_low[0]~6_combout ),
|
|
.datab(\z80_|alu_|db_high[3]~1_combout ),
|
|
.datac(\z80_|alu_|db_low[1]~12_combout ),
|
|
.datad(\z80_|alu_|db_low[0]~3_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .lut_mask = 16'h040C;
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y16_N24
|
|
cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout = (!\z80_|alu_|db_low[2]~23_combout & (\z80_|execute_|ctl_flags_alu~15_combout & (!\z80_|alu_|db_low[3]~25_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout )))
|
|
|
|
.dataa(\z80_|alu_|db_low[2]~23_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_alu~15_combout ),
|
|
.datac(\z80_|alu_|db_low[3]~25_combout ),
|
|
.datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .lut_mask = 16'h0400;
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y16_N12
|
|
cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout & ((\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ))))
|
|
|
|
.dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_12~combout ),
|
|
.datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~0_combout ),
|
|
.datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~2_combout ),
|
|
.datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_11~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .lut_mask = 16'hC888;
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_37~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y19_N26
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~7 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_sz_we~7_combout = (!\z80_|execute_|ctl_flags_sz_we~6_combout & \z80_|execute_|ctl_flags_xy_we~14_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_flags_sz_we~6_combout ),
|
|
.datad(\z80_|execute_|ctl_flags_xy_we~14_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_sz_we~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_sz_we~7 .lut_mask = 16'h0F00;
|
|
defparam \z80_|execute_|ctl_flags_sz_we~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y18_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_sz_we~8 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_sz_we~8_combout = (((!\z80_|execute_|ctl_flags_sz_we~3_combout ) # (!\z80_|execute_|ctl_flags_sz_we~2_combout )) # (!\z80_|execute_|ctl_flags_sz_we~4_combout )) # (!\z80_|execute_|ctl_flags_sz_we~7_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_sz_we~7_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_sz_we~4_combout ),
|
|
.datac(\z80_|execute_|ctl_flags_sz_we~2_combout ),
|
|
.datad(\z80_|execute_|ctl_flags_sz_we~3_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_sz_we~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_sz_we~8 .lut_mask = 16'h7FFF;
|
|
defparam \z80_|execute_|ctl_flags_sz_we~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X29_Y16_N13
|
|
dffeas \z80_|alu_flags_|SYNTHESIZED_WIRE_39 (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|alu_flags_|SYNTHESIZED_WIRE_37~1_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|execute_|ctl_flags_sz_we~8_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .is_wysiwyg = "true";
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_39 .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y15_N20
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~51 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~51_combout = (\z80_|execute_|setM1~50_combout & (!\z80_|pla_decode_|Equal52~1_combout & ((!\z80_|pla_decode_|Equal63~0_combout ) # (!\z80_|pla_decode_|Equal3~0_combout ))))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal3~0_combout ),
|
|
.datab(\z80_|pla_decode_|Equal63~0_combout ),
|
|
.datac(\z80_|execute_|setM1~50_combout ),
|
|
.datad(\z80_|pla_decode_|Equal52~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~51_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~51 .lut_mask = 16'h0070;
|
|
defparam \z80_|execute_|setM1~51 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y15_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_oe~2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_oe~2_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (((\z80_|execute_|ctl_state_alu~6_combout ) # (!\z80_|execute_|ctl_flags_oe~1_combout )) # (!\z80_|execute_|setM1~51_combout )))
|
|
|
|
.dataa(\z80_|execute_|setM1~51_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_oe~1_combout ),
|
|
.datac(\z80_|execute_|ctl_state_alu~6_combout ),
|
|
.datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_oe~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_oe~2 .lut_mask = 16'h00F7;
|
|
defparam \z80_|execute_|ctl_flags_oe~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y14_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_sw_2u~7 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_sw_2u~7_combout = (((\z80_|execute_|ctl_alu_oe~1_combout & \z80_|nM1_int~2_combout )) # (!\z80_|execute_|ctl_alu_oe~8_combout )) # (!\z80_|execute_|ctl_reg_out_hi~6_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_oe~1_combout ),
|
|
.datab(\z80_|nM1_int~2_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_out_hi~6_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_oe~8_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_sw_2u~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_sw_2u~7 .lut_mask = 16'h8FFF;
|
|
defparam \z80_|execute_|ctl_sw_2u~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y14_N10
|
|
cycloneive_lcell_comb \z80_|alu_control_|db[6]~20 (
|
|
// Equation(s):
|
|
// \z80_|alu_control_|db[6]~20_combout = (\z80_|alu_|db[6]~22_combout & (!\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & (\z80_|execute_|ctl_flags_oe~2_combout ))) # (!\z80_|alu_|db[6]~22_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) #
|
|
// ((!\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & \z80_|execute_|ctl_flags_oe~2_combout ))))
|
|
|
|
.dataa(\z80_|alu_|db[6]~22_combout ),
|
|
.datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ),
|
|
.datac(\z80_|execute_|ctl_flags_oe~2_combout ),
|
|
.datad(\z80_|execute_|ctl_sw_2u~7_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_control_|db[6]~20_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_control_|db[6]~20 .lut_mask = 16'h7530;
|
|
defparam \z80_|alu_control_|db[6]~20 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y14_N16
|
|
cycloneive_lcell_comb \z80_|alu_control_|db[6]~21 (
|
|
// Equation(s):
|
|
// \z80_|alu_control_|db[6]~21_combout = (!\z80_|alu_control_|db[6]~20_combout & ((\z80_|alu_control_|out[6]~2_combout ) # ((!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & !\z80_|execute_|ctl_66_oe~combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ),
|
|
.datab(\z80_|execute_|ctl_66_oe~combout ),
|
|
.datac(\z80_|alu_control_|out[6]~2_combout ),
|
|
.datad(\z80_|alu_control_|db[6]~20_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_control_|db[6]~21_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_control_|db[6]~21 .lut_mask = 16'h00F1;
|
|
defparam \z80_|alu_control_|db[6]~21 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y14_N24
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_out_lo~8 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_out_lo~8_combout = (\z80_|execute_|ctl_reg_out_lo~5_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~7_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_out_lo~5_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_out_lo~7_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_out_lo~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_out_lo~8 .lut_mask = 16'hBFBF;
|
|
defparam \z80_|execute_|ctl_reg_out_lo~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y14_N2
|
|
cycloneive_lcell_comb \z80_|alu_control_|db[6]~10 (
|
|
// Equation(s):
|
|
// \z80_|alu_control_|db[6]~10_combout = (\z80_|execute_|ctl_flags_oe~2_combout ) # ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|execute_|ctl_66_oe~2_combout & \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q )))
|
|
|
|
.dataa(\z80_|execute_|ctl_66_oe~2_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_oe~2_combout ),
|
|
.datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ),
|
|
.datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_control_|db[6]~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_control_|db[6]~10 .lut_mask = 16'hFFEC;
|
|
defparam \z80_|alu_control_|db[6]~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y14_N28
|
|
cycloneive_lcell_comb \z80_|alu_control_|db[6]~11 (
|
|
// Equation(s):
|
|
// \z80_|alu_control_|db[6]~11_combout = (\z80_|execute_|ctl_sw_1d~7_combout ) # ((\z80_|execute_|ctl_reg_out_lo~8_combout ) # ((\z80_|execute_|ctl_sw_2u~7_combout ) # (\z80_|alu_control_|db[6]~10_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_sw_1d~7_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_out_lo~8_combout ),
|
|
.datac(\z80_|execute_|ctl_sw_2u~7_combout ),
|
|
.datad(\z80_|alu_control_|db[6]~10_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_control_|db[6]~11_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_control_|db[6]~11 .lut_mask = 16'hFFFE;
|
|
defparam \z80_|alu_control_|db[6]~11 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y14_N20
|
|
cycloneive_lcell_comb \z80_|alu_control_|db[6]~22 (
|
|
// Equation(s):
|
|
// \z80_|alu_control_|db[6]~22_combout = ((\z80_|reg_file_|db_lo_ds[6]~0_combout & (\z80_|sw1_|db_down[6]~1_combout & \z80_|alu_control_|db[6]~21_combout ))) # (!\z80_|alu_control_|db[6]~11_combout )
|
|
|
|
.dataa(\z80_|reg_file_|db_lo_ds[6]~0_combout ),
|
|
.datab(\z80_|sw1_|db_down[6]~1_combout ),
|
|
.datac(\z80_|alu_control_|db[6]~21_combout ),
|
|
.datad(\z80_|alu_control_|db[6]~11_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_control_|db[6]~22_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_control_|db[6]~22 .lut_mask = 16'h80FF;
|
|
defparam \z80_|alu_control_|db[6]~22 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y15_N10
|
|
cycloneive_lcell_comb \z80_|alu_|db[6]~21 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db[6]~21_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[6]~84_combout & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout &
|
|
// ((\z80_|alu_control_|db[6]~22_combout ) # ((!\z80_|execute_|ctl_sw_2d~13_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ),
|
|
.datab(\z80_|alu_control_|db[6]~22_combout ),
|
|
.datac(\z80_|execute_|ctl_sw_2d~13_combout ),
|
|
.datad(\z80_|reg_file_|gdfx_temp1[6]~84_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db[6]~21_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db[6]~21 .lut_mask = 16'hCF45;
|
|
defparam \z80_|alu_|db[6]~21 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y15_N24
|
|
cycloneive_lcell_comb \z80_|alu_|db[6]~22 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db[6]~22_combout = ((\z80_|alu_|db[6]~21_combout & ((\z80_|alu_|db_high[2]~13_combout ) # (!\z80_|execute_|ctl_alu_oe~11_combout )))) # (!\z80_|alu_|db[7]~9_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_oe~11_combout ),
|
|
.datab(\z80_|alu_|db[7]~9_combout ),
|
|
.datac(\z80_|alu_|db_high[2]~13_combout ),
|
|
.datad(\z80_|alu_|db[6]~21_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db[6]~22_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db[6]~22 .lut_mask = 16'hF733;
|
|
defparam \z80_|alu_|db[6]~22 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y16_N3
|
|
dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[6] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[6] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y16_N2
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~80 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[6]~80_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[6]~22_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) #
|
|
// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ),
|
|
.datab(\z80_|alu_|db[6]~22_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [6]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[6]~80_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[6]~80 .lut_mask = 16'hD0DD;
|
|
defparam \z80_|reg_file_|gdfx_temp1[6]~80 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y16_N23
|
|
dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[6] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[6] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y16_N1
|
|
dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[6] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[6] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y16_N22
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~79 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[6]~79_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [6]),
|
|
.datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [6]),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[6]~79_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[6]~79 .lut_mask = 16'hF351;
|
|
defparam \z80_|reg_file_|gdfx_temp1[6]~79 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y16_N23
|
|
dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[6] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y16_N20
|
|
cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[6]~feeder (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|b2v_latch_bc_hi|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp1[6]~84_combout
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|reg_file_|gdfx_temp1[6]~84_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[6]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6]~feeder .lut_mask = 16'hFF00;
|
|
defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y16_N21
|
|
dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[6] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_file_|b2v_latch_bc_hi|latch[6]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[6] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y16_N22
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~78 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[6]~78_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [6]),
|
|
.datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [6]),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[6]~78_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[6]~78 .lut_mask = 16'hF531;
|
|
defparam \z80_|reg_file_|gdfx_temp1[6]~78 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X38_Y16_N30
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~82 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[6]~82_combout = (\z80_|reg_file_|gdfx_temp1[6]~81_combout & (\z80_|reg_file_|gdfx_temp1[6]~80_combout & (\z80_|reg_file_|gdfx_temp1[6]~79_combout & \z80_|reg_file_|gdfx_temp1[6]~78_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|gdfx_temp1[6]~81_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp1[6]~80_combout ),
|
|
.datac(\z80_|reg_file_|gdfx_temp1[6]~79_combout ),
|
|
.datad(\z80_|reg_file_|gdfx_temp1[6]~78_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[6]~82_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[6]~82 .lut_mask = 16'h8000;
|
|
defparam \z80_|reg_file_|gdfx_temp1[6]~82 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y14_N19
|
|
dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[6] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y14_N18
|
|
cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl2_hi|db[6]~5 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|b2v_latch_hl2_hi|db[6]~5_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]) # (!\z80_|reg_control_|reg_sel_hl2~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [6]),
|
|
.datad(\z80_|reg_control_|reg_sel_hl2~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|b2v_latch_hl2_hi|db[6]~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_hl2_hi|db[6]~5 .lut_mask = 16'hFBFF;
|
|
defparam \z80_|reg_file_|b2v_latch_hl2_hi|db[6]~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X36_Y15_N7
|
|
dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[6] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[6] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y15_N19
|
|
dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[6] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[6]~84_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[6] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y15_N24
|
|
cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout = \z80_|reg_file_|gdfx_temp1[6]~84_combout
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|reg_file_|gdfx_temp1[6]~84_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder .lut_mask = 16'hFF00;
|
|
defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y15_N25
|
|
dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[6] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_file_|b2v_latch_de_hi|latch[6]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_de_hi|latch [6]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_de_hi|latch[6] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y15_N18
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~76 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[6]~76_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [6] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [6])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [6]),
|
|
.datad(\z80_|reg_file_|b2v_latch_de_hi|latch [6]),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[6]~76_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[6]~76 .lut_mask = 16'hF351;
|
|
defparam \z80_|reg_file_|gdfx_temp1[6]~76 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y15_N6
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~77 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[6]~77_combout = (\z80_|reg_file_|b2v_latch_hl2_hi|db[6]~5_combout & (\z80_|reg_file_|gdfx_temp1[6]~76_combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ),
|
|
.datab(\z80_|reg_file_|b2v_latch_hl2_hi|db[6]~5_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_hl_hi|latch [6]),
|
|
.datad(\z80_|reg_file_|gdfx_temp1[6]~76_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[6]~77_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[6]~77 .lut_mask = 16'hC400;
|
|
defparam \z80_|reg_file_|gdfx_temp1[6]~77 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y15_N14
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~83 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[6]~83_combout = (\z80_|reg_file_|gdfx_temp1[6]~82_combout & (\z80_|reg_file_|gdfx_temp1[6]~77_combout & ((\z80_|reg_file_|b2v_latch_af_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|b2v_latch_af_hi|latch [6]),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ),
|
|
.datac(\z80_|reg_file_|gdfx_temp1[6]~82_combout ),
|
|
.datad(\z80_|reg_file_|gdfx_temp1[6]~77_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[6]~83_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[6]~83 .lut_mask = 16'hB000;
|
|
defparam \z80_|reg_file_|gdfx_temp1[6]~83 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y15_N12
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[6]~84 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[6]~84_combout = ((\z80_|reg_file_|gdfx_temp1[6]~83_combout & ((\z80_|reg_file_|db_hi_as[6]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_sw_4u~6_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp1[6]~83_combout ),
|
|
.datac(\z80_|reg_file_|db_hi_as[6]~24_combout ),
|
|
.datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[6]~84_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[6]~84 .lut_mask = 16'hC4FF;
|
|
defparam \z80_|reg_file_|gdfx_temp1[6]~84 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y14_N19
|
|
dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[6] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|db_hi_as[6]~24_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[6] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y14_N18
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~22 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_hi_as[6]~22_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[6]~84_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) #
|
|
// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))))
|
|
|
|
.dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp1[6]~84_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [6]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_hi_as[6]~22_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_hi_as[6]~22 .lut_mask = 16'hD0DD;
|
|
defparam \z80_|reg_file_|db_hi_as[6]~22 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y14_N17
|
|
dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[6] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_file_|db_hi_as[6]~24_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[6] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y14_N26
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~23 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_hi_as[6]~23_combout = (\z80_|reg_file_|db_hi_as[6]~22_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [6]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout )))
|
|
|
|
.dataa(\z80_|reg_file_|db_hi_as[6]~22_combout ),
|
|
.datab(\z80_|reg_file_|b2v_latch_pc_hi|latch [6]),
|
|
.datac(gnd),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_hi_as[6]~23_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_hi_as[6]~23 .lut_mask = 16'h88AA;
|
|
defparam \z80_|reg_file_|db_hi_as[6]~23 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y13_N14
|
|
cycloneive_lcell_comb \z80_|address_latch_|abusz[13] (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|abusz [13] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[5]~15_combout )
|
|
|
|
.dataa(\z80_|resets_|clrpc~0_combout ),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|reg_file_|db_hi_as[5]~15_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|abusz [13]),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|abusz[13] .lut_mask = 16'h5500;
|
|
defparam \z80_|address_latch_|abusz[13] .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y13_N15
|
|
dffeas \z80_|address_latch_|Q[13] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|address_latch_|abusz [13]),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|execute_|ctl_al_we~12_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|address_latch_|Q [13]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|Q[13] .is_wysiwyg = "true";
|
|
defparam \z80_|address_latch_|Q[13] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y13_N18
|
|
cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout = \z80_|address_latch_|Q [12] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & (\z80_|address_latch_|Q [11] $
|
|
// (\z80_|execute_|ctl_inc_dec~11_combout )))))
|
|
|
|
.dataa(\z80_|address_latch_|Q [11]),
|
|
.datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ),
|
|
.datac(\z80_|execute_|ctl_inc_dec~11_combout ),
|
|
.datad(\z80_|address_latch_|Q [12]),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .lut_mask = 16'hB748;
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y16_N31
|
|
dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[4] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y16_N29
|
|
dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[4] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y16_N30
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~61 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[4]~61_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [4]),
|
|
.datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [4]),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[4]~61_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[4]~61 .lut_mask = 16'hF351;
|
|
defparam \z80_|reg_file_|gdfx_temp1[4]~61 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y16_N15
|
|
dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[4] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y16_N14
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~62 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[4]~62_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[4]~18_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) #
|
|
// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ),
|
|
.datab(\z80_|alu_|db[4]~18_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [4]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[4]~62_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[4]~62 .lut_mask = 16'hD0DD;
|
|
defparam \z80_|reg_file_|gdfx_temp1[4]~62 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y16_N3
|
|
dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y16_N0
|
|
cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout = \z80_|reg_file_|gdfx_temp1[4]~66_combout
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder .lut_mask = 16'hFF00;
|
|
defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y16_N1
|
|
dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[4] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_file_|b2v_latch_bc_hi|latch[4]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y16_N2
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~60 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[4]~60_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [4])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [4]),
|
|
.datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [4]),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[4]~60_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[4]~60 .lut_mask = 16'hF531;
|
|
defparam \z80_|reg_file_|gdfx_temp1[4]~60 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y15_N29
|
|
dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[4] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y15_N23
|
|
dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[4] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y15_N22
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~63 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[4]~63_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ),
|
|
.datab(\z80_|reg_file_|b2v_latch_wz_hi|latch [4]),
|
|
.datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [4]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[4]~63_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[4]~63 .lut_mask = 16'hD0DD;
|
|
defparam \z80_|reg_file_|gdfx_temp1[4]~63 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y15_N10
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~64 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[4]~64_combout = (\z80_|reg_file_|gdfx_temp1[4]~61_combout & (\z80_|reg_file_|gdfx_temp1[4]~62_combout & (\z80_|reg_file_|gdfx_temp1[4]~60_combout & \z80_|reg_file_|gdfx_temp1[4]~63_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|gdfx_temp1[4]~61_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp1[4]~62_combout ),
|
|
.datac(\z80_|reg_file_|gdfx_temp1[4]~60_combout ),
|
|
.datad(\z80_|reg_file_|gdfx_temp1[4]~63_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[4]~64_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[4]~64 .lut_mask = 16'h8000;
|
|
defparam \z80_|reg_file_|gdfx_temp1[4]~64 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X36_Y15_N5
|
|
dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[4] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_file_|gdfx_temp1[4]~66_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_af_hi|latch [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_af_hi|latch[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y14_N5
|
|
dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y14_N4
|
|
cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl2_hi|db[4]~4 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|b2v_latch_hl2_hi|db[4]~4_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]) # (!\z80_|reg_control_|reg_sel_hl2~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [4]),
|
|
.datad(\z80_|reg_control_|reg_sel_hl2~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|b2v_latch_hl2_hi|db[4]~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_hl2_hi|db[4]~4 .lut_mask = 16'hFBFF;
|
|
defparam \z80_|reg_file_|b2v_latch_hl2_hi|db[4]~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X36_Y15_N1
|
|
dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[4] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y15_N5
|
|
dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[4] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_de_hi|latch [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_de_hi|latch[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y15_N23
|
|
dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[4] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[4]~66_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y15_N22
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~58 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[4]~58_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [4] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ),
|
|
.datab(\z80_|reg_file_|b2v_latch_de_hi|latch [4]),
|
|
.datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [4]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[4]~58_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[4]~58 .lut_mask = 16'hD0DD;
|
|
defparam \z80_|reg_file_|gdfx_temp1[4]~58 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y15_N0
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~59 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[4]~59_combout = (\z80_|reg_file_|b2v_latch_hl2_hi|db[4]~4_combout & (\z80_|reg_file_|gdfx_temp1[4]~58_combout & ((\z80_|reg_file_|b2v_latch_hl_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ),
|
|
.datab(\z80_|reg_file_|b2v_latch_hl2_hi|db[4]~4_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_hl_hi|latch [4]),
|
|
.datad(\z80_|reg_file_|gdfx_temp1[4]~58_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[4]~59_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[4]~59 .lut_mask = 16'hC400;
|
|
defparam \z80_|reg_file_|gdfx_temp1[4]~59 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y15_N22
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~65 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[4]~65_combout = (\z80_|reg_file_|gdfx_temp1[4]~64_combout & (\z80_|reg_file_|gdfx_temp1[4]~59_combout & ((\z80_|reg_file_|b2v_latch_af_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|gdfx_temp1[4]~64_combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_32~combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_af_hi|latch [4]),
|
|
.datad(\z80_|reg_file_|gdfx_temp1[4]~59_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[4]~65_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[4]~65 .lut_mask = 16'hA200;
|
|
defparam \z80_|reg_file_|gdfx_temp1[4]~65 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y15_N4
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[4]~66 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[4]~66_combout = ((\z80_|reg_file_|gdfx_temp1[4]~65_combout & ((\z80_|reg_file_|db_hi_as[4]~18_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_sw_4u~6_combout ),
|
|
.datab(\z80_|reg_file_|db_hi_as[4]~18_combout ),
|
|
.datac(\z80_|reg_file_|gdfx_temp1[4]~65_combout ),
|
|
.datad(\z80_|reg_file_|gdfx_temp1[0]~20_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[4]~66_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[4]~66 .lut_mask = 16'hD0FF;
|
|
defparam \z80_|reg_file_|gdfx_temp1[4]~66 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y14_N11
|
|
dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[4] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|db_hi_as[4]~18_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y14_N10
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~16 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_hi_as[4]~16_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[4]~66_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) #
|
|
// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))))
|
|
|
|
.dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp1[4]~66_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [4]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_hi_as[4]~16_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_hi_as[4]~16 .lut_mask = 16'hD0DD;
|
|
defparam \z80_|reg_file_|db_hi_as[4]~16 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y14_N25
|
|
dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[4] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_file_|db_hi_as[4]~18_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y14_N2
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~17 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_hi_as[4]~17_combout = (\z80_|reg_file_|db_hi_as[4]~16_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [4]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout )))
|
|
|
|
.dataa(\z80_|reg_file_|db_hi_as[4]~16_combout ),
|
|
.datab(\z80_|reg_file_|b2v_latch_pc_hi|latch [4]),
|
|
.datac(gnd),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_hi_as[4]~17_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_hi_as[4]~17 .lut_mask = 16'h88AA;
|
|
defparam \z80_|reg_file_|db_hi_as[4]~17 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y14_N24
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[4]~18 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_hi_as[4]~18_combout = ((\z80_|reg_file_|db_hi_as[4]~17_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout )
|
|
|
|
.dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ),
|
|
.datab(\z80_|reg_file_|db_hi_as[4]~17_combout ),
|
|
.datac(\z80_|reg_file_|db_hi_as[0]~2_combout ),
|
|
.datad(\z80_|execute_|ctl_bus_inc_oe~43_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_hi_as[4]~18_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_hi_as[4]~18 .lut_mask = 16'h8FCF;
|
|
defparam \z80_|reg_file_|db_hi_as[4]~18 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y13_N22
|
|
cycloneive_lcell_comb \z80_|address_latch_|abusz[12] (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|abusz [12] = (\z80_|reg_file_|db_hi_as[4]~18_combout & !\z80_|resets_|clrpc~0_combout )
|
|
|
|
.dataa(\z80_|reg_file_|db_hi_as[4]~18_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|resets_|clrpc~0_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|abusz [12]),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|abusz[12] .lut_mask = 16'h0A0A;
|
|
defparam \z80_|address_latch_|abusz[12] .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y13_N23
|
|
dffeas \z80_|address_latch_|Q[12] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|address_latch_|abusz [12]),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|execute_|ctl_al_we~12_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|address_latch_|Q [12]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|Q[12] .is_wysiwyg = "true";
|
|
defparam \z80_|address_latch_|Q[12] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y13_N20
|
|
cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout & ((\z80_|address_latch_|Q [11] & (!\z80_|execute_|ctl_inc_dec~11_combout &
|
|
// \z80_|address_latch_|Q [12])) # (!\z80_|address_latch_|Q [11] & (\z80_|execute_|ctl_inc_dec~11_combout & !\z80_|address_latch_|Q [12]))))
|
|
|
|
.dataa(\z80_|address_latch_|Q [11]),
|
|
.datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ),
|
|
.datac(\z80_|execute_|ctl_inc_dec~11_combout ),
|
|
.datad(\z80_|address_latch_|Q [12]),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'h0840;
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y13_N24
|
|
cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[14] (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|b2v_inst_inc_dec|address [14] = \z80_|address_latch_|Q [14] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & (\z80_|address_latch_|Q [13] $ (\z80_|execute_|ctl_inc_dec~11_combout )))))
|
|
|
|
.dataa(\z80_|address_latch_|Q [13]),
|
|
.datab(\z80_|execute_|ctl_inc_dec~11_combout ),
|
|
.datac(\z80_|address_latch_|Q [14]),
|
|
.datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|b2v_inst_inc_dec|address [14]),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .lut_mask = 16'h96F0;
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|address[14] .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y14_N16
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[6]~24 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_hi_as[6]~24_combout = ((\z80_|reg_file_|db_hi_as[6]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [14]) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ),
|
|
.datab(\z80_|reg_file_|db_hi_as[0]~2_combout ),
|
|
.datac(\z80_|reg_file_|db_hi_as[6]~23_combout ),
|
|
.datad(\z80_|address_latch_|b2v_inst_inc_dec|address [14]),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_hi_as[6]~24_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_hi_as[6]~24 .lut_mask = 16'hF373;
|
|
defparam \z80_|reg_file_|db_hi_as[6]~24 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y13_N30
|
|
cycloneive_lcell_comb \z80_|address_latch_|abusz[14] (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|abusz [14] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[6]~24_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|resets_|clrpc~0_combout ),
|
|
.datad(\z80_|reg_file_|db_hi_as[6]~24_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|abusz [14]),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|abusz[14] .lut_mask = 16'h0F00;
|
|
defparam \z80_|address_latch_|abusz[14] .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y13_N31
|
|
dffeas \z80_|address_latch_|Q[14] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|address_latch_|abusz [14]),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|execute_|ctl_al_we~12_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|address_latch_|Q [14]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|Q[14] .is_wysiwyg = "true";
|
|
defparam \z80_|address_latch_|Q[14] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y13_N4
|
|
cycloneive_lcell_comb \z80_|address_latch_|abusz[15] (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|abusz [15] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[7]~21_combout )
|
|
|
|
.dataa(\z80_|resets_|clrpc~0_combout ),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|reg_file_|db_hi_as[7]~21_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|abusz [15]),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|abusz[15] .lut_mask = 16'h5500;
|
|
defparam \z80_|address_latch_|abusz[15] .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y13_N5
|
|
dffeas \z80_|address_latch_|Q[15] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|address_latch_|abusz [15]),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|execute_|ctl_al_we~12_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|address_latch_|Q [15]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|Q[15] .is_wysiwyg = "true";
|
|
defparam \z80_|address_latch_|Q[15] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y11_N2
|
|
cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[15]~0 (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|b2v_inst_inc_dec|address[15]~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout & (\z80_|address_latch_|Q [13] $ (((\z80_|execute_|ctl_inc_dec~10_combout ) #
|
|
// (\z80_|execute_|ctl_inc_dec~7_combout )))))
|
|
|
|
.dataa(\z80_|execute_|ctl_inc_dec~10_combout ),
|
|
.datab(\z80_|execute_|ctl_inc_dec~7_combout ),
|
|
.datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ),
|
|
.datad(\z80_|address_latch_|Q [13]),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|b2v_inst_inc_dec|address[15]~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15]~0 .lut_mask = 16'h10E0;
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15]~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y13_N0
|
|
cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[15]~1 (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|b2v_inst_inc_dec|address[15]~1_combout = \z80_|address_latch_|Q [15] $ (((\z80_|address_latch_|b2v_inst_inc_dec|address[15]~0_combout & (\z80_|address_latch_|Q [14] $ (\z80_|execute_|ctl_inc_dec~11_combout )))))
|
|
|
|
.dataa(\z80_|address_latch_|Q [14]),
|
|
.datab(\z80_|execute_|ctl_inc_dec~11_combout ),
|
|
.datac(\z80_|address_latch_|Q [15]),
|
|
.datad(\z80_|address_latch_|b2v_inst_inc_dec|address[15]~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|b2v_inst_inc_dec|address[15]~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15]~1 .lut_mask = 16'h96F0;
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|address[15]~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y14_N7
|
|
dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[7] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_file_|db_hi_as[7]~21_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[7] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y14_N21
|
|
dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[7] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|db_hi_as[7]~21_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[7] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y14_N20
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~19 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_hi_as[7]~19_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[7]~75_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) #
|
|
// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))
|
|
|
|
.dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [7]),
|
|
.datad(\z80_|reg_file_|gdfx_temp1[7]~75_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_hi_as[7]~19_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_hi_as[7]~19 .lut_mask = 16'hF351;
|
|
defparam \z80_|reg_file_|db_hi_as[7]~19 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y14_N12
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~20 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_hi_as[7]~20_combout = (\z80_|reg_file_|db_hi_as[7]~19_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout )))
|
|
|
|
.dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [7]),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|reg_file_|db_hi_as[7]~19_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_hi_as[7]~20_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_hi_as[7]~20 .lut_mask = 16'hBB00;
|
|
defparam \z80_|reg_file_|db_hi_as[7]~20 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y14_N6
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[7]~21 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_hi_as[7]~21_combout = ((\z80_|reg_file_|db_hi_as[7]~20_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address[15]~1_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ),
|
|
.datab(\z80_|address_latch_|b2v_inst_inc_dec|address[15]~1_combout ),
|
|
.datac(\z80_|reg_file_|db_hi_as[0]~2_combout ),
|
|
.datad(\z80_|reg_file_|db_hi_as[7]~20_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_hi_as[7]~21_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_hi_as[7]~21 .lut_mask = 16'hDF0F;
|
|
defparam \z80_|reg_file_|db_hi_as[7]~21 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X36_Y15_N29
|
|
dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[7] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_af_hi|latch [7]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_af_hi|latch[7] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y15_N28
|
|
cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[7]~15 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|b2v_latch_af_hi|db[7]~15_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [7]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_af_hi|latch [7]),
|
|
.datad(\z80_|reg_control_|reg_sel_af~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|b2v_latch_af_hi|db[7]~15_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~15 .lut_mask = 16'hFBFF;
|
|
defparam \z80_|reg_file_|b2v_latch_af_hi|db[7]~15 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y15_N31
|
|
dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[7] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_file_|gdfx_temp1[7]~75_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[7] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y15_N25
|
|
dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[7] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[7] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y15_N24
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~72 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[7]~72_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ),
|
|
.datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [7]),
|
|
.datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [7]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[7]~72_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[7]~72 .lut_mask = 16'hC4F5;
|
|
defparam \z80_|reg_file_|gdfx_temp1[7]~72 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y16_N17
|
|
dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[7] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[7] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y16_N16
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~71 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[7]~71_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[7]~12_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) #
|
|
// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ),
|
|
.datab(\z80_|alu_|db[7]~12_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [7]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[7]~71_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[7]~71 .lut_mask = 16'hD0DD;
|
|
defparam \z80_|reg_file_|gdfx_temp1[7]~71 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y16_N11
|
|
dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[7] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[7] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y16_N13
|
|
dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[7] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[7] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y16_N10
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~70 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[7]~70_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [7]),
|
|
.datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [7]),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[7]~70_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[7]~70 .lut_mask = 16'hF351;
|
|
defparam \z80_|reg_file_|gdfx_temp1[7]~70 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y16_N15
|
|
dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[7] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y16_N29
|
|
dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[7] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[7] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y16_N14
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~69 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[7]~69_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [7]),
|
|
.datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [7]),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[7]~69_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[7]~69 .lut_mask = 16'hF531;
|
|
defparam \z80_|reg_file_|gdfx_temp1[7]~69 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X38_Y16_N24
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~73 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[7]~73_combout = (\z80_|reg_file_|gdfx_temp1[7]~72_combout & (\z80_|reg_file_|gdfx_temp1[7]~71_combout & (\z80_|reg_file_|gdfx_temp1[7]~70_combout & \z80_|reg_file_|gdfx_temp1[7]~69_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|gdfx_temp1[7]~72_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp1[7]~71_combout ),
|
|
.datac(\z80_|reg_file_|gdfx_temp1[7]~70_combout ),
|
|
.datad(\z80_|reg_file_|gdfx_temp1[7]~69_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[7]~73_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[7]~73 .lut_mask = 16'h8000;
|
|
defparam \z80_|reg_file_|gdfx_temp1[7]~73 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y14_N15
|
|
dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[7] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[7] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y14_N25
|
|
dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[7] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y14_N24
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~68 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[7]~68_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ),
|
|
.datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [7]),
|
|
.datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [7]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[7]~68_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[7]~68 .lut_mask = 16'hD0DD;
|
|
defparam \z80_|reg_file_|gdfx_temp1[7]~68 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y15_N3
|
|
dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[7] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[7]~75_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[7] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y15_N0
|
|
cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[7]~feeder (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|b2v_latch_de_hi|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp1[7]~75_combout
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|reg_file_|gdfx_temp1[7]~75_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|b2v_latch_de_hi|latch[7]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7]~feeder .lut_mask = 16'hFF00;
|
|
defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y15_N1
|
|
dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[7] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_file_|b2v_latch_de_hi|latch[7]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_de_hi|latch [7]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_de_hi|latch[7] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y15_N2
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~67 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[7]~67_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [7] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [7]),
|
|
.datad(\z80_|reg_file_|b2v_latch_de_hi|latch [7]),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[7]~67_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[7]~67 .lut_mask = 16'hF351;
|
|
defparam \z80_|reg_file_|gdfx_temp1[7]~67 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X38_Y15_N10
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~74 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[7]~74_combout = (\z80_|reg_file_|b2v_latch_af_hi|db[7]~15_combout & (\z80_|reg_file_|gdfx_temp1[7]~73_combout & (\z80_|reg_file_|gdfx_temp1[7]~68_combout & \z80_|reg_file_|gdfx_temp1[7]~67_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|b2v_latch_af_hi|db[7]~15_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp1[7]~73_combout ),
|
|
.datac(\z80_|reg_file_|gdfx_temp1[7]~68_combout ),
|
|
.datad(\z80_|reg_file_|gdfx_temp1[7]~67_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[7]~74_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[7]~74 .lut_mask = 16'h8000;
|
|
defparam \z80_|reg_file_|gdfx_temp1[7]~74 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y15_N30
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[7]~75 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[7]~75_combout = ((\z80_|reg_file_|gdfx_temp1[7]~74_combout & ((\z80_|reg_file_|db_hi_as[7]~21_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout )
|
|
|
|
.dataa(\z80_|reg_file_|db_hi_as[7]~21_combout ),
|
|
.datab(\z80_|execute_|ctl_sw_4u~6_combout ),
|
|
.datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ),
|
|
.datad(\z80_|reg_file_|gdfx_temp1[7]~74_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[7]~75_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[7]~75 .lut_mask = 16'hBF0F;
|
|
defparam \z80_|reg_file_|gdfx_temp1[7]~75 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y15_N0
|
|
cycloneive_lcell_comb \z80_|alu_|db[7]~11 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db[7]~11_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[7]~75_combout & ((\z80_|alu_control_|db[7]~19_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout &
|
|
// ((\z80_|alu_control_|db[7]~19_combout ) # ((!\z80_|execute_|ctl_sw_2d~13_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ),
|
|
.datab(\z80_|alu_control_|db[7]~19_combout ),
|
|
.datac(\z80_|execute_|ctl_sw_2d~13_combout ),
|
|
.datad(\z80_|reg_file_|gdfx_temp1[7]~75_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db[7]~11_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db[7]~11 .lut_mask = 16'hCF45;
|
|
defparam \z80_|alu_|db[7]~11 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y15_N30
|
|
cycloneive_lcell_comb \z80_|alu_|db[7]~12 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db[7]~12_combout = ((\z80_|alu_|db[7]~11_combout & ((\z80_|alu_|db_high[3]~7_combout ) # (!\z80_|execute_|ctl_alu_oe~11_combout )))) # (!\z80_|alu_|db[7]~9_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_oe~11_combout ),
|
|
.datab(\z80_|alu_|db[7]~9_combout ),
|
|
.datac(\z80_|alu_|db_high[3]~7_combout ),
|
|
.datad(\z80_|alu_|db[7]~11_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db[7]~12_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db[7]~12 .lut_mask = 16'hF733;
|
|
defparam \z80_|alu_|db[7]~12 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y14_N28
|
|
cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~0 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[0]~14_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[7]~12_combout )))
|
|
|
|
.dataa(\z80_|alu_|db[0]~14_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|alu_|db[7]~12_combout ),
|
|
.datad(\z80_|ir_|opcode [3]),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .lut_mask = 16'hAAF0;
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y14_N2
|
|
cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~1 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_control_|out[6]~2_combout )))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|alu_flags_|DFFE_inst_latch_cf2~0_combout ),
|
|
.datac(\z80_|alu_control_|out[6]~2_combout ),
|
|
.datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .lut_mask = 16'hCCF0;
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y14_N20
|
|
cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~2 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout & (((\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout & !\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout )))) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout
|
|
// & ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((!\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ))))
|
|
|
|
.dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ),
|
|
.datab(\z80_|alu_flags_|DFFE_inst_latch_cf2~1_combout ),
|
|
.datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ),
|
|
.datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .lut_mask = 16'h03CA;
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y14_N8
|
|
cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf2~3 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout = (\z80_|execute_|ctl_flags_cf2_we~3_combout & (\z80_|execute_|ctl_flags_cf2_sel_daa~combout $ (((!\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ))))) # (!\z80_|execute_|ctl_flags_cf2_we~3_combout &
|
|
// ((\z80_|alu_flags_|DFFE_inst_latch_cf2~q ) # ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout & \z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ),
|
|
.datab(\z80_|execute_|ctl_flags_cf2_we~3_combout ),
|
|
.datac(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ),
|
|
.datad(\z80_|alu_flags_|DFFE_inst_latch_cf2~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .lut_mask = 16'hBA74;
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_cf2~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X29_Y14_N9
|
|
dffeas \z80_|alu_flags_|DFFE_inst_latch_cf2 (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|alu_flags_|DFFE_inst_latch_cf2~3_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .is_wysiwyg = "true";
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_cf2 .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y17_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~8 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_use_cf2~8_combout = (\z80_|pla_decode_|Equal20~0_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # (\z80_|execute_|ctl_ir_we~8_combout ))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal20~0_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_ir_we~14_combout ),
|
|
.datad(\z80_|execute_|ctl_ir_we~8_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_use_cf2~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_use_cf2~8 .lut_mask = 16'hFFFA;
|
|
defparam \z80_|execute_|ctl_flags_use_cf2~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y17_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~9 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_use_cf2~9_combout = (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & ((\z80_|execute_|ctl_flags_use_cf2~8_combout ) # ((\z80_|pla_decode_|Equal63~0_combout & \z80_|pla_decode_|Equal9~0_combout ))))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal63~0_combout ),
|
|
.datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ),
|
|
.datac(\z80_|execute_|ctl_flags_use_cf2~8_combout ),
|
|
.datad(\z80_|pla_decode_|Equal9~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_use_cf2~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_use_cf2~9 .lut_mask = 16'h3230;
|
|
defparam \z80_|execute_|ctl_flags_use_cf2~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y15_N24
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~10 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_use_cf2~10_combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_M1_ff~q ))))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.datab(\z80_|pla_decode_|Equal11~0_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datad(\z80_|sequencer_|DFFE_M3_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_use_cf2~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_use_cf2~10 .lut_mask = 16'h0C04;
|
|
defparam \z80_|execute_|ctl_flags_use_cf2~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y15_N28
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~11 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_use_cf2~11_combout = (\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ) # ((\z80_|execute_|ctl_flags_use_cf2~10_combout ) # ((\z80_|execute_|ixy_d~7_combout & \z80_|pla_decode_|Equal10~0_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_pf_sel_pla66npla53M1T1_15~combout ),
|
|
.datab(\z80_|execute_|ixy_d~7_combout ),
|
|
.datac(\z80_|pla_decode_|Equal10~0_combout ),
|
|
.datad(\z80_|execute_|ctl_flags_use_cf2~10_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_use_cf2~11_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_use_cf2~11 .lut_mask = 16'hFFEA;
|
|
defparam \z80_|execute_|ctl_flags_use_cf2~11 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y15_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_use_cf2~12 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_use_cf2~12_combout = ((\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ) # ((\z80_|execute_|ctl_flags_use_cf2~9_combout ) # (\z80_|execute_|ctl_flags_use_cf2~11_combout ))) # (!\z80_|execute_|ctl_flags_use_cf2~13_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_use_cf2~13_combout ),
|
|
.datab(\z80_|execute_|ctl_pf_sel_pla11M1T1_11~combout ),
|
|
.datac(\z80_|execute_|ctl_flags_use_cf2~9_combout ),
|
|
.datad(\z80_|execute_|ctl_flags_use_cf2~11_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_use_cf2~12_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_use_cf2~12 .lut_mask = 16'hFFFD;
|
|
defparam \z80_|execute_|ctl_flags_use_cf2~12 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y14_N28
|
|
cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout = (\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & (\z80_|alu_flags_|DFFE_inst_latch_cf2~q )) # (!\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout & ((\z80_|execute_|ctl_flags_use_cf2~12_combout &
|
|
// (\z80_|alu_flags_|DFFE_inst_latch_cf2~q )) # (!\z80_|execute_|ctl_flags_use_cf2~12_combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~q )))))
|
|
|
|
.dataa(\z80_|alu_flags_|DFFE_inst_latch_cf2~q ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ),
|
|
.datac(\z80_|execute_|ctl_flags_use_cf2~12_combout ),
|
|
.datad(\z80_|alu_flags_|DFFE_inst_latch_cf~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .lut_mask = 16'hABA8;
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y15_N18
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~46 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op_low~46_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|pla_decode_|Equal10~0_combout & \z80_|sequencer_|DFFE_T3_ff~q ))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_M2_ff~q ),
|
|
.datab(\z80_|pla_decode_|Equal10~0_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op_low~46_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op_low~46 .lut_mask = 16'h8800;
|
|
defparam \z80_|execute_|ctl_alu_op_low~46 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y19_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~9 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_sel_op2_neg~9_combout = (\z80_|execute_|ctl_alu_core_S~4_combout & (\z80_|execute_|ctl_bus_inc_oe~44_combout & (\z80_|execute_|ctl_flags_alu~18_combout & \z80_|execute_|ctl_alu_op1_sel_bus~9_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_core_S~4_combout ),
|
|
.datab(\z80_|execute_|ctl_bus_inc_oe~44_combout ),
|
|
.datac(\z80_|execute_|ctl_flags_alu~18_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op1_sel_bus~9_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|ctl_alu_sel_op2_neg~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y18_N28
|
|
cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout = (\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # ((\z80_|pla_decode_|Equal63~0_combout & (\z80_|pla_decode_|Equal21~0_combout & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal63~0_combout ),
|
|
.datab(\z80_|pla_decode_|Equal21~0_combout ),
|
|
.datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ),
|
|
.datad(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .lut_mask = 16'hFF08;
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y15_N10
|
|
cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout = (\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ) # ((\z80_|execute_|ctl_alu_op_low~46_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~9_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_op_low~46_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ),
|
|
.datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~10_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .lut_mask = 16'hFFEF;
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~11 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y16_N16
|
|
cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout = ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ) # ((\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout & \z80_|execute_|ctl_alu_op_low~42_combout ))) # (!\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_pf_sel_pla82M1T1_16~combout ),
|
|
.datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~13_combout ),
|
|
.datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~11_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op_low~42_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .lut_mask = 16'hFBF3;
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~14 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y17_N16
|
|
cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout = (\z80_|execute_|ctl_state_alu~11_combout & ((\z80_|ir_|opcode [5] & (\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3])) # (!\z80_|ir_|opcode [5] & ((!\z80_|ir_|opcode [3])))))
|
|
|
|
.dataa(\z80_|ir_|opcode [5]),
|
|
.datab(\z80_|ir_|opcode [4]),
|
|
.datac(\z80_|execute_|ctl_state_alu~11_combout ),
|
|
.datad(\z80_|ir_|opcode [3]),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .lut_mask = 16'h8050;
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y16_N22
|
|
cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ) # ((\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ) # ((\z80_|execute_|ctl_alu_op_low~41_combout & \z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout )))
|
|
|
|
.dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~9_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_op_low~41_combout ),
|
|
.datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~14_combout ),
|
|
.datad(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~15_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .lut_mask = 16'hFEFA;
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_0~16 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y16_N18
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_cf_cpl~3 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_cf_cpl~3_combout = (\z80_|execute_|ctl_alu_op_low~41_combout & (\z80_|pla_decode_|Equal64~0_combout & ((\z80_|pla_decode_|Equal9~0_combout ) # (\z80_|pla_decode_|Equal3~0_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op_low~41_combout ),
|
|
.datab(\z80_|pla_decode_|Equal9~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal64~0_combout ),
|
|
.datad(\z80_|pla_decode_|Equal3~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_cf_cpl~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_cf_cpl~3 .lut_mask = 16'hA080;
|
|
defparam \z80_|execute_|ctl_flags_cf_cpl~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y16_N20
|
|
cycloneive_lcell_comb \z80_|alu_flags_|flags_cf (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|flags_cf~combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout $ (((\z80_|execute_|ctl_flags_cf_cpl~9_combout ) # (\z80_|execute_|ctl_flags_cf_cpl~3_combout )))))
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_cf_cpl~9_combout ),
|
|
.datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~8_combout ),
|
|
.datac(\z80_|alu_flags_|SYNTHESIZED_WIRE_0~16_combout ),
|
|
.datad(\z80_|execute_|ctl_flags_cf_cpl~3_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|flags_cf~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|flags_cf .lut_mask = 16'h0C48;
|
|
defparam \z80_|alu_flags_|flags_cf .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y14_N14
|
|
cycloneive_lcell_comb \z80_|sw2_|db_up[0]~0 (
|
|
// Equation(s):
|
|
// \z80_|sw2_|db_up[0]~0_combout = (\z80_|alu_|db[0]~14_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|alu_|db[0]~14_combout ),
|
|
.datad(\z80_|execute_|ctl_sw_2u~7_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|sw2_|db_up[0]~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|sw2_|db_up[0]~0 .lut_mask = 16'hF0FF;
|
|
defparam \z80_|sw2_|db_up[0]~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y14_N14
|
|
cycloneive_lcell_comb \z80_|alu_control_|db[0]~8 (
|
|
// Equation(s):
|
|
// \z80_|alu_control_|db[0]~8_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[0]~17_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_sw_mask543_en~0_combout ),
|
|
.datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ),
|
|
.datac(\z80_|execute_|ctl_sw_1d~7_combout ),
|
|
.datad(\z80_|bus_control_|db[0]~17_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_control_|db[0]~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_control_|db[0]~8 .lut_mask = 16'h4C0C;
|
|
defparam \z80_|alu_control_|db[0]~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y12_N11
|
|
dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[0] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_file_|db_lo_as[0]~3_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y12_N5
|
|
dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[0] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|db_lo_as[0]~3_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y12_N4
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~0 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_lo_as[0]~0_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[0]~22_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) #
|
|
// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_sw_4d~6_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp0[0]~22_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [0]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_lo_as[0]~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_lo_as[0]~0 .lut_mask = 16'hD0DD;
|
|
defparam \z80_|reg_file_|db_lo_as[0]~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y12_N0
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~1 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_lo_as[0]~1_combout = (\z80_|reg_file_|db_lo_as[0]~0_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout )))
|
|
|
|
.dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [0]),
|
|
.datab(gnd),
|
|
.datac(\z80_|reg_file_|db_lo_as[0]~0_combout ),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_lo_as[0]~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_lo_as[0]~1 .lut_mask = 16'hA0F0;
|
|
defparam \z80_|reg_file_|db_lo_as[0]~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y15_N28
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~70 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~70_combout = (!\z80_|nM1_int~2_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|pla_decode_|Equal41~2_combout )))
|
|
|
|
.dataa(\z80_|execute_|ixy_d~5_combout ),
|
|
.datab(\z80_|pla_decode_|Equal41~2_combout ),
|
|
.datac(\z80_|nM1_int~2_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op_low~22_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~70_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~70 .lut_mask = 16'h0307;
|
|
defparam \z80_|execute_|ctl_inc_cy~70 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y14_N8
|
|
cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~28 (
|
|
// Equation(s):
|
|
// \z80_|execute_|pc_inc_hold~28_combout = (\z80_|pla_decode_|Equal10~0_combout & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q ))))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T4_ff~q ),
|
|
.datab(\z80_|pla_decode_|Equal10~0_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_M4_ff~q ),
|
|
.datad(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|pc_inc_hold~28_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|pc_inc_hold~28 .lut_mask = 16'hC080;
|
|
defparam \z80_|execute_|pc_inc_hold~28 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y14_N10
|
|
cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~15 (
|
|
// Equation(s):
|
|
// \z80_|execute_|pc_inc_hold~15_combout = (\z80_|execute_|pc_inc_hold~28_combout ) # ((\z80_|execute_|ctl_alu_op_low~22_combout & ((\z80_|pla_decode_|Equal52~1_combout ) # (\z80_|execute_|ixy_d~16_combout ))))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal52~1_combout ),
|
|
.datab(\z80_|execute_|ixy_d~16_combout ),
|
|
.datac(\z80_|execute_|pc_inc_hold~28_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op_low~22_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|pc_inc_hold~15_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|pc_inc_hold~15 .lut_mask = 16'hFEF0;
|
|
defparam \z80_|execute_|pc_inc_hold~15 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y14_N18
|
|
cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~27 (
|
|
// Equation(s):
|
|
// \z80_|execute_|pc_inc_hold~27_combout = (\z80_|pla_decode_|Equal11~0_combout & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q ))))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T4_ff~q ),
|
|
.datab(\z80_|pla_decode_|Equal11~0_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_M4_ff~q ),
|
|
.datad(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|pc_inc_hold~27_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|pc_inc_hold~27 .lut_mask = 16'hC080;
|
|
defparam \z80_|execute_|pc_inc_hold~27 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y13_N26
|
|
cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~10 (
|
|
// Equation(s):
|
|
// \z80_|execute_|pc_inc_hold~10_combout = (\z80_|execute_|ctl_alu_op_low~22_combout & (((\z80_|execute_|ctl_mRead~7_combout ) # (\z80_|execute_|ctl_mRead~13_combout )))) # (!\z80_|execute_|ctl_alu_op_low~22_combout & (\z80_|execute_|ixy_d~5_combout &
|
|
// ((\z80_|execute_|ctl_mRead~13_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ixy_d~5_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~7_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_op_low~22_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~13_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|pc_inc_hold~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|pc_inc_hold~10 .lut_mask = 16'hFAC0;
|
|
defparam \z80_|execute_|pc_inc_hold~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y13_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout = (\z80_|execute_|ixy_d~5_combout & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|pla_decode_|Equal55~0_combout & \z80_|pla_decode_|Equal33~1_combout )))
|
|
|
|
.dataa(\z80_|execute_|ixy_d~5_combout ),
|
|
.datab(\z80_|pla_decode_|Equal6~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal55~0_combout ),
|
|
.datad(\z80_|pla_decode_|Equal33~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y15_N22
|
|
cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~11 (
|
|
// Equation(s):
|
|
// \z80_|execute_|pc_inc_hold~11_combout = (\z80_|execute_|ctl_alu_op_low~22_combout & ((\z80_|pla_decode_|Equal6~1_combout ) # ((\z80_|execute_|ctl_mRead~8_combout )))) # (!\z80_|execute_|ctl_alu_op_low~22_combout & (\z80_|execute_|ixy_d~5_combout &
|
|
// ((\z80_|pla_decode_|Equal6~1_combout ) # (\z80_|execute_|ctl_mRead~8_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op_low~22_combout ),
|
|
.datab(\z80_|pla_decode_|Equal6~1_combout ),
|
|
.datac(\z80_|execute_|ctl_mRead~8_combout ),
|
|
.datad(\z80_|execute_|ixy_d~5_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|pc_inc_hold~11_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|pc_inc_hold~11 .lut_mask = 16'hFCA8;
|
|
defparam \z80_|execute_|pc_inc_hold~11 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y11_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout = (\z80_|decode_state_|use_ixiy~combout & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & \z80_|pla_decode_|Equal33~2_combout )))
|
|
|
|
.dataa(\z80_|decode_state_|use_ixiy~combout ),
|
|
.datab(\z80_|sequencer_|DFFE_M3_ff~q ),
|
|
.datac(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.datad(\z80_|pla_decode_|Equal33~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y12_N6
|
|
cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~9 (
|
|
// Equation(s):
|
|
// \z80_|execute_|pc_inc_hold~9_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ) # ((\z80_|execute_|ctl_alu_op_low~22_combout & ((\z80_|execute_|ctl_mRead~12_combout ) # (!\z80_|execute_|pc_inc_hold~6_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_sys_hilo_pla40M3T2_4~0_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_op_low~22_combout ),
|
|
.datac(\z80_|execute_|ctl_mRead~12_combout ),
|
|
.datad(\z80_|execute_|pc_inc_hold~6_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|pc_inc_hold~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|pc_inc_hold~9 .lut_mask = 16'hEAEE;
|
|
defparam \z80_|execute_|pc_inc_hold~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y13_N12
|
|
cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~12 (
|
|
// Equation(s):
|
|
// \z80_|execute_|pc_inc_hold~12_combout = (\z80_|execute_|pc_inc_hold~10_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ) # ((\z80_|execute_|pc_inc_hold~11_combout ) # (\z80_|execute_|pc_inc_hold~9_combout )))
|
|
|
|
.dataa(\z80_|execute_|pc_inc_hold~10_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ),
|
|
.datac(\z80_|execute_|pc_inc_hold~11_combout ),
|
|
.datad(\z80_|execute_|pc_inc_hold~9_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|pc_inc_hold~12_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|pc_inc_hold~12 .lut_mask = 16'hFFFE;
|
|
defparam \z80_|execute_|pc_inc_hold~12 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y16_N24
|
|
cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~7 (
|
|
// Equation(s):
|
|
// \z80_|execute_|pc_inc_hold~7_combout = ((\z80_|pla_decode_|Equal12~1_combout ) # ((!\z80_|execute_|ctl_alu_op_low~22_combout & !\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|pla_decode_|Equal25~0_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op_low~22_combout ),
|
|
.datab(\z80_|pla_decode_|Equal25~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal12~1_combout ),
|
|
.datad(\z80_|execute_|ixy_d~5_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|pc_inc_hold~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|pc_inc_hold~7 .lut_mask = 16'hF3F7;
|
|
defparam \z80_|execute_|pc_inc_hold~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y14_N8
|
|
cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~8 (
|
|
// Equation(s):
|
|
// \z80_|execute_|pc_inc_hold~8_combout = (((!\z80_|sequencer_|DFFE_M2_ff~q & !\z80_|sequencer_|DFFE_M3_ff~q )) # (!\z80_|execute_|ctl_mRead~15_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q )
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.datab(\z80_|sequencer_|DFFE_M2_ff~q ),
|
|
.datac(\z80_|execute_|ctl_mRead~15_combout ),
|
|
.datad(\z80_|sequencer_|DFFE_M3_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|pc_inc_hold~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|pc_inc_hold~8 .lut_mask = 16'h5F7F;
|
|
defparam \z80_|execute_|pc_inc_hold~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y14_N22
|
|
cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~13 (
|
|
// Equation(s):
|
|
// \z80_|execute_|pc_inc_hold~13_combout = (\z80_|execute_|ctl_mRead~6_combout & (\z80_|sequencer_|DFFE_T2_ff~q & ((\z80_|sequencer_|DFFE_M2_ff~q ) # (\z80_|sequencer_|DFFE_M3_ff~q ))))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_M2_ff~q ),
|
|
.datab(\z80_|sequencer_|DFFE_M3_ff~q ),
|
|
.datac(\z80_|execute_|ctl_mRead~6_combout ),
|
|
.datad(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|pc_inc_hold~13_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|pc_inc_hold~13 .lut_mask = 16'hE000;
|
|
defparam \z80_|execute_|pc_inc_hold~13 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y14_N14
|
|
cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~14 (
|
|
// Equation(s):
|
|
// \z80_|execute_|pc_inc_hold~14_combout = (!\z80_|execute_|pc_inc_hold~12_combout & (\z80_|execute_|pc_inc_hold~7_combout & (\z80_|execute_|pc_inc_hold~8_combout & !\z80_|execute_|pc_inc_hold~13_combout )))
|
|
|
|
.dataa(\z80_|execute_|pc_inc_hold~12_combout ),
|
|
.datab(\z80_|execute_|pc_inc_hold~7_combout ),
|
|
.datac(\z80_|execute_|pc_inc_hold~8_combout ),
|
|
.datad(\z80_|execute_|pc_inc_hold~13_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|pc_inc_hold~14_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|pc_inc_hold~14 .lut_mask = 16'h0040;
|
|
defparam \z80_|execute_|pc_inc_hold~14 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y14_N24
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|decode_state_|use_ixiy~combout & (\z80_|pla_decode_|Equal45~0_combout & \z80_|sequencer_|DFFE_T2_ff~q )))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_M2_ff~q ),
|
|
.datab(\z80_|decode_state_|use_ixiy~combout ),
|
|
.datac(\z80_|pla_decode_|Equal45~0_combout ),
|
|
.datad(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y14_N16
|
|
cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~16 (
|
|
// Equation(s):
|
|
// \z80_|execute_|pc_inc_hold~16_combout = (!\z80_|execute_|pc_inc_hold~15_combout & (!\z80_|execute_|pc_inc_hold~27_combout & (\z80_|execute_|pc_inc_hold~14_combout & !\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout )))
|
|
|
|
.dataa(\z80_|execute_|pc_inc_hold~15_combout ),
|
|
.datab(\z80_|execute_|pc_inc_hold~27_combout ),
|
|
.datac(\z80_|execute_|pc_inc_hold~14_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sys_hilo_use_ixiypla53M2T2_4~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|pc_inc_hold~16_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|pc_inc_hold~16 .lut_mask = 16'h0010;
|
|
defparam \z80_|execute_|pc_inc_hold~16 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y16_N8
|
|
cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~22 (
|
|
// Equation(s):
|
|
// \z80_|execute_|pc_inc_hold~22_combout = (\z80_|execute_|ctl_mRead~34_combout & (\z80_|sequencer_|DFFE_M4_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_mRead~34_combout ),
|
|
.datab(\z80_|sequencer_|DFFE_M4_ff~q ),
|
|
.datac(\z80_|sequencer_|DFFE_T4_ff~q ),
|
|
.datad(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|pc_inc_hold~22_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|pc_inc_hold~22 .lut_mask = 16'h8880;
|
|
defparam \z80_|execute_|pc_inc_hold~22 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y16_N30
|
|
cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~23 (
|
|
// Equation(s):
|
|
// \z80_|execute_|pc_inc_hold~23_combout = (\z80_|execute_|pc_inc_hold~26_combout & (!\z80_|pla_decode_|Equal19~0_combout & ((\z80_|execute_|ctl_bus_db_oe~1_combout ) # (!\z80_|execute_|ctl_alu_op_low~22_combout ))))
|
|
|
|
.dataa(\z80_|execute_|pc_inc_hold~26_combout ),
|
|
.datab(\z80_|execute_|ctl_bus_db_oe~1_combout ),
|
|
.datac(\z80_|pla_decode_|Equal19~0_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op_low~22_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|pc_inc_hold~23_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|pc_inc_hold~23 .lut_mask = 16'h080A;
|
|
defparam \z80_|execute_|pc_inc_hold~23 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y16_N28
|
|
cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~24 (
|
|
// Equation(s):
|
|
// \z80_|execute_|pc_inc_hold~24_combout = (\z80_|execute_|pc_inc_hold~22_combout ) # ((!\z80_|execute_|pc_inc_hold~23_combout & ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ctl_alu_op_low~22_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ixy_d~5_combout ),
|
|
.datab(\z80_|execute_|pc_inc_hold~22_combout ),
|
|
.datac(\z80_|execute_|pc_inc_hold~23_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op_low~22_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|pc_inc_hold~24_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|pc_inc_hold~24 .lut_mask = 16'hCFCE;
|
|
defparam \z80_|execute_|pc_inc_hold~24 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y16_N28
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~41 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~41_combout = (((!\z80_|pla_decode_|Equal3~0_combout & !\z80_|pla_decode_|Equal21~0_combout )) # (!\z80_|pla_decode_|Equal24~0_combout )) # (!\z80_|execute_|ctl_alu_op_low~22_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op_low~22_combout ),
|
|
.datab(\z80_|pla_decode_|Equal3~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal21~0_combout ),
|
|
.datad(\z80_|pla_decode_|Equal24~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~41_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~41 .lut_mask = 16'h57FF;
|
|
defparam \z80_|execute_|ctl_inc_cy~41 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y15_N18
|
|
cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~21 (
|
|
// Equation(s):
|
|
// \z80_|execute_|pc_inc_hold~21_combout = (\z80_|execute_|ctl_mWrite~4_combout & (\z80_|pla_decode_|Equal55~0_combout & ((\z80_|execute_|ctl_alu_shift_oe~14_combout ) # (\z80_|execute_|ctl_mWrite~9_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ),
|
|
.datab(\z80_|execute_|ctl_mWrite~4_combout ),
|
|
.datac(\z80_|execute_|ctl_mWrite~9_combout ),
|
|
.datad(\z80_|pla_decode_|Equal55~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|pc_inc_hold~21_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|pc_inc_hold~21 .lut_mask = 16'hC800;
|
|
defparam \z80_|execute_|pc_inc_hold~21 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y15_N8
|
|
cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~25 (
|
|
// Equation(s):
|
|
// \z80_|execute_|pc_inc_hold~25_combout = ((\z80_|execute_|pc_inc_hold~24_combout ) # ((\z80_|execute_|pc_inc_hold~21_combout ) # (!\z80_|execute_|ctl_inc_cy~41_combout ))) # (!\z80_|execute_|pc_inc_hold~16_combout )
|
|
|
|
.dataa(\z80_|execute_|pc_inc_hold~16_combout ),
|
|
.datab(\z80_|execute_|pc_inc_hold~24_combout ),
|
|
.datac(\z80_|execute_|ctl_inc_cy~41_combout ),
|
|
.datad(\z80_|execute_|pc_inc_hold~21_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|pc_inc_hold~25_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|pc_inc_hold~25 .lut_mask = 16'hFFDF;
|
|
defparam \z80_|execute_|pc_inc_hold~25 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y15_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~69 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~69_combout = (!\z80_|execute_|pc_inc_hold~25_combout & (((!\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|pla_decode_|Equal34~0_combout )))
|
|
|
|
.dataa(\z80_|execute_|ixy_d~5_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_op_low~22_combout ),
|
|
.datac(\z80_|execute_|pc_inc_hold~25_combout ),
|
|
.datad(\z80_|pla_decode_|Equal34~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~69_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~69 .lut_mask = 16'h010F;
|
|
defparam \z80_|execute_|ctl_inc_cy~69 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y13_N8
|
|
cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~17 (
|
|
// Equation(s):
|
|
// \z80_|execute_|pc_inc_hold~17_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # ((\z80_|interrupts_|DFFE_inst44~q ) # (\z80_|decode_state_|in_halt~q ))
|
|
|
|
.dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ),
|
|
.datab(gnd),
|
|
.datac(\z80_|interrupts_|DFFE_inst44~q ),
|
|
.datad(\z80_|decode_state_|in_halt~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|pc_inc_hold~17_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|pc_inc_hold~17 .lut_mask = 16'hFFFA;
|
|
defparam \z80_|execute_|pc_inc_hold~17 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y15_N6
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~71 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~71_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (((\z80_|execute_|ctl_inc_cy~70_combout & \z80_|execute_|ctl_inc_cy~69_combout )) # (!\z80_|execute_|pc_inc_hold~17_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ),
|
|
.datab(\z80_|execute_|ctl_inc_cy~70_combout ),
|
|
.datac(\z80_|execute_|ctl_inc_cy~69_combout ),
|
|
.datad(\z80_|execute_|pc_inc_hold~17_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~71_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~71 .lut_mask = 16'h80AA;
|
|
defparam \z80_|execute_|ctl_inc_cy~71 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y15_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~44 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~44_combout = (\z80_|execute_|ctl_inc_cy~82_combout & (\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout & ((\z80_|execute_|pc_inc_hold~16_combout ) # (!\z80_|execute_|pc_inc_hold~17_combout )))) #
|
|
// (!\z80_|execute_|ctl_inc_cy~82_combout & (((\z80_|execute_|pc_inc_hold~16_combout ) # (!\z80_|execute_|pc_inc_hold~17_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_inc_cy~82_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_sel_pla9M1T5_2~combout ),
|
|
.datac(\z80_|execute_|pc_inc_hold~16_combout ),
|
|
.datad(\z80_|execute_|pc_inc_hold~17_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~44_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~44 .lut_mask = 16'hD0DD;
|
|
defparam \z80_|execute_|ctl_inc_cy~44 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y15_N2
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~42 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~42_combout = (\z80_|execute_|pc_inc_hold~16_combout & \z80_|execute_|ctl_inc_cy~41_combout )
|
|
|
|
.dataa(\z80_|execute_|pc_inc_hold~16_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_inc_cy~41_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~42_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~42 .lut_mask = 16'hA0A0;
|
|
defparam \z80_|execute_|ctl_inc_cy~42 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y15_N24
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~43 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~43_combout = (\z80_|execute_|ctl_mWrite~17_combout & (\z80_|execute_|ixy_d~5_combout & ((\z80_|execute_|ctl_inc_cy~42_combout ) # (!\z80_|execute_|pc_inc_hold~17_combout ))))
|
|
|
|
.dataa(\z80_|execute_|pc_inc_hold~17_combout ),
|
|
.datab(\z80_|execute_|ctl_inc_cy~42_combout ),
|
|
.datac(\z80_|execute_|ctl_mWrite~17_combout ),
|
|
.datad(\z80_|execute_|ixy_d~5_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~43_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~43 .lut_mask = 16'hD000;
|
|
defparam \z80_|execute_|ctl_inc_cy~43 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y14_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~57 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~57_combout = (\z80_|execute_|ctl_inc_cy~38_combout ) # ((\z80_|execute_|pc_inc_hold~17_combout & ((\z80_|execute_|pc_inc_hold~12_combout ) # (!\z80_|execute_|pc_inc_hold~7_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_inc_cy~38_combout ),
|
|
.datab(\z80_|execute_|pc_inc_hold~17_combout ),
|
|
.datac(\z80_|execute_|pc_inc_hold~7_combout ),
|
|
.datad(\z80_|execute_|pc_inc_hold~12_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~57_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~57 .lut_mask = 16'hEEAE;
|
|
defparam \z80_|execute_|ctl_inc_cy~57 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y14_N28
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~54 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~54_combout = ((!\z80_|execute_|ctl_alu_op_low~22_combout & ((!\z80_|sequencer_|DFFE_M3_ff~q ) # (!\z80_|sequencer_|DFFE_T4_ff~q )))) # (!\z80_|pla_decode_|Equal10~0_combout )
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T4_ff~q ),
|
|
.datab(\z80_|sequencer_|DFFE_M3_ff~q ),
|
|
.datac(\z80_|pla_decode_|Equal10~0_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op_low~22_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~54_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~54 .lut_mask = 16'h0F7F;
|
|
defparam \z80_|execute_|ctl_inc_cy~54 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y14_N26
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~58 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~58_combout = ((!\z80_|execute_|pc_inc_hold~27_combout & (\z80_|execute_|pc_inc_hold~14_combout & !\z80_|execute_|ctl_inc_cy~54_combout ))) # (!\z80_|execute_|ctl_inc_cy~57_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_inc_cy~57_combout ),
|
|
.datab(\z80_|execute_|pc_inc_hold~27_combout ),
|
|
.datac(\z80_|execute_|pc_inc_hold~14_combout ),
|
|
.datad(\z80_|execute_|ctl_inc_cy~54_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~58_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~58 .lut_mask = 16'h5575;
|
|
defparam \z80_|execute_|ctl_inc_cy~58 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y13_N16
|
|
cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~18 (
|
|
// Equation(s):
|
|
// \z80_|execute_|pc_inc_hold~18_combout = (\z80_|execute_|pc_inc_hold~10_combout ) # ((\z80_|execute_|pc_inc_hold~9_combout ) # ((\z80_|execute_|ixy_d~5_combout & \z80_|execute_|ctl_mRead~7_combout )))
|
|
|
|
.dataa(\z80_|execute_|ixy_d~5_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~7_combout ),
|
|
.datac(\z80_|execute_|pc_inc_hold~10_combout ),
|
|
.datad(\z80_|execute_|pc_inc_hold~9_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|pc_inc_hold~18_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|pc_inc_hold~18 .lut_mask = 16'hFFF8;
|
|
defparam \z80_|execute_|pc_inc_hold~18 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y14_N30
|
|
cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~19 (
|
|
// Equation(s):
|
|
// \z80_|execute_|pc_inc_hold~19_combout = (\z80_|execute_|pc_inc_hold~18_combout ) # ((\z80_|execute_|pc_inc_hold~13_combout ) # ((\z80_|execute_|pc_inc_hold~11_combout ) # (!\z80_|execute_|pc_inc_hold~7_combout )))
|
|
|
|
.dataa(\z80_|execute_|pc_inc_hold~18_combout ),
|
|
.datab(\z80_|execute_|pc_inc_hold~13_combout ),
|
|
.datac(\z80_|execute_|pc_inc_hold~7_combout ),
|
|
.datad(\z80_|execute_|pc_inc_hold~11_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|pc_inc_hold~19_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|pc_inc_hold~19 .lut_mask = 16'hFFEF;
|
|
defparam \z80_|execute_|pc_inc_hold~19 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y18_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~45 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~45_combout = ((\z80_|pla_decode_|Equal9~1_combout & ((\z80_|execute_|ctl_state_alu~4_combout ) # (\z80_|execute_|ixy_d~9_combout )))) # (!\z80_|execute_|ctl_inc_cy~87_combout )
|
|
|
|
.dataa(\z80_|pla_decode_|Equal9~1_combout ),
|
|
.datab(\z80_|execute_|ctl_state_alu~4_combout ),
|
|
.datac(\z80_|execute_|ctl_inc_cy~87_combout ),
|
|
.datad(\z80_|execute_|ixy_d~9_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~45_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~45 .lut_mask = 16'hAF8F;
|
|
defparam \z80_|execute_|ctl_inc_cy~45 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y15_N2
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~34 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~34_combout = ((!\z80_|execute_|ctl_alu_op_low~22_combout & (!\z80_|execute_|ctl_state_alu~2_combout & !\z80_|execute_|ixy_d~5_combout ))) # (!\z80_|execute_|ctl_mWrite~6_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op_low~22_combout ),
|
|
.datab(\z80_|execute_|ctl_mWrite~6_combout ),
|
|
.datac(\z80_|execute_|ctl_state_alu~2_combout ),
|
|
.datad(\z80_|execute_|ixy_d~5_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~34_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~34 .lut_mask = 16'h3337;
|
|
defparam \z80_|execute_|ctl_inc_cy~34 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y15_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~35 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~35_combout = (\z80_|execute_|ctl_sw_2u~0_combout & (\z80_|execute_|ctl_inc_cy~34_combout & ((!\z80_|pla_decode_|Equal11~0_combout ) # (!\z80_|execute_|ixy_d~5_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ixy_d~5_combout ),
|
|
.datab(\z80_|execute_|ctl_sw_2u~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal11~0_combout ),
|
|
.datad(\z80_|execute_|ctl_inc_cy~34_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~35_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~35 .lut_mask = 16'h4C00;
|
|
defparam \z80_|execute_|ctl_inc_cy~35 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y18_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~46 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~46_combout = (\z80_|pla_decode_|Equal11~0_combout & ((\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ctl_mWrite~6_combout & \z80_|execute_|ixy_d~7_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout &
|
|
// (\z80_|execute_|ctl_mWrite~6_combout & (\z80_|execute_|ixy_d~7_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal11~0_combout ),
|
|
.datab(\z80_|execute_|ctl_mWrite~6_combout ),
|
|
.datac(\z80_|execute_|ixy_d~7_combout ),
|
|
.datad(\z80_|execute_|ixy_d~9_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~46_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~46 .lut_mask = 16'hEAC0;
|
|
defparam \z80_|execute_|ctl_inc_cy~46 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y18_N18
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~47 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~47_combout = ((\z80_|execute_|ctl_inc_cy~46_combout ) # ((\z80_|execute_|ctl_mWrite~6_combout & \z80_|execute_|ctl_mRead~9_combout ))) # (!\z80_|execute_|ctl_inc_cy~39_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_inc_cy~39_combout ),
|
|
.datab(\z80_|execute_|ctl_mWrite~6_combout ),
|
|
.datac(\z80_|execute_|ctl_mRead~9_combout ),
|
|
.datad(\z80_|execute_|ctl_inc_cy~46_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~47_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~47 .lut_mask = 16'hFFD5;
|
|
defparam \z80_|execute_|ctl_inc_cy~47 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y18_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~48 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~48_combout = (\z80_|execute_|ctl_inc_cy~47_combout ) # ((\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ) # ((\z80_|pla_decode_|Equal11~0_combout & \z80_|execute_|ctl_alu_op_low~22_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal11~0_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_op_low~22_combout ),
|
|
.datac(\z80_|execute_|ctl_inc_cy~47_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_sel_pla10M5T1_5~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~48_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~48 .lut_mask = 16'hFFF8;
|
|
defparam \z80_|execute_|ctl_inc_cy~48 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y18_N26
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~50 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~50_combout = (\z80_|execute_|ctl_inc_cy~45_combout ) # (((\z80_|execute_|ctl_inc_cy~48_combout ) # (!\z80_|execute_|ctl_inc_cy~35_combout )) # (!\z80_|execute_|ctl_inc_cy~49_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_inc_cy~45_combout ),
|
|
.datab(\z80_|execute_|ctl_inc_cy~49_combout ),
|
|
.datac(\z80_|execute_|ctl_inc_cy~35_combout ),
|
|
.datad(\z80_|execute_|ctl_inc_cy~48_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~50_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~50 .lut_mask = 16'hFFBF;
|
|
defparam \z80_|execute_|ctl_inc_cy~50 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y14_N18
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~51 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~51_combout = (\z80_|execute_|ctl_inc_cy~50_combout & (((!\z80_|execute_|pc_inc_hold~19_combout & \z80_|execute_|pc_inc_hold~8_combout )) # (!\z80_|execute_|pc_inc_hold~17_combout )))
|
|
|
|
.dataa(\z80_|execute_|pc_inc_hold~19_combout ),
|
|
.datab(\z80_|execute_|pc_inc_hold~17_combout ),
|
|
.datac(\z80_|execute_|pc_inc_hold~8_combout ),
|
|
.datad(\z80_|execute_|ctl_inc_cy~50_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~51_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~51 .lut_mask = 16'h7300;
|
|
defparam \z80_|execute_|ctl_inc_cy~51 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y14_N6
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~85 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~85_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q )
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.datab(\z80_|sequencer_|DFFE_M4_ff~q ),
|
|
.datac(\z80_|sequencer_|M5~q ),
|
|
.datad(\z80_|execute_|ctl_mRead~6_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~85_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~85 .lut_mask = 16'h57FF;
|
|
defparam \z80_|execute_|ctl_inc_cy~85 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y13_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~63 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~63_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|interrupts_|DFFE_inst44~q & (\z80_|execute_|ctl_mRead~12_combout & !\z80_|decode_state_|in_halt~q )))
|
|
|
|
.dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ),
|
|
.datab(\z80_|interrupts_|DFFE_inst44~q ),
|
|
.datac(\z80_|execute_|ctl_mRead~12_combout ),
|
|
.datad(\z80_|decode_state_|in_halt~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~63_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~63 .lut_mask = 16'h0010;
|
|
defparam \z80_|execute_|ctl_inc_cy~63 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y13_N18
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~64 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~64_combout = (\z80_|execute_|ctl_alu_op_low~22_combout & ((\z80_|execute_|ctl_inc_cy~63_combout ) # ((!\z80_|execute_|ctl_reg_sys_hilo~21_combout & !\z80_|execute_|pc_inc_hold~9_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_sys_hilo~21_combout ),
|
|
.datab(\z80_|execute_|ctl_inc_cy~63_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_op_low~22_combout ),
|
|
.datad(\z80_|execute_|pc_inc_hold~9_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~64_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~64 .lut_mask = 16'hC0D0;
|
|
defparam \z80_|execute_|ctl_inc_cy~64 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y13_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~65 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~65_combout = (\z80_|execute_|ctl_inc_cy~64_combout ) # ((\z80_|execute_|ctl_mRead~13_combout & (\z80_|execute_|ctl_alu_shift_oe~14_combout & !\z80_|execute_|pc_inc_hold~18_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_mRead~13_combout ),
|
|
.datab(\z80_|execute_|ctl_inc_cy~64_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_shift_oe~14_combout ),
|
|
.datad(\z80_|execute_|pc_inc_hold~18_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~65_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~65 .lut_mask = 16'hCCEC;
|
|
defparam \z80_|execute_|ctl_inc_cy~65 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y13_N6
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~59 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~59_combout = (((!\z80_|pla_decode_|Equal55~0_combout ) # (!\z80_|execute_|ctl_alu_op_low~22_combout )) # (!\z80_|pla_decode_|Equal6~0_combout )) # (!\z80_|pla_decode_|Equal33~1_combout )
|
|
|
|
.dataa(\z80_|pla_decode_|Equal33~1_combout ),
|
|
.datab(\z80_|pla_decode_|Equal6~0_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_op_low~22_combout ),
|
|
.datad(\z80_|pla_decode_|Equal55~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~59_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~59 .lut_mask = 16'h7FFF;
|
|
defparam \z80_|execute_|ctl_inc_cy~59 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y13_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~60 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~60_combout = ((\z80_|execute_|ctl_inc_cy~59_combout & (!\z80_|execute_|pc_inc_hold~9_combout & !\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ))) # (!\z80_|execute_|pc_inc_hold~17_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_inc_cy~59_combout ),
|
|
.datab(\z80_|execute_|pc_inc_hold~9_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M3T2_4~combout ),
|
|
.datad(\z80_|execute_|pc_inc_hold~17_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~60_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~60 .lut_mask = 16'h02FF;
|
|
defparam \z80_|execute_|ctl_inc_cy~60 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y14_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~61 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~61_combout = (((!\z80_|sequencer_|DFFE_M4_ff~q & !\z80_|sequencer_|M5~q )) # (!\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|sequencer_|DFFE_T2_ff~q )
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.datab(\z80_|sequencer_|DFFE_M4_ff~q ),
|
|
.datac(\z80_|sequencer_|M5~q ),
|
|
.datad(\z80_|execute_|ctl_mRead~8_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~61_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~61 .lut_mask = 16'h57FF;
|
|
defparam \z80_|execute_|ctl_inc_cy~61 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y14_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~62 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~62_combout = (\z80_|execute_|pc_inc_hold~12_combout & (\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (\z80_|execute_|ctl_inc_cy~60_combout ))) # (!\z80_|execute_|pc_inc_hold~12_combout &
|
|
// (((\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & \z80_|execute_|ctl_inc_cy~60_combout )) # (!\z80_|execute_|ctl_inc_cy~61_combout )))
|
|
|
|
.dataa(\z80_|execute_|pc_inc_hold~12_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ),
|
|
.datac(\z80_|execute_|ctl_inc_cy~60_combout ),
|
|
.datad(\z80_|execute_|ctl_inc_cy~61_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~62_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~62 .lut_mask = 16'hC0D5;
|
|
defparam \z80_|execute_|ctl_inc_cy~62 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y14_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~66 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~66_combout = (\z80_|execute_|ctl_inc_cy~65_combout ) # ((\z80_|execute_|ctl_inc_cy~62_combout ) # ((!\z80_|execute_|ctl_inc_cy~85_combout & !\z80_|execute_|pc_inc_hold~19_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_inc_cy~85_combout ),
|
|
.datab(\z80_|execute_|ctl_inc_cy~65_combout ),
|
|
.datac(\z80_|execute_|pc_inc_hold~19_combout ),
|
|
.datad(\z80_|execute_|ctl_inc_cy~62_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~66_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~66 .lut_mask = 16'hFFCD;
|
|
defparam \z80_|execute_|ctl_inc_cy~66 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y16_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~53 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~53_combout = ((\z80_|execute_|ixy_d~5_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~33_combout )))) # (!\z80_|execute_|ctl_reg_sel_pc~7_combout )
|
|
|
|
.dataa(\z80_|execute_|ixy_d~5_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_sel_pc~7_combout ),
|
|
.datac(\z80_|execute_|ctl_bus_inc_oe~33_combout ),
|
|
.datad(\z80_|pla_decode_|Equal41~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~53_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~53 .lut_mask = 16'hBB3B;
|
|
defparam \z80_|execute_|ctl_inc_cy~53 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y12_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~52 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~52_combout = (\z80_|execute_|ctl_mRead~2_combout ) # ((\z80_|execute_|ctl_mWrite~8_combout ) # ((\z80_|pla_decode_|Equal34~0_combout ) # (!\z80_|execute_|ctl_reg_sel_wz~8_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_mRead~2_combout ),
|
|
.datab(\z80_|execute_|ctl_mWrite~8_combout ),
|
|
.datac(\z80_|pla_decode_|Equal34~0_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sel_wz~8_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~52_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~52 .lut_mask = 16'hFEFF;
|
|
defparam \z80_|execute_|ctl_inc_cy~52 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y12_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~84 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~84_combout = (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T2_ff~q & ((\z80_|execute_|ctl_inc_cy~52_combout ) # (!\z80_|execute_|fMRead~7_combout ))))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_M2_ff~q ),
|
|
.datab(\z80_|execute_|ctl_inc_cy~52_combout ),
|
|
.datac(\z80_|execute_|fMRead~7_combout ),
|
|
.datad(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~84_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~84 .lut_mask = 16'h8A00;
|
|
defparam \z80_|execute_|ctl_inc_cy~84 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y14_N28
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|pla_decode_|Equal8~0_combout & \z80_|execute_|ctl_mWrite~4_combout )))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.datab(\z80_|sequencer_|DFFE_M2_ff~q ),
|
|
.datac(\z80_|pla_decode_|Equal8~0_combout ),
|
|
.datad(\z80_|execute_|ctl_mWrite~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y14_N24
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~55 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~55_combout = ((\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ) # ((!\z80_|execute_|ctl_inc_cy~54_combout ) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ))) # (!\z80_|execute_|ctl_reg_sys_we~2_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_sys_we~2_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ),
|
|
.datac(\z80_|execute_|ctl_reg_sys_hilo[1]~15_combout ),
|
|
.datad(\z80_|execute_|ctl_inc_cy~54_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~55_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~55 .lut_mask = 16'hDFFF;
|
|
defparam \z80_|execute_|ctl_inc_cy~55 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y14_N2
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~56 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~56_combout = (!\z80_|execute_|pc_inc_hold~17_combout & ((\z80_|execute_|ctl_inc_cy~53_combout ) # ((\z80_|execute_|ctl_inc_cy~84_combout ) # (\z80_|execute_|ctl_inc_cy~55_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_inc_cy~53_combout ),
|
|
.datab(\z80_|execute_|ctl_inc_cy~84_combout ),
|
|
.datac(\z80_|execute_|pc_inc_hold~17_combout ),
|
|
.datad(\z80_|execute_|ctl_inc_cy~55_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~56_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~56 .lut_mask = 16'h0F0E;
|
|
defparam \z80_|execute_|ctl_inc_cy~56 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y14_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~67 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~67_combout = (\z80_|execute_|ctl_inc_cy~58_combout ) # ((\z80_|execute_|ctl_inc_cy~51_combout ) # ((\z80_|execute_|ctl_inc_cy~66_combout ) # (\z80_|execute_|ctl_inc_cy~56_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_inc_cy~58_combout ),
|
|
.datab(\z80_|execute_|ctl_inc_cy~51_combout ),
|
|
.datac(\z80_|execute_|ctl_inc_cy~66_combout ),
|
|
.datad(\z80_|execute_|ctl_inc_cy~56_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~67_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~67 .lut_mask = 16'hFFFE;
|
|
defparam \z80_|execute_|ctl_inc_cy~67 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y14_N20
|
|
cycloneive_lcell_comb \z80_|execute_|pc_inc_hold~20 (
|
|
// Equation(s):
|
|
// \z80_|execute_|pc_inc_hold~20_combout = (\z80_|execute_|pc_inc_hold~19_combout ) # ((\z80_|execute_|pc_inc_hold~27_combout ) # ((\z80_|execute_|pc_inc_hold~15_combout ) # (!\z80_|execute_|pc_inc_hold~8_combout )))
|
|
|
|
.dataa(\z80_|execute_|pc_inc_hold~19_combout ),
|
|
.datab(\z80_|execute_|pc_inc_hold~27_combout ),
|
|
.datac(\z80_|execute_|pc_inc_hold~8_combout ),
|
|
.datad(\z80_|execute_|pc_inc_hold~15_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|pc_inc_hold~20_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|pc_inc_hold~20 .lut_mask = 16'hFFEF;
|
|
defparam \z80_|execute_|pc_inc_hold~20 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y15_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~83 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~83_combout = (\z80_|execute_|ctl_state_alu~6_combout & (\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|execute_|pc_inc_hold~20_combout & \z80_|sequencer_|DFFE_T2_ff~q )))
|
|
|
|
.dataa(\z80_|execute_|ctl_state_alu~6_combout ),
|
|
.datab(\z80_|sequencer_|DFFE_M2_ff~q ),
|
|
.datac(\z80_|execute_|pc_inc_hold~20_combout ),
|
|
.datad(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~83_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~83 .lut_mask = 16'h0800;
|
|
defparam \z80_|execute_|ctl_inc_cy~83 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y15_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~68 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~68_combout = (\z80_|execute_|ctl_inc_cy~44_combout ) # ((\z80_|execute_|ctl_inc_cy~43_combout ) # ((\z80_|execute_|ctl_inc_cy~67_combout ) # (\z80_|execute_|ctl_inc_cy~83_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_inc_cy~44_combout ),
|
|
.datab(\z80_|execute_|ctl_inc_cy~43_combout ),
|
|
.datac(\z80_|execute_|ctl_inc_cy~67_combout ),
|
|
.datad(\z80_|execute_|ctl_inc_cy~83_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~68_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~68 .lut_mask = 16'hFFFE;
|
|
defparam \z80_|execute_|ctl_inc_cy~68 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y11_N30
|
|
cycloneive_lcell_comb \z80_|address_latch_|Q[0]~feeder (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|Q[0]~feeder_combout = \z80_|address_latch_|abusz [0]
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|address_latch_|abusz [0]),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|Q[0]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|Q[0]~feeder .lut_mask = 16'hFF00;
|
|
defparam \z80_|address_latch_|Q[0]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y11_N31
|
|
dffeas \z80_|address_latch_|Q[0] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|address_latch_|Q[0]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|execute_|ctl_al_we~12_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|address_latch_|Q [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|Q[0] .is_wysiwyg = "true";
|
|
defparam \z80_|address_latch_|Q[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y15_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~72 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~72_combout = (\z80_|execute_|pc_inc_hold~16_combout & (\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout & (\z80_|execute_|ctl_inc_cy~41_combout & !\z80_|execute_|pc_inc_hold~21_combout )))
|
|
|
|
.dataa(\z80_|execute_|pc_inc_hold~16_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_sel_pla91pla20M2T2_3~combout ),
|
|
.datac(\z80_|execute_|ctl_inc_cy~41_combout ),
|
|
.datad(\z80_|execute_|pc_inc_hold~21_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~72_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~72 .lut_mask = 16'h0080;
|
|
defparam \z80_|execute_|ctl_inc_cy~72 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y18_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~73 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~73_combout = (\z80_|execute_|ixy_d~9_combout ) # ((\z80_|execute_|ctl_alu_oe~0_combout ) # ((\z80_|sequencer_|DFFE_M4_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_M4_ff~q ),
|
|
.datab(\z80_|execute_|ixy_d~9_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_oe~0_combout ),
|
|
.datad(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~73_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~73 .lut_mask = 16'hFEFC;
|
|
defparam \z80_|execute_|ctl_inc_cy~73 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y18_N2
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~74 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~74_combout = ((\z80_|pla_decode_|Equal19~0_combout & ((\z80_|execute_|ctl_ir_we~4_combout ) # (\z80_|execute_|ctl_inc_cy~73_combout )))) # (!\z80_|execute_|ctl_inc_cy~86_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_inc_cy~86_combout ),
|
|
.datab(\z80_|pla_decode_|Equal19~0_combout ),
|
|
.datac(\z80_|execute_|ctl_ir_we~4_combout ),
|
|
.datad(\z80_|execute_|ctl_inc_cy~73_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~74_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~74 .lut_mask = 16'hDDD5;
|
|
defparam \z80_|execute_|ctl_inc_cy~74 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y15_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~75 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~75_combout = (\z80_|execute_|ctl_inc_cy~72_combout ) # ((\z80_|execute_|ctl_inc_cy~74_combout & ((!\z80_|execute_|pc_inc_hold~17_combout ) # (!\z80_|execute_|pc_inc_hold~25_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_inc_cy~72_combout ),
|
|
.datab(\z80_|execute_|pc_inc_hold~25_combout ),
|
|
.datac(\z80_|execute_|ctl_inc_cy~74_combout ),
|
|
.datad(\z80_|execute_|pc_inc_hold~17_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~75_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~75 .lut_mask = 16'hBAFA;
|
|
defparam \z80_|execute_|ctl_inc_cy~75 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y18_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~76 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~76_combout = (((!\z80_|execute_|ctl_inc_cy~40_combout ) # (!\z80_|execute_|ctl_inc_cy~37_combout )) # (!\z80_|execute_|ctl_inc_cy~33_combout )) # (!\z80_|execute_|ctl_inc_cy~32_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_inc_cy~32_combout ),
|
|
.datab(\z80_|execute_|ctl_inc_cy~33_combout ),
|
|
.datac(\z80_|execute_|ctl_inc_cy~37_combout ),
|
|
.datad(\z80_|execute_|ctl_inc_cy~40_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~76_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~76 .lut_mask = 16'h7FFF;
|
|
defparam \z80_|execute_|ctl_inc_cy~76 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y18_N18
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~80 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~80_combout = (\z80_|execute_|ctl_inc_cy~76_combout ) # ((!\z80_|execute_|ctl_inc_cy~36_combout ) # (!\z80_|execute_|ctl_inc_cy~79_combout ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|execute_|ctl_inc_cy~76_combout ),
|
|
.datac(\z80_|execute_|ctl_inc_cy~79_combout ),
|
|
.datad(\z80_|execute_|ctl_inc_cy~36_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~80_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~80 .lut_mask = 16'hCFFF;
|
|
defparam \z80_|execute_|ctl_inc_cy~80 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y15_N16
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~81 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~81_combout = (\z80_|execute_|ctl_inc_cy~75_combout ) # ((\z80_|execute_|ctl_inc_cy~80_combout & ((\z80_|execute_|ctl_inc_cy~69_combout ) # (!\z80_|execute_|pc_inc_hold~17_combout ))))
|
|
|
|
.dataa(\z80_|execute_|pc_inc_hold~17_combout ),
|
|
.datab(\z80_|execute_|ctl_inc_cy~69_combout ),
|
|
.datac(\z80_|execute_|ctl_inc_cy~75_combout ),
|
|
.datad(\z80_|execute_|ctl_inc_cy~80_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~81_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~81 .lut_mask = 16'hFDF0;
|
|
defparam \z80_|execute_|ctl_inc_cy~81 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y11_N20
|
|
cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout = \z80_|address_latch_|Q [0] $ (((\z80_|execute_|ctl_inc_cy~71_combout ) # ((\z80_|execute_|ctl_inc_cy~68_combout ) # (\z80_|execute_|ctl_inc_cy~81_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_inc_cy~71_combout ),
|
|
.datab(\z80_|execute_|ctl_inc_cy~68_combout ),
|
|
.datac(\z80_|address_latch_|Q [0]),
|
|
.datad(\z80_|execute_|ctl_inc_cy~81_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .lut_mask = 16'h0F1E;
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y12_N10
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[0]~3 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_lo_as[0]~3_combout = ((\z80_|reg_file_|db_lo_as[0]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ),
|
|
.datab(\z80_|reg_file_|db_lo_as[0]~1_combout ),
|
|
.datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ),
|
|
.datad(\z80_|reg_file_|db_lo_as[0]~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_lo_as[0]~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_lo_as[0]~3 .lut_mask = 16'hC4FF;
|
|
defparam \z80_|reg_file_|db_lo_as[0]~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y11_N1
|
|
dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[0] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y11_N10
|
|
cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[0]~feeder (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|b2v_latch_af_lo|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp0[0]~22_combout
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|reg_file_|gdfx_temp0[0]~22_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|b2v_latch_af_lo|latch[0]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0]~feeder .lut_mask = 16'hFF00;
|
|
defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y11_N11
|
|
dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[0] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_file_|b2v_latch_af_lo|latch[0]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_af_lo|latch [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_af_lo|latch[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y11_N0
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~13 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[0]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [0]),
|
|
.datad(\z80_|reg_file_|b2v_latch_af_lo|latch [0]),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[0]~13_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[0]~13 .lut_mask = 16'hF531;
|
|
defparam \z80_|reg_file_|gdfx_temp0[0]~13 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y14_N9
|
|
dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y14_N8
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~12 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[0]~12_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [0] & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|alu_control_|db[0]~12_combout ) # ((!\z80_|execute_|ctl_reg_in_lo~8_combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ),
|
|
.datab(\z80_|alu_control_|db[0]~12_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [0]),
|
|
.datad(\z80_|execute_|ctl_reg_in_lo~8_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[0]~12_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[0]~12 .lut_mask = 16'hC4F5;
|
|
defparam \z80_|reg_file_|gdfx_temp0[0]~12 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y11_N8
|
|
cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_lo|latch[0]~feeder (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|b2v_latch_de_lo|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp0[0]~22_combout
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|reg_file_|gdfx_temp0[0]~22_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|b2v_latch_de_lo|latch[0]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0]~feeder .lut_mask = 16'hFF00;
|
|
defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X30_Y11_N9
|
|
dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[0] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_file_|b2v_latch_de_lo|latch[0]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_de_lo|latch [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_de_lo|latch[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X30_Y11_N27
|
|
dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[0] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y11_N26
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~10 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[0]~10_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [0] &
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [0]),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [0]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[0]~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[0]~10 .lut_mask = 16'hB0BB;
|
|
defparam \z80_|reg_file_|gdfx_temp0[0]~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X30_Y12_N3
|
|
dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y12_N2
|
|
cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout = ((\z80_|execute_|ctl_reg_gp_we~8_combout ) # ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]) # (!\z80_|reg_control_|reg_sel_hl2~0_combout ))) # (!\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_hilo[0]~35_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_we~8_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [0]),
|
|
.datad(\z80_|reg_control_|reg_sel_hl2~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 .lut_mask = 16'hFDFF;
|
|
defparam \z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X30_Y12_N9
|
|
dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[0] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y12_N8
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~11 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[0]~11_combout = (\z80_|reg_file_|gdfx_temp0[0]~10_combout & (\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout & ((\z80_|reg_file_|b2v_latch_hl_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|gdfx_temp0[0]~10_combout ),
|
|
.datab(\z80_|reg_file_|b2v_latch_hl2_lo|db[0]~0_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_hl_lo|latch [0]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[0]~11_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[0]~11 .lut_mask = 16'h8088;
|
|
defparam \z80_|reg_file_|gdfx_temp0[0]~11 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y14_N2
|
|
cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp0[0]~22_combout
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|reg_file_|gdfx_temp0[0]~22_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder .lut_mask = 16'hFF00;
|
|
defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y14_N3
|
|
dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[0] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_file_|b2v_latch_bc_lo|latch[0]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y13_N13
|
|
dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[0] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y13_N12
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~14 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[0]~14_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [0] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [0]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ),
|
|
.datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [0]),
|
|
.datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [0]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[0]~14_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[0]~14 .lut_mask = 16'hC4F5;
|
|
defparam \z80_|reg_file_|gdfx_temp0[0]~14 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y13_N11
|
|
dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[0] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y12_N20
|
|
cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_sp_lo|latch[0]~feeder (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|b2v_latch_sp_lo|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp0[0]~22_combout
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|reg_file_|gdfx_temp0[0]~22_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|b2v_latch_sp_lo|latch[0]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0]~feeder .lut_mask = 16'hFF00;
|
|
defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y12_N21
|
|
dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[0] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_file_|b2v_latch_sp_lo|latch[0]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X31_Y12_N17
|
|
dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[0] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[0]~22_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y12_N16
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~15 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[0]~15_combout = (\z80_|reg_file_|b2v_latch_sp_lo|latch [0] & (((\z80_|reg_file_|b2v_latch_iy_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) # (!\z80_|reg_file_|b2v_latch_sp_lo|latch [0] &
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|b2v_latch_sp_lo|latch [0]),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_iy_lo|latch [0]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[0]~15_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[0]~15 .lut_mask = 16'hB0BB;
|
|
defparam \z80_|reg_file_|gdfx_temp0[0]~15 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y13_N10
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~16 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[0]~16_combout = (\z80_|reg_file_|gdfx_temp0[0]~14_combout & (\z80_|reg_file_|gdfx_temp0[0]~15_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|gdfx_temp0[0]~14_combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [0]),
|
|
.datad(\z80_|reg_file_|gdfx_temp0[0]~15_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[0]~16_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[0]~16 .lut_mask = 16'hA200;
|
|
defparam \z80_|reg_file_|gdfx_temp0[0]~16 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y13_N24
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~17 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[0]~17_combout = (\z80_|reg_file_|gdfx_temp0[0]~13_combout & (\z80_|reg_file_|gdfx_temp0[0]~12_combout & (\z80_|reg_file_|gdfx_temp0[0]~11_combout & \z80_|reg_file_|gdfx_temp0[0]~16_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|gdfx_temp0[0]~13_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp0[0]~12_combout ),
|
|
.datac(\z80_|reg_file_|gdfx_temp0[0]~11_combout ),
|
|
.datad(\z80_|reg_file_|gdfx_temp0[0]~16_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[0]~17_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[0]~17 .lut_mask = 16'h8000;
|
|
defparam \z80_|reg_file_|gdfx_temp0[0]~17 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y12_N16
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[0]~22 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[0]~22_combout = ((\z80_|reg_file_|gdfx_temp0[0]~17_combout & ((\z80_|reg_file_|db_lo_as[0]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_sw_4u~6_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ),
|
|
.datac(\z80_|reg_file_|db_lo_as[0]~3_combout ),
|
|
.datad(\z80_|reg_file_|gdfx_temp0[0]~17_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[0]~22_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[0]~22 .lut_mask = 16'hF733;
|
|
defparam \z80_|reg_file_|gdfx_temp0[0]~22 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y14_N22
|
|
cycloneive_lcell_comb \z80_|alu_control_|db[0]~9 (
|
|
// Equation(s):
|
|
// \z80_|alu_control_|db[0]~9_combout = (\z80_|sw2_|db_up[0]~0_combout & (\z80_|alu_control_|db[0]~8_combout & ((\z80_|reg_file_|gdfx_temp0[0]~22_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout ))))
|
|
|
|
.dataa(\z80_|sw2_|db_up[0]~0_combout ),
|
|
.datab(\z80_|alu_control_|db[0]~8_combout ),
|
|
.datac(\z80_|reg_file_|gdfx_temp0[0]~22_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_out_lo~8_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_control_|db[0]~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_control_|db[0]~9 .lut_mask = 16'h8088;
|
|
defparam \z80_|alu_control_|db[0]~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y14_N0
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|
cycloneive_lcell_comb \z80_|alu_control_|db[0]~12 (
|
|
// Equation(s):
|
|
// \z80_|alu_control_|db[0]~12_combout = ((\z80_|alu_control_|db[0]~9_combout & ((\z80_|alu_flags_|flags_cf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_control_|db[6]~11_combout )
|
|
|
|
.dataa(\z80_|alu_flags_|flags_cf~combout ),
|
|
.datab(\z80_|execute_|ctl_flags_oe~2_combout ),
|
|
.datac(\z80_|alu_control_|db[0]~9_combout ),
|
|
.datad(\z80_|alu_control_|db[6]~11_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_control_|db[0]~12_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_control_|db[0]~12 .lut_mask = 16'hB0FF;
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|
defparam \z80_|alu_control_|db[0]~12 .sum_lutc_input = "datac";
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|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y10_N2
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|
cycloneive_lcell_comb \z80_|address_latch_|abusz[8] (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|abusz [8] = (\z80_|reg_file_|db_hi_as[0]~6_combout & !\z80_|resets_|clrpc~0_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|reg_file_|db_hi_as[0]~6_combout ),
|
|
.datad(\z80_|resets_|clrpc~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|abusz [8]),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|abusz[8] .lut_mask = 16'h00F0;
|
|
defparam \z80_|address_latch_|abusz[8] .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y10_N3
|
|
dffeas \z80_|address_latch_|Q[8] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|address_latch_|abusz [8]),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|execute_|ctl_al_we~12_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|address_latch_|Q [8]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|Q[8] .is_wysiwyg = "true";
|
|
defparam \z80_|address_latch_|Q[8] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y13_N4
|
|
cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout = \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout $ (\z80_|address_latch_|Q [7])
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ),
|
|
.datad(\z80_|address_latch_|Q [7]),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .lut_mask = 16'h0FF0;
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X29_Y12_N21
|
|
dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[7] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[7] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X29_Y12_N11
|
|
dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[7] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y12_N10
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~84 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[7]~84_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (\z80_|reg_file_|b2v_latch_hl_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ),
|
|
.datab(\z80_|reg_file_|b2v_latch_hl_lo|latch [7]),
|
|
.datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [7]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[7]~84_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[7]~84 .lut_mask = 16'hD0DD;
|
|
defparam \z80_|reg_file_|gdfx_temp0[7]~84 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y11_N20
|
|
cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder_combout = \z80_|reg_file_|gdfx_temp0[7]~91_combout
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|reg_file_|gdfx_temp0[7]~91_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder .lut_mask = 16'hFF00;
|
|
defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X30_Y11_N21
|
|
dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[7] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_file_|b2v_latch_de_lo|latch[7]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_de_lo|latch [7]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_de_lo|latch[7] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X30_Y11_N7
|
|
dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[7] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[7] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y11_N6
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~83 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[7]~83_combout = (\z80_|reg_file_|b2v_latch_de_lo|latch [7] & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) # (!\z80_|reg_file_|b2v_latch_de_lo|latch [7] &
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|b2v_latch_de_lo|latch [7]),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [7]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[7]~83_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[7]~83 .lut_mask = 16'hB0BB;
|
|
defparam \z80_|reg_file_|gdfx_temp0[7]~83 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y12_N29
|
|
dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[7] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[7] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y12_N28
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~88 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[7]~88_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [7] & ((\z80_|alu_control_|db[7]~19_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|alu_control_|db[7]~19_combout ) # ((!\z80_|execute_|ctl_reg_in_lo~8_combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ),
|
|
.datab(\z80_|alu_control_|db[7]~19_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [7]),
|
|
.datad(\z80_|execute_|ctl_reg_in_lo~8_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[7]~88_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[7]~88 .lut_mask = 16'hC4F5;
|
|
defparam \z80_|reg_file_|gdfx_temp0[7]~88 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y14_N25
|
|
dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[7] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[7] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y14_N23
|
|
dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[7] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y14_N22
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~86 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[7]~86_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ),
|
|
.datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [7]),
|
|
.datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [7]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[7]~86_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[7]~86 .lut_mask = 16'hC4F5;
|
|
defparam \z80_|reg_file_|gdfx_temp0[7]~86 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X31_Y12_N25
|
|
dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[7] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[7] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X31_Y12_N27
|
|
dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[7] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[7] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y12_N26
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~87 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[7]~87_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [7]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ),
|
|
.datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [7]),
|
|
.datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [7]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[7]~87_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[7]~87 .lut_mask = 16'hC4F5;
|
|
defparam \z80_|reg_file_|gdfx_temp0[7]~87 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y12_N29
|
|
dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[7] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[7] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y12_N28
|
|
cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_wz_lo|db[7]~0 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|b2v_latch_wz_lo|db[7]~0_combout = (\z80_|reg_control_|reg_sys_we_lo~combout ) # (((\z80_|reg_file_|b2v_latch_wz_lo|latch [7]) # (!\z80_|execute_|ctl_reg_sel_wz~18_combout )) # (!\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ))
|
|
|
|
.dataa(\z80_|reg_control_|reg_sys_we_lo~combout ),
|
|
.datab(\z80_|execute_|ctl_reg_sys_hilo[0]~31_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [7]),
|
|
.datad(\z80_|execute_|ctl_reg_sel_wz~18_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|b2v_latch_wz_lo|db[7]~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_wz_lo|db[7]~0 .lut_mask = 16'hFBFF;
|
|
defparam \z80_|reg_file_|b2v_latch_wz_lo|db[7]~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y12_N18
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~89 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[7]~89_combout = (\z80_|reg_file_|gdfx_temp0[7]~88_combout & (\z80_|reg_file_|gdfx_temp0[7]~86_combout & (\z80_|reg_file_|gdfx_temp0[7]~87_combout & \z80_|reg_file_|b2v_latch_wz_lo|db[7]~0_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|gdfx_temp0[7]~88_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp0[7]~86_combout ),
|
|
.datac(\z80_|reg_file_|gdfx_temp0[7]~87_combout ),
|
|
.datad(\z80_|reg_file_|b2v_latch_wz_lo|db[7]~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[7]~89_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[7]~89 .lut_mask = 16'h8000;
|
|
defparam \z80_|reg_file_|gdfx_temp0[7]~89 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y11_N29
|
|
dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[7] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[7] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y11_N7
|
|
dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[7] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[7]~91_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_af_lo|latch [7]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_af_lo|latch[7] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y11_N28
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~85 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[7]~85_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [7] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [7]),
|
|
.datad(\z80_|reg_file_|b2v_latch_af_lo|latch [7]),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[7]~85_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[7]~85 .lut_mask = 16'hF531;
|
|
defparam \z80_|reg_file_|gdfx_temp0[7]~85 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y12_N24
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~90 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[7]~90_combout = (\z80_|reg_file_|gdfx_temp0[7]~84_combout & (\z80_|reg_file_|gdfx_temp0[7]~83_combout & (\z80_|reg_file_|gdfx_temp0[7]~89_combout & \z80_|reg_file_|gdfx_temp0[7]~85_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|gdfx_temp0[7]~84_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp0[7]~83_combout ),
|
|
.datac(\z80_|reg_file_|gdfx_temp0[7]~89_combout ),
|
|
.datad(\z80_|reg_file_|gdfx_temp0[7]~85_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[7]~90_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[7]~90 .lut_mask = 16'h8000;
|
|
defparam \z80_|reg_file_|gdfx_temp0[7]~90 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y12_N14
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[7]~91 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[7]~91_combout = ((\z80_|reg_file_|gdfx_temp0[7]~90_combout & ((\z80_|reg_file_|db_lo_as[7]~24_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout )
|
|
|
|
.dataa(\z80_|reg_file_|gdfx_temp0[7]~90_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp0[0]~21_combout ),
|
|
.datac(\z80_|execute_|ctl_sw_4u~6_combout ),
|
|
.datad(\z80_|reg_file_|db_lo_as[7]~24_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[7]~91_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[7]~91 .lut_mask = 16'hBB3B;
|
|
defparam \z80_|reg_file_|gdfx_temp0[7]~91 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y12_N15
|
|
dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[7] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|db_lo_as[7]~24_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[7] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y12_N14
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~22 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_lo_as[7]~22_combout = (\z80_|reg_file_|gdfx_temp0[7]~91_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [7])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))) # (!\z80_|reg_file_|gdfx_temp0[7]~91_combout &
|
|
// (!\z80_|execute_|ctl_sw_4d~6_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|gdfx_temp0[7]~91_combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [7]),
|
|
.datad(\z80_|execute_|ctl_sw_4d~6_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_lo_as[7]~22_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_lo_as[7]~22 .lut_mask = 16'hA2F3;
|
|
defparam \z80_|reg_file_|db_lo_as[7]~22 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X36_Y12_N13
|
|
dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[7] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_file_|db_lo_as[7]~24_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[7] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y12_N18
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~23 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_lo_as[7]~23_combout = (\z80_|reg_file_|db_lo_as[7]~22_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [7]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout )))
|
|
|
|
.dataa(\z80_|reg_file_|db_lo_as[7]~22_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ),
|
|
.datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [7]),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_lo_as[7]~23_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_lo_as[7]~23 .lut_mask = 16'hAA0A;
|
|
defparam \z80_|reg_file_|db_lo_as[7]~23 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y12_N12
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[7]~24 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_lo_as[7]~24_combout = ((\z80_|reg_file_|db_lo_as[7]~23_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout )
|
|
|
|
.dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ),
|
|
.datab(\z80_|reg_file_|db_lo_as[7]~23_combout ),
|
|
.datac(\z80_|reg_file_|db_lo_as[0]~2_combout ),
|
|
.datad(\z80_|execute_|ctl_bus_inc_oe~43_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_lo_as[7]~24_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_lo_as[7]~24 .lut_mask = 16'h8FCF;
|
|
defparam \z80_|reg_file_|db_lo_as[7]~24 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y13_N6
|
|
cycloneive_lcell_comb \z80_|address_latch_|abusz[7] (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|abusz [7] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[7]~24_combout )
|
|
|
|
.dataa(\z80_|resets_|clrpc~0_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|reg_file_|db_lo_as[7]~24_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|abusz [7]),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|abusz[7] .lut_mask = 16'h5050;
|
|
defparam \z80_|address_latch_|abusz[7] .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y13_N16
|
|
cycloneive_lcell_comb \z80_|address_latch_|Q[7]~feeder (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|Q[7]~feeder_combout = \z80_|address_latch_|abusz [7]
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|address_latch_|abusz [7]),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|Q[7]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|Q[7]~feeder .lut_mask = 16'hFF00;
|
|
defparam \z80_|address_latch_|Q[7]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y13_N17
|
|
dffeas \z80_|address_latch_|Q[7] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|address_latch_|Q[7]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|execute_|ctl_al_we~12_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|address_latch_|Q [7]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|Q[7] .is_wysiwyg = "true";
|
|
defparam \z80_|address_latch_|Q[7] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y13_N10
|
|
cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout = \z80_|address_latch_|Q [8] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & (\z80_|execute_|ctl_inc_dec~11_combout $ (\z80_|address_latch_|Q [7])))))
|
|
|
|
.dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ),
|
|
.datab(\z80_|address_latch_|Q [8]),
|
|
.datac(\z80_|execute_|ctl_inc_dec~11_combout ),
|
|
.datad(\z80_|address_latch_|Q [7]),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .lut_mask = 16'hC66C;
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y14_N23
|
|
dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[0] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_file_|db_hi_as[0]~6_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y14_N29
|
|
dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[0] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|db_hi_as[0]~6_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y14_N28
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~4 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_hi_as[0]~4_combout = (\z80_|reg_control_|reg_sw_4d_hi~0_combout & (\z80_|reg_file_|gdfx_temp1[0]~30_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) #
|
|
// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))
|
|
|
|
.dataa(\z80_|reg_control_|reg_sw_4d_hi~0_combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [0]),
|
|
.datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_hi_as[0]~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_hi_as[0]~4 .lut_mask = 16'hF351;
|
|
defparam \z80_|reg_file_|db_hi_as[0]~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y14_N0
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~5 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_hi_as[0]~5_combout = (\z80_|reg_file_|db_hi_as[0]~4_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout )))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_pc_hi|latch [0]),
|
|
.datad(\z80_|reg_file_|db_hi_as[0]~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_hi_as[0]~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_hi_as[0]~5 .lut_mask = 16'hF300;
|
|
defparam \z80_|reg_file_|db_hi_as[0]~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y14_N22
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~6 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_hi_as[0]~6_combout = ((\z80_|reg_file_|db_hi_as[0]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout )
|
|
|
|
.dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ),
|
|
.datab(\z80_|reg_file_|db_hi_as[0]~5_combout ),
|
|
.datac(\z80_|reg_file_|db_hi_as[0]~2_combout ),
|
|
.datad(\z80_|execute_|ctl_bus_inc_oe~43_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_hi_as[0]~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_hi_as[0]~6 .lut_mask = 16'h8FCF;
|
|
defparam \z80_|reg_file_|db_hi_as[0]~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y14_N27
|
|
dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y14_N13
|
|
dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[0] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y14_N26
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~23 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[0]~23_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [0]),
|
|
.datad(\z80_|reg_file_|b2v_latch_hl_hi|latch [0]),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[0]~23_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[0]~23 .lut_mask = 16'hF351;
|
|
defparam \z80_|reg_file_|gdfx_temp1[0]~23 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y16_N27
|
|
dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[0] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y16_N5
|
|
dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[0] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y16_N26
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~25 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[0]~25_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_iy_hi|latch [0]),
|
|
.datad(\z80_|reg_file_|b2v_latch_ix_hi|latch [0]),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[0]~25_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[0]~25 .lut_mask = 16'hF531;
|
|
defparam \z80_|reg_file_|gdfx_temp1[0]~25 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y15_N11
|
|
dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[0] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_file_|gdfx_temp1[0]~30_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y15_N13
|
|
dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[0] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y15_N12
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~27 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[0]~27_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ),
|
|
.datab(\z80_|reg_file_|b2v_latch_wz_hi|latch [0]),
|
|
.datac(\z80_|reg_file_|b2v_latch_sp_hi|latch [0]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[0]~27_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[0]~27 .lut_mask = 16'hD0DD;
|
|
defparam \z80_|reg_file_|gdfx_temp1[0]~27 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y16_N27
|
|
dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[0] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y16_N25
|
|
dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y16_N26
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~24 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[0]~24_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_bc_hi|latch [0]),
|
|
.datad(\z80_|reg_file_|b2v_latch_bc2_hi|latch [0]),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[0]~24_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[0]~24 .lut_mask = 16'hF351;
|
|
defparam \z80_|reg_file_|gdfx_temp1[0]~24 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y16_N27
|
|
dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[0] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y16_N26
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~26 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[0]~26_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[0]~14_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) #
|
|
// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ),
|
|
.datab(\z80_|alu_|db[0]~14_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [0]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[0]~26_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[0]~26 .lut_mask = 16'hD0DD;
|
|
defparam \z80_|reg_file_|gdfx_temp1[0]~26 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y15_N2
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~28 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[0]~28_combout = (\z80_|reg_file_|gdfx_temp1[0]~25_combout & (\z80_|reg_file_|gdfx_temp1[0]~27_combout & (\z80_|reg_file_|gdfx_temp1[0]~24_combout & \z80_|reg_file_|gdfx_temp1[0]~26_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|gdfx_temp1[0]~25_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp1[0]~27_combout ),
|
|
.datac(\z80_|reg_file_|gdfx_temp1[0]~24_combout ),
|
|
.datad(\z80_|reg_file_|gdfx_temp1[0]~26_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[0]~28_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[0]~28 .lut_mask = 16'h8000;
|
|
defparam \z80_|reg_file_|gdfx_temp1[0]~28 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X36_Y15_N17
|
|
dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[0] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_af_hi|latch [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_af_hi|latch[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y15_N16
|
|
cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[0]~11 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|b2v_latch_af_hi|db[0]~11_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [0]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_af_hi|latch [0]),
|
|
.datad(\z80_|reg_control_|reg_sel_af~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|b2v_latch_af_hi|db[0]~11_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~11 .lut_mask = 16'hFBFF;
|
|
defparam \z80_|reg_file_|b2v_latch_af_hi|db[0]~11 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y15_N11
|
|
dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[0] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[0]~30_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y15_N16
|
|
cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[0]~feeder (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|b2v_latch_de_hi|latch[0]~feeder_combout = \z80_|reg_file_|gdfx_temp1[0]~30_combout
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|reg_file_|gdfx_temp1[0]~30_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|b2v_latch_de_hi|latch[0]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0]~feeder .lut_mask = 16'hFF00;
|
|
defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y15_N17
|
|
dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[0] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_file_|b2v_latch_de_hi|latch[0]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_de_hi|latch [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_de_hi|latch[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y15_N10
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~22 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[0]~22_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [0] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [0]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [0])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [0]),
|
|
.datad(\z80_|reg_file_|b2v_latch_de_hi|latch [0]),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[0]~22_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[0]~22 .lut_mask = 16'hF351;
|
|
defparam \z80_|reg_file_|gdfx_temp1[0]~22 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y15_N24
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~29 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[0]~29_combout = (\z80_|reg_file_|gdfx_temp1[0]~23_combout & (\z80_|reg_file_|gdfx_temp1[0]~28_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[0]~11_combout & \z80_|reg_file_|gdfx_temp1[0]~22_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|gdfx_temp1[0]~23_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp1[0]~28_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_af_hi|db[0]~11_combout ),
|
|
.datad(\z80_|reg_file_|gdfx_temp1[0]~22_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[0]~29_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[0]~29 .lut_mask = 16'h8000;
|
|
defparam \z80_|reg_file_|gdfx_temp1[0]~29 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y15_N10
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[0]~30 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[0]~30_combout = ((\z80_|reg_file_|gdfx_temp1[0]~29_combout & ((\z80_|reg_file_|db_hi_as[0]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout )
|
|
|
|
.dataa(\z80_|reg_file_|db_hi_as[0]~6_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp1[0]~29_combout ),
|
|
.datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ),
|
|
.datad(\z80_|execute_|ctl_sw_4u~6_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[0]~30_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[0]~30 .lut_mask = 16'h8FCF;
|
|
defparam \z80_|reg_file_|gdfx_temp1[0]~30 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y15_N12
|
|
cycloneive_lcell_comb \z80_|alu_|db[0]~13 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db[0]~13_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[0]~30_combout & ((\z80_|alu_|db_low[0]~24_combout ) # (!\z80_|execute_|ctl_alu_oe~11_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout &
|
|
// (((\z80_|alu_|db_low[0]~24_combout ) # (!\z80_|execute_|ctl_alu_oe~11_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp1[0]~30_combout ),
|
|
.datac(\z80_|alu_|db_low[0]~24_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_oe~11_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db[0]~13_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db[0]~13 .lut_mask = 16'hD0DD;
|
|
defparam \z80_|alu_|db[0]~13 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y15_N22
|
|
cycloneive_lcell_comb \z80_|alu_|db[0]~14 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db[0]~14_combout = ((\z80_|alu_|db[0]~13_combout & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~9_combout )
|
|
|
|
.dataa(\z80_|alu_control_|db[0]~12_combout ),
|
|
.datab(\z80_|alu_|db[7]~9_combout ),
|
|
.datac(\z80_|execute_|ctl_sw_2d~13_combout ),
|
|
.datad(\z80_|alu_|db[0]~13_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db[0]~14_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db[0]~14 .lut_mask = 16'hBF33;
|
|
defparam \z80_|alu_|db[0]~14 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y16_N12
|
|
cycloneive_lcell_comb \z80_|alu_|db_low[1]~10 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_low[1]~10_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[2]~16_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[0]~14_combout )))
|
|
|
|
.dataa(\z80_|alu_|db[2]~16_combout ),
|
|
.datab(\z80_|alu_|db[0]~14_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|ir_|opcode [3]),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_low[1]~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_low[1]~10 .lut_mask = 16'hAACC;
|
|
defparam \z80_|alu_|db_low[1]~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y16_N10
|
|
cycloneive_lcell_comb \z80_|alu_|db_low[1]~11 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_low[1]~11_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_low[1]~10_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[1]~10_combout ))
|
|
|
|
.dataa(\z80_|alu_|db[1]~10_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|alu_|db_low[1]~10_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_low[1]~11_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_low[1]~11 .lut_mask = 16'hEE22;
|
|
defparam \z80_|alu_|db_low[1]~11 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y18_N22
|
|
cycloneive_lcell_comb \z80_|alu_|db_low[1]~8 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_low[1]~8_combout = (\z80_|execute_|ctl_alu_op2_oe~0_combout & (\z80_|alu_|op2_low [1] & ((\z80_|alu_|op1_low [1]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout & (((\z80_|alu_|op1_low [1]) #
|
|
// (!\z80_|execute_|ctl_alu_op1_oe~1_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op2_oe~0_combout ),
|
|
.datab(\z80_|alu_|op2_low [1]),
|
|
.datac(\z80_|execute_|ctl_alu_op1_oe~1_combout ),
|
|
.datad(\z80_|alu_|op1_low [1]),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_low[1]~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_low[1]~8 .lut_mask = 16'hDD0D;
|
|
defparam \z80_|alu_|db_low[1]~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y17_N2
|
|
cycloneive_lcell_comb \z80_|alu_|db_low[1]~7 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_low[1]~7_combout = ((\z80_|bus_control_|db[3]~21_combout & (!\z80_|bus_control_|db[5]~15_combout & !\z80_|bus_control_|db[4]~19_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout )
|
|
|
|
.dataa(\z80_|bus_control_|db[3]~21_combout ),
|
|
.datab(\z80_|bus_control_|db[5]~15_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_bs_oe~combout ),
|
|
.datad(\z80_|bus_control_|db[4]~19_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_low[1]~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_low[1]~7 .lut_mask = 16'h0F2F;
|
|
defparam \z80_|alu_|db_low[1]~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y18_N4
|
|
cycloneive_lcell_comb \z80_|alu_|result_lo[1]~feeder (
|
|
// Equation(s):
|
|
// \z80_|alu_|result_lo[1]~feeder_combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|result_lo[1]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|result_lo[1]~feeder .lut_mask = 16'hFF00;
|
|
defparam \z80_|alu_|result_lo[1]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X31_Y18_N5
|
|
dffeas \z80_|alu_|result_lo[1] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|alu_|result_lo[1]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|execute_|ctl_alu_op_low~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|alu_|result_lo [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|result_lo[1] .is_wysiwyg = "true";
|
|
defparam \z80_|alu_|result_lo[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y18_N4
|
|
cycloneive_lcell_comb \z80_|alu_|db_low[1]~9 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_low[1]~9_combout = (\z80_|alu_|db_low[1]~8_combout & (\z80_|alu_|db_low[1]~7_combout & ((\z80_|execute_|ctl_alu_res_oe~3_combout ) # (\z80_|alu_|result_lo [1]))))
|
|
|
|
.dataa(\z80_|alu_|db_low[1]~8_combout ),
|
|
.datab(\z80_|alu_|db_low[1]~7_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_res_oe~3_combout ),
|
|
.datad(\z80_|alu_|result_lo [1]),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_low[1]~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_low[1]~9 .lut_mask = 16'h8880;
|
|
defparam \z80_|alu_|db_low[1]~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y16_N26
|
|
cycloneive_lcell_comb \z80_|alu_|db_low[1]~12 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_low[1]~12_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[1]~11_combout & ((\z80_|alu_|db_low[1]~9_combout )))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[1]~9_combout ) #
|
|
// (!\z80_|alu_|db_high[3]~0_combout ))))
|
|
|
|
.dataa(\z80_|alu_|db_low[1]~11_combout ),
|
|
.datab(\z80_|alu_|db_high[3]~0_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ),
|
|
.datad(\z80_|alu_|db_low[1]~9_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_low[1]~12_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_low[1]~12 .lut_mask = 16'hAF03;
|
|
defparam \z80_|alu_|db_low[1]~12 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y15_N2
|
|
cycloneive_lcell_comb \z80_|alu_|db[1]~8 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db[1]~8_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[1]~21_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout &
|
|
// (((\z80_|alu_control_|db[1]~26_combout )) # (!\z80_|execute_|ctl_sw_2d~13_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ),
|
|
.datab(\z80_|execute_|ctl_sw_2d~13_combout ),
|
|
.datac(\z80_|reg_file_|gdfx_temp1[1]~21_combout ),
|
|
.datad(\z80_|alu_control_|db[1]~26_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db[1]~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db[1]~8 .lut_mask = 16'hF531;
|
|
defparam \z80_|alu_|db[1]~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y15_N18
|
|
cycloneive_lcell_comb \z80_|alu_|db[1]~10 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db[1]~10_combout = ((\z80_|alu_|db[1]~8_combout & ((\z80_|alu_|db_low[1]~12_combout ) # (!\z80_|execute_|ctl_alu_oe~11_combout )))) # (!\z80_|alu_|db[7]~9_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_oe~11_combout ),
|
|
.datab(\z80_|alu_|db[7]~9_combout ),
|
|
.datac(\z80_|alu_|db_low[1]~12_combout ),
|
|
.datad(\z80_|alu_|db[1]~8_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db[1]~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db[1]~10 .lut_mask = 16'hF733;
|
|
defparam \z80_|alu_|db[1]~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y16_N11
|
|
dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[1] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y16_N10
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~12 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[1]~12_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[1]~10_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) #
|
|
// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ),
|
|
.datab(\z80_|alu_|db[1]~10_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [1]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[1]~12_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[1]~12 .lut_mask = 16'hD0DD;
|
|
defparam \z80_|reg_file_|gdfx_temp1[1]~12 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y16_N4
|
|
cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp1[1]~21_combout
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|reg_file_|gdfx_temp1[1]~21_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder .lut_mask = 16'hFF00;
|
|
defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y16_N5
|
|
dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[1] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_file_|b2v_latch_iy_hi|latch[1]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y16_N1
|
|
dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[1] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y16_N0
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~11 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[1]~11_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ),
|
|
.datab(\z80_|reg_file_|b2v_latch_iy_hi|latch [1]),
|
|
.datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [1]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[1]~11_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[1]~11 .lut_mask = 16'hD0DD;
|
|
defparam \z80_|reg_file_|gdfx_temp1[1]~11 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y16_N11
|
|
dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y16_N17
|
|
dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[1] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y16_N10
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~10 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[1]~10_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (((\z80_|reg_file_|b2v_latch_bc_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [1]),
|
|
.datad(\z80_|reg_file_|b2v_latch_bc_hi|latch [1]),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[1]~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[1]~10 .lut_mask = 16'hF531;
|
|
defparam \z80_|reg_file_|gdfx_temp1[1]~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y15_N3
|
|
dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[1] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_file_|gdfx_temp1[1]~21_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y15_N1
|
|
dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[1] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y15_N0
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~13 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[1]~13_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [1]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ),
|
|
.datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [1]),
|
|
.datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [1]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[1]~13_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[1]~13 .lut_mask = 16'hC4F5;
|
|
defparam \z80_|reg_file_|gdfx_temp1[1]~13 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y16_N28
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~14 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[1]~14_combout = (\z80_|reg_file_|gdfx_temp1[1]~12_combout & (\z80_|reg_file_|gdfx_temp1[1]~11_combout & (\z80_|reg_file_|gdfx_temp1[1]~10_combout & \z80_|reg_file_|gdfx_temp1[1]~13_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|gdfx_temp1[1]~12_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp1[1]~11_combout ),
|
|
.datac(\z80_|reg_file_|gdfx_temp1[1]~10_combout ),
|
|
.datad(\z80_|reg_file_|gdfx_temp1[1]~13_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[1]~14_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[1]~14 .lut_mask = 16'h8000;
|
|
defparam \z80_|reg_file_|gdfx_temp1[1]~14 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X36_Y15_N25
|
|
dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[1] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_af_hi|latch [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_af_hi|latch[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y15_N24
|
|
cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[1]~10 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|b2v_latch_af_hi|db[1]~10_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [1]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_af_hi|latch [1]),
|
|
.datad(\z80_|reg_control_|reg_sel_af~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|b2v_latch_af_hi|db[1]~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~10 .lut_mask = 16'hFBFF;
|
|
defparam \z80_|reg_file_|b2v_latch_af_hi|db[1]~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y14_N29
|
|
dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[1] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y14_N11
|
|
dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y14_N10
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~9 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[1]~9_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ),
|
|
.datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [1]),
|
|
.datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [1]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[1]~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[1]~9 .lut_mask = 16'hD0DD;
|
|
defparam \z80_|reg_file_|gdfx_temp1[1]~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y15_N7
|
|
dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[1] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[1]~21_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y15_N20
|
|
cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder_combout = \z80_|reg_file_|gdfx_temp1[1]~21_combout
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|reg_file_|gdfx_temp1[1]~21_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder .lut_mask = 16'hFF00;
|
|
defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y15_N21
|
|
dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[1] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_file_|b2v_latch_de_hi|latch[1]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_de_hi|latch [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_de_hi|latch[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y15_N6
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~8 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[1]~8_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [1] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [1]),
|
|
.datad(\z80_|reg_file_|b2v_latch_de_hi|latch [1]),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[1]~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[1]~8 .lut_mask = 16'hF351;
|
|
defparam \z80_|reg_file_|gdfx_temp1[1]~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y15_N18
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~15 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[1]~15_combout = (\z80_|reg_file_|gdfx_temp1[1]~14_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[1]~10_combout & (\z80_|reg_file_|gdfx_temp1[1]~9_combout & \z80_|reg_file_|gdfx_temp1[1]~8_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|gdfx_temp1[1]~14_combout ),
|
|
.datab(\z80_|reg_file_|b2v_latch_af_hi|db[1]~10_combout ),
|
|
.datac(\z80_|reg_file_|gdfx_temp1[1]~9_combout ),
|
|
.datad(\z80_|reg_file_|gdfx_temp1[1]~8_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[1]~15_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[1]~15 .lut_mask = 16'h8000;
|
|
defparam \z80_|reg_file_|gdfx_temp1[1]~15 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y15_N2
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[1]~21 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[1]~21_combout = ((\z80_|reg_file_|gdfx_temp1[1]~15_combout & ((\z80_|reg_file_|db_hi_as[1]~3_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout )
|
|
|
|
.dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp1[1]~15_combout ),
|
|
.datac(\z80_|reg_file_|db_hi_as[1]~3_combout ),
|
|
.datad(\z80_|execute_|ctl_sw_4u~6_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[1]~21_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[1]~21 .lut_mask = 16'hD5DD;
|
|
defparam \z80_|reg_file_|gdfx_temp1[1]~21 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y14_N25
|
|
dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[1] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|db_hi_as[1]~3_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y14_N24
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~0 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_hi_as[1]~0_combout = (\z80_|reg_file_|gdfx_temp1[1]~21_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[1]~21_combout &
|
|
// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|gdfx_temp1[1]~21_combout ),
|
|
.datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [1]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_hi_as[1]~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_hi_as[1]~0 .lut_mask = 16'hB0BB;
|
|
defparam \z80_|reg_file_|db_hi_as[1]~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y14_N20
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~1 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_hi_as[1]~1_combout = (\z80_|reg_file_|db_hi_as[1]~0_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout )))
|
|
|
|
.dataa(\z80_|reg_file_|b2v_latch_pc_hi|latch [1]),
|
|
.datab(\z80_|reg_file_|db_hi_as[1]~0_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_hi_as[1]~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_hi_as[1]~1 .lut_mask = 16'h88CC;
|
|
defparam \z80_|reg_file_|db_hi_as[1]~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y14_N30
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[1]~3 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_hi_as[1]~3_combout = ((\z80_|reg_file_|db_hi_as[1]~1_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout )
|
|
|
|
.dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ),
|
|
.datab(\z80_|reg_file_|db_hi_as[1]~1_combout ),
|
|
.datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ),
|
|
.datad(\z80_|reg_file_|db_hi_as[0]~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_hi_as[1]~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_hi_as[1]~3 .lut_mask = 16'h8CFF;
|
|
defparam \z80_|reg_file_|db_hi_as[1]~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y10_N24
|
|
cycloneive_lcell_comb \z80_|address_latch_|abusz[9] (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|abusz [9] = (\z80_|reg_file_|db_hi_as[1]~3_combout & !\z80_|resets_|clrpc~0_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|reg_file_|db_hi_as[1]~3_combout ),
|
|
.datad(\z80_|resets_|clrpc~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|abusz [9]),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|abusz[9] .lut_mask = 16'h00F0;
|
|
defparam \z80_|address_latch_|abusz[9] .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y10_N22
|
|
cycloneive_lcell_comb \z80_|address_latch_|Q[9]~feeder (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|Q[9]~feeder_combout = \z80_|address_latch_|abusz [9]
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|address_latch_|abusz [9]),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|Q[9]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|Q[9]~feeder .lut_mask = 16'hFF00;
|
|
defparam \z80_|address_latch_|Q[9]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y10_N23
|
|
dffeas \z80_|address_latch_|Q[9] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|address_latch_|Q[9]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|execute_|ctl_al_we~12_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|address_latch_|Q [9]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|Q[9] .is_wysiwyg = "true";
|
|
defparam \z80_|address_latch_|Q[9] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y13_N26
|
|
cycloneive_lcell_comb \z80_|address_latch_|abusz[10] (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|abusz [10] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_hi_as[2]~9_combout )
|
|
|
|
.dataa(\z80_|resets_|clrpc~0_combout ),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|reg_file_|db_hi_as[2]~9_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|abusz [10]),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|abusz[10] .lut_mask = 16'h5500;
|
|
defparam \z80_|address_latch_|abusz[10] .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y13_N27
|
|
dffeas \z80_|address_latch_|Q[10] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|address_latch_|abusz [10]),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|execute_|ctl_al_we~12_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|address_latch_|Q [10]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|Q[10] .is_wysiwyg = "true";
|
|
defparam \z80_|address_latch_|Q[10] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y13_N12
|
|
cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout = \z80_|address_latch_|Q [10] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & (\z80_|execute_|ctl_inc_dec~11_combout $
|
|
// (\z80_|address_latch_|Q [9])))))
|
|
|
|
.dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ),
|
|
.datab(\z80_|execute_|ctl_inc_dec~11_combout ),
|
|
.datac(\z80_|address_latch_|Q [9]),
|
|
.datad(\z80_|address_latch_|Q [10]),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .lut_mask = 16'hD728;
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y14_N13
|
|
dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[2] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|db_hi_as[2]~9_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y14_N12
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~7 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_hi_as[2]~7_combout = (\z80_|reg_file_|gdfx_temp1[2]~39_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[2]~39_combout &
|
|
// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|gdfx_temp1[2]~39_combout ),
|
|
.datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [2]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_hi_as[2]~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_hi_as[2]~7 .lut_mask = 16'hB0BB;
|
|
defparam \z80_|reg_file_|db_hi_as[2]~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y14_N19
|
|
dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[2] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_file_|db_hi_as[2]~9_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y14_N8
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~8 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_hi_as[2]~8_combout = (\z80_|reg_file_|db_hi_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout )))
|
|
|
|
.dataa(\z80_|reg_file_|db_hi_as[2]~7_combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|reg_file_|b2v_latch_pc_hi|latch [2]),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_hi_as[2]~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_hi_as[2]~8 .lut_mask = 16'hAA22;
|
|
defparam \z80_|reg_file_|db_hi_as[2]~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y14_N18
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[2]~9 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_hi_as[2]~9_combout = ((\z80_|reg_file_|db_hi_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout )
|
|
|
|
.dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ),
|
|
.datab(\z80_|execute_|ctl_bus_inc_oe~43_combout ),
|
|
.datac(\z80_|reg_file_|db_hi_as[2]~8_combout ),
|
|
.datad(\z80_|reg_file_|db_hi_as[0]~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_hi_as[2]~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_hi_as[2]~9 .lut_mask = 16'hB0FF;
|
|
defparam \z80_|reg_file_|db_hi_as[2]~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y15_N14
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[2]~39 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[2]~39_combout = ((\z80_|reg_file_|gdfx_temp1[2]~38_combout & ((\z80_|reg_file_|db_hi_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout )
|
|
|
|
.dataa(\z80_|reg_file_|gdfx_temp1[0]~20_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp1[2]~38_combout ),
|
|
.datac(\z80_|reg_file_|db_hi_as[2]~9_combout ),
|
|
.datad(\z80_|execute_|ctl_sw_4u~6_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[2]~39_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[2]~39 .lut_mask = 16'hD5DD;
|
|
defparam \z80_|reg_file_|gdfx_temp1[2]~39 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y15_N24
|
|
cycloneive_lcell_comb \z80_|alu_|db[2]~15 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db[2]~15_combout = (\z80_|execute_|ctl_sw_2d~13_combout & (\z80_|alu_control_|db[2]~29_combout & ((\z80_|reg_file_|gdfx_temp1[2]~39_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|execute_|ctl_sw_2d~13_combout &
|
|
// ((\z80_|reg_file_|gdfx_temp1[2]~39_combout ) # ((!\z80_|execute_|ctl_reg_out_hi~7_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_sw_2d~13_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp1[2]~39_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_out_hi~7_combout ),
|
|
.datad(\z80_|alu_control_|db[2]~29_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db[2]~15_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db[2]~15 .lut_mask = 16'hCF45;
|
|
defparam \z80_|alu_|db[2]~15 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y15_N4
|
|
cycloneive_lcell_comb \z80_|alu_|db[2]~16 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db[2]~16_combout = ((\z80_|alu_|db[2]~15_combout & ((\z80_|alu_|db_low[2]~23_combout ) # (!\z80_|execute_|ctl_alu_oe~11_combout )))) # (!\z80_|alu_|db[7]~9_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_oe~11_combout ),
|
|
.datab(\z80_|alu_|db[2]~15_combout ),
|
|
.datac(\z80_|alu_|db[7]~9_combout ),
|
|
.datad(\z80_|alu_|db_low[2]~23_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db[2]~16_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db[2]~16 .lut_mask = 16'hCF4F;
|
|
defparam \z80_|alu_|db[2]~16 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y14_N24
|
|
cycloneive_lcell_comb \z80_|alu_control_|db[2]~27 (
|
|
// Equation(s):
|
|
// \z80_|alu_control_|db[2]~27_combout = (\z80_|alu_|db[2]~16_combout & (!\z80_|alu_flags_|DFFE_inst_latch_pf~q & ((\z80_|execute_|ctl_flags_oe~2_combout )))) # (!\z80_|alu_|db[2]~16_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) #
|
|
// ((!\z80_|alu_flags_|DFFE_inst_latch_pf~q & \z80_|execute_|ctl_flags_oe~2_combout ))))
|
|
|
|
.dataa(\z80_|alu_|db[2]~16_combout ),
|
|
.datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ),
|
|
.datac(\z80_|execute_|ctl_sw_2u~7_combout ),
|
|
.datad(\z80_|execute_|ctl_flags_oe~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_control_|db[2]~27_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_control_|db[2]~27 .lut_mask = 16'h7350;
|
|
defparam \z80_|alu_control_|db[2]~27 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y18_N0
|
|
cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_cf~2 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|DFFE_inst_latch_cf~2_combout = (\z80_|execute_|ctl_flags_alu~15_combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|execute_|ctl_flags_alu~15_combout ),
|
|
.datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .lut_mask = 16'h0C0C;
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_cf~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y18_N26
|
|
cycloneive_lcell_comb \z80_|alu_flags_|flags_hf2~0 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|flags_hf2~0_combout = (\z80_|execute_|ctl_flags_hf2_we~combout & ((\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ) # ((\z80_|alu_control_|db[4]~32_combout )))) # (!\z80_|execute_|ctl_flags_hf2_we~combout &
|
|
// (((\z80_|alu_flags_|flags_hf2~q ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_hf2_we~combout ),
|
|
.datab(\z80_|alu_flags_|DFFE_inst_latch_cf~2_combout ),
|
|
.datac(\z80_|alu_flags_|flags_hf2~q ),
|
|
.datad(\z80_|alu_control_|db[4]~32_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|flags_hf2~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|flags_hf2~0 .lut_mask = 16'hFAD8;
|
|
defparam \z80_|alu_flags_|flags_hf2~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X29_Y18_N27
|
|
dffeas \z80_|alu_flags_|flags_hf2 (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|alu_flags_|flags_hf2~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|alu_flags_|flags_hf2~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|flags_hf2 .is_wysiwyg = "true";
|
|
defparam \z80_|alu_flags_|flags_hf2 .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y14_N30
|
|
cycloneive_lcell_comb \z80_|alu_control_|db[2]~23 (
|
|
// Equation(s):
|
|
// \z80_|alu_control_|db[2]~23_combout = ((\z80_|alu_flags_|flags_hf2~q ) # ((\z80_|alu_control_|out[6]~0_combout ) # (\z80_|execute_|ctl_66_oe~combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ),
|
|
.datab(\z80_|alu_flags_|flags_hf2~q ),
|
|
.datac(\z80_|alu_control_|out[6]~0_combout ),
|
|
.datad(\z80_|execute_|ctl_66_oe~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_control_|db[2]~23_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_control_|db[2]~23 .lut_mask = 16'hFFFD;
|
|
defparam \z80_|alu_control_|db[2]~23 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y14_N30
|
|
cycloneive_lcell_comb \z80_|alu_control_|db[2]~29 (
|
|
// Equation(s):
|
|
// \z80_|alu_control_|db[2]~29_combout = ((\z80_|alu_control_|db[2]~28_combout & (!\z80_|alu_control_|db[2]~27_combout & \z80_|alu_control_|db[2]~23_combout ))) # (!\z80_|alu_control_|db[6]~11_combout )
|
|
|
|
.dataa(\z80_|alu_control_|db[2]~28_combout ),
|
|
.datab(\z80_|alu_control_|db[2]~27_combout ),
|
|
.datac(\z80_|alu_control_|db[2]~23_combout ),
|
|
.datad(\z80_|alu_control_|db[6]~11_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_control_|db[2]~29_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_control_|db[2]~29 .lut_mask = 16'h20FF;
|
|
defparam \z80_|alu_control_|db[2]~29 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y13_N4
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~39 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[2]~39_combout = (\z80_|execute_|ctl_reg_in_lo~8_combout & (\z80_|alu_control_|db[2]~29_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout )))) #
|
|
// (!\z80_|execute_|ctl_reg_in_lo~8_combout & ((\z80_|reg_file_|b2v_latch_sp_lo|latch [2]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_in_lo~8_combout ),
|
|
.datab(\z80_|reg_file_|b2v_latch_sp_lo|latch [2]),
|
|
.datac(\z80_|alu_control_|db[2]~29_combout ),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[2]~39_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[2]~39 .lut_mask = 16'hC4F5;
|
|
defparam \z80_|reg_file_|gdfx_temp0[2]~39 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y11_N3
|
|
dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[2] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y11_N21
|
|
dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[2] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[2]~42_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_af_lo|latch [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_af_lo|latch[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y11_N2
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~35 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[2]~35_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [2] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [2])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [2]),
|
|
.datad(\z80_|reg_file_|b2v_latch_af_lo|latch [2]),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[2]~35_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[2]~35 .lut_mask = 16'hF531;
|
|
defparam \z80_|reg_file_|gdfx_temp0[2]~35 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y13_N26
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~40 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[2]~40_combout = (\z80_|reg_file_|gdfx_temp0[2]~37_combout & (\z80_|reg_file_|gdfx_temp0[2]~38_combout & (\z80_|reg_file_|gdfx_temp0[2]~39_combout & \z80_|reg_file_|gdfx_temp0[2]~35_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|gdfx_temp0[2]~37_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp0[2]~38_combout ),
|
|
.datac(\z80_|reg_file_|gdfx_temp0[2]~39_combout ),
|
|
.datad(\z80_|reg_file_|gdfx_temp0[2]~35_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[2]~40_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[2]~40 .lut_mask = 16'h8000;
|
|
defparam \z80_|reg_file_|gdfx_temp0[2]~40 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y12_N30
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~41 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[2]~41_combout = (\z80_|reg_file_|gdfx_temp0[2]~33_combout & (\z80_|reg_file_|gdfx_temp0[2]~34_combout & \z80_|reg_file_|gdfx_temp0[2]~40_combout ))
|
|
|
|
.dataa(\z80_|reg_file_|gdfx_temp0[2]~33_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp0[2]~34_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|reg_file_|gdfx_temp0[2]~40_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[2]~41_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[2]~41 .lut_mask = 16'h8800;
|
|
defparam \z80_|reg_file_|gdfx_temp0[2]~41 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y12_N10
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[2]~42 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[2]~42_combout = ((\z80_|reg_file_|gdfx_temp0[2]~41_combout & ((\z80_|reg_file_|db_lo_as[2]~9_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_sw_4u~6_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp0[2]~41_combout ),
|
|
.datac(\z80_|reg_file_|gdfx_temp0[0]~21_combout ),
|
|
.datad(\z80_|reg_file_|db_lo_as[2]~9_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[2]~42_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[2]~42 .lut_mask = 16'hCF4F;
|
|
defparam \z80_|reg_file_|gdfx_temp0[2]~42 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y12_N15
|
|
dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[2] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|db_lo_as[2]~9_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y12_N14
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~7 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_lo_as[2]~7_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[2]~42_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) #
|
|
// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_sw_4d~6_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp0[2]~42_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [2]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_lo_as[2]~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_lo_as[2]~7 .lut_mask = 16'hD0DD;
|
|
defparam \z80_|reg_file_|db_lo_as[2]~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y12_N6
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~8 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_lo_as[2]~8_combout = (\z80_|reg_file_|db_lo_as[2]~7_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [2]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout )))
|
|
|
|
.dataa(\z80_|reg_file_|b2v_latch_ir_lo|latch [2]),
|
|
.datab(gnd),
|
|
.datac(\z80_|reg_file_|db_lo_as[2]~7_combout ),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_lo_as[2]~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_lo_as[2]~8 .lut_mask = 16'hA0F0;
|
|
defparam \z80_|reg_file_|db_lo_as[2]~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y11_N4
|
|
cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout = \z80_|address_latch_|Q [0] $ (((\z80_|execute_|ctl_inc_dec~9_combout ) # ((\z80_|execute_|ctl_inc_dec~7_combout ) # (!\z80_|execute_|ctl_inc_dec~6_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_inc_dec~9_combout ),
|
|
.datab(\z80_|address_latch_|Q [0]),
|
|
.datac(\z80_|execute_|ctl_inc_dec~6_combout ),
|
|
.datad(\z80_|execute_|ctl_inc_dec~7_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .lut_mask = 16'h3363;
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y11_N26
|
|
cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout & ((\z80_|execute_|ctl_inc_cy~71_combout ) # ((\z80_|execute_|ctl_inc_cy~81_combout ) #
|
|
// (\z80_|execute_|ctl_inc_cy~68_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_inc_cy~71_combout ),
|
|
.datab(\z80_|execute_|ctl_inc_cy~81_combout ),
|
|
.datac(\z80_|execute_|ctl_inc_cy~68_combout ),
|
|
.datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_41~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 .lut_mask = 16'hFE00;
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y11_N0
|
|
cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout = \z80_|address_latch_|Q [2] $ (((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout &
|
|
// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout )))
|
|
|
|
.dataa(\z80_|address_latch_|Q [2]),
|
|
.datab(gnd),
|
|
.datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ),
|
|
.datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .lut_mask = 16'h5AAA;
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y12_N8
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[2]~9 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_lo_as[2]~9_combout = ((\z80_|reg_file_|db_lo_as[2]~8_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout )
|
|
|
|
.dataa(\z80_|reg_file_|db_lo_as[2]~8_combout ),
|
|
.datab(\z80_|reg_file_|db_lo_as[0]~2_combout ),
|
|
.datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ),
|
|
.datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_lo_as[2]~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_lo_as[2]~9 .lut_mask = 16'hBB3B;
|
|
defparam \z80_|reg_file_|db_lo_as[2]~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y11_N8
|
|
cycloneive_lcell_comb \z80_|address_latch_|abusz[2] (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|abusz [2] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[2]~9_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|resets_|clrpc~0_combout ),
|
|
.datad(\z80_|reg_file_|db_lo_as[2]~9_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|abusz [2]),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|abusz[2] .lut_mask = 16'h0F00;
|
|
defparam \z80_|address_latch_|abusz[2] .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y11_N9
|
|
dffeas \z80_|address_latch_|Q[2] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|address_latch_|abusz [2]),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|execute_|ctl_al_we~12_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|address_latch_|Q [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|Q[2] .is_wysiwyg = "true";
|
|
defparam \z80_|address_latch_|Q[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y11_N18
|
|
cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout = \z80_|address_latch_|Q [2] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_inc_dec~5_combout )) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_bus_inc_oe~42_combout ),
|
|
.datab(\z80_|address_latch_|Q [2]),
|
|
.datac(\z80_|execute_|ctl_inc_dec~10_combout ),
|
|
.datad(\z80_|execute_|ctl_inc_dec~5_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 .lut_mask = 16'h3933;
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y12_N25
|
|
dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[3] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|db_lo_as[3]~12_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y12_N24
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~10 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_lo_as[3]~10_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[3]~52_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) #
|
|
// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_sw_4d~6_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp0[3]~52_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [3]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_lo_as[3]~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_lo_as[3]~10 .lut_mask = 16'hD0DD;
|
|
defparam \z80_|reg_file_|db_lo_as[3]~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y12_N31
|
|
dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[3] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_file_|db_lo_as[3]~12_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y12_N28
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~11 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_lo_as[3]~11_combout = (\z80_|reg_file_|db_lo_as[3]~10_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ),
|
|
.datab(\z80_|reg_file_|db_lo_as[3]~10_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|reg_file_|b2v_latch_ir_lo|latch [3]),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_lo_as[3]~11_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_lo_as[3]~11 .lut_mask = 16'hCC44;
|
|
defparam \z80_|reg_file_|db_lo_as[3]~11 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y11_N26
|
|
cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout = \z80_|address_latch_|Q [3] $ (((\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout &
|
|
// (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ))))
|
|
|
|
.dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ),
|
|
.datab(\z80_|address_latch_|Q [3]),
|
|
.datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ),
|
|
.datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .lut_mask = 16'h6CCC;
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y12_N30
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[3]~12 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_lo_as[3]~12_combout = ((\z80_|reg_file_|db_lo_as[3]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ),
|
|
.datab(\z80_|reg_file_|db_lo_as[3]~11_combout ),
|
|
.datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ),
|
|
.datad(\z80_|reg_file_|db_lo_as[0]~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_lo_as[3]~12_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_lo_as[3]~12 .lut_mask = 16'hC4FF;
|
|
defparam \z80_|reg_file_|db_lo_as[3]~12 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y11_N14
|
|
cycloneive_lcell_comb \z80_|address_latch_|abusz[3] (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|abusz [3] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[3]~12_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|resets_|clrpc~0_combout ),
|
|
.datac(\z80_|reg_file_|db_lo_as[3]~12_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|abusz [3]),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|abusz[3] .lut_mask = 16'h3030;
|
|
defparam \z80_|address_latch_|abusz[3] .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y11_N15
|
|
dffeas \z80_|address_latch_|Q[3] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|address_latch_|abusz [3]),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|execute_|ctl_al_we~12_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|address_latch_|Q [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|Q[3] .is_wysiwyg = "true";
|
|
defparam \z80_|address_latch_|Q[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y11_N24
|
|
cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout = \z80_|address_latch_|Q [3] $ ((((\z80_|execute_|ctl_inc_dec~10_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~42_combout )) # (!\z80_|execute_|ctl_inc_dec~5_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_inc_dec~5_combout ),
|
|
.datab(\z80_|address_latch_|Q [3]),
|
|
.datac(\z80_|execute_|ctl_inc_dec~10_combout ),
|
|
.datad(\z80_|execute_|ctl_bus_inc_oe~42_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 .lut_mask = 16'h3933;
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y11_N10
|
|
cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout &
|
|
// (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout )))
|
|
|
|
.dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_40~0_combout ),
|
|
.datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_42~combout ),
|
|
.datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ),
|
|
.datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_45~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .lut_mask = 16'h8000;
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y11_N16
|
|
cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout = (!\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|address_latch_|Q [6] $ (((\z80_|execute_|ctl_inc_dec~7_combout ) # (\z80_|execute_|ctl_inc_dec~10_combout )))))
|
|
|
|
.dataa(\z80_|address_latch_|Q [6]),
|
|
.datab(\z80_|execute_|ctl_inc_dec~7_combout ),
|
|
.datac(\z80_|execute_|ctl_inc_dec~10_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .lut_mask = 16'h0056;
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y11_N14
|
|
cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout & (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout &
|
|
// (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout & \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout )))
|
|
|
|
.dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|carry_borrow_out~0_combout ),
|
|
.datab(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_44~combout ),
|
|
.datac(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_43~4_combout ),
|
|
.datad(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .lut_mask = 16'h8000;
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y13_N22
|
|
cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout & ((\z80_|address_latch_|Q [8] & (!\z80_|execute_|ctl_inc_dec~11_combout & \z80_|address_latch_|Q
|
|
// [7])) # (!\z80_|address_latch_|Q [8] & (\z80_|execute_|ctl_inc_dec~11_combout & !\z80_|address_latch_|Q [7]))))
|
|
|
|
.dataa(\z80_|address_latch_|b2v_inst_inc_dec|SYNTHESIZED_WIRE_47~combout ),
|
|
.datab(\z80_|address_latch_|Q [8]),
|
|
.datac(\z80_|execute_|ctl_inc_dec~11_combout ),
|
|
.datad(\z80_|address_latch_|Q [7]),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .lut_mask = 16'h0820;
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y13_N28
|
|
cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout = (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout & ((\z80_|execute_|ctl_inc_dec~11_combout & (!\z80_|address_latch_|Q [9] &
|
|
// !\z80_|address_latch_|Q [10])) # (!\z80_|execute_|ctl_inc_dec~11_combout & (\z80_|address_latch_|Q [9] & \z80_|address_latch_|Q [10]))))
|
|
|
|
.dataa(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|carry_borrow_out~0_combout ),
|
|
.datab(\z80_|execute_|ctl_inc_dec~11_combout ),
|
|
.datac(\z80_|address_latch_|Q [9]),
|
|
.datad(\z80_|address_latch_|Q [10]),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .lut_mask = 16'h2008;
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y13_N26
|
|
cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|address[11] (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|b2v_inst_inc_dec|address [11] = \z80_|address_latch_|Q [11] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|address_latch_|Q [11]),
|
|
.datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|carry_borrow_out~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|b2v_inst_inc_dec|address [11]),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .lut_mask = 16'h0FF0;
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|address[11] .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y14_N4
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[3]~12 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_hi_as[3]~12_combout = ((\z80_|reg_file_|db_hi_as[3]~11_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address [11]) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout )
|
|
|
|
.dataa(\z80_|reg_file_|db_hi_as[0]~2_combout ),
|
|
.datab(\z80_|execute_|ctl_bus_inc_oe~43_combout ),
|
|
.datac(\z80_|reg_file_|db_hi_as[3]~11_combout ),
|
|
.datad(\z80_|address_latch_|b2v_inst_inc_dec|address [11]),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_hi_as[3]~12_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_hi_as[3]~12 .lut_mask = 16'hF575;
|
|
defparam \z80_|reg_file_|db_hi_as[3]~12 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y14_N17
|
|
dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[3] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y14_N31
|
|
dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y14_N30
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~41 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[3]~41_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ),
|
|
.datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [3]),
|
|
.datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [3]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[3]~41_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[3]~41 .lut_mask = 16'hD0DD;
|
|
defparam \z80_|reg_file_|gdfx_temp1[3]~41 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y15_N5
|
|
dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[3] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y15_N7
|
|
dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[3] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_file_|gdfx_temp1[3]~48_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y15_N4
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~45 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[3]~45_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (((\z80_|reg_file_|b2v_latch_sp_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [3]),
|
|
.datad(\z80_|reg_file_|b2v_latch_sp_hi|latch [3]),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[3]~45_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[3]~45 .lut_mask = 16'hF531;
|
|
defparam \z80_|reg_file_|gdfx_temp1[3]~45 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y16_N23
|
|
dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[3] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y16_N22
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~44 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[3]~44_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[3]~20_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) #
|
|
// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ),
|
|
.datab(\z80_|alu_|db[3]~20_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [3]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[3]~44_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[3]~44 .lut_mask = 16'hD0DD;
|
|
defparam \z80_|reg_file_|gdfx_temp1[3]~44 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y16_N19
|
|
dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[3] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y16_N9
|
|
dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[3] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y16_N18
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~43 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[3]~43_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [3]),
|
|
.datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [3]),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[3]~43_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[3]~43 .lut_mask = 16'hF351;
|
|
defparam \z80_|reg_file_|gdfx_temp1[3]~43 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y16_N9
|
|
dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[3] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y16_N7
|
|
dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y16_N6
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~42 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[3]~42_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ),
|
|
.datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [3]),
|
|
.datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [3]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[3]~42_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[3]~42 .lut_mask = 16'hC4F5;
|
|
defparam \z80_|reg_file_|gdfx_temp1[3]~42 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y16_N16
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~46 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[3]~46_combout = (\z80_|reg_file_|gdfx_temp1[3]~45_combout & (\z80_|reg_file_|gdfx_temp1[3]~44_combout & (\z80_|reg_file_|gdfx_temp1[3]~43_combout & \z80_|reg_file_|gdfx_temp1[3]~42_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|gdfx_temp1[3]~45_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp1[3]~44_combout ),
|
|
.datac(\z80_|reg_file_|gdfx_temp1[3]~43_combout ),
|
|
.datad(\z80_|reg_file_|gdfx_temp1[3]~42_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[3]~46_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[3]~46 .lut_mask = 16'h8000;
|
|
defparam \z80_|reg_file_|gdfx_temp1[3]~46 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y15_N8
|
|
cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[3]~feeder (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|b2v_latch_de_hi|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp1[3]~48_combout
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|reg_file_|gdfx_temp1[3]~48_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|b2v_latch_de_hi|latch[3]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3]~feeder .lut_mask = 16'hFF00;
|
|
defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y15_N9
|
|
dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[3] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_file_|b2v_latch_de_hi|latch[3]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_de_hi|latch [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_de_hi|latch[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y15_N27
|
|
dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[3] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y15_N26
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~40 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[3]~40_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [3] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ),
|
|
.datab(\z80_|reg_file_|b2v_latch_de_hi|latch [3]),
|
|
.datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [3]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[3]~40_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[3]~40 .lut_mask = 16'hD0DD;
|
|
defparam \z80_|reg_file_|gdfx_temp1[3]~40 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X36_Y15_N21
|
|
dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[3] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[3]~48_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_af_hi|latch [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_af_hi|latch[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y16_N10
|
|
cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[3]~13 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|b2v_latch_af_hi|db[3]~13_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [3]) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout )) # (!\z80_|reg_control_|reg_sel_af~0_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ),
|
|
.datab(\z80_|reg_control_|reg_sel_af~0_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ),
|
|
.datad(\z80_|reg_file_|b2v_latch_af_hi|latch [3]),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|b2v_latch_af_hi|db[3]~13_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~13 .lut_mask = 16'hFFBF;
|
|
defparam \z80_|reg_file_|b2v_latch_af_hi|db[3]~13 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y16_N22
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~47 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[3]~47_combout = (\z80_|reg_file_|gdfx_temp1[3]~41_combout & (\z80_|reg_file_|gdfx_temp1[3]~46_combout & (\z80_|reg_file_|gdfx_temp1[3]~40_combout & \z80_|reg_file_|b2v_latch_af_hi|db[3]~13_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|gdfx_temp1[3]~41_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp1[3]~46_combout ),
|
|
.datac(\z80_|reg_file_|gdfx_temp1[3]~40_combout ),
|
|
.datad(\z80_|reg_file_|b2v_latch_af_hi|db[3]~13_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[3]~47_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[3]~47 .lut_mask = 16'h8000;
|
|
defparam \z80_|reg_file_|gdfx_temp1[3]~47 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y15_N6
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[3]~48 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[3]~48_combout = ((\z80_|reg_file_|gdfx_temp1[3]~47_combout & ((\z80_|reg_file_|db_hi_as[3]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout )
|
|
|
|
.dataa(\z80_|reg_file_|db_hi_as[3]~12_combout ),
|
|
.datab(\z80_|execute_|ctl_sw_4u~6_combout ),
|
|
.datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ),
|
|
.datad(\z80_|reg_file_|gdfx_temp1[3]~47_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[3]~48_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[3]~48 .lut_mask = 16'hBF0F;
|
|
defparam \z80_|reg_file_|gdfx_temp1[3]~48 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y15_N6
|
|
cycloneive_lcell_comb \z80_|alu_|db[3]~19 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db[3]~19_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[3]~48_combout & ((\z80_|alu_|db_low[3]~25_combout ) # (!\z80_|execute_|ctl_alu_oe~11_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout &
|
|
// ((\z80_|alu_|db_low[3]~25_combout ) # ((!\z80_|execute_|ctl_alu_oe~11_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ),
|
|
.datab(\z80_|alu_|db_low[3]~25_combout ),
|
|
.datac(\z80_|reg_file_|gdfx_temp1[3]~48_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_oe~11_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db[3]~19_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db[3]~19 .lut_mask = 16'hC4F5;
|
|
defparam \z80_|alu_|db[3]~19 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y15_N28
|
|
cycloneive_lcell_comb \z80_|alu_|db[3]~20 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db[3]~20_combout = ((\z80_|alu_|db[3]~19_combout & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|alu_|db[7]~9_combout )
|
|
|
|
.dataa(\z80_|alu_control_|db[3]~35_combout ),
|
|
.datab(\z80_|alu_|db[7]~9_combout ),
|
|
.datac(\z80_|execute_|ctl_sw_2d~13_combout ),
|
|
.datad(\z80_|alu_|db[3]~19_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db[3]~20_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db[3]~20 .lut_mask = 16'hBF33;
|
|
defparam \z80_|alu_|db[3]~20 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y16_N18
|
|
cycloneive_lcell_comb \z80_|alu_|db_low[2]~21 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_low[2]~21_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[3]~20_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[1]~10_combout )))
|
|
|
|
.dataa(\z80_|alu_|db[3]~20_combout ),
|
|
.datab(\z80_|ir_|opcode [3]),
|
|
.datac(gnd),
|
|
.datad(\z80_|alu_|db[1]~10_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_low[2]~21_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_low[2]~21 .lut_mask = 16'hBB88;
|
|
defparam \z80_|alu_|db_low[2]~21 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y16_N12
|
|
cycloneive_lcell_comb \z80_|alu_|db_low[2]~22 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_low[2]~22_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_low[2]~21_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[2]~16_combout )))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|alu_|db_low[2]~21_combout ),
|
|
.datac(\z80_|alu_|db[2]~16_combout ),
|
|
.datad(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_low[2]~22_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_low[2]~22 .lut_mask = 16'hCCF0;
|
|
defparam \z80_|alu_|db_low[2]~22 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X31_Y17_N1
|
|
dffeas \z80_|alu_|result_lo[2] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|execute_|ctl_alu_op_low~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|alu_|result_lo [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|result_lo[2] .is_wysiwyg = "true";
|
|
defparam \z80_|alu_|result_lo[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y17_N10
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout = (\z80_|bus_control_|db[4]~19_combout & !\z80_|bus_control_|db[3]~21_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|bus_control_|db[4]~19_combout ),
|
|
.datac(\z80_|bus_control_|db[3]~21_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .lut_mask = 16'h0C0C;
|
|
defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y18_N22
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~6 (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~6_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_low [2])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_high [2])))))
|
|
|
|
.dataa(\z80_|alu_|op1_low [2]),
|
|
.datab(\z80_|execute_|ctl_alu_op_low~combout ),
|
|
.datac(\z80_|execute_|ctl_alu_op2_sel_lq~combout ),
|
|
.datad(\z80_|alu_|op1_high [2]),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~6 .lut_mask = 16'hB080;
|
|
defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y18_N30
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~7 (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~7_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~6_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & \z80_|alu_|db_low[2]~23_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ),
|
|
.datac(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~6_combout ),
|
|
.datad(\z80_|alu_|db_low[2]~23_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~7 .lut_mask = 16'h3230;
|
|
defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[2]~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y18_N31
|
|
dffeas \z80_|alu_|op2_low[2] (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|alu_|b2v_op2_latch_mux_low|Q[2]~7_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|alu_|op2_low [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|op2_low[2] .is_wysiwyg = "true";
|
|
defparam \z80_|alu_|op2_low[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y17_N6
|
|
cycloneive_lcell_comb \z80_|alu_|db_low[2]~18 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_low[2]~18_combout = (\z80_|execute_|ctl_alu_op2_oe~0_combout & (\z80_|alu_|op2_low [2] & ((\z80_|alu_|op1_low [2]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout & ((\z80_|alu_|op1_low [2]) #
|
|
// ((!\z80_|execute_|ctl_alu_op1_oe~1_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op2_oe~0_combout ),
|
|
.datab(\z80_|alu_|op1_low [2]),
|
|
.datac(\z80_|alu_|op2_low [2]),
|
|
.datad(\z80_|execute_|ctl_alu_op1_oe~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_low[2]~18_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_low[2]~18 .lut_mask = 16'hC4F5;
|
|
defparam \z80_|alu_|db_low[2]~18 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y17_N22
|
|
cycloneive_lcell_comb \z80_|alu_|db_low[2]~19 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_low[2]~19_combout = (\z80_|alu_|db_low[2]~18_combout & (((\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout & !\z80_|bus_control_|db[5]~15_combout )) # (!\z80_|execute_|ctl_alu_bs_oe~combout )))
|
|
|
|
.dataa(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ),
|
|
.datab(\z80_|bus_control_|db[5]~15_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_bs_oe~combout ),
|
|
.datad(\z80_|alu_|db_low[2]~18_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_low[2]~19_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_low[2]~19 .lut_mask = 16'h2F00;
|
|
defparam \z80_|alu_|db_low[2]~19 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y17_N0
|
|
cycloneive_lcell_comb \z80_|alu_|db_low[2]~20 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_low[2]~20_combout = (\z80_|alu_|db_low[2]~19_combout & ((\z80_|execute_|ctl_alu_res_oe~3_combout ) # (\z80_|alu_|result_lo [2])))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|execute_|ctl_alu_res_oe~3_combout ),
|
|
.datac(\z80_|alu_|result_lo [2]),
|
|
.datad(\z80_|alu_|db_low[2]~19_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_low[2]~20_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_low[2]~20 .lut_mask = 16'hFC00;
|
|
defparam \z80_|alu_|db_low[2]~20 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y16_N2
|
|
cycloneive_lcell_comb \z80_|alu_|db_low[2]~23 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_low[2]~23_combout = (\z80_|execute_|ctl_alu_shift_oe~43_combout & (\z80_|alu_|db_low[2]~22_combout & ((\z80_|alu_|db_low[2]~20_combout )))) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout & (((\z80_|alu_|db_low[2]~20_combout ) #
|
|
// (!\z80_|alu_|db_high[3]~0_combout ))))
|
|
|
|
.dataa(\z80_|alu_|db_low[2]~22_combout ),
|
|
.datab(\z80_|alu_|db_high[3]~0_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ),
|
|
.datad(\z80_|alu_|db_low[2]~20_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_low[2]~23_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_low[2]~23 .lut_mask = 16'hAF03;
|
|
defparam \z80_|alu_|db_low[2]~23 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y17_N2
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~7 (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~7_combout = (\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & ((\z80_|alu_|db_low[2]~23_combout ) # ((\z80_|alu_|db_high[2]~13_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout )))) #
|
|
// (!\z80_|execute_|ctl_alu_op1_sel_bus~15_combout & (((\z80_|alu_|db_high[2]~13_combout & \z80_|execute_|ctl_alu_op1_sel_low~combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op1_sel_bus~15_combout ),
|
|
.datab(\z80_|alu_|db_low[2]~23_combout ),
|
|
.datac(\z80_|alu_|db_high[2]~13_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op1_sel_low~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~7 .lut_mask = 16'hF888;
|
|
defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y17_N10
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~8 (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~8_combout = (!\z80_|execute_|ctl_alu_op1_sel_zero~combout & \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~7_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_alu_op1_sel_zero~combout ),
|
|
.datad(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~7_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~8 .lut_mask = 16'h0F00;
|
|
defparam \z80_|alu_|b2v_op1_latch_mux_low|Q[2]~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y17_N11
|
|
dffeas \z80_|alu_|op1_low[2] (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|alu_|b2v_op1_latch_mux_low|Q[2]~8_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|alu_|b2v_op1_latch_mux_low|ena~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|alu_|op1_low [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|op1_low[2] .is_wysiwyg = "true";
|
|
defparam \z80_|alu_|op1_low[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y17_N26
|
|
cycloneive_lcell_comb \z80_|alu_|alu_op1[2]~1 (
|
|
// Equation(s):
|
|
// \z80_|alu_|alu_op1[2]~1_combout = (\z80_|execute_|ctl_alu_op_low~41_combout & (\z80_|alu_|op1_low [2])) # (!\z80_|execute_|ctl_alu_op_low~41_combout & ((\z80_|execute_|ctl_alu_op_low~29_combout & ((\z80_|alu_|op1_high [2]))) #
|
|
// (!\z80_|execute_|ctl_alu_op_low~29_combout & (\z80_|alu_|op1_low [2]))))
|
|
|
|
.dataa(\z80_|alu_|op1_low [2]),
|
|
.datab(\z80_|execute_|ctl_alu_op_low~41_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_op_low~29_combout ),
|
|
.datad(\z80_|alu_|op1_high [2]),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|alu_op1[2]~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|alu_op1[2]~1 .lut_mask = 16'hBA8A;
|
|
defparam \z80_|alu_|alu_op1[2]~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y17_N30
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout = (\z80_|execute_|ctl_alu_core_S~combout ) # ((\z80_|alu_|alu_op1[2]~1_combout & \z80_|alu_|alu_op2[2]~0_combout ))
|
|
|
|
.dataa(\z80_|alu_|alu_op1[2]~1_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|alu_|alu_op2[2]~0_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_core_S~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .lut_mask = 16'hFFA0;
|
|
defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y17_N8
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[2]~0_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [2])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high
|
|
// [2])))))
|
|
|
|
.dataa(\z80_|alu_|alu_op2[2]~0_combout ),
|
|
.datab(\z80_|alu_|op1_low [2]),
|
|
.datac(\z80_|alu_|op1_high [2]),
|
|
.datad(\z80_|execute_|ctl_alu_op_low~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h1105;
|
|
defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y18_N20
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout = (!\z80_|execute_|ctl_alu_core_R~combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ) #
|
|
// ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout & !\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ))))
|
|
|
|
.dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~1_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_core_R~combout ),
|
|
.datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|SYNTHESIZED_WIRE_10~0_combout ),
|
|
.datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|cy_out~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .lut_mask = 16'h3031;
|
|
defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y17_N16
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) #
|
|
// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ))))
|
|
|
|
.dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_core_R~combout ),
|
|
.datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ),
|
|
.datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .lut_mask = 16'hDCDD;
|
|
defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y17_N20
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout = (!\z80_|alu_|alu_op2[3]~2_combout & ((\z80_|execute_|ctl_alu_op_low~combout & (!\z80_|alu_|op1_low [3])) # (!\z80_|execute_|ctl_alu_op_low~combout & ((!\z80_|alu_|op1_high
|
|
// [3])))))
|
|
|
|
.dataa(\z80_|alu_|op1_low [3]),
|
|
.datab(\z80_|alu_|alu_op2[3]~2_combout ),
|
|
.datac(\z80_|alu_|op1_high [3]),
|
|
.datad(\z80_|execute_|ctl_alu_op_low~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h1103;
|
|
defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y17_N10
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout = (\z80_|execute_|ctl_alu_core_R~combout ) # ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ) #
|
|
// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ))))
|
|
|
|
.dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ),
|
|
.datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_core_R~combout ),
|
|
.datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .lut_mask = 16'hF5F4;
|
|
defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y18_N6
|
|
cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~0 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|DFFE_inst_latch_hf~0_combout = (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout & (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[4]~32_combout )))) # (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout
|
|
// & ((\z80_|execute_|ctl_flags_alu~15_combout ) # ((\z80_|execute_|ctl_flags_bus~combout & \z80_|alu_control_|db[4]~32_combout ))))
|
|
|
|
.dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_bus~combout ),
|
|
.datac(\z80_|execute_|ctl_flags_alu~15_combout ),
|
|
.datad(\z80_|alu_control_|db[4]~32_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .lut_mask = 16'hDC50;
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_hf~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y19_N28
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~3 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_hf_we~3_combout = (\z80_|pla_decode_|Equal11~0_combout & (((\z80_|nM1_int~2_combout ) # (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))) # (!\z80_|pla_decode_|Equal11~0_combout & (\z80_|pla_decode_|Equal10~0_combout &
|
|
// ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ))))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal10~0_combout ),
|
|
.datab(\z80_|pla_decode_|Equal11~0_combout ),
|
|
.datac(\z80_|nM1_int~2_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_hf_we~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_hf_we~3 .lut_mask = 16'hEEC0;
|
|
defparam \z80_|execute_|ctl_flags_hf_we~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y18_N28
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_hf_we~4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_hf_we~4_combout = ((\z80_|execute_|ctl_flags_sz_we~6_combout ) # ((\z80_|execute_|ctl_flags_hf_we~3_combout ) # (!\z80_|execute_|ctl_flags_alu~14_combout ))) # (!\z80_|execute_|ctl_flags_xy_we~8_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_xy_we~8_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_sz_we~6_combout ),
|
|
.datac(\z80_|execute_|ctl_flags_alu~14_combout ),
|
|
.datad(\z80_|execute_|ctl_flags_hf_we~3_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_hf_we~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_hf_we~4 .lut_mask = 16'hFFDF;
|
|
defparam \z80_|execute_|ctl_flags_hf_we~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y18_N28
|
|
cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_hf~1 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|DFFE_inst_latch_hf~1_combout = (\z80_|execute_|ctl_flags_hf_we~2_combout & ((\z80_|execute_|ctl_flags_hf_we~4_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout )) # (!\z80_|execute_|ctl_flags_hf_we~4_combout &
|
|
// ((\z80_|alu_flags_|DFFE_inst_latch_hf~q ))))) # (!\z80_|execute_|ctl_flags_hf_we~2_combout & (\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ))
|
|
|
|
.dataa(\z80_|alu_flags_|DFFE_inst_latch_hf~0_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_hf_we~2_combout ),
|
|
.datac(\z80_|alu_flags_|DFFE_inst_latch_hf~q ),
|
|
.datad(\z80_|execute_|ctl_flags_hf_we~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .lut_mask = 16'hAAE2;
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_hf~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X29_Y18_N29
|
|
dffeas \z80_|alu_flags_|DFFE_inst_latch_hf (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|alu_flags_|DFFE_inst_latch_hf~1_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|alu_flags_|DFFE_inst_latch_hf~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_hf .is_wysiwyg = "true";
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_hf .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y14_N16
|
|
cycloneive_lcell_comb \z80_|alu_flags_|flags_hf (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|flags_hf~combout = \z80_|alu_flags_|DFFE_inst_latch_hf~q $ (((\z80_|execute_|ctl_flags_hf_cpl~13_combout ) # ((\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout & !\z80_|alu_flags_|flags_cf~combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_hilo_pla89M1T2_3~combout ),
|
|
.datab(\z80_|execute_|ctl_flags_hf_cpl~13_combout ),
|
|
.datac(\z80_|alu_flags_|DFFE_inst_latch_hf~q ),
|
|
.datad(\z80_|alu_flags_|flags_cf~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|flags_hf~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|flags_hf .lut_mask = 16'h3C1E;
|
|
defparam \z80_|alu_flags_|flags_hf .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y14_N16
|
|
cycloneive_lcell_comb \z80_|alu_control_|db[4]~30 (
|
|
// Equation(s):
|
|
// \z80_|alu_control_|db[4]~30_combout = (\z80_|alu_|db[4]~18_combout & (!\z80_|reg_file_|gdfx_temp0[4]~62_combout & ((\z80_|execute_|ctl_reg_out_lo~8_combout )))) # (!\z80_|alu_|db[4]~18_combout & ((\z80_|execute_|ctl_sw_2u~7_combout ) #
|
|
// ((!\z80_|reg_file_|gdfx_temp0[4]~62_combout & \z80_|execute_|ctl_reg_out_lo~8_combout ))))
|
|
|
|
.dataa(\z80_|alu_|db[4]~18_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp0[4]~62_combout ),
|
|
.datac(\z80_|execute_|ctl_sw_2u~7_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_out_lo~8_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_control_|db[4]~30_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_control_|db[4]~30 .lut_mask = 16'h7350;
|
|
defparam \z80_|alu_control_|db[4]~30 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y14_N10
|
|
cycloneive_lcell_comb \z80_|alu_control_|db[4]~31 (
|
|
// Equation(s):
|
|
// \z80_|alu_control_|db[4]~31_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & (!\z80_|alu_control_|db[4]~30_combout & ((\z80_|alu_flags_|flags_hf~combout ) # (!\z80_|execute_|ctl_flags_oe~2_combout ))))
|
|
|
|
.dataa(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ),
|
|
.datab(\z80_|alu_flags_|flags_hf~combout ),
|
|
.datac(\z80_|execute_|ctl_flags_oe~2_combout ),
|
|
.datad(\z80_|alu_control_|db[4]~30_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_control_|db[4]~31_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_control_|db[4]~31 .lut_mask = 16'h008A;
|
|
defparam \z80_|alu_control_|db[4]~31 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y14_N2
|
|
cycloneive_lcell_comb \z80_|alu_control_|db[4]~32 (
|
|
// Equation(s):
|
|
// \z80_|alu_control_|db[4]~32_combout = ((\z80_|alu_control_|db[4]~31_combout & ((\z80_|bus_control_|db[4]~19_combout ) # (!\z80_|execute_|ctl_sw_1d~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout )
|
|
|
|
.dataa(\z80_|bus_control_|db[4]~19_combout ),
|
|
.datab(\z80_|alu_control_|db[4]~31_combout ),
|
|
.datac(\z80_|execute_|ctl_sw_1d~7_combout ),
|
|
.datad(\z80_|alu_control_|db[6]~11_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_control_|db[4]~32_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_control_|db[4]~32 .lut_mask = 16'h8CFF;
|
|
defparam \z80_|alu_control_|db[4]~32 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y15_N26
|
|
cycloneive_lcell_comb \z80_|alu_|db[4]~17 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db[4]~17_combout = (\z80_|execute_|ctl_reg_out_hi~7_combout & (\z80_|reg_file_|gdfx_temp1[4]~66_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_sw_2d~13_combout )))) # (!\z80_|execute_|ctl_reg_out_hi~7_combout &
|
|
// ((\z80_|alu_control_|db[4]~32_combout ) # ((!\z80_|execute_|ctl_sw_2d~13_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_out_hi~7_combout ),
|
|
.datab(\z80_|alu_control_|db[4]~32_combout ),
|
|
.datac(\z80_|execute_|ctl_sw_2d~13_combout ),
|
|
.datad(\z80_|reg_file_|gdfx_temp1[4]~66_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db[4]~17_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db[4]~17 .lut_mask = 16'hCF45;
|
|
defparam \z80_|alu_|db[4]~17 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y15_N16
|
|
cycloneive_lcell_comb \z80_|alu_|db[4]~18 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db[4]~18_combout = ((\z80_|alu_|db[4]~17_combout & ((\z80_|alu_|db_high[0]~25_combout ) # (!\z80_|execute_|ctl_alu_oe~11_combout )))) # (!\z80_|alu_|db[7]~9_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_oe~11_combout ),
|
|
.datab(\z80_|alu_|db[7]~9_combout ),
|
|
.datac(\z80_|alu_|db[4]~17_combout ),
|
|
.datad(\z80_|alu_|db_high[0]~25_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db[4]~18_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db[4]~18 .lut_mask = 16'hF373;
|
|
defparam \z80_|alu_|db[4]~18 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y16_N16
|
|
cycloneive_lcell_comb \z80_|alu_|db_low[3]~13 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_low[3]~13_combout = (\z80_|ir_|opcode [3] & (\z80_|alu_|db[4]~18_combout )) # (!\z80_|ir_|opcode [3] & ((\z80_|alu_|db[2]~16_combout )))
|
|
|
|
.dataa(\z80_|alu_|db[4]~18_combout ),
|
|
.datab(\z80_|ir_|opcode [3]),
|
|
.datac(gnd),
|
|
.datad(\z80_|alu_|db[2]~16_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_low[3]~13_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_low[3]~13 .lut_mask = 16'hBB88;
|
|
defparam \z80_|alu_|db_low[3]~13 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y16_N10
|
|
cycloneive_lcell_comb \z80_|alu_|db_low[3]~14 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_low[3]~14_combout = ((\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db_low[3]~13_combout )) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db[3]~20_combout )))) #
|
|
// (!\z80_|execute_|ctl_alu_shift_oe~43_combout )
|
|
|
|
.dataa(\z80_|alu_|db_low[3]~13_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ),
|
|
.datad(\z80_|alu_|db[3]~20_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_low[3]~14_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_low[3]~14 .lut_mask = 16'hBF8F;
|
|
defparam \z80_|alu_|db_low[3]~14 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y16_N24
|
|
cycloneive_lcell_comb \z80_|alu_|db_low[3]~17 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_low[3]~17_combout = (\z80_|alu_|db_low[3]~16_combout & (\z80_|alu_|db_low[3]~14_combout & ((\z80_|execute_|ctl_alu_res_oe~3_combout ) # (\z80_|alu_|result_lo [3]))))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_res_oe~3_combout ),
|
|
.datab(\z80_|alu_|db_low[3]~16_combout ),
|
|
.datac(\z80_|alu_|result_lo [3]),
|
|
.datad(\z80_|alu_|db_low[3]~14_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_low[3]~17_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_low[3]~17 .lut_mask = 16'hC800;
|
|
defparam \z80_|alu_|db_low[3]~17 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y16_N14
|
|
cycloneive_lcell_comb \z80_|alu_|db_low[3]~25 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_low[3]~25_combout = (\z80_|alu_|db_low[3]~17_combout ) # ((!\z80_|alu_|db_high[3]~0_combout & !\z80_|execute_|ctl_alu_shift_oe~43_combout ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|alu_|db_high[3]~0_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ),
|
|
.datad(\z80_|alu_|db_low[3]~17_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_low[3]~25_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_low[3]~25 .lut_mask = 16'hFF03;
|
|
defparam \z80_|alu_|db_low[3]~25 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y18_N24
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~4 (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~4_combout = (\z80_|execute_|ctl_alu_op2_sel_lq~combout & ((\z80_|execute_|ctl_alu_op_low~combout & ((\z80_|alu_|op1_low [3]))) # (!\z80_|execute_|ctl_alu_op_low~combout & (\z80_|alu_|op1_high [3]))))
|
|
|
|
.dataa(\z80_|alu_|op1_high [3]),
|
|
.datab(\z80_|execute_|ctl_alu_op_low~combout ),
|
|
.datac(\z80_|alu_|op1_low [3]),
|
|
.datad(\z80_|execute_|ctl_alu_op2_sel_lq~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~4 .lut_mask = 16'hE200;
|
|
defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y18_N28
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~5 (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~5_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & ((\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~4_combout ) # ((\z80_|alu_|db_low[3]~25_combout & \z80_|execute_|ctl_alu_op2_sel_bus~8_combout ))))
|
|
|
|
.dataa(\z80_|alu_|db_low[3]~25_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ),
|
|
.datac(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ),
|
|
.datad(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~5 .lut_mask = 16'h3320;
|
|
defparam \z80_|alu_|b2v_op2_latch_mux_low|Q[3]~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y18_N29
|
|
dffeas \z80_|alu_|op2_low[3] (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|alu_|b2v_op2_latch_mux_low|Q[3]~5_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|alu_|op2_low [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|op2_low[3] .is_wysiwyg = "true";
|
|
defparam \z80_|alu_|op2_low[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y18_N12
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout = (\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & ((\z80_|alu_|db_high[3]~7_combout ) # ((\z80_|execute_|ctl_alu_op2_sel_lq~combout & \z80_|alu_|db_low[3]~25_combout )))) #
|
|
// (!\z80_|execute_|ctl_alu_op2_sel_bus~8_combout & (\z80_|execute_|ctl_alu_op2_sel_lq~combout & (\z80_|alu_|db_low[3]~25_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op2_sel_bus~8_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_op2_sel_lq~combout ),
|
|
.datac(\z80_|alu_|db_low[3]~25_combout ),
|
|
.datad(\z80_|alu_|db_high[3]~7_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 .lut_mask = 16'hEAC0;
|
|
defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y18_N20
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout = (!\z80_|execute_|ctl_alu_op2_sel_zero~combout & \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|execute_|ctl_alu_op2_sel_zero~combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 .lut_mask = 16'h3300;
|
|
defparam \z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y18_N21
|
|
dffeas \z80_|alu_|op2_high[3] (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|alu_|b2v_op2_latch_mux_high|Q[3]~1_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|alu_|b2v_op2_latch_mux_high|ena~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|alu_|op2_high [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|op2_high[3] .is_wysiwyg = "true";
|
|
defparam \z80_|alu_|op2_high[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y17_N2
|
|
cycloneive_lcell_comb \z80_|alu_|alu_op2[3]~2 (
|
|
// Equation(s):
|
|
// \z80_|alu_|alu_op2[3]~2_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [3]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [3]))))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_sel_op2_high~combout ),
|
|
.datab(\z80_|alu_|op2_low [3]),
|
|
.datac(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ),
|
|
.datad(\z80_|alu_|op2_high [3]),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|alu_op2[3]~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|alu_op2[3]~2 .lut_mask = 16'h1EB4;
|
|
defparam \z80_|alu_|alu_op2[3]~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y17_N22
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ) #
|
|
// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout )
|
|
|
|
.dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~1_combout ),
|
|
.datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_10~0_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_core_R~5_combout ),
|
|
.datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 .lut_mask = 16'h5F4F;
|
|
defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y17_N20
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout = (\z80_|alu_|alu_op2[3]~2_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_|alu_op1[3]~2_combout &
|
|
// !\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) # (!\z80_|alu_|alu_op2[3]~2_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[3]~2_combout ) #
|
|
// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ))))
|
|
|
|
.dataa(\z80_|alu_|alu_op2[3]~2_combout ),
|
|
.datab(\z80_|alu_|alu_op1[3]~2_combout ),
|
|
.datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ),
|
|
.datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|SYNTHESIZED_WIRE_1~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .lut_mask = 16'hEF08;
|
|
defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y18_N14
|
|
cycloneive_lcell_comb \z80_|alu_|db_high[3]~3 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_high[3]~3_combout = (\z80_|execute_|ctl_alu_op2_oe~0_combout & (\z80_|alu_|op2_high [3] & ((\z80_|alu_|op1_high [3]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout )))) # (!\z80_|execute_|ctl_alu_op2_oe~0_combout & (((\z80_|alu_|op1_high
|
|
// [3]) # (!\z80_|execute_|ctl_alu_op1_oe~1_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op2_oe~0_combout ),
|
|
.datab(\z80_|alu_|op2_high [3]),
|
|
.datac(\z80_|alu_|op1_high [3]),
|
|
.datad(\z80_|execute_|ctl_alu_op1_oe~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_high[3]~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_high[3]~3 .lut_mask = 16'hD0DD;
|
|
defparam \z80_|alu_|db_high[3]~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y16_N18
|
|
cycloneive_lcell_comb \z80_|alu_|db_high[3]~4 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_high[3]~4_combout = (\z80_|ir_|opcode [3] & ((\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ))) # (!\z80_|ir_|opcode [3] & (\z80_|alu_|db[6]~22_combout ))
|
|
|
|
.dataa(\z80_|alu_|db[6]~22_combout ),
|
|
.datab(\z80_|alu_control_|b2v_inst_shift_mux|out~2_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|ir_|opcode [3]),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_high[3]~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_high[3]~4 .lut_mask = 16'hCCAA;
|
|
defparam \z80_|alu_|db_high[3]~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y16_N28
|
|
cycloneive_lcell_comb \z80_|alu_|db_high[3]~5 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_high[3]~5_combout = (\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & ((\z80_|alu_|db_high[3]~4_combout ))) # (!\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout & (\z80_|alu_|db[7]~12_combout ))
|
|
|
|
.dataa(\z80_|alu_|db[7]~12_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_cf2_sel_shift~4_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|alu_|db_high[3]~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_high[3]~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_high[3]~5 .lut_mask = 16'hEE22;
|
|
defparam \z80_|alu_|db_high[3]~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y17_N28
|
|
cycloneive_lcell_comb \z80_|alu_|db_high[3]~2 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_high[3]~2_combout = ((\z80_|bus_control_|db[3]~21_combout & (\z80_|bus_control_|db[5]~15_combout & \z80_|bus_control_|db[4]~19_combout ))) # (!\z80_|execute_|ctl_alu_bs_oe~combout )
|
|
|
|
.dataa(\z80_|bus_control_|db[3]~21_combout ),
|
|
.datab(\z80_|bus_control_|db[5]~15_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_bs_oe~combout ),
|
|
.datad(\z80_|bus_control_|db[4]~19_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_high[3]~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_high[3]~2 .lut_mask = 16'h8F0F;
|
|
defparam \z80_|alu_|db_high[3]~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y16_N0
|
|
cycloneive_lcell_comb \z80_|alu_|db_high[3]~6 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_high[3]~6_combout = (\z80_|alu_|db_high[3]~3_combout & (\z80_|alu_|db_high[3]~2_combout & ((\z80_|alu_|db_high[3]~5_combout ) # (!\z80_|execute_|ctl_alu_shift_oe~43_combout ))))
|
|
|
|
.dataa(\z80_|alu_|db_high[3]~3_combout ),
|
|
.datab(\z80_|alu_|db_high[3]~5_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_shift_oe~43_combout ),
|
|
.datad(\z80_|alu_|db_high[3]~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_high[3]~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_high[3]~6 .lut_mask = 16'h8A00;
|
|
defparam \z80_|alu_|db_high[3]~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y16_N22
|
|
cycloneive_lcell_comb \z80_|alu_|db_high[3]~7 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db_high[3]~7_combout = ((\z80_|alu_|db_high[3]~6_combout & ((\z80_|execute_|ctl_alu_res_oe~3_combout ) # (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout )))) # (!\z80_|alu_|db_high[3]~1_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_res_oe~3_combout ),
|
|
.datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ),
|
|
.datac(\z80_|alu_|db_high[3]~1_combout ),
|
|
.datad(\z80_|alu_|db_high[3]~6_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db_high[3]~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db_high[3]~7 .lut_mask = 16'hEF0F;
|
|
defparam \z80_|alu_|db_high[3]~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y16_N24
|
|
cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_34 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[7]~19_combout ) # ((\z80_|alu_|db_high[3]~7_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) # (!\z80_|execute_|ctl_flags_bus~combout
|
|
// & (((\z80_|alu_|db_high[3]~7_combout & \z80_|execute_|ctl_flags_alu~15_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_bus~combout ),
|
|
.datab(\z80_|alu_control_|db[7]~19_combout ),
|
|
.datac(\z80_|alu_|db_high[3]~7_combout ),
|
|
.datad(\z80_|execute_|ctl_flags_alu~15_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .lut_mask = 16'hF888;
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_34 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X29_Y16_N25
|
|
dffeas \z80_|alu_flags_|DFFE_inst_latch_sf (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|alu_flags_|SYNTHESIZED_WIRE_34~combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|execute_|ctl_flags_sz_we~8_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|alu_flags_|DFFE_inst_latch_sf~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_sf .is_wysiwyg = "true";
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_sf .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y18_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~5 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_sel_op2_neg~5_combout = ((\z80_|alu_flags_|DFFE_inst_latch_nf~q & ((\z80_|execute_|ctl_flags_cf2_sel_daa~combout ) # (\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout )))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~3_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_hilo_pla77M1T1_3~combout ),
|
|
.datac(\z80_|execute_|ctl_alu_sel_op2_neg~3_combout ),
|
|
.datad(\z80_|alu_flags_|DFFE_inst_latch_nf~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .lut_mask = 16'hEF0F;
|
|
defparam \z80_|execute_|ctl_alu_sel_op2_neg~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y16_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~7 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_sel_op2_neg~7_combout = (\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ) # ((\z80_|pla_decode_|Equal61~2_combout & ((\z80_|nM1_int~2_combout ) # (\z80_|execute_|ctl_eval_cond~0_combout ))))
|
|
|
|
.dataa(\z80_|nM1_int~2_combout ),
|
|
.datab(\z80_|execute_|ctl_pf_sel_nop3pla68M3T1_20~combout ),
|
|
.datac(\z80_|pla_decode_|Equal61~2_combout ),
|
|
.datad(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .lut_mask = 16'hFCEC;
|
|
defparam \z80_|execute_|ctl_alu_sel_op2_neg~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y16_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout = (\z80_|pla_decode_|Equal13~0_combout & (\z80_|execute_|ctl_alu_op_low~22_combout & (\z80_|pla_decode_|Equal55~0_combout & !\z80_|ir_|opcode [3])))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal13~0_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_op_low~22_combout ),
|
|
.datac(\z80_|pla_decode_|Equal55~0_combout ),
|
|
.datad(\z80_|ir_|opcode [3]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 .lut_mask = 16'h0080;
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y16_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~6 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_sel_op2_neg~6_combout = (\z80_|pla_decode_|Equal10~0_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((\z80_|execute_|ixy_d~7_combout ) # (\z80_|nM1_int~2_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_state_alu~2_combout ),
|
|
.datab(\z80_|execute_|ixy_d~7_combout ),
|
|
.datac(\z80_|pla_decode_|Equal10~0_combout ),
|
|
.datad(\z80_|nM1_int~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .lut_mask = 16'hF0E0;
|
|
defparam \z80_|execute_|ctl_alu_sel_op2_neg~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y16_N2
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~8 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_sel_op2_neg~8_combout = ((\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ) # (\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ))) # (!\z80_|execute_|ctl_alu_op_low~48_combout
|
|
// )
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op_low~48_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_sel_op2_neg~7_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_sys_hilo_nop3pla68M2T2_3~combout ),
|
|
.datad(\z80_|execute_|ctl_alu_sel_op2_neg~6_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .lut_mask = 16'hFFFD;
|
|
defparam \z80_|execute_|ctl_alu_sel_op2_neg~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y18_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~11 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_sel_op2_neg~11_combout = (\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ) # (((\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ) # (!\z80_|execute_|ctl_alu_sel_op2_neg~10_combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_sel_op2_neg~5_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_sel_op2_neg~9_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_sel_op2_neg~10_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_sel_op2_neg~8_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .lut_mask = 16'hFFBF;
|
|
defparam \z80_|execute_|ctl_alu_sel_op2_neg~11 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y14_N6
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~12 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_sel_op2_neg~12_combout = (((\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ) # (\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout )) # (!\z80_|execute_|ctl_alu_sel_op2_neg~2_combout )) # (!\z80_|execute_|ctl_reg_out_hi~4_combout
|
|
// )
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_out_hi~4_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_sys_hilo_ixy_dT5_7~combout ),
|
|
.datad(\z80_|execute_|ctl_reg_gp_hilo_ixy_dT4_2~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .lut_mask = 16'hFFF7;
|
|
defparam \z80_|execute_|ctl_alu_sel_op2_neg~12 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y18_N26
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_sel_op2_neg~15 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_sel_op2_neg~15_combout = ((\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_sf~q & \z80_|execute_|ctl_alu_sel_op2_neg~12_combout ))) # (!\z80_|execute_|ctl_alu_sel_op2_neg~18_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_sel_op2_neg~18_combout ),
|
|
.datab(\z80_|alu_flags_|DFFE_inst_latch_sf~q ),
|
|
.datac(\z80_|execute_|ctl_alu_sel_op2_neg~11_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_sel_op2_neg~12_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .lut_mask = 16'hFDF5;
|
|
defparam \z80_|execute_|ctl_alu_sel_op2_neg~15 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y17_N26
|
|
cycloneive_lcell_comb \z80_|alu_|alu_op2[2]~0 (
|
|
// Equation(s):
|
|
// \z80_|alu_|alu_op2[2]~0_combout = \z80_|execute_|ctl_alu_sel_op2_neg~15_combout $ (((\z80_|execute_|ctl_alu_sel_op2_high~combout & ((\z80_|alu_|op2_high [2]))) # (!\z80_|execute_|ctl_alu_sel_op2_high~combout & (\z80_|alu_|op2_low [2]))))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_sel_op2_high~combout ),
|
|
.datab(\z80_|execute_|ctl_alu_sel_op2_neg~15_combout ),
|
|
.datac(\z80_|alu_|op2_low [2]),
|
|
.datad(\z80_|alu_|op2_high [2]),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|alu_op2[2]~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|alu_op2[2]~0 .lut_mask = 16'h369C;
|
|
defparam \z80_|alu_|alu_op2[2]~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y17_N18
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout = ((!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ) #
|
|
// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|execute_|ctl_alu_core_R~5_combout )
|
|
|
|
.dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~1_combout ),
|
|
.datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_10~0_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_core_R~5_combout ),
|
|
.datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .lut_mask = 16'h4F5F;
|
|
defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y17_N24
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout = (\z80_|alu_|alu_op2[2]~0_combout & ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ) # ((\z80_|alu_|alu_op1[2]~1_combout &
|
|
// \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout )))) # (!\z80_|alu_|alu_op2[2]~0_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout & ((\z80_|alu_|alu_op1[2]~1_combout ) #
|
|
// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ))))
|
|
|
|
.dataa(\z80_|alu_|alu_op2[2]~0_combout ),
|
|
.datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_1~combout ),
|
|
.datac(\z80_|alu_|alu_op1[2]~1_combout ),
|
|
.datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|SYNTHESIZED_WIRE_4~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .lut_mask = 16'hECC8;
|
|
defparam \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X28_Y17_N11
|
|
dffeas \z80_|alu_control_|DFFE_latch_pf_tmp (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|alu_|alu_parity_out~1_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|execute_|ctl_alu_op_low~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|alu_control_|DFFE_latch_pf_tmp~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_control_|DFFE_latch_pf_tmp .is_wysiwyg = "true";
|
|
defparam \z80_|alu_control_|DFFE_latch_pf_tmp .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y17_N8
|
|
cycloneive_lcell_comb \z80_|alu_|alu_parity_out~0 (
|
|
// Equation(s):
|
|
// \z80_|alu_|alu_parity_out~0_combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout $ (((\z80_|execute_|ctl_alu_op_low~29_combout & (!\z80_|alu_control_|DFFE_latch_pf_tmp~q & !\z80_|execute_|ctl_alu_op_low~41_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op_low~29_combout ),
|
|
.datab(\z80_|alu_control_|DFFE_latch_pf_tmp~q ),
|
|
.datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_0|result~0_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op_low~41_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|alu_parity_out~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|alu_parity_out~0 .lut_mask = 16'hF0D2;
|
|
defparam \z80_|alu_|alu_parity_out~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y17_N10
|
|
cycloneive_lcell_comb \z80_|alu_|alu_parity_out~1 (
|
|
// Equation(s):
|
|
// \z80_|alu_|alu_parity_out~1_combout = \z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout $ (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout $ (\z80_|alu_|alu_parity_out~0_combout $
|
|
// (!\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout )))
|
|
|
|
.dataa(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|result~0_combout ),
|
|
.datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|result~0_combout ),
|
|
.datac(\z80_|alu_|alu_parity_out~0_combout ),
|
|
.datad(\z80_|alu_|b2v_core|b2v_alu_slice_bit_1|result~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|alu_parity_out~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|alu_parity_out~1 .lut_mask = 16'h9669;
|
|
defparam \z80_|alu_|alu_parity_out~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y17_N24
|
|
cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~4 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|DFFE_inst_latch_pf~4_combout = (\z80_|execute_|ctl_pf_sel[0]~2_combout & (((!\z80_|pla_decode_|Equal62~3_combout & !\z80_|execute_|ctl_alu_op_low~27_combout )) # (!\z80_|nM1_int~2_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_pf_sel[0]~2_combout ),
|
|
.datab(\z80_|pla_decode_|Equal62~3_combout ),
|
|
.datac(\z80_|nM1_int~2_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op_low~27_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .lut_mask = 16'h0A2A;
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_pf~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y17_N18
|
|
cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~5 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|DFFE_inst_latch_pf~5_combout = (\z80_|execute_|ctl_pf_sel[0]~3_combout & (!\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout $
|
|
// (\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout )))) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout & (\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout $ ((\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_pf_sel[0]~3_combout ),
|
|
.datab(\z80_|alu_|b2v_core|b2v_alu_slice_bit_3|cy_out~0_combout ),
|
|
.datac(\z80_|alu_|b2v_core|b2v_alu_slice_bit_2|cy_out~0_combout ),
|
|
.datad(\z80_|alu_flags_|DFFE_inst_latch_pf~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .lut_mask = 16'h143C;
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_pf~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y17_N16
|
|
cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~6 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|DFFE_inst_latch_pf~6_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout & (((!\z80_|pla_decode_|Equal69~0_combout & \z80_|execute_|ctl_flags_bus~1_combout )) # (!\z80_|nM1_int~2_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal69~0_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_bus~1_combout ),
|
|
.datac(\z80_|nM1_int~2_combout ),
|
|
.datad(\z80_|alu_flags_|DFFE_inst_latch_pf~5_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .lut_mask = 16'h4F00;
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_pf~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y17_N6
|
|
cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~1 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|DFFE_inst_latch_pf~1_combout = (\z80_|execute_|ctl_pf_sel[0]~3_combout & (!\z80_|execute_|ctl_alu_op_low~27_combout & (\z80_|execute_|ctl_pf_sel[0]~2_combout & !\z80_|pla_decode_|Equal62~3_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_pf_sel[0]~3_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_op_low~27_combout ),
|
|
.datac(\z80_|execute_|ctl_pf_sel[0]~2_combout ),
|
|
.datad(\z80_|pla_decode_|Equal62~3_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .lut_mask = 16'h0020;
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_pf~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y13_N30
|
|
cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~2 (
|
|
// Equation(s):
|
|
// \z80_|decode_state_|DFFE_instNonRep~2_combout = (!\z80_|address_latch_|Q [6] & (!\z80_|address_latch_|Q [5] & (!\z80_|address_latch_|Q [4] & !\z80_|address_latch_|Q [7])))
|
|
|
|
.dataa(\z80_|address_latch_|Q [6]),
|
|
.datab(\z80_|address_latch_|Q [5]),
|
|
.datac(\z80_|address_latch_|Q [4]),
|
|
.datad(\z80_|address_latch_|Q [7]),
|
|
.cin(gnd),
|
|
.combout(\z80_|decode_state_|DFFE_instNonRep~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|decode_state_|DFFE_instNonRep~2 .lut_mask = 16'h0001;
|
|
defparam \z80_|decode_state_|DFFE_instNonRep~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y13_N0
|
|
cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~1 (
|
|
// Equation(s):
|
|
// \z80_|decode_state_|DFFE_instNonRep~1_combout = (!\z80_|address_latch_|Q [9] & (!\z80_|address_latch_|Q [8] & (!\z80_|address_latch_|Q [11] & !\z80_|address_latch_|Q [10])))
|
|
|
|
.dataa(\z80_|address_latch_|Q [9]),
|
|
.datab(\z80_|address_latch_|Q [8]),
|
|
.datac(\z80_|address_latch_|Q [11]),
|
|
.datad(\z80_|address_latch_|Q [10]),
|
|
.cin(gnd),
|
|
.combout(\z80_|decode_state_|DFFE_instNonRep~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|decode_state_|DFFE_instNonRep~1 .lut_mask = 16'h0001;
|
|
defparam \z80_|decode_state_|DFFE_instNonRep~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y11_N4
|
|
cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~3 (
|
|
// Equation(s):
|
|
// \z80_|decode_state_|DFFE_instNonRep~3_combout = (\z80_|address_latch_|Q [0] & (!\z80_|address_latch_|Q [2] & (!\z80_|address_latch_|Q [3] & !\z80_|address_latch_|Q [1])))
|
|
|
|
.dataa(\z80_|address_latch_|Q [0]),
|
|
.datab(\z80_|address_latch_|Q [2]),
|
|
.datac(\z80_|address_latch_|Q [3]),
|
|
.datad(\z80_|address_latch_|Q [1]),
|
|
.cin(gnd),
|
|
.combout(\z80_|decode_state_|DFFE_instNonRep~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|decode_state_|DFFE_instNonRep~3 .lut_mask = 16'h0002;
|
|
defparam \z80_|decode_state_|DFFE_instNonRep~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y13_N28
|
|
cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~0 (
|
|
// Equation(s):
|
|
// \z80_|decode_state_|DFFE_instNonRep~0_combout = (!\z80_|address_latch_|Q [14] & (!\z80_|address_latch_|Q [15] & (!\z80_|address_latch_|Q [12] & !\z80_|address_latch_|Q [13])))
|
|
|
|
.dataa(\z80_|address_latch_|Q [14]),
|
|
.datab(\z80_|address_latch_|Q [15]),
|
|
.datac(\z80_|address_latch_|Q [12]),
|
|
.datad(\z80_|address_latch_|Q [13]),
|
|
.cin(gnd),
|
|
.combout(\z80_|decode_state_|DFFE_instNonRep~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|decode_state_|DFFE_instNonRep~0 .lut_mask = 16'h0001;
|
|
defparam \z80_|decode_state_|DFFE_instNonRep~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y13_N24
|
|
cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~4 (
|
|
// Equation(s):
|
|
// \z80_|decode_state_|DFFE_instNonRep~4_combout = (\z80_|decode_state_|DFFE_instNonRep~2_combout & (\z80_|decode_state_|DFFE_instNonRep~1_combout & (\z80_|decode_state_|DFFE_instNonRep~3_combout & \z80_|decode_state_|DFFE_instNonRep~0_combout )))
|
|
|
|
.dataa(\z80_|decode_state_|DFFE_instNonRep~2_combout ),
|
|
.datab(\z80_|decode_state_|DFFE_instNonRep~1_combout ),
|
|
.datac(\z80_|decode_state_|DFFE_instNonRep~3_combout ),
|
|
.datad(\z80_|decode_state_|DFFE_instNonRep~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|decode_state_|DFFE_instNonRep~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|decode_state_|DFFE_instNonRep~4 .lut_mask = 16'h8000;
|
|
defparam \z80_|decode_state_|DFFE_instNonRep~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y15_N20
|
|
cycloneive_lcell_comb \z80_|decode_state_|DFFE_instNonRep~5 (
|
|
// Equation(s):
|
|
// \z80_|decode_state_|DFFE_instNonRep~5_combout = (\z80_|execute_|ctl_flags_bus~1_combout & (((\z80_|decode_state_|DFFE_instNonRep~q )))) # (!\z80_|execute_|ctl_flags_bus~1_combout & ((\z80_|execute_|ixy_d~9_combout &
|
|
// (\z80_|decode_state_|DFFE_instNonRep~4_combout )) # (!\z80_|execute_|ixy_d~9_combout & ((\z80_|decode_state_|DFFE_instNonRep~q )))))
|
|
|
|
.dataa(\z80_|decode_state_|DFFE_instNonRep~4_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_bus~1_combout ),
|
|
.datac(\z80_|decode_state_|DFFE_instNonRep~q ),
|
|
.datad(\z80_|execute_|ixy_d~9_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|decode_state_|DFFE_instNonRep~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|decode_state_|DFFE_instNonRep~5 .lut_mask = 16'hE2F0;
|
|
defparam \z80_|decode_state_|DFFE_instNonRep~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y15_N21
|
|
dffeas \z80_|decode_state_|DFFE_instNonRep (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|decode_state_|DFFE_instNonRep~5_combout ),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|decode_state_|DFFE_instNonRep~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|decode_state_|DFFE_instNonRep .is_wysiwyg = "true";
|
|
defparam \z80_|decode_state_|DFFE_instNonRep .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y17_N12
|
|
cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~2 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|DFFE_inst_latch_pf~2_combout = (\z80_|pla_decode_|Equal69~0_combout & ((\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout & ((\z80_|interrupts_|DFFE_instIFF2~q ))) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout &
|
|
// (!\z80_|decode_state_|DFFE_instNonRep~q ))))
|
|
|
|
.dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~1_combout ),
|
|
.datab(\z80_|decode_state_|DFFE_instNonRep~q ),
|
|
.datac(\z80_|interrupts_|DFFE_instIFF2~q ),
|
|
.datad(\z80_|pla_decode_|Equal69~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .lut_mask = 16'hB100;
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_pf~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y17_N14
|
|
cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~3 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|DFFE_inst_latch_pf~3_combout = (\z80_|nM1_int~2_combout & ((\z80_|execute_|ctl_flags_bus~1_combout & (\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout )) # (!\z80_|execute_|ctl_flags_bus~1_combout &
|
|
// ((!\z80_|decode_state_|DFFE_instNonRep~q )))))
|
|
|
|
.dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~2_combout ),
|
|
.datab(\z80_|nM1_int~2_combout ),
|
|
.datac(\z80_|decode_state_|DFFE_instNonRep~q ),
|
|
.datad(\z80_|execute_|ctl_flags_bus~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .lut_mask = 16'h880C;
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_pf~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y17_N2
|
|
cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~7 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|DFFE_inst_latch_pf~7_combout = (\z80_|pla_decode_|Equal69~0_combout ) # (((\z80_|pla_decode_|Equal62~3_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout )) # (!\z80_|execute_|ctl_flags_bus~1_combout ))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal69~0_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_bus~1_combout ),
|
|
.datac(\z80_|pla_decode_|Equal62~3_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op_low~27_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .lut_mask = 16'hFFFB;
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_pf~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y17_N0
|
|
cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~8 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout = (\z80_|execute_|ctl_pf_sel[0]~2_combout & (\z80_|execute_|ctl_pf_sel[0]~3_combout & ((!\z80_|nM1_int~2_combout ) # (!\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_pf_sel[0]~2_combout ),
|
|
.datab(\z80_|alu_flags_|DFFE_inst_latch_pf~7_combout ),
|
|
.datac(\z80_|nM1_int~2_combout ),
|
|
.datad(\z80_|execute_|ctl_pf_sel[0]~3_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .lut_mask = 16'h2A00;
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_pf~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y17_N26
|
|
cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~9 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ) # ((\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ) # ((\z80_|alu_|alu_parity_out~1_combout & \z80_|alu_flags_|DFFE_inst_latch_pf~8_combout )))
|
|
|
|
.dataa(\z80_|alu_|alu_parity_out~1_combout ),
|
|
.datab(\z80_|alu_flags_|DFFE_inst_latch_pf~6_combout ),
|
|
.datac(\z80_|alu_flags_|DFFE_inst_latch_pf~3_combout ),
|
|
.datad(\z80_|alu_flags_|DFFE_inst_latch_pf~8_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .lut_mask = 16'hFEFC;
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_pf~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y15_N0
|
|
cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~0 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|DFFE_inst_latch_pf~0_combout = (\z80_|execute_|ctl_flags_pf_we~9_combout & (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[2]~29_combout )))) # (!\z80_|execute_|ctl_flags_pf_we~9_combout &
|
|
// (((\z80_|alu_flags_|DFFE_inst_latch_pf~q ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_bus~combout ),
|
|
.datab(\z80_|alu_flags_|DFFE_inst_latch_pf~q ),
|
|
.datac(\z80_|execute_|ctl_flags_pf_we~9_combout ),
|
|
.datad(\z80_|alu_control_|db[2]~29_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .lut_mask = 16'hAC0C;
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_pf~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y15_N16
|
|
cycloneive_lcell_comb \z80_|alu_flags_|DFFE_inst_latch_pf~10 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|DFFE_inst_latch_pf~10_combout = (\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ) # ((\z80_|execute_|ctl_flags_alu~15_combout & (\z80_|execute_|ctl_flags_pf_we~9_combout & \z80_|alu_flags_|DFFE_inst_latch_pf~9_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_alu~15_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_pf_we~9_combout ),
|
|
.datac(\z80_|alu_flags_|DFFE_inst_latch_pf~9_combout ),
|
|
.datad(\z80_|alu_flags_|DFFE_inst_latch_pf~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .lut_mask = 16'hFF80;
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_pf~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X31_Y15_N17
|
|
dffeas \z80_|alu_flags_|DFFE_inst_latch_pf (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|alu_flags_|DFFE_inst_latch_pf~10_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|alu_flags_|DFFE_inst_latch_pf~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_pf .is_wysiwyg = "true";
|
|
defparam \z80_|alu_flags_|DFFE_inst_latch_pf .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y13_N6
|
|
cycloneive_lcell_comb \z80_|alu_control_|sel[1]~0 (
|
|
// Equation(s):
|
|
// \z80_|alu_control_|sel[1]~0_combout = (\z80_|ir_|opcode [5] & (((!\z80_|pla_decode_|Equal6~0_combout ) # (!\z80_|pla_decode_|Equal40~0_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.datab(\z80_|ir_|opcode [5]),
|
|
.datac(\z80_|pla_decode_|Equal40~0_combout ),
|
|
.datad(\z80_|pla_decode_|Equal6~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_control_|sel[1]~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_control_|sel[1]~0 .lut_mask = 16'h4CCC;
|
|
defparam \z80_|alu_control_|sel[1]~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y16_N18
|
|
cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~0 (
|
|
// Equation(s):
|
|
// \z80_|alu_control_|b2v_inst_cond_mux|out~0_combout = (\z80_|alu_control_|sel[1]~0_combout & (((\z80_|ir_|opcode [4])))) # (!\z80_|alu_control_|sel[1]~0_combout & ((\z80_|ir_|opcode [4] & ((\z80_|alu_flags_|flags_cf~combout ))) # (!\z80_|ir_|opcode [4]
|
|
// & (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ))))
|
|
|
|
.dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ),
|
|
.datab(\z80_|alu_flags_|flags_cf~combout ),
|
|
.datac(\z80_|alu_control_|sel[1]~0_combout ),
|
|
.datad(\z80_|ir_|opcode [4]),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .lut_mask = 16'hFC0A;
|
|
defparam \z80_|alu_control_|b2v_inst_cond_mux|out~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y16_N16
|
|
cycloneive_lcell_comb \z80_|alu_control_|b2v_inst_cond_mux|out~1 (
|
|
// Equation(s):
|
|
// \z80_|alu_control_|b2v_inst_cond_mux|out~1_combout = (\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout & (((\z80_|alu_flags_|DFFE_inst_latch_sf~q ) # (!\z80_|alu_control_|sel[1]~0_combout )))) # (!\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout &
|
|
// (\z80_|alu_flags_|DFFE_inst_latch_pf~q & (\z80_|alu_control_|sel[1]~0_combout )))
|
|
|
|
.dataa(\z80_|alu_flags_|DFFE_inst_latch_pf~q ),
|
|
.datab(\z80_|alu_control_|b2v_inst_cond_mux|out~0_combout ),
|
|
.datac(\z80_|alu_control_|sel[1]~0_combout ),
|
|
.datad(\z80_|alu_flags_|DFFE_inst_latch_sf~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .lut_mask = 16'hEC2C;
|
|
defparam \z80_|alu_control_|b2v_inst_cond_mux|out~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y16_N26
|
|
cycloneive_lcell_comb \z80_|alu_control_|flags_cond_true~0 (
|
|
// Equation(s):
|
|
// \z80_|alu_control_|flags_cond_true~0_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (\z80_|ir_|opcode [3] $ (((!\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ))))) # (!\z80_|execute_|ctl_eval_cond~0_combout &
|
|
// (((\z80_|alu_control_|flags_cond_true~q ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.datab(\z80_|ir_|opcode [3]),
|
|
.datac(\z80_|alu_control_|flags_cond_true~q ),
|
|
.datad(\z80_|alu_control_|b2v_inst_cond_mux|out~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_control_|flags_cond_true~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_control_|flags_cond_true~0 .lut_mask = 16'hD872;
|
|
defparam \z80_|alu_control_|flags_cond_true~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X29_Y16_N27
|
|
dffeas \z80_|alu_control_|flags_cond_true (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|alu_control_|flags_cond_true~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|alu_control_|flags_cond_true~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_control_|flags_cond_true .is_wysiwyg = "true";
|
|
defparam \z80_|alu_control_|flags_cond_true .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y12_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~20 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sel_wz~20_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & (\z80_|pla_decode_|Equal35~0_combout & \z80_|alu_control_|flags_cond_true~q )))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.datab(\z80_|sequencer_|DFFE_M3_ff~q ),
|
|
.datac(\z80_|pla_decode_|Equal35~0_combout ),
|
|
.datad(\z80_|alu_control_|flags_cond_true~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sel_wz~20_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sel_wz~20 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|ctl_reg_sel_wz~20 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y12_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~1 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_sw_4d~1_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ) # ((\z80_|execute_|ctl_reg_sel_wz~20_combout ) # ((\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ctl_al_we~14_combout )))
|
|
|
|
.dataa(\z80_|execute_|ixy_d~7_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_sys_hilo_pla57M1T4_4~combout ),
|
|
.datac(\z80_|execute_|ctl_reg_sel_wz~20_combout ),
|
|
.datad(\z80_|execute_|ctl_al_we~14_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_sw_4d~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_sw_4d~1 .lut_mask = 16'hFCFE;
|
|
defparam \z80_|execute_|ctl_sw_4d~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y12_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_sw_4d~6 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_sw_4d~6_combout = (\z80_|execute_|ctl_sw_4d~0_combout ) # ((\z80_|execute_|ctl_sw_4d~1_combout ) # (!\z80_|execute_|ctl_sw_4d~5_combout ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|execute_|ctl_sw_4d~0_combout ),
|
|
.datac(\z80_|execute_|ctl_sw_4d~1_combout ),
|
|
.datad(\z80_|execute_|ctl_sw_4d~5_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_sw_4d~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_sw_4d~6 .lut_mask = 16'hFCFF;
|
|
defparam \z80_|execute_|ctl_sw_4d~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y12_N17
|
|
dffeas \z80_|reg_file_|b2v_latch_pc_lo|latch[1] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|db_lo_as[1]~6_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_75~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_pc_lo|latch[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y12_N16
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~4 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_lo_as[1]~4_combout = (\z80_|execute_|ctl_sw_4d~6_combout & (\z80_|reg_file_|gdfx_temp0[1]~32_combout & ((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout )))) #
|
|
// (!\z80_|execute_|ctl_sw_4d~6_combout & (((\z80_|reg_file_|b2v_latch_pc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_sw_4d~6_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp0[1]~32_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_pc_lo|latch [1]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_74~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_lo_as[1]~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_lo_as[1]~4 .lut_mask = 16'hD0DD;
|
|
defparam \z80_|reg_file_|db_lo_as[1]~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y12_N23
|
|
dffeas \z80_|reg_file_|b2v_latch_ir_lo|latch[1] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_file_|db_lo_as[1]~6_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_63~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_ir_lo|latch[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y12_N20
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~5 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_lo_as[1]~5_combout = (\z80_|reg_file_|db_lo_as[1]~4_combout & ((\z80_|reg_file_|b2v_latch_ir_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout )))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|reg_file_|db_lo_as[1]~4_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_ir_lo|latch [1]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_62~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_lo_as[1]~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_lo_as[1]~5 .lut_mask = 16'hC0CC;
|
|
defparam \z80_|reg_file_|db_lo_as[1]~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y11_N18
|
|
cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout = \z80_|address_latch_|Q [1] $ (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout )
|
|
|
|
.dataa(\z80_|address_latch_|Q [1]),
|
|
.datab(gnd),
|
|
.datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|SYNTHESIZED_WIRE_0~0_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .lut_mask = 16'h5A5A;
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y12_N22
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_lo_as[1]~6 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_lo_as[1]~6_combout = ((\z80_|reg_file_|db_lo_as[1]~5_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_lo_as[0]~2_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_bus_inc_oe~43_combout ),
|
|
.datab(\z80_|reg_file_|db_lo_as[1]~5_combout ),
|
|
.datac(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ),
|
|
.datad(\z80_|reg_file_|db_lo_as[0]~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_lo_as[1]~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_lo_as[1]~6 .lut_mask = 16'hC4FF;
|
|
defparam \z80_|reg_file_|db_lo_as[1]~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y12_N7
|
|
dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[1] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y12_N6
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~29 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[1]~29_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [1] & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (((\z80_|alu_control_|db[1]~26_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_in_lo~8_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [1]),
|
|
.datad(\z80_|alu_control_|db[1]~26_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[1]~29_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[1]~29 .lut_mask = 16'hF531;
|
|
defparam \z80_|reg_file_|gdfx_temp0[1]~29 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X31_Y12_N15
|
|
dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[1] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X31_Y12_N5
|
|
dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[1] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y12_N4
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~28 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[1]~28_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (\z80_|reg_file_|b2v_latch_iy_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout & (((\z80_|reg_file_|b2v_latch_ix_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ),
|
|
.datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [1]),
|
|
.datac(\z80_|reg_file_|b2v_latch_ix_lo|latch [1]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[1]~28_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[1]~28 .lut_mask = 16'hD0DD;
|
|
defparam \z80_|reg_file_|gdfx_temp0[1]~28 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y14_N1
|
|
dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[1] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y14_N19
|
|
dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y14_N18
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~26 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[1]~26_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [1]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ),
|
|
.datab(\z80_|reg_file_|b2v_latch_bc_lo|latch [1]),
|
|
.datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [1]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[1]~26_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[1]~26 .lut_mask = 16'hC4F5;
|
|
defparam \z80_|reg_file_|gdfx_temp0[1]~26 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y13_N19
|
|
dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[1] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y13_N18
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~27 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[1]~27_combout = (\z80_|reg_file_|gdfx_temp0[1]~26_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|reg_file_|gdfx_temp0[1]~26_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [1]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[1]~27_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[1]~27 .lut_mask = 16'hC0CC;
|
|
defparam \z80_|reg_file_|gdfx_temp0[1]~27 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y12_N14
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~30 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[1]~30_combout = (\z80_|reg_file_|gdfx_temp0[1]~29_combout & (\z80_|reg_file_|gdfx_temp0[1]~28_combout & \z80_|reg_file_|gdfx_temp0[1]~27_combout ))
|
|
|
|
.dataa(\z80_|reg_file_|gdfx_temp0[1]~29_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp0[1]~28_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|reg_file_|gdfx_temp0[1]~27_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[1]~30_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[1]~30 .lut_mask = 16'h8800;
|
|
defparam \z80_|reg_file_|gdfx_temp0[1]~30 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X30_Y12_N7
|
|
dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[1] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X30_Y12_N1
|
|
dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y12_N0
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~24 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[1]~24_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [1] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [1] &
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [1]),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [1]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[1]~24_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[1]~24 .lut_mask = 16'hA2F3;
|
|
defparam \z80_|reg_file_|gdfx_temp0[1]~24 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X31_Y11_N5
|
|
dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[1] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X31_Y11_N19
|
|
dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[1] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_de_lo|latch [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_de_lo|latch[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y11_N4
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~23 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[1]~23_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [1]),
|
|
.datad(\z80_|reg_file_|b2v_latch_de_lo|latch [1]),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[1]~23_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[1]~23 .lut_mask = 16'hF351;
|
|
defparam \z80_|reg_file_|gdfx_temp0[1]~23 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y11_N23
|
|
dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[1] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y11_N25
|
|
dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[1] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[1]~32_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_af_lo|latch [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_af_lo|latch[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y11_N22
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~25 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[1]~25_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [1] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [1]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [1])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [1]),
|
|
.datad(\z80_|reg_file_|b2v_latch_af_lo|latch [1]),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[1]~25_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[1]~25 .lut_mask = 16'hF531;
|
|
defparam \z80_|reg_file_|gdfx_temp0[1]~25 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y11_N30
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~31 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[1]~31_combout = (\z80_|reg_file_|gdfx_temp0[1]~30_combout & (\z80_|reg_file_|gdfx_temp0[1]~24_combout & (\z80_|reg_file_|gdfx_temp0[1]~23_combout & \z80_|reg_file_|gdfx_temp0[1]~25_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|gdfx_temp0[1]~30_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp0[1]~24_combout ),
|
|
.datac(\z80_|reg_file_|gdfx_temp0[1]~23_combout ),
|
|
.datad(\z80_|reg_file_|gdfx_temp0[1]~25_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[1]~31_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[1]~31 .lut_mask = 16'h8000;
|
|
defparam \z80_|reg_file_|gdfx_temp0[1]~31 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y11_N8
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[1]~32 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[1]~32_combout = ((\z80_|reg_file_|gdfx_temp0[1]~31_combout & ((\z80_|reg_file_|db_lo_as[1]~6_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_sw_4u~6_combout ),
|
|
.datab(\z80_|reg_file_|db_lo_as[1]~6_combout ),
|
|
.datac(\z80_|reg_file_|gdfx_temp0[1]~31_combout ),
|
|
.datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[1]~32_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[1]~32 .lut_mask = 16'hD0FF;
|
|
defparam \z80_|reg_file_|gdfx_temp0[1]~32 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y14_N30
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_lo_ds[1]~1 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_lo_ds[1]~1_combout = (\z80_|reg_file_|gdfx_temp0[1]~32_combout ) # ((!\z80_|execute_|ctl_reg_out_lo~5_combout & (\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout & \z80_|execute_|ctl_reg_out_lo~7_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_out_lo~5_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_hilo[1]~37_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_out_lo~7_combout ),
|
|
.datad(\z80_|reg_file_|gdfx_temp0[1]~32_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_lo_ds[1]~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_lo_ds[1]~1 .lut_mask = 16'hFF40;
|
|
defparam \z80_|reg_file_|db_lo_ds[1]~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y14_N16
|
|
cycloneive_lcell_comb \z80_|alu_control_|db[1]~25 (
|
|
// Equation(s):
|
|
// \z80_|alu_control_|db[1]~25_combout = (\z80_|reg_file_|db_lo_ds[1]~1_combout & (((\z80_|bus_control_|db[1]~11_combout & !\z80_|execute_|ctl_sw_mask543_en~0_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|db_lo_ds[1]~1_combout ),
|
|
.datab(\z80_|bus_control_|db[1]~11_combout ),
|
|
.datac(\z80_|execute_|ctl_sw_1d~7_combout ),
|
|
.datad(\z80_|execute_|ctl_sw_mask543_en~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_control_|db[1]~25_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_control_|db[1]~25 .lut_mask = 16'h0A8A;
|
|
defparam \z80_|alu_control_|db[1]~25 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y14_N4
|
|
cycloneive_lcell_comb \z80_|alu_control_|db[1]~24 (
|
|
// Equation(s):
|
|
// \z80_|alu_control_|db[1]~24_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (((!\z80_|alu_|db[1]~10_combout & \z80_|execute_|ctl_sw_2u~7_combout )) # (!\z80_|alu_flags_|DFFE_inst_latch_nf~q ))) # (!\z80_|execute_|ctl_flags_oe~2_combout &
|
|
// (!\z80_|alu_|db[1]~10_combout & (\z80_|execute_|ctl_sw_2u~7_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_oe~2_combout ),
|
|
.datab(\z80_|alu_|db[1]~10_combout ),
|
|
.datac(\z80_|execute_|ctl_sw_2u~7_combout ),
|
|
.datad(\z80_|alu_flags_|DFFE_inst_latch_nf~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_control_|db[1]~24_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_control_|db[1]~24 .lut_mask = 16'h30BA;
|
|
defparam \z80_|alu_control_|db[1]~24 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y14_N18
|
|
cycloneive_lcell_comb \z80_|alu_control_|db[1]~26 (
|
|
// Equation(s):
|
|
// \z80_|alu_control_|db[1]~26_combout = ((\z80_|alu_control_|db[1]~25_combout & (!\z80_|alu_control_|db[1]~24_combout & \z80_|alu_control_|db[2]~23_combout ))) # (!\z80_|alu_control_|db[6]~11_combout )
|
|
|
|
.dataa(\z80_|alu_control_|db[1]~25_combout ),
|
|
.datab(\z80_|alu_control_|db[1]~24_combout ),
|
|
.datac(\z80_|alu_control_|db[2]~23_combout ),
|
|
.datad(\z80_|alu_control_|db[6]~11_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_control_|db[1]~26_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_control_|db[1]~26 .lut_mask = 16'h20FF;
|
|
defparam \z80_|alu_control_|db[1]~26 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y13_N2
|
|
cycloneive_lcell_comb \z80_|bus_control_|db[1]~10 (
|
|
// Equation(s):
|
|
// \z80_|bus_control_|db[1]~10_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[1]~26_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))
|
|
|
|
.dataa(\z80_|bus_control_|db[0]~4_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_bus_db_we~7_combout ),
|
|
.datad(\z80_|alu_control_|db[1]~26_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|bus_control_|db[1]~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|bus_control_|db[1]~10 .lut_mask = 16'hAA0A;
|
|
defparam \z80_|bus_control_|db[1]~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y16_N18
|
|
cycloneive_lcell_comb \z80_|execute_|nextM~4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|nextM~4_combout = ((!\z80_|execute_|ctl_mRead~34_combout & ((!\z80_|pla_decode_|Equal24~0_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_state_alu~2_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_state_alu~2_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~34_combout ),
|
|
.datac(\z80_|pla_decode_|Equal21~0_combout ),
|
|
.datad(\z80_|pla_decode_|Equal24~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|nextM~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|nextM~4 .lut_mask = 16'h5777;
|
|
defparam \z80_|execute_|nextM~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y13_N16
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_iorw~12 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_iorw~12_combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [1] & (!\z80_|ir_|opcode [2] & \z80_|execute_|ctl_eval_cond~0_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal13~0_combout ),
|
|
.datab(\z80_|ir_|opcode [1]),
|
|
.datac(\z80_|ir_|opcode [2]),
|
|
.datad(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_iorw~12_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_iorw~12 .lut_mask = 16'h0200;
|
|
defparam \z80_|execute_|ctl_iorw~12 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y16_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_iorw~8 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_iorw~8_combout = (\z80_|execute_|ctl_iorw~12_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout & (\z80_|pla_decode_|Equal3~0_combout & \z80_|pla_decode_|Equal24~0_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_state_alu~2_combout ),
|
|
.datab(\z80_|execute_|ctl_iorw~12_combout ),
|
|
.datac(\z80_|pla_decode_|Equal3~0_combout ),
|
|
.datad(\z80_|pla_decode_|Equal24~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_iorw~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_iorw~8 .lut_mask = 16'hECCC;
|
|
defparam \z80_|execute_|ctl_iorw~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y11_N28
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_iorw~9 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_iorw~9_combout = ((\z80_|execute_|ctl_iorw~8_combout ) # ((\z80_|execute_|ctl_mWrite~17_combout & \z80_|execute_|ctl_mRead~9_combout ))) # (!\z80_|execute_|nextM~4_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_mWrite~17_combout ),
|
|
.datab(\z80_|execute_|nextM~4_combout ),
|
|
.datac(\z80_|execute_|ctl_mRead~9_combout ),
|
|
.datad(\z80_|execute_|ctl_iorw~8_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_iorw~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_iorw~9 .lut_mask = 16'hFFB3;
|
|
defparam \z80_|execute_|ctl_iorw~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X27_Y11_N29
|
|
dffeas \z80_|memory_ifc_|DFFE_iorq_ff1 (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|execute_|ctl_iorw~9_combout ),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|clk_delay_|hold_clk_iorq~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|memory_ifc_|DFFE_iorq_ff1~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .is_wysiwyg = "true";
|
|
defparam \z80_|memory_ifc_|DFFE_iorq_ff1 .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X27_Y11_N25
|
|
dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|memory_ifc_|DFFE_iorq_ff1~q ),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|clk_delay_|hold_clk_iorq~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .is_wysiwyg = "true";
|
|
defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_15 .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y11_N14
|
|
cycloneive_lcell_comb \z80_|memory_ifc_|wait_iorq~feeder (
|
|
// Equation(s):
|
|
// \z80_|memory_ifc_|wait_iorq~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|memory_ifc_|wait_iorq~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|memory_ifc_|wait_iorq~feeder .lut_mask = 16'hFF00;
|
|
defparam \z80_|memory_ifc_|wait_iorq~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X27_Y11_N15
|
|
dffeas \z80_|memory_ifc_|wait_iorq (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|memory_ifc_|wait_iorq~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|clk_delay_|hold_clk_iorq~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|memory_ifc_|wait_iorq~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|memory_ifc_|wait_iorq .is_wysiwyg = "true";
|
|
defparam \z80_|memory_ifc_|wait_iorq .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X27_Y11_N9
|
|
dffeas \z80_|memory_ifc_|DFFE_iorq_ff4 (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|memory_ifc_|wait_iorq~q ),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|clk_delay_|hold_clk_iorq~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|memory_ifc_|DFFE_iorq_ff4~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .is_wysiwyg = "true";
|
|
defparam \z80_|memory_ifc_|DFFE_iorq_ff4 .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y11_N8
|
|
cycloneive_lcell_comb \z80_|memory_ifc_|iorq~0 (
|
|
// Equation(s):
|
|
// \z80_|memory_ifc_|iorq~0_combout = (\z80_|memory_ifc_|wait_iorq~q ) # ((\z80_|memory_ifc_|DFFE_iorq_ff4~q ) # (\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|memory_ifc_|wait_iorq~q ),
|
|
.datac(\z80_|memory_ifc_|DFFE_iorq_ff4~q ),
|
|
.datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_15~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|memory_ifc_|iorq~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|memory_ifc_|iorq~0 .lut_mask = 16'hFFFC;
|
|
defparam \z80_|memory_ifc_|iorq~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X27_Y11_N3
|
|
dffeas \z80_|memory_ifc_|DFFE_m1_ff1 (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|execute_|setM1~54_combout ),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|clk_delay_|hold_clk_iorq~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|memory_ifc_|DFFE_m1_ff1~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|memory_ifc_|DFFE_m1_ff1 .is_wysiwyg = "true";
|
|
defparam \z80_|memory_ifc_|DFFE_m1_ff1 .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y11_N26
|
|
cycloneive_lcell_comb \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 (
|
|
// Equation(s):
|
|
// \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout = !\z80_|memory_ifc_|DFFE_m1_ff1~q
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|memory_ifc_|DFFE_m1_ff1~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .lut_mask = 16'h00FF;
|
|
defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X27_Y11_N27
|
|
dffeas \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|clk_delay_|hold_clk_iorq~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .is_wysiwyg = "true";
|
|
defparam \z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1 .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X27_Y11_N19
|
|
dffeas \z80_|memory_ifc_|DFFE_m1_ff3 (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|clk_delay_|hold_clk_iorq~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|memory_ifc_|DFFE_m1_ff3~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|memory_ifc_|DFFE_m1_ff3 .is_wysiwyg = "true";
|
|
defparam \z80_|memory_ifc_|DFFE_m1_ff3 .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y11_N18
|
|
cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~0 (
|
|
// Equation(s):
|
|
// \z80_|memory_ifc_|nRD_out~0_combout = (\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q & (((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q )) # (!\z80_|interrupts_|DFFE_inst44~q ))) # (!\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q &
|
|
// (\z80_|memory_ifc_|DFFE_m1_ff3~q & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|interrupts_|DFFE_inst44~q ))))
|
|
|
|
.dataa(\z80_|memory_ifc_|wait_m_ALTERA_SYNTHESIZED1~q ),
|
|
.datab(\z80_|interrupts_|DFFE_inst44~q ),
|
|
.datac(\z80_|memory_ifc_|DFFE_m1_ff3~q ),
|
|
.datad(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|memory_ifc_|nRD_out~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|memory_ifc_|nRD_out~0 .lut_mask = 16'hFA32;
|
|
defparam \z80_|memory_ifc_|nRD_out~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y16_N28
|
|
cycloneive_lcell_comb \z80_|execute_|fIORead~0 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fIORead~0_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ctl_alu_op_low~22_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_state_alu~2_combout ),
|
|
.datab(\z80_|pla_decode_|Equal55~0_combout ),
|
|
.datac(\z80_|execute_|ctl_mWrite~4_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op_low~22_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fIORead~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fIORead~0 .lut_mask = 16'hC080;
|
|
defparam \z80_|execute_|fIORead~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y19_N22
|
|
cycloneive_lcell_comb \z80_|execute_|fIORead~1 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fIORead~1_combout = (\z80_|pla_decode_|Equal68~2_combout & (\z80_|pla_decode_|Equal1~4_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|fIOWrite~0_combout ))))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal68~2_combout ),
|
|
.datab(\z80_|pla_decode_|Equal1~4_combout ),
|
|
.datac(\z80_|execute_|ctl_mWrite~5_combout ),
|
|
.datad(\z80_|execute_|fIOWrite~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fIORead~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fIORead~1 .lut_mask = 16'h8088;
|
|
defparam \z80_|execute_|fIORead~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y19_N30
|
|
cycloneive_lcell_comb \z80_|execute_|fIORead~2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fIORead~2_combout = (\z80_|execute_|fIORead~1_combout ) # ((\z80_|execute_|ctl_mWrite~17_combout & ((\z80_|execute_|ctl_mWrite~5_combout ) # (\z80_|execute_|ctl_state_alu~3_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_mWrite~5_combout ),
|
|
.datab(\z80_|execute_|ctl_state_alu~3_combout ),
|
|
.datac(\z80_|execute_|fIORead~1_combout ),
|
|
.datad(\z80_|execute_|ctl_mWrite~17_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fIORead~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fIORead~2 .lut_mask = 16'hFEF0;
|
|
defparam \z80_|execute_|fIORead~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y12_N18
|
|
cycloneive_lcell_comb \z80_|execute_|fIOWrite~1 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fIOWrite~1_combout = (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|sequencer_|DFFE_T4_ff~q ) # (!\z80_|execute_|ixy_d~4_combout )))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T4_ff~q ),
|
|
.datab(gnd),
|
|
.datac(\z80_|sequencer_|DFFE_M3_ff~q ),
|
|
.datad(\z80_|execute_|ixy_d~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fIOWrite~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fIOWrite~1 .lut_mask = 16'hA0F0;
|
|
defparam \z80_|execute_|fIOWrite~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y12_N20
|
|
cycloneive_lcell_comb \z80_|execute_|fIORead~3 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fIORead~3_combout = (\z80_|execute_|fIORead~0_combout ) # ((\z80_|execute_|fIORead~2_combout ) # ((\z80_|execute_|ctl_mRead~2_combout & \z80_|execute_|fIOWrite~1_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_mRead~2_combout ),
|
|
.datab(\z80_|execute_|fIORead~0_combout ),
|
|
.datac(\z80_|execute_|fIORead~2_combout ),
|
|
.datad(\z80_|execute_|fIOWrite~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fIORead~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fIORead~3 .lut_mask = 16'hFEFC;
|
|
defparam \z80_|execute_|fIORead~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y13_N16
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_mRead~30 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mRead~30_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|pla_decode_|Equal33~3_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal6~1_combout ))))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal33~3_combout ),
|
|
.datab(\z80_|pla_decode_|Equal41~2_combout ),
|
|
.datac(\z80_|execute_|ctl_state_alu~2_combout ),
|
|
.datad(\z80_|pla_decode_|Equal6~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mRead~30_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mRead~30 .lut_mask = 16'hF0E0;
|
|
defparam \z80_|execute_|ctl_mRead~30 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y15_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_mRead~31 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mRead~31_combout = (\z80_|execute_|ctl_mRead~30_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & \z80_|execute_|ctl_mRead~10_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_mRead~30_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~10_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mRead~31_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mRead~31 .lut_mask = 16'hFAAA;
|
|
defparam \z80_|execute_|ctl_mRead~31 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y15_N30
|
|
cycloneive_lcell_comb \z80_|execute_|nextM~3 (
|
|
// Equation(s):
|
|
// \z80_|execute_|nextM~3_combout = (!\z80_|execute_|ixy_d~16_combout & (!\z80_|execute_|ixy_d~10_combout & !\z80_|pla_decode_|Equal41~2_combout ))
|
|
|
|
.dataa(\z80_|execute_|ixy_d~16_combout ),
|
|
.datab(\z80_|execute_|ixy_d~10_combout ),
|
|
.datac(\z80_|pla_decode_|Equal41~2_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|nextM~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|nextM~3 .lut_mask = 16'h0101;
|
|
defparam \z80_|execute_|nextM~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y15_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_mRead~29 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mRead~29_combout = (\z80_|execute_|ixy_d~8_combout & (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|nextM~3_combout )))
|
|
|
|
.dataa(\z80_|execute_|nextM~3_combout ),
|
|
.datab(\z80_|execute_|ixy_d~8_combout ),
|
|
.datac(\z80_|decode_state_|use_ixiy~combout ),
|
|
.datad(\z80_|pla_decode_|Equal49~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mRead~29_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mRead~29 .lut_mask = 16'hC444;
|
|
defparam \z80_|execute_|ctl_mRead~29 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y16_N26
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~58 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~58_combout = (!\z80_|execute_|ctl_mRead~12_combout & ((\z80_|decode_state_|DFFE_instIY1~q ) # ((\z80_|decode_state_|DFFE_inst4~q ) # (!\z80_|pla_decode_|Equal49~0_combout ))))
|
|
|
|
.dataa(\z80_|decode_state_|DFFE_instIY1~q ),
|
|
.datab(\z80_|decode_state_|DFFE_inst4~q ),
|
|
.datac(\z80_|pla_decode_|Equal49~0_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~12_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~58_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~58 .lut_mask = 16'h00EF;
|
|
defparam \z80_|execute_|setM1~58 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y12_N22
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~38 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~38_combout = (\z80_|execute_|setM1~37_combout & \z80_|execute_|ctl_reg_sys_hilo~38_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|setM1~37_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sys_hilo~38_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~38_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~38 .lut_mask = 16'hF000;
|
|
defparam \z80_|execute_|setM1~38 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y12_N0
|
|
cycloneive_lcell_comb \z80_|execute_|fMRead~4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fMRead~4_combout = (\z80_|execute_|ctl_al_we~4_combout & (\z80_|execute_|ctl_reg_sel_wz~8_combout & !\z80_|pla_decode_|Equal34~0_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_al_we~4_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_sel_wz~8_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|pla_decode_|Equal34~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fMRead~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fMRead~4 .lut_mask = 16'h0088;
|
|
defparam \z80_|execute_|fMRead~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y14_N14
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~39 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~39_combout = (!\z80_|pla_decode_|Equal29~0_combout & (\z80_|execute_|fMRead~4_combout & !\z80_|pla_decode_|Equal9~1_combout ))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal29~0_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|fMRead~4_combout ),
|
|
.datad(\z80_|pla_decode_|Equal9~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~39_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~39 .lut_mask = 16'h0050;
|
|
defparam \z80_|execute_|setM1~39 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y14_N4
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~40 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~40_combout = (\z80_|execute_|setM1~58_combout & (\z80_|execute_|setM1~38_combout & (\z80_|execute_|setM1~39_combout & !\z80_|execute_|ctl_mRead~14_combout )))
|
|
|
|
.dataa(\z80_|execute_|setM1~58_combout ),
|
|
.datab(\z80_|execute_|setM1~38_combout ),
|
|
.datac(\z80_|execute_|setM1~39_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~14_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~40_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~40 .lut_mask = 16'h0080;
|
|
defparam \z80_|execute_|setM1~40 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y14_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_mRead~32 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mRead~32_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((\z80_|execute_|ctl_mRead~11_combout ) # (!\z80_|execute_|setM1~40_combout )) # (!\z80_|execute_|ctl_mRead~17_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_mRead~17_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~11_combout ),
|
|
.datac(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.datad(\z80_|execute_|setM1~40_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mRead~32_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mRead~32 .lut_mask = 16'hD0F0;
|
|
defparam \z80_|execute_|ctl_mRead~32 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y14_N16
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_mRead~33 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mRead~33_combout = (\z80_|execute_|ctl_mRead~31_combout ) # (((\z80_|execute_|ctl_mRead~29_combout ) # (\z80_|execute_|ctl_mRead~32_combout )) # (!\z80_|execute_|ctl_mRead~28_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_mRead~31_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~28_combout ),
|
|
.datac(\z80_|execute_|ctl_mRead~29_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~32_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mRead~33_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mRead~33 .lut_mask = 16'hFFFB;
|
|
defparam \z80_|execute_|ctl_mRead~33 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X25_Y14_N17
|
|
dffeas \z80_|memory_ifc_|DFFE_mrd_ff1 (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|execute_|ctl_mRead~33_combout ),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|clk_delay_|hold_clk_iorq~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|memory_ifc_|DFFE_mrd_ff1~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .is_wysiwyg = "true";
|
|
defparam \z80_|memory_ifc_|DFFE_mrd_ff1 .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y11_N30
|
|
cycloneive_lcell_comb \z80_|memory_ifc_|wait_mrd~feeder (
|
|
// Equation(s):
|
|
// \z80_|memory_ifc_|wait_mrd~feeder_combout = \z80_|memory_ifc_|DFFE_mrd_ff1~q
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|memory_ifc_|DFFE_mrd_ff1~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|memory_ifc_|wait_mrd~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|memory_ifc_|wait_mrd~feeder .lut_mask = 16'hFF00;
|
|
defparam \z80_|memory_ifc_|wait_mrd~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X27_Y11_N31
|
|
dffeas \z80_|memory_ifc_|wait_mrd (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|memory_ifc_|wait_mrd~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|clk_delay_|hold_clk_iorq~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|memory_ifc_|wait_mrd~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|memory_ifc_|wait_mrd .is_wysiwyg = "true";
|
|
defparam \z80_|memory_ifc_|wait_mrd .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X27_Y11_N17
|
|
dffeas \z80_|memory_ifc_|DFFE_mrd_ff3 (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|memory_ifc_|wait_mrd~q ),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|clk_delay_|hold_clk_iorq~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|memory_ifc_|DFFE_mrd_ff3~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .is_wysiwyg = "true";
|
|
defparam \z80_|memory_ifc_|DFFE_mrd_ff3 .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y11_N12
|
|
cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~1 (
|
|
// Equation(s):
|
|
// \z80_|memory_ifc_|nRD_out~1_combout = (!\z80_|memory_ifc_|wait_mrd~q & !\z80_|memory_ifc_|DFFE_mrd_ff3~q )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|memory_ifc_|wait_mrd~q ),
|
|
.datad(\z80_|memory_ifc_|DFFE_mrd_ff3~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|memory_ifc_|nRD_out~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|memory_ifc_|nRD_out~1 .lut_mask = 16'h000F;
|
|
defparam \z80_|memory_ifc_|nRD_out~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y11_N20
|
|
cycloneive_lcell_comb \z80_|memory_ifc_|nRD_out~2 (
|
|
// Equation(s):
|
|
// \z80_|memory_ifc_|nRD_out~2_combout = (\z80_|memory_ifc_|nRD_out~0_combout ) # (((\z80_|memory_ifc_|iorq~0_combout & \z80_|execute_|fIORead~3_combout )) # (!\z80_|memory_ifc_|nRD_out~1_combout ))
|
|
|
|
.dataa(\z80_|memory_ifc_|iorq~0_combout ),
|
|
.datab(\z80_|memory_ifc_|nRD_out~0_combout ),
|
|
.datac(\z80_|execute_|fIORead~3_combout ),
|
|
.datad(\z80_|memory_ifc_|nRD_out~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|memory_ifc_|nRD_out~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|memory_ifc_|nRD_out~2 .lut_mask = 16'hECFF;
|
|
defparam \z80_|memory_ifc_|nRD_out~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y12_N30
|
|
cycloneive_lcell_comb \z80_|execute_|fIOWrite~3 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fIOWrite~3_combout = ((\z80_|sequencer_|DFFE_T1_ff~q & !\z80_|sequencer_|DFFE_T4_ff~q )) # (!\z80_|sequencer_|DFFE_M3_ff~q )
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datac(\z80_|sequencer_|DFFE_M3_ff~q ),
|
|
.datad(\z80_|sequencer_|DFFE_T4_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fIOWrite~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fIOWrite~3 .lut_mask = 16'h0FCF;
|
|
defparam \z80_|execute_|fIOWrite~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y12_N0
|
|
cycloneive_lcell_comb \z80_|execute_|fIOWrite~4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fIOWrite~4_combout = (\z80_|execute_|ctl_mRead~34_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ixy_d~6_combout ) # (!\z80_|execute_|fIOWrite~3_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ixy_d~5_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~34_combout ),
|
|
.datac(\z80_|execute_|fIOWrite~3_combout ),
|
|
.datad(\z80_|execute_|ixy_d~6_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fIOWrite~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fIOWrite~4 .lut_mask = 16'hCC8C;
|
|
defparam \z80_|execute_|fIOWrite~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y16_N22
|
|
cycloneive_lcell_comb \z80_|execute_|fIOWrite~2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fIOWrite~2_combout = (\z80_|execute_|ctl_iorw~10_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # ((\z80_|execute_|ctl_mWrite~5_combout ) # (!\z80_|execute_|fMRead~2_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_state_alu~2_combout ),
|
|
.datab(\z80_|execute_|ctl_iorw~10_combout ),
|
|
.datac(\z80_|execute_|ctl_mWrite~5_combout ),
|
|
.datad(\z80_|execute_|fMRead~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fIOWrite~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fIOWrite~2 .lut_mask = 16'hC8CC;
|
|
defparam \z80_|execute_|fIOWrite~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y12_N22
|
|
cycloneive_lcell_comb \z80_|execute_|fIOWrite~5 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fIOWrite~5_combout = (\z80_|execute_|fIOWrite~4_combout ) # ((\z80_|execute_|fIOWrite~2_combout ) # ((\z80_|execute_|ctl_mRead~3_combout & \z80_|execute_|fIOWrite~1_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_mRead~3_combout ),
|
|
.datab(\z80_|execute_|fIOWrite~4_combout ),
|
|
.datac(\z80_|execute_|fIOWrite~2_combout ),
|
|
.datad(\z80_|execute_|fIOWrite~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fIOWrite~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fIOWrite~5 .lut_mask = 16'hFEFC;
|
|
defparam \z80_|execute_|fIOWrite~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y15_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~15 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mWrite~15_combout = (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout & \z80_|execute_|ctl_mRead~5_combout )))) # (!\z80_|execute_|ctl_eval_cond~0_combout &
|
|
// (((\z80_|execute_|ctl_state_alu~2_combout & \z80_|execute_|ctl_mRead~5_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.datab(\z80_|execute_|ctl_mWrite~7_combout ),
|
|
.datac(\z80_|execute_|ctl_state_alu~2_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~5_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mWrite~15_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mWrite~15 .lut_mask = 16'hF888;
|
|
defparam \z80_|execute_|ctl_mWrite~15 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y17_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~12 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mWrite~12_combout = (!\z80_|execute_|ctl_mWrite~18_combout & (((!\z80_|execute_|ctl_mRead~6_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ctl_state_alu~4_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_state_alu~4_combout ),
|
|
.datab(\z80_|execute_|ctl_mWrite~18_combout ),
|
|
.datac(\z80_|execute_|ctl_mRead~6_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~8_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mWrite~12_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mWrite~12 .lut_mask = 16'h1113;
|
|
defparam \z80_|execute_|ctl_mWrite~12 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y17_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~13 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mWrite~13_combout = (\z80_|execute_|ctl_mWrite~12_combout & (\z80_|execute_|ctl_mWrite~10_combout & ((!\z80_|execute_|ctl_eval_cond~0_combout ) # (!\z80_|execute_|ctl_mWrite~8_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_mWrite~8_combout ),
|
|
.datab(\z80_|execute_|ctl_mWrite~12_combout ),
|
|
.datac(\z80_|execute_|ctl_mWrite~10_combout ),
|
|
.datad(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mWrite~13_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mWrite~13 .lut_mask = 16'h40C0;
|
|
defparam \z80_|execute_|ctl_mWrite~13 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y17_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~14 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mWrite~14_combout = (\z80_|execute_|ctl_mWrite~11_combout & (\z80_|execute_|ctl_reg_gp_sel[1]~4_combout & (\z80_|execute_|ctl_mWrite~13_combout & \z80_|execute_|ctl_bus_db_oe~7_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_mWrite~11_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_sel[1]~4_combout ),
|
|
.datac(\z80_|execute_|ctl_mWrite~13_combout ),
|
|
.datad(\z80_|execute_|ctl_bus_db_oe~7_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mWrite~14_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mWrite~14 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|ctl_mWrite~14 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y11_N6
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_mWrite~16 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mWrite~16_combout = (\z80_|execute_|ctl_mWrite~15_combout ) # (((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ixy_d~17_combout )) # (!\z80_|execute_|ctl_mWrite~14_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_mWrite~15_combout ),
|
|
.datab(\z80_|execute_|ixy_d~8_combout ),
|
|
.datac(\z80_|execute_|ixy_d~17_combout ),
|
|
.datad(\z80_|execute_|ctl_mWrite~14_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mWrite~16_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mWrite~16 .lut_mask = 16'hAEFF;
|
|
defparam \z80_|execute_|ctl_mWrite~16 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X27_Y11_N7
|
|
dffeas \z80_|memory_ifc_|DFFE_mwr_ff1 (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|execute_|ctl_mWrite~16_combout ),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|clk_delay_|hold_clk_iorq~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|memory_ifc_|DFFE_mwr_ff1~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .is_wysiwyg = "true";
|
|
defparam \z80_|memory_ifc_|DFFE_mwr_ff1 .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y11_N22
|
|
cycloneive_lcell_comb \z80_|memory_ifc_|wait_mwr~feeder (
|
|
// Equation(s):
|
|
// \z80_|memory_ifc_|wait_mwr~feeder_combout = \z80_|memory_ifc_|DFFE_mwr_ff1~q
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|memory_ifc_|DFFE_mwr_ff1~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|memory_ifc_|wait_mwr~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|memory_ifc_|wait_mwr~feeder .lut_mask = 16'hFF00;
|
|
defparam \z80_|memory_ifc_|wait_mwr~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X27_Y11_N23
|
|
dffeas \z80_|memory_ifc_|wait_mwr (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|memory_ifc_|wait_mwr~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|clk_delay_|hold_clk_iorq~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|memory_ifc_|wait_mwr~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|memory_ifc_|wait_mwr .is_wysiwyg = "true";
|
|
defparam \z80_|memory_ifc_|wait_mwr .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X27_Y11_N21
|
|
dffeas \z80_|memory_ifc_|mwr_wr (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|memory_ifc_|wait_mwr~q ),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|clk_delay_|hold_clk_iorq~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|memory_ifc_|mwr_wr~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|memory_ifc_|mwr_wr .is_wysiwyg = "true";
|
|
defparam \z80_|memory_ifc_|mwr_wr .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y11_N20
|
|
cycloneive_lcell_comb \z80_|memory_ifc_|nWR_out~0 (
|
|
// Equation(s):
|
|
// \z80_|memory_ifc_|nWR_out~0_combout = (\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|execute_|fIOWrite~5_combout & \z80_|memory_ifc_|iorq~0_combout ))
|
|
|
|
.dataa(\z80_|execute_|fIOWrite~5_combout ),
|
|
.datab(\z80_|memory_ifc_|iorq~0_combout ),
|
|
.datac(\z80_|memory_ifc_|mwr_wr~q ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|memory_ifc_|nWR_out~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|memory_ifc_|nWR_out~0 .lut_mask = 16'hF8F8;
|
|
defparam \z80_|memory_ifc_|nWR_out~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y11_N16
|
|
cycloneive_lcell_comb \Equal2~1 (
|
|
// Equation(s):
|
|
// \Equal2~1_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\z80_|memory_ifc_|nRD_out~2_combout & !\z80_|memory_ifc_|nWR_out~0_combout ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.datac(\z80_|memory_ifc_|nRD_out~2_combout ),
|
|
.datad(\z80_|memory_ifc_|nWR_out~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\Equal2~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \Equal2~1 .lut_mask = 16'h00C0;
|
|
defparam \Equal2~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y12_N10
|
|
cycloneive_lcell_comb \z80_|execute_|fMWrite~3 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fMWrite~3_combout = ((!\z80_|sequencer_|DFFE_T2_ff~q & \z80_|sequencer_|DFFE_T1_ff~q )) # (!\z80_|sequencer_|DFFE_M4_ff~q )
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.datab(\z80_|sequencer_|DFFE_M4_ff~q ),
|
|
.datac(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fMWrite~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fMWrite~3 .lut_mask = 16'h7373;
|
|
defparam \z80_|execute_|fMWrite~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y12_N16
|
|
cycloneive_lcell_comb \z80_|execute_|fMWrite~4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fMWrite~4_combout = (!\z80_|execute_|fMWrite~3_combout & ((\z80_|execute_|ctl_mWrite~7_combout ) # ((\z80_|pla_decode_|Equal13~2_combout ) # (\z80_|execute_|ctl_mRead~5_combout ))))
|
|
|
|
.dataa(\z80_|execute_|fMWrite~3_combout ),
|
|
.datab(\z80_|execute_|ctl_mWrite~7_combout ),
|
|
.datac(\z80_|pla_decode_|Equal13~2_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~5_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fMWrite~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fMWrite~4 .lut_mask = 16'h5554;
|
|
defparam \z80_|execute_|fMWrite~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y17_N24
|
|
cycloneive_lcell_comb \z80_|execute_|fMWrite~0 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fMWrite~0_combout = ((!\z80_|sequencer_|DFFE_T3_ff~q & !\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|sequencer_|M5~q )
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.datab(gnd),
|
|
.datac(\z80_|sequencer_|M5~q ),
|
|
.datad(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fMWrite~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fMWrite~0 .lut_mask = 16'h0F5F;
|
|
defparam \z80_|execute_|fMWrite~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y17_N22
|
|
cycloneive_lcell_comb \z80_|execute_|fMWrite~2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fMWrite~2_combout = (!\z80_|execute_|fMWrite~1_combout & (((\z80_|execute_|ixy_d~6_combout ) # (\z80_|execute_|ixy_d~5_combout )) # (!\z80_|execute_|fMWrite~0_combout )))
|
|
|
|
.dataa(\z80_|execute_|fMWrite~1_combout ),
|
|
.datab(\z80_|execute_|fMWrite~0_combout ),
|
|
.datac(\z80_|execute_|ixy_d~6_combout ),
|
|
.datad(\z80_|execute_|ixy_d~5_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fMWrite~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fMWrite~2 .lut_mask = 16'h5551;
|
|
defparam \z80_|execute_|fMWrite~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y18_N8
|
|
cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~3 (
|
|
// Equation(s):
|
|
// \z80_|pin_control_|bus_db_pin_oe~3_combout = (\z80_|execute_|ctl_bus_inc_oe~26_combout & (!\z80_|execute_|fMWrite~4_combout & (!\z80_|execute_|fMWrite~2_combout & !\z80_|execute_|fIOWrite~5_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_bus_inc_oe~26_combout ),
|
|
.datab(\z80_|execute_|fMWrite~4_combout ),
|
|
.datac(\z80_|execute_|fMWrite~2_combout ),
|
|
.datad(\z80_|execute_|fIOWrite~5_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|pin_control_|bus_db_pin_oe~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pin_control_|bus_db_pin_oe~3 .lut_mask = 16'h0002;
|
|
defparam \z80_|pin_control_|bus_db_pin_oe~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y15_N14
|
|
cycloneive_lcell_comb \z80_|execute_|fMWrite~8 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fMWrite~8_combout = (\z80_|pla_decode_|Equal9~1_combout & (((\z80_|execute_|ctl_alu_oe~0_combout ) # (\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|pla_decode_|Equal9~1_combout & (\z80_|execute_|ctl_mRead~8_combout &
|
|
// ((\z80_|execute_|ctl_alu_oe~0_combout ) # (\z80_|execute_|ctl_reg_in_hi~2_combout ))))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal9~1_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~8_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_oe~0_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_in_hi~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fMWrite~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fMWrite~8 .lut_mask = 16'hEEE0;
|
|
defparam \z80_|execute_|fMWrite~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y12_N28
|
|
cycloneive_lcell_comb \z80_|execute_|fMWrite~7 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fMWrite~7_combout = (\z80_|execute_|ctl_state_alu~4_combout & ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_mWrite~7_combout ) # (\z80_|execute_|ctl_mRead~7_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_mRead~5_combout ),
|
|
.datab(\z80_|execute_|ctl_state_alu~4_combout ),
|
|
.datac(\z80_|execute_|ctl_mWrite~7_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~7_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fMWrite~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fMWrite~7 .lut_mask = 16'hCCC8;
|
|
defparam \z80_|execute_|fMWrite~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y17_N26
|
|
cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~16 (
|
|
// Equation(s):
|
|
// \z80_|pin_control_|bus_db_pin_oe~16_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|pla_decode_|Equal13~2_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ),
|
|
.datab(\z80_|pla_decode_|Equal13~2_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_M4_ff~q ),
|
|
.datad(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|pin_control_|bus_db_pin_oe~16_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pin_control_|bus_db_pin_oe~16 .lut_mask = 16'h1555;
|
|
defparam \z80_|pin_control_|bus_db_pin_oe~16 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y17_N14
|
|
cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~8 (
|
|
// Equation(s):
|
|
// \z80_|pin_control_|bus_db_pin_oe~8_combout = (\z80_|execute_|ixy_d~5_combout & (!\z80_|execute_|ctl_mRead~5_combout & ((!\z80_|execute_|ctl_ir_we~4_combout ) # (!\z80_|execute_|ctl_mRead~8_combout )))) # (!\z80_|execute_|ixy_d~5_combout &
|
|
// (((!\z80_|execute_|ctl_ir_we~4_combout )) # (!\z80_|execute_|ctl_mRead~8_combout )))
|
|
|
|
.dataa(\z80_|execute_|ixy_d~5_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~8_combout ),
|
|
.datac(\z80_|execute_|ctl_ir_we~4_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~5_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|pin_control_|bus_db_pin_oe~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pin_control_|bus_db_pin_oe~8 .lut_mask = 16'h153F;
|
|
defparam \z80_|pin_control_|bus_db_pin_oe~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y17_N0
|
|
cycloneive_lcell_comb \z80_|execute_|fMWrite~6 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fMWrite~6_combout = ((\z80_|pla_decode_|Equal46~0_combout ) # ((\z80_|ir_|opcode [6] & !\z80_|ir_|opcode [7]))) # (!\z80_|execute_|ctl_ir_we~5_combout )
|
|
|
|
.dataa(\z80_|ir_|opcode [6]),
|
|
.datab(\z80_|ir_|opcode [7]),
|
|
.datac(\z80_|execute_|ctl_ir_we~5_combout ),
|
|
.datad(\z80_|pla_decode_|Equal46~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fMWrite~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fMWrite~6 .lut_mask = 16'hFF2F;
|
|
defparam \z80_|execute_|fMWrite~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y17_N8
|
|
cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~9 (
|
|
// Equation(s):
|
|
// \z80_|pin_control_|bus_db_pin_oe~9_combout = (\z80_|execute_|fMWrite~6_combout & (((\z80_|execute_|fIOWrite~0_combout )) # (!\z80_|execute_|ctl_mWrite~8_combout ))) # (!\z80_|execute_|fMWrite~6_combout & (\z80_|execute_|fMWrite~0_combout &
|
|
// ((\z80_|execute_|fIOWrite~0_combout ) # (!\z80_|execute_|ctl_mWrite~8_combout ))))
|
|
|
|
.dataa(\z80_|execute_|fMWrite~6_combout ),
|
|
.datab(\z80_|execute_|ctl_mWrite~8_combout ),
|
|
.datac(\z80_|execute_|fIOWrite~0_combout ),
|
|
.datad(\z80_|execute_|fMWrite~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|pin_control_|bus_db_pin_oe~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pin_control_|bus_db_pin_oe~9 .lut_mask = 16'hF3A2;
|
|
defparam \z80_|pin_control_|bus_db_pin_oe~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y17_N28
|
|
cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~7 (
|
|
// Equation(s):
|
|
// \z80_|pin_control_|bus_db_pin_oe~7_combout = (\z80_|execute_|ixy_d~7_combout & (((\z80_|execute_|fMRead~3_combout & !\z80_|execute_|ctl_mRead~4_combout )))) # (!\z80_|execute_|ixy_d~7_combout & (((!\z80_|execute_|ctl_mRead~4_combout )) #
|
|
// (!\z80_|execute_|ctl_alu_oe~0_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_oe~0_combout ),
|
|
.datab(\z80_|execute_|fMRead~3_combout ),
|
|
.datac(\z80_|execute_|ixy_d~7_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|pin_control_|bus_db_pin_oe~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pin_control_|bus_db_pin_oe~7 .lut_mask = 16'h05CF;
|
|
defparam \z80_|pin_control_|bus_db_pin_oe~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y17_N10
|
|
cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~10 (
|
|
// Equation(s):
|
|
// \z80_|pin_control_|bus_db_pin_oe~10_combout = (\z80_|pin_control_|bus_db_pin_oe~16_combout & (\z80_|pin_control_|bus_db_pin_oe~8_combout & (\z80_|pin_control_|bus_db_pin_oe~9_combout & \z80_|pin_control_|bus_db_pin_oe~7_combout )))
|
|
|
|
.dataa(\z80_|pin_control_|bus_db_pin_oe~16_combout ),
|
|
.datab(\z80_|pin_control_|bus_db_pin_oe~8_combout ),
|
|
.datac(\z80_|pin_control_|bus_db_pin_oe~9_combout ),
|
|
.datad(\z80_|pin_control_|bus_db_pin_oe~7_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|pin_control_|bus_db_pin_oe~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pin_control_|bus_db_pin_oe~10 .lut_mask = 16'h8000;
|
|
defparam \z80_|pin_control_|bus_db_pin_oe~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y14_N20
|
|
cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~11 (
|
|
// Equation(s):
|
|
// \z80_|pin_control_|bus_db_pin_oe~11_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & (!\z80_|execute_|fMWrite~7_combout & (\z80_|execute_|ctl_reg_sel_wz~7_combout & \z80_|pin_control_|bus_db_pin_oe~10_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ),
|
|
.datab(\z80_|execute_|fMWrite~7_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_sel_wz~7_combout ),
|
|
.datad(\z80_|pin_control_|bus_db_pin_oe~10_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|pin_control_|bus_db_pin_oe~11_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pin_control_|bus_db_pin_oe~11 .lut_mask = 16'h2000;
|
|
defparam \z80_|pin_control_|bus_db_pin_oe~11 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y18_N6
|
|
cycloneive_lcell_comb \z80_|execute_|fMWrite~5 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fMWrite~5_combout = (!\z80_|execute_|ctl_mWrite~17_combout & (!\z80_|execute_|ctl_mWrite~6_combout & !\z80_|execute_|ctl_mRead~5_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_mWrite~17_combout ),
|
|
.datab(\z80_|execute_|ctl_mWrite~6_combout ),
|
|
.datac(\z80_|execute_|ctl_mRead~5_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fMWrite~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fMWrite~5 .lut_mask = 16'h0101;
|
|
defparam \z80_|execute_|fMWrite~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y18_N28
|
|
cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~6 (
|
|
// Equation(s):
|
|
// \z80_|pin_control_|bus_db_pin_oe~6_combout = (\z80_|execute_|ctl_inc_dec~2_combout & ((\z80_|execute_|fMWrite~5_combout ) # ((!\z80_|execute_|ixy_d~7_combout & !\z80_|execute_|ixy_d~6_combout ))))
|
|
|
|
.dataa(\z80_|execute_|fMWrite~5_combout ),
|
|
.datab(\z80_|execute_|ctl_inc_dec~2_combout ),
|
|
.datac(\z80_|execute_|ixy_d~7_combout ),
|
|
.datad(\z80_|execute_|ixy_d~6_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|pin_control_|bus_db_pin_oe~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pin_control_|bus_db_pin_oe~6 .lut_mask = 16'h888C;
|
|
defparam \z80_|pin_control_|bus_db_pin_oe~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y18_N26
|
|
cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~12 (
|
|
// Equation(s):
|
|
// \z80_|pin_control_|bus_db_pin_oe~12_combout = (!\z80_|execute_|fMWrite~8_combout & (\z80_|pin_control_|bus_db_pin_oe~11_combout & (\z80_|execute_|ctl_bus_inc_oe~30_combout & \z80_|pin_control_|bus_db_pin_oe~6_combout )))
|
|
|
|
.dataa(\z80_|execute_|fMWrite~8_combout ),
|
|
.datab(\z80_|pin_control_|bus_db_pin_oe~11_combout ),
|
|
.datac(\z80_|execute_|ctl_bus_inc_oe~30_combout ),
|
|
.datad(\z80_|pin_control_|bus_db_pin_oe~6_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|pin_control_|bus_db_pin_oe~12_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pin_control_|bus_db_pin_oe~12 .lut_mask = 16'h4000;
|
|
defparam \z80_|pin_control_|bus_db_pin_oe~12 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y16_N20
|
|
cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~4 (
|
|
// Equation(s):
|
|
// \z80_|pin_control_|bus_db_pin_oe~4_combout = (\z80_|pla_decode_|Equal11~0_combout & (!\z80_|execute_|ixy_d~7_combout & ((!\z80_|execute_|ctl_mRead~6_combout ) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))) # (!\z80_|pla_decode_|Equal11~0_combout &
|
|
// (((!\z80_|execute_|ctl_mRead~6_combout )) # (!\z80_|execute_|ctl_reg_in_hi~2_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal11~0_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_in_hi~2_combout ),
|
|
.datac(\z80_|execute_|ctl_mRead~6_combout ),
|
|
.datad(\z80_|execute_|ixy_d~7_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|pin_control_|bus_db_pin_oe~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pin_control_|bus_db_pin_oe~4 .lut_mask = 16'h153F;
|
|
defparam \z80_|pin_control_|bus_db_pin_oe~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y12_N30
|
|
cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~5 (
|
|
// Equation(s):
|
|
// \z80_|pin_control_|bus_db_pin_oe~5_combout = (\z80_|pin_control_|bus_db_pin_oe~4_combout & (((\z80_|execute_|ixy_d~4_combout ) # (!\z80_|execute_|ctl_mWrite~7_combout )) # (!\z80_|sequencer_|DFFE_M2_ff~q )))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_M2_ff~q ),
|
|
.datab(\z80_|execute_|ctl_mWrite~7_combout ),
|
|
.datac(\z80_|pin_control_|bus_db_pin_oe~4_combout ),
|
|
.datad(\z80_|execute_|ixy_d~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|pin_control_|bus_db_pin_oe~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pin_control_|bus_db_pin_oe~5 .lut_mask = 16'hF070;
|
|
defparam \z80_|pin_control_|bus_db_pin_oe~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y18_N24
|
|
cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~13 (
|
|
// Equation(s):
|
|
// \z80_|pin_control_|bus_db_pin_oe~13_combout = (\z80_|pin_control_|bus_db_pin_oe~12_combout & (\z80_|pin_control_|bus_db_pin_oe~5_combout & ((!\z80_|execute_|ixy_d~6_combout ) # (!\z80_|pla_decode_|Equal11~0_combout ))))
|
|
|
|
.dataa(\z80_|pin_control_|bus_db_pin_oe~12_combout ),
|
|
.datab(\z80_|pin_control_|bus_db_pin_oe~5_combout ),
|
|
.datac(\z80_|pla_decode_|Equal11~0_combout ),
|
|
.datad(\z80_|execute_|ixy_d~6_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|pin_control_|bus_db_pin_oe~13_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pin_control_|bus_db_pin_oe~13 .lut_mask = 16'h0888;
|
|
defparam \z80_|pin_control_|bus_db_pin_oe~13 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y18_N12
|
|
cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~14 (
|
|
// Equation(s):
|
|
// \z80_|pin_control_|bus_db_pin_oe~14_combout = (\z80_|pin_control_|bus_db_pin_oe~3_combout & (\z80_|execute_|ctl_inc_cy~35_combout & (\z80_|execute_|ctl_apin_mux~0_combout & \z80_|pin_control_|bus_db_pin_oe~13_combout )))
|
|
|
|
.dataa(\z80_|pin_control_|bus_db_pin_oe~3_combout ),
|
|
.datab(\z80_|execute_|ctl_inc_cy~35_combout ),
|
|
.datac(\z80_|execute_|ctl_apin_mux~0_combout ),
|
|
.datad(\z80_|pin_control_|bus_db_pin_oe~13_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|pin_control_|bus_db_pin_oe~14_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pin_control_|bus_db_pin_oe~14 .lut_mask = 16'h8000;
|
|
defparam \z80_|pin_control_|bus_db_pin_oe~14 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y12_N4
|
|
cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~2 (
|
|
// Equation(s):
|
|
// \z80_|pin_control_|bus_db_pin_oe~2_combout = (\z80_|sequencer_|DFFE_T3_ff~q ) # (\z80_|sequencer_|DFFE_T2_ff~q )
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.datac(gnd),
|
|
.datad(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|pin_control_|bus_db_pin_oe~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pin_control_|bus_db_pin_oe~2 .lut_mask = 16'hFFCC;
|
|
defparam \z80_|pin_control_|bus_db_pin_oe~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y12_N14
|
|
cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_oe~15 (
|
|
// Equation(s):
|
|
// \z80_|pin_control_|bus_db_pin_oe~15_combout = (\z80_|pin_control_|bus_db_pin_oe~14_combout & (\z80_|execute_|fIOWrite~5_combout & ((\z80_|sequencer_|DFFE_T4_ff~q )))) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout &
|
|
// ((\z80_|pin_control_|bus_db_pin_oe~2_combout ) # ((\z80_|execute_|fIOWrite~5_combout & \z80_|sequencer_|DFFE_T4_ff~q ))))
|
|
|
|
.dataa(\z80_|pin_control_|bus_db_pin_oe~14_combout ),
|
|
.datab(\z80_|execute_|fIOWrite~5_combout ),
|
|
.datac(\z80_|pin_control_|bus_db_pin_oe~2_combout ),
|
|
.datad(\z80_|sequencer_|DFFE_T4_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|pin_control_|bus_db_pin_oe~15_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pin_control_|bus_db_pin_oe~15 .lut_mask = 16'hDC50;
|
|
defparam \z80_|pin_control_|bus_db_pin_oe~15 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X38_Y11_N12
|
|
cycloneive_lcell_comb \z80_|clk_delay_|DFF_inst5~feeder (
|
|
// Equation(s):
|
|
// \z80_|clk_delay_|DFF_inst5~feeder_combout = \z80_|clk_delay_|SYNTHESIZED_WIRE_7~q
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|clk_delay_|DFF_inst5~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|clk_delay_|DFF_inst5~feeder .lut_mask = 16'hFF00;
|
|
defparam \z80_|clk_delay_|DFF_inst5~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X38_Y11_N13
|
|
dffeas \z80_|clk_delay_|DFF_inst5 (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|clk_delay_|DFF_inst5~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|clk_delay_|DFF_inst5~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|clk_delay_|DFF_inst5 .is_wysiwyg = "true";
|
|
defparam \z80_|clk_delay_|DFF_inst5 .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X29_Y11_N15
|
|
dffeas \z80_|memory_ifc_|wait_iorqinta (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|clk_delay_|DFF_inst5~q ),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|memory_ifc_|wait_iorqinta~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|memory_ifc_|wait_iorqinta .is_wysiwyg = "true";
|
|
defparam \z80_|memory_ifc_|wait_iorqinta .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X29_Y11_N31
|
|
dffeas \z80_|memory_ifc_|DFFE_intr_ff3 (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|memory_ifc_|wait_iorqinta~q ),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|memory_ifc_|DFFE_intr_ff3~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|memory_ifc_|DFFE_intr_ff3 .is_wysiwyg = "true";
|
|
defparam \z80_|memory_ifc_|DFFE_intr_ff3 .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y11_N30
|
|
cycloneive_lcell_comb \z80_|memory_ifc_|nIORQ_out~0 (
|
|
// Equation(s):
|
|
// \z80_|memory_ifc_|nIORQ_out~0_combout = (\z80_|memory_ifc_|iorq~0_combout ) # ((\z80_|memory_ifc_|wait_iorqinta~q ) # (\z80_|memory_ifc_|DFFE_intr_ff3~q ))
|
|
|
|
.dataa(\z80_|memory_ifc_|iorq~0_combout ),
|
|
.datab(\z80_|memory_ifc_|wait_iorqinta~q ),
|
|
.datac(\z80_|memory_ifc_|DFFE_intr_ff3~q ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|memory_ifc_|nIORQ_out~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|memory_ifc_|nIORQ_out~0 .lut_mask = 16'hFEFE;
|
|
defparam \z80_|memory_ifc_|nIORQ_out~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y11_N28
|
|
cycloneive_lcell_comb \Equal2~0 (
|
|
// Equation(s):
|
|
// \Equal2~0_combout = (\z80_|memory_ifc_|nIORQ_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\z80_|memory_ifc_|nRD_out~2_combout & !\z80_|memory_ifc_|nWR_out~0_combout )))
|
|
|
|
.dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ),
|
|
.datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.datac(\z80_|memory_ifc_|nRD_out~2_combout ),
|
|
.datad(\z80_|memory_ifc_|nWR_out~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\Equal2~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \Equal2~0 .lut_mask = 16'h0080;
|
|
defparam \Equal2~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y14_N16
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux~2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_apin_mux~2_combout = ((\z80_|execute_|ctl_apin_mux~1_combout & \z80_|execute_|ctl_mWrite~6_combout )) # (!\z80_|execute_|ctl_inc_dec~6_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_apin_mux~1_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_inc_dec~6_combout ),
|
|
.datad(\z80_|execute_|ctl_mWrite~6_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_apin_mux~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_apin_mux~2 .lut_mask = 16'hAF0F;
|
|
defparam \z80_|execute_|ctl_apin_mux~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y13_N8
|
|
cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[10]~10 (
|
|
// Equation(s):
|
|
// \z80_|address_pins_|DFFE_apin_latch[10]~10_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [10])))
|
|
|
|
.dataa(\z80_|execute_|ctl_apin_mux~2_combout ),
|
|
.datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d1_out~combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|address_latch_|abusz [10]),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .lut_mask = 16'hDD88;
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[10]~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y18_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_apin_mux2~0 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_apin_mux2~0_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|sequencer_|DFFE_T1_ff~q )))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.datab(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.datac(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_apin_mux2~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_apin_mux2~0 .lut_mask = 16'h4545;
|
|
defparam \z80_|execute_|ctl_apin_mux2~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y12_N24
|
|
cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~0 (
|
|
// Equation(s):
|
|
// \z80_|pin_control_|bus_ab_pin_we~0_combout = ((\z80_|execute_|fIORead~3_combout ) # (!\z80_|pin_control_|bus_db_pin_oe~14_combout )) # (!\z80_|sequencer_|DFFE_M1_ff~q )
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.datab(\z80_|execute_|fIORead~3_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|pin_control_|bus_db_pin_oe~14_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|pin_control_|bus_ab_pin_we~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pin_control_|bus_ab_pin_we~0 .lut_mask = 16'hDDFF;
|
|
defparam \z80_|pin_control_|bus_ab_pin_we~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y12_N26
|
|
cycloneive_lcell_comb \z80_|pin_control_|bus_ab_pin_we~1 (
|
|
// Equation(s):
|
|
// \z80_|pin_control_|bus_ab_pin_we~1_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ) # ((!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|execute_|fMRead~36_combout ) # (\z80_|pin_control_|bus_ab_pin_we~0_combout ))))
|
|
|
|
.dataa(\z80_|execute_|fMRead~36_combout ),
|
|
.datab(\z80_|pin_control_|bus_ab_pin_we~0_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|pin_control_|bus_ab_pin_we~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pin_control_|bus_ab_pin_we~1 .lut_mask = 16'hFF0E;
|
|
defparam \z80_|pin_control_|bus_ab_pin_we~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y13_N9
|
|
dffeas \z80_|address_pins_|DFFE_apin_latch[10] (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|address_pins_|DFFE_apin_latch[10]~10_combout ),
|
|
.asdata(\z80_|address_latch_|Q [10]),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(\z80_|execute_|ctl_apin_mux2~0_combout ),
|
|
.ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|address_pins_|DFFE_apin_latch [10]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[10] .is_wysiwyg = "true";
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[10] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOIBUF_X18_Y34_N1
|
|
cycloneive_io_ibuf \PS2_DAT~input (
|
|
.i(PS2_DAT),
|
|
.ibar(gnd),
|
|
.o(\PS2_DAT~input_o ));
|
|
// synopsys translate_off
|
|
defparam \PS2_DAT~input .bus_hold = "false";
|
|
defparam \PS2_DAT~input .simulate_z_as = "z";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOIBUF_X53_Y14_N1
|
|
cycloneive_io_ibuf \KEY[0]~input (
|
|
.i(KEY[0]),
|
|
.ibar(gnd),
|
|
.o(\KEY[0]~input_o ));
|
|
// synopsys translate_off
|
|
defparam \KEY[0]~input .bus_hold = "false";
|
|
defparam \KEY[0]~input .simulate_z_as = "z";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X52_Y17_N6
|
|
cycloneive_lcell_comb reset(
|
|
// Equation(s):
|
|
// \reset~combout = (!\KEY[0]~input_o ) # (!\ula_|pll_|altpll_component|auto_generated|wire_pll1_locked )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\ula_|pll_|altpll_component|auto_generated|wire_pll1_locked ),
|
|
.datad(\KEY[0]~input_o ),
|
|
.cin(gnd),
|
|
.combout(\reset~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam reset.lut_mask = 16'h0FFF;
|
|
defparam reset.sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: CLKCTRL_G8
|
|
cycloneive_clkctrl \reset~clkctrl (
|
|
.ena(vcc),
|
|
.inclk({vcc,vcc,vcc,\reset~combout }),
|
|
.clkselect(2'b00),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.outclk(\reset~clkctrl_outclk ));
|
|
// synopsys translate_off
|
|
defparam \reset~clkctrl .clock_type = "global clock";
|
|
defparam \reset~clkctrl .ena_register_mode = "none";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y10_N0
|
|
cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~3 (
|
|
// Equation(s):
|
|
// \ula_|ps2_keyboard_|bit_count~3_combout = (\ula_|ps2_keyboard_|bit_count [2] & (\ula_|ps2_keyboard_|bit_count [0] & (!\ula_|ps2_keyboard_|bit_count [3] & \ula_|ps2_keyboard_|bit_count [1]))) # (!\ula_|ps2_keyboard_|bit_count [2] &
|
|
// (((\ula_|ps2_keyboard_|bit_count [3] & !\ula_|ps2_keyboard_|bit_count [1]))))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|bit_count [0]),
|
|
.datab(\ula_|ps2_keyboard_|bit_count [2]),
|
|
.datac(\ula_|ps2_keyboard_|bit_count [3]),
|
|
.datad(\ula_|ps2_keyboard_|bit_count [1]),
|
|
.cin(gnd),
|
|
.combout(\ula_|ps2_keyboard_|bit_count~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|bit_count~3 .lut_mask = 16'h0830;
|
|
defparam \ula_|ps2_keyboard_|bit_count~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOIBUF_X9_Y34_N8
|
|
cycloneive_io_ibuf \PS2_CLK~input (
|
|
.i(PS2_CLK),
|
|
.ibar(gnd),
|
|
.o(\PS2_CLK~input_o ));
|
|
// synopsys translate_off
|
|
defparam \PS2_CLK~input .bus_hold = "false";
|
|
defparam \PS2_CLK~input .simulate_z_as = "z";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X16_Y26_N20
|
|
cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[7]~feeder (
|
|
// Equation(s):
|
|
// \ula_|ps2_keyboard_|clk_filter[7]~feeder_combout = \PS2_CLK~input_o
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\PS2_CLK~input_o ),
|
|
.cin(gnd),
|
|
.combout(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .lut_mask = 16'hFF00;
|
|
defparam \ula_|ps2_keyboard_|clk_filter[7]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X16_Y26_N21
|
|
dffeas \ula_|ps2_keyboard_|clk_filter[7] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|ps2_keyboard_|clk_filter[7]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|ps2_keyboard_|clk_filter [7]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|clk_filter[7] .is_wysiwyg = "true";
|
|
defparam \ula_|ps2_keyboard_|clk_filter[7] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X16_Y26_N18
|
|
cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[6]~feeder (
|
|
// Equation(s):
|
|
// \ula_|ps2_keyboard_|clk_filter[6]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [7]
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\ula_|ps2_keyboard_|clk_filter [7]),
|
|
.cin(gnd),
|
|
.combout(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .lut_mask = 16'hFF00;
|
|
defparam \ula_|ps2_keyboard_|clk_filter[6]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X16_Y26_N19
|
|
dffeas \ula_|ps2_keyboard_|clk_filter[6] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|ps2_keyboard_|clk_filter[6]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|ps2_keyboard_|clk_filter [6]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|clk_filter[6] .is_wysiwyg = "true";
|
|
defparam \ula_|ps2_keyboard_|clk_filter[6] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X16_Y26_N0
|
|
cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[5]~feeder (
|
|
// Equation(s):
|
|
// \ula_|ps2_keyboard_|clk_filter[5]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [6]
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\ula_|ps2_keyboard_|clk_filter [6]),
|
|
.cin(gnd),
|
|
.combout(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .lut_mask = 16'hFF00;
|
|
defparam \ula_|ps2_keyboard_|clk_filter[5]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X16_Y26_N1
|
|
dffeas \ula_|ps2_keyboard_|clk_filter[5] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|ps2_keyboard_|clk_filter[5]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|ps2_keyboard_|clk_filter [5]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|clk_filter[5] .is_wysiwyg = "true";
|
|
defparam \ula_|ps2_keyboard_|clk_filter[5] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X16_Y26_N6
|
|
cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[4]~feeder (
|
|
// Equation(s):
|
|
// \ula_|ps2_keyboard_|clk_filter[4]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [5]
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\ula_|ps2_keyboard_|clk_filter [5]),
|
|
.cin(gnd),
|
|
.combout(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .lut_mask = 16'hFF00;
|
|
defparam \ula_|ps2_keyboard_|clk_filter[4]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X16_Y26_N7
|
|
dffeas \ula_|ps2_keyboard_|clk_filter[4] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|ps2_keyboard_|clk_filter[4]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|ps2_keyboard_|clk_filter [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|clk_filter[4] .is_wysiwyg = "true";
|
|
defparam \ula_|ps2_keyboard_|clk_filter[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X16_Y26_N10
|
|
cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[3]~feeder (
|
|
// Equation(s):
|
|
// \ula_|ps2_keyboard_|clk_filter[3]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [4]
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\ula_|ps2_keyboard_|clk_filter [4]),
|
|
.cin(gnd),
|
|
.combout(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .lut_mask = 16'hFF00;
|
|
defparam \ula_|ps2_keyboard_|clk_filter[3]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X16_Y26_N11
|
|
dffeas \ula_|ps2_keyboard_|clk_filter[3] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|ps2_keyboard_|clk_filter[3]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|ps2_keyboard_|clk_filter [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|clk_filter[3] .is_wysiwyg = "true";
|
|
defparam \ula_|ps2_keyboard_|clk_filter[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X16_Y26_N24
|
|
cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[2]~feeder (
|
|
// Equation(s):
|
|
// \ula_|ps2_keyboard_|clk_filter[2]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [3]
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\ula_|ps2_keyboard_|clk_filter [3]),
|
|
.cin(gnd),
|
|
.combout(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .lut_mask = 16'hFF00;
|
|
defparam \ula_|ps2_keyboard_|clk_filter[2]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X16_Y26_N25
|
|
dffeas \ula_|ps2_keyboard_|clk_filter[2] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|ps2_keyboard_|clk_filter[2]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|ps2_keyboard_|clk_filter [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|clk_filter[2] .is_wysiwyg = "true";
|
|
defparam \ula_|ps2_keyboard_|clk_filter[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X16_Y26_N26
|
|
cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[1]~feeder (
|
|
// Equation(s):
|
|
// \ula_|ps2_keyboard_|clk_filter[1]~feeder_combout = \ula_|ps2_keyboard_|clk_filter [2]
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\ula_|ps2_keyboard_|clk_filter [2]),
|
|
.cin(gnd),
|
|
.combout(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .lut_mask = 16'hFF00;
|
|
defparam \ula_|ps2_keyboard_|clk_filter[1]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X16_Y26_N27
|
|
dffeas \ula_|ps2_keyboard_|clk_filter[1] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|ps2_keyboard_|clk_filter[1]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|ps2_keyboard_|clk_filter [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|clk_filter[1] .is_wysiwyg = "true";
|
|
defparam \ula_|ps2_keyboard_|clk_filter[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X16_Y26_N16
|
|
cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~0 (
|
|
// Equation(s):
|
|
// \ula_|ps2_keyboard_|Equal0~0_combout = (!\ula_|ps2_keyboard_|clk_filter [4] & (!\ula_|ps2_keyboard_|clk_filter [7] & (!\ula_|ps2_keyboard_|clk_filter [6] & !\ula_|ps2_keyboard_|clk_filter [5])))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|clk_filter [4]),
|
|
.datab(\ula_|ps2_keyboard_|clk_filter [7]),
|
|
.datac(\ula_|ps2_keyboard_|clk_filter [6]),
|
|
.datad(\ula_|ps2_keyboard_|clk_filter [5]),
|
|
.cin(gnd),
|
|
.combout(\ula_|ps2_keyboard_|Equal0~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|Equal0~0 .lut_mask = 16'h0001;
|
|
defparam \ula_|ps2_keyboard_|Equal0~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X16_Y26_N12
|
|
cycloneive_lcell_comb \ula_|ps2_keyboard_|Equal0~1 (
|
|
// Equation(s):
|
|
// \ula_|ps2_keyboard_|Equal0~1_combout = (!\ula_|ps2_keyboard_|clk_filter [3] & (!\ula_|ps2_keyboard_|clk_filter [2] & (!\ula_|ps2_keyboard_|clk_filter [1] & \ula_|ps2_keyboard_|Equal0~0_combout )))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|clk_filter [3]),
|
|
.datab(\ula_|ps2_keyboard_|clk_filter [2]),
|
|
.datac(\ula_|ps2_keyboard_|clk_filter [1]),
|
|
.datad(\ula_|ps2_keyboard_|Equal0~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|ps2_keyboard_|Equal0~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|Equal0~1 .lut_mask = 16'h0100;
|
|
defparam \ula_|ps2_keyboard_|Equal0~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X16_Y26_N2
|
|
cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_filter[0]~0 (
|
|
// Equation(s):
|
|
// \ula_|ps2_keyboard_|clk_filter[0]~0_combout = !\ula_|ps2_keyboard_|clk_filter [1]
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\ula_|ps2_keyboard_|clk_filter [1]),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .lut_mask = 16'h0F0F;
|
|
defparam \ula_|ps2_keyboard_|clk_filter[0]~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X16_Y26_N3
|
|
dffeas \ula_|ps2_keyboard_|clk_filter[0] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|ps2_keyboard_|clk_filter[0]~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|ps2_keyboard_|clk_filter [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|clk_filter[0] .is_wysiwyg = "true";
|
|
defparam \ula_|ps2_keyboard_|clk_filter[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X16_Y26_N22
|
|
cycloneive_lcell_comb \ula_|ps2_keyboard_|ps2_clk_in~0 (
|
|
// Equation(s):
|
|
// \ula_|ps2_keyboard_|ps2_clk_in~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|clk_filter [0]))) # (!\ula_|ps2_keyboard_|Equal0~1_combout & (\ula_|ps2_keyboard_|ps2_clk_in~q ))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|Equal0~1_combout ),
|
|
.datab(gnd),
|
|
.datac(\ula_|ps2_keyboard_|ps2_clk_in~q ),
|
|
.datad(\ula_|ps2_keyboard_|clk_filter [0]),
|
|
.cin(gnd),
|
|
.combout(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .lut_mask = 16'hFA50;
|
|
defparam \ula_|ps2_keyboard_|ps2_clk_in~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X16_Y26_N23
|
|
dffeas \ula_|ps2_keyboard_|ps2_clk_in (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|ps2_keyboard_|ps2_clk_in~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|ps2_keyboard_|ps2_clk_in~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|ps2_clk_in .is_wysiwyg = "true";
|
|
defparam \ula_|ps2_keyboard_|ps2_clk_in .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X16_Y26_N28
|
|
cycloneive_lcell_comb \ula_|ps2_keyboard_|clk_edge~0 (
|
|
// Equation(s):
|
|
// \ula_|ps2_keyboard_|clk_edge~0_combout = (\ula_|ps2_keyboard_|Equal0~1_combout & (!\ula_|ps2_keyboard_|ps2_clk_in~q & \ula_|ps2_keyboard_|clk_filter [0]))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|Equal0~1_combout ),
|
|
.datab(gnd),
|
|
.datac(\ula_|ps2_keyboard_|ps2_clk_in~q ),
|
|
.datad(\ula_|ps2_keyboard_|clk_filter [0]),
|
|
.cin(gnd),
|
|
.combout(\ula_|ps2_keyboard_|clk_edge~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|clk_edge~0 .lut_mask = 16'h0A00;
|
|
defparam \ula_|ps2_keyboard_|clk_edge~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X16_Y26_N29
|
|
dffeas \ula_|ps2_keyboard_|clk_edge (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|ps2_keyboard_|clk_edge~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|ps2_keyboard_|clk_edge~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|clk_edge .is_wysiwyg = "true";
|
|
defparam \ula_|ps2_keyboard_|clk_edge .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X21_Y10_N1
|
|
dffeas \ula_|ps2_keyboard_|bit_count[3] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|ps2_keyboard_|bit_count~3_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|ps2_keyboard_|clk_edge~q ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|ps2_keyboard_|bit_count [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|bit_count[3] .is_wysiwyg = "true";
|
|
defparam \ula_|ps2_keyboard_|bit_count[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y10_N28
|
|
cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~1 (
|
|
// Equation(s):
|
|
// \ula_|ps2_keyboard_|bit_count~1_combout = (!\ula_|ps2_keyboard_|bit_count [3] & (\ula_|ps2_keyboard_|bit_count [2] $ (((\ula_|ps2_keyboard_|bit_count [0] & \ula_|ps2_keyboard_|bit_count [1])))))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|bit_count [0]),
|
|
.datab(\ula_|ps2_keyboard_|bit_count [3]),
|
|
.datac(\ula_|ps2_keyboard_|bit_count [2]),
|
|
.datad(\ula_|ps2_keyboard_|bit_count [1]),
|
|
.cin(gnd),
|
|
.combout(\ula_|ps2_keyboard_|bit_count~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|bit_count~1 .lut_mask = 16'h1230;
|
|
defparam \ula_|ps2_keyboard_|bit_count~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X21_Y10_N29
|
|
dffeas \ula_|ps2_keyboard_|bit_count[2] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|ps2_keyboard_|bit_count~1_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|ps2_keyboard_|clk_edge~q ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|ps2_keyboard_|bit_count [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|bit_count[2] .is_wysiwyg = "true";
|
|
defparam \ula_|ps2_keyboard_|bit_count[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y10_N10
|
|
cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~2 (
|
|
// Equation(s):
|
|
// \ula_|ps2_keyboard_|bit_count~2_combout = (\ula_|ps2_keyboard_|bit_count [0] & (!\ula_|ps2_keyboard_|bit_count [1] & ((!\ula_|ps2_keyboard_|bit_count [3]) # (!\ula_|ps2_keyboard_|bit_count [2])))) # (!\ula_|ps2_keyboard_|bit_count [0] &
|
|
// (((\ula_|ps2_keyboard_|bit_count [1] & !\ula_|ps2_keyboard_|bit_count [3]))))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|bit_count [0]),
|
|
.datab(\ula_|ps2_keyboard_|bit_count [2]),
|
|
.datac(\ula_|ps2_keyboard_|bit_count [1]),
|
|
.datad(\ula_|ps2_keyboard_|bit_count [3]),
|
|
.cin(gnd),
|
|
.combout(\ula_|ps2_keyboard_|bit_count~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|bit_count~2 .lut_mask = 16'h025A;
|
|
defparam \ula_|ps2_keyboard_|bit_count~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X21_Y10_N11
|
|
dffeas \ula_|ps2_keyboard_|bit_count[1] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|ps2_keyboard_|bit_count~2_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|ps2_keyboard_|clk_edge~q ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|ps2_keyboard_|bit_count [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|bit_count[1] .is_wysiwyg = "true";
|
|
defparam \ula_|ps2_keyboard_|bit_count[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y10_N22
|
|
cycloneive_lcell_comb \ula_|ps2_keyboard_|bit_count~0 (
|
|
// Equation(s):
|
|
// \ula_|ps2_keyboard_|bit_count~0_combout = (!\ula_|ps2_keyboard_|bit_count [0] & (((!\ula_|ps2_keyboard_|bit_count [1] & !\ula_|ps2_keyboard_|bit_count [2])) # (!\ula_|ps2_keyboard_|bit_count [3])))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|bit_count [1]),
|
|
.datab(\ula_|ps2_keyboard_|bit_count [2]),
|
|
.datac(\ula_|ps2_keyboard_|bit_count [0]),
|
|
.datad(\ula_|ps2_keyboard_|bit_count [3]),
|
|
.cin(gnd),
|
|
.combout(\ula_|ps2_keyboard_|bit_count~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|bit_count~0 .lut_mask = 16'h010F;
|
|
defparam \ula_|ps2_keyboard_|bit_count~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X21_Y10_N23
|
|
dffeas \ula_|ps2_keyboard_|bit_count[0] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|ps2_keyboard_|bit_count~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|ps2_keyboard_|clk_edge~q ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|ps2_keyboard_|bit_count [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|bit_count[0] .is_wysiwyg = "true";
|
|
defparam \ula_|ps2_keyboard_|bit_count[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y10_N2
|
|
cycloneive_lcell_comb \ula_|ps2_keyboard_|always1~0 (
|
|
// Equation(s):
|
|
// \ula_|ps2_keyboard_|always1~0_combout = (!\ula_|ps2_keyboard_|bit_count [1] & (!\ula_|ps2_keyboard_|bit_count [2] & (!\PS2_DAT~input_o & !\ula_|ps2_keyboard_|bit_count [3])))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|bit_count [1]),
|
|
.datab(\ula_|ps2_keyboard_|bit_count [2]),
|
|
.datac(\PS2_DAT~input_o ),
|
|
.datad(\ula_|ps2_keyboard_|bit_count [3]),
|
|
.cin(gnd),
|
|
.combout(\ula_|ps2_keyboard_|always1~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|always1~0 .lut_mask = 16'h0001;
|
|
defparam \ula_|ps2_keyboard_|always1~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y10_N12
|
|
cycloneive_lcell_comb \ula_|ps2_keyboard_|LessThan0~0 (
|
|
// Equation(s):
|
|
// \ula_|ps2_keyboard_|LessThan0~0_combout = (\ula_|ps2_keyboard_|bit_count [3] & ((\ula_|ps2_keyboard_|bit_count [1]) # (\ula_|ps2_keyboard_|bit_count [2])))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|bit_count [1]),
|
|
.datab(\ula_|ps2_keyboard_|bit_count [2]),
|
|
.datac(gnd),
|
|
.datad(\ula_|ps2_keyboard_|bit_count [3]),
|
|
.cin(gnd),
|
|
.combout(\ula_|ps2_keyboard_|LessThan0~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|LessThan0~0 .lut_mask = 16'hEE00;
|
|
defparam \ula_|ps2_keyboard_|LessThan0~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y10_N26
|
|
cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[0]~0 (
|
|
// Equation(s):
|
|
// \ula_|ps2_keyboard_|shiftreg[0]~0_combout = (\ula_|ps2_keyboard_|clk_edge~q & (!\ula_|ps2_keyboard_|LessThan0~0_combout & ((\ula_|ps2_keyboard_|bit_count [0]) # (!\ula_|ps2_keyboard_|always1~0_combout ))))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|bit_count [0]),
|
|
.datab(\ula_|ps2_keyboard_|always1~0_combout ),
|
|
.datac(\ula_|ps2_keyboard_|clk_edge~q ),
|
|
.datad(\ula_|ps2_keyboard_|LessThan0~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .lut_mask = 16'h00B0;
|
|
defparam \ula_|ps2_keyboard_|shiftreg[0]~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X27_Y8_N17
|
|
dffeas \ula_|ps2_keyboard_|shiftreg[8] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\PS2_DAT~input_o ),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|ps2_keyboard_|shiftreg [8]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|shiftreg[8] .is_wysiwyg = "true";
|
|
defparam \ula_|ps2_keyboard_|shiftreg[8] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y8_N14
|
|
cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[7]~feeder (
|
|
// Equation(s):
|
|
// \ula_|ps2_keyboard_|shiftreg[7]~feeder_combout = \ula_|ps2_keyboard_|shiftreg [8]
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [8]),
|
|
.cin(gnd),
|
|
.combout(\ula_|ps2_keyboard_|shiftreg[7]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|shiftreg[7]~feeder .lut_mask = 16'hFF00;
|
|
defparam \ula_|ps2_keyboard_|shiftreg[7]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X27_Y8_N15
|
|
dffeas \ula_|ps2_keyboard_|shiftreg[7] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|ps2_keyboard_|shiftreg[7]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|ps2_keyboard_|shiftreg [7]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|shiftreg[7] .is_wysiwyg = "true";
|
|
defparam \ula_|ps2_keyboard_|shiftreg[7] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X27_Y8_N9
|
|
dffeas \ula_|ps2_keyboard_|shiftreg[6] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\ula_|ps2_keyboard_|shiftreg [7]),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|ps2_keyboard_|shiftreg [6]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|shiftreg[6] .is_wysiwyg = "true";
|
|
defparam \ula_|ps2_keyboard_|shiftreg[6] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X27_Y8_N5
|
|
dffeas \ula_|ps2_keyboard_|shiftreg[5] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\ula_|ps2_keyboard_|shiftreg [6]),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|ps2_keyboard_|shiftreg [5]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|shiftreg[5] .is_wysiwyg = "true";
|
|
defparam \ula_|ps2_keyboard_|shiftreg[5] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X27_Y8_N23
|
|
dffeas \ula_|ps2_keyboard_|shiftreg[4] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\ula_|ps2_keyboard_|shiftreg [5]),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|ps2_keyboard_|shiftreg [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|shiftreg[4] .is_wysiwyg = "true";
|
|
defparam \ula_|ps2_keyboard_|shiftreg[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X29_Y9_N17
|
|
dffeas \ula_|ps2_keyboard_|shiftreg[3] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\ula_|ps2_keyboard_|shiftreg [4]),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|ps2_keyboard_|shiftreg [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|shiftreg[3] .is_wysiwyg = "true";
|
|
defparam \ula_|ps2_keyboard_|shiftreg[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X29_Y8_N23
|
|
dffeas \ula_|ps2_keyboard_|shiftreg[2] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\ula_|ps2_keyboard_|shiftreg [3]),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|ps2_keyboard_|shiftreg [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|shiftreg[2] .is_wysiwyg = "true";
|
|
defparam \ula_|ps2_keyboard_|shiftreg[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X29_Y8_N21
|
|
dffeas \ula_|ps2_keyboard_|shiftreg[1] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\ula_|ps2_keyboard_|shiftreg [2]),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|ps2_keyboard_|shiftreg [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|shiftreg[1] .is_wysiwyg = "true";
|
|
defparam \ula_|ps2_keyboard_|shiftreg[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y10_N18
|
|
cycloneive_lcell_comb \ula_|ps2_keyboard_|shiftreg[0]~feeder (
|
|
// Equation(s):
|
|
// \ula_|ps2_keyboard_|shiftreg[0]~feeder_combout = \ula_|ps2_keyboard_|shiftreg [1]
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [1]),
|
|
.cin(gnd),
|
|
.combout(\ula_|ps2_keyboard_|shiftreg[0]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|shiftreg[0]~feeder .lut_mask = 16'hFF00;
|
|
defparam \ula_|ps2_keyboard_|shiftreg[0]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X26_Y10_N19
|
|
dffeas \ula_|ps2_keyboard_|shiftreg[0] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|ps2_keyboard_|shiftreg[0]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|ps2_keyboard_|shiftreg[0]~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|ps2_keyboard_|shiftreg [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|shiftreg[0] .is_wysiwyg = "true";
|
|
defparam \ula_|ps2_keyboard_|shiftreg[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y10_N4
|
|
cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~0 (
|
|
// Equation(s):
|
|
// \ula_|ps2_keyboard_|WideXor0~0_combout = \ula_|ps2_keyboard_|shiftreg [1] $ (\ula_|ps2_keyboard_|shiftreg [0] $ (\ula_|ps2_keyboard_|shiftreg [3] $ (\ula_|ps2_keyboard_|shiftreg [2])))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [1]),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [0]),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [3]),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [2]),
|
|
.cin(gnd),
|
|
.combout(\ula_|ps2_keyboard_|WideXor0~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|WideXor0~0 .lut_mask = 16'h6996;
|
|
defparam \ula_|ps2_keyboard_|WideXor0~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y8_N16
|
|
cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~1 (
|
|
// Equation(s):
|
|
// \ula_|ps2_keyboard_|WideXor0~1_combout = \ula_|ps2_keyboard_|shiftreg [6] $ (\ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [8] $ (\ula_|ps2_keyboard_|shiftreg [7])))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [6]),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [5]),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [8]),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [7]),
|
|
.cin(gnd),
|
|
.combout(\ula_|ps2_keyboard_|WideXor0~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|WideXor0~1 .lut_mask = 16'h6996;
|
|
defparam \ula_|ps2_keyboard_|WideXor0~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y10_N22
|
|
cycloneive_lcell_comb \ula_|ps2_keyboard_|WideXor0~2 (
|
|
// Equation(s):
|
|
// \ula_|ps2_keyboard_|WideXor0~2_combout = \ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|WideXor0~0_combout $ (\ula_|ps2_keyboard_|WideXor0~1_combout ))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [4]),
|
|
.datab(gnd),
|
|
.datac(\ula_|ps2_keyboard_|WideXor0~0_combout ),
|
|
.datad(\ula_|ps2_keyboard_|WideXor0~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|ps2_keyboard_|WideXor0~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|WideXor0~2 .lut_mask = 16'hA55A;
|
|
defparam \ula_|ps2_keyboard_|WideXor0~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y10_N4
|
|
cycloneive_lcell_comb \ula_|ps2_keyboard_|scan_code_ready~0 (
|
|
// Equation(s):
|
|
// \ula_|ps2_keyboard_|scan_code_ready~0_combout = (\PS2_DAT~input_o & (\ula_|ps2_keyboard_|clk_edge~q & (\ula_|ps2_keyboard_|WideXor0~2_combout & \ula_|ps2_keyboard_|LessThan0~0_combout )))
|
|
|
|
.dataa(\PS2_DAT~input_o ),
|
|
.datab(\ula_|ps2_keyboard_|clk_edge~q ),
|
|
.datac(\ula_|ps2_keyboard_|WideXor0~2_combout ),
|
|
.datad(\ula_|ps2_keyboard_|LessThan0~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|ps2_keyboard_|scan_code_ready~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|scan_code_ready~0 .lut_mask = 16'h8000;
|
|
defparam \ula_|ps2_keyboard_|scan_code_ready~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X21_Y10_N5
|
|
dffeas \ula_|ps2_keyboard_|scan_code_ready (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|ps2_keyboard_|scan_code_ready~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|ps2_keyboard_|scan_code_ready~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|ps2_keyboard_|scan_code_ready .is_wysiwyg = "true";
|
|
defparam \ula_|ps2_keyboard_|scan_code_ready .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y8_N22
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~0 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|Equal0~0_combout = (\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [5])))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [7]),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [0]),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [3]),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [5]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|Equal0~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|Equal0~0 .lut_mask = 16'h0200;
|
|
defparam \ula_|zx_keyboard_|Equal0~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y8_N28
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~1 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|Equal0~1_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|Equal0~0_combout & !\ula_|ps2_keyboard_|shiftreg [1])))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [6]),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [2]),
|
|
.datac(\ula_|zx_keyboard_|Equal0~0_combout ),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [1]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|Equal0~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|Equal0~1 .lut_mask = 16'h0020;
|
|
defparam \ula_|zx_keyboard_|Equal0~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y8_N24
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|released~0 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|released~0_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|ps2_keyboard_|shiftreg [4]) # (\ula_|zx_keyboard_|released~q )))) # (!\ula_|ps2_keyboard_|scan_code_ready~q &
|
|
// (((\ula_|zx_keyboard_|released~q ))))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [4]),
|
|
.datab(\ula_|ps2_keyboard_|scan_code_ready~q ),
|
|
.datac(\ula_|zx_keyboard_|released~q ),
|
|
.datad(\ula_|zx_keyboard_|Equal0~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|released~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|released~0 .lut_mask = 16'hF830;
|
|
defparam \ula_|zx_keyboard_|released~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X27_Y8_N25
|
|
dffeas \ula_|zx_keyboard_|released (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|zx_keyboard_|released~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|zx_keyboard_|released~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|released .is_wysiwyg = "true";
|
|
defparam \ula_|zx_keyboard_|released .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y8_N30
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|extended~0 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|extended~0_combout = (\ula_|zx_keyboard_|Equal0~1_combout & ((\ula_|zx_keyboard_|extended~q ) # (!\ula_|ps2_keyboard_|shiftreg [4])))
|
|
|
|
.dataa(\ula_|zx_keyboard_|Equal0~1_combout ),
|
|
.datab(gnd),
|
|
.datac(\ula_|zx_keyboard_|extended~q ),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [4]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|extended~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|extended~0 .lut_mask = 16'hA0AA;
|
|
defparam \ula_|zx_keyboard_|extended~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X28_Y8_N31
|
|
dffeas \ula_|zx_keyboard_|extended (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|zx_keyboard_|extended~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|ps2_keyboard_|scan_code_ready~q ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|zx_keyboard_|extended~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|extended .is_wysiwyg = "true";
|
|
defparam \ula_|zx_keyboard_|extended .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y8_N0
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~21 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[7][1]~21_combout = (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [7] & \ula_|ps2_keyboard_|scan_code_ready~q ))
|
|
|
|
.dataa(\ula_|zx_keyboard_|extended~q ),
|
|
.datab(gnd),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [7]),
|
|
.datad(\ula_|ps2_keyboard_|scan_code_ready~q ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[7][1]~21_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[7][1]~21 .lut_mask = 16'h0500;
|
|
defparam \ula_|zx_keyboard_|keys[7][1]~21 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y8_N20
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~22 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[5][4]~22_combout = (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [4])
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [2]),
|
|
.datab(gnd),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [4]),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[5][4]~22_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[5][4]~22 .lut_mask = 16'hA0A0;
|
|
defparam \ula_|zx_keyboard_|keys[5][4]~22 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y9_N28
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~23 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[1][4]~23_combout = (\ula_|zx_keyboard_|keys[7][1]~21_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][4]~22_combout & !\ula_|ps2_keyboard_|shiftreg [1])))
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[7][1]~21_combout ),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [6]),
|
|
.datac(\ula_|zx_keyboard_|keys[5][4]~22_combout ),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [1]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[1][4]~23_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[1][4]~23 .lut_mask = 16'h0020;
|
|
defparam \ula_|zx_keyboard_|keys[1][4]~23 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y9_N2
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~24 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[2][1]~24_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[1][4]~23_combout ))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [0]),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [5]),
|
|
.datac(gnd),
|
|
.datad(\ula_|zx_keyboard_|keys[1][4]~23_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[2][1]~24_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[2][1]~24 .lut_mask = 16'h2200;
|
|
defparam \ula_|zx_keyboard_|keys[2][1]~24 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y9_N20
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][1]~25 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[2][1]~25_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~24_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][1]~24_combout & ((\ula_|zx_keyboard_|keys[2][1]~q ))))) #
|
|
// (!\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][1]~q ))))
|
|
|
|
.dataa(\ula_|zx_keyboard_|released~q ),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [3]),
|
|
.datac(\ula_|zx_keyboard_|keys[2][1]~q ),
|
|
.datad(\ula_|zx_keyboard_|keys[2][1]~24_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[2][1]~25_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[2][1]~25 .lut_mask = 16'h74F0;
|
|
defparam \ula_|zx_keyboard_|keys[2][1]~25 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X27_Y9_N21
|
|
dffeas \ula_|zx_keyboard_|keys[2][1] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|zx_keyboard_|keys[2][1]~25_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|zx_keyboard_|keys[2][1]~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[2][1] .is_wysiwyg = "true";
|
|
defparam \ula_|zx_keyboard_|keys[2][1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y9_N30
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~0 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|key_row~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [10]) # (!\ula_|zx_keyboard_|keys[2][1]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.datac(\z80_|address_pins_|DFFE_apin_latch [10]),
|
|
.datad(\ula_|zx_keyboard_|keys[2][1]~q ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|key_row~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|key_row~0 .lut_mask = 16'hF3FF;
|
|
defparam \ula_|zx_keyboard_|key_row~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y9_N16
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~26 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[3][1]~26_combout = (\ula_|zx_keyboard_|keys[7][1]~21_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|keys[5][4]~22_combout & !\ula_|ps2_keyboard_|shiftreg [5])))
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[7][1]~21_combout ),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [6]),
|
|
.datac(\ula_|zx_keyboard_|keys[5][4]~22_combout ),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [5]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[3][1]~26_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[3][1]~26 .lut_mask = 16'h0020;
|
|
defparam \ula_|zx_keyboard_|keys[3][1]~26 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y9_N10
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~27 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[3][1]~27_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [3]))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [1]),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [0]),
|
|
.datac(gnd),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [3]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[3][1]~27_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[3][1]~27 .lut_mask = 16'h2200;
|
|
defparam \ula_|zx_keyboard_|keys[3][1]~27 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y9_N28
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][1]~28 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[3][1]~28_combout = (\ula_|zx_keyboard_|keys[3][1]~26_combout & ((\ula_|zx_keyboard_|keys[3][1]~27_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][1]~27_combout & ((\ula_|zx_keyboard_|keys[3][1]~q
|
|
// ))))) # (!\ula_|zx_keyboard_|keys[3][1]~26_combout & (((\ula_|zx_keyboard_|keys[3][1]~q ))))
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[3][1]~26_combout ),
|
|
.datab(\ula_|zx_keyboard_|released~q ),
|
|
.datac(\ula_|zx_keyboard_|keys[3][1]~q ),
|
|
.datad(\ula_|zx_keyboard_|keys[3][1]~27_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[3][1]~28_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[3][1]~28 .lut_mask = 16'h72F0;
|
|
defparam \ula_|zx_keyboard_|keys[3][1]~28 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X28_Y9_N29
|
|
dffeas \ula_|zx_keyboard_|keys[3][1] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|zx_keyboard_|keys[3][1]~28_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|zx_keyboard_|keys[3][1]~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[3][1] .is_wysiwyg = "true";
|
|
defparam \ula_|zx_keyboard_|keys[3][1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y13_N12
|
|
cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[11]~11 (
|
|
// Equation(s):
|
|
// \z80_|address_pins_|DFFE_apin_latch[11]~11_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [11])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [11])))
|
|
|
|
.dataa(\z80_|execute_|ctl_apin_mux~2_combout ),
|
|
.datab(\z80_|address_latch_|b2v_inst_inc_dec|address [11]),
|
|
.datac(gnd),
|
|
.datad(\z80_|address_latch_|abusz [11]),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .lut_mask = 16'hDD88;
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[11]~11 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y13_N13
|
|
dffeas \z80_|address_pins_|DFFE_apin_latch[11] (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|address_pins_|DFFE_apin_latch[11]~11_combout ),
|
|
.asdata(\z80_|address_latch_|Q [11]),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(\z80_|execute_|ctl_apin_mux2~0_combout ),
|
|
.ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|address_pins_|DFFE_apin_latch [11]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[11] .is_wysiwyg = "true";
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[11] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y6_N16
|
|
cycloneive_lcell_comb \z80_|address_pins_|abus[11]~19 (
|
|
// Equation(s):
|
|
// \z80_|address_pins_|abus[11]~19_combout = (\z80_|address_pins_|DFFE_apin_latch [11]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.datad(\z80_|address_pins_|DFFE_apin_latch [11]),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_pins_|abus[11]~19_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|abus[11]~19 .lut_mask = 16'hFF0F;
|
|
defparam \z80_|address_pins_|abus[11]~19 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y8_N30
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~17 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[7][4]~17_combout = (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [7] & \ula_|ps2_keyboard_|scan_code_ready~q )))
|
|
|
|
.dataa(\ula_|zx_keyboard_|extended~q ),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [6]),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [7]),
|
|
.datad(\ula_|ps2_keyboard_|scan_code_ready~q ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[7][4]~17_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[7][4]~17 .lut_mask = 16'h0100;
|
|
defparam \ula_|zx_keyboard_|keys[7][4]~17 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y7_N18
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~18 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[6][4]~18_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [1])))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [2]),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [4]),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [0]),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [1]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[6][4]~18_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[6][4]~18 .lut_mask = 16'h4000;
|
|
defparam \ula_|zx_keyboard_|keys[6][4]~18 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y7_N2
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~19 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[1][1]~19_combout = (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[7][4]~17_combout & \ula_|zx_keyboard_|keys[6][4]~18_combout )))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [5]),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [3]),
|
|
.datac(\ula_|zx_keyboard_|keys[7][4]~17_combout ),
|
|
.datad(\ula_|zx_keyboard_|keys[6][4]~18_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[1][1]~19_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[1][1]~19 .lut_mask = 16'h4000;
|
|
defparam \ula_|zx_keyboard_|keys[1][1]~19 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y7_N16
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][1]~20 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[1][1]~20_combout = (\ula_|zx_keyboard_|keys[1][1]~19_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][1]~19_combout & ((\ula_|zx_keyboard_|keys[1][1]~q )))
|
|
|
|
.dataa(\ula_|zx_keyboard_|released~q ),
|
|
.datab(gnd),
|
|
.datac(\ula_|zx_keyboard_|keys[1][1]~q ),
|
|
.datad(\ula_|zx_keyboard_|keys[1][1]~19_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[1][1]~20_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[1][1]~20 .lut_mask = 16'h55F0;
|
|
defparam \ula_|zx_keyboard_|keys[1][1]~20 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X27_Y7_N17
|
|
dffeas \ula_|zx_keyboard_|keys[1][1] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|zx_keyboard_|keys[1][1]~20_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|zx_keyboard_|keys[1][1]~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[1][1] .is_wysiwyg = "true";
|
|
defparam \ula_|zx_keyboard_|keys[1][1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y10_N4
|
|
cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[9]~9 (
|
|
// Equation(s):
|
|
// \z80_|address_pins_|DFFE_apin_latch[9]~9_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [9])))
|
|
|
|
.dataa(\z80_|execute_|ctl_apin_mux~2_combout ),
|
|
.datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_9|d0_out~combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|address_latch_|abusz [9]),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .lut_mask = 16'hDD88;
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[9]~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y10_N5
|
|
dffeas \z80_|address_pins_|DFFE_apin_latch[9] (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|address_pins_|DFFE_apin_latch[9]~9_combout ),
|
|
.asdata(\z80_|address_latch_|Q [9]),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(\z80_|execute_|ctl_apin_mux2~0_combout ),
|
|
.ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|address_pins_|DFFE_apin_latch [9]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[9] .is_wysiwyg = "true";
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[9] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y10_N10
|
|
cycloneive_lcell_comb \z80_|address_pins_|abus[9]~17 (
|
|
// Equation(s):
|
|
// \z80_|address_pins_|abus[9]~17_combout = (\z80_|address_pins_|DFFE_apin_latch [9]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|address_pins_|DFFE_apin_latch [9]),
|
|
.datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_pins_|abus[9]~17_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|abus[9]~17 .lut_mask = 16'hCFCF;
|
|
defparam \z80_|address_pins_|abus[9]~17 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y8_N28
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~13 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[0][0]~13_combout = (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|ps2_keyboard_|shiftreg [7] & !\ula_|zx_keyboard_|Equal0~1_combout ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|ps2_keyboard_|scan_code_ready~q ),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [7]),
|
|
.datad(\ula_|zx_keyboard_|Equal0~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[0][0]~13_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[0][0]~13 .lut_mask = 16'h000C;
|
|
defparam \ula_|zx_keyboard_|keys[0][0]~13 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y7_N16
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~2 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|shifted~2_combout = (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|zx_keyboard_|extended~q & \ula_|zx_keyboard_|keys[0][0]~13_combout ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [5]),
|
|
.datac(\ula_|zx_keyboard_|extended~q ),
|
|
.datad(\ula_|zx_keyboard_|keys[0][0]~13_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|shifted~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|shifted~2 .lut_mask = 16'h0300;
|
|
defparam \ula_|zx_keyboard_|shifted~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y10_N16
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~14 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[0][1]~14_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [4] $ (\ula_|ps2_keyboard_|shiftreg [2]))))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [4]),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [0]),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [3]),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [2]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[0][1]~14_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[0][1]~14 .lut_mask = 16'h1020;
|
|
defparam \ula_|zx_keyboard_|keys[0][1]~14 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y10_N2
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~15 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[0][1]~15_combout = (\ula_|zx_keyboard_|keys[0][1]~14_combout & ((\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [1])) # (!\ula_|ps2_keyboard_|shiftreg [4] &
|
|
// (\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [1]))))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [4]),
|
|
.datab(\ula_|zx_keyboard_|keys[0][1]~14_combout ),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [6]),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [1]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[0][1]~15_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[0][1]~15 .lut_mask = 16'h0840;
|
|
defparam \ula_|zx_keyboard_|keys[0][1]~15 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y10_N6
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr17~0 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|WideOr17~0_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|ps2_keyboard_|shiftreg [1] &
|
|
// (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [3])))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [1]),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [0]),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [6]),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [3]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|WideOr17~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|WideOr17~0 .lut_mask = 16'h4002;
|
|
defparam \ula_|zx_keyboard_|WideOr17~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y10_N30
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~5 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|shifted~5_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|WideOr17~0_combout ))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [4]),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [2]),
|
|
.datac(\ula_|zx_keyboard_|WideOr17~0_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|shifted~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|shifted~5 .lut_mask = 16'h2020;
|
|
defparam \ula_|zx_keyboard_|shifted~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y10_N26
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~4 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|shifted~4_combout = (\ula_|zx_keyboard_|shifted~5_combout & ((\ula_|zx_keyboard_|shifted~2_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|shifted~2_combout & ((\ula_|zx_keyboard_|shifted~q ))))) #
|
|
// (!\ula_|zx_keyboard_|shifted~5_combout & (((\ula_|zx_keyboard_|shifted~q ))))
|
|
|
|
.dataa(\ula_|zx_keyboard_|shifted~5_combout ),
|
|
.datab(\ula_|zx_keyboard_|released~q ),
|
|
.datac(\ula_|zx_keyboard_|shifted~q ),
|
|
.datad(\ula_|zx_keyboard_|shifted~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|shifted~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|shifted~4 .lut_mask = 16'h72F0;
|
|
defparam \ula_|zx_keyboard_|shifted~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X26_Y10_N27
|
|
dffeas \ula_|zx_keyboard_|shifted (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|zx_keyboard_|shifted~4_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|zx_keyboard_|shifted~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|shifted .is_wysiwyg = "true";
|
|
defparam \ula_|zx_keyboard_|shifted .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y10_N0
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~12 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[0][1]~12_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [4]))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|zx_keyboard_|released~q ),
|
|
.datac(\ula_|zx_keyboard_|shifted~q ),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [4]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[0][1]~12_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[0][1]~12 .lut_mask = 16'hCCCF;
|
|
defparam \ula_|zx_keyboard_|keys[0][1]~12 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y10_N20
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][1]~16 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[0][1]~16_combout = (\ula_|zx_keyboard_|shifted~2_combout & ((\ula_|zx_keyboard_|keys[0][1]~15_combout & ((!\ula_|zx_keyboard_|keys[0][1]~12_combout ))) # (!\ula_|zx_keyboard_|keys[0][1]~15_combout &
|
|
// (\ula_|zx_keyboard_|keys[0][1]~q )))) # (!\ula_|zx_keyboard_|shifted~2_combout & (((\ula_|zx_keyboard_|keys[0][1]~q ))))
|
|
|
|
.dataa(\ula_|zx_keyboard_|shifted~2_combout ),
|
|
.datab(\ula_|zx_keyboard_|keys[0][1]~15_combout ),
|
|
.datac(\ula_|zx_keyboard_|keys[0][1]~q ),
|
|
.datad(\ula_|zx_keyboard_|keys[0][1]~12_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[0][1]~16_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[0][1]~16 .lut_mask = 16'h70F8;
|
|
defparam \ula_|zx_keyboard_|keys[0][1]~16 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X26_Y10_N21
|
|
dffeas \ula_|zx_keyboard_|keys[0][1] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|zx_keyboard_|keys[0][1]~16_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|zx_keyboard_|keys[0][1]~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[0][1] .is_wysiwyg = "true";
|
|
defparam \ula_|zx_keyboard_|keys[0][1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y10_N0
|
|
cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[8]~8 (
|
|
// Equation(s):
|
|
// \z80_|address_pins_|DFFE_apin_latch[8]~8_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [8])))
|
|
|
|
.dataa(\z80_|execute_|ctl_apin_mux~2_combout ),
|
|
.datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d1_out~combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|address_latch_|abusz [8]),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .lut_mask = 16'hDD88;
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[8]~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y10_N1
|
|
dffeas \z80_|address_pins_|DFFE_apin_latch[8] (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|address_pins_|DFFE_apin_latch[8]~8_combout ),
|
|
.asdata(\z80_|address_latch_|Q [8]),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(\z80_|execute_|ctl_apin_mux2~0_combout ),
|
|
.ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|address_pins_|DFFE_apin_latch [8]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[8] .is_wysiwyg = "true";
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[8] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y9_N24
|
|
cycloneive_lcell_comb \z80_|address_pins_|abus[8]~18 (
|
|
// Equation(s):
|
|
// \z80_|address_pins_|abus[8]~18_combout = (\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.datad(\z80_|address_pins_|DFFE_apin_latch [8]),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_pins_|abus[8]~18_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|abus[8]~18 .lut_mask = 16'hFF0F;
|
|
defparam \z80_|address_pins_|abus[8]~18 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y9_N2
|
|
cycloneive_lcell_comb \D[1]~26 (
|
|
// Equation(s):
|
|
// \D[1]~26_combout = (\ula_|zx_keyboard_|keys[1][1]~q & (\z80_|address_pins_|abus[9]~17_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][1]~q )))) # (!\ula_|zx_keyboard_|keys[1][1]~q &
|
|
// (((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][1]~q ))))
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[1][1]~q ),
|
|
.datab(\z80_|address_pins_|abus[9]~17_combout ),
|
|
.datac(\ula_|zx_keyboard_|keys[0][1]~q ),
|
|
.datad(\z80_|address_pins_|abus[8]~18_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[1]~26_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[1]~26 .lut_mask = 16'hDD0D;
|
|
defparam \D[1]~26 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y9_N4
|
|
cycloneive_lcell_comb \D[1]~27 (
|
|
// Equation(s):
|
|
// \D[1]~27_combout = (\ula_|zx_keyboard_|key_row~0_combout & (\D[1]~26_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][1]~q ))))
|
|
|
|
.dataa(\ula_|zx_keyboard_|key_row~0_combout ),
|
|
.datab(\ula_|zx_keyboard_|keys[3][1]~q ),
|
|
.datac(\z80_|address_pins_|abus[11]~19_combout ),
|
|
.datad(\D[1]~26_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[1]~27_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[1]~27 .lut_mask = 16'hA200;
|
|
defparam \D[1]~27 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y13_N16
|
|
cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[12]~12 (
|
|
// Equation(s):
|
|
// \z80_|address_pins_|DFFE_apin_latch[12]~12_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [12])))
|
|
|
|
.dataa(\z80_|execute_|ctl_apin_mux~2_combout ),
|
|
.datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d0_out~combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|address_latch_|abusz [12]),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .lut_mask = 16'hDD88;
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[12]~12 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y13_N17
|
|
dffeas \z80_|address_pins_|DFFE_apin_latch[12] (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|address_pins_|DFFE_apin_latch[12]~12_combout ),
|
|
.asdata(\z80_|address_latch_|Q [12]),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(\z80_|execute_|ctl_apin_mux2~0_combout ),
|
|
.ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|address_pins_|DFFE_apin_latch [12]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[12] .is_wysiwyg = "true";
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[12] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y10_N28
|
|
cycloneive_lcell_comb \z80_|address_pins_|abus[12]~21 (
|
|
// Equation(s):
|
|
// \z80_|address_pins_|abus[12]~21_combout = (\z80_|address_pins_|DFFE_apin_latch [12]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.datad(\z80_|address_pins_|DFFE_apin_latch [12]),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_pins_|abus[12]~21_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|abus[12]~21 .lut_mask = 16'hFF0F;
|
|
defparam \z80_|address_pins_|abus[12]~21 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y13_N2
|
|
cycloneive_lcell_comb \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout = \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout $ (\z80_|address_latch_|Q [13])
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|SYNTHESIZED_WIRE_0~0_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|address_latch_|Q [13]),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .lut_mask = 16'h33CC;
|
|
defparam \z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y13_N6
|
|
cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[13]~13 (
|
|
// Equation(s):
|
|
// \z80_|address_pins_|DFFE_apin_latch[13]~13_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [13]))
|
|
|
|
.dataa(\z80_|execute_|ctl_apin_mux~2_combout ),
|
|
.datab(\z80_|address_latch_|abusz [13]),
|
|
.datac(gnd),
|
|
.datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .lut_mask = 16'hEE44;
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[13]~13 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y13_N7
|
|
dffeas \z80_|address_pins_|DFFE_apin_latch[13] (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|address_pins_|DFFE_apin_latch[13]~13_combout ),
|
|
.asdata(\z80_|address_latch_|Q [13]),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(\z80_|execute_|ctl_apin_mux2~0_combout ),
|
|
.ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|address_pins_|DFFE_apin_latch [13]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[13] .is_wysiwyg = "true";
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[13] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y10_N6
|
|
cycloneive_lcell_comb \z80_|address_pins_|abus[13]~20 (
|
|
// Equation(s):
|
|
// \z80_|address_pins_|abus[13]~20_combout = (\z80_|address_pins_|DFFE_apin_latch [13]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.datac(gnd),
|
|
.datad(\z80_|address_pins_|DFFE_apin_latch [13]),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_pins_|abus[13]~20_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|abus[13]~20 .lut_mask = 16'hFF33;
|
|
defparam \z80_|address_pins_|abus[13]~20 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y10_N12
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~36 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[5][1]~36_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [5]))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [1]),
|
|
.datab(gnd),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [0]),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [5]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[5][1]~36_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[5][1]~36 .lut_mask = 16'h0005;
|
|
defparam \ula_|zx_keyboard_|keys[5][1]~36 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y7_N4
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~34 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[5][1]~34_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|zx_keyboard_|extended~q & \ula_|zx_keyboard_|keys[0][0]~13_combout ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [4]),
|
|
.datac(\ula_|zx_keyboard_|extended~q ),
|
|
.datad(\ula_|zx_keyboard_|keys[0][0]~13_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[5][1]~34_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[5][1]~34 .lut_mask = 16'h0300;
|
|
defparam \ula_|zx_keyboard_|keys[5][1]~34 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y10_N2
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~35 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[5][1]~35_combout = (\ula_|zx_keyboard_|keys[5][1]~34_combout & (\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [2]))
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[5][1]~34_combout ),
|
|
.datab(gnd),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [6]),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [2]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[5][1]~35_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[5][1]~35 .lut_mask = 16'hA000;
|
|
defparam \ula_|zx_keyboard_|keys[5][1]~35 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y10_N0
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~33 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[5][1]~33_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [3] & \ula_|zx_keyboard_|shifted~q ))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [3]),
|
|
.datab(\ula_|zx_keyboard_|shifted~q ),
|
|
.datac(gnd),
|
|
.datad(\ula_|zx_keyboard_|released~q ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[5][1]~33_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[5][1]~33 .lut_mask = 16'hFF88;
|
|
defparam \ula_|zx_keyboard_|keys[5][1]~33 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y10_N22
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][1]~37 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[5][1]~37_combout = (\ula_|zx_keyboard_|keys[5][1]~36_combout & ((\ula_|zx_keyboard_|keys[5][1]~35_combout & ((!\ula_|zx_keyboard_|keys[5][1]~33_combout ))) # (!\ula_|zx_keyboard_|keys[5][1]~35_combout &
|
|
// (\ula_|zx_keyboard_|keys[5][1]~q )))) # (!\ula_|zx_keyboard_|keys[5][1]~36_combout & (((\ula_|zx_keyboard_|keys[5][1]~q ))))
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[5][1]~36_combout ),
|
|
.datab(\ula_|zx_keyboard_|keys[5][1]~35_combout ),
|
|
.datac(\ula_|zx_keyboard_|keys[5][1]~q ),
|
|
.datad(\ula_|zx_keyboard_|keys[5][1]~33_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[5][1]~37_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[5][1]~37 .lut_mask = 16'h70F8;
|
|
defparam \ula_|zx_keyboard_|keys[5][1]~37 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X29_Y10_N23
|
|
dffeas \ula_|zx_keyboard_|keys[5][1] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|zx_keyboard_|keys[5][1]~37_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|zx_keyboard_|keys[5][1]~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[5][1] .is_wysiwyg = "true";
|
|
defparam \ula_|zx_keyboard_|keys[5][1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y8_N4
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~29 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[4][1]~29_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2])
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [0]),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [2]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[4][1]~29_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[4][1]~29 .lut_mask = 16'h0F00;
|
|
defparam \ula_|zx_keyboard_|keys[4][1]~29 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y9_N10
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~30 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[7][2]~30_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [5]))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [6]),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [4]),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [5]),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[7][2]~30_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[7][2]~30 .lut_mask = 16'h0202;
|
|
defparam \ula_|zx_keyboard_|keys[7][2]~30 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y9_N0
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~31 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[5][2]~31_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[7][1]~21_combout & (\ula_|zx_keyboard_|keys[7][2]~30_combout & \ula_|ps2_keyboard_|shiftreg [1])))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [3]),
|
|
.datab(\ula_|zx_keyboard_|keys[7][1]~21_combout ),
|
|
.datac(\ula_|zx_keyboard_|keys[7][2]~30_combout ),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [1]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[5][2]~31_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[5][2]~31 .lut_mask = 16'h4000;
|
|
defparam \ula_|zx_keyboard_|keys[5][2]~31 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y10_N24
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][1]~32 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[4][1]~32_combout = (\ula_|zx_keyboard_|keys[4][1]~29_combout & ((\ula_|zx_keyboard_|keys[5][2]~31_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[5][2]~31_combout & ((\ula_|zx_keyboard_|keys[4][1]~q
|
|
// ))))) # (!\ula_|zx_keyboard_|keys[4][1]~29_combout & (((\ula_|zx_keyboard_|keys[4][1]~q ))))
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[4][1]~29_combout ),
|
|
.datab(\ula_|zx_keyboard_|released~q ),
|
|
.datac(\ula_|zx_keyboard_|keys[4][1]~q ),
|
|
.datad(\ula_|zx_keyboard_|keys[5][2]~31_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[4][1]~32_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[4][1]~32 .lut_mask = 16'h72F0;
|
|
defparam \ula_|zx_keyboard_|keys[4][1]~32 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X29_Y10_N25
|
|
dffeas \ula_|zx_keyboard_|keys[4][1] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|zx_keyboard_|keys[4][1]~32_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|zx_keyboard_|keys[4][1]~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[4][1] .is_wysiwyg = "true";
|
|
defparam \ula_|zx_keyboard_|keys[4][1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y10_N28
|
|
cycloneive_lcell_comb \D[1]~28 (
|
|
// Equation(s):
|
|
// \D[1]~28_combout = (\z80_|address_pins_|abus[12]~21_combout & ((\z80_|address_pins_|abus[13]~20_combout ) # ((!\ula_|zx_keyboard_|keys[5][1]~q )))) # (!\z80_|address_pins_|abus[12]~21_combout & (!\ula_|zx_keyboard_|keys[4][1]~q &
|
|
// ((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][1]~q ))))
|
|
|
|
.dataa(\z80_|address_pins_|abus[12]~21_combout ),
|
|
.datab(\z80_|address_pins_|abus[13]~20_combout ),
|
|
.datac(\ula_|zx_keyboard_|keys[5][1]~q ),
|
|
.datad(\ula_|zx_keyboard_|keys[4][1]~q ),
|
|
.cin(gnd),
|
|
.combout(\D[1]~28_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[1]~28 .lut_mask = 16'h8ACF;
|
|
defparam \D[1]~28 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y11_N6
|
|
cycloneive_lcell_comb \z80_|address_pins_|abus[0]~16 (
|
|
// Equation(s):
|
|
// \z80_|address_pins_|abus[0]~16_combout = (\z80_|address_pins_|DFFE_apin_latch [0]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|address_pins_|DFFE_apin_latch [0]),
|
|
.datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_pins_|abus[0]~16_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|abus[0]~16 .lut_mask = 16'hCFCF;
|
|
defparam \z80_|address_pins_|abus[0]~16 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y13_N18
|
|
cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[14]~14 (
|
|
// Equation(s):
|
|
// \z80_|address_pins_|DFFE_apin_latch[14]~14_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [14])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [14])))
|
|
|
|
.dataa(\z80_|execute_|ctl_apin_mux~2_combout ),
|
|
.datab(\z80_|address_latch_|b2v_inst_inc_dec|address [14]),
|
|
.datac(gnd),
|
|
.datad(\z80_|address_latch_|abusz [14]),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .lut_mask = 16'hDD88;
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[14]~14 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y13_N19
|
|
dffeas \z80_|address_pins_|DFFE_apin_latch[14] (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|address_pins_|DFFE_apin_latch[14]~14_combout ),
|
|
.asdata(\z80_|address_latch_|Q [14]),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(\z80_|execute_|ctl_apin_mux2~0_combout ),
|
|
.ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|address_pins_|DFFE_apin_latch [14]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[14] .is_wysiwyg = "true";
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[14] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y10_N20
|
|
cycloneive_lcell_comb \z80_|address_pins_|abus[14]~23 (
|
|
// Equation(s):
|
|
// \z80_|address_pins_|abus[14]~23_combout = (\z80_|address_pins_|DFFE_apin_latch [14]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.datad(\z80_|address_pins_|DFFE_apin_latch [14]),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_pins_|abus[14]~23_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|abus[14]~23 .lut_mask = 16'hFF0F;
|
|
defparam \z80_|address_pins_|abus[14]~23 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y9_N26
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~40 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[6][1]~40_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [1])) # (!\ula_|ps2_keyboard_|shiftreg [2] & (!\ula_|ps2_keyboard_|shiftreg [4] &
|
|
// \ula_|ps2_keyboard_|shiftreg [1]))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [2]),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [4]),
|
|
.datac(gnd),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [1]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[6][1]~40_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[6][1]~40 .lut_mask = 16'h1188;
|
|
defparam \ula_|zx_keyboard_|keys[6][1]~40 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y9_N12
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~41 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[6][1]~41_combout = (\ula_|zx_keyboard_|keys[6][1]~40_combout & (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [2] $ (\ula_|ps2_keyboard_|shiftreg [3]))))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [2]),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [3]),
|
|
.datac(\ula_|zx_keyboard_|keys[6][1]~40_combout ),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [0]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[6][1]~41_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[6][1]~41 .lut_mask = 16'h6000;
|
|
defparam \ula_|zx_keyboard_|keys[6][1]~41 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y8_N8
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~39 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[6][1]~39_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[0][0]~13_combout & !\ula_|zx_keyboard_|extended~q )))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [6]),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [5]),
|
|
.datac(\ula_|zx_keyboard_|keys[0][0]~13_combout ),
|
|
.datad(\ula_|zx_keyboard_|extended~q ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[6][1]~39_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[6][1]~39 .lut_mask = 16'h0020;
|
|
defparam \ula_|zx_keyboard_|keys[6][1]~39 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y9_N24
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~38 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[6][1]~38_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [2]))
|
|
|
|
.dataa(\ula_|zx_keyboard_|shifted~q ),
|
|
.datab(gnd),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [2]),
|
|
.datad(\ula_|zx_keyboard_|released~q ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[6][1]~38_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[6][1]~38 .lut_mask = 16'hFFA0;
|
|
defparam \ula_|zx_keyboard_|keys[6][1]~38 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y9_N22
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][1]~42 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[6][1]~42_combout = (\ula_|zx_keyboard_|keys[6][1]~41_combout & ((\ula_|zx_keyboard_|keys[6][1]~39_combout & ((!\ula_|zx_keyboard_|keys[6][1]~38_combout ))) # (!\ula_|zx_keyboard_|keys[6][1]~39_combout &
|
|
// (\ula_|zx_keyboard_|keys[6][1]~q )))) # (!\ula_|zx_keyboard_|keys[6][1]~41_combout & (((\ula_|zx_keyboard_|keys[6][1]~q ))))
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[6][1]~41_combout ),
|
|
.datab(\ula_|zx_keyboard_|keys[6][1]~39_combout ),
|
|
.datac(\ula_|zx_keyboard_|keys[6][1]~q ),
|
|
.datad(\ula_|zx_keyboard_|keys[6][1]~38_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[6][1]~42_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[6][1]~42 .lut_mask = 16'h70F8;
|
|
defparam \ula_|zx_keyboard_|keys[6][1]~42 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X28_Y9_N23
|
|
dffeas \ula_|zx_keyboard_|keys[6][1] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|zx_keyboard_|keys[6][1]~42_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|zx_keyboard_|keys[6][1]~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[6][1] .is_wysiwyg = "true";
|
|
defparam \ula_|zx_keyboard_|keys[6][1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y10_N14
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~4 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|WideOr16~4_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2])) # (!\ula_|ps2_keyboard_|shiftreg [1] &
|
|
// (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2]))))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [1]),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [0]),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [3]),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [2]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|WideOr16~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|WideOr16~4 .lut_mask = 16'h0402;
|
|
defparam \ula_|zx_keyboard_|WideOr16~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y10_N24
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~2 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|WideOr16~2_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [1]))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [0]),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [3]),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [1]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|WideOr16~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|WideOr16~2 .lut_mask = 16'h000C;
|
|
defparam \ula_|zx_keyboard_|WideOr16~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y10_N28
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~7 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|WideOr16~7_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~4_combout )) # (!\ula_|ps2_keyboard_|shiftreg [6] & (((\ula_|zx_keyboard_|WideOr16~2_combout & !\ula_|ps2_keyboard_|shiftreg [2]))))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [6]),
|
|
.datab(\ula_|zx_keyboard_|WideOr16~4_combout ),
|
|
.datac(\ula_|zx_keyboard_|WideOr16~2_combout ),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [2]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|WideOr16~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|WideOr16~7 .lut_mask = 16'h88D8;
|
|
defparam \ula_|zx_keyboard_|WideOr16~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y10_N8
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~5 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|WideOr16~5_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [1] & ((!\ula_|ps2_keyboard_|shiftreg [2])))) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] &
|
|
// ((\ula_|ps2_keyboard_|shiftreg [1]) # (\ula_|ps2_keyboard_|shiftreg [2]))))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [1]),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [0]),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [3]),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [2]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|WideOr16~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|WideOr16~5 .lut_mask = 16'h3064;
|
|
defparam \ula_|zx_keyboard_|WideOr16~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y10_N10
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~6 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|WideOr16~6_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|WideOr16~7_combout )) # (!\ula_|ps2_keyboard_|shiftreg [4] & (((\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|WideOr16~5_combout ))))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [4]),
|
|
.datab(\ula_|zx_keyboard_|WideOr16~7_combout ),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [6]),
|
|
.datad(\ula_|zx_keyboard_|WideOr16~5_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|WideOr16~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|WideOr16~6 .lut_mask = 16'hD888;
|
|
defparam \ula_|zx_keyboard_|WideOr16~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y8_N18
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~43 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[7][1]~43_combout = (!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [7] & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|scan_code_ready~q )))
|
|
|
|
.dataa(\ula_|zx_keyboard_|extended~q ),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [7]),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [5]),
|
|
.datad(\ula_|ps2_keyboard_|scan_code_ready~q ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[7][1]~43_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[7][1]~43 .lut_mask = 16'h0100;
|
|
defparam \ula_|zx_keyboard_|keys[7][1]~43 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y10_N24
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][1]~44 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[7][1]~44_combout = (\ula_|zx_keyboard_|WideOr16~6_combout & ((\ula_|zx_keyboard_|keys[7][1]~43_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[7][1]~43_combout & (\ula_|zx_keyboard_|keys[7][1]~q ))))
|
|
// # (!\ula_|zx_keyboard_|WideOr16~6_combout & (((\ula_|zx_keyboard_|keys[7][1]~q ))))
|
|
|
|
.dataa(\ula_|zx_keyboard_|WideOr16~6_combout ),
|
|
.datab(\ula_|zx_keyboard_|keys[7][1]~43_combout ),
|
|
.datac(\ula_|zx_keyboard_|keys[7][1]~q ),
|
|
.datad(\ula_|zx_keyboard_|released~q ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[7][1]~44_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[7][1]~44 .lut_mask = 16'h70F8;
|
|
defparam \ula_|zx_keyboard_|keys[7][1]~44 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X27_Y10_N25
|
|
dffeas \ula_|zx_keyboard_|keys[7][1] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|zx_keyboard_|keys[7][1]~44_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|zx_keyboard_|keys[7][1]~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[7][1] .is_wysiwyg = "true";
|
|
defparam \ula_|zx_keyboard_|keys[7][1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y13_N10
|
|
cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[15]~15 (
|
|
// Equation(s):
|
|
// \z80_|address_pins_|DFFE_apin_latch[15]~15_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|address[15]~1_combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [15]))
|
|
|
|
.dataa(\z80_|execute_|ctl_apin_mux~2_combout ),
|
|
.datab(\z80_|address_latch_|abusz [15]),
|
|
.datac(gnd),
|
|
.datad(\z80_|address_latch_|b2v_inst_inc_dec|address[15]~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .lut_mask = 16'hEE44;
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[15]~15 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y13_N11
|
|
dffeas \z80_|address_pins_|DFFE_apin_latch[15] (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|address_pins_|DFFE_apin_latch[15]~15_combout ),
|
|
.asdata(\z80_|address_latch_|Q [15]),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(\z80_|execute_|ctl_apin_mux2~0_combout ),
|
|
.ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|address_pins_|DFFE_apin_latch [15]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[15] .is_wysiwyg = "true";
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[15] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y11_N8
|
|
cycloneive_lcell_comb \z80_|address_pins_|abus[15]~22 (
|
|
// Equation(s):
|
|
// \z80_|address_pins_|abus[15]~22_combout = (\z80_|address_pins_|DFFE_apin_latch [15]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.datad(\z80_|address_pins_|DFFE_apin_latch [15]),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_pins_|abus[15]~22_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|abus[15]~22 .lut_mask = 16'hFF0F;
|
|
defparam \z80_|address_pins_|abus[15]~22 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y10_N16
|
|
cycloneive_lcell_comb \D[1]~29 (
|
|
// Equation(s):
|
|
// \D[1]~29_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][1]~q )))) # (!\z80_|address_pins_|abus[14]~23_combout & (!\ula_|zx_keyboard_|keys[6][1]~q &
|
|
// ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][1]~q ))))
|
|
|
|
.dataa(\z80_|address_pins_|abus[14]~23_combout ),
|
|
.datab(\ula_|zx_keyboard_|keys[6][1]~q ),
|
|
.datac(\ula_|zx_keyboard_|keys[7][1]~q ),
|
|
.datad(\z80_|address_pins_|abus[15]~22_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[1]~29_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[1]~29 .lut_mask = 16'hBB0B;
|
|
defparam \D[1]~29 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y10_N26
|
|
cycloneive_lcell_comb \D[1]~30 (
|
|
// Equation(s):
|
|
// \D[1]~30_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[1]~27_combout & (\D[1]~28_combout & \D[1]~29_combout )))
|
|
|
|
.dataa(\D[1]~27_combout ),
|
|
.datab(\D[1]~28_combout ),
|
|
.datac(\z80_|address_pins_|abus[0]~16_combout ),
|
|
.datad(\D[1]~29_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[1]~30_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[1]~30 .lut_mask = 16'hF8F0;
|
|
defparam \D[1]~30 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y11_N20
|
|
cycloneive_lcell_comb \ExtRamWE~0 (
|
|
// Equation(s):
|
|
// \ExtRamWE~0_combout = (!\z80_|memory_ifc_|nIORQ_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (!\z80_|memory_ifc_|nRD_out~2_combout & \z80_|memory_ifc_|nWR_out~0_combout )))
|
|
|
|
.dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ),
|
|
.datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.datac(\z80_|memory_ifc_|nRD_out~2_combout ),
|
|
.datad(\z80_|memory_ifc_|nWR_out~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\ExtRamWE~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ExtRamWE~0 .lut_mask = 16'h0400;
|
|
defparam \ExtRamWE~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y11_N0
|
|
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] (
|
|
// Equation(s):
|
|
// \ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2] = (!\z80_|address_pins_|abus[14]~23_combout & (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[15]~22_combout & \z80_|address_pins_|abus[13]~20_combout )))
|
|
|
|
.dataa(\z80_|address_pins_|abus[14]~23_combout ),
|
|
.datab(\ExtRamWE~0_combout ),
|
|
.datac(\z80_|address_pins_|abus[15]~22_combout ),
|
|
.datad(\z80_|address_pins_|abus[13]~20_combout ),
|
|
.cin(gnd),
|
|
.combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .lut_mask = 16'h4000;
|
|
defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode236w[2] .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y10_N10
|
|
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 (
|
|
// Equation(s):
|
|
// \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout = (!\z80_|address_pins_|DFFE_apin_latch [14] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|address_pins_|DFFE_apin_latch [13]))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|address_pins_|DFFE_apin_latch [14]),
|
|
.datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.datad(\z80_|address_pins_|DFFE_apin_latch [13]),
|
|
.cin(gnd),
|
|
.combout(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .lut_mask = 16'h3000;
|
|
defparam \ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y11_N6
|
|
cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[1]~1 (
|
|
// Equation(s):
|
|
// \z80_|address_pins_|DFFE_apin_latch[1]~1_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [1]))
|
|
|
|
.dataa(\z80_|execute_|ctl_apin_mux~2_combout ),
|
|
.datab(\z80_|address_latch_|abusz [1]),
|
|
.datac(gnd),
|
|
.datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d1_out~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .lut_mask = 16'hEE44;
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[1]~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y11_N7
|
|
dffeas \z80_|address_pins_|DFFE_apin_latch[1] (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|address_pins_|DFFE_apin_latch[1]~1_combout ),
|
|
.asdata(\z80_|address_latch_|Q [1]),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(\z80_|execute_|ctl_apin_mux2~0_combout ),
|
|
.ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|address_pins_|DFFE_apin_latch [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[1] .is_wysiwyg = "true";
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y11_N10
|
|
cycloneive_lcell_comb \z80_|address_pins_|abus[1]~25 (
|
|
// Equation(s):
|
|
// \z80_|address_pins_|abus[1]~25_combout = (\z80_|address_pins_|DFFE_apin_latch [1]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|address_pins_|DFFE_apin_latch [1]),
|
|
.datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_pins_|abus[1]~25_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|abus[1]~25 .lut_mask = 16'hCFCF;
|
|
defparam \z80_|address_pins_|abus[1]~25 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y11_N12
|
|
cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[2]~2 (
|
|
// Equation(s):
|
|
// \z80_|address_pins_|DFFE_apin_latch[2]~2_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [2])))
|
|
|
|
.dataa(\z80_|execute_|ctl_apin_mux~2_combout ),
|
|
.datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d0_out~combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|address_latch_|abusz [2]),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .lut_mask = 16'hDD88;
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[2]~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y11_N13
|
|
dffeas \z80_|address_pins_|DFFE_apin_latch[2] (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|address_pins_|DFFE_apin_latch[2]~2_combout ),
|
|
.asdata(\z80_|address_latch_|Q [2]),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(\z80_|execute_|ctl_apin_mux2~0_combout ),
|
|
.ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|address_pins_|DFFE_apin_latch [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[2] .is_wysiwyg = "true";
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y11_N16
|
|
cycloneive_lcell_comb \z80_|address_pins_|abus[2]~26 (
|
|
// Equation(s):
|
|
// \z80_|address_pins_|abus[2]~26_combout = (\z80_|address_pins_|DFFE_apin_latch [2]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.datad(\z80_|address_pins_|DFFE_apin_latch [2]),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_pins_|abus[2]~26_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|abus[2]~26 .lut_mask = 16'hFF0F;
|
|
defparam \z80_|address_pins_|abus[2]~26 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y11_N28
|
|
cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[3]~3 (
|
|
// Equation(s):
|
|
// \z80_|address_pins_|DFFE_apin_latch[3]~3_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [3]))
|
|
|
|
.dataa(\z80_|address_latch_|abusz [3]),
|
|
.datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_2|d1_out~combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|execute_|ctl_apin_mux~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .lut_mask = 16'hCCAA;
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[3]~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y11_N29
|
|
dffeas \z80_|address_pins_|DFFE_apin_latch[3] (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|address_pins_|DFFE_apin_latch[3]~3_combout ),
|
|
.asdata(\z80_|address_latch_|Q [3]),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(\z80_|execute_|ctl_apin_mux2~0_combout ),
|
|
.ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|address_pins_|DFFE_apin_latch [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[3] .is_wysiwyg = "true";
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y11_N0
|
|
cycloneive_lcell_comb \z80_|address_pins_|abus[3]~27 (
|
|
// Equation(s):
|
|
// \z80_|address_pins_|abus[3]~27_combout = (\z80_|address_pins_|DFFE_apin_latch [3]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )
|
|
|
|
.dataa(\z80_|address_pins_|DFFE_apin_latch [3]),
|
|
.datab(gnd),
|
|
.datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_pins_|abus[3]~27_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|abus[3]~27 .lut_mask = 16'hAFAF;
|
|
defparam \z80_|address_pins_|abus[3]~27 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y10_N16
|
|
cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[4]~4 (
|
|
// Equation(s):
|
|
// \z80_|address_pins_|DFFE_apin_latch[4]~4_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [4])))
|
|
|
|
.dataa(\z80_|execute_|ctl_apin_mux~2_combout ),
|
|
.datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d0_out~combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|address_latch_|abusz [4]),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .lut_mask = 16'hDD88;
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[4]~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y10_N17
|
|
dffeas \z80_|address_pins_|DFFE_apin_latch[4] (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|address_pins_|DFFE_apin_latch[4]~4_combout ),
|
|
.asdata(\z80_|address_latch_|Q [4]),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(\z80_|execute_|ctl_apin_mux2~0_combout ),
|
|
.ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|address_pins_|DFFE_apin_latch [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[4] .is_wysiwyg = "true";
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y10_N6
|
|
cycloneive_lcell_comb \z80_|address_pins_|abus[4]~28 (
|
|
// Equation(s):
|
|
// \z80_|address_pins_|abus[4]~28_combout = (\z80_|address_pins_|DFFE_apin_latch [4]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.datad(\z80_|address_pins_|DFFE_apin_latch [4]),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_pins_|abus[4]~28_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|abus[4]~28 .lut_mask = 16'hFF0F;
|
|
defparam \z80_|address_pins_|abus[4]~28 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y10_N18
|
|
cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[5]~5 (
|
|
// Equation(s):
|
|
// \z80_|address_pins_|DFFE_apin_latch[5]~5_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout )) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [5])))
|
|
|
|
.dataa(\z80_|execute_|ctl_apin_mux~2_combout ),
|
|
.datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_4|d1_out~combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|address_latch_|abusz [5]),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .lut_mask = 16'hDD88;
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[5]~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y10_N19
|
|
dffeas \z80_|address_pins_|DFFE_apin_latch[5] (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|address_pins_|DFFE_apin_latch[5]~5_combout ),
|
|
.asdata(\z80_|address_latch_|Q [5]),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(\z80_|execute_|ctl_apin_mux2~0_combout ),
|
|
.ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|address_pins_|DFFE_apin_latch [5]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[5] .is_wysiwyg = "true";
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[5] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y10_N30
|
|
cycloneive_lcell_comb \z80_|address_pins_|abus[5]~29 (
|
|
// Equation(s):
|
|
// \z80_|address_pins_|abus[5]~29_combout = (\z80_|address_pins_|DFFE_apin_latch [5]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.datad(\z80_|address_pins_|DFFE_apin_latch [5]),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_pins_|abus[5]~29_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|abus[5]~29 .lut_mask = 16'hFF0F;
|
|
defparam \z80_|address_pins_|abus[5]~29 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y10_N14
|
|
cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[6]~6 (
|
|
// Equation(s):
|
|
// \z80_|address_pins_|DFFE_apin_latch[6]~6_combout = (\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|b2v_inst_inc_dec|address [6])) # (!\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|abusz [6])))
|
|
|
|
.dataa(\z80_|execute_|ctl_apin_mux~2_combout ),
|
|
.datab(\z80_|address_latch_|b2v_inst_inc_dec|address [6]),
|
|
.datac(gnd),
|
|
.datad(\z80_|address_latch_|abusz [6]),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .lut_mask = 16'hDD88;
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[6]~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y10_N15
|
|
dffeas \z80_|address_pins_|DFFE_apin_latch[6] (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|address_pins_|DFFE_apin_latch[6]~6_combout ),
|
|
.asdata(\z80_|address_latch_|Q [6]),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(\z80_|execute_|ctl_apin_mux2~0_combout ),
|
|
.ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|address_pins_|DFFE_apin_latch [6]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[6] .is_wysiwyg = "true";
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[6] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y10_N26
|
|
cycloneive_lcell_comb \z80_|address_pins_|abus[6]~30 (
|
|
// Equation(s):
|
|
// \z80_|address_pins_|abus[6]~30_combout = (\z80_|address_pins_|DFFE_apin_latch [6]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|address_pins_|DFFE_apin_latch [6]),
|
|
.datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_pins_|abus[6]~30_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|abus[6]~30 .lut_mask = 16'hCFCF;
|
|
defparam \z80_|address_pins_|abus[6]~30 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y13_N20
|
|
cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[7]~7 (
|
|
// Equation(s):
|
|
// \z80_|address_pins_|DFFE_apin_latch[7]~7_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [7]))
|
|
|
|
.dataa(\z80_|execute_|ctl_apin_mux~2_combout ),
|
|
.datab(\z80_|address_latch_|abusz [7]),
|
|
.datac(gnd),
|
|
.datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_7|d0_out~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .lut_mask = 16'hEE44;
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[7]~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y13_N21
|
|
dffeas \z80_|address_pins_|DFFE_apin_latch[7] (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|address_pins_|DFFE_apin_latch[7]~7_combout ),
|
|
.asdata(\z80_|address_latch_|Q [7]),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(\z80_|execute_|ctl_apin_mux2~0_combout ),
|
|
.ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|address_pins_|DFFE_apin_latch [7]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[7] .is_wysiwyg = "true";
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[7] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y11_N24
|
|
cycloneive_lcell_comb \z80_|address_pins_|abus[7]~31 (
|
|
// Equation(s):
|
|
// \z80_|address_pins_|abus[7]~31_combout = (\z80_|address_pins_|DFFE_apin_latch [7]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )
|
|
|
|
.dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|address_pins_|DFFE_apin_latch [7]),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_pins_|abus[7]~31_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|abus[7]~31 .lut_mask = 16'hFF55;
|
|
defparam \z80_|address_pins_|abus[7]~31 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y7_N0
|
|
cycloneive_lcell_comb \z80_|address_pins_|abus[10]~24 (
|
|
// Equation(s):
|
|
// \z80_|address_pins_|abus[10]~24_combout = (\z80_|address_pins_|DFFE_apin_latch [10]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )
|
|
|
|
.dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|address_pins_|DFFE_apin_latch [10]),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_pins_|abus[10]~24_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|abus[10]~24 .lut_mask = 16'hFF55;
|
|
defparam \z80_|address_pins_|abus[10]~24 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X33_Y12_N0
|
|
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a9 (
|
|
.portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[1]~32_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file = "led_patterns.mif";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "single_port";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 32768;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y11_N4
|
|
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] (
|
|
// Equation(s):
|
|
// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2] = (!\z80_|address_pins_|abus[14]~23_combout & (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[15]~22_combout & !\z80_|address_pins_|abus[13]~20_combout )))
|
|
|
|
.dataa(\z80_|address_pins_|abus[14]~23_combout ),
|
|
.datab(\ExtRamWE~0_combout ),
|
|
.datac(\z80_|address_pins_|abus[15]~22_combout ),
|
|
.datad(\z80_|address_pins_|abus[13]~20_combout ),
|
|
.cin(gnd),
|
|
.combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .lut_mask = 16'h0040;
|
|
defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2] .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y10_N0
|
|
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 (
|
|
// Equation(s):
|
|
// \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout = (!\z80_|address_pins_|DFFE_apin_latch [14] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|address_pins_|DFFE_apin_latch [13]))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|address_pins_|DFFE_apin_latch [14]),
|
|
.datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.datad(\z80_|address_pins_|DFFE_apin_latch [13]),
|
|
.cin(gnd),
|
|
.combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .lut_mask = 16'h0030;
|
|
defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X33_Y10_N0
|
|
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a1 (
|
|
.portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[1]~32_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file = "led_patterns.mif";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "single_port";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 32768;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042;
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y10_N22
|
|
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder (
|
|
// Equation(s):
|
|
// \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = \z80_|address_pins_|abus[13]~20_combout
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|address_pins_|abus[13]~20_combout ),
|
|
.cin(gnd),
|
|
.combout(\ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hFF00;
|
|
defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X23_Y10_N23
|
|
dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[0] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ram1|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ram1|altsyncram_component|auto_generated|address_reg_a [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true";
|
|
defparam \ram1|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X23_Y10_N7
|
|
dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [0]),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true";
|
|
defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y11_N24
|
|
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] (
|
|
// Equation(s):
|
|
// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2] = (\z80_|address_pins_|abus[14]~23_combout & (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[15]~22_combout & !\z80_|address_pins_|abus[13]~20_combout )))
|
|
|
|
.dataa(\z80_|address_pins_|abus[14]~23_combout ),
|
|
.datab(\ExtRamWE~0_combout ),
|
|
.datac(\z80_|address_pins_|abus[15]~22_combout ),
|
|
.datad(\z80_|address_pins_|abus[13]~20_combout ),
|
|
.cin(gnd),
|
|
.combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .lut_mask = 16'h0080;
|
|
defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2] .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y10_N12
|
|
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 (
|
|
// Equation(s):
|
|
// \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout = (!\z80_|address_pins_|DFFE_apin_latch [13] & (\z80_|address_pins_|DFFE_apin_latch [14] & \z80_|resets_|SYNTHESIZED_WIRE_12~q ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|address_pins_|DFFE_apin_latch [13]),
|
|
.datac(\z80_|address_pins_|DFFE_apin_latch [14]),
|
|
.datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.cin(gnd),
|
|
.combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .lut_mask = 16'h3000;
|
|
defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X33_Y8_N0
|
|
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a17 (
|
|
.portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[1]~32_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .clk0_core_clock_enable = "ena0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .data_interleave_width_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file = "led_patterns.mif";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .init_file_layout = "port_a";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .operation_mode = "single_port";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_byte_enable_clock = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_out_clock = "clock0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_address = 0;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_first_bit_number = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_last_address = 8191;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_depth = 32768;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_logical_ram_width = 8;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .port_b_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .ram_block_type = "M9K";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a17 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X23_Y14_N5
|
|
dffeas \ram1|altsyncram_component|auto_generated|address_reg_a[1] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|address_pins_|abus[14]~23_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ram1|altsyncram_component|auto_generated|address_reg_a [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .is_wysiwyg = "true";
|
|
defparam \ram1|altsyncram_component|auto_generated|address_reg_a[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X23_Y14_N27
|
|
dffeas \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\ram1|altsyncram_component|auto_generated|address_reg_a [1]),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .is_wysiwyg = "true";
|
|
defparam \ram1|altsyncram_component|auto_generated|out_address_reg_a[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y10_N8
|
|
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 (
|
|
// Equation(s):
|
|
// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) #
|
|
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ))) #
|
|
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ))))
|
|
|
|
.dataa(\ram1|altsyncram_component|auto_generated|ram_block1a1~portadataout ),
|
|
.datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
|
|
.datac(\ram1|altsyncram_component|auto_generated|ram_block1a17~portadataout ),
|
|
.datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]),
|
|
.cin(gnd),
|
|
.combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 .lut_mask = 16'hFC22;
|
|
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y11_N18
|
|
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] (
|
|
// Equation(s):
|
|
// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2] = (\z80_|address_pins_|abus[14]~23_combout & (\ExtRamWE~0_combout & (\z80_|address_pins_|abus[15]~22_combout & \z80_|address_pins_|abus[13]~20_combout )))
|
|
|
|
.dataa(\z80_|address_pins_|abus[14]~23_combout ),
|
|
.datab(\ExtRamWE~0_combout ),
|
|
.datac(\z80_|address_pins_|abus[15]~22_combout ),
|
|
.datad(\z80_|address_pins_|abus[13]~20_combout ),
|
|
.cin(gnd),
|
|
.combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .lut_mask = 16'h8000;
|
|
defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2] .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y10_N30
|
|
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 (
|
|
// Equation(s):
|
|
// \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout = ((\z80_|address_pins_|DFFE_apin_latch [13] & \z80_|address_pins_|DFFE_apin_latch [14])) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|address_pins_|DFFE_apin_latch [13]),
|
|
.datac(\z80_|address_pins_|DFFE_apin_latch [14]),
|
|
.datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.cin(gnd),
|
|
.combout(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .lut_mask = 16'hC0FF;
|
|
defparam \ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X33_Y7_N0
|
|
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a25 (
|
|
.portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[1]~32_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a25_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .clk0_core_clock_enable = "ena0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .data_interleave_width_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file = "led_patterns.mif";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .init_file_layout = "port_a";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .operation_mode = "single_port";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_byte_enable_clock = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_out_clock = "clock0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_address = 0;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_first_bit_number = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_last_address = 8191;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_depth = 32768;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_logical_ram_width = 8;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .port_b_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .ram_block_type = "M9K";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a25 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y10_N6
|
|
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 (
|
|
// Equation(s):
|
|
// \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ) #
|
|
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout &
|
|
// (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))
|
|
|
|
.dataa(\ram1|altsyncram_component|auto_generated|ram_block1a9~portadataout ),
|
|
.datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~0_combout ),
|
|
.datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
|
|
.datad(\ram1|altsyncram_component|auto_generated|ram_block1a25~portadataout ),
|
|
.cin(gnd),
|
|
.combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 .lut_mask = 16'hEC2C;
|
|
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X33_Y2_N0
|
|
cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a1 (
|
|
.portawe(vcc),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(!\z80_|address_pins_|abus[13]~20_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain(1'b0),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\rom|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file = "./rom/gw03.hex";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "rom";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock0";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_a_write_enable_clock = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h35C65240B61076066A23CE4CFC5E76063A1C2AE07DF555007338BDC080EA0C23082C891C76A4845096304A0D8502080C1198911998821D09C29CA830C337499236E0548D65FF9125A765F0220F6EB9D1B318244CC6CA2CBC9CEC6979C14EB28DE2E0440C6CBD61341FC178649A852D4A2A0627C688D905B882524E191E7951EAEF30312A73337CBAD4838F42A3293859CD169240D8E652F6D72D8D19D56DD7675939FC47C933E1B0AEF12A484454C247B00A6BEC5402AA08B5106E3065602454C80CEC08A7F5F85CE65326632B4C4F3920019A35AE2AEB321131046EE45B81D4EFD5995634050D4CFEC166B032B6415553AF0358304080D9DD0A2E5948593830;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h376E511217E00B624A46BA2E4CC10B729C326F710F24CFE78C5E63F3024B17CC5E1380C938A0A16C9B696272DE7A2948BE8AFE81310146B8AAE5E549FA27EFBE27929938B8E10530250877A4998D0DF0004852125C20CA8D4279881E41208B14198817644F293AC1946061117122A39D8841818C1389D51BDAC549181902516571163594CEC5863F0F56625E221D6B8180848C6B2BE24AA0AEEE5D187201CAAE6AA394A8644314895565192AE415630A42894D6EF21343903B348EED8642F2310644C9567C0BF9911B870B989C59330089AA4C8065AB1B11132213EE0FD830817DE6C2ED45D76325CA2A8E198859334553AB02945CAB1F17C142288008073004;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h20721F982534A8179F13E2C6328CDE7D2A73087D3A9314419022103DFF7677769FE2D1F27443253D58403577C801AE23371F00290A17E1C4A40258BFD204230EE9969472A81B83113144528F831AA6C3221E137C1E9C670E26809A894013828D9E2DBCBF62498A769893D7218899245CD18AE49F0146517422EE475D520029ED39BCEF6BF4D23532957455F1C80115524179D59C4C4534DF7296991146CE24508366123AA809AB30B47977571C5D70397A93C723106D0A2C254714359DC7C9E13AE624C94932927924D20024CD638A05C8620023319662D80E05805625BC4A4006C78011F78D8B82E59F0CD4B32D6801669BE3EB0B96960DFF152005EC7C16CB;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'h9C8CA06AA05B63C89A59A3E4E80807B27A70B0006624C4AC4A0595CCD8CA20824CA272352720BCD900A6D79BFD9D0595EC0D044ABC8CC28E9AE946E3D2000A4EFA4F91915C6AC9D8570C292F10848189906127BCBE06FFE92DAFB4AAFB240D88DDBB7B207EFA1709B05E1C4801BD45625A36BB62220506E171891964A31BED2215408676F600F490FAA59B488C7998CC8CCC28922AC62644EEBB432EEECB51B16CDEE7468681D6C31E4991CA3736E9ACB7531EC6D8BBCD453718101EA25D79278C6AC955A8A6140421573E413CF5A80AA1436D8B4C31A2AB26D2A61CE834248BAD5751BD429B4F61318427560CE39D49299002165212181064E24FF0093B997B;
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X22_Y2_N0
|
|
cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a9 (
|
|
.portawe(vcc),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(\z80_|address_pins_|abus[13]~20_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain(1'b0),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\rom|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file = "./rom/gw03.hex";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "rom";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock0";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_a_write_enable_clock = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h420000004200000000000000000080000000000000000000000000000030004480000000424202423E1E3E02304C3C0C3C7E7E40403E427E3402421824347C1C0400280000003C3406303220344C403C0400100010100000005062742400000091991809FB3BD9084A1241F5015988B3C506031934089E0E1FA8043DDAF2CC07D94A6F2B1D133C211222B22C787D430E45D4C53282288077DFC0F704AAD55127A2BEAEA114958D2817AB1213183A4E1A15E3690A08A33B429284A202011A1243D49CACA1C0A441405A720D21A0921294045F746229E287B95E956AA3DE0CA3B7A019C8039C4DDA6BC99371248CC6008A54CB84503442C4F91309238ECB252072;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h81F3167814687CBD683E54D44555E6C95B5F2A72C0C193C6110C0221A448D0C9A0D8E36A84D5C61285128845215F8F8821C308E368283D8E2B42989C04A8B51354E09A38775020189010680840800297C31282442326D008D1F2351A89FFD7C16087F8B130F04418C0A1C082FC005843F5B42CADD9455ADBD328C13219110DE100D988737BBB44C414210118C673B0C1BDF76C499226F78FF41A0AF7AFD3308AAA0AAA22B1C70003F542A66FD1F1CF9D4578315F8C1C6FEC3EDB9B322CB204821A94A248414CE030020F207BF040A06A3DF993DEA3823423F405294A52014565100E0A7211342DF02958046899EEBE6E491299A09312778193FEBD7FFABA8000;
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defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h2C05EF54A3C0F7F5F017E03F5800377CCF6E493C84E8F56441831087370A084801DEC1A54696B9912E8B0705C8587D4F7D36C8638947A620554CC77819B55B7A12D552A8A0496EFE3AAC6F34739A94E798101823148D811212E9A349CC219049527CCD419525AD29AB7D372C0B56AA0A065F8BDC905346478059EC82801920687FF29C990C9E66273CC78041192D03081CC62A8A0D8CB4D9CF2F2558131A78B8A807C3A1110211AFCA2A142F0BA928156D142250438143D339E4E2079F298493C08C4847914664518E27EF7EB9C870A226AFC35BEDB651840466400D4B3C0F877740114D6B08228BCC693FB12CECCCD2461586069445ACFC910B1241434622B6;
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defparam \rom|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h5FFE6AD3343986C4103935236B6E6E11B940EF46A8FC06E6872A6929D50DCDB75621E625522D34519BF2C353F8AA030B9109C2F9686AD3AF57AF3016D9160354C0BED5FBD379F904A41BAFB6BE4EE9F208058229DD0C354F034A6C4D8B6C16A29F0120108829220B230F44550832C1022530CC13C4C30D8254ECA5200A1941266EE48A1CA6430860DE613153615CAF4C8D191004CE9C6105D8C6795B6484467D21D9DC46029B8376E97F2C7BF8C3A218EE79DDBCF886B2BBDE702F71B38AEC6914E5DCCAFE50CC13922A5B149C598A621F80C24D215291228844E7F33F9763C6639303AE5376F664C7125632C1A280CECD5740C77849D937472B202579964F60;
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// synopsys translate_on
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|
|
|
// Location: CLKCTRL_G15
|
|
cycloneive_clkctrl \CLOCK_50~inputclkctrl (
|
|
.ena(vcc),
|
|
.inclk({vcc,vcc,vcc,\CLOCK_50~input_o }),
|
|
.clkselect(2'b00),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.outclk(\CLOCK_50~inputclkctrl_outclk ));
|
|
// synopsys translate_off
|
|
defparam \CLOCK_50~inputclkctrl .clock_type = "global clock";
|
|
defparam \CLOCK_50~inputclkctrl .ena_register_mode = "none";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y10_N4
|
|
cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder (
|
|
// Equation(s):
|
|
// \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout = \z80_|address_pins_|abus[13]~20_combout
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|address_pins_|abus[13]~20_combout ),
|
|
.cin(gnd),
|
|
.combout(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .lut_mask = 16'hFF00;
|
|
defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder .sum_lutc_input = "datac";
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|
// synopsys translate_on
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|
|
|
// Location: FF_X23_Y10_N5
|
|
dffeas \ram0|altsyncram_component|auto_generated|address_reg_a[0] (
|
|
.clk(\CLOCK_50~inputclkctrl_outclk ),
|
|
.d(\ram0|altsyncram_component|auto_generated|address_reg_a[0]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ram0|altsyncram_component|auto_generated|address_reg_a [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .is_wysiwyg = "true";
|
|
defparam \ram0|altsyncram_component|auto_generated|address_reg_a[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X23_Y10_N15
|
|
dffeas \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] (
|
|
.clk(\CLOCK_50~inputclkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\ram0|altsyncram_component|auto_generated|address_reg_a [0]),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .is_wysiwyg = "true";
|
|
defparam \ram0|altsyncram_component|auto_generated|out_address_reg_a[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y10_N14
|
|
cycloneive_lcell_comb \Selector3~0 (
|
|
// Equation(s):
|
|
// \Selector3~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [14] & ((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))) # (!\z80_|address_pins_|DFFE_apin_latch [14] &
|
|
// (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]))))
|
|
|
|
.dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
|
|
.datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.datac(\ram0|altsyncram_component|auto_generated|out_address_reg_a [0]),
|
|
.datad(\z80_|address_pins_|DFFE_apin_latch [14]),
|
|
.cin(gnd),
|
|
.combout(\Selector3~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \Selector3~0 .lut_mask = 16'hF0B8;
|
|
defparam \Selector3~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y11_N22
|
|
cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0 (
|
|
// Equation(s):
|
|
// \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout = (\z80_|address_pins_|abus[14]~23_combout & (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[15]~22_combout & \z80_|address_pins_|abus[13]~20_combout )))
|
|
|
|
.dataa(\z80_|address_pins_|abus[14]~23_combout ),
|
|
.datab(\ExtRamWE~0_combout ),
|
|
.datac(\z80_|address_pins_|abus[15]~22_combout ),
|
|
.datad(\z80_|address_pins_|abus[13]~20_combout ),
|
|
.cin(gnd),
|
|
.combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0 .lut_mask = 16'h0800;
|
|
defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y31_N14
|
|
cycloneive_lcell_comb \~GND (
|
|
// Equation(s):
|
|
// \~GND~combout = GND
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\~GND~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \~GND .lut_mask = 16'h0000;
|
|
defparam \~GND .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y30_N24
|
|
cycloneive_lcell_comb \ula_|video_|vram_address[0]~feeder (
|
|
// Equation(s):
|
|
// \ula_|video_|vram_address[0]~feeder_combout = \ula_|video_|vga_hc [4]
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\ula_|video_|vga_hc [4]),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|vram_address[0]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
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|
defparam \ula_|video_|vram_address[0]~feeder .lut_mask = 16'hFF00;
|
|
defparam \ula_|video_|vram_address[0]~feeder .sum_lutc_input = "datac";
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|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y31_N26
|
|
cycloneive_lcell_comb \ula_|video_|vram_address~0 (
|
|
// Equation(s):
|
|
// \ula_|video_|vram_address~0_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [1] $ (\ula_|video_|vga_hc [2]))))
|
|
|
|
.dataa(\ula_|video_|vga_hc [1]),
|
|
.datab(\ula_|video_|vga_hc [3]),
|
|
.datac(\ula_|video_|vga_hc [2]),
|
|
.datad(\ula_|video_|vga_hc [0]),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|vram_address~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vram_address~0 .lut_mask = 16'h0048;
|
|
defparam \ula_|video_|vram_address~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y30_N25
|
|
dffeas \ula_|video_|vram_address[0] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|vram_address[0]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|video_|vram_address~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|vram_address [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vram_address[0] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|vram_address[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y30_N22
|
|
cycloneive_lcell_comb \ula_|video_|vram_address[1]~feeder (
|
|
// Equation(s):
|
|
// \ula_|video_|vram_address[1]~feeder_combout = \ula_|video_|vga_hc [5]
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\ula_|video_|vga_hc [5]),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|vram_address[1]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vram_address[1]~feeder .lut_mask = 16'hFF00;
|
|
defparam \ula_|video_|vram_address[1]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y30_N23
|
|
dffeas \ula_|video_|vram_address[1] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|vram_address[1]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|video_|vram_address~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|vram_address [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vram_address[1] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|vram_address[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y30_N20
|
|
cycloneive_lcell_comb \ula_|video_|vram_address[2]~4 (
|
|
// Equation(s):
|
|
// \ula_|video_|vram_address[2]~4_combout = !\ula_|video_|vga_hc [6]
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\ula_|video_|vga_hc [6]),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|vram_address[2]~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vram_address[2]~4 .lut_mask = 16'h0F0F;
|
|
defparam \ula_|video_|vram_address[2]~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y30_N21
|
|
dffeas \ula_|video_|vram_address[2] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|vram_address[2]~4_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|video_|vram_address~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|vram_address [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vram_address[2] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|vram_address[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y30_N30
|
|
cycloneive_lcell_comb \ula_|video_|Add3~0 (
|
|
// Equation(s):
|
|
// \ula_|video_|Add3~0_combout = \ula_|video_|vga_hc [6] $ (\ula_|video_|vga_hc [7])
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\ula_|video_|vga_hc [6]),
|
|
.datad(\ula_|video_|vga_hc [7]),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|Add3~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Add3~0 .lut_mask = 16'h0FF0;
|
|
defparam \ula_|video_|Add3~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y30_N31
|
|
dffeas \ula_|video_|vram_address[3] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|Add3~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|video_|vram_address~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|vram_address [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vram_address[3] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|vram_address[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y30_N16
|
|
cycloneive_lcell_comb \ula_|video_|Add3~1 (
|
|
// Equation(s):
|
|
// \ula_|video_|Add3~1_combout = \ula_|video_|vga_hc [8] $ (((!\ula_|video_|vga_hc [7]) # (!\ula_|video_|vga_hc [6])))
|
|
|
|
.dataa(\ula_|video_|vga_hc [8]),
|
|
.datab(gnd),
|
|
.datac(\ula_|video_|vga_hc [6]),
|
|
.datad(\ula_|video_|vga_hc [7]),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|Add3~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Add3~1 .lut_mask = 16'hA555;
|
|
defparam \ula_|video_|Add3~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y30_N17
|
|
dffeas \ula_|video_|vram_address[4] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|Add3~1_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|video_|vram_address~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|vram_address [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vram_address[4] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|vram_address[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y30_N10
|
|
cycloneive_lcell_comb \ula_|video_|Add4~0 (
|
|
// Equation(s):
|
|
// \ula_|video_|Add4~0_combout = (\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] $ (VCC))) # (!\ula_|video_|vga_vc [0] & (\ula_|video_|vga_vc [1] & VCC))
|
|
// \ula_|video_|Add4~1 = CARRY((\ula_|video_|vga_vc [0] & \ula_|video_|vga_vc [1]))
|
|
|
|
.dataa(\ula_|video_|vga_vc [0]),
|
|
.datab(\ula_|video_|vga_vc [1]),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|Add4~0_combout ),
|
|
.cout(\ula_|video_|Add4~1 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Add4~0 .lut_mask = 16'h6688;
|
|
defparam \ula_|video_|Add4~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y30_N12
|
|
cycloneive_lcell_comb \ula_|video_|Add4~2 (
|
|
// Equation(s):
|
|
// \ula_|video_|Add4~2_combout = (\ula_|video_|vga_vc [2] & (\ula_|video_|Add4~1 & VCC)) # (!\ula_|video_|vga_vc [2] & (!\ula_|video_|Add4~1 ))
|
|
// \ula_|video_|Add4~3 = CARRY((!\ula_|video_|vga_vc [2] & !\ula_|video_|Add4~1 ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|video_|vga_vc [2]),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\ula_|video_|Add4~1 ),
|
|
.combout(\ula_|video_|Add4~2_combout ),
|
|
.cout(\ula_|video_|Add4~3 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Add4~2 .lut_mask = 16'hC303;
|
|
defparam \ula_|video_|Add4~2 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y30_N14
|
|
cycloneive_lcell_comb \ula_|video_|Add4~4 (
|
|
// Equation(s):
|
|
// \ula_|video_|Add4~4_combout = (\ula_|video_|vga_vc [3] & ((GND) # (!\ula_|video_|Add4~3 ))) # (!\ula_|video_|vga_vc [3] & (\ula_|video_|Add4~3 $ (GND)))
|
|
// \ula_|video_|Add4~5 = CARRY((\ula_|video_|vga_vc [3]) # (!\ula_|video_|Add4~3 ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|video_|vga_vc [3]),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\ula_|video_|Add4~3 ),
|
|
.combout(\ula_|video_|Add4~4_combout ),
|
|
.cout(\ula_|video_|Add4~5 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Add4~4 .lut_mask = 16'h3CCF;
|
|
defparam \ula_|video_|Add4~4 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y30_N16
|
|
cycloneive_lcell_comb \ula_|video_|Add4~6 (
|
|
// Equation(s):
|
|
// \ula_|video_|Add4~6_combout = (\ula_|video_|vga_vc [4] & (!\ula_|video_|Add4~5 )) # (!\ula_|video_|vga_vc [4] & ((\ula_|video_|Add4~5 ) # (GND)))
|
|
// \ula_|video_|Add4~7 = CARRY((!\ula_|video_|Add4~5 ) # (!\ula_|video_|vga_vc [4]))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|video_|vga_vc [4]),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\ula_|video_|Add4~5 ),
|
|
.combout(\ula_|video_|Add4~6_combout ),
|
|
.cout(\ula_|video_|Add4~7 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Add4~6 .lut_mask = 16'h3C3F;
|
|
defparam \ula_|video_|Add4~6 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y30_N17
|
|
dffeas \ula_|video_|vram_address[5] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|Add4~6_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|video_|vram_address~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|vram_address [5]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vram_address[5] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|vram_address[5] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y30_N18
|
|
cycloneive_lcell_comb \ula_|video_|Add4~8 (
|
|
// Equation(s):
|
|
// \ula_|video_|Add4~8_combout = (\ula_|video_|vga_vc [5] & ((GND) # (!\ula_|video_|Add4~7 ))) # (!\ula_|video_|vga_vc [5] & (\ula_|video_|Add4~7 $ (GND)))
|
|
// \ula_|video_|Add4~9 = CARRY((\ula_|video_|vga_vc [5]) # (!\ula_|video_|Add4~7 ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|video_|vga_vc [5]),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\ula_|video_|Add4~7 ),
|
|
.combout(\ula_|video_|Add4~8_combout ),
|
|
.cout(\ula_|video_|Add4~9 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Add4~8 .lut_mask = 16'h3CCF;
|
|
defparam \ula_|video_|Add4~8 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y30_N19
|
|
dffeas \ula_|video_|vram_address[6] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|Add4~8_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|video_|vram_address~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|vram_address [6]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vram_address[6] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|vram_address[6] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y30_N20
|
|
cycloneive_lcell_comb \ula_|video_|Add4~10 (
|
|
// Equation(s):
|
|
// \ula_|video_|Add4~10_combout = (\ula_|video_|vga_vc [6] & (!\ula_|video_|Add4~9 )) # (!\ula_|video_|vga_vc [6] & ((\ula_|video_|Add4~9 ) # (GND)))
|
|
// \ula_|video_|Add4~11 = CARRY((!\ula_|video_|Add4~9 ) # (!\ula_|video_|vga_vc [6]))
|
|
|
|
.dataa(\ula_|video_|vga_vc [6]),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\ula_|video_|Add4~9 ),
|
|
.combout(\ula_|video_|Add4~10_combout ),
|
|
.cout(\ula_|video_|Add4~11 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Add4~10 .lut_mask = 16'h5A5F;
|
|
defparam \ula_|video_|Add4~10 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y30_N21
|
|
dffeas \ula_|video_|vram_address[7] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|Add4~10_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|video_|vram_address~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|vram_address [7]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vram_address[7] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|vram_address[7] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y30_N22
|
|
cycloneive_lcell_comb \ula_|video_|Add4~12 (
|
|
// Equation(s):
|
|
// \ula_|video_|Add4~12_combout = (\ula_|video_|vga_vc [7] & ((GND) # (!\ula_|video_|Add4~11 ))) # (!\ula_|video_|vga_vc [7] & (\ula_|video_|Add4~11 $ (GND)))
|
|
// \ula_|video_|Add4~13 = CARRY((\ula_|video_|vga_vc [7]) # (!\ula_|video_|Add4~11 ))
|
|
|
|
.dataa(\ula_|video_|vga_vc [7]),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\ula_|video_|Add4~11 ),
|
|
.combout(\ula_|video_|Add4~12_combout ),
|
|
.cout(\ula_|video_|Add4~13 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Add4~12 .lut_mask = 16'h5AAF;
|
|
defparam \ula_|video_|Add4~12 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y30_N26
|
|
cycloneive_lcell_comb \ula_|video_|Selector6~0 (
|
|
// Equation(s):
|
|
// \ula_|video_|Selector6~0_combout = (\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~12_combout ))) # (!\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~0_combout ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|video_|vga_hc [2]),
|
|
.datac(\ula_|video_|Add4~0_combout ),
|
|
.datad(\ula_|video_|Add4~12_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|Selector6~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Selector6~0 .lut_mask = 16'hFC30;
|
|
defparam \ula_|video_|Selector6~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y31_N16
|
|
cycloneive_lcell_comb \ula_|video_|vram_address[9]~1 (
|
|
// Equation(s):
|
|
// \ula_|video_|vram_address[9]~1_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [1] $ (\ula_|video_|vga_hc [2]))))
|
|
|
|
.dataa(\ula_|video_|vga_hc [1]),
|
|
.datab(\ula_|video_|vga_hc [3]),
|
|
.datac(\ula_|video_|vga_hc [2]),
|
|
.datad(\ula_|video_|vga_hc [0]),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|vram_address[9]~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vram_address[9]~1 .lut_mask = 16'h0048;
|
|
defparam \ula_|video_|vram_address[9]~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y30_N27
|
|
dffeas \ula_|video_|vram_address[8] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|Selector6~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|video_|vram_address[9]~1_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|vram_address [8]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vram_address[8] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|vram_address[8] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y30_N24
|
|
cycloneive_lcell_comb \ula_|video_|Add4~14 (
|
|
// Equation(s):
|
|
// \ula_|video_|Add4~14_combout = \ula_|video_|Add4~13 $ (!\ula_|video_|vga_vc [8])
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\ula_|video_|vga_vc [8]),
|
|
.cin(\ula_|video_|Add4~13 ),
|
|
.combout(\ula_|video_|Add4~14_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Add4~14 .lut_mask = 16'hF00F;
|
|
defparam \ula_|video_|Add4~14 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y30_N12
|
|
cycloneive_lcell_comb \ula_|video_|Selector5~0 (
|
|
// Equation(s):
|
|
// \ula_|video_|Selector5~0_combout = (\ula_|video_|vga_hc [2] & ((\ula_|video_|Add4~14_combout ))) # (!\ula_|video_|vga_hc [2] & (\ula_|video_|Add4~2_combout ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|video_|vga_hc [2]),
|
|
.datac(\ula_|video_|Add4~2_combout ),
|
|
.datad(\ula_|video_|Add4~14_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|Selector5~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Selector5~0 .lut_mask = 16'hFC30;
|
|
defparam \ula_|video_|Selector5~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y30_N13
|
|
dffeas \ula_|video_|vram_address[9] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|Selector5~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|video_|vram_address[9]~1_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|vram_address [9]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vram_address[9] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|vram_address[9] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y31_N6
|
|
cycloneive_lcell_comb \ula_|video_|vram_address[10]~2 (
|
|
// Equation(s):
|
|
// \ula_|video_|vram_address[10]~2_combout = (\ula_|video_|vga_hc [3] & (!\ula_|video_|vga_hc [0] & (\ula_|video_|vga_hc [1] $ (\ula_|video_|vga_hc [2]))))
|
|
|
|
.dataa(\ula_|video_|vga_hc [1]),
|
|
.datab(\ula_|video_|vga_hc [3]),
|
|
.datac(\ula_|video_|vga_hc [2]),
|
|
.datad(\ula_|video_|vga_hc [0]),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|vram_address[10]~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vram_address[10]~2 .lut_mask = 16'h0048;
|
|
defparam \ula_|video_|vram_address[10]~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y31_N28
|
|
cycloneive_lcell_comb \ula_|video_|vram_address[10]~3 (
|
|
// Equation(s):
|
|
// \ula_|video_|vram_address[10]~3_combout = (\ula_|video_|vram_address[10]~2_combout & (\ula_|video_|vga_hc [1] & (\ula_|video_|Add4~4_combout ))) # (!\ula_|video_|vram_address[10]~2_combout & (((\ula_|video_|vram_address [10]))))
|
|
|
|
.dataa(\ula_|video_|vga_hc [1]),
|
|
.datab(\ula_|video_|Add4~4_combout ),
|
|
.datac(\ula_|video_|vram_address [10]),
|
|
.datad(\ula_|video_|vram_address[10]~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|vram_address[10]~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vram_address[10]~3 .lut_mask = 16'h88F0;
|
|
defparam \ula_|video_|vram_address[10]~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y31_N29
|
|
dffeas \ula_|video_|vram_address[10] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|vram_address[10]~3_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|vram_address [10]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vram_address[10] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|vram_address[10] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y30_N6
|
|
cycloneive_lcell_comb \ula_|video_|Selector3~0 (
|
|
// Equation(s):
|
|
// \ula_|video_|Selector3~0_combout = (\ula_|video_|vga_hc [2]) # (\ula_|video_|Add4~12_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\ula_|video_|vga_hc [2]),
|
|
.datad(\ula_|video_|Add4~12_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|Selector3~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Selector3~0 .lut_mask = 16'hFFF0;
|
|
defparam \ula_|video_|Selector3~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y30_N7
|
|
dffeas \ula_|video_|vram_address[11] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|Selector3~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|video_|vram_address[9]~1_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|vram_address [11]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vram_address[11] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|vram_address[11] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y30_N8
|
|
cycloneive_lcell_comb \ula_|video_|Selector2~0 (
|
|
// Equation(s):
|
|
// \ula_|video_|Selector2~0_combout = (\ula_|video_|vga_hc [2]) # (\ula_|video_|Add4~14_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\ula_|video_|vga_hc [2]),
|
|
.datad(\ula_|video_|Add4~14_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|Selector2~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Selector2~0 .lut_mask = 16'hFFF0;
|
|
defparam \ula_|video_|Selector2~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y30_N9
|
|
dffeas \ula_|video_|vram_address[12] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|Selector2~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|video_|vram_address[9]~1_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|vram_address [12]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|vram_address[12] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|vram_address[12] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X33_Y26_N0
|
|
cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a9 (
|
|
.portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\CLOCK_50~inputclkctrl_outclk ),
|
|
.clk1(\CLOCK_50~inputclkctrl_outclk ),
|
|
.ena0(\z80_|address_pins_|abus[13]~20_combout ),
|
|
.ena1(gnd),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[1]~32_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain({\~GND~combout }),
|
|
.portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4],
|
|
\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk0_core_clock_enable = "ena0";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .clk1_core_clock_enable = "ena1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file = "ula/test_scr.hex";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .init_file_layout = "port_a";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mixed_port_feed_through_mode = "dont_care";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .operation_mode = "bidir_dual_port";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_address_width = 13;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_out_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_data_width = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_address = 0;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_first_bit_number = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_last_address = 8191;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 16384;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_logical_ram_width = 8;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_address_width = 13;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_in_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_out_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_data_width = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_address = 0;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_first_bit_number = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_last_address = 8191;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_depth = 16384;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_logical_ram_width = 8;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_read_enable_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .port_b_write_enable_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .ram_block_type = "M9K";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a9 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y11_N10
|
|
cycloneive_lcell_comb \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1 (
|
|
// Equation(s):
|
|
// \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout = (\z80_|address_pins_|abus[14]~23_combout & (\ExtRamWE~0_combout & (!\z80_|address_pins_|abus[15]~22_combout & !\z80_|address_pins_|abus[13]~20_combout )))
|
|
|
|
.dataa(\z80_|address_pins_|abus[14]~23_combout ),
|
|
.datab(\ExtRamWE~0_combout ),
|
|
.datac(\z80_|address_pins_|abus[15]~22_combout ),
|
|
.datad(\z80_|address_pins_|abus[13]~20_combout ),
|
|
.cin(gnd),
|
|
.combout(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1 .lut_mask = 16'h0008;
|
|
defparam \ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X33_Y30_N0
|
|
cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a1 (
|
|
.portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\CLOCK_50~inputclkctrl_outclk ),
|
|
.clk1(\CLOCK_50~inputclkctrl_outclk ),
|
|
.ena0(!\z80_|address_pins_|abus[13]~20_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[1]~32_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain({\~GND~combout }),
|
|
.portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4],
|
|
\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ),
|
|
.portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a1_PORTBDATAOUT_bus ));
|
|
// synopsys translate_off
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .clk0_core_clock_enable = "ena0";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .data_interleave_width_in_bits = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file = "ula/test_scr.hex";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .init_file_layout = "port_a";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mixed_port_feed_through_mode = "dont_care";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .operation_mode = "bidir_dual_port";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_address_width = 13;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_byte_enable_clock = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_out_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_data_width = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_address = 0;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_first_bit_number = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_last_address = 8191;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_depth = 16384;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_logical_ram_width = 8;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_address_width = 13;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_in_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_out_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_data_width = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_address = 0;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_first_bit_number = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_last_address = 8191;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_depth = 16384;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_logical_ram_width = 8;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_read_enable_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .port_b_write_enable_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .ram_block_type = "M9K";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF08003E0108003E010E3E3FFF007F3C0000FF3C0000FDBC1F40FFFC3FC1FFFE3FE7FEFE3FE7FDFFFFE7FFFDFFE2FFFDFFE1F8FDFFE1F9FEF871FFFD7058FF3E8C30067FFFFFFFFFFFFFFFF;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408102A0040070801214EA871928C2000000000000000000000000FFFFFFFFA0408103C0040273851234A2871928CA00000000000000000000000080000000BFFFFFFFC00406738D523F828719508E000000000000000000000000800000009FBF7EFD8004143A8D123F0E831959CA0000000000000000000000009FBF7EFC80000000800608228D5333C68B9919FA000000000000000000000000BFFFFFFEC000000180060082801313668B9973F6000000000000000000000000E0408102FFFFFFFD9FE60AFA87732526801913E6000000000000000000000000C0000000FFFFFFFD9FF60AFA877300268019136E;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init1 = 2048'h9FE8332288F812F68FF0C7C6CC6806F2895C8DE2B8019AE68988BF4291EC79C29FE0036A887802F29FE887C6CCE846E3892C8FE299C09DE28BA8BFC298F43A8280000372886806C29FE88302CC2042E388608DE299E89DC28AA8BEC298B41AE28000037E882856C29EE8818288E042A288608DF289F897C28AA8BFD298B019F28008937E880847C69EE881C288E04AE288B08FE288D8D0428AE02EC298BC08EA800883FA88084786DC2880D388004FE289D08DE288B081428BF07E82C8FC0AAB800883F2880847C6DC2882C389900B6289D89D668820D94283143782C8FC49C3800882F6880857C69C0882C381940BE289889DE28900B94281BC7D82899C88F3;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a1 .mem_init0 = 2048'hCB9C84F288C855028DE04086AC0122869175A48288D30882FFFFFFFCC0000002CB9C80B78DD447828DE440828C0126829175840280D10B82FFFFFFFDE0408082C8D480838FD45582881C4482840160028179800280510B82C0000001BFFFFFFE8AD480BA8F844182880860828601660A8179900280510B02800000009FBF7F7C8B90A1328C8401828BE0608A86836E1281791012805107029FBF7F7D800000008B9883228C9405828BE0728286832E0281799042C0500F43BFFFFFFF80000000889081128FD400828A0066828782288281199002C0401F03A0408083FFFFFFFF888881128FE440828800268287D22CE280199022A0003F00E0408080FFFFFFFF;
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|
// synopsys translate_on
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|
|
|
// Location: LCCOMB_X30_Y10_N20
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|
cycloneive_lcell_comb \Selector1~0 (
|
|
// Equation(s):
|
|
// \Selector1~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\Selector3~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout )) # (!\Selector3~0_combout &
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|
// ((\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ))))) # (!\z80_|address_pins_|abus[14]~23_combout & (\Selector3~0_combout ))
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|
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.dataa(\z80_|address_pins_|abus[14]~23_combout ),
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|
.datab(\Selector3~0_combout ),
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|
.datac(\ram0|altsyncram_component|auto_generated|ram_block1a9~portadataout ),
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|
.datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~portadataout ),
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|
.cin(gnd),
|
|
.combout(\Selector1~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \Selector1~0 .lut_mask = 16'hE6C4;
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|
defparam \Selector1~0 .sum_lutc_input = "datac";
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|
// synopsys translate_on
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|
|
|
// Location: LCCOMB_X30_Y10_N22
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|
cycloneive_lcell_comb \Selector1~1 (
|
|
// Equation(s):
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|
// \Selector1~1_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\Selector1~0_combout )))) # (!\z80_|address_pins_|abus[14]~23_combout & ((\Selector1~0_combout & ((\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ))) #
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|
// (!\Selector1~0_combout & (\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ))))
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|
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.dataa(\z80_|address_pins_|abus[14]~23_combout ),
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|
.datab(\rom|altsyncram_component|auto_generated|ram_block1a1~portadataout ),
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|
.datac(\rom|altsyncram_component|auto_generated|ram_block1a9~portadataout ),
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|
.datad(\Selector1~0_combout ),
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|
.cin(gnd),
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|
.combout(\Selector1~1_combout ),
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|
.cout());
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|
// synopsys translate_off
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|
defparam \Selector1~1 .lut_mask = 16'hFA44;
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defparam \Selector1~1 .sum_lutc_input = "datac";
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|
// synopsys translate_on
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|
|
// Location: LCCOMB_X31_Y10_N28
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cycloneive_lcell_comb \D[1]~81 (
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|
// Equation(s):
|
|
// \D[1]~81_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\Selector1~1_combout )))
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// # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ))))
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|
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|
.dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[1]~1_combout ),
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.datab(\z80_|address_pins_|DFFE_apin_latch [15]),
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|
.datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
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|
.datad(\Selector1~1_combout ),
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|
.cin(gnd),
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.combout(\D[1]~81_combout ),
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|
.cout());
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|
// synopsys translate_off
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|
defparam \D[1]~81 .lut_mask = 16'hBA8A;
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defparam \D[1]~81 .sum_lutc_input = "datac";
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|
// synopsys translate_on
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|
|
|
// Location: LCCOMB_X31_Y10_N20
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cycloneive_lcell_comb \D[1]~31 (
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|
// Equation(s):
|
|
// \D[1]~31_combout = ((\Equal2~0_combout & (\D[1]~30_combout )) # (!\Equal2~0_combout & ((\D[1]~81_combout )))) # (!\Equal2~1_combout )
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|
|
|
.dataa(\Equal2~1_combout ),
|
|
.datab(\Equal2~0_combout ),
|
|
.datac(\D[1]~30_combout ),
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|
.datad(\D[1]~81_combout ),
|
|
.cin(gnd),
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|
.combout(\D[1]~31_combout ),
|
|
.cout());
|
|
// synopsys translate_off
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|
defparam \D[1]~31 .lut_mask = 16'hF7D5;
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|
defparam \D[1]~31 .sum_lutc_input = "datac";
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|
// synopsys translate_on
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|
|
|
// Location: LCCOMB_X31_Y10_N2
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|
cycloneive_lcell_comb \D[1]~32 (
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|
// Equation(s):
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|
// \D[1]~32_combout = (\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\z80_|data_pins_|dout [1] & \D[1]~31_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\D[1]~31_combout )) # (!\Equal2~1_combout )))
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|
|
|
.dataa(\Equal2~1_combout ),
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|
.datab(\z80_|data_pins_|dout [1]),
|
|
.datac(\z80_|pin_control_|bus_db_pin_oe~15_combout ),
|
|
.datad(\D[1]~31_combout ),
|
|
.cin(gnd),
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|
.combout(\D[1]~32_combout ),
|
|
.cout());
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|
// synopsys translate_off
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|
defparam \D[1]~32 .lut_mask = 16'hCF05;
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|
defparam \D[1]~32 .sum_lutc_input = "datac";
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|
// synopsys translate_on
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|
|
|
// Location: LCCOMB_X30_Y13_N14
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|
cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] (
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|
// Equation(s):
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|
// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [1] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[1]~11_combout ) # ((\D[1]~32_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout &
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// (((\D[1]~32_combout & \z80_|pin_control_|bus_db_pin_re~combout ))))
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.dataa(\z80_|execute_|ctl_bus_db_we~7_combout ),
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|
.datab(\z80_|bus_control_|db[1]~11_combout ),
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|
.datac(\D[1]~32_combout ),
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|
.datad(\z80_|pin_control_|bus_db_pin_re~combout ),
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|
.cin(gnd),
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|
.combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]),
|
|
.cout());
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|
// synopsys translate_off
|
|
defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .lut_mask = 16'hF888;
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|
defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[1] .sum_lutc_input = "datac";
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|
// synopsys translate_on
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|
|
|
// Location: LCCOMB_X28_Y12_N16
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cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re~2 (
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|
// Equation(s):
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|
// \z80_|pin_control_|bus_db_pin_re~2_combout = (\z80_|sequencer_|DFFE_T2_ff~q & (((\z80_|execute_|fIORead~3_combout & \z80_|sequencer_|DFFE_T3_ff~q )) # (!\z80_|sequencer_|DFFE_M1_ff~q ))) # (!\z80_|sequencer_|DFFE_T2_ff~q &
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// (\z80_|execute_|fIORead~3_combout & ((\z80_|sequencer_|DFFE_T3_ff~q ))))
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.dataa(\z80_|sequencer_|DFFE_T2_ff~q ),
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|
.datab(\z80_|execute_|fIORead~3_combout ),
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|
.datac(\z80_|sequencer_|DFFE_M1_ff~q ),
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|
.datad(\z80_|sequencer_|DFFE_T3_ff~q ),
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|
.cin(gnd),
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|
.combout(\z80_|pin_control_|bus_db_pin_re~2_combout ),
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|
.cout());
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|
// synopsys translate_off
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|
defparam \z80_|pin_control_|bus_db_pin_re~2 .lut_mask = 16'hCE0A;
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|
defparam \z80_|pin_control_|bus_db_pin_re~2 .sum_lutc_input = "datac";
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|
// synopsys translate_on
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|
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|
// Location: LCCOMB_X30_Y13_N8
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cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_2 (
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|
// Equation(s):
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|
// \z80_|data_pins_|SYNTHESIZED_WIRE_2~combout = (\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|execute_|fMRead~36_combout & \z80_|sequencer_|DFFE_T2_ff~q )))
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|
.dataa(\z80_|execute_|ctl_bus_db_we~7_combout ),
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|
.datab(\z80_|execute_|fMRead~36_combout ),
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|
.datac(\z80_|sequencer_|DFFE_T2_ff~q ),
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|
.datad(\z80_|pin_control_|bus_db_pin_re~2_combout ),
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|
.cin(gnd),
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|
.combout(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ),
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|
.cout());
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|
// synopsys translate_off
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|
defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .lut_mask = 16'hFFEA;
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defparam \z80_|data_pins_|SYNTHESIZED_WIRE_2 .sum_lutc_input = "datac";
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|
// synopsys translate_on
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|
|
|
// Location: FF_X30_Y13_N15
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|
dffeas \z80_|data_pins_|dout[1] (
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|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
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|
.d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [1]),
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|
.asdata(vcc),
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|
.clrn(vcc),
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|
.aload(gnd),
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|
.sclr(gnd),
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|
.sload(gnd),
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|
.ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ),
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|
.devclrn(devclrn),
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|
.devpor(devpor),
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|
.q(\z80_|data_pins_|dout [1]),
|
|
.prn(vcc));
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|
// synopsys translate_off
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|
defparam \z80_|data_pins_|dout[1] .is_wysiwyg = "true";
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|
defparam \z80_|data_pins_|dout[1] .power_up = "low";
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|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y13_N28
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|
cycloneive_lcell_comb \z80_|bus_control_|db[1]~11 (
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|
// Equation(s):
|
|
// \z80_|bus_control_|db[1]~11_combout = ((\z80_|bus_control_|db[1]~10_combout & ((\z80_|data_pins_|dout [1]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout )
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|
.dataa(\z80_|bus_control_|db[0]~6_combout ),
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|
.datab(\z80_|bus_control_|db[1]~10_combout ),
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|
.datac(\z80_|data_pins_|dout [1]),
|
|
.datad(\z80_|execute_|ctl_bus_db_oe~combout ),
|
|
.cin(gnd),
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|
.combout(\z80_|bus_control_|db[1]~11_combout ),
|
|
.cout());
|
|
// synopsys translate_off
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|
defparam \z80_|bus_control_|db[1]~11 .lut_mask = 16'hD5DD;
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|
defparam \z80_|bus_control_|db[1]~11 .sum_lutc_input = "datac";
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|
// synopsys translate_on
|
|
|
|
// Location: FF_X30_Y13_N29
|
|
dffeas \z80_|ir_|opcode[1] (
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|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
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|
.d(\z80_|bus_control_|db[1]~11_combout ),
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|
.asdata(vcc),
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|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
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|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|execute_|ctl_ir_we~13_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|ir_|opcode [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|ir_|opcode[1] .is_wysiwyg = "true";
|
|
defparam \z80_|ir_|opcode[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y13_N0
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal2~0 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal2~0_combout = (!\z80_|ir_|opcode [2] & \z80_|ir_|opcode [1])
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|ir_|opcode [2]),
|
|
.datac(\z80_|ir_|opcode [1]),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal2~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal2~0 .lut_mask = 16'h3030;
|
|
defparam \z80_|pla_decode_|Equal2~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y17_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_mRead~15 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mRead~15_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal13~0_combout & \z80_|ir_|opcode [3])))
|
|
|
|
.dataa(\z80_|ir_|opcode [0]),
|
|
.datab(\z80_|pla_decode_|Equal2~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal13~0_combout ),
|
|
.datad(\z80_|ir_|opcode [3]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mRead~15_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mRead~15 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|ctl_mRead~15 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y14_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_inc_cy~39 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_inc_cy~39_combout = (((!\z80_|sequencer_|M5~q & !\z80_|sequencer_|DFFE_M4_ff~q )) # (!\z80_|sequencer_|DFFE_T2_ff~q )) # (!\z80_|execute_|ctl_mRead~15_combout )
|
|
|
|
.dataa(\z80_|sequencer_|M5~q ),
|
|
.datab(\z80_|sequencer_|DFFE_M4_ff~q ),
|
|
.datac(\z80_|execute_|ctl_mRead~15_combout ),
|
|
.datad(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_inc_cy~39_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_inc_cy~39 .lut_mask = 16'h1FFF;
|
|
defparam \z80_|execute_|ctl_inc_cy~39 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y13_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo[1]~36 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sys_hilo[1]~36_combout = (\z80_|execute_|ctl_inc_cy~39_combout & (\z80_|execute_|ctl_inc_cy~38_combout & \z80_|execute_|ctl_inc_cy~82_combout ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|execute_|ctl_inc_cy~39_combout ),
|
|
.datac(\z80_|execute_|ctl_inc_cy~38_combout ),
|
|
.datad(\z80_|execute_|ctl_inc_cy~82_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .lut_mask = 16'hC000;
|
|
defparam \z80_|execute_|ctl_reg_sys_hilo[1]~36 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y13_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_sw_4u~4_combout = (\z80_|execute_|ctl_alu_op_low~22_combout & (\z80_|pla_decode_|Equal55~0_combout & (!\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal6~0_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op_low~22_combout ),
|
|
.datab(\z80_|pla_decode_|Equal55~0_combout ),
|
|
.datac(\z80_|ir_|opcode [5]),
|
|
.datad(\z80_|pla_decode_|Equal6~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_sw_4u~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_sw_4u~4 .lut_mask = 16'h0800;
|
|
defparam \z80_|execute_|ctl_sw_4u~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y13_N28
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~16 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sel_wz~16_combout = (!\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout & (!\z80_|execute_|ctl_sw_4u~4_combout & ((!\z80_|execute_|ctl_state_alu~2_combout ) # (!\z80_|execute_|ctl_ir_we~12_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_sys_hilo_pla38pla13M4T2_4~combout ),
|
|
.datab(\z80_|execute_|ctl_ir_we~12_combout ),
|
|
.datac(\z80_|execute_|ctl_state_alu~2_combout ),
|
|
.datad(\z80_|execute_|ctl_sw_4u~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sel_wz~16_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sel_wz~16 .lut_mask = 16'h0015;
|
|
defparam \z80_|execute_|ctl_reg_sel_wz~16 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y13_N2
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~17 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sel_wz~17_combout = (\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout & (\z80_|execute_|fMRead~6_combout & (\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout & \z80_|execute_|ctl_reg_sel_wz~16_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~36_combout ),
|
|
.datab(\z80_|execute_|fMRead~6_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_sys_hilo[1]~10_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sel_wz~16_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sel_wz~17_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sel_wz~17 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|ctl_reg_sel_wz~17 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y17_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~5 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_sw_4u~5_combout = (\z80_|execute_|ctl_alu_op_low~28_combout ) # (((\z80_|execute_|ctl_alu_shift_oe~14_combout & \z80_|pla_decode_|Equal47~0_combout )) # (!\z80_|execute_|ctl_sw_4u~1_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_shift_oe~14_combout ),
|
|
.datab(\z80_|pla_decode_|Equal47~0_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_op_low~28_combout ),
|
|
.datad(\z80_|execute_|ctl_sw_4u~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_sw_4u~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_sw_4u~5 .lut_mask = 16'hF8FF;
|
|
defparam \z80_|execute_|ctl_sw_4u~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y15_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_sw_4u~6 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_sw_4u~6_combout = (((\z80_|execute_|ctl_sw_4u~5_combout ) # (!\z80_|execute_|ctl_sw_4u~3_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout )) # (!\z80_|execute_|ctl_reg_sel_wz~17_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_sel_wz~17_combout ),
|
|
.datab(\z80_|execute_|ctl_apin_mux~0_combout ),
|
|
.datac(\z80_|execute_|ctl_sw_4u~3_combout ),
|
|
.datad(\z80_|execute_|ctl_sw_4u~5_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_sw_4u~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_sw_4u~6 .lut_mask = 16'hFF7F;
|
|
defparam \z80_|execute_|ctl_sw_4u~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X30_Y12_N27
|
|
dffeas \z80_|reg_file_|b2v_latch_hl_lo|latch[3] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_59~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_hl_lo|latch[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X30_Y12_N29
|
|
dffeas \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_55~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_hl2_lo|latch[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y12_N28
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~44 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[3]~44_combout = (\z80_|reg_file_|b2v_latch_hl_lo|latch [3] & (((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))) # (!\z80_|reg_file_|b2v_latch_hl_lo|latch [3] &
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout & ((\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|b2v_latch_hl_lo|latch [3]),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_54~combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_hl2_lo|latch [3]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_58~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[3]~44_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[3]~44 .lut_mask = 16'hA2F3;
|
|
defparam \z80_|reg_file_|gdfx_temp0[3]~44 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X31_Y11_N21
|
|
dffeas \z80_|reg_file_|b2v_latch_de2_lo|latch[3] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_47~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_de2_lo|latch[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X31_Y11_N11
|
|
dffeas \z80_|reg_file_|b2v_latch_de_lo|latch[3] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_51~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_de_lo|latch [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_de_lo|latch[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y11_N20
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~43 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[3]~43_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (\z80_|reg_file_|b2v_latch_de_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_de2_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout & (((\z80_|reg_file_|b2v_latch_de2_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_50~combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_46~combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_de2_lo|latch [3]),
|
|
.datad(\z80_|reg_file_|b2v_latch_de_lo|latch [3]),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[3]~43_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[3]~43 .lut_mask = 16'hF351;
|
|
defparam \z80_|reg_file_|gdfx_temp0[3]~43 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y13_N7
|
|
dffeas \z80_|reg_file_|b2v_latch_wz_lo|latch[3] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_83~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_wz_lo|latch[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y14_N13
|
|
dffeas \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_39~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_bc2_lo|latch[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y14_N12
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~46 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[3]~46_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (\z80_|reg_file_|b2v_latch_bc2_lo|latch [3] & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout & (((\z80_|alu_control_|db[3]~35_combout )) # (!\z80_|execute_|ctl_reg_in_lo~8_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_38~0_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_in_lo~8_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_bc2_lo|latch [3]),
|
|
.datad(\z80_|alu_control_|db[3]~35_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[3]~46_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[3]~46 .lut_mask = 16'hF531;
|
|
defparam \z80_|reg_file_|gdfx_temp0[3]~46 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y13_N6
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~47 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[3]~47_combout = (\z80_|reg_file_|gdfx_temp0[3]~46_combout & ((\z80_|reg_file_|b2v_latch_wz_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout )))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_82~combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_wz_lo|latch [3]),
|
|
.datad(\z80_|reg_file_|gdfx_temp0[3]~46_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[3]~47_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[3]~47 .lut_mask = 16'hF300;
|
|
defparam \z80_|reg_file_|gdfx_temp0[3]~47 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y12_N30
|
|
cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~52_combout
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|reg_file_|gdfx_temp0[3]~52_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder .lut_mask = 16'hFF00;
|
|
defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X31_Y12_N31
|
|
dffeas \z80_|reg_file_|b2v_latch_iy_lo|latch[3] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_file_|b2v_latch_iy_lo|latch[3]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_71~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_iy_lo|latch[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y12_N13
|
|
dffeas \z80_|reg_file_|b2v_latch_sp_lo|latch[3] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_79~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_sp_lo|latch[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y12_N12
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~49 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[3]~49_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & (\z80_|reg_file_|b2v_latch_sp_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout & ((\z80_|reg_file_|b2v_latch_iy_lo|latch [3]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_78~0_combout ),
|
|
.datab(\z80_|reg_file_|b2v_latch_iy_lo|latch [3]),
|
|
.datac(\z80_|reg_file_|b2v_latch_sp_lo|latch [3]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_70~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[3]~49_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[3]~49 .lut_mask = 16'hC4F5;
|
|
defparam \z80_|reg_file_|gdfx_temp0[3]~49 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y11_N27
|
|
dffeas \z80_|reg_file_|b2v_latch_af2_lo|latch[3] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_31~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_af2_lo|latch[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y11_N12
|
|
cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout = \z80_|reg_file_|gdfx_temp0[3]~52_combout
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|reg_file_|gdfx_temp0[3]~52_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder .lut_mask = 16'hFF00;
|
|
defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y11_N13
|
|
dffeas \z80_|reg_file_|b2v_latch_af_lo|latch[3] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_file_|b2v_latch_af_lo|latch[3]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_35~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_af_lo|latch [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_af_lo|latch[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y11_N26
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~45 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[3]~45_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (\z80_|reg_file_|b2v_latch_af2_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_af_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout & (((\z80_|reg_file_|b2v_latch_af_lo|latch [3])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_30~combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_34~combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_af2_lo|latch [3]),
|
|
.datad(\z80_|reg_file_|b2v_latch_af_lo|latch [3]),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[3]~45_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[3]~45 .lut_mask = 16'hF531;
|
|
defparam \z80_|reg_file_|gdfx_temp0[3]~45 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y13_N17
|
|
dffeas \z80_|reg_file_|b2v_latch_ix_lo|latch[3] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_67~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_ix_lo|latch[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y14_N15
|
|
dffeas \z80_|reg_file_|b2v_latch_bc_lo|latch[3] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp0[3]~52_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_43~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_bc_lo|latch[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y14_N14
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~48 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[3]~48_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (\z80_|reg_file_|b2v_latch_ix_lo|latch [3] & ((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout & (((\z80_|reg_file_|b2v_latch_bc_lo|latch [3]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_66~0_combout ),
|
|
.datab(\z80_|reg_file_|b2v_latch_ix_lo|latch [3]),
|
|
.datac(\z80_|reg_file_|b2v_latch_bc_lo|latch [3]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_42~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[3]~48_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[3]~48 .lut_mask = 16'hD0DD;
|
|
defparam \z80_|reg_file_|gdfx_temp0[3]~48 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y11_N4
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~50 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[3]~50_combout = (\z80_|reg_file_|gdfx_temp0[3]~47_combout & (\z80_|reg_file_|gdfx_temp0[3]~49_combout & (\z80_|reg_file_|gdfx_temp0[3]~45_combout & \z80_|reg_file_|gdfx_temp0[3]~48_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|gdfx_temp0[3]~47_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp0[3]~49_combout ),
|
|
.datac(\z80_|reg_file_|gdfx_temp0[3]~45_combout ),
|
|
.datad(\z80_|reg_file_|gdfx_temp0[3]~48_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[3]~50_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[3]~50 .lut_mask = 16'h8000;
|
|
defparam \z80_|reg_file_|gdfx_temp0[3]~50 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y11_N10
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~51 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[3]~51_combout = (\z80_|reg_file_|gdfx_temp0[3]~44_combout & (\z80_|reg_file_|gdfx_temp0[3]~43_combout & \z80_|reg_file_|gdfx_temp0[3]~50_combout ))
|
|
|
|
.dataa(\z80_|reg_file_|gdfx_temp0[3]~44_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp0[3]~43_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|reg_file_|gdfx_temp0[3]~50_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[3]~51_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[3]~51 .lut_mask = 16'h8800;
|
|
defparam \z80_|reg_file_|gdfx_temp0[3]~51 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y11_N14
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp0[3]~52 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp0[3]~52_combout = ((\z80_|reg_file_|gdfx_temp0[3]~51_combout & ((\z80_|reg_file_|db_lo_as[3]~12_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp0[0]~21_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_sw_4u~6_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp0[3]~51_combout ),
|
|
.datac(\z80_|reg_file_|db_lo_as[3]~12_combout ),
|
|
.datad(\z80_|reg_file_|gdfx_temp0[0]~21_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp0[3]~52_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp0[3]~52 .lut_mask = 16'hC4FF;
|
|
defparam \z80_|reg_file_|gdfx_temp0[3]~52 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y15_N20
|
|
cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_35 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[3]~35_combout ) # ((\z80_|execute_|ctl_flags_alu~15_combout & \z80_|alu_|db_low[3]~25_combout )))) # (!\z80_|execute_|ctl_flags_bus~combout
|
|
// & (((\z80_|execute_|ctl_flags_alu~15_combout & \z80_|alu_|db_low[3]~25_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_bus~combout ),
|
|
.datab(\z80_|alu_control_|db[3]~35_combout ),
|
|
.datac(\z80_|execute_|ctl_flags_alu~15_combout ),
|
|
.datad(\z80_|alu_|db_low[3]~25_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .lut_mask = 16'hF888;
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_35 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y19_N24
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~15 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_xy_we~15_combout = (\z80_|execute_|ctl_state_alu~2_combout & ((\z80_|execute_|ctl_ir_we~12_combout ) # ((\z80_|execute_|ctl_alu_op_low~22_combout & \z80_|pla_decode_|Equal56~0_combout )))) #
|
|
// (!\z80_|execute_|ctl_state_alu~2_combout & (\z80_|execute_|ctl_alu_op_low~22_combout & (\z80_|pla_decode_|Equal56~0_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_state_alu~2_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_op_low~22_combout ),
|
|
.datac(\z80_|pla_decode_|Equal56~0_combout ),
|
|
.datad(\z80_|execute_|ctl_ir_we~12_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_xy_we~15_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_xy_we~15 .lut_mask = 16'hEAC0;
|
|
defparam \z80_|execute_|ctl_flags_xy_we~15 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y19_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~16 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_xy_we~16_combout = (\z80_|execute_|ctl_flags_xy_we~15_combout ) # ((\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ) # (!\z80_|execute_|ctl_flags_xy_we~12_combout ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|execute_|ctl_flags_xy_we~15_combout ),
|
|
.datac(\z80_|execute_|ctl_pf_sel_pla12M1T1_12~2_combout ),
|
|
.datad(\z80_|execute_|ctl_flags_xy_we~12_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_xy_we~16_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_xy_we~16 .lut_mask = 16'hFCFF;
|
|
defparam \z80_|execute_|ctl_flags_xy_we~16 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y18_N18
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~17 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_xy_we~17_combout = (\z80_|execute_|ctl_flags_xy_we~16_combout ) # (((!\z80_|execute_|ctl_flags_xy_we~19_combout ) # (!\z80_|execute_|ctl_flags_xy_we~9_combout )) # (!\z80_|execute_|ctl_flags_xy_we~11_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_xy_we~16_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_xy_we~11_combout ),
|
|
.datac(\z80_|execute_|ctl_flags_xy_we~9_combout ),
|
|
.datad(\z80_|execute_|ctl_flags_xy_we~19_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_xy_we~17_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_xy_we~17 .lut_mask = 16'hBFFF;
|
|
defparam \z80_|execute_|ctl_flags_xy_we~17 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y18_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_flags_xy_we~18 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_flags_xy_we~18_combout = ((\z80_|execute_|ctl_flags_xy_we~17_combout ) # ((!\z80_|execute_|ctl_flags_pf_we~4_combout ) # (!\z80_|execute_|ctl_pf_sel[0]~3_combout ))) # (!\z80_|execute_|ctl_flags_sz_we~7_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_sz_we~7_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_xy_we~17_combout ),
|
|
.datac(\z80_|execute_|ctl_pf_sel[0]~3_combout ),
|
|
.datad(\z80_|execute_|ctl_flags_pf_we~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_flags_xy_we~18_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_flags_xy_we~18 .lut_mask = 16'hDFFF;
|
|
defparam \z80_|execute_|ctl_flags_xy_we~18 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X31_Y15_N21
|
|
dffeas \z80_|alu_flags_|flags_xf (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|alu_flags_|SYNTHESIZED_WIRE_35~combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|execute_|ctl_flags_xy_we~18_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|alu_flags_|flags_xf~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|flags_xf .is_wysiwyg = "true";
|
|
defparam \z80_|alu_flags_|flags_xf .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y15_N30
|
|
cycloneive_lcell_comb \z80_|alu_control_|db[3]~33 (
|
|
// Equation(s):
|
|
// \z80_|alu_control_|db[3]~33_combout = (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|alu_flags_|flags_xf~q ) # (!\z80_|execute_|ctl_flags_oe~2_combout )))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ),
|
|
.datac(\z80_|execute_|ctl_flags_oe~2_combout ),
|
|
.datad(\z80_|alu_flags_|flags_xf~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_control_|db[3]~33_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_control_|db[3]~33 .lut_mask = 16'hCC0C;
|
|
defparam \z80_|alu_control_|db[3]~33 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y14_N20
|
|
cycloneive_lcell_comb \z80_|sw1_|db_down[3]~2 (
|
|
// Equation(s):
|
|
// \z80_|sw1_|db_down[3]~2_combout = (\z80_|bus_control_|db[3]~21_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_66_oe~2_combout ),
|
|
.datab(\z80_|execute_|ctl_sw_1d~6_combout ),
|
|
.datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ),
|
|
.datad(\z80_|bus_control_|db[3]~21_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|sw1_|db_down[3]~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|sw1_|db_down[3]~2 .lut_mask = 16'hFFC4;
|
|
defparam \z80_|sw1_|db_down[3]~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y14_N6
|
|
cycloneive_lcell_comb \z80_|alu_control_|db[3]~34 (
|
|
// Equation(s):
|
|
// \z80_|alu_control_|db[3]~34_combout = (\z80_|alu_control_|db[3]~33_combout & (\z80_|sw1_|db_down[3]~2_combout & ((\z80_|reg_file_|gdfx_temp0[3]~52_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|gdfx_temp0[3]~52_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_out_lo~8_combout ),
|
|
.datac(\z80_|alu_control_|db[3]~33_combout ),
|
|
.datad(\z80_|sw1_|db_down[3]~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_control_|db[3]~34_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_control_|db[3]~34 .lut_mask = 16'hB000;
|
|
defparam \z80_|alu_control_|db[3]~34 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y14_N0
|
|
cycloneive_lcell_comb \z80_|alu_control_|db[3]~35 (
|
|
// Equation(s):
|
|
// \z80_|alu_control_|db[3]~35_combout = ((\z80_|alu_control_|db[3]~34_combout & ((\z80_|alu_|db[3]~20_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout )
|
|
|
|
.dataa(\z80_|alu_control_|db[3]~34_combout ),
|
|
.datab(\z80_|execute_|ctl_sw_2u~7_combout ),
|
|
.datac(\z80_|alu_|db[3]~20_combout ),
|
|
.datad(\z80_|alu_control_|db[6]~11_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_control_|db[3]~35_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_control_|db[3]~35 .lut_mask = 16'hA2FF;
|
|
defparam \z80_|alu_control_|db[3]~35 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y8_N16
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~75 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[3][0]~75_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [1]))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [0]),
|
|
.datab(gnd),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [3]),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [1]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[3][0]~75_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[3][0]~75 .lut_mask = 16'h0500;
|
|
defparam \ula_|zx_keyboard_|keys[3][0]~75 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y8_N12
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~0 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|Selector5~0_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[3][0]~75_combout & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6])))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [2]),
|
|
.datab(\ula_|zx_keyboard_|keys[3][0]~75_combout ),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [5]),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [6]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|Selector5~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|Selector5~0 .lut_mask = 16'h0400;
|
|
defparam \ula_|zx_keyboard_|Selector5~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y10_N12
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|Selector5~1 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|Selector5~1_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [2])))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [1]),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [0]),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [3]),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [2]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|Selector5~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|Selector5~1 .lut_mask = 16'h4000;
|
|
defparam \ula_|zx_keyboard_|Selector5~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y8_N8
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~132 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[4][3]~132_combout = (\ula_|zx_keyboard_|Selector5~0_combout ) # ((\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [6] & \ula_|zx_keyboard_|Selector5~1_combout )))
|
|
|
|
.dataa(\ula_|zx_keyboard_|Selector5~0_combout ),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [5]),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [6]),
|
|
.datad(\ula_|zx_keyboard_|Selector5~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[4][3]~132_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[4][3]~132 .lut_mask = 16'hAEAA;
|
|
defparam \ula_|zx_keyboard_|keys[4][3]~132 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y8_N10
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~106 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[4][3]~106_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|WideOr16~2_combout & (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|keys[5][4]~22_combout )))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [6]),
|
|
.datab(\ula_|zx_keyboard_|WideOr16~2_combout ),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [5]),
|
|
.datad(\ula_|zx_keyboard_|keys[5][4]~22_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[4][3]~106_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[4][3]~106 .lut_mask = 16'h8000;
|
|
defparam \ula_|zx_keyboard_|keys[4][3]~106 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y8_N26
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~107 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[4][3]~107_combout = (\ula_|zx_keyboard_|extended~q & (((\ula_|zx_keyboard_|keys[4][3]~106_combout )))) # (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[4][3]~132_combout & (\ula_|ps2_keyboard_|shiftreg [4])))
|
|
|
|
.dataa(\ula_|zx_keyboard_|extended~q ),
|
|
.datab(\ula_|zx_keyboard_|keys[4][3]~132_combout ),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [4]),
|
|
.datad(\ula_|zx_keyboard_|keys[4][3]~106_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[4][3]~107_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[4][3]~107 .lut_mask = 16'hEA40;
|
|
defparam \ula_|zx_keyboard_|keys[4][3]~107 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y8_N4
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~133 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[4][3]~133_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|shifted~q )))
|
|
|
|
.dataa(\ula_|zx_keyboard_|extended~q ),
|
|
.datab(\ula_|zx_keyboard_|released~q ),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [5]),
|
|
.datad(\ula_|zx_keyboard_|shifted~q ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[4][3]~133_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[4][3]~133 .lut_mask = 16'hCDCC;
|
|
defparam \ula_|zx_keyboard_|keys[4][3]~133 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y8_N6
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~108 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[4][3]~108_combout = (\ula_|zx_keyboard_|keys[4][3]~107_combout & ((\ula_|zx_keyboard_|keys[0][0]~13_combout & (!\ula_|zx_keyboard_|keys[4][3]~133_combout )) # (!\ula_|zx_keyboard_|keys[0][0]~13_combout &
|
|
// ((\ula_|zx_keyboard_|keys[4][3]~q ))))) # (!\ula_|zx_keyboard_|keys[4][3]~107_combout & (((\ula_|zx_keyboard_|keys[4][3]~q ))))
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[4][3]~107_combout ),
|
|
.datab(\ula_|zx_keyboard_|keys[4][3]~133_combout ),
|
|
.datac(\ula_|zx_keyboard_|keys[4][3]~q ),
|
|
.datad(\ula_|zx_keyboard_|keys[0][0]~13_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[4][3]~108_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[4][3]~108 .lut_mask = 16'h72F0;
|
|
defparam \ula_|zx_keyboard_|keys[4][3]~108 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X27_Y8_N7
|
|
dffeas \ula_|zx_keyboard_|keys[4][3] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|zx_keyboard_|keys[4][3]~108_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|zx_keyboard_|keys[4][3]~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[4][3] .is_wysiwyg = "true";
|
|
defparam \ula_|zx_keyboard_|keys[4][3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y7_N2
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~104 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[5][3]~104_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [5]))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [3]),
|
|
.datab(gnd),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [0]),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [5]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[5][3]~104_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[5][3]~104 .lut_mask = 16'h0A00;
|
|
defparam \ula_|zx_keyboard_|keys[5][3]~104 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y7_N22
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][3]~105 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[5][3]~105_combout = (\ula_|zx_keyboard_|keys[1][4]~23_combout & ((\ula_|zx_keyboard_|keys[5][3]~104_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[5][3]~104_combout & ((\ula_|zx_keyboard_|keys[5][3]~q
|
|
// ))))) # (!\ula_|zx_keyboard_|keys[1][4]~23_combout & (((\ula_|zx_keyboard_|keys[5][3]~q ))))
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[1][4]~23_combout ),
|
|
.datab(\ula_|zx_keyboard_|released~q ),
|
|
.datac(\ula_|zx_keyboard_|keys[5][3]~q ),
|
|
.datad(\ula_|zx_keyboard_|keys[5][3]~104_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[5][3]~105_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[5][3]~105 .lut_mask = 16'h72F0;
|
|
defparam \ula_|zx_keyboard_|keys[5][3]~105 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X28_Y7_N23
|
|
dffeas \ula_|zx_keyboard_|keys[5][3] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|zx_keyboard_|keys[5][3]~105_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|zx_keyboard_|keys[5][3]~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[5][3] .is_wysiwyg = "true";
|
|
defparam \ula_|zx_keyboard_|keys[5][3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y7_N12
|
|
cycloneive_lcell_comb \D[3]~55 (
|
|
// Equation(s):
|
|
// \D[3]~55_combout = (\z80_|address_pins_|abus[12]~21_combout & (((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][3]~q )))) # (!\z80_|address_pins_|abus[12]~21_combout & (!\ula_|zx_keyboard_|keys[4][3]~q &
|
|
// ((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][3]~q ))))
|
|
|
|
.dataa(\z80_|address_pins_|abus[12]~21_combout ),
|
|
.datab(\ula_|zx_keyboard_|keys[4][3]~q ),
|
|
.datac(\ula_|zx_keyboard_|keys[5][3]~q ),
|
|
.datad(\z80_|address_pins_|abus[13]~20_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[3]~55_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[3]~55 .lut_mask = 16'hBB0B;
|
|
defparam \D[3]~55 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y9_N4
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~46 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[6][4]~46_combout = (\ula_|zx_keyboard_|keys[7][1]~21_combout & (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [5])))
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[7][1]~21_combout ),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [6]),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [3]),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [5]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[6][4]~46_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[6][4]~46 .lut_mask = 16'h0200;
|
|
defparam \ula_|zx_keyboard_|keys[6][4]~46 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y9_N24
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~62 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[5][4]~62_combout = (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [1])
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [0]),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [1]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[5][4]~62_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[5][4]~62 .lut_mask = 16'h00F0;
|
|
defparam \ula_|zx_keyboard_|keys[5][4]~62 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y9_N10
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~102 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[3][3]~102_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[6][4]~46_combout & (\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|keys[5][4]~62_combout )))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [4]),
|
|
.datab(\ula_|zx_keyboard_|keys[6][4]~46_combout ),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [2]),
|
|
.datad(\ula_|zx_keyboard_|keys[5][4]~62_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[3][3]~102_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[3][3]~102 .lut_mask = 16'h4000;
|
|
defparam \ula_|zx_keyboard_|keys[3][3]~102 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y7_N10
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][3]~103 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[3][3]~103_combout = (\ula_|zx_keyboard_|keys[3][3]~102_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][3]~102_combout & ((\ula_|zx_keyboard_|keys[3][3]~q )))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|zx_keyboard_|released~q ),
|
|
.datac(\ula_|zx_keyboard_|keys[3][3]~q ),
|
|
.datad(\ula_|zx_keyboard_|keys[3][3]~102_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[3][3]~103_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[3][3]~103 .lut_mask = 16'h33F0;
|
|
defparam \ula_|zx_keyboard_|keys[3][3]~103 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X28_Y7_N11
|
|
dffeas \ula_|zx_keyboard_|keys[3][3] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|zx_keyboard_|keys[3][3]~103_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|zx_keyboard_|keys[3][3]~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[3][3] .is_wysiwyg = "true";
|
|
defparam \ula_|zx_keyboard_|keys[3][3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y9_N4
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~96 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[0][4]~96_combout = (\ula_|zx_keyboard_|keys[5][1]~34_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [6]))))
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[5][1]~34_combout ),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [5]),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [2]),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [6]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[0][4]~96_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[0][4]~96 .lut_mask = 16'h0208;
|
|
defparam \ula_|zx_keyboard_|keys[0][4]~96 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y9_N18
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~94 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[2][4]~94_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [6]))
|
|
|
|
.dataa(\ula_|zx_keyboard_|shifted~q ),
|
|
.datab(\ula_|zx_keyboard_|released~q ),
|
|
.datac(gnd),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [6]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[2][4]~94_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[2][4]~94 .lut_mask = 16'hDDCC;
|
|
defparam \ula_|zx_keyboard_|keys[2][4]~94 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y9_N8
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~95 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[0][3]~95_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [3] & (!\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [6]))) # (!\ula_|ps2_keyboard_|shiftreg [1] &
|
|
// (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [6])))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [1]),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [3]),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [0]),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [6]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[0][3]~95_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[0][3]~95 .lut_mask = 16'h0810;
|
|
defparam \ula_|zx_keyboard_|keys[0][3]~95 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y9_N18
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][3]~97 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[0][3]~97_combout = (\ula_|zx_keyboard_|keys[0][4]~96_combout & ((\ula_|zx_keyboard_|keys[0][3]~95_combout & (!\ula_|zx_keyboard_|keys[2][4]~94_combout )) # (!\ula_|zx_keyboard_|keys[0][3]~95_combout &
|
|
// ((\ula_|zx_keyboard_|keys[0][3]~q ))))) # (!\ula_|zx_keyboard_|keys[0][4]~96_combout & (((\ula_|zx_keyboard_|keys[0][3]~q ))))
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[0][4]~96_combout ),
|
|
.datab(\ula_|zx_keyboard_|keys[2][4]~94_combout ),
|
|
.datac(\ula_|zx_keyboard_|keys[0][3]~q ),
|
|
.datad(\ula_|zx_keyboard_|keys[0][3]~95_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[0][3]~97_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[0][3]~97 .lut_mask = 16'h72F0;
|
|
defparam \ula_|zx_keyboard_|keys[0][3]~97 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X27_Y9_N19
|
|
dffeas \ula_|zx_keyboard_|keys[0][3] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|zx_keyboard_|keys[0][3]~97_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|zx_keyboard_|keys[0][3]~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[0][3] .is_wysiwyg = "true";
|
|
defparam \ula_|zx_keyboard_|keys[0][3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y7_N6
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~45 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[6][4]~45_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [1]))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [2]),
|
|
.datab(gnd),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [0]),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [1]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[6][4]~45_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[6][4]~45 .lut_mask = 16'h5000;
|
|
defparam \ula_|zx_keyboard_|keys[6][4]~45 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y7_N24
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~92 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[1][3]~92_combout = (\ula_|zx_keyboard_|keys[6][4]~45_combout & (\ula_|zx_keyboard_|keys[7][4]~17_combout & (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [5])))
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[6][4]~45_combout ),
|
|
.datab(\ula_|zx_keyboard_|keys[7][4]~17_combout ),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [4]),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [5]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[1][3]~92_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[1][3]~92 .lut_mask = 16'h0800;
|
|
defparam \ula_|zx_keyboard_|keys[1][3]~92 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y7_N14
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][3]~93 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[1][3]~93_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[1][3]~92_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][3]~92_combout & ((\ula_|zx_keyboard_|keys[1][3]~q ))))) #
|
|
// (!\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[1][3]~q ))))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [3]),
|
|
.datab(\ula_|zx_keyboard_|released~q ),
|
|
.datac(\ula_|zx_keyboard_|keys[1][3]~q ),
|
|
.datad(\ula_|zx_keyboard_|keys[1][3]~92_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[1][3]~93_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[1][3]~93 .lut_mask = 16'h72F0;
|
|
defparam \ula_|zx_keyboard_|keys[1][3]~93 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X28_Y7_N15
|
|
dffeas \ula_|zx_keyboard_|keys[1][3] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|zx_keyboard_|keys[1][3]~93_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|zx_keyboard_|keys[1][3]~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[1][3] .is_wysiwyg = "true";
|
|
defparam \ula_|zx_keyboard_|keys[1][3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y7_N0
|
|
cycloneive_lcell_comb \D[3]~53 (
|
|
// Equation(s):
|
|
// \D[3]~53_combout = (\ula_|zx_keyboard_|keys[0][3]~q & (\z80_|address_pins_|abus[8]~18_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][3]~q )))) # (!\ula_|zx_keyboard_|keys[0][3]~q &
|
|
// (((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][3]~q ))))
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[0][3]~q ),
|
|
.datab(\z80_|address_pins_|abus[8]~18_combout ),
|
|
.datac(\ula_|zx_keyboard_|keys[1][3]~q ),
|
|
.datad(\z80_|address_pins_|abus[9]~17_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[3]~53_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[3]~53 .lut_mask = 16'hDD0D;
|
|
defparam \D[3]~53 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y9_N26
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~99 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[2][3]~99_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [6])) # (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [2] &
|
|
// \ula_|ps2_keyboard_|shiftreg [6]))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [5]),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [2]),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [6]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[2][3]~99_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[2][3]~99 .lut_mask = 16'h03C0;
|
|
defparam \ula_|zx_keyboard_|keys[2][3]~99 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y9_N0
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~100 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[2][3]~100_combout = (\ula_|zx_keyboard_|keys[2][3]~99_combout & (\ula_|zx_keyboard_|keys[5][4]~62_combout & (\ula_|ps2_keyboard_|shiftreg [2] $ (!\ula_|ps2_keyboard_|shiftreg [3]))))
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[2][3]~99_combout ),
|
|
.datab(\ula_|zx_keyboard_|keys[5][4]~62_combout ),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [2]),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [3]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[2][3]~100_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[2][3]~100 .lut_mask = 16'h8008;
|
|
defparam \ula_|zx_keyboard_|keys[2][3]~100 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y9_N2
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~98 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[2][3]~98_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|zx_keyboard_|shifted~q & !\ula_|ps2_keyboard_|shiftreg [2]))
|
|
|
|
.dataa(\ula_|zx_keyboard_|shifted~q ),
|
|
.datab(gnd),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [2]),
|
|
.datad(\ula_|zx_keyboard_|released~q ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[2][3]~98_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[2][3]~98 .lut_mask = 16'hFF05;
|
|
defparam \ula_|zx_keyboard_|keys[2][3]~98 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y9_N8
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][3]~101 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[2][3]~101_combout = (\ula_|zx_keyboard_|keys[5][1]~34_combout & ((\ula_|zx_keyboard_|keys[2][3]~100_combout & ((!\ula_|zx_keyboard_|keys[2][3]~98_combout ))) # (!\ula_|zx_keyboard_|keys[2][3]~100_combout &
|
|
// (\ula_|zx_keyboard_|keys[2][3]~q )))) # (!\ula_|zx_keyboard_|keys[5][1]~34_combout & (((\ula_|zx_keyboard_|keys[2][3]~q ))))
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[5][1]~34_combout ),
|
|
.datab(\ula_|zx_keyboard_|keys[2][3]~100_combout ),
|
|
.datac(\ula_|zx_keyboard_|keys[2][3]~q ),
|
|
.datad(\ula_|zx_keyboard_|keys[2][3]~98_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[2][3]~101_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[2][3]~101 .lut_mask = 16'h70F8;
|
|
defparam \ula_|zx_keyboard_|keys[2][3]~101 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X28_Y9_N9
|
|
dffeas \ula_|zx_keyboard_|keys[2][3] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|zx_keyboard_|keys[2][3]~101_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|zx_keyboard_|keys[2][3]~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[2][3] .is_wysiwyg = "true";
|
|
defparam \ula_|zx_keyboard_|keys[2][3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y7_N2
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~3 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|key_row~3_combout = ((\z80_|address_pins_|DFFE_apin_latch [10]) # (!\ula_|zx_keyboard_|keys[2][3]~q )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )
|
|
|
|
.dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.datab(\z80_|address_pins_|DFFE_apin_latch [10]),
|
|
.datac(gnd),
|
|
.datad(\ula_|zx_keyboard_|keys[2][3]~q ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|key_row~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|key_row~3 .lut_mask = 16'hDDFF;
|
|
defparam \ula_|zx_keyboard_|key_row~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y7_N20
|
|
cycloneive_lcell_comb \D[3]~54 (
|
|
// Equation(s):
|
|
// \D[3]~54_combout = (\D[3]~53_combout & (\ula_|zx_keyboard_|key_row~3_combout & ((\z80_|address_pins_|abus[11]~19_combout ) # (!\ula_|zx_keyboard_|keys[3][3]~q ))))
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[3][3]~q ),
|
|
.datab(\D[3]~53_combout ),
|
|
.datac(\z80_|address_pins_|abus[11]~19_combout ),
|
|
.datad(\ula_|zx_keyboard_|key_row~3_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[3]~54_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[3]~54 .lut_mask = 16'hC400;
|
|
defparam \D[3]~54 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y9_N26
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~109 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[0][4]~109_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|zx_keyboard_|shifted~q & \ula_|ps2_keyboard_|shiftreg [6]))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|zx_keyboard_|shifted~q ),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [6]),
|
|
.datad(\ula_|zx_keyboard_|released~q ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[0][4]~109_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[0][4]~109 .lut_mask = 16'hFFC0;
|
|
defparam \ula_|zx_keyboard_|keys[0][4]~109 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y9_N22
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~60 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[7][2]~60_combout = (\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [6])
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [5]),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [6]),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[7][2]~60_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[7][2]~60 .lut_mask = 16'h0C0C;
|
|
defparam \ula_|zx_keyboard_|keys[7][2]~60 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y9_N20
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~110 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[7][3]~110_combout = (\ula_|zx_keyboard_|WideOr16~2_combout & ((\ula_|zx_keyboard_|keys[7][2]~30_combout ) # ((\ula_|zx_keyboard_|keys[7][2]~60_combout & \ula_|ps2_keyboard_|shiftreg [4]))))
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[7][2]~60_combout ),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [4]),
|
|
.datac(\ula_|zx_keyboard_|WideOr16~2_combout ),
|
|
.datad(\ula_|zx_keyboard_|keys[7][2]~30_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[7][3]~110_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[7][3]~110 .lut_mask = 16'hF080;
|
|
defparam \ula_|zx_keyboard_|keys[7][3]~110 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y9_N2
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~111 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[7][3]~111_combout = (\ula_|zx_keyboard_|keys[0][0]~13_combout & (!\ula_|zx_keyboard_|extended~q & (\ula_|zx_keyboard_|keys[7][3]~110_combout & !\ula_|ps2_keyboard_|shiftreg [2])))
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[0][0]~13_combout ),
|
|
.datab(\ula_|zx_keyboard_|extended~q ),
|
|
.datac(\ula_|zx_keyboard_|keys[7][3]~110_combout ),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [2]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[7][3]~111_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[7][3]~111 .lut_mask = 16'h0020;
|
|
defparam \ula_|zx_keyboard_|keys[7][3]~111 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y9_N14
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][3]~112 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[7][3]~112_combout = (\ula_|zx_keyboard_|keys[7][3]~111_combout & (!\ula_|zx_keyboard_|keys[0][4]~109_combout )) # (!\ula_|zx_keyboard_|keys[7][3]~111_combout & ((\ula_|zx_keyboard_|keys[7][3]~q )))
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[0][4]~109_combout ),
|
|
.datab(gnd),
|
|
.datac(\ula_|zx_keyboard_|keys[7][3]~q ),
|
|
.datad(\ula_|zx_keyboard_|keys[7][3]~111_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[7][3]~112_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[7][3]~112 .lut_mask = 16'h55F0;
|
|
defparam \ula_|zx_keyboard_|keys[7][3]~112 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X29_Y9_N15
|
|
dffeas \ula_|zx_keyboard_|keys[7][3] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|zx_keyboard_|keys[7][3]~112_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|zx_keyboard_|keys[7][3]~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[7][3] .is_wysiwyg = "true";
|
|
defparam \ula_|zx_keyboard_|keys[7][3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y9_N14
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|Selector13~0 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|Selector13~0_combout = (\ula_|zx_keyboard_|released~q ) # ((!\ula_|ps2_keyboard_|shiftreg [5] & \ula_|zx_keyboard_|shifted~q ))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [5]),
|
|
.datab(\ula_|zx_keyboard_|shifted~q ),
|
|
.datac(gnd),
|
|
.datad(\ula_|zx_keyboard_|released~q ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|Selector13~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|Selector13~0 .lut_mask = 16'hFF44;
|
|
defparam \ula_|zx_keyboard_|Selector13~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y9_N12
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~113 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[6][3]~113_combout = (!\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [5] & !\ula_|ps2_keyboard_|shiftreg [2])))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [6]),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [4]),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [5]),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [2]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[6][3]~113_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[6][3]~113 .lut_mask = 16'h0040;
|
|
defparam \ula_|zx_keyboard_|keys[6][3]~113 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y9_N18
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~114 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[6][3]~114_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|zx_keyboard_|keys[6][3]~113_combout )) # (!\ula_|ps2_keyboard_|shiftreg [0] & (((\ula_|ps2_keyboard_|shiftreg [2] & \ula_|zx_keyboard_|keys[7][2]~30_combout ))))
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[6][3]~113_combout ),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [2]),
|
|
.datac(\ula_|zx_keyboard_|keys[7][2]~30_combout ),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [0]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[6][3]~114_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[6][3]~114 .lut_mask = 16'hAAC0;
|
|
defparam \ula_|zx_keyboard_|keys[6][3]~114 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y9_N16
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~135 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[6][3]~135_combout = ((\ula_|zx_keyboard_|extended~q ) # ((!\ula_|zx_keyboard_|keys[6][3]~114_combout ) # (!\ula_|ps2_keyboard_|shiftreg [3]))) # (!\ula_|zx_keyboard_|keys[0][0]~13_combout )
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[0][0]~13_combout ),
|
|
.datab(\ula_|zx_keyboard_|extended~q ),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [3]),
|
|
.datad(\ula_|zx_keyboard_|keys[6][3]~114_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[6][3]~135_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[6][3]~135 .lut_mask = 16'hDFFF;
|
|
defparam \ula_|zx_keyboard_|keys[6][3]~135 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y9_N8
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][3]~136 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[6][3]~136_combout = (\ula_|zx_keyboard_|keys[6][3]~135_combout & (((\ula_|zx_keyboard_|keys[6][3]~q )))) # (!\ula_|zx_keyboard_|keys[6][3]~135_combout & ((\ula_|ps2_keyboard_|shiftreg [1] &
|
|
// (!\ula_|zx_keyboard_|Selector13~0_combout )) # (!\ula_|ps2_keyboard_|shiftreg [1] & ((\ula_|zx_keyboard_|keys[6][3]~q )))))
|
|
|
|
.dataa(\ula_|zx_keyboard_|Selector13~0_combout ),
|
|
.datab(\ula_|zx_keyboard_|keys[6][3]~135_combout ),
|
|
.datac(\ula_|zx_keyboard_|keys[6][3]~q ),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [1]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[6][3]~136_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[6][3]~136 .lut_mask = 16'hD1F0;
|
|
defparam \ula_|zx_keyboard_|keys[6][3]~136 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X29_Y9_N9
|
|
dffeas \ula_|zx_keyboard_|keys[6][3] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|zx_keyboard_|keys[6][3]~136_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|zx_keyboard_|keys[6][3]~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[6][3] .is_wysiwyg = "true";
|
|
defparam \ula_|zx_keyboard_|keys[6][3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y9_N30
|
|
cycloneive_lcell_comb \D[3]~56 (
|
|
// Equation(s):
|
|
// \D[3]~56_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\z80_|address_pins_|abus[15]~22_combout )) # (!\ula_|zx_keyboard_|keys[7][3]~q ))) # (!\z80_|address_pins_|abus[14]~23_combout & (!\ula_|zx_keyboard_|keys[6][3]~q &
|
|
// ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][3]~q ))))
|
|
|
|
.dataa(\z80_|address_pins_|abus[14]~23_combout ),
|
|
.datab(\ula_|zx_keyboard_|keys[7][3]~q ),
|
|
.datac(\ula_|zx_keyboard_|keys[6][3]~q ),
|
|
.datad(\z80_|address_pins_|abus[15]~22_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[3]~56_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[3]~56 .lut_mask = 16'hAF23;
|
|
defparam \D[3]~56 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y7_N30
|
|
cycloneive_lcell_comb \D[3]~57 (
|
|
// Equation(s):
|
|
// \D[3]~57_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[3]~55_combout & (\D[3]~54_combout & \D[3]~56_combout )))
|
|
|
|
.dataa(\D[3]~55_combout ),
|
|
.datab(\D[3]~54_combout ),
|
|
.datac(\z80_|address_pins_|abus[0]~16_combout ),
|
|
.datad(\D[3]~56_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[3]~57_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[3]~57 .lut_mask = 16'hF8F0;
|
|
defparam \D[3]~57 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X33_Y14_N0
|
|
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a27 (
|
|
.portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[3]~74_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a27_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .clk0_core_clock_enable = "ena0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .data_interleave_width_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .init_file = "led_patterns.mif";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .init_file_layout = "port_a";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .operation_mode = "single_port";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_address_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_byte_enable_clock = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_out_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_out_clock = "clock0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_first_address = 0;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_first_bit_number = 3;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_last_address = 8191;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_logical_ram_depth = 32768;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_logical_ram_width = 8;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_b_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .port_b_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .ram_block_type = "M9K";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a27 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X22_Y14_N0
|
|
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a3 (
|
|
.portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[3]~74_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file = "led_patterns.mif";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "single_port";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 32768;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018;
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X22_Y13_N0
|
|
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a19 (
|
|
.portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[3]~74_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a19_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .clk0_core_clock_enable = "ena0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .data_interleave_width_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file = "led_patterns.mif";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .init_file_layout = "port_a";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .operation_mode = "single_port";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_byte_enable_clock = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_out_clock = "clock0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_address = 0;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_first_bit_number = 3;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_last_address = 8191;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_depth = 32768;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_logical_ram_width = 8;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .port_b_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .ram_block_type = "M9K";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a19 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y14_N26
|
|
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 (
|
|
// Equation(s):
|
|
// \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) #
|
|
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ))) #
|
|
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ))))
|
|
|
|
.dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
|
|
.datab(\ram1|altsyncram_component|auto_generated|ram_block1a3~portadataout ),
|
|
.datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]),
|
|
.datad(\ram1|altsyncram_component|auto_generated|ram_block1a19~portadataout ),
|
|
.cin(gnd),
|
|
.combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 .lut_mask = 16'hF4A4;
|
|
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X22_Y16_N0
|
|
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a11 (
|
|
.portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[3]~74_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file = "led_patterns.mif";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "single_port";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 32768;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y14_N22
|
|
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 (
|
|
// Equation(s):
|
|
// \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout &
|
|
// (\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ))))) #
|
|
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ))))
|
|
|
|
.dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
|
|
.datab(\ram1|altsyncram_component|auto_generated|ram_block1a27~portadataout ),
|
|
.datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~6_combout ),
|
|
.datad(\ram1|altsyncram_component|auto_generated|ram_block1a11~portadataout ),
|
|
.cin(gnd),
|
|
.combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 .lut_mask = 16'hDAD0;
|
|
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X22_Y20_N0
|
|
cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a3 (
|
|
.portawe(vcc),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(!\z80_|address_pins_|abus[13]~20_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain(1'b0),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\rom|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file = "./rom/gw03.hex";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "rom";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock0";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_a_write_enable_clock = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h7BBD7F79FFE0AB8FC33758D1C1145DDD6311CF69FFFDF62EDD236FC6A0358FA2B4B15EB89456517DFF58F68BDADB95B5F764CAE7E7C7E7D70CADB8FFD8F9A72BFBB9EB400590D7F939FF5A70A29817DC2CC29B679B2D7146BD21D47EF06F7D5EAF72F66DC666B0726D66FD941AD9BC6D758D5EC24DFEBA64871D6B86D37DF1DFBFF05FBD6AD8CA62C6CBE43BDBFD99E9EB6DD724D235FBEA9FE7D6767D811C40681A00AF8D864D8BB6D2A0916C8A93250A76B8A977F82E8FDFBE68F8E0F8DF237CA976FE488D1069D687A6F1D68A70F37CAAA367A74CBB75D3A6FFB4B1E8D4B7F7F22D2FE1509BDF80E6DD7B717D7E9C6531C3A86BE9F1D7A6AFD5BFB7A37A60;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h8AB3B7FDEE7B9CC735FCCE93E3AC1AAAA691AD6350E57F1F5773302B6F36F63D130E0574D6BB44B2C0D7A907702A748D0BA50F8FA5437ACD3B343C35039F44D19CD4E55E6CB00410842B02A7FD105706DF9E2A1FA025005632A0CC080400D280CCCA0665222D038CC873351A21B23939A98CC08803282189C8440D40CD40462421A40982C046D22C10146484345CAF7BC828BFE79DFBE3C631CBF660C487EBB759BD7F8DE9E0F27A65DE5245BEB8F7829C36F0D136168F97C2BD77D649A39EB4DDB3A42AC80797FDEF4DE3EEF7ED8C7307E4CE6A6317F7BF25D077BBF03AEA3363B065F7D671322D6BFB2B8759433929CEC27E3FD7741292A4A5AF02703CC4E3;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'hFD5CB07B6C729B510A78BEC5F7C7A1E7809F1976D0DD3615C1D27D2DF596BFE7A8BCDC2E6655185CC45008B39EFD1FA6E9F5E816114F93E1E7A2A27C72C7349F3497229CB9044B6E7A7861A04A712AAF29EFBD393727F1F3FC2AA1E6CF571457F0A09C47F23F20FE2AABF5FD3ABE6167E5FD36E1D9735BBD5375C1F79BD0424ECF133BF47B9D3DA46DD6DBF3A8ADCDD3DF1176D2FE23447DFC65E1DD7BF3BE5E1C9DCD8EBB9D36AF570CF25CDD16F645D1DE9F9EE575E3A2B91D5659FC131CE3DCD4560015805B13AC0290001EF8261B7E4EB867C828D9777FFF47B6903008DDD7D77EF5E2C6D7220BE64B3C6E9EF22AFDFCC8005C2FFFFA3AB9AD1ADFC0AFE7;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h06ABC52D5DBEF57EEB3311A9D85D253B44E250E1566BED57C6DBEB2ABFD1ADF6FF4DEBFBDEB376DF68D5EEDB5EB4D5AB5B79745D76CD8ADC59CB30C8AA33E1551D2FCA8DCB43C5356BAE638588C302868CE1161CACADFEF7696F8C3AA82EC16F47A8EA413A2DCF09B996582318DBF3C4711871B3BC0404EC45252A485234A663C1FFFB3487617BE24FD79501DE05F1A341B89EC82FD5702497FD866639C0DE08B383E6E7C3B310E1F7FF595C5DF6F0E9A9FFFBE16D3FFBE82C1E0051F1E060D500812F408CC6501331852531B04480021D9220D4903A41404312032840153FE9CC8070206B8245AC240020752EBC2BEF3E74AB288F360C239C4AFAE93F68775A;
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X22_Y32_N0
|
|
cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a11 (
|
|
.portawe(vcc),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(\z80_|address_pins_|abus[13]~20_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain(1'b0),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\rom|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file = "./rom/gw03.hex";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "rom";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock0";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_a_write_enable_clock = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'hA504087E764CA02840304044540424244404044024804008A40A54484448544A800400207E4A0818204040024A1262124210084014407E08520A4A42424A1256522828280000524A124A4A7E4A527E4A106010607C38003C025408FE2400000087857B4051593F8FEF8A4F84E99E6FCC30DBEF9DDB582A41325A97B1EEE4166FF390FF8420BD829D1679F5F18B57EAB9C5CFBE75ECF7F3730C105ADF74BA7D7F9159D64BD7F217C1803F5B1169B463FF6C6EC899D6482FBA8E6B53DCF12F3BFFBE72266D55B4E9E5887FAF8840007C50220105C908100BAF6FBA7BF97E6E020792ADFDFBD96CFD77B36CF30CC5DE43A85FB6F0020203478F160F42F9A061FE44;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h812017671773A9EE08641F818054455F0BABE232D2AA00081423C0BCCE1E642C4B7AE34419240F3C0170E001D6CE75F0475D5A8A9012B9BD97153AB038EF6187776B42A5FE80BB5AAA2A550A58904A1C6DC992952AB4532C6CB2F975BC101356F70811E17D8C73F1D9BEF7F7E82EFAE6C2D2DB2126004D81CA67DACC344F6458C165510222E12BABC9B940EB70182EDBEEF007365AA980A2002829A05282A2AAAA8AAA32A2C38012BFEB492278CD27651FD91BDE452EEF054801275AA0D49D9A896B7EB5FD69B679669CBA00AA9A431956A3CE676A9D7B50D84F3FFFFFC4AAF735995E3ADF9E07EB861E3035B1EF3EF935DAFFFA1F94FDCA5B803F14101BE318;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'hCE21FFE0D222852612C7A87E8DFE961BD8CF052D4757559DF3ED2417472384AF04FF86DDFE9FCBD3DC2A4967F492CDD5A8FFBD9857306D8B07F3AD96A6138C0360BE688D11B16D7936F4B55E0E301BAD6A96802B5719271D55D5E93FED5335EF86E8AEC1EE37F6F5FFD77F204F5EBFDA614C41C1F85C32FFB05F2881BF7EB1D73DDBF48E39F1AE9FC0A7CAC2B4515882877D84D415C7A00D91E87F57E95B60EFEB9963425C951C00298F26A884C3AEF0DBF539D04E867EB6FB957E817C230DFEE3BE607B3FAC5DD39FB436C5BB7926D7FFF03EF787FF563C3FEF787919A8383DEF3142B9927BEAF99BCFB066319F5BDF2EFFB11686607A73BE9CB85CF6EC52D0;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h420539B476E305B8200E47DFAAE8D5D1D0724DCC3FD72C4F8DE54622A1DD1BA78CA3CE9F24BEFA9E2BB9D89B423C327C8E050114401A62FDCD2054E166C0005F7941B61372AC884EE60A372057B59CFF30A6020B875C06E7C5FBDF9A91F8F0588ED67F67AA66B0674CD240410F613700B8DFE7F8837F88FF4520002E4BFD7FA2768008002000002624793100811F43BC315A6004052671392B47FEB7F5DC90E62175C7B8FC48FCC916D46F9315DFDECBE43E5F03D7D27F97E09E4700AA694552A1FF3BE5E159FFDDEB2FBECAEB87BBCC5FCF6E23D77E4DD4C9DEBC93C10F636326FAFE3BE30DFAF7B9E7A5FFE44BF314DAA1C1529CDBFFE9D94EB11A9F68D4DF;
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X22_Y22_N0
|
|
cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a11 (
|
|
.portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\CLOCK_50~inputclkctrl_outclk ),
|
|
.clk1(\CLOCK_50~inputclkctrl_outclk ),
|
|
.ena0(\z80_|address_pins_|abus[13]~20_combout ),
|
|
.ena1(gnd),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[3]~74_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain({\~GND~combout }),
|
|
.portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4],
|
|
\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a11_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .clk0_core_clock_enable = "ena0";
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defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .clk1_core_clock_enable = "ena1";
|
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defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .data_interleave_width_in_bits = 1;
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defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .init_file = "ula/test_scr.hex";
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defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .init_file_layout = "port_a";
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defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mixed_port_feed_through_mode = "dont_care";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .operation_mode = "bidir_dual_port";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_address_width = 13;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_byte_enable_clock = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_out_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_data_width = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_address = 0;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_first_bit_number = 3;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_last_address = 8191;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_depth = 16384;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_logical_ram_width = 8;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_address_width = 13;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_in_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_out_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_out_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_data_width = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_first_address = 0;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_first_bit_number = 3;
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|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_last_address = 8191;
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defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_logical_ram_depth = 16384;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_logical_ram_width = 8;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_read_enable_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .port_b_write_enable_clock = "clock1";
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|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .ram_block_type = "M9K";
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defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
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|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
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|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a11 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
// synopsys translate_on
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|
|
|
// Location: M9K_X22_Y30_N0
|
|
cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a3 (
|
|
.portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\CLOCK_50~inputclkctrl_outclk ),
|
|
.clk1(\CLOCK_50~inputclkctrl_outclk ),
|
|
.ena0(!\z80_|address_pins_|abus[13]~20_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[3]~74_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain({\~GND~combout }),
|
|
.portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4],
|
|
\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTADATAOUT_bus ),
|
|
.portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a3_PORTBDATAOUT_bus ));
|
|
// synopsys translate_off
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .clk0_core_clock_enable = "ena0";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .data_interleave_width_in_bits = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file = "ula/test_scr.hex";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .init_file_layout = "port_a";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mixed_port_feed_through_mode = "dont_care";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .operation_mode = "bidir_dual_port";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_address_width = 13;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_byte_enable_clock = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_out_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_data_width = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_address = 0;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_first_bit_number = 3;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_last_address = 8191;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_depth = 16384;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_logical_ram_width = 8;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_address_width = 13;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_in_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_out_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_data_width = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_address = 0;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_first_bit_number = 3;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_last_address = 8191;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_depth = 16384;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_logical_ram_width = 8;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_read_enable_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .port_b_write_enable_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .ram_block_type = "M9K";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init3 = 2048'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000E00000000000000000010000F0000000FF000000FF804001FF804001FFE00002FFF00802FFF03803FFF0F003FFF07003FFF83003FFFC6003FFFC0003F1FE0003FCFF8000000000000000000;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040A784000B4B14FE9289D000000000000000000000000FFFFFFFF00000000000408985EC2BFD15FE969DD000000000000000000000000000000003FFFFFFE40041C994CE2A7815FE94999000000000000000000000000000000007FFFFFFF400401895AC288C14FE949DD0000000000000000000000007FFFFFFE40000003400401A95EE2AAD15FE90BC50000000000000000000000007FFFFFFE4000000140040F69400223795FE963C1000000000000000000000000400000003FFFFFFC5FE40E795BE33D3940014361000000000000000000000000000000003FFFFFFC5FE420395FE3081940090369;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init1 = 2048'h5FE8234948F016F55FF8A5910C281BC040DE8DE1780599C168543F41725B3AC15FE8236548F006C15FE8B14108A816C040088FE179C59FC1699632C1537F1A8140082365487017C55FE8A1D5488802C148208FE179C499C16B9637C1533F08F1400813E9482817C55FE892C1480812414BC48DE159D48EC16BB62791530F00E1400812F1482807815FE89BD1488002D149449F69495C394160663E81523313E9400882FD480807C15CE88AC149E037C149949FC14B4C3941606E5F81423304A1400082FD480017C11C088A8041600FE1499C9CC16A4C39C1630D1D81024345D0400896FD580807C11C088A9041D40DE149CC9DC16854394163315D81026300D0;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a3 .mem_init0 = 2048'h022388704B6887014BD84185680166815764AC0148D308813FFFFFFC0000000003228A304BA085014BFC40816C0166915375AC0140D308013FFFFFFC40000000432289294EB08F014A1C40816C016681537DA80140D10E01400000017FFFFFFE406281154FB08D014A0040894C016299437DB00140D10F01400000037FFFFFFE4062A13149A88D814BE0429146016EA14179B001405107017FFFFFFF0000000043E0812549C889814BE0528146016C814179924140511F413FFFFFFE0000000043E881314EE881814A00468147436C814159100100513F0000000000FFFFFFFF4B6883014EA881814800668147C22C814019900100003E0000000000FFFFFFFF;
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y14_N24
|
|
cycloneive_lcell_comb \Selector3~1 (
|
|
// Equation(s):
|
|
// \Selector3~1_combout = (\Selector3~0_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout )) # (!\z80_|address_pins_|abus[14]~23_combout ))) # (!\Selector3~0_combout & (\z80_|address_pins_|abus[14]~23_combout &
|
|
// ((\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ))))
|
|
|
|
.dataa(\Selector3~0_combout ),
|
|
.datab(\z80_|address_pins_|abus[14]~23_combout ),
|
|
.datac(\ram0|altsyncram_component|auto_generated|ram_block1a11~portadataout ),
|
|
.datad(\ram0|altsyncram_component|auto_generated|ram_block1a3~portadataout ),
|
|
.cin(gnd),
|
|
.combout(\Selector3~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \Selector3~1 .lut_mask = 16'hE6A2;
|
|
defparam \Selector3~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y14_N16
|
|
cycloneive_lcell_comb \Selector3~2 (
|
|
// Equation(s):
|
|
// \Selector3~2_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\Selector3~1_combout )))) # (!\z80_|address_pins_|abus[14]~23_combout & ((\Selector3~1_combout & ((\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ))) #
|
|
// (!\Selector3~1_combout & (\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ))))
|
|
|
|
.dataa(\rom|altsyncram_component|auto_generated|ram_block1a3~portadataout ),
|
|
.datab(\z80_|address_pins_|abus[14]~23_combout ),
|
|
.datac(\rom|altsyncram_component|auto_generated|ram_block1a11~portadataout ),
|
|
.datad(\Selector3~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\Selector3~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \Selector3~2 .lut_mask = 16'hFC22;
|
|
defparam \Selector3~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y14_N10
|
|
cycloneive_lcell_comb \D[3]~85 (
|
|
// Equation(s):
|
|
// \D[3]~85_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\Selector3~2_combout
|
|
// ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ))))
|
|
|
|
.dataa(\z80_|address_pins_|DFFE_apin_latch [15]),
|
|
.datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[3]~7_combout ),
|
|
.datad(\Selector3~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[3]~85_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[3]~85 .lut_mask = 16'hF4B0;
|
|
defparam \D[3]~85 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y14_N2
|
|
cycloneive_lcell_comb \D[3]~73 (
|
|
// Equation(s):
|
|
// \D[3]~73_combout = ((\Equal2~0_combout & (\D[3]~57_combout )) # (!\Equal2~0_combout & ((\D[3]~85_combout )))) # (!\Equal2~1_combout )
|
|
|
|
.dataa(\D[3]~57_combout ),
|
|
.datab(\Equal2~1_combout ),
|
|
.datac(\Equal2~0_combout ),
|
|
.datad(\D[3]~85_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[3]~73_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[3]~73 .lut_mask = 16'hBFB3;
|
|
defparam \D[3]~73 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y14_N8
|
|
cycloneive_lcell_comb \D[3]~74 (
|
|
// Equation(s):
|
|
// \D[3]~74_combout = (\z80_|pin_control_|bus_db_pin_oe~15_combout & (\z80_|data_pins_|dout [3] & ((\D[3]~73_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\D[3]~73_combout ) # (!\Equal2~1_combout ))))
|
|
|
|
.dataa(\z80_|data_pins_|dout [3]),
|
|
.datab(\Equal2~1_combout ),
|
|
.datac(\z80_|pin_control_|bus_db_pin_oe~15_combout ),
|
|
.datad(\D[3]~73_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[3]~74_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[3]~74 .lut_mask = 16'hAF03;
|
|
defparam \D[3]~74 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y13_N16
|
|
cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] (
|
|
// Equation(s):
|
|
// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [3] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[3]~21_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[3]~74_combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout &
|
|
// (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[3]~74_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_bus_db_we~7_combout ),
|
|
.datab(\z80_|pin_control_|bus_db_pin_re~combout ),
|
|
.datac(\z80_|bus_control_|db[3]~21_combout ),
|
|
.datad(\D[3]~74_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .lut_mask = 16'hECA0;
|
|
defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[3] .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X30_Y13_N17
|
|
dffeas \z80_|data_pins_|dout[3] (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [3]),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|data_pins_|dout [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|data_pins_|dout[3] .is_wysiwyg = "true";
|
|
defparam \z80_|data_pins_|dout[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y13_N20
|
|
cycloneive_lcell_comb \z80_|bus_control_|db[3]~20 (
|
|
// Equation(s):
|
|
// \z80_|bus_control_|db[3]~20_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [3]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|bus_control_|db[0]~4_combout ),
|
|
.datac(\z80_|execute_|ctl_bus_db_oe~combout ),
|
|
.datad(\z80_|data_pins_|dout [3]),
|
|
.cin(gnd),
|
|
.combout(\z80_|bus_control_|db[3]~20_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|bus_control_|db[3]~20 .lut_mask = 16'hCC0C;
|
|
defparam \z80_|bus_control_|db[3]~20 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y17_N30
|
|
cycloneive_lcell_comb \z80_|bus_control_|db[3]~21 (
|
|
// Equation(s):
|
|
// \z80_|bus_control_|db[3]~21_combout = ((\z80_|bus_control_|db[3]~20_combout & ((\z80_|alu_control_|db[3]~35_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout )
|
|
|
|
.dataa(\z80_|bus_control_|db[0]~6_combout ),
|
|
.datab(\z80_|alu_control_|db[3]~35_combout ),
|
|
.datac(\z80_|bus_control_|db[3]~20_combout ),
|
|
.datad(\z80_|execute_|ctl_bus_db_we~7_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|bus_control_|db[3]~21_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|bus_control_|db[3]~21 .lut_mask = 16'hD5F5;
|
|
defparam \z80_|bus_control_|db[3]~21 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y17_N12
|
|
cycloneive_lcell_comb \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 (
|
|
// Equation(s):
|
|
// \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout = (\z80_|bus_control_|db[4]~19_combout & \z80_|bus_control_|db[3]~21_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|bus_control_|db[4]~19_combout ),
|
|
.datac(\z80_|bus_control_|db[3]~21_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .lut_mask = 16'hC0C0;
|
|
defparam \z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X30_Y17_N13
|
|
dffeas \z80_|interrupts_|im2 (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2_combout ),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|execute_|ctl_im_we~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|interrupts_|im2~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|interrupts_|im2 .is_wysiwyg = "true";
|
|
defparam \z80_|interrupts_|im2 .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y13_N2
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_mRead~10 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mRead~10_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|interrupts_|im2~q & \z80_|interrupts_|DFFE_inst44~q ))
|
|
|
|
.dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ),
|
|
.datab(\z80_|interrupts_|im2~q ),
|
|
.datac(\z80_|interrupts_|DFFE_inst44~q ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mRead~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mRead~10 .lut_mask = 16'h4040;
|
|
defparam \z80_|execute_|ctl_mRead~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y13_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_sw_mask543_en~0 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_sw_mask543_en~0_combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|execute_|ctl_mRead~10_combout & (\z80_|pla_decode_|Equal47~0_combout & \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout )))
|
|
|
|
.dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ),
|
|
.datab(\z80_|execute_|ctl_mRead~10_combout ),
|
|
.datac(\z80_|pla_decode_|Equal47~0_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_sw_mask543_en~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_sw_mask543_en~0 .lut_mask = 16'h1000;
|
|
defparam \z80_|execute_|ctl_sw_mask543_en~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y14_N24
|
|
cycloneive_lcell_comb \z80_|alu_control_|db[7]~16 (
|
|
// Equation(s):
|
|
// \z80_|alu_control_|db[7]~16_combout = (\z80_|alu_flags_|DFFE_inst_latch_sf~q & (!\z80_|alu_|db[7]~12_combout & ((\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_flags_|DFFE_inst_latch_sf~q & ((\z80_|execute_|ctl_flags_oe~2_combout ) #
|
|
// ((!\z80_|alu_|db[7]~12_combout & \z80_|execute_|ctl_sw_2u~7_combout ))))
|
|
|
|
.dataa(\z80_|alu_flags_|DFFE_inst_latch_sf~q ),
|
|
.datab(\z80_|alu_|db[7]~12_combout ),
|
|
.datac(\z80_|execute_|ctl_flags_oe~2_combout ),
|
|
.datad(\z80_|execute_|ctl_sw_2u~7_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_control_|db[7]~16_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_control_|db[7]~16 .lut_mask = 16'h7350;
|
|
defparam \z80_|alu_control_|db[7]~16 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y14_N6
|
|
cycloneive_lcell_comb \z80_|alu_control_|db[7]~17 (
|
|
// Equation(s):
|
|
// \z80_|alu_control_|db[7]~17_combout = (!\z80_|alu_control_|db[7]~16_combout & (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout & ((\z80_|reg_file_|gdfx_temp0[7]~91_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|gdfx_temp0[7]~91_combout ),
|
|
.datab(\z80_|alu_control_|db[7]~16_combout ),
|
|
.datac(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_out_lo~8_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_control_|db[7]~17_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_control_|db[7]~17 .lut_mask = 16'h2030;
|
|
defparam \z80_|alu_control_|db[7]~17 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y14_N12
|
|
cycloneive_lcell_comb \z80_|alu_control_|db[7]~18 (
|
|
// Equation(s):
|
|
// \z80_|alu_control_|db[7]~18_combout = (\z80_|alu_control_|db[7]~17_combout & (((!\z80_|execute_|ctl_sw_mask543_en~0_combout & \z80_|bus_control_|db[7]~7_combout )) # (!\z80_|execute_|ctl_sw_1d~7_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_sw_mask543_en~0_combout ),
|
|
.datab(\z80_|bus_control_|db[7]~7_combout ),
|
|
.datac(\z80_|execute_|ctl_sw_1d~7_combout ),
|
|
.datad(\z80_|alu_control_|db[7]~17_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_control_|db[7]~18_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_control_|db[7]~18 .lut_mask = 16'h4F00;
|
|
defparam \z80_|alu_control_|db[7]~18 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y14_N26
|
|
cycloneive_lcell_comb \z80_|alu_control_|db[7]~19 (
|
|
// Equation(s):
|
|
// \z80_|alu_control_|db[7]~19_combout = (\z80_|alu_control_|db[7]~18_combout ) # (!\z80_|alu_control_|db[6]~11_combout )
|
|
|
|
.dataa(\z80_|alu_control_|db[7]~18_combout ),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|alu_control_|db[6]~11_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_control_|db[7]~19_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_control_|db[7]~19 .lut_mask = 16'hAAFF;
|
|
defparam \z80_|alu_control_|db[7]~19 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y13_N28
|
|
cycloneive_lcell_comb \z80_|bus_control_|db[7]~5 (
|
|
// Equation(s):
|
|
// \z80_|bus_control_|db[7]~5_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[7]~19_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_bus_db_we~7_combout ),
|
|
.datab(\z80_|bus_control_|db[0]~4_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|alu_control_|db[7]~19_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|bus_control_|db[7]~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|bus_control_|db[7]~5 .lut_mask = 16'hCC44;
|
|
defparam \z80_|bus_control_|db[7]~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y11_N2
|
|
cycloneive_lcell_comb \D[5]~67 (
|
|
// Equation(s):
|
|
// \D[5]~67_combout = (!\z80_|memory_ifc_|nIORQ_out~0_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\z80_|memory_ifc_|nRD_out~2_combout & !\z80_|memory_ifc_|nWR_out~0_combout )))
|
|
|
|
.dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ),
|
|
.datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.datac(\z80_|memory_ifc_|nRD_out~2_combout ),
|
|
.datad(\z80_|memory_ifc_|nWR_out~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[5]~67_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[5]~67 .lut_mask = 16'h0040;
|
|
defparam \D[5]~67 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X33_Y21_N0
|
|
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a7 (
|
|
.portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[7]~80_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file = "led_patterns.mif";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "single_port";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 32768;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081;
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X33_Y20_N0
|
|
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a23 (
|
|
.portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[7]~80_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a23_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .clk0_core_clock_enable = "ena0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .data_interleave_width_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file = "led_patterns.mif";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .init_file_layout = "port_a";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .operation_mode = "single_port";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_byte_enable_clock = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_out_clock = "clock0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_address = 0;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_first_bit_number = 7;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_last_address = 8191;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_depth = 32768;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_logical_ram_width = 8;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .port_b_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .ram_block_type = "M9K";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a23 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y21_N10
|
|
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14 (
|
|
// Equation(s):
|
|
// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ) #
|
|
// (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout &
|
|
// ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]))))
|
|
|
|
.dataa(\ram1|altsyncram_component|auto_generated|ram_block1a7~portadataout ),
|
|
.datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]),
|
|
.datac(\ram1|altsyncram_component|auto_generated|ram_block1a23~portadataout ),
|
|
.datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
|
|
.cin(gnd),
|
|
.combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14 .lut_mask = 16'hCCE2;
|
|
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X33_Y18_N0
|
|
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a31 (
|
|
.portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[7]~80_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a31_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .clk0_core_clock_enable = "ena0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .data_interleave_width_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file = "led_patterns.mif";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .init_file_layout = "port_a";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .operation_mode = "single_port";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_byte_enable_clock = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_out_clock = "clock0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_address = 0;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_first_bit_number = 7;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_last_address = 8191;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_depth = 32768;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_logical_ram_width = 8;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .port_b_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .ram_block_type = "M9K";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a31 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X33_Y16_N0
|
|
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a15 (
|
|
.portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[7]~80_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file = "led_patterns.mif";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "single_port";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 32768;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y21_N24
|
|
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15 (
|
|
// Equation(s):
|
|
// \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ) #
|
|
// ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] &
|
|
// \ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ))))
|
|
|
|
.dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~14_combout ),
|
|
.datab(\ram1|altsyncram_component|auto_generated|ram_block1a31~portadataout ),
|
|
.datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
|
|
.datad(\ram1|altsyncram_component|auto_generated|ram_block1a15~portadataout ),
|
|
.cin(gnd),
|
|
.combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15 .lut_mask = 16'hDA8A;
|
|
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X33_Y29_N0
|
|
cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a15 (
|
|
.portawe(vcc),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(\z80_|address_pins_|abus[13]~20_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain(1'b0),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\rom|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file = "./rom/gw03.hex";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "rom";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock0";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_a_write_enable_clock = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h3C0000000000000000000000000000000000000000000000000000000000000080000000000002000000000200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFB91060128E2D09899B4D10A148392808351AD282E76190E029FDC286449331D89080802222C0D04D1121484041D21084C223B0A12EBE72083D81421B93CA9589A04864A853089602E536320C2A5944831907110C246020089C76EE701A4E23964C6586008731635460418000008202040C300110000FCE7E12403749F8C6AB8F69167210EF8A4B8228710884C5C47A9986E8840C02862C088C36E19CF1D315;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h03020CCE064769B15020A6030880234C64E9BEF8E98A81489083A026140D648906E5AD6C882882990A40D293FED064710CB226CDA0330D7B189B344442EC35E3763C75FA1DB107B865E5B8F7B95E77F222244C6BDC1879C0562EF779BE0009465775469089F04C623E19317B486F653C1C22CA642CD685C10EE47EDD66C8C226C7C57F084106FB3B8B1E47463C0088D11104F23C180222A0AA22A22882A202A00000000288964258156302504F5F660C054DEDCA20CC201A4074192601E376C9596CD8B4B568A4DFEF3DBF8027A3422A56A2C003E514582104BF8D6B5D80BB397FBBEC46E8B3CAEBE0100275A1092081D0C1E5716DF09CFEEC00AD800529E1A8;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h873CB568FC3F09080F4400DAC600092017210911A6081DCC4979244124815884AE6302C4BE6BA8C22A084803225A0855ABBBC528B1CA2456A4951A53C1209153CFC3000F43632B49C39723270C604B184D1940F1B2A04459BEB088666843BB38C23A8D170CED981891256A2C1D9B31C0F040202103900E6765976089DB8DE16E0001022EC10015E263787F7E581EF83F062200C626EC4E19021840D9C112400C4B987A78AE1BF80005EF370C0739371E0D3E5CF1E3677332370BB98D1831B30F7D8CDC0131C444798F040DC0116E2C4336B0166109A15D1FCC7EDE31EB23862203C11245EE31E38E6DEF2188BE2068F3C716E10317783020D8EF5C256774BA0E;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h1B9CE2DA363196DC20007FF5554FC631286DC716B048384C26510685218DF9E6C629E6050C619658692170C1022C2232C965C92C189020C705873084858910322166D72DC524870C422BBFFD4808A7032B088DE3000B853800736C8E9968C19A4B72C08871D2413188E4829219C38C2025920480D64856902E4D4D60B640C833C14D536A45D144B244C24A290076E58CC2E64E4A2DC4C5939C4C2DDBD1B918B231248625B2C0DD0F07A27A111CB80A48808C7C21C205029100010400228BB3BDFF7DCCEF40196C8381658D8840043B119B86A46247665810E2203000141023C366CB633B3376DC625DA8A0856C484392B779E1BA4088EDB4A6CDB9BD46DCC0B2;
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X33_Y23_N0
|
|
cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a15 (
|
|
.portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\CLOCK_50~inputclkctrl_outclk ),
|
|
.clk1(\CLOCK_50~inputclkctrl_outclk ),
|
|
.ena0(\z80_|address_pins_|abus[13]~20_combout ),
|
|
.ena1(gnd),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[7]~80_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain({\~GND~combout }),
|
|
.portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4],
|
|
\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a15_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk0_core_clock_enable = "ena0";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .clk1_core_clock_enable = "ena1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .data_interleave_width_in_bits = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file = "ula/test_scr.hex";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .init_file_layout = "port_a";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mixed_port_feed_through_mode = "dont_care";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .operation_mode = "bidir_dual_port";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_address_width = 13;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_byte_enable_clock = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_out_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_data_width = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_address = 0;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_first_bit_number = 7;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_last_address = 8191;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_depth = 16384;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_logical_ram_width = 8;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_address_width = 13;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_in_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_out_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_data_width = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_address = 0;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_first_bit_number = 7;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_last_address = 8191;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_depth = 16384;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_logical_ram_width = 8;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_read_enable_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .port_b_write_enable_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .ram_block_type = "M9K";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a15 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X33_Y24_N0
|
|
cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a7 (
|
|
.portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\CLOCK_50~inputclkctrl_outclk ),
|
|
.clk1(\CLOCK_50~inputclkctrl_outclk ),
|
|
.ena0(!\z80_|address_pins_|abus[13]~20_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[7]~80_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain({\~GND~combout }),
|
|
.portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4],
|
|
\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ),
|
|
.portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a7_PORTBDATAOUT_bus ));
|
|
// synopsys translate_off
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file = "ula/test_scr.hex";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mixed_port_feed_through_mode = "dont_care";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "bidir_dual_port";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_in_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_out_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_address = 0;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_first_bit_number = 7;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_last_address = 8191;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_depth = 16384;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_logical_ram_width = 8;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_read_enable_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .port_b_write_enable_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFC0810207C0001A176020155177486D89000000000000000000000000FFFFFFFF80000003C0000217724019F17748EDC900000000000000000000000000000001BF7EFDF9400406B17A400BF57748AD81000000000000000000000000000000013F7EFDF940041EB1724218157749A7910000000000000000000000003F7EFDF90000000140042AF97B426C157DC9B7590000000000000000000000003F7EFDF90000000140042069600246057DC95351000000000000000000000000408102053FFFFFF95FE4084175C246896009F35100000000000000000000000040810207BFFFFFFF7FE4147177C2004960291759;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h7FE8374958F827C15FF88F91E9A80DC3629A9FC172033EC170FB0E8173F792815FE826E158F805C95FF8AF8169A80DC3629A1EC17B033BC1706B3E8173FFB0C1400826E558F805C15DF8AF9169A82DD163C21BC17B133BC1716B3781723F14C1400826E958D825815DD8AF8168482DC161229BC17A133FC171AB3781723F16E9400826E95818058179582F9160480FC162229FC17ACA39C172FB3F8152CF10A1400826E958180D8179580F05614C0DC162329BC171EB398173537F8152E310D1400826E158180D81F8580FD1612C0F41631293C173BB398D63037F81D22313D1400827E958080F01F8188FCB60A40F41435083C1723B198161834F01D67300E3;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'hD4FB0D2352268F0151E680016803440977EDE98148F31101BFFFFFFF4081010750FB094B52728F0151FEC0016C034C0153EDA90148F31F013FFFFFFB4081010152F3096156DA8901503ED2016C03480173FDA00148F11F01000000013F7EFEF952E3017156DA85015022C2016C034C0153FCA00148F10F01000000013F7EFEF956B3A9115052850543C2C2116C014D2153FDA12148D11F013F7EFEF900000001469F8B3150728D0143C05A016D014C81537DA00148D11E01BF7EFEF900000001528F8F2156628D0140004E016F054481513DA181C8513E0580000007FFFFFFFF528E8B2156E28C0148024E0167676C415139B041C8513E07C0810107FFFFFFFF;
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y21_N14
|
|
cycloneive_lcell_comb \Mux0~0 (
|
|
// Equation(s):
|
|
// \Mux0~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\Selector3~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # (!\Selector3~0_combout &
|
|
// ((\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ))))) # (!\z80_|address_pins_|abus[14]~23_combout & (((\Selector3~0_combout ))))
|
|
|
|
.dataa(\z80_|address_pins_|abus[14]~23_combout ),
|
|
.datab(\ram0|altsyncram_component|auto_generated|ram_block1a15~portadataout ),
|
|
.datac(\ram0|altsyncram_component|auto_generated|ram_block1a7~portadataout ),
|
|
.datad(\Selector3~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\Mux0~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \Mux0~0 .lut_mask = 16'hDDA0;
|
|
defparam \Mux0~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X33_Y32_N0
|
|
cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a7 (
|
|
.portawe(vcc),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(!\z80_|address_pins_|abus[13]~20_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain(1'b0),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\rom|altsyncram_component|auto_generated|ram_block1a7_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .clk0_core_clock_enable = "ena0";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_offset_in_bits = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .data_interleave_width_in_bits = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file = "./rom/gw03.hex";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .init_file_layout = "port_a";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .operation_mode = "rom";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_clear = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_address_width = 13;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_byte_enable_clock = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clear = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_out_clock = "clock0";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_data_width = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_address = 0;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_first_bit_number = 7;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_last_address = 8191;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_depth = 16384;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_logical_ram_width = 8;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_a_write_enable_clock = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_address_width = 13;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .port_b_data_width = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .ram_block_type = "M9K";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init3 = 2048'h7C762E21DB2481CB6BB88C68811C76C63B18ECC1BACDC6110DCC70BC20940800C71478E35468600B01A93082C63DD073AE4181844449C08D8D56B0DCC881251C202139803D3000B2E0209DB9101160989A5916381001B0446631006064DB1B996E436E644CF6C8606F124DA230E9B66E2F46BB466E2CE068661B4B05F02F7D00CB3E518948104042F84F1840401018406877D800A00000F5122597005DA4411000800020249004081008924124080114000000020BFFFFEC638C31207B6C321407D901787004001C459326210CCE00C6AF707B84440C313110B8C4D13B2C6E06C4C088B1A9B24BEB0178C4D6C18230DF72B07A28063647CC4721026D8C711864;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init2 = 2048'h881B30810845E6D18622EC9B6236A000030986A4F0644601226000A2F220D40310438334E51C28000400B18422CA60FC42C9C03F066366ECBBB010B00B004807CC0E00DAEC3000194A52B80C606262092D84A1102410000001400010002000800200080020000800200008000800400040002004000040002000020002000801000010004002001000200008000AEE708008880C86112251B45B36C0048833B319B4C2CE6660D2C0619246C4B208BC0AD00202001E104FC30911410804201E92102B400E8004C40AD6E4614466308ABC7165AA57060A3A736A188ABB300200A10BB04344008422327B1393C43396A931B8C8C87227A6141C0E2DCC76D830B082;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init1 = 2048'h101CC0024A6C32005CCB31908842211604D8B326101118B54B188CB4D502F5F02DA65C2472B824F109BC594C2401209C01A0E59830002C73B396C6015B85A163184B56183004204267600220A061A004893E1D609106BDBB553920A011AA5AE581E08228382D54C2989BC59535528176240438C9AA757917F95C7428981A26470D1C3E528444D9B00E561C40973AE1806031C464834F03D34A11233A34B34A1D1A55A50C3384B549B64C381920140D4008004020B119D5834C10064000006001169808000200040100000002F8986E37654DDFF88E20860382DC089D4C239F6E4C3C8D784218667F524CE209881213DC91099C14744901620044C802DA414966;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a7 .mem_init0 = 2048'h84724A241226DB4809C9A1100DE6A63984D651A2624A09420496DDC12CC10964B6E370363701B41848117683379C8422106D001BB41FB8248067301E1002C636A276585D5273AC87206840415DA74B4E9D213CAE3234B308E19608AA38250844883838649E1442A0D983F4A9094A5AD4A52D56C5D80CAC58D9645944A230091549F30426B100842A12B25160D6D991E6C8C81AFB4C644004C2140A342020D84C9001624489A10045D16C944B02763FF55405E400BADFE5BFFFFFF00000000011042250089108884888410924041204444209102084241104204108824114455292225124929249248894408541300A6DB00791E5B12FEF24037181F1901B007B;
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y21_N16
|
|
cycloneive_lcell_comb \Mux0~1 (
|
|
// Equation(s):
|
|
// \Mux0~1_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\Mux0~0_combout )))) # (!\z80_|address_pins_|abus[14]~23_combout & ((\Mux0~0_combout & (\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout )) # (!\Mux0~0_combout &
|
|
// ((\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout )))))
|
|
|
|
.dataa(\z80_|address_pins_|abus[14]~23_combout ),
|
|
.datab(\rom|altsyncram_component|auto_generated|ram_block1a15~portadataout ),
|
|
.datac(\Mux0~0_combout ),
|
|
.datad(\rom|altsyncram_component|auto_generated|ram_block1a7~portadataout ),
|
|
.cin(gnd),
|
|
.combout(\Mux0~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \Mux0~1 .lut_mask = 16'hE5E0;
|
|
defparam \Mux0~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y21_N22
|
|
cycloneive_lcell_comb \D[7]~89 (
|
|
// Equation(s):
|
|
// \D[7]~89_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Mux0~1_combout ))))) #
|
|
// (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout ))
|
|
|
|
.dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[7]~15_combout ),
|
|
.datac(\z80_|address_pins_|DFFE_apin_latch [15]),
|
|
.datad(\Mux0~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[7]~89_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[7]~89 .lut_mask = 16'hCEC4;
|
|
defparam \D[7]~89 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y21_N30
|
|
cycloneive_lcell_comb \D[7]~72 (
|
|
// Equation(s):
|
|
// \D[7]~72_combout = (\D[5]~67_combout & (\D[7]~89_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) # (!\D[5]~67_combout & ((\z80_|data_pins_|dout [7]) # ((!\z80_|pin_control_|bus_db_pin_oe~15_combout ))))
|
|
|
|
.dataa(\D[5]~67_combout ),
|
|
.datab(\z80_|data_pins_|dout [7]),
|
|
.datac(\D[7]~89_combout ),
|
|
.datad(\z80_|pin_control_|bus_db_pin_oe~15_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[7]~72_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[7]~72 .lut_mask = 16'hC4F5;
|
|
defparam \D[7]~72 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y11_N12
|
|
cycloneive_lcell_comb \D[0]~84 (
|
|
// Equation(s):
|
|
// \D[0]~84_combout = (\z80_|pin_control_|bus_db_pin_oe~15_combout ) # ((\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & !\z80_|memory_ifc_|nWR_out~0_combout )))
|
|
|
|
.dataa(\z80_|memory_ifc_|nRD_out~2_combout ),
|
|
.datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.datac(\z80_|pin_control_|bus_db_pin_oe~15_combout ),
|
|
.datad(\z80_|memory_ifc_|nWR_out~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[0]~84_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[0]~84 .lut_mask = 16'hF0F8;
|
|
defparam \D[0]~84 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y21_N6
|
|
cycloneive_lcell_comb \D[7]~80 (
|
|
// Equation(s):
|
|
// \D[7]~80_combout = (\D[7]~72_combout ) # (!\D[0]~84_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\D[7]~72_combout ),
|
|
.datad(\D[0]~84_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[7]~80_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[7]~80 .lut_mask = 16'hF0FF;
|
|
defparam \D[7]~80 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y13_N12
|
|
cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] (
|
|
// Equation(s):
|
|
// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [7] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[7]~7_combout ) # ((\D[7]~80_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout &
|
|
// (((\D[7]~80_combout & \z80_|pin_control_|bus_db_pin_re~combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_bus_db_we~7_combout ),
|
|
.datab(\z80_|bus_control_|db[7]~7_combout ),
|
|
.datac(\D[7]~80_combout ),
|
|
.datad(\z80_|pin_control_|bus_db_pin_re~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .lut_mask = 16'hF888;
|
|
defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[7] .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X30_Y13_N13
|
|
dffeas \z80_|data_pins_|dout[7] (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [7]),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|data_pins_|dout [7]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|data_pins_|dout[7] .is_wysiwyg = "true";
|
|
defparam \z80_|data_pins_|dout[7] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y13_N20
|
|
cycloneive_lcell_comb \z80_|bus_control_|db[7]~7 (
|
|
// Equation(s):
|
|
// \z80_|bus_control_|db[7]~7_combout = ((\z80_|bus_control_|db[7]~5_combout & ((\z80_|data_pins_|dout [7]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout )
|
|
|
|
.dataa(\z80_|bus_control_|db[0]~6_combout ),
|
|
.datab(\z80_|bus_control_|db[7]~5_combout ),
|
|
.datac(\z80_|data_pins_|dout [7]),
|
|
.datad(\z80_|execute_|ctl_bus_db_oe~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|bus_control_|db[7]~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|bus_control_|db[7]~7 .lut_mask = 16'hD5DD;
|
|
defparam \z80_|bus_control_|db[7]~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X30_Y13_N21
|
|
dffeas \z80_|ir_|opcode[7] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|bus_control_|db[7]~7_combout ),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|execute_|ctl_ir_we~13_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|ir_|opcode [7]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|ir_|opcode[7] .is_wysiwyg = "true";
|
|
defparam \z80_|ir_|opcode[7] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y13_N30
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal6~0 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal6~0_combout = (!\z80_|decode_state_|DFFE_instED~q & (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|ir_|opcode [7] & !\z80_|ir_|opcode [6])))
|
|
|
|
.dataa(\z80_|decode_state_|DFFE_instED~q ),
|
|
.datab(\z80_|decode_state_|DFFE_instCB~q ),
|
|
.datac(\z80_|ir_|opcode [7]),
|
|
.datad(\z80_|ir_|opcode [6]),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal6~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal6~0 .lut_mask = 16'h0001;
|
|
defparam \z80_|pla_decode_|Equal6~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y16_N4
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal12~0 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal12~0_combout = (!\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal6~0_combout & (\z80_|ir_|opcode [1] & !\z80_|ir_|opcode [0])))
|
|
|
|
.dataa(\z80_|ir_|opcode [2]),
|
|
.datab(\z80_|pla_decode_|Equal6~0_combout ),
|
|
.datac(\z80_|ir_|opcode [1]),
|
|
.datad(\z80_|ir_|opcode [0]),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal12~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal12~0 .lut_mask = 16'h0040;
|
|
defparam \z80_|pla_decode_|Equal12~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y17_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_mRead~16 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mRead~16_combout = (\z80_|ir_|opcode [5] & (!\z80_|ir_|opcode [4] & (\z80_|pla_decode_|Equal12~0_combout & \z80_|ir_|opcode [3])))
|
|
|
|
.dataa(\z80_|ir_|opcode [5]),
|
|
.datab(\z80_|ir_|opcode [4]),
|
|
.datac(\z80_|pla_decode_|Equal12~0_combout ),
|
|
.datad(\z80_|ir_|opcode [3]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mRead~16_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mRead~16 .lut_mask = 16'h2000;
|
|
defparam \z80_|execute_|ctl_mRead~16 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y15_N26
|
|
cycloneive_lcell_comb \z80_|execute_|fMRead~24 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fMRead~24_combout = (\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|execute_|ctl_mRead~16_combout ) # ((\z80_|execute_|ctl_mRead~15_combout )))) # (!\z80_|execute_|ctl_ir_we~4_combout & (\z80_|execute_|ctl_alu_oe~0_combout &
|
|
// ((\z80_|execute_|ctl_mRead~16_combout ) # (\z80_|execute_|ctl_mRead~15_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_ir_we~4_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~16_combout ),
|
|
.datac(\z80_|execute_|ctl_mRead~15_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_oe~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fMRead~24_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fMRead~24 .lut_mask = 16'hFCA8;
|
|
defparam \z80_|execute_|fMRead~24 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y11_N12
|
|
cycloneive_lcell_comb \z80_|execute_|fMRead~25 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fMRead~25_combout = ((\z80_|execute_|fMRead~24_combout ) # ((\z80_|execute_|ixy_d~5_combout & !\z80_|execute_|pc_inc_hold~26_combout ))) # (!\z80_|execute_|ctl_bus_db_oe~0_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_bus_db_oe~0_combout ),
|
|
.datab(\z80_|execute_|ixy_d~5_combout ),
|
|
.datac(\z80_|execute_|fMRead~24_combout ),
|
|
.datad(\z80_|execute_|pc_inc_hold~26_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fMRead~25_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fMRead~25 .lut_mask = 16'hF5FD;
|
|
defparam \z80_|execute_|fMRead~25 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y16_N26
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_mRead~21 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mRead~21_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|decode_state_|in_halt~q & (!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal77~0_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal33~0_combout ),
|
|
.datab(\z80_|decode_state_|in_halt~q ),
|
|
.datac(\z80_|decode_state_|use_ixiy~combout ),
|
|
.datad(\z80_|pla_decode_|Equal77~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mRead~21_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mRead~21 .lut_mask = 16'h0200;
|
|
defparam \z80_|execute_|ctl_mRead~21 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y14_N12
|
|
cycloneive_lcell_comb \z80_|execute_|fMRead~16 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fMRead~16_combout = (\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_ir_we~12_combout ) # ((\z80_|execute_|ctl_mRead~13_combout ) # (\z80_|execute_|ctl_mRead~21_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_ir_we~11_combout ),
|
|
.datab(\z80_|execute_|ctl_ir_we~12_combout ),
|
|
.datac(\z80_|execute_|ctl_mRead~13_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~21_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fMRead~16_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fMRead~16 .lut_mask = 16'hFFFE;
|
|
defparam \z80_|execute_|fMRead~16 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y17_N28
|
|
cycloneive_lcell_comb \z80_|execute_|fMRead~14 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fMRead~14_combout = (\z80_|execute_|ctl_ir_we~14_combout ) # ((\z80_|execute_|ctl_ir_we~8_combout ) # ((!\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )))
|
|
|
|
.dataa(\z80_|decode_state_|use_ixiy~combout ),
|
|
.datab(\z80_|pla_decode_|Equal49~0_combout ),
|
|
.datac(\z80_|execute_|ctl_ir_we~14_combout ),
|
|
.datad(\z80_|execute_|ctl_ir_we~8_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fMRead~14_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fMRead~14 .lut_mask = 16'hFFF4;
|
|
defparam \z80_|execute_|fMRead~14 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y14_N2
|
|
cycloneive_lcell_comb \z80_|execute_|fMRead~15 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fMRead~15_combout = (!\z80_|execute_|fMWrite~3_combout & ((\z80_|execute_|ctl_ir_we~11_combout ) # ((\z80_|execute_|ctl_mRead~4_combout ) # (\z80_|execute_|fMRead~14_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_ir_we~11_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~4_combout ),
|
|
.datac(\z80_|execute_|fMRead~14_combout ),
|
|
.datad(\z80_|execute_|fMWrite~3_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fMRead~15_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fMRead~15 .lut_mask = 16'h00FE;
|
|
defparam \z80_|execute_|fMRead~15 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y16_N6
|
|
cycloneive_lcell_comb \z80_|execute_|fMRead~12 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fMRead~12_combout = (!\z80_|pla_decode_|Equal13~2_combout & (!\z80_|execute_|ctl_mRead~2_combout & (!\z80_|pla_decode_|Equal6~1_combout & \z80_|execute_|ctl_bus_db_oe~1_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal13~2_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~2_combout ),
|
|
.datac(\z80_|pla_decode_|Equal6~1_combout ),
|
|
.datad(\z80_|execute_|ctl_bus_db_oe~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fMRead~12_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fMRead~12 .lut_mask = 16'h0100;
|
|
defparam \z80_|execute_|fMRead~12 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y14_N18
|
|
cycloneive_lcell_comb \z80_|execute_|fMRead~11 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fMRead~11_combout = (((\z80_|execute_|ctl_mRead~11_combout ) # (\z80_|execute_|ctl_mRead~21_combout )) # (!\z80_|execute_|pc_inc_hold~6_combout )) # (!\z80_|execute_|nextM~3_combout )
|
|
|
|
.dataa(\z80_|execute_|nextM~3_combout ),
|
|
.datab(\z80_|execute_|pc_inc_hold~6_combout ),
|
|
.datac(\z80_|execute_|ctl_mRead~11_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~21_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fMRead~11_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fMRead~11 .lut_mask = 16'hFFF7;
|
|
defparam \z80_|execute_|fMRead~11 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y14_N0
|
|
cycloneive_lcell_comb \z80_|execute_|fMRead~13 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fMRead~13_combout = (\z80_|execute_|ctl_state_alu~2_combout & (((\z80_|execute_|ctl_ir_we~14_combout ) # (\z80_|execute_|fMRead~11_combout )) # (!\z80_|execute_|fMRead~12_combout )))
|
|
|
|
.dataa(\z80_|execute_|fMRead~12_combout ),
|
|
.datab(\z80_|execute_|ctl_ir_we~14_combout ),
|
|
.datac(\z80_|execute_|ctl_state_alu~2_combout ),
|
|
.datad(\z80_|execute_|fMRead~11_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fMRead~13_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fMRead~13 .lut_mask = 16'hF0D0;
|
|
defparam \z80_|execute_|fMRead~13 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y14_N6
|
|
cycloneive_lcell_comb \z80_|execute_|fMRead~17 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fMRead~17_combout = (\z80_|execute_|fMRead~15_combout ) # ((\z80_|execute_|fMRead~13_combout ) # ((\z80_|execute_|fMRead~16_combout & \z80_|execute_|ctl_state_alu~4_combout )))
|
|
|
|
.dataa(\z80_|execute_|fMRead~16_combout ),
|
|
.datab(\z80_|execute_|fMRead~15_combout ),
|
|
.datac(\z80_|execute_|ctl_state_alu~4_combout ),
|
|
.datad(\z80_|execute_|fMRead~13_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fMRead~17_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fMRead~17 .lut_mask = 16'hFFEC;
|
|
defparam \z80_|execute_|fMRead~17 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y12_N6
|
|
cycloneive_lcell_comb \z80_|execute_|fMRead~22 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fMRead~22_combout = (\z80_|execute_|fMRead~17_combout ) # (((!\z80_|execute_|fMRead~21_combout ) # (!\z80_|execute_|ctl_bus_inc_oe~40_combout )) # (!\z80_|execute_|ctl_sw_4d~2_combout ))
|
|
|
|
.dataa(\z80_|execute_|fMRead~17_combout ),
|
|
.datab(\z80_|execute_|ctl_sw_4d~2_combout ),
|
|
.datac(\z80_|execute_|ctl_bus_inc_oe~40_combout ),
|
|
.datad(\z80_|execute_|fMRead~21_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fMRead~22_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fMRead~22 .lut_mask = 16'hBFFF;
|
|
defparam \z80_|execute_|fMRead~22 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y13_N22
|
|
cycloneive_lcell_comb \z80_|execute_|fMRead~27 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fMRead~27_combout = ((\z80_|sequencer_|DFFE_M2_ff~q & (!\z80_|execute_|ixy_d~4_combout & \z80_|execute_|ctl_mRead~12_combout ))) # (!\z80_|execute_|fMRead~26_combout )
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_M2_ff~q ),
|
|
.datab(\z80_|execute_|fMRead~26_combout ),
|
|
.datac(\z80_|execute_|ixy_d~4_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~12_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fMRead~27_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fMRead~27 .lut_mask = 16'h3B33;
|
|
defparam \z80_|execute_|fMRead~27 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y13_N14
|
|
cycloneive_lcell_comb \z80_|execute_|fMRead~37 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fMRead~37_combout = (\z80_|sequencer_|DFFE_M4_ff~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|execute_|ctl_mRead~13_combout ) # (\z80_|execute_|ctl_state_alu~6_combout ))))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_M4_ff~q ),
|
|
.datab(\z80_|execute_|ctl_mRead~13_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datad(\z80_|execute_|ctl_state_alu~6_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fMRead~37_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fMRead~37 .lut_mask = 16'h0A08;
|
|
defparam \z80_|execute_|fMRead~37 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y13_N20
|
|
cycloneive_lcell_comb \z80_|execute_|fMRead~31 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fMRead~31_combout = (\z80_|pla_decode_|Equal33~3_combout & ((\z80_|execute_|ixy_d~5_combout ) # ((\z80_|execute_|ixy_d~6_combout )))) # (!\z80_|pla_decode_|Equal33~3_combout & (\z80_|pla_decode_|Equal6~1_combout &
|
|
// ((\z80_|execute_|ixy_d~5_combout ) # (\z80_|execute_|ixy_d~6_combout ))))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal33~3_combout ),
|
|
.datab(\z80_|execute_|ixy_d~5_combout ),
|
|
.datac(\z80_|execute_|ixy_d~6_combout ),
|
|
.datad(\z80_|pla_decode_|Equal6~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fMRead~31_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fMRead~31 .lut_mask = 16'hFCA8;
|
|
defparam \z80_|execute_|fMRead~31 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y17_N14
|
|
cycloneive_lcell_comb \z80_|execute_|fMRead~29 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fMRead~29_combout = (\z80_|execute_|ctl_ir_we~5_combout & (\z80_|pla_decode_|Equal33~0_combout & ((\z80_|ir_|opcode [7]) # (\z80_|ir_|opcode [6]))))
|
|
|
|
.dataa(\z80_|execute_|ctl_ir_we~5_combout ),
|
|
.datab(\z80_|ir_|opcode [7]),
|
|
.datac(\z80_|pla_decode_|Equal33~0_combout ),
|
|
.datad(\z80_|ir_|opcode [6]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fMRead~29_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fMRead~29 .lut_mask = 16'hA080;
|
|
defparam \z80_|execute_|fMRead~29 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y13_N30
|
|
cycloneive_lcell_comb \z80_|execute_|fMRead~30 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fMRead~30_combout = (\z80_|execute_|ctl_alu_shift_oe~14_combout & ((\z80_|execute_|ctl_ir_we~9_combout ) # ((\z80_|execute_|fMRead~29_combout ) # (\z80_|execute_|ctl_ir_we~10_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_ir_we~9_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_shift_oe~14_combout ),
|
|
.datac(\z80_|execute_|fMRead~29_combout ),
|
|
.datad(\z80_|execute_|ctl_ir_we~10_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fMRead~30_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fMRead~30 .lut_mask = 16'hCCC8;
|
|
defparam \z80_|execute_|fMRead~30 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y13_N0
|
|
cycloneive_lcell_comb \z80_|execute_|fMRead~28 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fMRead~28_combout = ((\z80_|execute_|ixy_d~6_combout & ((\z80_|pla_decode_|Equal41~2_combout ) # (\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|nextM~4_combout )
|
|
|
|
.dataa(\z80_|execute_|ixy_d~6_combout ),
|
|
.datab(\z80_|execute_|nextM~4_combout ),
|
|
.datac(\z80_|pla_decode_|Equal41~2_combout ),
|
|
.datad(\z80_|pla_decode_|Equal9~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fMRead~28_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fMRead~28 .lut_mask = 16'hBBB3;
|
|
defparam \z80_|execute_|fMRead~28 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y13_N18
|
|
cycloneive_lcell_comb \z80_|execute_|fMRead~32 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fMRead~32_combout = ((\z80_|execute_|fMRead~31_combout ) # ((\z80_|execute_|fMRead~30_combout ) # (\z80_|execute_|fMRead~28_combout ))) # (!\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_sys_hilo[1]~14_combout ),
|
|
.datab(\z80_|execute_|fMRead~31_combout ),
|
|
.datac(\z80_|execute_|fMRead~30_combout ),
|
|
.datad(\z80_|execute_|fMRead~28_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fMRead~32_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fMRead~32 .lut_mask = 16'hFFFD;
|
|
defparam \z80_|execute_|fMRead~32 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y13_N12
|
|
cycloneive_lcell_comb \z80_|execute_|fMRead~33 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fMRead~33_combout = (\z80_|execute_|fMRead~27_combout ) # (((\z80_|execute_|fMRead~37_combout ) # (\z80_|execute_|fMRead~32_combout )) # (!\z80_|execute_|fMRead~6_combout ))
|
|
|
|
.dataa(\z80_|execute_|fMRead~27_combout ),
|
|
.datab(\z80_|execute_|fMRead~6_combout ),
|
|
.datac(\z80_|execute_|fMRead~37_combout ),
|
|
.datad(\z80_|execute_|fMRead~32_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fMRead~33_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fMRead~33 .lut_mask = 16'hFFFB;
|
|
defparam \z80_|execute_|fMRead~33 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y14_N24
|
|
cycloneive_lcell_comb \z80_|execute_|fMRead~23 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fMRead~23_combout = (\z80_|execute_|ctl_state_alu~3_combout & (((\z80_|execute_|ctl_mRead~34_combout ) # (!\z80_|execute_|fMRead~5_combout )) # (!\z80_|execute_|fMRead~4_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_state_alu~3_combout ),
|
|
.datab(\z80_|execute_|fMRead~4_combout ),
|
|
.datac(\z80_|execute_|ctl_mRead~34_combout ),
|
|
.datad(\z80_|execute_|fMRead~5_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fMRead~23_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fMRead~23 .lut_mask = 16'hA2AA;
|
|
defparam \z80_|execute_|fMRead~23 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y11_N26
|
|
cycloneive_lcell_comb \z80_|execute_|fMRead~34 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fMRead~34_combout = (\z80_|execute_|fMRead~25_combout ) # ((\z80_|execute_|fMRead~22_combout ) # ((\z80_|execute_|fMRead~33_combout ) # (\z80_|execute_|fMRead~23_combout )))
|
|
|
|
.dataa(\z80_|execute_|fMRead~25_combout ),
|
|
.datab(\z80_|execute_|fMRead~22_combout ),
|
|
.datac(\z80_|execute_|fMRead~33_combout ),
|
|
.datad(\z80_|execute_|fMRead~23_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fMRead~34_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fMRead~34 .lut_mask = 16'hFFFE;
|
|
defparam \z80_|execute_|fMRead~34 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y14_N14
|
|
cycloneive_lcell_comb \z80_|execute_|fMRead~35 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fMRead~35_combout = ((\z80_|execute_|ctl_ir_we~12_combout ) # ((\z80_|execute_|ctl_mRead~21_combout ) # (!\z80_|execute_|fMRead~7_combout ))) # (!\z80_|execute_|fMWrite~1_combout )
|
|
|
|
.dataa(\z80_|execute_|fMWrite~1_combout ),
|
|
.datab(\z80_|execute_|ctl_ir_we~12_combout ),
|
|
.datac(\z80_|execute_|fMRead~7_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~21_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fMRead~35_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fMRead~35 .lut_mask = 16'hFFDF;
|
|
defparam \z80_|execute_|fMRead~35 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y11_N2
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~19 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sel_pc~19_combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|sequencer_|DFFE_M3_ff~q & ((\z80_|pla_decode_|Equal33~3_combout ) # (!\z80_|execute_|ctl_al_we~5_combout ))))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datab(\z80_|sequencer_|DFFE_M3_ff~q ),
|
|
.datac(\z80_|pla_decode_|Equal33~3_combout ),
|
|
.datad(\z80_|execute_|ctl_al_we~5_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sel_pc~19_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sel_pc~19 .lut_mask = 16'h4044;
|
|
defparam \z80_|execute_|ctl_reg_sel_pc~19 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y11_N16
|
|
cycloneive_lcell_comb \z80_|execute_|fMRead~36 (
|
|
// Equation(s):
|
|
// \z80_|execute_|fMRead~36_combout = (\z80_|execute_|fMRead~34_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~19_combout ) # ((!\z80_|execute_|fMRead~2_combout & \z80_|execute_|fMRead~35_combout )))
|
|
|
|
.dataa(\z80_|execute_|fMRead~34_combout ),
|
|
.datab(\z80_|execute_|fMRead~2_combout ),
|
|
.datac(\z80_|execute_|fMRead~35_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sel_pc~19_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|fMRead~36_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|fMRead~36 .lut_mask = 16'hFFBA;
|
|
defparam \z80_|execute_|fMRead~36 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y13_N22
|
|
cycloneive_lcell_comb \z80_|pin_control_|bus_db_pin_re (
|
|
// Equation(s):
|
|
// \z80_|pin_control_|bus_db_pin_re~combout = (\z80_|pin_control_|bus_db_pin_re~2_combout ) # ((\z80_|sequencer_|DFFE_T2_ff~q & \z80_|execute_|fMRead~36_combout ))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|fMRead~36_combout ),
|
|
.datad(\z80_|pin_control_|bus_db_pin_re~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|pin_control_|bus_db_pin_re~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pin_control_|bus_db_pin_re .lut_mask = 16'hFFA0;
|
|
defparam \z80_|pin_control_|bus_db_pin_re .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y9_N16
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~118 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[2][4]~118_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [6]))) # (!\ula_|ps2_keyboard_|shiftreg [2] &
|
|
// (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [6])))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [2]),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [5]),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [0]),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [6]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[2][4]~118_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[2][4]~118 .lut_mask = 16'h1008;
|
|
defparam \ula_|zx_keyboard_|keys[2][4]~118 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y9_N6
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~119 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[2][4]~119_combout = (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[2][4]~118_combout & \ula_|zx_keyboard_|keys[5][1]~34_combout )))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [1]),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [3]),
|
|
.datac(\ula_|zx_keyboard_|keys[2][4]~118_combout ),
|
|
.datad(\ula_|zx_keyboard_|keys[5][1]~34_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[2][4]~119_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[2][4]~119 .lut_mask = 16'h4000;
|
|
defparam \ula_|zx_keyboard_|keys[2][4]~119 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y9_N0
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][4]~120 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[2][4]~120_combout = (\ula_|zx_keyboard_|keys[2][4]~119_combout & ((!\ula_|zx_keyboard_|keys[2][4]~94_combout ))) # (!\ula_|zx_keyboard_|keys[2][4]~119_combout & (\ula_|zx_keyboard_|keys[2][4]~q ))
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[2][4]~119_combout ),
|
|
.datab(gnd),
|
|
.datac(\ula_|zx_keyboard_|keys[2][4]~q ),
|
|
.datad(\ula_|zx_keyboard_|keys[2][4]~94_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[2][4]~120_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[2][4]~120 .lut_mask = 16'h50FA;
|
|
defparam \ula_|zx_keyboard_|keys[2][4]~120 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X28_Y9_N1
|
|
dffeas \ula_|zx_keyboard_|keys[2][4] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|zx_keyboard_|keys[2][4]~120_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|zx_keyboard_|keys[2][4]~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[2][4] .is_wysiwyg = "true";
|
|
defparam \ula_|zx_keyboard_|keys[2][4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y8_N18
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~129 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[3][4]~129_combout = (!\ula_|ps2_keyboard_|shiftreg [7] & (\ula_|ps2_keyboard_|scan_code_ready~q & (!\ula_|zx_keyboard_|Equal0~1_combout & \ula_|ps2_keyboard_|shiftreg [5])))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [7]),
|
|
.datab(\ula_|ps2_keyboard_|scan_code_ready~q ),
|
|
.datac(\ula_|zx_keyboard_|Equal0~1_combout ),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [5]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[3][4]~129_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[3][4]~129 .lut_mask = 16'h0400;
|
|
defparam \ula_|zx_keyboard_|keys[3][4]~129 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y8_N22
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~116 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[3][4]~116_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [2] & \ula_|ps2_keyboard_|shiftreg [0]))) # (!\ula_|ps2_keyboard_|shiftreg [6] &
|
|
// (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [0])))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [6]),
|
|
.datab(\ula_|zx_keyboard_|extended~q ),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [2]),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [0]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[3][4]~116_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[3][4]~116 .lut_mask = 16'h0810;
|
|
defparam \ula_|zx_keyboard_|keys[3][4]~116 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y8_N20
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~134 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[3][4]~134_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [1] & \ula_|zx_keyboard_|keys[3][4]~116_combout )))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [4]),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [3]),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [1]),
|
|
.datad(\ula_|zx_keyboard_|keys[3][4]~116_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[3][4]~134_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[3][4]~134 .lut_mask = 16'h4000;
|
|
defparam \ula_|zx_keyboard_|keys[3][4]~134 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y8_N18
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][4]~117 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[3][4]~117_combout = (\ula_|zx_keyboard_|keys[3][4]~129_combout & ((\ula_|zx_keyboard_|keys[3][4]~134_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][4]~134_combout & ((\ula_|zx_keyboard_|keys[3][4]~q
|
|
// ))))) # (!\ula_|zx_keyboard_|keys[3][4]~129_combout & (((\ula_|zx_keyboard_|keys[3][4]~q ))))
|
|
|
|
.dataa(\ula_|zx_keyboard_|released~q ),
|
|
.datab(\ula_|zx_keyboard_|keys[3][4]~129_combout ),
|
|
.datac(\ula_|zx_keyboard_|keys[3][4]~q ),
|
|
.datad(\ula_|zx_keyboard_|keys[3][4]~134_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[3][4]~117_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[3][4]~117 .lut_mask = 16'h74F0;
|
|
defparam \ula_|zx_keyboard_|keys[3][4]~117 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X29_Y8_N19
|
|
dffeas \ula_|zx_keyboard_|keys[3][4] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|zx_keyboard_|keys[3][4]~117_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|zx_keyboard_|keys[3][4]~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[3][4] .is_wysiwyg = "true";
|
|
defparam \ula_|zx_keyboard_|keys[3][4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y9_N6
|
|
cycloneive_lcell_comb \D[4]~60 (
|
|
// Equation(s):
|
|
// \D[4]~60_combout = (\z80_|address_pins_|abus[11]~19_combout & ((\z80_|address_pins_|abus[10]~24_combout ) # ((!\ula_|zx_keyboard_|keys[2][4]~q )))) # (!\z80_|address_pins_|abus[11]~19_combout & (!\ula_|zx_keyboard_|keys[3][4]~q &
|
|
// ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][4]~q ))))
|
|
|
|
.dataa(\z80_|address_pins_|abus[11]~19_combout ),
|
|
.datab(\z80_|address_pins_|abus[10]~24_combout ),
|
|
.datac(\ula_|zx_keyboard_|keys[2][4]~q ),
|
|
.datad(\ula_|zx_keyboard_|keys[3][4]~q ),
|
|
.cin(gnd),
|
|
.combout(\D[4]~60_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[4]~60 .lut_mask = 16'h8ACF;
|
|
defparam \D[4]~60 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y9_N30
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|Equal0~2 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|Equal0~2_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [3]))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [5]),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [0]),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [3]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|Equal0~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|Equal0~2 .lut_mask = 16'h000C;
|
|
defparam \ula_|zx_keyboard_|Equal0~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y9_N8
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][4]~121 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[1][4]~121_combout = (\ula_|zx_keyboard_|keys[1][4]~23_combout & ((\ula_|zx_keyboard_|Equal0~2_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|Equal0~2_combout & ((\ula_|zx_keyboard_|keys[1][4]~q ))))) #
|
|
// (!\ula_|zx_keyboard_|keys[1][4]~23_combout & (((\ula_|zx_keyboard_|keys[1][4]~q ))))
|
|
|
|
.dataa(\ula_|zx_keyboard_|released~q ),
|
|
.datab(\ula_|zx_keyboard_|keys[1][4]~23_combout ),
|
|
.datac(\ula_|zx_keyboard_|keys[1][4]~q ),
|
|
.datad(\ula_|zx_keyboard_|Equal0~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[1][4]~121_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[1][4]~121 .lut_mask = 16'h74F0;
|
|
defparam \ula_|zx_keyboard_|keys[1][4]~121 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X27_Y9_N9
|
|
dffeas \ula_|zx_keyboard_|keys[1][4] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|zx_keyboard_|keys[1][4]~121_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|zx_keyboard_|keys[1][4]~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[1][4] .is_wysiwyg = "true";
|
|
defparam \ula_|zx_keyboard_|keys[1][4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y9_N30
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][4]~115 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[0][4]~115_combout = (\ula_|zx_keyboard_|keys[3][1]~27_combout & ((\ula_|zx_keyboard_|keys[0][4]~96_combout & ((!\ula_|zx_keyboard_|keys[0][4]~109_combout ))) # (!\ula_|zx_keyboard_|keys[0][4]~96_combout &
|
|
// (\ula_|zx_keyboard_|keys[0][4]~q )))) # (!\ula_|zx_keyboard_|keys[3][1]~27_combout & (((\ula_|zx_keyboard_|keys[0][4]~q ))))
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[3][1]~27_combout ),
|
|
.datab(\ula_|zx_keyboard_|keys[0][4]~96_combout ),
|
|
.datac(\ula_|zx_keyboard_|keys[0][4]~q ),
|
|
.datad(\ula_|zx_keyboard_|keys[0][4]~109_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[0][4]~115_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[0][4]~115 .lut_mask = 16'h70F8;
|
|
defparam \ula_|zx_keyboard_|keys[0][4]~115 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X28_Y9_N31
|
|
dffeas \ula_|zx_keyboard_|keys[0][4] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|zx_keyboard_|keys[0][4]~115_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|zx_keyboard_|keys[0][4]~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[0][4] .is_wysiwyg = "true";
|
|
defparam \ula_|zx_keyboard_|keys[0][4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y9_N0
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~4 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|key_row~4_combout = ((\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) # (!\ula_|zx_keyboard_|keys[0][4]~q )
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[0][4]~q ),
|
|
.datab(gnd),
|
|
.datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.datad(\z80_|address_pins_|DFFE_apin_latch [8]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|key_row~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|key_row~4 .lut_mask = 16'hFF5F;
|
|
defparam \ula_|zx_keyboard_|key_row~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y9_N22
|
|
cycloneive_lcell_comb \D[4]~61 (
|
|
// Equation(s):
|
|
// \D[4]~61_combout = (\D[4]~60_combout & (\ula_|zx_keyboard_|key_row~4_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][4]~q ))))
|
|
|
|
.dataa(\D[4]~60_combout ),
|
|
.datab(\z80_|address_pins_|abus[9]~17_combout ),
|
|
.datac(\ula_|zx_keyboard_|keys[1][4]~q ),
|
|
.datad(\ula_|zx_keyboard_|key_row~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[4]~61_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[4]~61 .lut_mask = 16'h8A00;
|
|
defparam \D[4]~61 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y8_N2
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~124 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[4][4]~124_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|extended~q & !\ula_|ps2_keyboard_|shiftreg [2])) # (!\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|zx_keyboard_|extended~q & \ula_|ps2_keyboard_|shiftreg
|
|
// [2]))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [6]),
|
|
.datac(\ula_|zx_keyboard_|extended~q ),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [2]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[4][4]~124_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[4][4]~124 .lut_mask = 16'h03C0;
|
|
defparam \ula_|zx_keyboard_|keys[4][4]~124 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y8_N12
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~125 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[4][4]~125_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[4][4]~124_combout & (\ula_|zx_keyboard_|Equal0~2_combout & \ula_|ps2_keyboard_|shiftreg [1])))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [4]),
|
|
.datab(\ula_|zx_keyboard_|keys[4][4]~124_combout ),
|
|
.datac(\ula_|zx_keyboard_|Equal0~2_combout ),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [1]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[4][4]~125_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[4][4]~125 .lut_mask = 16'h8000;
|
|
defparam \ula_|zx_keyboard_|keys[4][4]~125 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y8_N6
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][4]~126 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[4][4]~126_combout = (\ula_|zx_keyboard_|keys[0][0]~13_combout & ((\ula_|zx_keyboard_|keys[4][4]~125_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][4]~125_combout & ((\ula_|zx_keyboard_|keys[4][4]~q
|
|
// ))))) # (!\ula_|zx_keyboard_|keys[0][0]~13_combout & (((\ula_|zx_keyboard_|keys[4][4]~q ))))
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[0][0]~13_combout ),
|
|
.datab(\ula_|zx_keyboard_|released~q ),
|
|
.datac(\ula_|zx_keyboard_|keys[4][4]~q ),
|
|
.datad(\ula_|zx_keyboard_|keys[4][4]~125_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[4][4]~126_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[4][4]~126 .lut_mask = 16'h72F0;
|
|
defparam \ula_|zx_keyboard_|keys[4][4]~126 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X28_Y8_N7
|
|
dffeas \ula_|zx_keyboard_|keys[4][4] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|zx_keyboard_|keys[4][4]~126_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|zx_keyboard_|keys[4][4]~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[4][4] .is_wysiwyg = "true";
|
|
defparam \ula_|zx_keyboard_|keys[4][4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y8_N16
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~122 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[5][4]~122_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [0] & \ula_|ps2_keyboard_|shiftreg [2])))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [4]),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [1]),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [0]),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [2]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[5][4]~122_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[5][4]~122 .lut_mask = 16'h2000;
|
|
defparam \ula_|zx_keyboard_|keys[5][4]~122 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y8_N0
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][4]~123 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[5][4]~123_combout = (\ula_|zx_keyboard_|keys[6][4]~46_combout & ((\ula_|zx_keyboard_|keys[5][4]~122_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[5][4]~122_combout & (\ula_|zx_keyboard_|keys[5][4]~q
|
|
// )))) # (!\ula_|zx_keyboard_|keys[6][4]~46_combout & (((\ula_|zx_keyboard_|keys[5][4]~q ))))
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[6][4]~46_combout ),
|
|
.datab(\ula_|zx_keyboard_|keys[5][4]~122_combout ),
|
|
.datac(\ula_|zx_keyboard_|keys[5][4]~q ),
|
|
.datad(\ula_|zx_keyboard_|released~q ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[5][4]~123_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[5][4]~123 .lut_mask = 16'h70F8;
|
|
defparam \ula_|zx_keyboard_|keys[5][4]~123 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X28_Y8_N1
|
|
dffeas \ula_|zx_keyboard_|keys[5][4] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|zx_keyboard_|keys[5][4]~123_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|zx_keyboard_|keys[5][4]~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[5][4] .is_wysiwyg = "true";
|
|
defparam \ula_|zx_keyboard_|keys[5][4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y8_N8
|
|
cycloneive_lcell_comb \D[4]~62 (
|
|
// Equation(s):
|
|
// \D[4]~62_combout = (\ula_|zx_keyboard_|keys[4][4]~q & (\z80_|address_pins_|abus[12]~21_combout & ((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][4]~q )))) # (!\ula_|zx_keyboard_|keys[4][4]~q &
|
|
// ((\z80_|address_pins_|abus[13]~20_combout ) # ((!\ula_|zx_keyboard_|keys[5][4]~q ))))
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[4][4]~q ),
|
|
.datab(\z80_|address_pins_|abus[13]~20_combout ),
|
|
.datac(\z80_|address_pins_|abus[12]~21_combout ),
|
|
.datad(\ula_|zx_keyboard_|keys[5][4]~q ),
|
|
.cin(gnd),
|
|
.combout(\D[4]~62_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[4]~62 .lut_mask = 16'hC4F5;
|
|
defparam \D[4]~62 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y7_N28
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~49 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[7][4]~49_combout = (\ula_|zx_keyboard_|keys[7][1]~21_combout & (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|Equal0~2_combout & !\ula_|ps2_keyboard_|shiftreg [6])))
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[7][1]~21_combout ),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [1]),
|
|
.datac(\ula_|zx_keyboard_|Equal0~2_combout ),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [6]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[7][4]~49_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[7][4]~49 .lut_mask = 16'h0080;
|
|
defparam \ula_|zx_keyboard_|keys[7][4]~49 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y7_N0
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|shifted~3 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|shifted~3_combout = (\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2])
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [4]),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [2]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|shifted~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|shifted~3 .lut_mask = 16'h00F0;
|
|
defparam \ula_|zx_keyboard_|shifted~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y7_N22
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][4]~127 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[7][4]~127_combout = (\ula_|zx_keyboard_|keys[7][4]~49_combout & ((\ula_|zx_keyboard_|shifted~3_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|shifted~3_combout & ((\ula_|zx_keyboard_|keys[7][4]~q ))))) #
|
|
// (!\ula_|zx_keyboard_|keys[7][4]~49_combout & (((\ula_|zx_keyboard_|keys[7][4]~q ))))
|
|
|
|
.dataa(\ula_|zx_keyboard_|released~q ),
|
|
.datab(\ula_|zx_keyboard_|keys[7][4]~49_combout ),
|
|
.datac(\ula_|zx_keyboard_|keys[7][4]~q ),
|
|
.datad(\ula_|zx_keyboard_|shifted~3_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[7][4]~127_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[7][4]~127 .lut_mask = 16'h74F0;
|
|
defparam \ula_|zx_keyboard_|keys[7][4]~127 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X27_Y7_N23
|
|
dffeas \ula_|zx_keyboard_|keys[7][4] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|zx_keyboard_|keys[7][4]~127_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|zx_keyboard_|keys[7][4]~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[7][4] .is_wysiwyg = "true";
|
|
defparam \ula_|zx_keyboard_|keys[7][4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y7_N8
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][4]~128 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[6][4]~128_combout = (\ula_|zx_keyboard_|keys[6][4]~46_combout & ((\ula_|zx_keyboard_|keys[6][4]~18_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[6][4]~18_combout & ((\ula_|zx_keyboard_|keys[6][4]~q
|
|
// ))))) # (!\ula_|zx_keyboard_|keys[6][4]~46_combout & (((\ula_|zx_keyboard_|keys[6][4]~q ))))
|
|
|
|
.dataa(\ula_|zx_keyboard_|released~q ),
|
|
.datab(\ula_|zx_keyboard_|keys[6][4]~46_combout ),
|
|
.datac(\ula_|zx_keyboard_|keys[6][4]~q ),
|
|
.datad(\ula_|zx_keyboard_|keys[6][4]~18_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[6][4]~128_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[6][4]~128 .lut_mask = 16'h74F0;
|
|
defparam \ula_|zx_keyboard_|keys[6][4]~128 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X27_Y7_N9
|
|
dffeas \ula_|zx_keyboard_|keys[6][4] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|zx_keyboard_|keys[6][4]~128_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|zx_keyboard_|keys[6][4]~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[6][4] .is_wysiwyg = "true";
|
|
defparam \ula_|zx_keyboard_|keys[6][4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y10_N28
|
|
cycloneive_lcell_comb \D[4]~63 (
|
|
// Equation(s):
|
|
// \D[4]~63_combout = (\ula_|zx_keyboard_|keys[7][4]~q & (\z80_|address_pins_|abus[15]~22_combout & ((\z80_|address_pins_|abus[14]~23_combout ) # (!\ula_|zx_keyboard_|keys[6][4]~q )))) # (!\ula_|zx_keyboard_|keys[7][4]~q &
|
|
// (((\z80_|address_pins_|abus[14]~23_combout ) # (!\ula_|zx_keyboard_|keys[6][4]~q ))))
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[7][4]~q ),
|
|
.datab(\z80_|address_pins_|abus[15]~22_combout ),
|
|
.datac(\ula_|zx_keyboard_|keys[6][4]~q ),
|
|
.datad(\z80_|address_pins_|abus[14]~23_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[4]~63_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[4]~63 .lut_mask = 16'hDD0D;
|
|
defparam \D[4]~63 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y10_N6
|
|
cycloneive_lcell_comb \D[4]~64 (
|
|
// Equation(s):
|
|
// \D[4]~64_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[4]~61_combout & (\D[4]~62_combout & \D[4]~63_combout )))
|
|
|
|
.dataa(\D[4]~61_combout ),
|
|
.datab(\D[4]~62_combout ),
|
|
.datac(\z80_|address_pins_|abus[0]~16_combout ),
|
|
.datad(\D[4]~63_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[4]~64_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[4]~64 .lut_mask = 16'hF8F0;
|
|
defparam \D[4]~64 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X33_Y5_N0
|
|
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a28 (
|
|
.portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[4]~76_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a28_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .clk0_core_clock_enable = "ena0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .data_interleave_width_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file = "led_patterns.mif";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .init_file_layout = "port_a";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .operation_mode = "single_port";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_byte_enable_clock = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_out_clock = "clock0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_address = 0;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_first_bit_number = 4;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_last_address = 8191;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_depth = 32768;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_logical_ram_width = 8;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .port_b_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .ram_block_type = "M9K";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a28 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X33_Y6_N0
|
|
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a20 (
|
|
.portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[4]~76_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .clk0_core_clock_enable = "ena0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .data_interleave_width_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file = "led_patterns.mif";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .init_file_layout = "port_a";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .operation_mode = "single_port";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_byte_enable_clock = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_out_clock = "clock0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_address = 0;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_first_bit_number = 4;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_last_address = 8191;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_depth = 32768;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_logical_ram_width = 8;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .port_b_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .ram_block_type = "M9K";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a20 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X33_Y11_N0
|
|
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a12 (
|
|
.portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[4]~76_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file = "led_patterns.mif";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "single_port";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 32768;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X33_Y9_N0
|
|
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a4 (
|
|
.portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[4]~76_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file = "led_patterns.mif";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "single_port";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 32768;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018;
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y10_N4
|
|
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 (
|
|
// Equation(s):
|
|
// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ) #
|
|
// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout &
|
|
// !\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]))))
|
|
|
|
.dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
|
|
.datab(\ram1|altsyncram_component|auto_generated|ram_block1a12~portadataout ),
|
|
.datac(\ram1|altsyncram_component|auto_generated|ram_block1a4~portadataout ),
|
|
.datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]),
|
|
.cin(gnd),
|
|
.combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 .lut_mask = 16'hAAD8;
|
|
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y10_N14
|
|
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 (
|
|
// Equation(s):
|
|
// \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ) #
|
|
// ((!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout &
|
|
// \ram1|altsyncram_component|auto_generated|out_address_reg_a [1]))))
|
|
|
|
.dataa(\ram1|altsyncram_component|auto_generated|ram_block1a28~portadataout ),
|
|
.datab(\ram1|altsyncram_component|auto_generated|ram_block1a20~portadataout ),
|
|
.datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~8_combout ),
|
|
.datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]),
|
|
.cin(gnd),
|
|
.combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 .lut_mask = 16'hACF0;
|
|
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X33_Y3_N0
|
|
cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a12 (
|
|
.portawe(vcc),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(\z80_|address_pins_|abus[13]~20_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain(1'b0),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\rom|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file = "./rom/gw03.hex";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "rom";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock0";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_a_write_enable_clock = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'hA50276000854A0103840403E540424244404783E18807A08A47C54484448544A807E7E10005270182040407E4A1252124208084008404208420A4A42424A125A024428106448524A624A4A24425242522060108010543C00044A105424005E0031ED1E0529E507AE2F6FF1CD51D4C772A648E65F6532C28022061303F06C36CDBD319B55CB8E626C20E46C93C1463A0B1CE594F0ED3B62330C104DECE46CA6CD966B1386612C7B43980349408F36FB64C14342DAE26CE4D8D5E791388729D743B09A27AB81D71A14AB3D24E385B602248476D00249239514B58D3098504ACD119B99E9021B650A69494C22600667473128DA5010D2195982823226DED0ADFCB8;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h5861917919344A4685CC0990862A11324792E761B6D41C0FCC0838C1C27211A2453FDC2219C225E421B320085A8FBFD0C42135B16448DFC226E09B3438A740C352979565817114DE46462844A57F7958873FC4B255C8AE549BDD1A87415D5018F88D5002628FFD13203066C850F10649F21319109208387641120B362124803F0678522BA2812C1454A502ED1A59CBD76A034756F5765DF7555F57575F7F57FFFF7FFF7D5712524D4A30723514B2B3064A84B4742D48415281863DDFAA9D9B7E7BB16DDB96B7845371C30B55DB96C8F6EB4B453242FF6A4DF84A76B5AEDC88A68DC6A06905054C8C36E4199E74638E6532965218A965909BA456000451343351;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'hE2975A2686A7AE0288F140141B698E2A82A835F478453A1D722CFCED12859FD735188757AC5A42DEB501FE010586249AC1EA60D08F74CFA5086EC78FC9190C056059E332C311521E6522901852D484B423A98816C9B26A08C92368E9FF05524502288A804612A2A0A102A418CBDFBA554499541660F8124640110101263142892A086B442661015380041594608092D9CB919250100A37DDA3919A1427F660963C251301FB2CA45562245308885131119115C652B2493252340201101942D26000CC60799124A8520C08050122171281808058018C38A645D07931896B39ED259A22242CB58413089465B246231330D806105010035100B08761A08506094160;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h1228D91C352915424000000AA0088F63153A8AD81B945C8789F01C86548D12CEAB6AA38578BD55CEC9AA28082C285B8C0201104838AD502AC160C13C70620B818249144AB52CED94200A0202A885100E0D938A30A34512C0CEC98F08A98900F2093E11673256B3169C12284980E92A034141E0782507800F8100009C403C07867000000030082004A17800828F090A0C318CE120012172286317922341A2A12840B6C18040682080125C75401AEC44E8C01A8D40D1412B25A09F7600B0C6FEC65BFE5CE861A20F71E8032916A78F29CC546518461522E4E14998DD54BC0E40B64B710C9DC948F06010DF01D880E2044BE8854062D10DD93F30A62AA7FD227C4C;
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X33_Y27_N0
|
|
cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a12 (
|
|
.portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\CLOCK_50~inputclkctrl_outclk ),
|
|
.clk1(\CLOCK_50~inputclkctrl_outclk ),
|
|
.ena0(\z80_|address_pins_|abus[13]~20_combout ),
|
|
.ena1(gnd),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[4]~76_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain({\~GND~combout }),
|
|
.portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4],
|
|
\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a12_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .clk0_core_clock_enable = "ena0";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .clk1_core_clock_enable = "ena1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .data_interleave_width_in_bits = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .init_file = "ula/test_scr.hex";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .init_file_layout = "port_a";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mixed_port_feed_through_mode = "dont_care";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .operation_mode = "bidir_dual_port";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_address_width = 13;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_byte_enable_clock = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_out_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_data_width = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_address = 0;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_first_bit_number = 4;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_last_address = 8191;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_depth = 16384;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_logical_ram_width = 8;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_address_width = 13;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_in_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_out_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_out_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_data_width = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_first_address = 0;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_first_bit_number = 4;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_last_address = 8191;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_logical_ram_depth = 16384;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_logical_ram_width = 8;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_read_enable_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .port_b_write_enable_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .ram_block_type = "M9K";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a12 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X22_Y24_N0
|
|
cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a4 (
|
|
.portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\CLOCK_50~inputclkctrl_outclk ),
|
|
.clk1(\CLOCK_50~inputclkctrl_outclk ),
|
|
.ena0(!\z80_|address_pins_|abus[13]~20_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[4]~76_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain({\~GND~combout }),
|
|
.portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4],
|
|
\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ),
|
|
.portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a4_PORTBDATAOUT_bus ));
|
|
// synopsys translate_off
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file = "ula/test_scr.hex";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mixed_port_feed_through_mode = "dont_care";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "bidir_dual_port";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_in_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_out_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_address = 0;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_first_bit_number = 4;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_last_address = 8191;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_depth = 16384;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_logical_ram_width = 8;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_read_enable_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .port_b_write_enable_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFF0000003E0000003E0000C83F0000D83F0000F03F0000303E0000303E0000003F0010003F0010203F0010F03F0010703F0018303F001C603D800C003CFE26003C7F0F803FFFFFFFFFFFFFFFF;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF00000000000008108000BDF288E9688E000000000000000000000000FFFFFFFF0000000000041D989EA296D29EE969CA000000000000000000000000000000007FFFFFFC8004198A9AA298929EE9498A00000000000000000000000000000000FFFFFFFE800400CA9AA2AADA8AE949CE0000000000000000000000007FFFFFFEC00000028004046A9F22BA5A9EE90FC20000000000000000000000007FFFFFFE8000000280040FEA8002AA7A9EE12742000000000000000000000000000000023FFFFFFC9FE42BA298E2293A80096742000000000000000000000000000000003FFFFFFC9FE4B19298E3181E8009436A;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'h9FE8234A88F836EE9FF8BD4208282BC080DE87C2B84199C2B85E37C2B05B3A829FE8236688F837CE9FF8898208A82A44808A87CAB9C19DC2B80E3AC2927F2AC2800833E288F837C69FE8AB9688882E4283248DC2B9D188C2ABAE2F8291371092800832EA887807C69FE8AB8688080AC283E49D42B914BFC2A3BF1E82910712EA800802EA883807869DE88E8688080AC68BC4BDC2BB1439C2A27F5F82910314E2800886E6880807C69CC89A8681800BC289549CC2AB0C3942A04B7F82953315E2800886EE900805C61C089FC081E415C289D89DC2AB4E3142A1233D8217330090800086EE900805821C08BEC080D407C289C89DC2AADE3142A13B7F82176300F0;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h076B0A5083288F028370C182A801468297E5AC1288D308023FFFFFFC00000000072BA9608BA08D028BF4D182AC015682937CA80288D308023FFFFFFC00000002872B892A8FA08F028A14509AAC0166B2B37DA80288D10D02800000027FFFFFFE852BAD128E388D028A004082AC0166C2937DA00288D10F02C00000027FFFFFFE846289368968C90289E0528A8C016CA29379B20280510F02FFFFFFFE0000000085E2A922816089828BE0428286416C829179B00280511F027FFFFFFC0000000087EA8B32872089828800569287436CA28179B20200513F0000000000FFFFFFFF8768A3028610858288004682874364828019900200403E0000000000FFFFFFFF;
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X33_Y4_N0
|
|
cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a4 (
|
|
.portawe(vcc),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(!\z80_|address_pins_|abus[13]~20_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain(1'b0),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\rom|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .clk0_core_clock_enable = "ena0";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_offset_in_bits = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .data_interleave_width_in_bits = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file = "./rom/gw03.hex";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .init_file_layout = "port_a";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .operation_mode = "rom";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_clear = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_address_width = 13;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_byte_enable_clock = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clear = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_out_clock = "clock0";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_data_width = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_address = 0;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_first_bit_number = 4;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_last_address = 8191;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_depth = 16384;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_logical_ram_width = 8;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_a_write_enable_clock = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_address_width = 13;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .port_b_data_width = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .ram_block_type = "M9K";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init3 = 2048'h35861A00A6112A1481AF1A50A6004A05291627227FF08229B87389E08119A28A7888672DC999B7046A61E60810A7434450E3D33E330F321A18E8A120D1EDC8623DA2C64840C2CCE811522B42008095E5A456C98F4B25EAEA410610545024640CF10410AC463BF9349074917E9A74A12830EFA280EBD3131E484A255D0191C6852730A263DBCCAAA88712242B3BE49AA5338990229B391158C726BC7EB4ECC32308980020680249882691A680488292310B4313CE87FFCD5329A64B708CAC8533316412C4900F646A36630261DA093053D98F19D2C5B653165D4A71AA5682B29B89B6054CC727D292805705A93268676A31111371390B240EC3CC85D331813EB1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init2 = 2048'h1AA1C248D293110CB951445117D9B6AA500F65068B8CC508BD00184F8705B010A0CC46CC9302649242CE08191634113154562B149100204551178DE805D98EC8A2E5A64B241400267194CD524499BC01D31058CD18684A817A5800B65143281C1310B00A49902C0104004C654E0582040001103654011012021912281216B000C653A0510A1B00C36AC88058CAC126E14E198DFB07E81C3F41510BB08F8F851C3B9AF0147BC1F730B4E91D9D11C3A8F1B82DF19988ACC44072FDB17B4D81882E9DD952B29003D7767BA581A68BC41C2B16AD6EB57F1D048CD4E464190D25ADF2C194E3598360AFB031A1690F4625BB628363B4C90A400E3A04DAA70DA0CC4776;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init1 = 2048'hC82B30671933680037A65978674DDEC2D30EEEDA78F5F2A1DEE660FFEA11B175DCB42E9277212A58842051A078007109A0D820166B881042600284403143048295D23A0E191EBC2134B833D53D37E42B05018289A10300A188E315CE98640F548A370D60A0AA3E7288A0B0869FA5E703D1AE17C0EC276B2AFB747B550A8B41021620D1A60A901095D12A0973B95E20838001330138951361967847D42901910A3488480610A91A851E84FF08783F81AEA52D2FDC2200BD2FE81C0357FBEC1D875686C6CA41B2224C88D8456C1DBF20D820A6649774CB11B69933246E9739C998470542C2E3C783A4C24767084C52DC209D60E95DBC096D9A0171A12D5AB99BAB;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a4 .mem_init0 = 2048'h17A24D2C636ED2478B5AE1C99D40761B1E7AA6A89DDD1BBD8DBD223E70531BCDE90C8E38C8E0478AD8B388F94891C9673A50BC32478E083074657E8E0EA53BEE861F8BC1993560946D92D1C0C7F046A245B5849CB751FF15B97FCD50BC7B8524C13E7C640F3645082248D1CC14296E30DEA3057B35C641762CD00D40DABC27472251A60725008AAA056591C4000BB48C0BC29B8034A03400027B84769B520D9196968460CA3388A03ECB45F2C4B70F1829221000FFFC7FEC346F079F13079798EC2A08157331C6CC0E30884244916A0DE26D4D22454091290404A492016887E2111F830F9851184101370588A06D3BF9AE621A5F4E632A6799C83EFAAE06769D;
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y10_N24
|
|
cycloneive_lcell_comb \Selector4~0 (
|
|
// Equation(s):
|
|
// \Selector4~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\Selector3~0_combout ) # ((\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout )))) # (!\z80_|address_pins_|abus[14]~23_combout & (!\Selector3~0_combout &
|
|
// ((\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ))))
|
|
|
|
.dataa(\z80_|address_pins_|abus[14]~23_combout ),
|
|
.datab(\Selector3~0_combout ),
|
|
.datac(\ram0|altsyncram_component|auto_generated|ram_block1a4~portadataout ),
|
|
.datad(\rom|altsyncram_component|auto_generated|ram_block1a4~portadataout ),
|
|
.cin(gnd),
|
|
.combout(\Selector4~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \Selector4~0 .lut_mask = 16'hB9A8;
|
|
defparam \Selector4~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y10_N14
|
|
cycloneive_lcell_comb \Selector4~1 (
|
|
// Equation(s):
|
|
// \Selector4~1_combout = (\Selector3~0_combout & ((\Selector4~0_combout & ((\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ))) # (!\Selector4~0_combout & (\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout )))) #
|
|
// (!\Selector3~0_combout & (((\Selector4~0_combout ))))
|
|
|
|
.dataa(\rom|altsyncram_component|auto_generated|ram_block1a12~portadataout ),
|
|
.datab(\Selector3~0_combout ),
|
|
.datac(\ram0|altsyncram_component|auto_generated|ram_block1a12~portadataout ),
|
|
.datad(\Selector4~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\Selector4~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \Selector4~1 .lut_mask = 16'hF388;
|
|
defparam \Selector4~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y10_N10
|
|
cycloneive_lcell_comb \D[4]~86 (
|
|
// Equation(s):
|
|
// \D[4]~86_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Selector4~1_combout
|
|
// ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ))))
|
|
|
|
.dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.datab(\z80_|address_pins_|DFFE_apin_latch [15]),
|
|
.datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[4]~9_combout ),
|
|
.datad(\Selector4~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[4]~86_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[4]~86 .lut_mask = 16'hF2D0;
|
|
defparam \D[4]~86 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y10_N16
|
|
cycloneive_lcell_comb \D[4]~75 (
|
|
// Equation(s):
|
|
// \D[4]~75_combout = ((\Equal2~0_combout & (\D[4]~64_combout )) # (!\Equal2~0_combout & ((\D[4]~86_combout )))) # (!\Equal2~1_combout )
|
|
|
|
.dataa(\Equal2~1_combout ),
|
|
.datab(\D[4]~64_combout ),
|
|
.datac(\Equal2~0_combout ),
|
|
.datad(\D[4]~86_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[4]~75_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[4]~75 .lut_mask = 16'hDFD5;
|
|
defparam \D[4]~75 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y10_N30
|
|
cycloneive_lcell_comb \D[4]~76 (
|
|
// Equation(s):
|
|
// \D[4]~76_combout = (\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\z80_|data_pins_|dout [4] & \D[4]~75_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\D[4]~75_combout )) # (!\Equal2~1_combout )))
|
|
|
|
.dataa(\Equal2~1_combout ),
|
|
.datab(\z80_|data_pins_|dout [4]),
|
|
.datac(\z80_|pin_control_|bus_db_pin_oe~15_combout ),
|
|
.datad(\D[4]~75_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[4]~76_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[4]~76 .lut_mask = 16'hCF05;
|
|
defparam \D[4]~76 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y13_N30
|
|
cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] (
|
|
// Equation(s):
|
|
// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [4] = (\z80_|bus_control_|db[4]~19_combout & ((\z80_|execute_|ctl_bus_db_we~7_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[4]~76_combout )))) # (!\z80_|bus_control_|db[4]~19_combout &
|
|
// (\z80_|pin_control_|bus_db_pin_re~combout & ((\D[4]~76_combout ))))
|
|
|
|
.dataa(\z80_|bus_control_|db[4]~19_combout ),
|
|
.datab(\z80_|pin_control_|bus_db_pin_re~combout ),
|
|
.datac(\z80_|execute_|ctl_bus_db_we~7_combout ),
|
|
.datad(\D[4]~76_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [4]),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] .lut_mask = 16'hECA0;
|
|
defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[4] .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X30_Y13_N31
|
|
dffeas \z80_|data_pins_|dout[4] (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [4]),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|data_pins_|dout [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|data_pins_|dout[4] .is_wysiwyg = "true";
|
|
defparam \z80_|data_pins_|dout[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y13_N24
|
|
cycloneive_lcell_comb \z80_|bus_control_|db[4]~18 (
|
|
// Equation(s):
|
|
// \z80_|bus_control_|db[4]~18_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))
|
|
|
|
.dataa(\z80_|bus_control_|db[0]~4_combout ),
|
|
.datab(\z80_|data_pins_|dout [4]),
|
|
.datac(gnd),
|
|
.datad(\z80_|execute_|ctl_bus_db_oe~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|bus_control_|db[4]~18_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|bus_control_|db[4]~18 .lut_mask = 16'h88AA;
|
|
defparam \z80_|bus_control_|db[4]~18 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y17_N0
|
|
cycloneive_lcell_comb \z80_|bus_control_|db[4]~19 (
|
|
// Equation(s):
|
|
// \z80_|bus_control_|db[4]~19_combout = ((\z80_|bus_control_|db[4]~18_combout & ((\z80_|alu_control_|db[4]~32_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout )
|
|
|
|
.dataa(\z80_|bus_control_|db[0]~6_combout ),
|
|
.datab(\z80_|bus_control_|db[4]~18_combout ),
|
|
.datac(\z80_|alu_control_|db[4]~32_combout ),
|
|
.datad(\z80_|execute_|ctl_bus_db_we~7_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|bus_control_|db[4]~19_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|bus_control_|db[4]~19 .lut_mask = 16'hD5DD;
|
|
defparam \z80_|bus_control_|db[4]~19 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X30_Y17_N1
|
|
dffeas \z80_|ir_|opcode[4] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|bus_control_|db[4]~19_combout ),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|execute_|ctl_ir_we~13_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|ir_|opcode [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|ir_|opcode[4] .is_wysiwyg = "true";
|
|
defparam \z80_|ir_|opcode[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y17_N18
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal32~0 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal32~0_combout = (!\z80_|ir_|opcode [4] & \z80_|ir_|opcode [3])
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|ir_|opcode [4]),
|
|
.datac(gnd),
|
|
.datad(\z80_|ir_|opcode [3]),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal32~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal32~0 .lut_mask = 16'h3300;
|
|
defparam \z80_|pla_decode_|Equal32~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y16_N18
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal41~1 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal41~1_combout = (\z80_|ir_|opcode [7] & (\z80_|ir_|opcode [6] & ((\z80_|decode_state_|DFFE_instIY1~q ) # (\z80_|decode_state_|DFFE_inst4~q ))))
|
|
|
|
.dataa(\z80_|decode_state_|DFFE_instIY1~q ),
|
|
.datab(\z80_|decode_state_|DFFE_inst4~q ),
|
|
.datac(\z80_|ir_|opcode [7]),
|
|
.datad(\z80_|ir_|opcode [6]),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal41~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal41~1 .lut_mask = 16'hE000;
|
|
defparam \z80_|pla_decode_|Equal41~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y17_N12
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal41~2 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal41~2_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal32~0_combout & (\z80_|pla_decode_|Equal41~1_combout & \z80_|pla_decode_|Equal8~0_combout )))
|
|
|
|
.dataa(\z80_|ir_|opcode [5]),
|
|
.datab(\z80_|pla_decode_|Equal32~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal41~1_combout ),
|
|
.datad(\z80_|pla_decode_|Equal8~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal41~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal41~2 .lut_mask = 16'h4000;
|
|
defparam \z80_|pla_decode_|Equal41~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y17_N6
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal36~0 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal36~0_combout = (!\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal2~0_combout & (\z80_|pla_decode_|Equal1~7_combout & \z80_|pla_decode_|Equal32~0_combout )))
|
|
|
|
.dataa(\z80_|ir_|opcode [5]),
|
|
.datab(\z80_|pla_decode_|Equal2~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal1~7_combout ),
|
|
.datad(\z80_|pla_decode_|Equal32~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal36~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal36~0 .lut_mask = 16'h4000;
|
|
defparam \z80_|pla_decode_|Equal36~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y13_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_cb_set (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_state_tbl_cb_set~combout = (\z80_|resets_|SYNTHESIZED_WIRE_11~combout & (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal41~2_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout &
|
|
// ((\z80_|pla_decode_|Equal36~0_combout ) # ((\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & \z80_|pla_decode_|Equal41~2_combout ))))
|
|
|
|
.dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ),
|
|
.datab(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ),
|
|
.datac(\z80_|pla_decode_|Equal41~2_combout ),
|
|
.datad(\z80_|pla_decode_|Equal36~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_state_tbl_cb_set~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_state_tbl_cb_set .lut_mask = 16'hD5C0;
|
|
defparam \z80_|execute_|ctl_state_tbl_cb_set .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y13_N2
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_we~8 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_state_tbl_we~8_combout = (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q ) # ((\z80_|sequencer_|DFFE_T3_ff~q & \z80_|pla_decode_|Equal41~2_combout ))))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.datab(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.datac(\z80_|pla_decode_|Equal41~2_combout ),
|
|
.datad(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_state_tbl_we~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_state_tbl_we~8 .lut_mask = 16'h00EC;
|
|
defparam \z80_|execute_|ctl_state_tbl_we~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X29_Y13_N9
|
|
dffeas \z80_|decode_state_|DFFE_instCB (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|execute_|ctl_state_tbl_cb_set~combout ),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|execute_|ctl_state_tbl_we~8_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|decode_state_|DFFE_instCB~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|decode_state_|DFFE_instCB .is_wysiwyg = "true";
|
|
defparam \z80_|decode_state_|DFFE_instCB .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y16_N2
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal52~0 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal52~0_combout = (!\z80_|decode_state_|DFFE_instCB~q & (!\z80_|decode_state_|DFFE_instED~q & (\z80_|ir_|opcode [7] & \z80_|ir_|opcode [6])))
|
|
|
|
.dataa(\z80_|decode_state_|DFFE_instCB~q ),
|
|
.datab(\z80_|decode_state_|DFFE_instED~q ),
|
|
.datac(\z80_|ir_|opcode [7]),
|
|
.datad(\z80_|ir_|opcode [6]),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal52~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal52~0 .lut_mask = 16'h1000;
|
|
defparam \z80_|pla_decode_|Equal52~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y16_N16
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal2~1 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal2~1_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|ir_|opcode [0] & \z80_|pla_decode_|Equal32~0_combout )))
|
|
|
|
.dataa(\z80_|ir_|opcode [5]),
|
|
.datab(\z80_|pla_decode_|Equal52~0_combout ),
|
|
.datac(\z80_|ir_|opcode [0]),
|
|
.datad(\z80_|pla_decode_|Equal32~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal2~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal2~1 .lut_mask = 16'h8000;
|
|
defparam \z80_|pla_decode_|Equal2~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y13_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_state_tbl_ed_set (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_state_tbl_ed_set~combout = (\z80_|ir_|opcode [2] & (\z80_|pla_decode_|Equal2~1_combout & (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout & !\z80_|ir_|opcode [1])))
|
|
|
|
.dataa(\z80_|ir_|opcode [2]),
|
|
.datab(\z80_|pla_decode_|Equal2~1_combout ),
|
|
.datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ),
|
|
.datad(\z80_|ir_|opcode [1]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_state_tbl_ed_set~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_state_tbl_ed_set .lut_mask = 16'h0008;
|
|
defparam \z80_|execute_|ctl_state_tbl_ed_set .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X29_Y13_N13
|
|
dffeas \z80_|decode_state_|DFFE_instED (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|execute_|ctl_state_tbl_ed_set~combout ),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|execute_|ctl_state_tbl_we~8_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|decode_state_|DFFE_instED~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|decode_state_|DFFE_instED .is_wysiwyg = "true";
|
|
defparam \z80_|decode_state_|DFFE_instED .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y13_N26
|
|
cycloneive_lcell_comb \z80_|decode_state_|table_xx~0 (
|
|
// Equation(s):
|
|
// \z80_|decode_state_|table_xx~0_combout = (\z80_|decode_state_|DFFE_instED~q ) # (\z80_|decode_state_|DFFE_instCB~q )
|
|
|
|
.dataa(\z80_|decode_state_|DFFE_instED~q ),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|decode_state_|DFFE_instCB~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|decode_state_|table_xx~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|decode_state_|table_xx~0 .lut_mask = 16'hFFAA;
|
|
defparam \z80_|decode_state_|table_xx~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y13_N24
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal34~0 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal34~0_combout = (!\z80_|ir_|opcode [0] & (!\z80_|decode_state_|table_xx~0_combout & (\z80_|pla_decode_|Equal3~1_combout & \z80_|pla_decode_|Equal41~0_combout )))
|
|
|
|
.dataa(\z80_|ir_|opcode [0]),
|
|
.datab(\z80_|decode_state_|table_xx~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal3~1_combout ),
|
|
.datad(\z80_|pla_decode_|Equal41~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal34~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal34~0 .lut_mask = 16'h1000;
|
|
defparam \z80_|pla_decode_|Equal34~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y16_N6
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~6 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sel_pc~6_combout = (\z80_|execute_|ctl_alu_op_low~22_combout & (!\z80_|execute_|ixy_d~16_combout & ((!\z80_|execute_|ixy_d~5_combout ) # (!\z80_|pla_decode_|Equal34~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~22_combout &
|
|
// (((!\z80_|execute_|ixy_d~5_combout )) # (!\z80_|pla_decode_|Equal34~0_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op_low~22_combout ),
|
|
.datab(\z80_|pla_decode_|Equal34~0_combout ),
|
|
.datac(\z80_|execute_|ixy_d~16_combout ),
|
|
.datad(\z80_|execute_|ixy_d~5_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sel_pc~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sel_pc~6 .lut_mask = 16'h135F;
|
|
defparam \z80_|execute_|ctl_reg_sel_pc~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y16_N28
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~5 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sel_pc~5_combout = ((!\z80_|execute_|ctl_mRead~6_combout & (!\z80_|execute_|ctl_mRead~7_combout & !\z80_|execute_|ctl_mRead~15_combout ))) # (!\z80_|execute_|ixy_d~5_combout )
|
|
|
|
.dataa(\z80_|execute_|ixy_d~5_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~6_combout ),
|
|
.datac(\z80_|execute_|ctl_mRead~7_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~15_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sel_pc~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sel_pc~5 .lut_mask = 16'h5557;
|
|
defparam \z80_|execute_|ctl_reg_sel_pc~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y16_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sel_pc~4_combout = ((!\z80_|execute_|ixy_d~10_combout & ((!\z80_|pla_decode_|Equal24~0_combout ) # (!\z80_|pla_decode_|Equal21~0_combout )))) # (!\z80_|execute_|ctl_alu_op_low~22_combout )
|
|
|
|
.dataa(\z80_|execute_|ixy_d~10_combout ),
|
|
.datab(\z80_|pla_decode_|Equal21~0_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_op_low~22_combout ),
|
|
.datad(\z80_|pla_decode_|Equal24~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sel_pc~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sel_pc~4 .lut_mask = 16'h1F5F;
|
|
defparam \z80_|execute_|ctl_reg_sel_pc~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y16_N16
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sel_pc~2_combout = ((!\z80_|execute_|ctl_mRead~13_combout & ((\z80_|pla_decode_|Equal12~1_combout ) # (!\z80_|pla_decode_|Equal25~0_combout )))) # (!\z80_|execute_|ixy_d~5_combout )
|
|
|
|
.dataa(\z80_|execute_|ixy_d~5_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~13_combout ),
|
|
.datac(\z80_|pla_decode_|Equal12~1_combout ),
|
|
.datad(\z80_|pla_decode_|Equal25~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sel_pc~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sel_pc~2 .lut_mask = 16'h7577;
|
|
defparam \z80_|execute_|ctl_reg_sel_pc~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y16_N18
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~3 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sel_pc~3_combout = (\z80_|execute_|ctl_reg_sel_pc~2_combout & (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|execute_|ctl_mRead~8_combout )) # (!\z80_|execute_|ixy_d~5_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal19~0_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_sel_pc~2_combout ),
|
|
.datac(\z80_|execute_|ctl_mRead~8_combout ),
|
|
.datad(\z80_|execute_|ixy_d~5_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sel_pc~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sel_pc~3 .lut_mask = 16'h04CC;
|
|
defparam \z80_|execute_|ctl_reg_sel_pc~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y16_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~7 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sel_pc~7_combout = (\z80_|execute_|ctl_reg_sel_pc~6_combout & (\z80_|execute_|ctl_reg_sel_pc~5_combout & (\z80_|execute_|ctl_reg_sel_pc~4_combout & \z80_|execute_|ctl_reg_sel_pc~3_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_sel_pc~6_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_sel_pc~5_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_sel_pc~4_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sel_pc~3_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sel_pc~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sel_pc~7 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|ctl_reg_sel_pc~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y16_N2
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~8 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sel_pc~8_combout = (\z80_|pla_decode_|Equal12~1_combout & (((\z80_|pla_decode_|Equal3~0_combout & \z80_|pla_decode_|Equal24~0_combout )))) # (!\z80_|pla_decode_|Equal12~1_combout & ((\z80_|pla_decode_|Equal25~0_combout ) #
|
|
// ((\z80_|pla_decode_|Equal3~0_combout & \z80_|pla_decode_|Equal24~0_combout ))))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal12~1_combout ),
|
|
.datab(\z80_|pla_decode_|Equal25~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal3~0_combout ),
|
|
.datad(\z80_|pla_decode_|Equal24~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sel_pc~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sel_pc~8 .lut_mask = 16'hF444;
|
|
defparam \z80_|execute_|ctl_reg_sel_pc~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y16_N26
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~9 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sel_pc~9_combout = (\z80_|execute_|ctl_alu_op_low~22_combout & ((\z80_|execute_|ctl_mRead~15_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~8_combout ) # (\z80_|pla_decode_|Equal34~0_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op_low~22_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~15_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_sel_pc~8_combout ),
|
|
.datad(\z80_|pla_decode_|Equal34~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sel_pc~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sel_pc~9 .lut_mask = 16'hAAA8;
|
|
defparam \z80_|execute_|ctl_reg_sel_pc~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y16_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~10 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sel_pc~10_combout = (\z80_|execute_|ctl_reg_sel_pc~7_combout & (!\z80_|execute_|ctl_reg_sel_pc~9_combout & ((!\z80_|pla_decode_|Equal41~2_combout ) # (!\z80_|execute_|ixy_d~5_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ixy_d~5_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_sel_pc~7_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_sel_pc~9_combout ),
|
|
.datad(\z80_|pla_decode_|Equal41~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sel_pc~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sel_pc~10 .lut_mask = 16'h040C;
|
|
defparam \z80_|execute_|ctl_reg_sel_pc~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y12_N14
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~16 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sel_pc~16_combout = (((\z80_|execute_|ctl_state_alu~3_combout & !\z80_|execute_|fMRead~4_combout )) # (!\z80_|execute_|ctl_apin_mux~0_combout )) # (!\z80_|execute_|ctl_reg_sel_pc~10_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_sel_pc~10_combout ),
|
|
.datab(\z80_|execute_|ctl_apin_mux~0_combout ),
|
|
.datac(\z80_|execute_|ctl_state_alu~3_combout ),
|
|
.datad(\z80_|execute_|fMRead~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sel_pc~16_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sel_pc~16 .lut_mask = 16'h77F7;
|
|
defparam \z80_|execute_|ctl_reg_sel_pc~16 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y17_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~17 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sel_pc~17_combout = (\z80_|nM1_int~2_combout ) # ((\z80_|execute_|ctl_reg_sys_we~0_combout ) # ((!\z80_|execute_|ctl_sw_4u~1_combout ) # (!\z80_|execute_|ctl_inc_dec~12_combout )))
|
|
|
|
.dataa(\z80_|nM1_int~2_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_sys_we~0_combout ),
|
|
.datac(\z80_|execute_|ctl_inc_dec~12_combout ),
|
|
.datad(\z80_|execute_|ctl_sw_4u~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sel_pc~17_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sel_pc~17 .lut_mask = 16'hEFFF;
|
|
defparam \z80_|execute_|ctl_reg_sel_pc~17 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y11_N0
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~15 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sel_pc~15_combout = (\z80_|execute_|ctl_reg_sel_pc~19_combout ) # ((!\z80_|execute_|fMRead~2_combout & ((!\z80_|execute_|ctl_reg_sel_pc~14_combout ) # (!\z80_|execute_|setM1~38_combout ))))
|
|
|
|
.dataa(\z80_|execute_|setM1~38_combout ),
|
|
.datab(\z80_|execute_|fMRead~2_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_sel_pc~14_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sel_pc~19_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sel_pc~15_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sel_pc~15 .lut_mask = 16'hFF13;
|
|
defparam \z80_|execute_|ctl_reg_sel_pc~15 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y12_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_pc~18 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sel_pc~18_combout = (\z80_|execute_|ctl_reg_sel_pc~16_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~17_combout ) # ((\z80_|execute_|ctl_reg_sel_pc~15_combout ) # (!\z80_|execute_|ctl_reg_sel_pc~13_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_sel_pc~16_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_sel_pc~17_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_sel_pc~13_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sel_pc~15_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sel_pc~18_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sel_pc~18 .lut_mask = 16'hFFEF;
|
|
defparam \z80_|execute_|ctl_reg_sel_pc~18 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X20_Y18_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_sel_wz~19 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_sel_wz~19_combout = (((!\z80_|pla_decode_|Equal19~0_combout & !\z80_|pla_decode_|Equal34~0_combout )) # (!\z80_|sequencer_|M5~q )) # (!\z80_|sequencer_|DFFE_T3_ff~q )
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.datab(\z80_|pla_decode_|Equal19~0_combout ),
|
|
.datac(\z80_|sequencer_|M5~q ),
|
|
.datad(\z80_|pla_decode_|Equal34~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_sel_wz~19_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_sel_wz~19 .lut_mask = 16'h5F7F;
|
|
defparam \z80_|execute_|ctl_reg_sel_wz~19 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y14_N20
|
|
cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc~3 (
|
|
// Equation(s):
|
|
// \z80_|reg_control_|reg_sel_pc~3_combout = (!\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout & (\z80_|execute_|ctl_reg_sel_wz~19_combout & (\z80_|reg_control_|reg_sel_pc~2_combout & \z80_|execute_|ctl_alu_sel_op2_neg~2_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_hilo_pla6M1T4_4~combout ),
|
|
.datab(\z80_|execute_|ctl_reg_sel_wz~19_combout ),
|
|
.datac(\z80_|reg_control_|reg_sel_pc~2_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_sel_op2_neg~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_control_|reg_sel_pc~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_control_|reg_sel_pc~3 .lut_mask = 16'h4000;
|
|
defparam \z80_|reg_control_|reg_sel_pc~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y12_N24
|
|
cycloneive_lcell_comb \z80_|reg_control_|reg_sel_pc (
|
|
// Equation(s):
|
|
// \z80_|reg_control_|reg_sel_pc~combout = (\z80_|execute_|ctl_reg_sel_pc~18_combout & (!\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & (!\z80_|execute_|ctl_reg_sel_wz~20_combout & \z80_|reg_control_|reg_sel_pc~3_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_sel_pc~18_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ),
|
|
.datac(\z80_|execute_|ctl_reg_sel_wz~20_combout ),
|
|
.datad(\z80_|reg_control_|reg_sel_pc~3_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_control_|reg_sel_pc~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_control_|reg_sel_pc .lut_mask = 16'h0200;
|
|
defparam \z80_|reg_control_|reg_sel_pc .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y12_N24
|
|
cycloneive_lcell_comb \z80_|reg_file_|SYNTHESIZED_WIRE_72 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|SYNTHESIZED_WIRE_72~combout = (\z80_|reg_control_|reg_sel_pc~combout & (!\z80_|reg_control_|reg_sys_we_hi~combout & \z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ))
|
|
|
|
.dataa(\z80_|reg_control_|reg_sel_pc~combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|reg_control_|reg_sys_we_hi~combout ),
|
|
.datad(\z80_|execute_|ctl_reg_sys_hilo[1]~35_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .lut_mask = 16'h0A00;
|
|
defparam \z80_|reg_file_|SYNTHESIZED_WIRE_72 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y14_N10
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[0]~2 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_hi_as[0]~2_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ) # ((\z80_|reg_control_|reg_sw_4d_hi~0_combout ) # ((\z80_|execute_|ctl_bus_inc_oe~43_combout ) # (\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ),
|
|
.datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ),
|
|
.datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_hi_as[0]~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_hi_as[0]~2 .lut_mask = 16'hFFFE;
|
|
defparam \z80_|reg_file_|db_hi_as[0]~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y14_N23
|
|
dffeas \z80_|reg_file_|b2v_latch_pc_hi|latch[5] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_file_|db_hi_as[5]~15_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_73~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_pc_hi|latch[5] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y14_N17
|
|
dffeas \z80_|reg_file_|b2v_latch_ir_hi|latch[5] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|db_hi_as[5]~15_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_61~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_ir_hi|latch[5] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y14_N16
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~13 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_hi_as[5]~13_combout = (\z80_|reg_file_|gdfx_temp1[5]~57_combout & (((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout )))) # (!\z80_|reg_file_|gdfx_temp1[5]~57_combout &
|
|
// (!\z80_|reg_control_|reg_sw_4d_hi~0_combout & ((\z80_|reg_file_|b2v_latch_ir_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|gdfx_temp1[5]~57_combout ),
|
|
.datab(\z80_|reg_control_|reg_sw_4d_hi~0_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_ir_hi|latch [5]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_60~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_hi_as[5]~13_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_hi_as[5]~13 .lut_mask = 16'hB0BB;
|
|
defparam \z80_|reg_file_|db_hi_as[5]~13 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y14_N28
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~14 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_hi_as[5]~14_combout = (\z80_|reg_file_|db_hi_as[5]~13_combout & ((\z80_|reg_file_|b2v_latch_pc_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_72~combout ),
|
|
.datab(\z80_|reg_file_|b2v_latch_pc_hi|latch [5]),
|
|
.datac(gnd),
|
|
.datad(\z80_|reg_file_|db_hi_as[5]~13_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_hi_as[5]~14_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_hi_as[5]~14 .lut_mask = 16'hDD00;
|
|
defparam \z80_|reg_file_|db_hi_as[5]~14 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y14_N22
|
|
cycloneive_lcell_comb \z80_|reg_file_|db_hi_as[5]~15 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|db_hi_as[5]~15_combout = ((\z80_|reg_file_|db_hi_as[5]~14_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ) # (!\z80_|execute_|ctl_bus_inc_oe~43_combout )))) # (!\z80_|reg_file_|db_hi_as[0]~2_combout )
|
|
|
|
.dataa(\z80_|reg_file_|db_hi_as[0]~2_combout ),
|
|
.datab(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_10|d1_out~combout ),
|
|
.datac(\z80_|execute_|ctl_bus_inc_oe~43_combout ),
|
|
.datad(\z80_|reg_file_|db_hi_as[5]~14_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|db_hi_as[5]~15_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|db_hi_as[5]~15 .lut_mask = 16'hDF55;
|
|
defparam \z80_|reg_file_|db_hi_as[5]~15 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y14_N9
|
|
dffeas \z80_|reg_file_|b2v_latch_hl_hi|latch[5] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_57~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_hl_hi|latch[5] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y14_N23
|
|
dffeas \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_53~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_hl2_hi|latch[5] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y14_N22
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~50 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[5]~50_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (\z80_|reg_file_|b2v_latch_hl_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout & (((\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_56~combout ),
|
|
.datab(\z80_|reg_file_|b2v_latch_hl_hi|latch [5]),
|
|
.datac(\z80_|reg_file_|b2v_latch_hl2_hi|latch [5]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_52~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[5]~50_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[5]~50 .lut_mask = 16'hD0DD;
|
|
defparam \z80_|reg_file_|gdfx_temp1[5]~50 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y16_N13
|
|
dffeas \z80_|reg_file_|b2v_latch_af2_hi|latch[5] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_29~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_af2_hi|latch[5] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y16_N12
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~53 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[5]~53_combout = (\z80_|execute_|ctl_reg_in_hi~12_combout & (\z80_|alu_|db[5]~24_combout & ((\z80_|reg_file_|b2v_latch_af2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout )))) #
|
|
// (!\z80_|execute_|ctl_reg_in_hi~12_combout & (((\z80_|reg_file_|b2v_latch_af2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_in_hi~12_combout ),
|
|
.datab(\z80_|alu_|db[5]~24_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_af2_hi|latch [5]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_28~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[5]~53_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[5]~53 .lut_mask = 16'hD0DD;
|
|
defparam \z80_|reg_file_|gdfx_temp1[5]~53 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y15_N19
|
|
dffeas \z80_|reg_file_|b2v_latch_sp_hi|latch[5] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_file_|gdfx_temp1[5]~57_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_77~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_sp_hi|latch[5] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y15_N17
|
|
dffeas \z80_|reg_file_|b2v_latch_wz_hi|latch[5] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_81~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_wz_hi|latch[5] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y15_N16
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~54 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[5]~54_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & (\z80_|reg_file_|b2v_latch_wz_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout & ((\z80_|reg_file_|b2v_latch_sp_hi|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_80~combout ),
|
|
.datab(\z80_|reg_file_|b2v_latch_sp_hi|latch [5]),
|
|
.datac(\z80_|reg_file_|b2v_latch_wz_hi|latch [5]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_76~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[5]~54_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[5]~54 .lut_mask = 16'hC4F5;
|
|
defparam \z80_|reg_file_|gdfx_temp1[5]~54 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y16_N3
|
|
dffeas \z80_|reg_file_|b2v_latch_ix_hi|latch[5] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_65~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_ix_hi|latch[5] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y16_N21
|
|
dffeas \z80_|reg_file_|b2v_latch_iy_hi|latch[5] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_69~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_iy_hi|latch[5] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y16_N2
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~52 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[5]~52_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (\z80_|reg_file_|b2v_latch_iy_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_ix_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout & (((\z80_|reg_file_|b2v_latch_ix_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_68~combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_64~0_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_ix_hi|latch [5]),
|
|
.datad(\z80_|reg_file_|b2v_latch_iy_hi|latch [5]),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[5]~52_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[5]~52 .lut_mask = 16'hF351;
|
|
defparam \z80_|reg_file_|gdfx_temp1[5]~52 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y16_N5
|
|
dffeas \z80_|reg_file_|b2v_latch_bc_hi|latch[5] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_41~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_bc_hi|latch[5] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y16_N19
|
|
dffeas \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_37~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_bc2_hi|latch[5] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y16_N18
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~51 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[5]~51_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & (\z80_|reg_file_|b2v_latch_bc2_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout & ((\z80_|reg_file_|b2v_latch_bc_hi|latch [5]) # ((!\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ))))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_36~0_combout ),
|
|
.datab(\z80_|reg_file_|b2v_latch_bc_hi|latch [5]),
|
|
.datac(\z80_|reg_file_|b2v_latch_bc2_hi|latch [5]),
|
|
.datad(\z80_|reg_file_|SYNTHESIZED_WIRE_40~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[5]~51_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[5]~51 .lut_mask = 16'hC4F5;
|
|
defparam \z80_|reg_file_|gdfx_temp1[5]~51 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y16_N0
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~55 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[5]~55_combout = (\z80_|reg_file_|gdfx_temp1[5]~53_combout & (\z80_|reg_file_|gdfx_temp1[5]~54_combout & (\z80_|reg_file_|gdfx_temp1[5]~52_combout & \z80_|reg_file_|gdfx_temp1[5]~51_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|gdfx_temp1[5]~53_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp1[5]~54_combout ),
|
|
.datac(\z80_|reg_file_|gdfx_temp1[5]~52_combout ),
|
|
.datad(\z80_|reg_file_|gdfx_temp1[5]~51_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[5]~55_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[5]~55 .lut_mask = 16'h8000;
|
|
defparam \z80_|reg_file_|gdfx_temp1[5]~55 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X36_Y15_N27
|
|
dffeas \z80_|reg_file_|b2v_latch_af_hi|latch[5] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_33~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_af_hi|latch [5]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_af_hi|latch[5] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y15_N26
|
|
cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout = (\z80_|execute_|ctl_reg_gp_we~8_combout ) # (((\z80_|reg_file_|b2v_latch_af_hi|latch [5]) # (!\z80_|reg_control_|reg_sel_af~0_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_gp_we~8_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_hilo[1]~43_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_af_hi|latch [5]),
|
|
.datad(\z80_|reg_control_|reg_sel_af~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 .lut_mask = 16'hFBFF;
|
|
defparam \z80_|reg_file_|b2v_latch_af_hi|db[5]~14 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y15_N15
|
|
dffeas \z80_|reg_file_|b2v_latch_de2_hi|latch[5] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|reg_file_|gdfx_temp1[5]~57_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_45~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_de2_hi|latch[5] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y15_N28
|
|
cycloneive_lcell_comb \z80_|reg_file_|b2v_latch_de_hi|latch[5]~feeder (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|b2v_latch_de_hi|latch[5]~feeder_combout = \z80_|reg_file_|gdfx_temp1[5]~57_combout
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|reg_file_|gdfx_temp1[5]~57_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|b2v_latch_de_hi|latch[5]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5]~feeder .lut_mask = 16'hFF00;
|
|
defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y15_N29
|
|
dffeas \z80_|reg_file_|b2v_latch_de_hi|latch[5] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|reg_file_|b2v_latch_de_hi|latch[5]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|reg_file_|SYNTHESIZED_WIRE_49~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|reg_file_|b2v_latch_de_hi|latch [5]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .is_wysiwyg = "true";
|
|
defparam \z80_|reg_file_|b2v_latch_de_hi|latch[5] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y15_N14
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~49 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[5]~49_combout = (\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (\z80_|reg_file_|b2v_latch_de_hi|latch [5] & ((\z80_|reg_file_|b2v_latch_de2_hi|latch [5]) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))) #
|
|
// (!\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout & (((\z80_|reg_file_|b2v_latch_de2_hi|latch [5])) # (!\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout )))
|
|
|
|
.dataa(\z80_|reg_file_|SYNTHESIZED_WIRE_48~combout ),
|
|
.datab(\z80_|reg_file_|SYNTHESIZED_WIRE_44~combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_de2_hi|latch [5]),
|
|
.datad(\z80_|reg_file_|b2v_latch_de_hi|latch [5]),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[5]~49_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[5]~49 .lut_mask = 16'hF351;
|
|
defparam \z80_|reg_file_|gdfx_temp1[5]~49 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X38_Y15_N8
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~56 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[5]~56_combout = (\z80_|reg_file_|gdfx_temp1[5]~50_combout & (\z80_|reg_file_|gdfx_temp1[5]~55_combout & (\z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout & \z80_|reg_file_|gdfx_temp1[5]~49_combout )))
|
|
|
|
.dataa(\z80_|reg_file_|gdfx_temp1[5]~50_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp1[5]~55_combout ),
|
|
.datac(\z80_|reg_file_|b2v_latch_af_hi|db[5]~14_combout ),
|
|
.datad(\z80_|reg_file_|gdfx_temp1[5]~49_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[5]~56_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[5]~56 .lut_mask = 16'h8000;
|
|
defparam \z80_|reg_file_|gdfx_temp1[5]~56 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y15_N18
|
|
cycloneive_lcell_comb \z80_|reg_file_|gdfx_temp1[5]~57 (
|
|
// Equation(s):
|
|
// \z80_|reg_file_|gdfx_temp1[5]~57_combout = ((\z80_|reg_file_|gdfx_temp1[5]~56_combout & ((\z80_|reg_file_|db_hi_as[5]~15_combout ) # (!\z80_|execute_|ctl_sw_4u~6_combout )))) # (!\z80_|reg_file_|gdfx_temp1[0]~20_combout )
|
|
|
|
.dataa(\z80_|reg_file_|db_hi_as[5]~15_combout ),
|
|
.datab(\z80_|execute_|ctl_sw_4u~6_combout ),
|
|
.datac(\z80_|reg_file_|gdfx_temp1[0]~20_combout ),
|
|
.datad(\z80_|reg_file_|gdfx_temp1[5]~56_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|reg_file_|gdfx_temp1[5]~57_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|reg_file_|gdfx_temp1[5]~57 .lut_mask = 16'hBF0F;
|
|
defparam \z80_|reg_file_|gdfx_temp1[5]~57 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y15_N14
|
|
cycloneive_lcell_comb \z80_|alu_|db[5]~23 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db[5]~23_combout = (\z80_|alu_control_|db[5]~15_combout & ((\z80_|reg_file_|gdfx_temp1[5]~57_combout ) # ((!\z80_|execute_|ctl_reg_out_hi~7_combout )))) # (!\z80_|alu_control_|db[5]~15_combout & (!\z80_|execute_|ctl_sw_2d~13_combout &
|
|
// ((\z80_|reg_file_|gdfx_temp1[5]~57_combout ) # (!\z80_|execute_|ctl_reg_out_hi~7_combout ))))
|
|
|
|
.dataa(\z80_|alu_control_|db[5]~15_combout ),
|
|
.datab(\z80_|reg_file_|gdfx_temp1[5]~57_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_out_hi~7_combout ),
|
|
.datad(\z80_|execute_|ctl_sw_2d~13_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db[5]~23_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db[5]~23 .lut_mask = 16'h8ACF;
|
|
defparam \z80_|alu_|db[5]~23 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y15_N14
|
|
cycloneive_lcell_comb \z80_|alu_|db[5]~24 (
|
|
// Equation(s):
|
|
// \z80_|alu_|db[5]~24_combout = ((\z80_|alu_|db[5]~23_combout & ((\z80_|alu_|db_high[1]~19_combout ) # (!\z80_|execute_|ctl_alu_oe~11_combout )))) # (!\z80_|alu_|db[7]~9_combout )
|
|
|
|
.dataa(\z80_|alu_|db[5]~23_combout ),
|
|
.datab(\z80_|alu_|db_high[1]~19_combout ),
|
|
.datac(\z80_|alu_|db[7]~9_combout ),
|
|
.datad(\z80_|execute_|ctl_alu_oe~11_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_|db[5]~24_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_|db[5]~24 .lut_mask = 16'h8FAF;
|
|
defparam \z80_|alu_|db[5]~24 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y14_N26
|
|
cycloneive_lcell_comb \z80_|sw1_|db_down[5]~0 (
|
|
// Equation(s):
|
|
// \z80_|sw1_|db_down[5]~0_combout = (\z80_|bus_control_|db[5]~15_combout ) # ((\z80_|execute_|ctl_sw_1d~6_combout & ((\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ) # (!\z80_|execute_|ctl_66_oe~2_combout ))))
|
|
|
|
.dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ),
|
|
.datab(\z80_|execute_|ctl_sw_1d~6_combout ),
|
|
.datac(\z80_|bus_control_|db[5]~15_combout ),
|
|
.datad(\z80_|execute_|ctl_66_oe~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|sw1_|db_down[5]~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|sw1_|db_down[5]~0 .lut_mask = 16'hF8FC;
|
|
defparam \z80_|sw1_|db_down[5]~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y15_N22
|
|
cycloneive_lcell_comb \z80_|alu_flags_|SYNTHESIZED_WIRE_36 (
|
|
// Equation(s):
|
|
// \z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout = (\z80_|execute_|ctl_flags_bus~combout & ((\z80_|alu_control_|db[5]~15_combout ) # ((\z80_|alu_|db_high[1]~19_combout & \z80_|execute_|ctl_flags_alu~15_combout )))) # (!\z80_|execute_|ctl_flags_bus~combout
|
|
// & (\z80_|alu_|db_high[1]~19_combout & (\z80_|execute_|ctl_flags_alu~15_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_bus~combout ),
|
|
.datab(\z80_|alu_|db_high[1]~19_combout ),
|
|
.datac(\z80_|execute_|ctl_flags_alu~15_combout ),
|
|
.datad(\z80_|alu_control_|db[5]~15_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .lut_mask = 16'hEAC0;
|
|
defparam \z80_|alu_flags_|SYNTHESIZED_WIRE_36 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X31_Y15_N23
|
|
dffeas \z80_|alu_flags_|flags_yf (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|alu_flags_|SYNTHESIZED_WIRE_36~combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|execute_|ctl_flags_xy_we~18_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|alu_flags_|flags_yf~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_flags_|flags_yf .is_wysiwyg = "true";
|
|
defparam \z80_|alu_flags_|flags_yf .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y14_N26
|
|
cycloneive_lcell_comb \z80_|alu_control_|db[5]~13 (
|
|
// Equation(s):
|
|
// \z80_|alu_control_|db[5]~13_combout = (\z80_|execute_|ctl_flags_oe~2_combout & (\z80_|alu_flags_|flags_yf~q & ((\z80_|alu_control_|out[6]~2_combout ) # (\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout )))) # (!\z80_|execute_|ctl_flags_oe~2_combout &
|
|
// ((\z80_|alu_control_|out[6]~2_combout ) # ((\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_oe~2_combout ),
|
|
.datab(\z80_|alu_control_|out[6]~2_combout ),
|
|
.datac(\z80_|alu_flags_|flags_yf~q ),
|
|
.datad(\z80_|alu_control_|SYNTHESIZED_WIRE_2~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_control_|db[5]~13_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_control_|db[5]~13 .lut_mask = 16'hF5C4;
|
|
defparam \z80_|alu_control_|db[5]~13 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y14_N8
|
|
cycloneive_lcell_comb \z80_|alu_control_|db[5]~14 (
|
|
// Equation(s):
|
|
// \z80_|alu_control_|db[5]~14_combout = (\z80_|sw1_|db_down[5]~0_combout & (\z80_|alu_control_|db[5]~13_combout & ((\z80_|reg_file_|gdfx_temp0[5]~72_combout ) # (!\z80_|execute_|ctl_reg_out_lo~8_combout ))))
|
|
|
|
.dataa(\z80_|sw1_|db_down[5]~0_combout ),
|
|
.datab(\z80_|alu_control_|db[5]~13_combout ),
|
|
.datac(\z80_|reg_file_|gdfx_temp0[5]~72_combout ),
|
|
.datad(\z80_|execute_|ctl_reg_out_lo~8_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_control_|db[5]~14_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_control_|db[5]~14 .lut_mask = 16'h8088;
|
|
defparam \z80_|alu_control_|db[5]~14 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y14_N14
|
|
cycloneive_lcell_comb \z80_|alu_control_|db[5]~15 (
|
|
// Equation(s):
|
|
// \z80_|alu_control_|db[5]~15_combout = ((\z80_|alu_control_|db[5]~14_combout & ((\z80_|alu_|db[5]~24_combout ) # (!\z80_|execute_|ctl_sw_2u~7_combout )))) # (!\z80_|alu_control_|db[6]~11_combout )
|
|
|
|
.dataa(\z80_|alu_|db[5]~24_combout ),
|
|
.datab(\z80_|execute_|ctl_sw_2u~7_combout ),
|
|
.datac(\z80_|alu_control_|db[5]~14_combout ),
|
|
.datad(\z80_|alu_control_|db[6]~11_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|alu_control_|db[5]~15_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|alu_control_|db[5]~15 .lut_mask = 16'hB0FF;
|
|
defparam \z80_|alu_control_|db[5]~15 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X33_Y17_N0
|
|
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a29 (
|
|
.portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[5]~77_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a29_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .clk0_core_clock_enable = "ena0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .data_interleave_width_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file = "led_patterns.mif";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .init_file_layout = "port_a";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .operation_mode = "single_port";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_byte_enable_clock = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_out_clock = "clock0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_address = 0;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_first_bit_number = 5;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_last_address = 8191;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_depth = 32768;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_logical_ram_width = 8;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .port_b_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .ram_block_type = "M9K";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a29 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X33_Y15_N0
|
|
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a13 (
|
|
.portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[5]~77_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file = "led_patterns.mif";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "single_port";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 32768;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X33_Y19_N0
|
|
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a21 (
|
|
.portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[5]~77_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a21_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .clk0_core_clock_enable = "ena0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .data_interleave_width_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file = "led_patterns.mif";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .init_file_layout = "port_a";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .operation_mode = "single_port";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_byte_enable_clock = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_out_clock = "clock0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_address = 0;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_first_bit_number = 5;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_last_address = 8191;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_depth = 32768;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_logical_ram_width = 8;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .port_b_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .ram_block_type = "M9K";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a21 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X33_Y22_N0
|
|
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a5 (
|
|
.portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[5]~77_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file = "led_patterns.mif";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "single_port";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 32768;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024;
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y21_N28
|
|
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 (
|
|
// Equation(s):
|
|
// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ) #
|
|
// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout &
|
|
// !\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]))))
|
|
|
|
.dataa(\ram1|altsyncram_component|auto_generated|ram_block1a21~portadataout ),
|
|
.datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]),
|
|
.datac(\ram1|altsyncram_component|auto_generated|ram_block1a5~portadataout ),
|
|
.datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
|
|
.cin(gnd),
|
|
.combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 .lut_mask = 16'hCCB8;
|
|
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y21_N18
|
|
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 (
|
|
// Equation(s):
|
|
// \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout &
|
|
// (\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ))))) #
|
|
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ))))
|
|
|
|
.dataa(\ram1|altsyncram_component|auto_generated|ram_block1a29~portadataout ),
|
|
.datab(\ram1|altsyncram_component|auto_generated|ram_block1a13~portadataout ),
|
|
.datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
|
|
.datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~10_combout ),
|
|
.cin(gnd),
|
|
.combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 .lut_mask = 16'hAFC0;
|
|
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X33_Y31_N0
|
|
cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a13 (
|
|
.portawe(vcc),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(\z80_|address_pins_|abus[13]~20_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain(1'b0),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\rom|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file = "./rom/gw03.hex";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "rom";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock0";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_a_write_enable_clock = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h990442000864A0284030400454782424440404007E404808A4005448387E547C8004420800620824402040024A1242124204044008404208420A4A42424A1242020028008000524A024A4A284252446240001000101042000054265C7E0600007FAF5CA001C181BE0C02418447B1D88BAA85409896BC7C0E5FAC2529CB69A4038E2564731F88FE730045956C357C5ECF7EF8591DF2A8ACFFBFEEF268CD9B51238594AF691A9B8640983B7F76AAB97209EA6257389992FFE684926E0B19FA338B8489D73811171D5C9FF3DCFFFFFF8002000780101F3F4035A0CDED99F79A4775854F179F7D7DBBCF81B2F6421FF684CA6AF85894D29B9D3ACCBA3F27D9DC9911;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h5B438D714D4E3DD115E8BD1286EAB5FA1D71BD8F4508BD4BDC8838F9D27B552259BCEFFBB68A6FF529B3B0D92970010BBB6C7D872421210E190E1CCC47A485EAD2F8735647315839EF6F683C64773FC73464D5FE354936D50823A5DAEBEBDBCC6CAFF2622B8D518F63C6030424188FD357718970D25A30CD0731E532DB23002D02C12B12378356DE2C52041CA7A320C51E0D7CA9F5D575775D57FD75DDFDF75FFFDFFFD75F145247F03A0AE7F1E1EB2D5A99D2444108C6A5979B7CC26ABCC241EA4C912568003BB493CE04FF086C188980052BF6ABAAA2FD5D658000011277EB924C10EFAF3CB9B62486512344C61ADE6F15AB67F335A52513FF05AFAEEE8400;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h0C840083AD485153ACD3C035591630199B8C096CE4DC557D6D55FCCD738573D6E0948817C496E9DE8EA1F88F627B7460106691CC452DB9799E59A5D003733C4EA1BCE33AD2D8BE40A4E5BB7D7BBEC2CEADBBC8B6F87A4A56FBE0B891DE57E4C64EF9AD87727C49CFE7C5DE942B72AC7F6D97DE18920777FDDEE9EB11122A4E18F5569FDE08906765428FB9E6F89FBF0DEAA6064637BCA63FD02E273E5557F0548662C97BC2E8D3FFDB26D23E87BFD97E635A6560CFD93F8EED26E30C70DE8633D6B97C86DF7D9BEDFB99E36B6658F16C6DEFBDD5DF728D6209C852C37FE67CFF32EE4CCCECC64F7E6225FC99EC64C3B6DD7DED0FD7CCEA3BF09A006ECDD1009E;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'hA9C9CE3AECF7BE27C000000A8ABA95251B309A60B9DDC19EC3E391458CBB53CA00A85E3C5AAE2C49DDC2F6C7B013DACB319A769818A1081A7389F711D76A09BCBED23D9A99FF9B77183697955D76BF0E0008822742DA45B883C9193DAF09424501859565800698515E10A8189EE9B323E35CE7388D73C6E7A50D0DE6739C73AC538D134115D860ADA57B5B868E54393B1E31E762062577697D57E8464340420E9434CCA34CC9A1CB1FAACC56168071EAC113F5265D5F6A45A098D604A820508C4EA47F9A7E46083716911B0D585CE937B530218E8D2AD3777EE7D3B4BC56C29ADB46809D15D185F8809229B150C29C8081174CA6173B99703DA466629005C604;
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X33_Y1_N0
|
|
cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a5 (
|
|
.portawe(vcc),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(!\z80_|address_pins_|abus[13]~20_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain(1'b0),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\rom|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .init_file = "./rom/gw03.hex";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "rom";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock0";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 16384;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_a_write_enable_clock = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'hE10F8B8C100323720BEBBDEBB81DF13FF97B252E2CB4F27BA091FBD0002D1A611E1EDBBC716D44D2912B80041C44558060CFCF15955C0D780DD5E71393920844F25E16C87C5D0308EEC52C011514BBC13AFA1028924D0C7CE738105BD47A10AA5B5C1D9D4193E4339F492B0E1A64E13AE35BE6B67AC8057BDACC155F14E906A017A1841358335450D4B26CD2A21B3D8F2211080B81EC040D7FA0B51CD48008112508062020A02490900092D2040259108806A328F4006D2AA514B42FB006ECCCCB9A360865678449975A8AE72B5C0F7BA800C1B5DC55D7D6FE2EF4EED85D00AB111821321BA426A4FE4956B43595832C271E83E060341AE5F2023FC808177383;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h1A2955372D510AC266A5445146E27000020C320FAE1557E37154040A13202DC6F40B840FB9A59B6DBB296562CB6220EFBE99D2776A202044D9101006FD221D305519198C859000004012AFF4FB060307C92BB732203BFDFEFFFFFFDFFF87FCFFFBFFEFF03FFE0FFFBFAFE0FF80787FFF7FFF83F7F87003FFBFFFFBFFFBFF0FFC0FF81FFF7FFBFFDFFFBFFFE1FF0086F3141AAB6005810A0621595A893F9D85983B9254954341968BAC8C141C90938C05B2C9CD267E11650407375FEDD6A2FEB346AAF6CFDC0791AA97B741995A3B3981E06D1A44D3711955197BB9910FCA20744915C84D6C24BAF53929814CA8A4697E8F4201145AE7415DC122A5F010436107;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h02E84F969E3C800AC610D276182020227809001A50DDDBA3487BB6AE802BA06509312DA0E620656EAF24D57C08FFB14D289613DC32083803B84DC6415FD5EDC000300A8D128FA20030ACCBAFA237B7024504D36A4BA26081137F059E78991154FE2AC2A884A8CC7FBBB21C851CC92B12E15593C0C020FFEE066558590E882D5B67459F1A8C3240FE4E6A8D028C0C088FCF471D400A19B38211004DD122212288B111114514CB11840E04828849C621392041163C00808C67223422F00110201DD18FCFFFF3FFE7F9FFFFFFF82C0B422D214711E08904524A069491774E663F48F665955B4E2C63DAC0078652D10120900298F7EE380092442AFD400BEC43C003;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'hB5D49EA9D7036A45AA9E870B8E8016720C7C3102AE925262492C84584942D209042216E0216C85B8912250B7157D5955AD406CB685BBF071B47D5193363C1CECAFE59E91BF11498940A0944996D47EE8D7E3A4EAE611AE19A965D01BA86B55E9C52A6A379A382C6C265FB0DA01396D0800C0046405C06F466DD18C4DD7655CD4E7622EC485808C841D64B737041FF68813B149A41531A0A692FB14AE2E5B49D49CDCADCF90E7BD88125BCE706BF6D04AABFC1C001163DC6EFF7FD3230303030000000000000000000008400000000000000000000000000030600000100007E00220000000000000080040004023AD496997B8C0077B886EEF161CF2298A091B;
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X33_Y25_N0
|
|
cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a13 (
|
|
.portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\CLOCK_50~inputclkctrl_outclk ),
|
|
.clk1(\CLOCK_50~inputclkctrl_outclk ),
|
|
.ena0(\z80_|address_pins_|abus[13]~20_combout ),
|
|
.ena1(gnd),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[5]~77_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain({\~GND~combout }),
|
|
.portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4],
|
|
\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .clk0_core_clock_enable = "ena0";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .clk1_core_clock_enable = "ena1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .data_interleave_width_in_bits = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .init_file = "ula/test_scr.hex";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .init_file_layout = "port_a";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mixed_port_feed_through_mode = "dont_care";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .operation_mode = "bidir_dual_port";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_address_width = 13;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_byte_enable_clock = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_out_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_data_width = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_address = 0;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_first_bit_number = 5;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_last_address = 8191;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_depth = 16384;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_logical_ram_width = 8;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_address_width = 13;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_in_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_out_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_out_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_data_width = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_first_address = 0;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_first_bit_number = 5;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_last_address = 8191;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_logical_ram_depth = 16384;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_logical_ram_width = 8;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_read_enable_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .port_b_write_enable_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .ram_block_type = "M9K";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a13 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X33_Y28_N0
|
|
cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a5 (
|
|
.portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\CLOCK_50~inputclkctrl_outclk ),
|
|
.clk1(\CLOCK_50~inputclkctrl_outclk ),
|
|
.ena0(!\z80_|address_pins_|abus[13]~20_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[5]~77_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain({\~GND~combout }),
|
|
.portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4],
|
|
\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ),
|
|
.portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a5_PORTBDATAOUT_bus ));
|
|
// synopsys translate_off
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .clk0_core_clock_enable = "ena0";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .data_interleave_width_in_bits = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .init_file = "ula/test_scr.hex";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .init_file_layout = "port_a";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mixed_port_feed_through_mode = "dont_care";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .operation_mode = "bidir_dual_port";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_address_width = 13;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_byte_enable_clock = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_out_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_data_width = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_address = 0;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_first_bit_number = 5;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_last_address = 8191;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_depth = 16384;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_logical_ram_width = 8;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_address_width = 13;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_in_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_out_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_data_width = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_address = 0;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_first_bit_number = 5;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_last_address = 8191;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_depth = 16384;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_logical_ram_width = 8;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_read_enable_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .port_b_write_enable_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .ram_block_type = "M9K";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init3 = 2048'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FF80000001C000000160F000FF70C0007F78C00000F05001007870010010000000000800000038000000F000000070000000300000006000000000000040000000F00000000000000000000;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000001D108000BEDA9FA9698A000000000000000000000000FFFFFFFF408102048004188297E014DA9FA9E9CA00000000000000000000000000000000FFFFFFFC800400CA972208DA9FA9CD8E00000000000000000000000000000000FFFFFFFC8004046A97A289FA9FA9CDC20000000000000000000000007FFFFFFC8000000280040E2A97A2997A9DA9CFC20000000000000000000000007FFFFFFE8000000280042EB28002BE369DA9274200000000000000000000000040810206BFFFFFFE9FE430A29D82AC3E8009E34A000000000000000000000000000000023FFFFFFC9FE4B1829FA2800E8009436A;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init1 = 2048'h9FE8334E88F827C697F88D1600A80A44809E8FC2B86999C2B85B3A82B1D32A869FE8336A88F807CA97F88F96A0A80EC2838E8D42B9E98FC2B86B3B82B0D7B2D2800832E288F827CA97F88B82A0080EC683869542B939B8C2B1AB0F8290B730C2800826EA8878078297F88AD2A0280EC283E694C2B83A3BC2A3AB3E8291A316AA800826EE881807C69DE8ABD6A0280BC282209CD2BA2A3D42A2737F82918314E2800806E6981805C69D48AED6A1E80BCA82709FC2BB223DC2A07B7F8295DF11C2800886E6980805869848AAC6A1E42DC281789DC2BBAA3DC6A02B7582955F00928008A6EE98082D9618088AC8A0F40FC289E89DC2BBCA3DC2A18B7782154F02F0;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a5 .mem_init0 = 2048'h174F0870801C870281E2C982A801460297E5AC0288F318023FFFFFFC0000000297DF094A8094870281D6C082AC01460293FDA89288D31902BFFFFFFE40810106879F8D228C8685028016C082AC014642B3FCA80288D10F02800000027FFFFFFE879F893284DEC9028000408AAC014C02937DA00288D10F02800000027FFFFFFC841FA902804E81068BC04292AC0145E29379B00288D11F02FFFFFFFC0000000084FE89328166C1028BE05282AE4144829179B20288511F02FFFFFFFC0000000084F283328516850A88204602874364829179B08280513E0240810104FFFFFFFF843A8302853685828800560287476C928039B00200413E0000000000FFFFFFFF;
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y21_N20
|
|
cycloneive_lcell_comb \Mux2~0 (
|
|
// Equation(s):
|
|
// \Mux2~0_combout = (\Selector3~0_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # (!\z80_|address_pins_|abus[14]~23_combout ))) # (!\Selector3~0_combout & (\z80_|address_pins_|abus[14]~23_combout &
|
|
// ((\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ))))
|
|
|
|
.dataa(\Selector3~0_combout ),
|
|
.datab(\z80_|address_pins_|abus[14]~23_combout ),
|
|
.datac(\ram0|altsyncram_component|auto_generated|ram_block1a13~portadataout ),
|
|
.datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~portadataout ),
|
|
.cin(gnd),
|
|
.combout(\Mux2~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \Mux2~0 .lut_mask = 16'hE6A2;
|
|
defparam \Mux2~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y21_N26
|
|
cycloneive_lcell_comb \Mux2~1 (
|
|
// Equation(s):
|
|
// \Mux2~1_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\Mux2~0_combout )))) # (!\z80_|address_pins_|abus[14]~23_combout & ((\Mux2~0_combout & (\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout )) # (!\Mux2~0_combout &
|
|
// ((\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout )))))
|
|
|
|
.dataa(\z80_|address_pins_|abus[14]~23_combout ),
|
|
.datab(\rom|altsyncram_component|auto_generated|ram_block1a13~portadataout ),
|
|
.datac(\rom|altsyncram_component|auto_generated|ram_block1a5~portadataout ),
|
|
.datad(\Mux2~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\Mux2~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \Mux2~1 .lut_mask = 16'hEE50;
|
|
defparam \Mux2~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y21_N8
|
|
cycloneive_lcell_comb \D[5]~87 (
|
|
// Equation(s):
|
|
// \D[5]~87_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Mux2~1_combout ))))) #
|
|
// (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ))
|
|
|
|
.dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.datab(\ram1|altsyncram_component|auto_generated|mux2|result_node[5]~11_combout ),
|
|
.datac(\Mux2~1_combout ),
|
|
.datad(\z80_|address_pins_|DFFE_apin_latch [15]),
|
|
.cin(gnd),
|
|
.combout(\D[5]~87_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[5]~87 .lut_mask = 16'hCCE4;
|
|
defparam \D[5]~87 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y21_N4
|
|
cycloneive_lcell_comb \D[5]~68 (
|
|
// Equation(s):
|
|
// \D[5]~68_combout = (\D[5]~67_combout & (\D[5]~87_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) # (!\D[5]~67_combout & ((\z80_|data_pins_|dout [5]) # ((!\z80_|pin_control_|bus_db_pin_oe~15_combout ))))
|
|
|
|
.dataa(\D[5]~67_combout ),
|
|
.datab(\z80_|data_pins_|dout [5]),
|
|
.datac(\D[5]~87_combout ),
|
|
.datad(\z80_|pin_control_|bus_db_pin_oe~15_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[5]~68_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[5]~68 .lut_mask = 16'hC4F5;
|
|
defparam \D[5]~68 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y21_N12
|
|
cycloneive_lcell_comb \D[5]~77 (
|
|
// Equation(s):
|
|
// \D[5]~77_combout = (\D[5]~68_combout ) # (!\D[0]~84_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\D[5]~68_combout ),
|
|
.datad(\D[0]~84_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[5]~77_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[5]~77 .lut_mask = 16'hF0FF;
|
|
defparam \D[5]~77 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y13_N16
|
|
cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] (
|
|
// Equation(s):
|
|
// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [5] = (\D[5]~77_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[5]~15_combout )))) # (!\D[5]~77_combout &
|
|
// (((\z80_|execute_|ctl_bus_db_we~7_combout & \z80_|bus_control_|db[5]~15_combout ))))
|
|
|
|
.dataa(\D[5]~77_combout ),
|
|
.datab(\z80_|pin_control_|bus_db_pin_re~combout ),
|
|
.datac(\z80_|execute_|ctl_bus_db_we~7_combout ),
|
|
.datad(\z80_|bus_control_|db[5]~15_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .lut_mask = 16'hF888;
|
|
defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[5] .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X30_Y13_N25
|
|
dffeas \z80_|data_pins_|dout[5] (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [5]),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|data_pins_|dout [5]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|data_pins_|dout[5] .is_wysiwyg = "true";
|
|
defparam \z80_|data_pins_|dout[5] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y13_N10
|
|
cycloneive_lcell_comb \z80_|bus_control_|db[5]~14 (
|
|
// Equation(s):
|
|
// \z80_|bus_control_|db[5]~14_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [5]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|execute_|ctl_bus_db_oe~combout ),
|
|
.datac(\z80_|bus_control_|db[0]~4_combout ),
|
|
.datad(\z80_|data_pins_|dout [5]),
|
|
.cin(gnd),
|
|
.combout(\z80_|bus_control_|db[5]~14_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|bus_control_|db[5]~14 .lut_mask = 16'hF030;
|
|
defparam \z80_|bus_control_|db[5]~14 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y17_N18
|
|
cycloneive_lcell_comb \z80_|bus_control_|db[5]~15 (
|
|
// Equation(s):
|
|
// \z80_|bus_control_|db[5]~15_combout = ((\z80_|bus_control_|db[5]~14_combout & ((\z80_|alu_control_|db[5]~15_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout )
|
|
|
|
.dataa(\z80_|bus_control_|db[0]~6_combout ),
|
|
.datab(\z80_|alu_control_|db[5]~15_combout ),
|
|
.datac(\z80_|bus_control_|db[5]~14_combout ),
|
|
.datad(\z80_|execute_|ctl_bus_db_we~7_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|bus_control_|db[5]~15_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|bus_control_|db[5]~15 .lut_mask = 16'hD5F5;
|
|
defparam \z80_|bus_control_|db[5]~15 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X30_Y16_N17
|
|
dffeas \z80_|ir_|opcode[5] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|bus_control_|db[5]~15_combout ),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|execute_|ctl_ir_we~13_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|ir_|opcode [5]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|ir_|opcode[5] .is_wysiwyg = "true";
|
|
defparam \z80_|ir_|opcode[5] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y17_N24
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_mRead~8 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mRead~8_combout = (\z80_|ir_|opcode [5] & (\z80_|pla_decode_|Equal55~0_combout & (\z80_|pla_decode_|Equal6~0_combout & \z80_|pla_decode_|Equal9~0_combout )))
|
|
|
|
.dataa(\z80_|ir_|opcode [5]),
|
|
.datab(\z80_|pla_decode_|Equal55~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal6~0_combout ),
|
|
.datad(\z80_|pla_decode_|Equal9~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mRead~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mRead~8 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|ctl_mRead~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y15_N6
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~8 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_bus_db_we~8_combout = (\z80_|sequencer_|M5~q & (!\z80_|sequencer_|DFFE_T1_ff~q & ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|pla_decode_|Equal9~1_combout ))))
|
|
|
|
.dataa(\z80_|sequencer_|M5~q ),
|
|
.datab(\z80_|execute_|ctl_mRead~8_combout ),
|
|
.datac(\z80_|pla_decode_|Equal9~1_combout ),
|
|
.datad(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_bus_db_we~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_bus_db_we~8 .lut_mask = 16'h00A8;
|
|
defparam \z80_|execute_|ctl_bus_db_we~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y15_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_bus_db_we~4_combout = (\z80_|execute_|ixy_d~7_combout & ((\z80_|execute_|ctl_mWrite~6_combout ) # ((\z80_|pla_decode_|Equal21~0_combout & \z80_|pla_decode_|Equal24~0_combout ))))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal21~0_combout ),
|
|
.datab(\z80_|pla_decode_|Equal24~0_combout ),
|
|
.datac(\z80_|execute_|ixy_d~7_combout ),
|
|
.datad(\z80_|execute_|ctl_mWrite~6_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_bus_db_we~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_bus_db_we~4 .lut_mask = 16'hF080;
|
|
defparam \z80_|execute_|ctl_bus_db_we~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y15_N28
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~6 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_bus_db_we~6_combout = (\z80_|execute_|ctl_bus_db_we~4_combout ) # (((!\z80_|execute_|ctl_apin_mux~0_combout ) # (!\z80_|execute_|ctl_sw_2u~3_combout )) # (!\z80_|execute_|ctl_bus_db_we~5_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_bus_db_we~4_combout ),
|
|
.datab(\z80_|execute_|ctl_bus_db_we~5_combout ),
|
|
.datac(\z80_|execute_|ctl_sw_2u~3_combout ),
|
|
.datad(\z80_|execute_|ctl_apin_mux~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_bus_db_we~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_bus_db_we~6 .lut_mask = 16'hBFFF;
|
|
defparam \z80_|execute_|ctl_bus_db_we~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y16_N24
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout = (\z80_|pla_decode_|Equal13~0_combout & (!\z80_|ir_|opcode [3] & (\z80_|pla_decode_|Equal8~0_combout & \z80_|execute_|ctl_ir_we~4_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal13~0_combout ),
|
|
.datab(\z80_|ir_|opcode [3]),
|
|
.datac(\z80_|pla_decode_|Equal8~0_combout ),
|
|
.datad(\z80_|execute_|ctl_ir_we~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .lut_mask = 16'h2000;
|
|
defparam \z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y16_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~3 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_bus_db_we~3_combout = (\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ) # ((\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_iorw~10_combout ) # (\z80_|execute_|ctl_mWrite~7_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_gp_sel_pla31pla33M4T1_3~combout ),
|
|
.datac(\z80_|execute_|ctl_iorw~10_combout ),
|
|
.datad(\z80_|execute_|ctl_mWrite~7_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_bus_db_we~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_bus_db_we~3 .lut_mask = 16'hEEEC;
|
|
defparam \z80_|execute_|ctl_bus_db_we~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y15_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_bus_db_we~2_combout = (\z80_|execute_|ctl_ir_we~4_combout & ((\z80_|pla_decode_|Equal13~2_combout ) # ((\z80_|execute_|ctl_mRead~8_combout ) # (\z80_|execute_|ctl_mWrite~7_combout ))))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal13~2_combout ),
|
|
.datab(\z80_|execute_|ctl_ir_we~4_combout ),
|
|
.datac(\z80_|execute_|ctl_mRead~8_combout ),
|
|
.datad(\z80_|execute_|ctl_mWrite~7_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_bus_db_we~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_bus_db_we~2 .lut_mask = 16'hCCC8;
|
|
defparam \z80_|execute_|ctl_bus_db_we~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y15_N30
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_we~7 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_bus_db_we~7_combout = (\z80_|execute_|ctl_bus_db_we~8_combout ) # ((\z80_|execute_|ctl_bus_db_we~6_combout ) # ((\z80_|execute_|ctl_bus_db_we~3_combout ) # (\z80_|execute_|ctl_bus_db_we~2_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_bus_db_we~8_combout ),
|
|
.datab(\z80_|execute_|ctl_bus_db_we~6_combout ),
|
|
.datac(\z80_|execute_|ctl_bus_db_we~3_combout ),
|
|
.datad(\z80_|execute_|ctl_bus_db_we~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_bus_db_we~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_bus_db_we~7 .lut_mask = 16'hFFFE;
|
|
defparam \z80_|execute_|ctl_bus_db_we~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y8_N2
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~66 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[5][0]~66_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|zx_keyboard_|shifted~q ))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [4]),
|
|
.datab(\ula_|zx_keyboard_|released~q ),
|
|
.datac(\ula_|zx_keyboard_|shifted~q ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[5][0]~66_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[5][0]~66 .lut_mask = 16'hCECE;
|
|
defparam \ula_|zx_keyboard_|keys[5][0]~66 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y8_N30
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~80 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[5][0]~80_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [0]))) # (!\ula_|ps2_keyboard_|shiftreg [4] &
|
|
// (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [0])))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [4]),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [1]),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [3]),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [0]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[5][0]~80_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[5][0]~80 .lut_mask = 16'h1008;
|
|
defparam \ula_|zx_keyboard_|keys[5][0]~80 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y8_N0
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~81 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[5][0]~81_combout = (\ula_|zx_keyboard_|keys[5][0]~80_combout & (\ula_|ps2_keyboard_|shiftreg [2] $ (\ula_|ps2_keyboard_|shiftreg [4])))
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[5][0]~80_combout ),
|
|
.datab(gnd),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [2]),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [4]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[5][0]~81_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[5][0]~81 .lut_mask = 16'h0AA0;
|
|
defparam \ula_|zx_keyboard_|keys[5][0]~81 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y8_N4
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][0]~82 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[5][0]~82_combout = (\ula_|zx_keyboard_|keys[6][1]~39_combout & ((\ula_|zx_keyboard_|keys[5][0]~81_combout & (!\ula_|zx_keyboard_|keys[5][0]~66_combout )) # (!\ula_|zx_keyboard_|keys[5][0]~81_combout &
|
|
// ((\ula_|zx_keyboard_|keys[5][0]~q ))))) # (!\ula_|zx_keyboard_|keys[6][1]~39_combout & (((\ula_|zx_keyboard_|keys[5][0]~q ))))
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[5][0]~66_combout ),
|
|
.datab(\ula_|zx_keyboard_|keys[6][1]~39_combout ),
|
|
.datac(\ula_|zx_keyboard_|keys[5][0]~q ),
|
|
.datad(\ula_|zx_keyboard_|keys[5][0]~81_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[5][0]~82_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[5][0]~82 .lut_mask = 16'h74F0;
|
|
defparam \ula_|zx_keyboard_|keys[5][0]~82 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X29_Y8_N5
|
|
dffeas \ula_|zx_keyboard_|keys[5][0] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|zx_keyboard_|keys[5][0]~82_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|zx_keyboard_|keys[5][0]~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[5][0] .is_wysiwyg = "true";
|
|
defparam \ula_|zx_keyboard_|keys[5][0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y10_N10
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~84 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[4][0]~84_combout = (\ula_|zx_keyboard_|released~q ) # ((\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|zx_keyboard_|shifted~q ))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [3]),
|
|
.datab(\ula_|zx_keyboard_|shifted~q ),
|
|
.datac(gnd),
|
|
.datad(\ula_|zx_keyboard_|released~q ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[4][0]~84_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[4][0]~84 .lut_mask = 16'hFF22;
|
|
defparam \ula_|zx_keyboard_|keys[4][0]~84 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y10_N8
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~83 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[4][0]~83_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [5] $ (\ula_|ps2_keyboard_|shiftreg [3])))) # (!\ula_|ps2_keyboard_|shiftreg [1] &
|
|
// (!\ula_|ps2_keyboard_|shiftreg [5] & (!\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [0])))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [5]),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [1]),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [3]),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [0]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[4][0]~83_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[4][0]~83 .lut_mask = 16'h0148;
|
|
defparam \ula_|zx_keyboard_|keys[4][0]~83 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y10_N20
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][0]~85 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[4][0]~85_combout = (\ula_|zx_keyboard_|keys[4][0]~83_combout & ((\ula_|zx_keyboard_|keys[5][1]~35_combout & (!\ula_|zx_keyboard_|keys[4][0]~84_combout )) # (!\ula_|zx_keyboard_|keys[5][1]~35_combout &
|
|
// ((\ula_|zx_keyboard_|keys[4][0]~q ))))) # (!\ula_|zx_keyboard_|keys[4][0]~83_combout & (((\ula_|zx_keyboard_|keys[4][0]~q ))))
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[4][0]~84_combout ),
|
|
.datab(\ula_|zx_keyboard_|keys[4][0]~83_combout ),
|
|
.datac(\ula_|zx_keyboard_|keys[4][0]~q ),
|
|
.datad(\ula_|zx_keyboard_|keys[5][1]~35_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[4][0]~85_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[4][0]~85 .lut_mask = 16'h74F0;
|
|
defparam \ula_|zx_keyboard_|keys[4][0]~85 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X29_Y10_N21
|
|
dffeas \ula_|zx_keyboard_|keys[4][0] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|zx_keyboard_|keys[4][0]~85_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|zx_keyboard_|keys[4][0]~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[4][0] .is_wysiwyg = "true";
|
|
defparam \ula_|zx_keyboard_|keys[4][0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y10_N14
|
|
cycloneive_lcell_comb \D[0]~42 (
|
|
// Equation(s):
|
|
// \D[0]~42_combout = (\z80_|address_pins_|abus[12]~21_combout & (((\z80_|address_pins_|abus[13]~20_combout )) # (!\ula_|zx_keyboard_|keys[5][0]~q ))) # (!\z80_|address_pins_|abus[12]~21_combout & (!\ula_|zx_keyboard_|keys[4][0]~q &
|
|
// ((\z80_|address_pins_|abus[13]~20_combout ) # (!\ula_|zx_keyboard_|keys[5][0]~q ))))
|
|
|
|
.dataa(\z80_|address_pins_|abus[12]~21_combout ),
|
|
.datab(\ula_|zx_keyboard_|keys[5][0]~q ),
|
|
.datac(\z80_|address_pins_|abus[13]~20_combout ),
|
|
.datad(\ula_|zx_keyboard_|keys[4][0]~q ),
|
|
.cin(gnd),
|
|
.combout(\D[0]~42_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[0]~42 .lut_mask = 16'hA2F3;
|
|
defparam \D[0]~42 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y9_N14
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~78 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[1][0]~78_combout = (!\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|zx_keyboard_|keys[1][4]~23_combout & \ula_|ps2_keyboard_|shiftreg [3])))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [0]),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [5]),
|
|
.datac(\ula_|zx_keyboard_|keys[1][4]~23_combout ),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [3]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[1][0]~78_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[1][0]~78 .lut_mask = 16'h1000;
|
|
defparam \ula_|zx_keyboard_|keys[1][0]~78 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y9_N26
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][0]~79 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[1][0]~79_combout = (\ula_|zx_keyboard_|keys[1][0]~78_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[1][0]~78_combout & ((\ula_|zx_keyboard_|keys[1][0]~q )))
|
|
|
|
.dataa(\ula_|zx_keyboard_|released~q ),
|
|
.datab(gnd),
|
|
.datac(\ula_|zx_keyboard_|keys[1][0]~q ),
|
|
.datad(\ula_|zx_keyboard_|keys[1][0]~78_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[1][0]~79_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[1][0]~79 .lut_mask = 16'h55F0;
|
|
defparam \ula_|zx_keyboard_|keys[1][0]~79 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X27_Y9_N27
|
|
dffeas \ula_|zx_keyboard_|keys[1][0] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|zx_keyboard_|keys[1][0]~79_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|zx_keyboard_|keys[1][0]~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[1][0] .is_wysiwyg = "true";
|
|
defparam \ula_|zx_keyboard_|keys[1][0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y9_N12
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][0]~76 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[3][0]~76_combout = (\ula_|zx_keyboard_|keys[3][1]~26_combout & ((\ula_|zx_keyboard_|keys[3][0]~75_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[3][0]~75_combout & ((\ula_|zx_keyboard_|keys[3][0]~q
|
|
// ))))) # (!\ula_|zx_keyboard_|keys[3][1]~26_combout & (((\ula_|zx_keyboard_|keys[3][0]~q ))))
|
|
|
|
.dataa(\ula_|zx_keyboard_|released~q ),
|
|
.datab(\ula_|zx_keyboard_|keys[3][1]~26_combout ),
|
|
.datac(\ula_|zx_keyboard_|keys[3][0]~q ),
|
|
.datad(\ula_|zx_keyboard_|keys[3][0]~75_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[3][0]~76_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[3][0]~76 .lut_mask = 16'h74F0;
|
|
defparam \ula_|zx_keyboard_|keys[3][0]~76 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X27_Y9_N13
|
|
dffeas \ula_|zx_keyboard_|keys[3][0] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|zx_keyboard_|keys[3][0]~76_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|zx_keyboard_|keys[3][0]~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[3][0] .is_wysiwyg = "true";
|
|
defparam \ula_|zx_keyboard_|keys[3][0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y9_N10
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][0]~77 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[2][0]~77_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (((\ula_|zx_keyboard_|keys[2][0]~q )))) # (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[2][1]~24_combout & (!\ula_|zx_keyboard_|released~q )) #
|
|
// (!\ula_|zx_keyboard_|keys[2][1]~24_combout & ((\ula_|zx_keyboard_|keys[2][0]~q )))))
|
|
|
|
.dataa(\ula_|zx_keyboard_|released~q ),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [3]),
|
|
.datac(\ula_|zx_keyboard_|keys[2][0]~q ),
|
|
.datad(\ula_|zx_keyboard_|keys[2][1]~24_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[2][0]~77_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[2][0]~77 .lut_mask = 16'hD1F0;
|
|
defparam \ula_|zx_keyboard_|keys[2][0]~77 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X27_Y9_N11
|
|
dffeas \ula_|zx_keyboard_|keys[2][0] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|zx_keyboard_|keys[2][0]~77_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|zx_keyboard_|keys[2][0]~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[2][0] .is_wysiwyg = "true";
|
|
defparam \ula_|zx_keyboard_|keys[2][0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y9_N28
|
|
cycloneive_lcell_comb \D[0]~40 (
|
|
// Equation(s):
|
|
// \D[0]~40_combout = (\ula_|zx_keyboard_|keys[3][0]~q & (\z80_|address_pins_|abus[11]~19_combout & ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][0]~q )))) # (!\ula_|zx_keyboard_|keys[3][0]~q &
|
|
// ((\z80_|address_pins_|abus[10]~24_combout ) # ((!\ula_|zx_keyboard_|keys[2][0]~q ))))
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[3][0]~q ),
|
|
.datab(\z80_|address_pins_|abus[10]~24_combout ),
|
|
.datac(\z80_|address_pins_|abus[11]~19_combout ),
|
|
.datad(\ula_|zx_keyboard_|keys[2][0]~q ),
|
|
.cin(gnd),
|
|
.combout(\D[0]~40_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[0]~40 .lut_mask = 16'hC4F5;
|
|
defparam \D[0]~40 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y9_N20
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr0~0 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|WideOr0~0_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|ps2_keyboard_|shiftreg [1] & (!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [0])) # (!\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|ps2_keyboard_|shiftreg
|
|
// [2]))))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [1]),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [3]),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [2]),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [0]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|WideOr0~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|WideOr0~0 .lut_mask = 16'h1012;
|
|
defparam \ula_|zx_keyboard_|WideOr0~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y7_N26
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys~71 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys~71_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|zx_keyboard_|WideOr0~0_combout )))) # (!\ula_|ps2_keyboard_|shiftreg [4] & (((!\ula_|ps2_keyboard_|shiftreg [3])) # (!\ula_|zx_keyboard_|keys[6][4]~45_combout )))
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[6][4]~45_combout ),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [4]),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [3]),
|
|
.datad(\ula_|zx_keyboard_|WideOr0~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys~71_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys~71 .lut_mask = 16'h13DF;
|
|
defparam \ula_|zx_keyboard_|keys~71 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y10_N20
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][3]~70 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[4][3]~70_combout = (\ula_|ps2_keyboard_|shiftreg [5] & \ula_|ps2_keyboard_|shiftreg [6])
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [5]),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [6]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[4][3]~70_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[4][3]~70 .lut_mask = 16'hAA00;
|
|
defparam \ula_|zx_keyboard_|keys[4][3]~70 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y8_N26
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~72 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[0][0]~72_combout = (\ula_|zx_keyboard_|keys[0][0]~13_combout & (((!\ula_|zx_keyboard_|keys~71_combout & \ula_|zx_keyboard_|keys[4][3]~70_combout )) # (!\ula_|zx_keyboard_|extended~q )))
|
|
|
|
.dataa(\ula_|zx_keyboard_|extended~q ),
|
|
.datab(\ula_|zx_keyboard_|keys~71_combout ),
|
|
.datac(\ula_|zx_keyboard_|keys[0][0]~13_combout ),
|
|
.datad(\ula_|zx_keyboard_|keys[4][3]~70_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[0][0]~72_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[0][0]~72 .lut_mask = 16'h7050;
|
|
defparam \ula_|zx_keyboard_|keys[0][0]~72 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y8_N20
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr4~0 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|WideOr4~0_combout = (\ula_|ps2_keyboard_|shiftreg [5] & (((\ula_|ps2_keyboard_|shiftreg [6] & \ula_|ps2_keyboard_|shiftreg [1])))) # (!\ula_|ps2_keyboard_|shiftreg [5] & (\ula_|ps2_keyboard_|shiftreg [4] &
|
|
// (!\ula_|ps2_keyboard_|shiftreg [6] & !\ula_|ps2_keyboard_|shiftreg [1])))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [5]),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [4]),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [6]),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [1]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|WideOr4~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|WideOr4~0 .lut_mask = 16'hA004;
|
|
defparam \ula_|zx_keyboard_|WideOr4~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y8_N14
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys~73 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys~73_combout = (!\ula_|zx_keyboard_|extended~q & (((\ula_|ps2_keyboard_|shiftreg [3]) # (!\ula_|zx_keyboard_|WideOr4~0_combout )) # (!\ula_|zx_keyboard_|keys[4][1]~29_combout )))
|
|
|
|
.dataa(\ula_|zx_keyboard_|extended~q ),
|
|
.datab(\ula_|zx_keyboard_|keys[4][1]~29_combout ),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [3]),
|
|
.datad(\ula_|zx_keyboard_|WideOr4~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys~73_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys~73 .lut_mask = 16'h5155;
|
|
defparam \ula_|zx_keyboard_|keys~73 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y8_N10
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][0]~74 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[0][0]~74_combout = (\ula_|zx_keyboard_|keys[0][0]~72_combout & ((\ula_|zx_keyboard_|keys~73_combout & (\ula_|zx_keyboard_|keys[0][0]~q )) # (!\ula_|zx_keyboard_|keys~73_combout & ((!\ula_|zx_keyboard_|released~q ))))) #
|
|
// (!\ula_|zx_keyboard_|keys[0][0]~72_combout & (((\ula_|zx_keyboard_|keys[0][0]~q ))))
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[0][0]~72_combout ),
|
|
.datab(\ula_|zx_keyboard_|keys~73_combout ),
|
|
.datac(\ula_|zx_keyboard_|keys[0][0]~q ),
|
|
.datad(\ula_|zx_keyboard_|released~q ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[0][0]~74_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[0][0]~74 .lut_mask = 16'hD0F2;
|
|
defparam \ula_|zx_keyboard_|keys[0][0]~74 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X28_Y8_N11
|
|
dffeas \ula_|zx_keyboard_|keys[0][0] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|zx_keyboard_|keys[0][0]~74_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|zx_keyboard_|keys[0][0]~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[0][0] .is_wysiwyg = "true";
|
|
defparam \ula_|zx_keyboard_|keys[0][0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y9_N14
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~2 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|key_row~2_combout = ((\z80_|address_pins_|DFFE_apin_latch [8]) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )) # (!\ula_|zx_keyboard_|keys[0][0]~q )
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|zx_keyboard_|keys[0][0]~q ),
|
|
.datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.datad(\z80_|address_pins_|DFFE_apin_latch [8]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|key_row~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|key_row~2 .lut_mask = 16'hFF3F;
|
|
defparam \ula_|zx_keyboard_|key_row~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y9_N16
|
|
cycloneive_lcell_comb \D[0]~41 (
|
|
// Equation(s):
|
|
// \D[0]~41_combout = (\D[0]~40_combout & (\ula_|zx_keyboard_|key_row~2_combout & ((\z80_|address_pins_|abus[9]~17_combout ) # (!\ula_|zx_keyboard_|keys[1][0]~q ))))
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[1][0]~q ),
|
|
.datab(\D[0]~40_combout ),
|
|
.datac(\ula_|zx_keyboard_|key_row~2_combout ),
|
|
.datad(\z80_|address_pins_|abus[9]~17_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[0]~41_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[0]~41 .lut_mask = 16'hC040;
|
|
defparam \D[0]~41 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y9_N20
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~89 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[6][0]~89_combout = (\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|ps2_keyboard_|shiftreg [6] & (!\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [5])))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [3]),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [6]),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [0]),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [5]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[6][0]~89_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[6][0]~89 .lut_mask = 16'h0008;
|
|
defparam \ula_|zx_keyboard_|keys[6][0]~89 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y9_N18
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~90 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[6][0]~90_combout = (\ula_|ps2_keyboard_|shiftreg [1] & (\ula_|zx_keyboard_|keys[6][0]~89_combout & (\ula_|zx_keyboard_|shifted~3_combout & \ula_|zx_keyboard_|keys[7][1]~21_combout )))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [1]),
|
|
.datab(\ula_|zx_keyboard_|keys[6][0]~89_combout ),
|
|
.datac(\ula_|zx_keyboard_|shifted~3_combout ),
|
|
.datad(\ula_|zx_keyboard_|keys[7][1]~21_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[6][0]~90_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[6][0]~90 .lut_mask = 16'h8000;
|
|
defparam \ula_|zx_keyboard_|keys[6][0]~90 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y10_N18
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][0]~91 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[6][0]~91_combout = (\ula_|zx_keyboard_|keys[6][0]~90_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[6][0]~90_combout & (\ula_|zx_keyboard_|keys[6][0]~q ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|zx_keyboard_|keys[6][0]~90_combout ),
|
|
.datac(\ula_|zx_keyboard_|keys[6][0]~q ),
|
|
.datad(\ula_|zx_keyboard_|released~q ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[6][0]~91_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[6][0]~91 .lut_mask = 16'h30FC;
|
|
defparam \ula_|zx_keyboard_|keys[6][0]~91 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X30_Y10_N19
|
|
dffeas \ula_|zx_keyboard_|keys[6][0] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|zx_keyboard_|keys[6][0]~91_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|zx_keyboard_|keys[6][0]~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[6][0] .is_wysiwyg = "true";
|
|
defparam \ula_|zx_keyboard_|keys[6][0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y8_N22
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~131 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[7][0]~131_combout = (\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[3][0]~75_combout & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [6])))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [2]),
|
|
.datab(\ula_|zx_keyboard_|keys[3][0]~75_combout ),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [4]),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [6]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[7][0]~131_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[7][0]~131 .lut_mask = 16'h8000;
|
|
defparam \ula_|zx_keyboard_|keys[7][0]~131 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y9_N22
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|WideOr16~3 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|WideOr16~3_combout = (!\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [6])
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [2]),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [6]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|WideOr16~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|WideOr16~3 .lut_mask = 16'h000F;
|
|
defparam \ula_|zx_keyboard_|WideOr16~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y9_N12
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~86 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[7][0]~86_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[5][4]~62_combout & (\ula_|zx_keyboard_|WideOr16~3_combout & \ula_|ps2_keyboard_|shiftreg [3])))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [4]),
|
|
.datab(\ula_|zx_keyboard_|keys[5][4]~62_combout ),
|
|
.datac(\ula_|zx_keyboard_|WideOr16~3_combout ),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [3]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[7][0]~86_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[7][0]~86 .lut_mask = 16'h4000;
|
|
defparam \ula_|zx_keyboard_|keys[7][0]~86 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y9_N6
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~87 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[7][0]~87_combout = (\ula_|zx_keyboard_|keys[7][1]~21_combout & (\ula_|ps2_keyboard_|shiftreg [5] & ((\ula_|zx_keyboard_|keys[7][0]~131_combout ) # (\ula_|zx_keyboard_|keys[7][0]~86_combout ))))
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[7][1]~21_combout ),
|
|
.datab(\ula_|zx_keyboard_|keys[7][0]~131_combout ),
|
|
.datac(\ula_|zx_keyboard_|keys[7][0]~86_combout ),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [5]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[7][0]~87_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[7][0]~87 .lut_mask = 16'hA800;
|
|
defparam \ula_|zx_keyboard_|keys[7][0]~87 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y10_N4
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][0]~88 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[7][0]~88_combout = (\ula_|zx_keyboard_|keys[7][0]~87_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[7][0]~87_combout & (\ula_|zx_keyboard_|keys[7][0]~q ))
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[7][0]~87_combout ),
|
|
.datab(gnd),
|
|
.datac(\ula_|zx_keyboard_|keys[7][0]~q ),
|
|
.datad(\ula_|zx_keyboard_|released~q ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[7][0]~88_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[7][0]~88 .lut_mask = 16'h50FA;
|
|
defparam \ula_|zx_keyboard_|keys[7][0]~88 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X30_Y10_N5
|
|
dffeas \ula_|zx_keyboard_|keys[7][0] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|zx_keyboard_|keys[7][0]~88_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|zx_keyboard_|keys[7][0]~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[7][0] .is_wysiwyg = "true";
|
|
defparam \ula_|zx_keyboard_|keys[7][0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y10_N12
|
|
cycloneive_lcell_comb \D[0]~43 (
|
|
// Equation(s):
|
|
// \D[0]~43_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q )))) # (!\z80_|address_pins_|abus[14]~23_combout & (!\ula_|zx_keyboard_|keys[6][0]~q &
|
|
// ((\z80_|address_pins_|abus[15]~22_combout ) # (!\ula_|zx_keyboard_|keys[7][0]~q ))))
|
|
|
|
.dataa(\z80_|address_pins_|abus[14]~23_combout ),
|
|
.datab(\ula_|zx_keyboard_|keys[6][0]~q ),
|
|
.datac(\ula_|zx_keyboard_|keys[7][0]~q ),
|
|
.datad(\z80_|address_pins_|abus[15]~22_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[0]~43_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[0]~43 .lut_mask = 16'hBB0B;
|
|
defparam \D[0]~43 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y10_N10
|
|
cycloneive_lcell_comb \D[0]~44 (
|
|
// Equation(s):
|
|
// \D[0]~44_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[0]~42_combout & (\D[0]~41_combout & \D[0]~43_combout )))
|
|
|
|
.dataa(\D[0]~42_combout ),
|
|
.datab(\D[0]~41_combout ),
|
|
.datac(\z80_|address_pins_|abus[0]~16_combout ),
|
|
.datad(\D[0]~43_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[0]~44_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[0]~44 .lut_mask = 16'hF8F0;
|
|
defparam \D[0]~44 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X22_Y17_N0
|
|
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a24 (
|
|
.portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[0]~46_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a24_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .clk0_core_clock_enable = "ena0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .data_interleave_width_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file = "led_patterns.mif";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .init_file_layout = "port_a";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .operation_mode = "single_port";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_byte_enable_clock = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_out_clock = "clock0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_address = 0;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_first_bit_number = 0;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_last_address = 8191;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_depth = 32768;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_logical_ram_width = 8;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .port_b_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .ram_block_type = "M9K";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a24 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X22_Y18_N0
|
|
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a16 (
|
|
.portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[0]~46_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a16_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .clk0_core_clock_enable = "ena0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .data_interleave_width_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file = "led_patterns.mif";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .init_file_layout = "port_a";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .operation_mode = "single_port";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_byte_enable_clock = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_out_clock = "clock0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_address = 0;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_first_bit_number = 0;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_last_address = 8191;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_depth = 32768;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_logical_ram_width = 8;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .port_b_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .ram_block_type = "M9K";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a16 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X22_Y15_N0
|
|
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a8 (
|
|
.portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[0]~46_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file = "led_patterns.mif";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "single_port";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 32768;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X22_Y19_N0
|
|
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a0 (
|
|
.portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[0]~46_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file = "led_patterns.mif";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "single_port";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 32768;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000081;
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y14_N12
|
|
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4 (
|
|
// Equation(s):
|
|
// \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])))) #
|
|
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout )) #
|
|
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout )))))
|
|
|
|
.dataa(\ram1|altsyncram_component|auto_generated|ram_block1a8~portadataout ),
|
|
.datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]),
|
|
.datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
|
|
.datad(\ram1|altsyncram_component|auto_generated|ram_block1a0~portadataout ),
|
|
.cin(gnd),
|
|
.combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4 .lut_mask = 16'hE3E0;
|
|
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y14_N6
|
|
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5 (
|
|
// Equation(s):
|
|
// \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout &
|
|
// (\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout )) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout & ((\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ))))) #
|
|
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout ))))
|
|
|
|
.dataa(\ram1|altsyncram_component|auto_generated|ram_block1a24~portadataout ),
|
|
.datab(\ram1|altsyncram_component|auto_generated|ram_block1a16~portadataout ),
|
|
.datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]),
|
|
.datad(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5 .lut_mask = 16'hAFC0;
|
|
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X33_Y13_N0
|
|
cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a8 (
|
|
.portawe(vcc),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(\z80_|address_pins_|abus[13]~20_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain(1'b0),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\rom|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file = "./rom/gw03.hex";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "rom";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock0";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_a_write_enable_clock = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h3C00000000000000000000000000000000000000000000000000000000000000800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005DB824E17CAAE881C1908A79F24B7D1B4857A981A6AF39DFF5A2FEE9141EB33592D8E9B82471FDDA6791810A1C29D415CC1A8FA03444DF0083F83506BA93E8D1A1856A768D73A08418BFB25A40001DD4833DAF33BD311BB45F39667627407EF59ED569C483EB3BE1B10551B1428A6169579293ED063CAA9C6ADB0433CFC15C33AFF04C710408C20AC28B5909A229CD7D1DB4EB9A44CE0EEDBBBD391D3128AAA3;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'hDDE6FC8EBE3F9F3C3DFC6E8F07BFD31D50660B1E0B2506A533CE0E340C7C745CAEC4837C2A5FECBB94C1C969FFDDFF79BFFAAFDCA8D748399ABF75558ADD02F56F6DFFF29CB70FFD25A59DFFFED7B3F7E8B4CE6FFF3EF9CEC6BAE57ABFFFCEE647B2AFF5B87AA26AFFDD317DEDCFBDFFE1A0CAD3B58877DD2F647F7DF748E7CF4693FD3C1238FFAFBD7FDF567FA8FEF024F33AFD3AABC6B105EA80272D64895FFF9FFF6E3881C81AFDCF2257FD4F8ED5257D0E9B800726B6564D2B05012F76DF636CDEB4BDFCAEEFC61DFFEFB7E26262DEF2CB9F71565824FEBF3F7BDDEABB593F1BF746FBFFC353E37263FF38A796EF39E3FD7DFEBA7FFEFFBD97ABAF09E909;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'hE629BDF93D7F5B5BAF92FBAB477E9B315DB5A310CFACC7408DF9A544B1E57AF6EFEF92C2FA4D8D4E4AC86C277338FA37BCDD9D47782DB75EFF80781BCD23D0AFCAE30B9FE6AA29FFF6F72DA73DFE4F7ACD39687B9E69C5359E9B991F0246EFFBC5595561AC64787878F5CE14C664CF9EB0CDAFFBABEF1E83358371B9ED96E5069555AFBBD3AEBFCABFBBED7A5C5FE9BD0E6A91C6E7610042695EEB08D8881B1D735AF87DAE59FABBD7DEAF8717F2B72F428F5E37E5D6E13157B99CBD2D73B9C73C563C8B02C8CC39C64DDCEA1BEEB5E7353F93786145598FE634EF1000179B345725EA43CE18F187A1DE4DAABEA97963E3A7A96B8B7CBC095BEB7CE46274D9AF;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h4ED4AE2B1650D21EAFE01E7099EFCA3094FD4D705CF6B84AE21583E13385F8650004406BD60A023AB063D4E5966EA41AA997F5A49BFCB0657A9732D28EB8217E65F627A15E1057ADEE7B9E27122A58FB2B98B1EA560390C7E87715861814E04DCB76FAB179E9619BC7E7E9C9FD801CF87DBA1EA496E829D4E62861E1AF436A7585287860729C77B6C68CAEA3033A6E84D67249B594C407B39C68B4C1C97FDEFC6BAD12FDBB525EF4F87F4A23EC13CBC0262D8899A3A290F04F41C1324045B9FCEEC890579E95D5A0A546CCCDD48577558ABE7CA36EF67A70F6A8758BDA052D5B95DE707778B17C2379847A23AE5D4BB01F36F3F44A8162566D9FB15DE7CC83F7;
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X22_Y28_N0
|
|
cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a0 (
|
|
.portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\CLOCK_50~inputclkctrl_outclk ),
|
|
.clk1(\CLOCK_50~inputclkctrl_outclk ),
|
|
.ena0(!\z80_|address_pins_|abus[13]~20_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[0]~46_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain({\~GND~combout }),
|
|
.portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4],
|
|
\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ),
|
|
.portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a0_PORTBDATAOUT_bus ));
|
|
// synopsys translate_off
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file = "ula/test_scr.hex";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "bidir_dual_port";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_in_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_out_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_address = 0;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_first_bit_number = 0;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_last_address = 8191;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 16384;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_logical_ram_width = 8;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .port_b_write_enable_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF0000000000000000000000003FF03FFC20107FFC3FF00B9C3FF007FC18000FFC3FF03FD42FF43FFC2FFC3FE01FFE7FE81FFE3FDC07FE3FFC07FE2FFC07FE0F0807FE1F18207F0F3030FD8C30383300600000000000000000;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h000000000000000000000000FFFFFFFFE0408103E004044390120EAA803920C6000000000000000000000000FFFFFFFFE0408103A004005A84723CEA813930C2000000000000000000000000800000009FBF7EFD8004027A8572358A813950EA000000000000000000000000800000009FBF7EFC8005157A85733F0A8139518E0000000000000000000000009FBF7EFC800000008006113A8C73330A813919EA0000000000000000000000009FBF7EFC8000000080060022801333A2813973EA00000000000000000000000080000000DFFFFFFD9FF6022A84730366801913FE000000000000000000000000E0408102FFFFFFFD9FF60ABA84730426901913EE;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h9FF81326887812F28FF0D7C2CC6856E3894C8B62980099E28988BFC2B9EC79829FE81362887842E68FF0C7C2CCE056E2896C89E2888098E28AA8BBC299FC1AC280081372887842E69EE0C7CA8CE046E289E089E289C899E28AA8BEC2993C1AE28008837E882852C69EE0874288E046E2886099E289689FCE8AD8BFC2999C09F680088376880846C69CA88382880042A289D08DE289F098C28AF8BFC289FC88F280088376880857C29CA893C2888043A289508DE288F0D9428BF0AFC289F4888A800883F2880857829C2891C3889047F2898885E2899081428990AF8289FC8BE3800893F6880847C2DC0894E389944F62888899668918914289803582CB8C8AF3;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hCBAC80F38DA845828DF44582840124029375A4A288D108A2FFFFFFFDE0408082CAEC80968DF855828CE4408284012006917194C280510B82DFFFFFFC8000000288EC84A28FFC4586880C648A860124128179900280510F82800000009FBF7F7C8BA080BA8FEC40828808618286012C028179901280510702800000009FBF7F7C8BB081BA8CAC408289E0618286812C1281791002805007029FBF7F7C8000000089B881828CB440828BE07782868322028139909280400F029FBF7F7D8000000089A4C3928FF444828A00260A8792227281199022A0001F03E0408081FFFFFFFF89A0C1928FD440828800260687B720C280199002E0001F03E0408083FFFFFFFF;
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X22_Y21_N0
|
|
cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a8 (
|
|
.portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\CLOCK_50~inputclkctrl_outclk ),
|
|
.clk1(\CLOCK_50~inputclkctrl_outclk ),
|
|
.ena0(\z80_|address_pins_|abus[13]~20_combout ),
|
|
.ena1(gnd),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[0]~46_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain({\~GND~combout }),
|
|
.portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4],
|
|
\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk0_core_clock_enable = "ena0";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .clk1_core_clock_enable = "ena1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .data_interleave_width_in_bits = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file = "ula/test_scr.hex";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .init_file_layout = "port_a";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mixed_port_feed_through_mode = "dont_care";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .operation_mode = "bidir_dual_port";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_address_width = 13;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_byte_enable_clock = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_out_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_data_width = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_address = 0;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_first_bit_number = 0;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_last_address = 8191;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_depth = 16384;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_logical_ram_width = 8;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_address_width = 13;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_in_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_out_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_data_width = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_address = 0;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_first_bit_number = 0;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_last_address = 8191;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_depth = 16384;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_logical_ram_width = 8;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_read_enable_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .port_b_write_enable_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .ram_block_type = "M9K";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a8 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y14_N4
|
|
cycloneive_lcell_comb \Selector2~0 (
|
|
// Equation(s):
|
|
// \Selector2~0_combout = (\Selector3~0_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ) # (!\z80_|address_pins_|abus[14]~23_combout )))) # (!\Selector3~0_combout &
|
|
// (\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout & (\z80_|address_pins_|abus[14]~23_combout )))
|
|
|
|
.dataa(\ram0|altsyncram_component|auto_generated|ram_block1a0~portadataout ),
|
|
.datab(\Selector3~0_combout ),
|
|
.datac(\z80_|address_pins_|abus[14]~23_combout ),
|
|
.datad(\ram0|altsyncram_component|auto_generated|ram_block1a8~portadataout ),
|
|
.cin(gnd),
|
|
.combout(\Selector2~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \Selector2~0 .lut_mask = 16'hEC2C;
|
|
defparam \Selector2~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X22_Y31_N0
|
|
cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a0 (
|
|
.portawe(vcc),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(!\z80_|address_pins_|abus[13]~20_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain(1'b0),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\rom|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .clk0_core_clock_enable = "ena0";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file = "./rom/gw03.hex";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 13;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 8191;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 16384;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 8;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none";
|
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defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 13;
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defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 1;
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defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K";
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defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h1EEA3633EFEA856D05BA968C1B3C30CA1788DD95D16B8F914DDDFC3EE5C69945DF7D7BF31C6072BFA7993996AB7DD2F3EE4009844CC9D6CF9E583AEC48A52F2904B57D8E0D755851232838F9B5348838530D7AF95411555D263B8CA86A5D29D7CE4B65409D6F04C5709A56C241C3BCEF07459A416EB4E8F3D73CC714F4333AFE605D53A5C955D5D1412F8361617A54446971FD187442A60FB04457857BECC3120A01FDC7FE2CBF038A61DEE5FCE2D10C8F35FBF80C05ABFF4B6935287B125E8D56F9FDFE7D64C1F4E1F5641845CD17E836B97780400C702523FA8E7C7BBD6F0666591A35ADD26B6B7E33CA56E9AB329EFA7E68F98AE7CE9507755C74C430286A;
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defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'h88537A811D4EF6CD9668CCD3E2E7A8041788DCA5F7E08AF52AF5276078304DEB75B74BB9AC3C1A492952F7EEAA0E7CF9FBEDD0FB47EEFDCC3734B816F355C913CD2E1AF14C30545297A91BED3AEAEFF8F696B5F4FC80BC6B1A2559492E9198E4A5875745B625C6CA7A7292332492D139728A689DA1AE78B6B44CE4F4A4EA5A22F331598B364EF27516CC49A4662C5E5C92ED140D96373678F833AE434698237599716B8CBAE2D3D061F2C3D6337AB435B5C2144AB6FA2F8BB51357801066B6589467DA6C480E6D19CEEA8451CEFA88FD70E7925B0302F877F87FA833FBD147E937309C08305A10187707E3D57DDE4931F1D9E97A8F378981ABBF8D7B6B7539C3;
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defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'h763DD7AA7EED3F4AD4EA7491ADE6F14E6DBADD0F090A8DF34D7BAD35DD2275F0BCCF19EEF299751C919C9C13C6FB9ED711AC4DA7D947CC79E9B6323EF6CE62638CEBCB187AE5D44ECA689C9BD4E5AE544DEA7E90D186B9F335F3323877AAD54196CE81973CB555904419599375501366EC343561BCF83357F8823671393B278C1C387A7970C7F3E688673CF5975EE3E5FF105CFCCFAB725D698FB088B063063C7833830C7B2C7AFB8A8D203C312306DA0E72641FFB93D59B5EC84F44AD55F4B884735325ACC969B2EAE10A1478D866F667DDEF7BBF75E6958B6D02DC6D0F807660A229B98541E6FE734DE2280A9B57FCD5A9BEFEF7CDA5ABEB44FD73D2794D56;
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defparam \rom|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'hD0734B461A36980411EB2A6C1BE76029258777EF227A8F6E84F74C4436098F67BA611013110188547995B108BB2DAE76F423A0D98845F9248BDFA45E10CA403A5E2B1A3E16869E1D37BCE906B82F401CBD467617DB34D9E0C80B5E6E10063EC4BD52921D249E377D95CFAAA309EEDAA57DA85F55DBB7048A69A4C801013948B617F7F5724D40707E6FF30002982023020449B4680C45D1CE6D8EB30A061DB8FEDD6E630C15271E48CA801988654FB501D5393392EE765C1EC95C1E4D86F18A965372B72B484E2F2664B735B69A5AB532B086BA4C62AD6D56EECBDB6984B251454845BD5B243DAED2B2489B313A35C50252AFD3E0B76FEF342335C7F1321D92FF;
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// synopsys translate_on
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// Location: LCCOMB_X23_Y14_N28
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cycloneive_lcell_comb \Selector2~1 (
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// Equation(s):
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// \Selector2~1_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\Selector2~0_combout )))) # (!\z80_|address_pins_|abus[14]~23_combout & ((\Selector2~0_combout & (\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout )) #
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// (!\Selector2~0_combout & ((\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout )))))
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.dataa(\rom|altsyncram_component|auto_generated|ram_block1a8~portadataout ),
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.datab(\z80_|address_pins_|abus[14]~23_combout ),
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.datac(\Selector2~0_combout ),
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.datad(\rom|altsyncram_component|auto_generated|ram_block1a0~portadataout ),
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.cin(gnd),
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.combout(\Selector2~1_combout ),
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.cout());
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// synopsys translate_off
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defparam \Selector2~1 .lut_mask = 16'hE3E0;
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defparam \Selector2~1 .sum_lutc_input = "datac";
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// synopsys translate_on
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// Location: LCCOMB_X23_Y14_N30
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cycloneive_lcell_comb \D[0]~83 (
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// Equation(s):
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// \D[0]~83_combout = (\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\z80_|address_pins_|DFFE_apin_latch [15] & (\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout )) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\Selector2~1_combout
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// ))))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout ))
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.dataa(\ram1|altsyncram_component|auto_generated|mux2|result_node[0]~5_combout ),
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.datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
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.datac(\z80_|address_pins_|DFFE_apin_latch [15]),
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.datad(\Selector2~1_combout ),
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.cin(gnd),
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.combout(\D[0]~83_combout ),
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.cout());
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// synopsys translate_off
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defparam \D[0]~83 .lut_mask = 16'hAEA2;
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defparam \D[0]~83 .sum_lutc_input = "datac";
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// synopsys translate_on
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// Location: LCCOMB_X23_Y14_N14
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cycloneive_lcell_comb \D[0]~45 (
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// Equation(s):
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// \D[0]~45_combout = ((\Equal2~0_combout & (\D[0]~44_combout )) # (!\Equal2~0_combout & ((\D[0]~83_combout )))) # (!\Equal2~1_combout )
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.dataa(\Equal2~0_combout ),
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.datab(\D[0]~44_combout ),
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.datac(\D[0]~83_combout ),
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.datad(\Equal2~1_combout ),
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.cin(gnd),
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.combout(\D[0]~45_combout ),
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.cout());
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// synopsys translate_off
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defparam \D[0]~45 .lut_mask = 16'hD8FF;
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defparam \D[0]~45 .sum_lutc_input = "datac";
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// synopsys translate_on
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// Location: LCCOMB_X23_Y14_N0
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cycloneive_lcell_comb \D[0]~46 (
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// Equation(s):
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// \D[0]~46_combout = (\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\D[0]~45_combout & \z80_|data_pins_|dout [0])))) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\D[0]~45_combout )) # (!\Equal2~1_combout )))
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.dataa(\z80_|pin_control_|bus_db_pin_oe~15_combout ),
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.datab(\Equal2~1_combout ),
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.datac(\D[0]~45_combout ),
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.datad(\z80_|data_pins_|dout [0]),
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.cin(gnd),
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.combout(\D[0]~46_combout ),
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.cout());
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// synopsys translate_off
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defparam \D[0]~46 .lut_mask = 16'hF151;
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defparam \D[0]~46 .sum_lutc_input = "datac";
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// synopsys translate_on
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// Location: LCCOMB_X30_Y13_N26
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cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] (
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// Equation(s):
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// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [0] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[0]~17_combout ) # ((\D[0]~46_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout &
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// (\D[0]~46_combout & ((\z80_|pin_control_|bus_db_pin_re~combout ))))
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.dataa(\z80_|execute_|ctl_bus_db_we~7_combout ),
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.datab(\D[0]~46_combout ),
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.datac(\z80_|bus_control_|db[0]~17_combout ),
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.datad(\z80_|pin_control_|bus_db_pin_re~combout ),
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.cin(gnd),
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.combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]),
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.cout());
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// synopsys translate_off
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defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .lut_mask = 16'hECA0;
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defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[0] .sum_lutc_input = "datac";
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// synopsys translate_on
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// Location: FF_X30_Y13_N27
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dffeas \z80_|data_pins_|dout[0] (
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.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
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.d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [0]),
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.asdata(vcc),
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.clrn(vcc),
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.aload(gnd),
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.sclr(gnd),
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.sload(gnd),
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.ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ),
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.devclrn(devclrn),
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.devpor(devpor),
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.q(\z80_|data_pins_|dout [0]),
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.prn(vcc));
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// synopsys translate_off
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defparam \z80_|data_pins_|dout[0] .is_wysiwyg = "true";
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defparam \z80_|data_pins_|dout[0] .power_up = "low";
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// synopsys translate_on
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// Location: LCCOMB_X29_Y13_N10
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cycloneive_lcell_comb \z80_|bus_control_|db[0]~16 (
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// Equation(s):
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// \z80_|bus_control_|db[0]~16_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|data_pins_|dout [0]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))
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.dataa(\z80_|data_pins_|dout [0]),
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.datab(\z80_|bus_control_|db[0]~4_combout ),
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.datac(\z80_|execute_|ctl_bus_db_oe~combout ),
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.datad(gnd),
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.cin(gnd),
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.combout(\z80_|bus_control_|db[0]~16_combout ),
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.cout());
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// synopsys translate_off
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defparam \z80_|bus_control_|db[0]~16 .lut_mask = 16'h8C8C;
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defparam \z80_|bus_control_|db[0]~16 .sum_lutc_input = "datac";
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// synopsys translate_on
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// Location: LCCOMB_X29_Y13_N0
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cycloneive_lcell_comb \z80_|bus_control_|db[0]~17 (
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// Equation(s):
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// \z80_|bus_control_|db[0]~17_combout = ((\z80_|bus_control_|db[0]~16_combout & ((\z80_|alu_control_|db[0]~12_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))) # (!\z80_|bus_control_|db[0]~6_combout )
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.dataa(\z80_|execute_|ctl_bus_db_we~7_combout ),
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.datab(\z80_|alu_control_|db[0]~12_combout ),
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.datac(\z80_|bus_control_|db[0]~6_combout ),
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.datad(\z80_|bus_control_|db[0]~16_combout ),
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.cin(gnd),
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.combout(\z80_|bus_control_|db[0]~17_combout ),
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.cout());
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// synopsys translate_off
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defparam \z80_|bus_control_|db[0]~17 .lut_mask = 16'hDF0F;
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defparam \z80_|bus_control_|db[0]~17 .sum_lutc_input = "datac";
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// synopsys translate_on
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// Location: FF_X29_Y13_N1
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dffeas \z80_|ir_|opcode[0] (
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.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
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.d(\z80_|bus_control_|db[0]~17_combout ),
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.asdata(vcc),
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.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
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.aload(gnd),
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.sclr(gnd),
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.sload(gnd),
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.ena(\z80_|execute_|ctl_ir_we~13_combout ),
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.devclrn(devclrn),
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.devpor(devpor),
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.q(\z80_|ir_|opcode [0]),
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.prn(vcc));
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// synopsys translate_off
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defparam \z80_|ir_|opcode[0] .is_wysiwyg = "true";
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defparam \z80_|ir_|opcode[0] .power_up = "low";
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// synopsys translate_on
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// Location: LCCOMB_X27_Y16_N6
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cycloneive_lcell_comb \z80_|pla_decode_|Equal3~2 (
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// Equation(s):
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// \z80_|pla_decode_|Equal3~2_combout = (\z80_|ir_|opcode [0] & (\z80_|pla_decode_|Equal3~1_combout & (\z80_|pla_decode_|Equal52~0_combout & \z80_|pla_decode_|Equal3~0_combout )))
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.dataa(\z80_|ir_|opcode [0]),
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.datab(\z80_|pla_decode_|Equal3~1_combout ),
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.datac(\z80_|pla_decode_|Equal52~0_combout ),
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.datad(\z80_|pla_decode_|Equal3~0_combout ),
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.cin(gnd),
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.combout(\z80_|pla_decode_|Equal3~2_combout ),
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.cout());
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// synopsys translate_off
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defparam \z80_|pla_decode_|Equal3~2 .lut_mask = 16'h8000;
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defparam \z80_|pla_decode_|Equal3~2 .sum_lutc_input = "datac";
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// synopsys translate_on
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// Location: LCCOMB_X29_Y17_N16
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cycloneive_lcell_comb \z80_|pla_decode_|Equal43~0 (
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// Equation(s):
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// \z80_|pla_decode_|Equal43~0_combout = (\z80_|pla_decode_|Equal1~7_combout & (\z80_|pla_decode_|Equal32~0_combout & (\z80_|ir_|opcode [5] & \z80_|pla_decode_|Equal3~1_combout )))
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.dataa(\z80_|pla_decode_|Equal1~7_combout ),
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.datab(\z80_|pla_decode_|Equal32~0_combout ),
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.datac(\z80_|ir_|opcode [5]),
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.datad(\z80_|pla_decode_|Equal3~1_combout ),
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|
.cin(gnd),
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.combout(\z80_|pla_decode_|Equal43~0_combout ),
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.cout());
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|
// synopsys translate_off
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defparam \z80_|pla_decode_|Equal43~0 .lut_mask = 16'h8000;
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defparam \z80_|pla_decode_|Equal43~0 .sum_lutc_input = "datac";
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// synopsys translate_on
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|
|
// Location: LCCOMB_X29_Y17_N24
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cycloneive_lcell_comb \z80_|interrupts_|test1~2 (
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|
// Equation(s):
|
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// \z80_|interrupts_|test1~2_combout = (!\z80_|pla_decode_|Equal3~2_combout & (!\z80_|pla_decode_|Equal43~0_combout & (!\z80_|pla_decode_|Equal79~0_combout & !\z80_|pla_decode_|Equal36~0_combout )))
|
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.dataa(\z80_|pla_decode_|Equal3~2_combout ),
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|
.datab(\z80_|pla_decode_|Equal43~0_combout ),
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.datac(\z80_|pla_decode_|Equal79~0_combout ),
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|
.datad(\z80_|pla_decode_|Equal36~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|interrupts_|test1~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|interrupts_|test1~2 .lut_mask = 16'h0001;
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|
defparam \z80_|interrupts_|test1~2 .sum_lutc_input = "datac";
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|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y13_N22
|
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cycloneive_lcell_comb \z80_|interrupts_|test1~3 (
|
|
// Equation(s):
|
|
// \z80_|interrupts_|test1~3_combout = (!\z80_|execute_|setM1~54_combout & (((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|interrupts_|test1~2_combout )) # (!\z80_|sequencer_|DFFE_T4_ff~q )))
|
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|
|
.dataa(\z80_|sequencer_|DFFE_T4_ff~q ),
|
|
.datab(\z80_|execute_|setM1~54_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.datad(\z80_|interrupts_|test1~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|interrupts_|test1~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|interrupts_|test1~3 .lut_mask = 16'h3331;
|
|
defparam \z80_|interrupts_|test1~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X28_Y13_N1
|
|
dffeas \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|interrupts_|test1~3_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .is_wysiwyg = "true";
|
|
defparam \z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y14_N6
|
|
cycloneive_lcell_comb \z80_|clk_delay_|SYNTHESIZED_WIRE_4 (
|
|
// Equation(s):
|
|
// \z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout = (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (!\z80_|sequencer_|DFFE_T1_ff~q & (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|interrupts_|DFFE_inst44~q )))
|
|
|
|
.dataa(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ),
|
|
.datab(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datac(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.datad(\z80_|interrupts_|DFFE_inst44~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .lut_mask = 16'h0100;
|
|
defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X29_Y14_N7
|
|
dffeas \z80_|clk_delay_|SYNTHESIZED_WIRE_7 (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|clk_delay_|SYNTHESIZED_WIRE_4~combout ),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .is_wysiwyg = "true";
|
|
defparam \z80_|clk_delay_|SYNTHESIZED_WIRE_7 .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y12_N12
|
|
cycloneive_lcell_comb \z80_|clk_delay_|hold_clk_iorq (
|
|
// Equation(s):
|
|
// \z80_|clk_delay_|hold_clk_iorq~combout = (!\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q & !\z80_|clk_delay_|DFF_inst5~q )
|
|
|
|
.dataa(\z80_|clk_delay_|SYNTHESIZED_WIRE_7~q ),
|
|
.datab(\z80_|clk_delay_|DFF_inst5~q ),
|
|
.datac(gnd),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|clk_delay_|hold_clk_iorq~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|clk_delay_|hold_clk_iorq .lut_mask = 16'h1111;
|
|
defparam \z80_|clk_delay_|hold_clk_iorq .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X26_Y13_N31
|
|
dffeas \z80_|sequencer_|DFFE_T4_ff (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|sequencer_|SYNTHESIZED_WIRE_15~combout ),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|clk_delay_|hold_clk_iorq~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|sequencer_|DFFE_T4_ff~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|sequencer_|DFFE_T4_ff .is_wysiwyg = "true";
|
|
defparam \z80_|sequencer_|DFFE_T4_ff .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y14_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_eval_cond~0 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_eval_cond~0_combout = (\z80_|sequencer_|DFFE_T4_ff~q & !\z80_|sequencer_|DFFE_M1_ff~q )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|sequencer_|DFFE_T4_ff~q ),
|
|
.datad(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_eval_cond~0 .lut_mask = 16'h00F0;
|
|
defparam \z80_|execute_|ctl_eval_cond~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y17_N22
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_mRead~27 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mRead~27_combout = (\z80_|execute_|ctl_mRead~23_combout & (((!\z80_|pla_decode_|Equal38~2_combout & !\z80_|pla_decode_|Equal52~1_combout )) # (!\z80_|execute_|ctl_eval_cond~0_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.datab(\z80_|pla_decode_|Equal38~2_combout ),
|
|
.datac(\z80_|execute_|ctl_mRead~23_combout ),
|
|
.datad(\z80_|pla_decode_|Equal52~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mRead~27_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mRead~27 .lut_mask = 16'h5070;
|
|
defparam \z80_|execute_|ctl_mRead~27 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y17_N20
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_mRead~26 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mRead~26_combout = (\z80_|execute_|ctl_mRead~34_combout ) # ((\z80_|pla_decode_|Equal21~1_combout ) # (\z80_|pla_decode_|Equal37~0_combout ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|execute_|ctl_mRead~34_combout ),
|
|
.datac(\z80_|pla_decode_|Equal21~1_combout ),
|
|
.datad(\z80_|pla_decode_|Equal37~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mRead~26_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mRead~26 .lut_mask = 16'hFFFC;
|
|
defparam \z80_|execute_|ctl_mRead~26 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y17_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_mRead~28 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_mRead~28_combout = (\z80_|execute_|ctl_mRead~27_combout & (\z80_|execute_|ctl_mRead~22_combout & ((!\z80_|execute_|ctl_mRead~9_combout ) # (!\z80_|execute_|ctl_mRead~26_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_mRead~27_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~26_combout ),
|
|
.datac(\z80_|execute_|ctl_mRead~22_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~9_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_mRead~28_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_mRead~28 .lut_mask = 16'h20A0;
|
|
defparam \z80_|execute_|ctl_mRead~28 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y15_N12
|
|
cycloneive_lcell_comb \z80_|execute_|nextM~6 (
|
|
// Equation(s):
|
|
// \z80_|execute_|nextM~6_combout = (((\z80_|decode_state_|use_ixiy~combout & \z80_|pla_decode_|Equal49~0_combout )) # (!\z80_|execute_|nextM~3_combout )) # (!\z80_|execute_|ixy_d~17_combout )
|
|
|
|
.dataa(\z80_|decode_state_|use_ixiy~combout ),
|
|
.datab(\z80_|execute_|ixy_d~17_combout ),
|
|
.datac(\z80_|execute_|nextM~3_combout ),
|
|
.datad(\z80_|pla_decode_|Equal49~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|nextM~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|nextM~6 .lut_mask = 16'hBF3F;
|
|
defparam \z80_|execute_|nextM~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y15_N10
|
|
cycloneive_lcell_comb \z80_|execute_|nextM~7 (
|
|
// Equation(s):
|
|
// \z80_|execute_|nextM~7_combout = ((\z80_|execute_|nextM~6_combout & ((\z80_|execute_|ctl_state_alu~2_combout ) # (\z80_|execute_|ixy_d~8_combout )))) # (!\z80_|execute_|nextM~4_combout )
|
|
|
|
.dataa(\z80_|execute_|nextM~6_combout ),
|
|
.datab(\z80_|execute_|ctl_state_alu~2_combout ),
|
|
.datac(\z80_|execute_|ixy_d~8_combout ),
|
|
.datad(\z80_|execute_|nextM~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|nextM~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|nextM~7 .lut_mask = 16'hA8FF;
|
|
defparam \z80_|execute_|nextM~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y15_N6
|
|
cycloneive_lcell_comb \z80_|execute_|nextM~8 (
|
|
// Equation(s):
|
|
// \z80_|execute_|nextM~8_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((\z80_|execute_|ixy_d~8_combout & !\z80_|execute_|ctl_flags_bus~1_combout )) # (!\z80_|alu_control_|flags_cond_true~q ))) #
|
|
// (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (\z80_|execute_|ixy_d~8_combout & ((!\z80_|execute_|ctl_flags_bus~1_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ),
|
|
.datab(\z80_|execute_|ixy_d~8_combout ),
|
|
.datac(\z80_|alu_control_|flags_cond_true~q ),
|
|
.datad(\z80_|execute_|ctl_flags_bus~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|nextM~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|nextM~8 .lut_mask = 16'h0ACE;
|
|
defparam \z80_|execute_|nextM~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y14_N26
|
|
cycloneive_lcell_comb \z80_|execute_|nextM~9 (
|
|
// Equation(s):
|
|
// \z80_|execute_|nextM~9_combout = (\z80_|pla_decode_|Equal55~0_combout & (\z80_|execute_|ctl_mWrite~4_combout & ((\z80_|execute_|ctl_mRead~9_combout ) # (\z80_|execute_|ixy_d~6_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_mRead~9_combout ),
|
|
.datab(\z80_|pla_decode_|Equal55~0_combout ),
|
|
.datac(\z80_|execute_|ixy_d~6_combout ),
|
|
.datad(\z80_|execute_|ctl_mWrite~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|nextM~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|nextM~9 .lut_mask = 16'hC800;
|
|
defparam \z80_|execute_|nextM~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y15_N6
|
|
cycloneive_lcell_comb \z80_|execute_|nextM~10 (
|
|
// Equation(s):
|
|
// \z80_|execute_|nextM~10_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ) # ((\z80_|execute_|nextM~9_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|ixy_d~9_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~34_combout ),
|
|
.datac(\z80_|execute_|nextM~9_combout ),
|
|
.datad(\z80_|execute_|ixy_d~9_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|nextM~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|nextM~10 .lut_mask = 16'hFEFA;
|
|
defparam \z80_|execute_|nextM~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y15_N20
|
|
cycloneive_lcell_comb \z80_|execute_|nextM~12 (
|
|
// Equation(s):
|
|
// \z80_|execute_|nextM~12_combout = (\z80_|execute_|nextM~8_combout ) # ((\z80_|execute_|ctl_alu_op_low~46_combout ) # ((\z80_|execute_|nextM~10_combout ) # (!\z80_|execute_|nextM~11_combout )))
|
|
|
|
.dataa(\z80_|execute_|nextM~8_combout ),
|
|
.datab(\z80_|execute_|ctl_alu_op_low~46_combout ),
|
|
.datac(\z80_|execute_|nextM~10_combout ),
|
|
.datad(\z80_|execute_|nextM~11_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|nextM~12_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|nextM~12 .lut_mask = 16'hFEFF;
|
|
defparam \z80_|execute_|nextM~12 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y15_N24
|
|
cycloneive_lcell_comb \z80_|execute_|nextM~15 (
|
|
// Equation(s):
|
|
// \z80_|execute_|nextM~15_combout = (\z80_|sequencer_|DFFE_T3_ff~q & (\z80_|sequencer_|DFFE_M2_ff~q & ((\z80_|execute_|ctl_mRead~5_combout ) # (!\z80_|execute_|fMRead~12_combout ))))
|
|
|
|
.dataa(\z80_|execute_|fMRead~12_combout ),
|
|
.datab(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.datac(\z80_|sequencer_|DFFE_M2_ff~q ),
|
|
.datad(\z80_|execute_|ctl_mRead~5_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|nextM~15_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|nextM~15 .lut_mask = 16'hC040;
|
|
defparam \z80_|execute_|nextM~15 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y15_N26
|
|
cycloneive_lcell_comb \z80_|execute_|nextM~13 (
|
|
// Equation(s):
|
|
// \z80_|execute_|nextM~13_combout = (\z80_|execute_|nextM~7_combout ) # ((\z80_|execute_|nextM~12_combout ) # (\z80_|execute_|nextM~15_combout ))
|
|
|
|
.dataa(\z80_|execute_|nextM~7_combout ),
|
|
.datab(\z80_|execute_|nextM~12_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|execute_|nextM~15_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|nextM~13_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|nextM~13 .lut_mask = 16'hFFEE;
|
|
defparam \z80_|execute_|nextM~13 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y14_N6
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~41 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~41_combout = (\z80_|execute_|setM1~40_combout & !\z80_|execute_|ctl_mWrite~7_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|execute_|setM1~40_combout ),
|
|
.datac(\z80_|execute_|ctl_mWrite~7_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~41_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~41 .lut_mask = 16'h0C0C;
|
|
defparam \z80_|execute_|setM1~41 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y12_N8
|
|
cycloneive_lcell_comb \z80_|execute_|nextM~5 (
|
|
// Equation(s):
|
|
// \z80_|execute_|nextM~5_combout = (\z80_|execute_|ctl_eval_cond~0_combout & (((!\z80_|execute_|setM1~41_combout ) # (!\z80_|execute_|setM1~47_combout )) # (!\z80_|execute_|nextM~2_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.datab(\z80_|execute_|nextM~2_combout ),
|
|
.datac(\z80_|execute_|setM1~47_combout ),
|
|
.datad(\z80_|execute_|setM1~41_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|nextM~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|nextM~5 .lut_mask = 16'h2AAA;
|
|
defparam \z80_|execute_|nextM~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y11_N0
|
|
cycloneive_lcell_comb \z80_|execute_|nextM~14 (
|
|
// Equation(s):
|
|
// \z80_|execute_|nextM~14_combout = (((\z80_|execute_|nextM~13_combout ) # (\z80_|execute_|nextM~5_combout )) # (!\z80_|execute_|ctl_mWrite~14_combout )) # (!\z80_|execute_|ctl_mRead~28_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_mRead~28_combout ),
|
|
.datab(\z80_|execute_|ctl_mWrite~14_combout ),
|
|
.datac(\z80_|execute_|nextM~13_combout ),
|
|
.datad(\z80_|execute_|nextM~5_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|nextM~14_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|nextM~14 .lut_mask = 16'hFFF7;
|
|
defparam \z80_|execute_|nextM~14 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y13_N24
|
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cycloneive_lcell_comb \z80_|sequencer_|ena_M (
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// Equation(s):
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// \z80_|sequencer_|ena_M~combout = (\z80_|execute_|setM1~54_combout & !\z80_|execute_|nextM~14_combout )
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.dataa(gnd),
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.datab(\z80_|execute_|setM1~54_combout ),
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.datac(gnd),
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.datad(\z80_|execute_|nextM~14_combout ),
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.cin(gnd),
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.combout(\z80_|sequencer_|ena_M~combout ),
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.cout());
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// synopsys translate_off
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defparam \z80_|sequencer_|ena_M .lut_mask = 16'h00CC;
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defparam \z80_|sequencer_|ena_M .sum_lutc_input = "datac";
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// synopsys translate_on
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// Location: FF_X26_Y13_N25
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dffeas \z80_|sequencer_|DFFE_T1_ff (
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.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
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.d(\z80_|sequencer_|ena_M~combout ),
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.asdata(vcc),
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.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
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.aload(gnd),
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.sclr(gnd),
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.sload(gnd),
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.ena(\z80_|clk_delay_|hold_clk_iorq~combout ),
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.devclrn(devclrn),
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.devpor(devpor),
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.q(\z80_|sequencer_|DFFE_T1_ff~q ),
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.prn(vcc));
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// synopsys translate_off
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defparam \z80_|sequencer_|DFFE_T1_ff .is_wysiwyg = "true";
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defparam \z80_|sequencer_|DFFE_T1_ff .power_up = "low";
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// synopsys translate_on
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// Location: LCCOMB_X26_Y13_N20
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cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_13 (
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// Equation(s):
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// \z80_|sequencer_|SYNTHESIZED_WIRE_13~combout = (!\z80_|sequencer_|DFFE_T1_ff~q & (\z80_|execute_|setM1~54_combout & !\z80_|execute_|nextM~14_combout ))
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.dataa(gnd),
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.datab(\z80_|sequencer_|DFFE_T1_ff~q ),
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.datac(\z80_|execute_|setM1~54_combout ),
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.datad(\z80_|execute_|nextM~14_combout ),
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.cin(gnd),
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.combout(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ),
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.cout());
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// synopsys translate_off
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defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .lut_mask = 16'h0030;
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defparam \z80_|sequencer_|SYNTHESIZED_WIRE_13 .sum_lutc_input = "datac";
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// synopsys translate_on
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// Location: FF_X26_Y13_N21
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dffeas \z80_|sequencer_|DFFE_T2_ff (
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.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
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.d(\z80_|sequencer_|SYNTHESIZED_WIRE_13~combout ),
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.asdata(vcc),
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.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
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.aload(gnd),
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.sclr(gnd),
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.sload(gnd),
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.ena(\z80_|clk_delay_|hold_clk_iorq~combout ),
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.devclrn(devclrn),
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.devpor(devpor),
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.q(\z80_|sequencer_|DFFE_T2_ff~q ),
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.prn(vcc));
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// synopsys translate_off
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defparam \z80_|sequencer_|DFFE_T2_ff .is_wysiwyg = "true";
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defparam \z80_|sequencer_|DFFE_T2_ff .power_up = "low";
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// synopsys translate_on
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// Location: LCCOMB_X26_Y13_N16
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cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_14 (
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// Equation(s):
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// \z80_|sequencer_|SYNTHESIZED_WIRE_14~combout = (\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|execute_|setM1~54_combout & !\z80_|execute_|nextM~14_combout ))
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.dataa(gnd),
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.datab(\z80_|sequencer_|DFFE_T2_ff~q ),
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.datac(\z80_|execute_|setM1~54_combout ),
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.datad(\z80_|execute_|nextM~14_combout ),
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.cin(gnd),
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.combout(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ),
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.cout());
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// synopsys translate_off
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defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .lut_mask = 16'h00C0;
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defparam \z80_|sequencer_|SYNTHESIZED_WIRE_14 .sum_lutc_input = "datac";
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// synopsys translate_on
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// Location: FF_X26_Y13_N17
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dffeas \z80_|sequencer_|DFFE_T3_ff (
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.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
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.d(\z80_|sequencer_|SYNTHESIZED_WIRE_14~combout ),
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.asdata(vcc),
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.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
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.aload(gnd),
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.sclr(gnd),
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.sload(gnd),
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.ena(\z80_|clk_delay_|hold_clk_iorq~combout ),
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.devclrn(devclrn),
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.devpor(devpor),
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.q(\z80_|sequencer_|DFFE_T3_ff~q ),
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.prn(vcc));
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// synopsys translate_off
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defparam \z80_|sequencer_|DFFE_T3_ff .is_wysiwyg = "true";
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defparam \z80_|sequencer_|DFFE_T3_ff .power_up = "low";
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// synopsys translate_on
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// Location: LCCOMB_X29_Y14_N12
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cycloneive_lcell_comb \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 (
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// Equation(s):
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// \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout = (!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T3_ff~q )
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.dataa(gnd),
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.datab(gnd),
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.datac(\z80_|sequencer_|DFFE_M1_ff~q ),
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.datad(\z80_|sequencer_|DFFE_T3_ff~q ),
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.cin(gnd),
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.combout(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ),
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.cout());
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// synopsys translate_off
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defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .lut_mask = 16'h0F00;
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defparam \z80_|execute_|ctl_reg_sys_hilo_1M1T3_3 .sum_lutc_input = "datac";
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// synopsys translate_on
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// Location: LCCOMB_X27_Y16_N10
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cycloneive_lcell_comb \z80_|execute_|ctl_66_oe~2 (
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// Equation(s):
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// \z80_|execute_|ctl_66_oe~2_combout = (\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout & (\z80_|pla_decode_|Equal52~0_combout & (\z80_|execute_|comb~0_combout & \z80_|ir_|opcode [0])))
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.dataa(\z80_|execute_|ctl_reg_sys_hilo_1M1T3_3~combout ),
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.datab(\z80_|pla_decode_|Equal52~0_combout ),
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.datac(\z80_|execute_|comb~0_combout ),
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.datad(\z80_|ir_|opcode [0]),
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.cin(gnd),
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.combout(\z80_|execute_|ctl_66_oe~2_combout ),
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.cout());
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// synopsys translate_off
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defparam \z80_|execute_|ctl_66_oe~2 .lut_mask = 16'h8000;
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defparam \z80_|execute_|ctl_66_oe~2 .sum_lutc_input = "datac";
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// synopsys translate_on
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// Location: FF_X30_Y17_N11
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dffeas \z80_|interrupts_|im1 (
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.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
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.d(\z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3_combout ),
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.asdata(vcc),
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.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
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.aload(gnd),
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.sclr(gnd),
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.sload(gnd),
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.ena(\z80_|execute_|ctl_im_we~combout ),
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.devclrn(devclrn),
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.devpor(devpor),
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.q(\z80_|interrupts_|im1~q ),
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.prn(vcc));
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// synopsys translate_off
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defparam \z80_|interrupts_|im1 .is_wysiwyg = "true";
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defparam \z80_|interrupts_|im1 .power_up = "low";
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// synopsys translate_on
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// Location: LCCOMB_X28_Y13_N28
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cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~0 (
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// Equation(s):
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// \z80_|execute_|ctl_bus_ff_oe~0_combout = (\z80_|interrupts_|DFFE_inst44~q & ((\z80_|interrupts_|im1~q ) # ((\z80_|interrupts_|im2~q & !\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))))
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.dataa(\z80_|interrupts_|DFFE_inst44~q ),
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.datab(\z80_|interrupts_|im2~q ),
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.datac(\z80_|interrupts_|im1~q ),
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.datad(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ),
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.cin(gnd),
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.combout(\z80_|execute_|ctl_bus_ff_oe~0_combout ),
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.cout());
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// synopsys translate_off
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defparam \z80_|execute_|ctl_bus_ff_oe~0 .lut_mask = 16'hA0A8;
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defparam \z80_|execute_|ctl_bus_ff_oe~0 .sum_lutc_input = "datac";
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// synopsys translate_on
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// Location: LCCOMB_X28_Y13_N6
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cycloneive_lcell_comb \z80_|execute_|ctl_bus_ff_oe~1 (
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// Equation(s):
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// \z80_|execute_|ctl_bus_ff_oe~1_combout = (\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (((!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )))) # (!\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q & (\z80_|execute_|ctl_bus_ff_oe~0_combout &
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// ((\z80_|execute_|ctl_66_oe~2_combout ) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout ))))
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.dataa(\z80_|execute_|ctl_66_oe~2_combout ),
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.datab(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ),
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.datac(\z80_|interrupts_|in_nmi_ALTERA_SYNTHESIZED~q ),
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.datad(\z80_|execute_|ctl_bus_ff_oe~0_combout ),
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.cin(gnd),
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.combout(\z80_|execute_|ctl_bus_ff_oe~1_combout ),
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.cout());
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// synopsys translate_off
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defparam \z80_|execute_|ctl_bus_ff_oe~1 .lut_mask = 16'h3B30;
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defparam \z80_|execute_|ctl_bus_ff_oe~1 .sum_lutc_input = "datac";
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// synopsys translate_on
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// Location: LCCOMB_X28_Y13_N24
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cycloneive_lcell_comb \z80_|execute_|ctl_bus_zero_oe~0 (
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// Equation(s):
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// \z80_|execute_|ctl_bus_zero_oe~0_combout = (\z80_|pla_decode_|Equal33~1_combout & (\z80_|execute_|ctl_eval_cond~0_combout & ((\z80_|execute_|ctl_iorw~10_combout ) # (\z80_|execute_|ctl_alu_op_low~27_combout ))))
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.dataa(\z80_|pla_decode_|Equal33~1_combout ),
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.datab(\z80_|execute_|ctl_eval_cond~0_combout ),
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.datac(\z80_|execute_|ctl_iorw~10_combout ),
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.datad(\z80_|execute_|ctl_alu_op_low~27_combout ),
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.cin(gnd),
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.combout(\z80_|execute_|ctl_bus_zero_oe~0_combout ),
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.cout());
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// synopsys translate_off
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defparam \z80_|execute_|ctl_bus_zero_oe~0 .lut_mask = 16'h8880;
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defparam \z80_|execute_|ctl_bus_zero_oe~0 .sum_lutc_input = "datac";
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// synopsys translate_on
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// Location: LCCOMB_X28_Y13_N18
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cycloneive_lcell_comb \z80_|bus_control_|db[0]~4 (
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// Equation(s):
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// \z80_|bus_control_|db[0]~4_combout = (\z80_|execute_|ctl_bus_ff_oe~1_combout ) # ((!\z80_|execute_|ctl_bus_zero_oe~0_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q ))))
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.dataa(\z80_|execute_|ctl_bus_ff_oe~1_combout ),
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.datab(\z80_|execute_|ctl_bus_zero_oe~0_combout ),
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.datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ),
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.datad(\z80_|decode_state_|in_halt~q ),
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.cin(gnd),
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.combout(\z80_|bus_control_|db[0]~4_combout ),
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.cout());
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// synopsys translate_off
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defparam \z80_|bus_control_|db[0]~4 .lut_mask = 16'hBABB;
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defparam \z80_|bus_control_|db[0]~4 .sum_lutc_input = "datac";
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// synopsys translate_on
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// Location: LCCOMB_X31_Y13_N24
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cycloneive_lcell_comb \z80_|bus_control_|db[6]~8 (
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// Equation(s):
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// \z80_|bus_control_|db[6]~8_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[6]~22_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))
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.dataa(\z80_|bus_control_|db[0]~4_combout ),
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.datab(gnd),
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.datac(\z80_|execute_|ctl_bus_db_we~7_combout ),
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.datad(\z80_|alu_control_|db[6]~22_combout ),
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.cin(gnd),
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.combout(\z80_|bus_control_|db[6]~8_combout ),
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.cout());
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|
// synopsys translate_off
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defparam \z80_|bus_control_|db[6]~8 .lut_mask = 16'hAA0A;
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defparam \z80_|bus_control_|db[6]~8 .sum_lutc_input = "datac";
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// synopsys translate_on
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// Location: M9K_X22_Y7_N0
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cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a22 (
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.portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]),
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.portare(vcc),
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.portaaddrstall(gnd),
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.portbwe(gnd),
|
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.portbre(vcc),
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.portbaddrstall(gnd),
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.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
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|
.clk1(gnd),
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.ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ),
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.ena1(vcc),
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|
.ena2(vcc),
|
|
.ena3(vcc),
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.clr0(gnd),
|
|
.clr1(gnd),
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|
.portadatain({\D[6]~79_combout }),
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|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
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\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
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\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
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.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a22_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .clk0_core_clock_enable = "ena0";
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|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_offset_in_bits = 1;
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|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .data_interleave_width_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file = "led_patterns.mif";
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|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .init_file_layout = "port_a";
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|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
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|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .operation_mode = "single_port";
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|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_clear = "none";
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|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_address_width = 13;
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|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_byte_enable_clock = "none";
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|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clear = "none";
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|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_out_clock = "clock0";
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|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_data_width = 1;
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|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_address = 0;
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|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_first_bit_number = 6;
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|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_last_address = 8191;
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|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_depth = 32768;
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|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_logical_ram_width = 8;
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|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_a_read_during_write_mode = "new_data_with_nbe_read";
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|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_address_width = 13;
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|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .port_b_data_width = 1;
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|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .ram_block_type = "M9K";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a22 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X22_Y8_N0
|
|
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a30 (
|
|
.portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[6]~79_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a30_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .clk0_core_clock_enable = "ena0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .data_interleave_width_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file = "led_patterns.mif";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .init_file_layout = "port_a";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .operation_mode = "single_port";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_byte_enable_clock = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_out_clock = "clock0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_address = 0;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_first_bit_number = 6;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_last_address = 8191;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_depth = 32768;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_logical_ram_width = 8;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .port_b_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .ram_block_type = "M9K";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a30 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X22_Y11_N0
|
|
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a14 (
|
|
.portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[6]~79_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file = "led_patterns.mif";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "single_port";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 32768;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X22_Y10_N0
|
|
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a6 (
|
|
.portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[6]~79_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file = "led_patterns.mif";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "single_port";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 32768;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000042;
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y10_N16
|
|
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12 (
|
|
// Equation(s):
|
|
// \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ) #
|
|
// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (((\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout &
|
|
// !\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]))))
|
|
|
|
.dataa(\ram1|altsyncram_component|auto_generated|ram_block1a14~portadataout ),
|
|
.datab(\ram1|altsyncram_component|auto_generated|ram_block1a6~portadataout ),
|
|
.datac(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
|
|
.datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]),
|
|
.cin(gnd),
|
|
.combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12 .lut_mask = 16'hF0AC;
|
|
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y10_N22
|
|
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13 (
|
|
// Equation(s):
|
|
// \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout = (\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout & (((\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ) #
|
|
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1])))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout &
|
|
// ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]))))
|
|
|
|
.dataa(\ram1|altsyncram_component|auto_generated|ram_block1a22~portadataout ),
|
|
.datab(\ram1|altsyncram_component|auto_generated|ram_block1a30~portadataout ),
|
|
.datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~12_combout ),
|
|
.datad(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]),
|
|
.cin(gnd),
|
|
.combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13 .lut_mask = 16'hCAF0;
|
|
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X22_Y1_N0
|
|
cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a6 (
|
|
.portawe(vcc),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(!\z80_|address_pins_|abus[13]~20_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain(1'b0),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\rom|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file = "./rom/gw03.hex";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "rom";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock0";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_a_write_enable_clock = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h3C766E63DB6481CB39BC8C68831C724633186CC1BAE9D608A5DEF0FF219C28C1EFF4FDE394D0E19B6FD89186C23CF071E6F1CC8F7FC4F1E48756B0DCD8ED6D0C3DA139003D7A86B2F878DD99DAFB70DE1A19F3FB7DB3B8EF2633007664CB19992E43664448EFF06072648DBA32EDB76E26439BCCEF2DFBF664594B04FBAE72A84A3E508B49DC6BEAAB4F3F0CCCF6D8F568F2DA00EB384A7F53249323198000100408002024010408824080002008011482ED5615E40012EE630C3B2CDB2C13A736DB5B7BD2850018CF936621C6863095A73F7BE7442CB13110B9C0BBB96EEF16CE618EEDCFB393738178C476C367909F71307F6803F677575763DB2D8C3118E4;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h881331ED7AC4EFD38DFACDBB236790005719AEA2FAECCF0D126A30A27222D61BBA428334561F4EDB60C6BF8DB6E267BC56CB69BBCE636CCCB3B2B4B103CC46D5CEEC06DAECB0001569589D5F267AFE086C8FED5DE41DFEFF027DFDFF7FFBFBFDFFDFFF6FFFBDFFDFFF57FF7F7FB7FBBDFBDFFDBFF78FFDBFFEDDFFFDFFFEFF6FF7F7FDDFFEDFF6FF7FFEEFFEFEFC4E51EC0888848E1F2044B47B66608D8A3B3919B9466E6D60D27565964244B218B48AD83430D996068EC908D9E112096996041D77401A0C0CCF5DEEE561F7F7E68CBE72E48E570B047C772CBACC33753080E32EB0B348C0B62337739B1BC73192392592C84E37B7AC141CFE65EE76D83C9083;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h1C5CF062CA6F13854A59BDEEEA07E3C6559EBB3618111895CBBACCBCD512B5F07D361CCE72B925658DBE1F7C4707E195C5C665B8118C3C31B196C261DA85A5E11889D25CB816ACC6627802052C61A4099B7B0EC923971DB3B9F9204BDBCCFA457EE296E8986E64C6DC99E59436641567648CB84DEB7D7937F974F038D838274F3D3CF1BE8C84DDB000565880A776E5C0E13166E49F47119A4CA1311CF97B965E7CBBCB2CB384BD0D92ED105D0617856E80441124B31DE58B8C001607FEE668899693E3EFF8FBF1FCEEFBCF7CF9BA6C37640DDF7FFE6187B19ACF089D4C038F6607B78D38001FE67E56CCE399DE36D7DDBD699D5CFC5B6D7A1421CE06FE40DB6E;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h0776C62C316FF94B0BC3A0288DE6A62B14D6C1A2DADF9BDF85B2CCB02CE1DB2D96632C3232C3974CDC1172E1779D8C6738251819975DB8146067301E0C0277B6B657485DCD62AC0662C8C005DDE7494C9CA13AAE3234BB0EE1B708A23A2F48AC4C3838641E940620F9CDDCCA14BCC07104C112BCC9032C48E925594CB886A604C9F7627EB100872A52FB5141D65111E6C8DA0ADB6CEC6004461D0E366B20DCCDB607E624499300E4DF6D95CB62F62FB75403E400EFBC3BD34080FC9CDCFCFCFFFFFFFFFFFFFFFFFFFFF7BFFFFFFFFFFFFFFFFFFFFFFFFFFFCF9FFFFFEFFFF81FFDDFFFFFFFFFFFFFF7FFBFFFBFDC0A6DBE6F8BE5BB7FE7A39B3DA3F3BE13B679;
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X22_Y4_N0
|
|
cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a14 (
|
|
.portawe(vcc),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(\z80_|address_pins_|abus[13]~20_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain(1'b0),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\rom|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file = "./rom/gw03.hex";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "rom";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock0";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_a_write_enable_clock = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h4200420000441C443C0C3C00480018FC387C7C000000007E180038300000204880084204004204423E1E3E02247E3C7E3C7E7E7E7E30007E3C7E7E7E3C7E7C3C0400000000000C34023C2E302464003C00000000000000000020460024000000FF991E65536D2D8D9C9B4DB081C83A5A881B0DFDE2D72DF0FA08FCD6F664173D989098D02025E0F6043B4B9080F4923880C3A3B02D269E730C3DCC423386DCB98B4AD0C5C8D6119602E5121008325B7457090E914F4876EC8A18C664210A4C2392C7658400073421047C75FBE7BE73FDFFF05FEE07BF8AEF7F1378B359E8C61F8F692C2218C98A4A8748531986E7C770D984E0000C02060C000C0DF50F68A580;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h0100046606572583002086010800054C0F2DE8371AC0000A9003E024840C7C0806F6612D770080980A40D293FEC069F16CB2164CA033C539F69B37741AEF1CE3662FF5DF9CB107BB23A39EF7B95E7372200448DBDC18F9C0DE0EF379BF49480657781E91788044213E091339886F337D0612CA646CD48FC58EE77EDD7ECEC466C744FD00E1A7F9E9FBFE4777FD50ABD11F0E57FF4808802282200888A20AA88000000008800AC11D556264251ECFA68C056FBCCB040C614A6850222300D2F6FF59F878FCF5689FCFEF34BFD52FA2422A56A3C113409F7813007F8D6B5F80FE9D7FB1E62675F7C2CBE01032DCA16BADC570C1CBF7ECBC4E7E6C54A5D4550BE1A8;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'hE33CB578DEBFAFAEDFD530DE8FA1992072F31B116644B18C72F9F44116C79ADF2F3982C7BE09AD4A32196807648A2495ADF98FD2B16CC096A5E25F5BC811C953CEC3000F432029B3FE3F211712944CA54D1940F193204C199C9F49666CC11B38C23B9D130CA49818913D3A2C1FBF71C5B0C774336F903C677D976189D98CA127AAAD6B6AF36195DA637C6EFA3E36E8FE97FA02EC26EB46198AD8DAD8C11260AF499D7BD86619EE5574CD27C80D39F71E653FDCF1B366737233CBB98D1E7B330F7DCCFC5939C4EC79CF0E1CD43BA7AFC716900A21BDB9DD0FCC7ECE1063238407C7E1B221EA10E38F64EF31CEBF3368E1C712BB1B33781134CFE54C2123349A6E;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h5F9CB25A3631964C20007FF5754FC631A97D4F93986C30CF24394625658DE9A7C228A2050470925E29A35D8D06242712CD25C9241898204D85A710947C802013E1265727652C8F0C422BA8C28A0FBB893B0881E00403DDD8843B2D8EB929D0D8CB76E03779E019E2C4E4028219C38C202C9384E0D24E569C2E4D4D60B670CE37414D536A41D144B6C4624A2B00366D8CF6734A4A2DC465B308462CCBD1BF9CB863FC93EDB2CA5DC61B01639318985C88F01680E307C42311C0124700B28BF9B4FF7CCCEFE1996DE3ED6D8CFBF1871BD98EE7646242664EB2E338BD009838637124C921BB3332DC66D9C1706B6C48C3129639A3BA4088EDB496EDBBBFC2CC40B6;
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X22_Y23_N0
|
|
cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a14 (
|
|
.portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\CLOCK_50~inputclkctrl_outclk ),
|
|
.clk1(\CLOCK_50~inputclkctrl_outclk ),
|
|
.ena0(\z80_|address_pins_|abus[13]~20_combout ),
|
|
.ena1(gnd),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[6]~79_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain({\~GND~combout }),
|
|
.portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4],
|
|
\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a14_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk0_core_clock_enable = "ena0";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .clk1_core_clock_enable = "ena1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .data_interleave_width_in_bits = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file = "ula/test_scr.hex";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .init_file_layout = "port_a";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mixed_port_feed_through_mode = "dont_care";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .operation_mode = "bidir_dual_port";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_address_width = 13;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_byte_enable_clock = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_out_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_data_width = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_address = 0;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_first_bit_number = 6;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_last_address = 8191;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_depth = 16384;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_logical_ram_width = 8;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_address_width = 13;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_in_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_out_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_data_width = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_address = 0;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_first_bit_number = 6;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_last_address = 8191;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_depth = 16384;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_logical_ram_width = 8;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_read_enable_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .port_b_write_enable_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .ram_block_type = "M9K";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a14 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X22_Y26_N0
|
|
cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a6 (
|
|
.portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\CLOCK_50~inputclkctrl_outclk ),
|
|
.clk1(\CLOCK_50~inputclkctrl_outclk ),
|
|
.ena0(!\z80_|address_pins_|abus[13]~20_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[6]~79_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain({\~GND~combout }),
|
|
.portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4],
|
|
\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTADATAOUT_bus ),
|
|
.portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a6_PORTBDATAOUT_bus ));
|
|
// synopsys translate_off
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .clk0_core_clock_enable = "ena0";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .data_interleave_width_in_bits = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file = "ula/test_scr.hex";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .init_file_layout = "port_a";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mixed_port_feed_through_mode = "dont_care";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .operation_mode = "bidir_dual_port";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_address_width = 13;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_byte_enable_clock = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_out_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_data_width = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_address = 0;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_first_bit_number = 6;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_last_address = 8191;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_depth = 16384;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_logical_ram_width = 8;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_address_width = 13;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_in_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_out_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_data_width = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_address = 0;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_first_bit_number = 6;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_last_address = 8191;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_depth = 16384;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_logical_ram_width = 8;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_read_enable_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .port_b_write_enable_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .ram_block_type = "M9K";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFEBFFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFFFFDFFFFFFFFFFFFFBFFFFFFFFFEFFFFFFFDFFFFFFFFFFFFFEFFFFFFFDF8FFFFFFF9FFFFFFFFFFFFFFFF3FFFFFFE7FFFFFFFFFFFFFFFF;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000380001887600094C977486989000000000000000000000000FFFFFFFFC0810205C00018C36DC09CF97749EDCD00000000000000000000000000000001FFFFFFFDC004000B6D028BF17749ED8100000000000000000000000000000001BF7EFDF9400404A96D8289B57549FFC10000000000000000000000003F7EFDF90000000140041EB16D8298357DC9F7410000000000000000000000007FFFFFFD8000000340043AB160021E757DC9134100000000000000000000000040810207BFFFFFFF5FE430497702760D60099349000000000000000000000000408102073FFFFFFD5FE40E49774240C96009735D;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init1 = 2048'h5FE8334948F827C15FF88F8169A80ECB609EAD417A698FC178F33E8171F72A915FE836E948F807C95FF88F81E9A80FC7639E1FC17B2BBEC170730F8D70F7B0C1400826E548B807C95FF88F95E8280FCB63C6BCC17B3B3FC171AB3E81708734C1400826ED58F8258159F88B8168280FC161629DC17A3B3F41738B3F8150AF16E9400826ED581805C151D88A8160682FC1422297C17A2A39C162FB378550CF10A1400826ED58182581D1580B8761EC2FC14232B7C179AA39C5627B7781D0CF10D3400826E158182D81F0488A4B61EC0DC143789FC17BBB39C1610B7F81D45F11D34008A7E958080D01F0088A4160B42DD143689FC17B9B398561837F81D41702B1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a6 .mem_init0 = 2048'h50DF086350368F0151C688016801460157EDE81148F310013FFFFFFF40810103D2D70D4B50168F0141D6C8116C01462153EDA90148F31D01BFFFFFFF40810107D2D7296354D68501403EC0016C01482173FDA08148F11F01800000037FFFFFFD4297893154DE81054022D2116C014D6153FCA00148D10F01000000013F7EFEF9429F810150CEC10143E042016C014C09537DA00148D11F01BF7EFEF900000001469F833150168D0543E04A116F014DA15379B181C8511F03FFFFFFFD00000001449AAB2155368D01482046016F416CA15079B001C8513E03C0810105FFFFFFFF403A8B0155C685014800461167476CA15039B08180413E0500000007FFFFFFFF;
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y10_N16
|
|
cycloneive_lcell_comb \Selector6~0 (
|
|
// Equation(s):
|
|
// \Selector6~0_combout = (\z80_|address_pins_|abus[14]~23_combout & ((\Selector3~0_combout & (\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout )) # (!\Selector3~0_combout &
|
|
// ((\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ))))) # (!\z80_|address_pins_|abus[14]~23_combout & (\Selector3~0_combout ))
|
|
|
|
.dataa(\z80_|address_pins_|abus[14]~23_combout ),
|
|
.datab(\Selector3~0_combout ),
|
|
.datac(\ram0|altsyncram_component|auto_generated|ram_block1a14~portadataout ),
|
|
.datad(\ram0|altsyncram_component|auto_generated|ram_block1a6~portadataout ),
|
|
.cin(gnd),
|
|
.combout(\Selector6~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \Selector6~0 .lut_mask = 16'hE6C4;
|
|
defparam \Selector6~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y10_N18
|
|
cycloneive_lcell_comb \Selector6~1 (
|
|
// Equation(s):
|
|
// \Selector6~1_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\Selector6~0_combout )))) # (!\z80_|address_pins_|abus[14]~23_combout & ((\Selector6~0_combout & ((\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ))) #
|
|
// (!\Selector6~0_combout & (\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ))))
|
|
|
|
.dataa(\rom|altsyncram_component|auto_generated|ram_block1a6~portadataout ),
|
|
.datab(\z80_|address_pins_|abus[14]~23_combout ),
|
|
.datac(\rom|altsyncram_component|auto_generated|ram_block1a14~portadataout ),
|
|
.datad(\Selector6~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\Selector6~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \Selector6~1 .lut_mask = 16'hFC22;
|
|
defparam \Selector6~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y10_N4
|
|
cycloneive_lcell_comb \D[6]~88 (
|
|
// Equation(s):
|
|
// \D[6]~88_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\Selector6~1_combout
|
|
// ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout ))))
|
|
|
|
.dataa(\z80_|address_pins_|DFFE_apin_latch [15]),
|
|
.datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[6]~13_combout ),
|
|
.datad(\Selector6~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[6]~88_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[6]~88 .lut_mask = 16'hF4B0;
|
|
defparam \D[6]~88 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOIBUF_X16_Y34_N8
|
|
cycloneive_io_ibuf \raw_loader_in~input (
|
|
.i(raw_loader_in),
|
|
.ibar(gnd),
|
|
.o(\raw_loader_in~input_o ));
|
|
// synopsys translate_off
|
|
defparam \raw_loader_in~input .bus_hold = "false";
|
|
defparam \raw_loader_in~input .simulate_z_as = "z";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y10_N24
|
|
cycloneive_lcell_comb \D[6]~69 (
|
|
// Equation(s):
|
|
// \D[6]~69_combout = ((\z80_|address_pins_|DFFE_apin_latch [0]) # (\raw_loader_in~input_o )) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.datac(\z80_|address_pins_|DFFE_apin_latch [0]),
|
|
.datad(\raw_loader_in~input_o ),
|
|
.cin(gnd),
|
|
.combout(\D[6]~69_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[6]~69 .lut_mask = 16'hFFF3;
|
|
defparam \D[6]~69 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y10_N0
|
|
cycloneive_lcell_comb \D[6]~78 (
|
|
// Equation(s):
|
|
// \D[6]~78_combout = ((\Equal2~0_combout & ((\D[6]~69_combout ))) # (!\Equal2~0_combout & (\D[6]~88_combout ))) # (!\Equal2~1_combout )
|
|
|
|
.dataa(\Equal2~0_combout ),
|
|
.datab(\Equal2~1_combout ),
|
|
.datac(\D[6]~88_combout ),
|
|
.datad(\D[6]~69_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[6]~78_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[6]~78 .lut_mask = 16'hFB73;
|
|
defparam \D[6]~78 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y10_N6
|
|
cycloneive_lcell_comb \D[6]~79 (
|
|
// Equation(s):
|
|
// \D[6]~79_combout = (\z80_|pin_control_|bus_db_pin_oe~15_combout & (\z80_|data_pins_|dout [6] & ((\D[6]~78_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\D[6]~78_combout ) # (!\Equal2~1_combout ))))
|
|
|
|
.dataa(\z80_|data_pins_|dout [6]),
|
|
.datab(\Equal2~1_combout ),
|
|
.datac(\z80_|pin_control_|bus_db_pin_oe~15_combout ),
|
|
.datad(\D[6]~78_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[6]~79_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[6]~79 .lut_mask = 16'hAF03;
|
|
defparam \D[6]~79 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y13_N18
|
|
cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] (
|
|
// Equation(s):
|
|
// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [6] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[6]~9_combout ) # ((\z80_|pin_control_|bus_db_pin_re~combout & \D[6]~79_combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout &
|
|
// (\z80_|pin_control_|bus_db_pin_re~combout & (\D[6]~79_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_bus_db_we~7_combout ),
|
|
.datab(\z80_|pin_control_|bus_db_pin_re~combout ),
|
|
.datac(\D[6]~79_combout ),
|
|
.datad(\z80_|bus_control_|db[6]~9_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .lut_mask = 16'hEAC0;
|
|
defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[6] .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X30_Y13_N19
|
|
dffeas \z80_|data_pins_|dout[6] (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [6]),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|data_pins_|dout [6]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|data_pins_|dout[6] .is_wysiwyg = "true";
|
|
defparam \z80_|data_pins_|dout[6] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y13_N6
|
|
cycloneive_lcell_comb \z80_|bus_control_|db[6]~9 (
|
|
// Equation(s):
|
|
// \z80_|bus_control_|db[6]~9_combout = ((\z80_|bus_control_|db[6]~8_combout & ((\z80_|data_pins_|dout [6]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout )
|
|
|
|
.dataa(\z80_|bus_control_|db[0]~6_combout ),
|
|
.datab(\z80_|bus_control_|db[6]~8_combout ),
|
|
.datac(\z80_|data_pins_|dout [6]),
|
|
.datad(\z80_|execute_|ctl_bus_db_oe~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|bus_control_|db[6]~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|bus_control_|db[6]~9 .lut_mask = 16'hD5DD;
|
|
defparam \z80_|bus_control_|db[6]~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X30_Y13_N7
|
|
dffeas \z80_|ir_|opcode[6] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|bus_control_|db[6]~9_combout ),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|execute_|ctl_ir_we~13_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|ir_|opcode [6]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|ir_|opcode[6] .is_wysiwyg = "true";
|
|
defparam \z80_|ir_|opcode[6] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y17_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_ir_we~10 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_ir_we~10_combout = (!\z80_|ir_|opcode [6] & (\z80_|ir_|opcode [7] & (\z80_|execute_|ctl_ir_we~5_combout & !\z80_|pla_decode_|Equal46~0_combout )))
|
|
|
|
.dataa(\z80_|ir_|opcode [6]),
|
|
.datab(\z80_|ir_|opcode [7]),
|
|
.datac(\z80_|execute_|ctl_ir_we~5_combout ),
|
|
.datad(\z80_|pla_decode_|Equal46~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_ir_we~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_ir_we~10 .lut_mask = 16'h0040;
|
|
defparam \z80_|execute_|ctl_ir_we~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y19_N8
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~0 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_bus_db_oe~0_combout = (\z80_|execute_|ctl_alu_bs_oe~6_combout & (((!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~7_combout )) # (!\z80_|execute_|ctl_ir_we~4_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_ir_we~10_combout ),
|
|
.datab(\z80_|execute_|ctl_ir_we~7_combout ),
|
|
.datac(\z80_|execute_|ctl_alu_bs_oe~6_combout ),
|
|
.datad(\z80_|execute_|ctl_ir_we~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_bus_db_oe~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_bus_db_oe~0 .lut_mask = 16'h10F0;
|
|
defparam \z80_|execute_|ctl_bus_db_oe~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y13_N10
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~4 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_bus_db_oe~4_combout = (!\z80_|execute_|ctl_bus_db_oe~3_combout ) # (!\z80_|execute_|ctl_bus_db_oe~0_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_bus_db_oe~0_combout ),
|
|
.datad(\z80_|execute_|ctl_bus_db_oe~3_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_bus_db_oe~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_bus_db_oe~4 .lut_mask = 16'h0FFF;
|
|
defparam \z80_|execute_|ctl_bus_db_oe~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y13_N12
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~2 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_bus_db_oe~2_combout = (!\z80_|execute_|ctl_bus_ff_oe~1_combout & (!\z80_|execute_|ctl_bus_zero_oe~0_combout & ((\z80_|resets_|SYNTHESIZED_WIRE_11~combout ) # (!\z80_|decode_state_|in_halt~q ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_bus_ff_oe~1_combout ),
|
|
.datab(\z80_|execute_|ctl_bus_zero_oe~0_combout ),
|
|
.datac(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ),
|
|
.datad(\z80_|decode_state_|in_halt~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_bus_db_oe~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_bus_db_oe~2 .lut_mask = 16'h1011;
|
|
defparam \z80_|execute_|ctl_bus_db_oe~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y17_N2
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~5 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_bus_db_oe~5_combout = (\z80_|execute_|ctl_ir_we~8_combout ) # ((\z80_|pla_decode_|Equal41~2_combout ) # ((\z80_|execute_|ctl_ir_we~14_combout ) # (\z80_|execute_|ctl_ir_we~11_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_ir_we~8_combout ),
|
|
.datab(\z80_|pla_decode_|Equal41~2_combout ),
|
|
.datac(\z80_|execute_|ctl_ir_we~14_combout ),
|
|
.datad(\z80_|execute_|ctl_ir_we~11_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_bus_db_oe~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_bus_db_oe~5 .lut_mask = 16'hFFFE;
|
|
defparam \z80_|execute_|ctl_bus_db_oe~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y17_N4
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe~6 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_bus_db_oe~6_combout = ((\z80_|execute_|ctl_66_oe~2_combout ) # ((\z80_|execute_|ctl_bus_db_oe~5_combout & \z80_|execute_|ctl_ir_we~4_combout ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_11~combout )
|
|
|
|
.dataa(\z80_|resets_|SYNTHESIZED_WIRE_11~combout ),
|
|
.datab(\z80_|execute_|ctl_bus_db_oe~5_combout ),
|
|
.datac(\z80_|execute_|ctl_ir_we~4_combout ),
|
|
.datad(\z80_|execute_|ctl_66_oe~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_bus_db_oe~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_bus_db_oe~6 .lut_mask = 16'hFFD5;
|
|
defparam \z80_|execute_|ctl_bus_db_oe~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y13_N16
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_bus_db_oe (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_bus_db_oe~combout = (\z80_|execute_|ctl_bus_db_oe~2_combout & ((\z80_|execute_|ctl_bus_db_oe~4_combout ) # ((\z80_|execute_|ctl_bus_db_oe~6_combout ) # (!\z80_|execute_|ctl_sw_1d~6_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_bus_db_oe~4_combout ),
|
|
.datab(\z80_|execute_|ctl_bus_db_oe~2_combout ),
|
|
.datac(\z80_|execute_|ctl_sw_1d~6_combout ),
|
|
.datad(\z80_|execute_|ctl_bus_db_oe~6_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_bus_db_oe~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_bus_db_oe .lut_mask = 16'hCC8C;
|
|
defparam \z80_|execute_|ctl_bus_db_oe .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y13_N14
|
|
cycloneive_lcell_comb \z80_|bus_control_|db[0]~6 (
|
|
// Equation(s):
|
|
// \z80_|bus_control_|db[0]~6_combout = (\z80_|execute_|ctl_bus_db_oe~combout ) # ((\z80_|execute_|ctl_bus_db_we~7_combout ) # (!\z80_|execute_|ctl_bus_db_oe~2_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_bus_db_oe~combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_bus_db_we~7_combout ),
|
|
.datad(\z80_|execute_|ctl_bus_db_oe~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|bus_control_|db[0]~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|bus_control_|db[0]~6 .lut_mask = 16'hFAFF;
|
|
defparam \z80_|bus_control_|db[0]~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y9_N24
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~61 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[7][2]~61_combout = (\ula_|zx_keyboard_|keys[7][2]~60_combout & (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [1])))
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[7][2]~60_combout ),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [0]),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [4]),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [1]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[7][2]~61_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[7][2]~61 .lut_mask = 16'h2000;
|
|
defparam \ula_|zx_keyboard_|keys[7][2]~61 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y9_N6
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~63 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[7][2]~63_combout = (\ula_|ps2_keyboard_|shiftreg [3] & ((\ula_|zx_keyboard_|keys[7][2]~61_combout ) # ((\ula_|zx_keyboard_|keys[5][4]~62_combout & \ula_|zx_keyboard_|keys[7][2]~30_combout ))))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [3]),
|
|
.datab(\ula_|zx_keyboard_|keys[7][2]~61_combout ),
|
|
.datac(\ula_|zx_keyboard_|keys[5][4]~62_combout ),
|
|
.datad(\ula_|zx_keyboard_|keys[7][2]~30_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[7][2]~63_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[7][2]~63 .lut_mask = 16'hA888;
|
|
defparam \ula_|zx_keyboard_|keys[7][2]~63 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y9_N28
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~64 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[7][2]~64_combout = (\ula_|zx_keyboard_|keys[0][0]~13_combout & (!\ula_|ps2_keyboard_|shiftreg [2] & (\ula_|zx_keyboard_|keys[7][2]~63_combout & !\ula_|zx_keyboard_|extended~q )))
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[0][0]~13_combout ),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [2]),
|
|
.datac(\ula_|zx_keyboard_|keys[7][2]~63_combout ),
|
|
.datad(\ula_|zx_keyboard_|extended~q ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[7][2]~64_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[7][2]~64 .lut_mask = 16'h0020;
|
|
defparam \ula_|zx_keyboard_|keys[7][2]~64 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y9_N4
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[7][2]~65 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[7][2]~65_combout = (\ula_|zx_keyboard_|keys[7][2]~64_combout & (!\ula_|zx_keyboard_|Selector13~0_combout )) # (!\ula_|zx_keyboard_|keys[7][2]~64_combout & ((\ula_|zx_keyboard_|keys[7][2]~q )))
|
|
|
|
.dataa(\ula_|zx_keyboard_|Selector13~0_combout ),
|
|
.datab(gnd),
|
|
.datac(\ula_|zx_keyboard_|keys[7][2]~q ),
|
|
.datad(\ula_|zx_keyboard_|keys[7][2]~64_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[7][2]~65_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[7][2]~65 .lut_mask = 16'h55F0;
|
|
defparam \ula_|zx_keyboard_|keys[7][2]~65 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X29_Y9_N5
|
|
dffeas \ula_|zx_keyboard_|keys[7][2] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|zx_keyboard_|keys[7][2]~65_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|zx_keyboard_|keys[7][2]~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[7][2] .is_wysiwyg = "true";
|
|
defparam \ula_|zx_keyboard_|keys[7][2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y8_N2
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~67 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[6][2]~67_combout = (\ula_|ps2_keyboard_|shiftreg [0] & (!\ula_|ps2_keyboard_|shiftreg [1] & \ula_|ps2_keyboard_|shiftreg [4])) # (!\ula_|ps2_keyboard_|shiftreg [0] & (\ula_|ps2_keyboard_|shiftreg [1] &
|
|
// !\ula_|ps2_keyboard_|shiftreg [4]))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [0]),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [1]),
|
|
.datac(gnd),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [4]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[6][2]~67_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[6][2]~67 .lut_mask = 16'h2244;
|
|
defparam \ula_|zx_keyboard_|keys[6][2]~67 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y8_N6
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~68 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[6][2]~68_combout = (!\ula_|ps2_keyboard_|shiftreg [3] & (\ula_|zx_keyboard_|keys[6][2]~67_combout & (\ula_|ps2_keyboard_|shiftreg [4] $ (!\ula_|ps2_keyboard_|shiftreg [2]))))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [4]),
|
|
.datab(\ula_|ps2_keyboard_|shiftreg [3]),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [2]),
|
|
.datad(\ula_|zx_keyboard_|keys[6][2]~67_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[6][2]~68_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[6][2]~68 .lut_mask = 16'h2100;
|
|
defparam \ula_|zx_keyboard_|keys[6][2]~68 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y8_N10
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[6][2]~69 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[6][2]~69_combout = (\ula_|zx_keyboard_|keys[6][1]~39_combout & ((\ula_|zx_keyboard_|keys[6][2]~68_combout & (!\ula_|zx_keyboard_|keys[5][0]~66_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~68_combout &
|
|
// ((\ula_|zx_keyboard_|keys[6][2]~q ))))) # (!\ula_|zx_keyboard_|keys[6][1]~39_combout & (((\ula_|zx_keyboard_|keys[6][2]~q ))))
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[5][0]~66_combout ),
|
|
.datab(\ula_|zx_keyboard_|keys[6][1]~39_combout ),
|
|
.datac(\ula_|zx_keyboard_|keys[6][2]~q ),
|
|
.datad(\ula_|zx_keyboard_|keys[6][2]~68_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[6][2]~69_combout ),
|
|
.cout());
|
|
// synopsys translate_off
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|
defparam \ula_|zx_keyboard_|keys[6][2]~69 .lut_mask = 16'h74F0;
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|
defparam \ula_|zx_keyboard_|keys[6][2]~69 .sum_lutc_input = "datac";
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|
// synopsys translate_on
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|
|
|
// Location: FF_X29_Y8_N11
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|
dffeas \ula_|zx_keyboard_|keys[6][2] (
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|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
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|
.d(\ula_|zx_keyboard_|keys[6][2]~69_combout ),
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|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|zx_keyboard_|keys[6][2]~q ),
|
|
.prn(vcc));
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|
// synopsys translate_off
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|
defparam \ula_|zx_keyboard_|keys[6][2] .is_wysiwyg = "true";
|
|
defparam \ula_|zx_keyboard_|keys[6][2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y8_N12
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|
cycloneive_lcell_comb \D[2]~36 (
|
|
// Equation(s):
|
|
// \D[2]~36_combout = (\ula_|zx_keyboard_|keys[7][2]~q & (\z80_|address_pins_|abus[15]~22_combout & ((\z80_|address_pins_|abus[14]~23_combout ) # (!\ula_|zx_keyboard_|keys[6][2]~q )))) # (!\ula_|zx_keyboard_|keys[7][2]~q &
|
|
// (((\z80_|address_pins_|abus[14]~23_combout )) # (!\ula_|zx_keyboard_|keys[6][2]~q )))
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|
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.dataa(\ula_|zx_keyboard_|keys[7][2]~q ),
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|
.datab(\ula_|zx_keyboard_|keys[6][2]~q ),
|
|
.datac(\z80_|address_pins_|abus[14]~23_combout ),
|
|
.datad(\z80_|address_pins_|abus[15]~22_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[2]~36_combout ),
|
|
.cout());
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|
// synopsys translate_off
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|
defparam \D[2]~36 .lut_mask = 16'hF351;
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|
defparam \D[2]~36 .sum_lutc_input = "datac";
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|
// synopsys translate_on
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|
|
|
// Location: LCCOMB_X29_Y8_N26
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|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~58 (
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|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[4][2]~58_combout = (\ula_|ps2_keyboard_|shiftreg [6] & (\ula_|zx_keyboard_|extended~q & (!\ula_|ps2_keyboard_|shiftreg [3] & !\ula_|ps2_keyboard_|shiftreg [1]))) # (!\ula_|ps2_keyboard_|shiftreg [6] &
|
|
// (!\ula_|zx_keyboard_|extended~q & (\ula_|ps2_keyboard_|shiftreg [3] & \ula_|ps2_keyboard_|shiftreg [1])))
|
|
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|
.dataa(\ula_|ps2_keyboard_|shiftreg [6]),
|
|
.datab(\ula_|zx_keyboard_|extended~q ),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [3]),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [1]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[4][2]~58_combout ),
|
|
.cout());
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|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[4][2]~58 .lut_mask = 16'h1008;
|
|
defparam \ula_|zx_keyboard_|keys[4][2]~58 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y8_N14
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|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~130 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[4][2]~130_combout = (\ula_|ps2_keyboard_|shiftreg [4] & (\ula_|zx_keyboard_|keys[4][2]~58_combout & (\ula_|ps2_keyboard_|shiftreg [2] & !\ula_|ps2_keyboard_|shiftreg [0])))
|
|
|
|
.dataa(\ula_|ps2_keyboard_|shiftreg [4]),
|
|
.datab(\ula_|zx_keyboard_|keys[4][2]~58_combout ),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [2]),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [0]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[4][2]~130_combout ),
|
|
.cout());
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|
// synopsys translate_off
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|
defparam \ula_|zx_keyboard_|keys[4][2]~130 .lut_mask = 16'h0080;
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|
defparam \ula_|zx_keyboard_|keys[4][2]~130 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y8_N24
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[4][2]~59 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[4][2]~59_combout = (\ula_|zx_keyboard_|keys[3][4]~129_combout & ((\ula_|zx_keyboard_|keys[4][2]~130_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[4][2]~130_combout & ((\ula_|zx_keyboard_|keys[4][2]~q
|
|
// ))))) # (!\ula_|zx_keyboard_|keys[3][4]~129_combout & (((\ula_|zx_keyboard_|keys[4][2]~q ))))
|
|
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|
.dataa(\ula_|zx_keyboard_|released~q ),
|
|
.datab(\ula_|zx_keyboard_|keys[3][4]~129_combout ),
|
|
.datac(\ula_|zx_keyboard_|keys[4][2]~q ),
|
|
.datad(\ula_|zx_keyboard_|keys[4][2]~130_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[4][2]~59_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[4][2]~59 .lut_mask = 16'h74F0;
|
|
defparam \ula_|zx_keyboard_|keys[4][2]~59 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X29_Y8_N25
|
|
dffeas \ula_|zx_keyboard_|keys[4][2] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
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|
.d(\ula_|zx_keyboard_|keys[4][2]~59_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|zx_keyboard_|keys[4][2]~q ),
|
|
.prn(vcc));
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|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[4][2] .is_wysiwyg = "true";
|
|
defparam \ula_|zx_keyboard_|keys[4][2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y10_N26
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~56 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[5][2]~56_combout = (\ula_|ps2_keyboard_|shiftreg [0] & !\ula_|ps2_keyboard_|shiftreg [2])
|
|
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|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [0]),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [2]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[5][2]~56_combout ),
|
|
.cout());
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|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[5][2]~56 .lut_mask = 16'h00F0;
|
|
defparam \ula_|zx_keyboard_|keys[5][2]~56 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y10_N18
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[5][2]~57 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[5][2]~57_combout = (\ula_|zx_keyboard_|keys[5][2]~56_combout & ((\ula_|zx_keyboard_|keys[5][2]~31_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[5][2]~31_combout & ((\ula_|zx_keyboard_|keys[5][2]~q
|
|
// ))))) # (!\ula_|zx_keyboard_|keys[5][2]~56_combout & (((\ula_|zx_keyboard_|keys[5][2]~q ))))
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[5][2]~56_combout ),
|
|
.datab(\ula_|zx_keyboard_|released~q ),
|
|
.datac(\ula_|zx_keyboard_|keys[5][2]~q ),
|
|
.datad(\ula_|zx_keyboard_|keys[5][2]~31_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[5][2]~57_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[5][2]~57 .lut_mask = 16'h72F0;
|
|
defparam \ula_|zx_keyboard_|keys[5][2]~57 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X29_Y10_N19
|
|
dffeas \ula_|zx_keyboard_|keys[5][2] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|zx_keyboard_|keys[5][2]~57_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|zx_keyboard_|keys[5][2]~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[5][2] .is_wysiwyg = "true";
|
|
defparam \ula_|zx_keyboard_|keys[5][2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y8_N24
|
|
cycloneive_lcell_comb \D[2]~35 (
|
|
// Equation(s):
|
|
// \D[2]~35_combout = (\z80_|address_pins_|abus[13]~20_combout & (((\z80_|address_pins_|abus[12]~21_combout )) # (!\ula_|zx_keyboard_|keys[4][2]~q ))) # (!\z80_|address_pins_|abus[13]~20_combout & (!\ula_|zx_keyboard_|keys[5][2]~q &
|
|
// ((\z80_|address_pins_|abus[12]~21_combout ) # (!\ula_|zx_keyboard_|keys[4][2]~q ))))
|
|
|
|
.dataa(\z80_|address_pins_|abus[13]~20_combout ),
|
|
.datab(\ula_|zx_keyboard_|keys[4][2]~q ),
|
|
.datac(\z80_|address_pins_|abus[12]~21_combout ),
|
|
.datad(\ula_|zx_keyboard_|keys[5][2]~q ),
|
|
.cin(gnd),
|
|
.combout(\D[2]~35_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[2]~35 .lut_mask = 16'hA2F3;
|
|
defparam \D[2]~35 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y7_N10
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~54 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[0][2]~54_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & !\ula_|ps2_keyboard_|shiftreg [2])
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [4]),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [2]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[0][2]~54_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[0][2]~54 .lut_mask = 16'h000F;
|
|
defparam \ula_|zx_keyboard_|keys[0][2]~54 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y7_N18
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[0][2]~55 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[0][2]~55_combout = (\ula_|zx_keyboard_|keys[7][4]~49_combout & ((\ula_|zx_keyboard_|keys[0][2]~54_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[0][2]~54_combout & ((\ula_|zx_keyboard_|keys[0][2]~q
|
|
// ))))) # (!\ula_|zx_keyboard_|keys[7][4]~49_combout & (((\ula_|zx_keyboard_|keys[0][2]~q ))))
|
|
|
|
.dataa(\ula_|zx_keyboard_|released~q ),
|
|
.datab(\ula_|zx_keyboard_|keys[7][4]~49_combout ),
|
|
.datac(\ula_|zx_keyboard_|keys[0][2]~q ),
|
|
.datad(\ula_|zx_keyboard_|keys[0][2]~54_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[0][2]~55_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[0][2]~55 .lut_mask = 16'h74F0;
|
|
defparam \ula_|zx_keyboard_|keys[0][2]~55 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X27_Y7_N19
|
|
dffeas \ula_|zx_keyboard_|keys[0][2] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|zx_keyboard_|keys[0][2]~55_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|zx_keyboard_|keys[0][2]~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[0][2] .is_wysiwyg = "true";
|
|
defparam \ula_|zx_keyboard_|keys[0][2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y7_N26
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~50 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[3][2]~50_combout = (!\ula_|ps2_keyboard_|shiftreg [4] & \ula_|ps2_keyboard_|shiftreg [2])
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [4]),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [2]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[3][2]~50_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[3][2]~50 .lut_mask = 16'h0F00;
|
|
defparam \ula_|zx_keyboard_|keys[3][2]~50 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y7_N14
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[3][2]~51 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[3][2]~51_combout = (\ula_|zx_keyboard_|keys[3][2]~50_combout & ((\ula_|zx_keyboard_|keys[7][4]~49_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[7][4]~49_combout & (\ula_|zx_keyboard_|keys[3][2]~q
|
|
// )))) # (!\ula_|zx_keyboard_|keys[3][2]~50_combout & (((\ula_|zx_keyboard_|keys[3][2]~q ))))
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[3][2]~50_combout ),
|
|
.datab(\ula_|zx_keyboard_|keys[7][4]~49_combout ),
|
|
.datac(\ula_|zx_keyboard_|keys[3][2]~q ),
|
|
.datad(\ula_|zx_keyboard_|released~q ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[3][2]~51_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[3][2]~51 .lut_mask = 16'h70F8;
|
|
defparam \ula_|zx_keyboard_|keys[3][2]~51 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X27_Y7_N15
|
|
dffeas \ula_|zx_keyboard_|keys[3][2] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|zx_keyboard_|keys[3][2]~51_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|zx_keyboard_|keys[3][2]~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[3][2] .is_wysiwyg = "true";
|
|
defparam \ula_|zx_keyboard_|keys[3][2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y7_N12
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~52 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[2][2]~52_combout = (\ula_|zx_keyboard_|Equal0~2_combout & (\ula_|zx_keyboard_|keys[7][4]~17_combout & (\ula_|zx_keyboard_|keys[3][2]~50_combout & !\ula_|ps2_keyboard_|shiftreg [1])))
|
|
|
|
.dataa(\ula_|zx_keyboard_|Equal0~2_combout ),
|
|
.datab(\ula_|zx_keyboard_|keys[7][4]~17_combout ),
|
|
.datac(\ula_|zx_keyboard_|keys[3][2]~50_combout ),
|
|
.datad(\ula_|ps2_keyboard_|shiftreg [1]),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[2][2]~52_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[2][2]~52 .lut_mask = 16'h0080;
|
|
defparam \ula_|zx_keyboard_|keys[2][2]~52 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y7_N24
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[2][2]~53 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[2][2]~53_combout = (\ula_|zx_keyboard_|keys[2][2]~52_combout & (!\ula_|zx_keyboard_|released~q )) # (!\ula_|zx_keyboard_|keys[2][2]~52_combout & ((\ula_|zx_keyboard_|keys[2][2]~q )))
|
|
|
|
.dataa(\ula_|zx_keyboard_|released~q ),
|
|
.datab(gnd),
|
|
.datac(\ula_|zx_keyboard_|keys[2][2]~q ),
|
|
.datad(\ula_|zx_keyboard_|keys[2][2]~52_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[2][2]~53_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[2][2]~53 .lut_mask = 16'h55F0;
|
|
defparam \ula_|zx_keyboard_|keys[2][2]~53 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X27_Y7_N25
|
|
dffeas \ula_|zx_keyboard_|keys[2][2] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|zx_keyboard_|keys[2][2]~53_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|zx_keyboard_|keys[2][2]~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[2][2] .is_wysiwyg = "true";
|
|
defparam \ula_|zx_keyboard_|keys[2][2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X28_Y7_N8
|
|
cycloneive_lcell_comb \D[2]~33 (
|
|
// Equation(s):
|
|
// \D[2]~33_combout = (\ula_|zx_keyboard_|keys[3][2]~q & (\z80_|address_pins_|abus[11]~19_combout & ((\z80_|address_pins_|abus[10]~24_combout ) # (!\ula_|zx_keyboard_|keys[2][2]~q )))) # (!\ula_|zx_keyboard_|keys[3][2]~q &
|
|
// (((\z80_|address_pins_|abus[10]~24_combout )) # (!\ula_|zx_keyboard_|keys[2][2]~q )))
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[3][2]~q ),
|
|
.datab(\ula_|zx_keyboard_|keys[2][2]~q ),
|
|
.datac(\z80_|address_pins_|abus[11]~19_combout ),
|
|
.datad(\z80_|address_pins_|abus[10]~24_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[2]~33_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[2]~33 .lut_mask = 16'hF531;
|
|
defparam \D[2]~33 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y7_N20
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~47 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[1][2]~47_combout = (\ula_|zx_keyboard_|keys[6][4]~45_combout & (\ula_|zx_keyboard_|keys[6][4]~46_combout & !\ula_|ps2_keyboard_|shiftreg [4]))
|
|
|
|
.dataa(\ula_|zx_keyboard_|keys[6][4]~45_combout ),
|
|
.datab(\ula_|zx_keyboard_|keys[6][4]~46_combout ),
|
|
.datac(\ula_|ps2_keyboard_|shiftreg [4]),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[1][2]~47_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[1][2]~47 .lut_mask = 16'h0808;
|
|
defparam \ula_|zx_keyboard_|keys[1][2]~47 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y7_N6
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|keys[1][2]~48 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|keys[1][2]~48_combout = (\ula_|zx_keyboard_|keys[1][2]~47_combout & ((!\ula_|zx_keyboard_|released~q ))) # (!\ula_|zx_keyboard_|keys[1][2]~47_combout & (\ula_|zx_keyboard_|keys[1][2]~q ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|zx_keyboard_|keys[1][2]~47_combout ),
|
|
.datac(\ula_|zx_keyboard_|keys[1][2]~q ),
|
|
.datad(\ula_|zx_keyboard_|released~q ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|keys[1][2]~48_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[1][2]~48 .lut_mask = 16'h30FC;
|
|
defparam \ula_|zx_keyboard_|keys[1][2]~48 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X27_Y7_N7
|
|
dffeas \ula_|zx_keyboard_|keys[1][2] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|zx_keyboard_|keys[1][2]~48_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|zx_keyboard_|keys[1][2]~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|keys[1][2] .is_wysiwyg = "true";
|
|
defparam \ula_|zx_keyboard_|keys[1][2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y7_N28
|
|
cycloneive_lcell_comb \ula_|zx_keyboard_|key_row~1 (
|
|
// Equation(s):
|
|
// \ula_|zx_keyboard_|key_row~1_combout = (\z80_|address_pins_|DFFE_apin_latch [9]) # ((!\ula_|zx_keyboard_|keys[1][2]~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|address_pins_|DFFE_apin_latch [9]),
|
|
.datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.datad(\ula_|zx_keyboard_|keys[1][2]~q ),
|
|
.cin(gnd),
|
|
.combout(\ula_|zx_keyboard_|key_row~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|zx_keyboard_|key_row~1 .lut_mask = 16'hCFFF;
|
|
defparam \ula_|zx_keyboard_|key_row~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y7_N4
|
|
cycloneive_lcell_comb \D[2]~34 (
|
|
// Equation(s):
|
|
// \D[2]~34_combout = (\D[2]~33_combout & (\ula_|zx_keyboard_|key_row~1_combout & ((\z80_|address_pins_|abus[8]~18_combout ) # (!\ula_|zx_keyboard_|keys[0][2]~q ))))
|
|
|
|
.dataa(\z80_|address_pins_|abus[8]~18_combout ),
|
|
.datab(\ula_|zx_keyboard_|keys[0][2]~q ),
|
|
.datac(\D[2]~33_combout ),
|
|
.datad(\ula_|zx_keyboard_|key_row~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[2]~34_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[2]~34 .lut_mask = 16'hB000;
|
|
defparam \D[2]~34 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y8_N28
|
|
cycloneive_lcell_comb \D[2]~37 (
|
|
// Equation(s):
|
|
// \D[2]~37_combout = (\z80_|address_pins_|abus[0]~16_combout ) # ((\D[2]~36_combout & (\D[2]~35_combout & \D[2]~34_combout )))
|
|
|
|
.dataa(\D[2]~36_combout ),
|
|
.datab(\D[2]~35_combout ),
|
|
.datac(\D[2]~34_combout ),
|
|
.datad(\z80_|address_pins_|abus[0]~16_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[2]~37_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[2]~37 .lut_mask = 16'hFF80;
|
|
defparam \D[2]~37 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X22_Y6_N0
|
|
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a18 (
|
|
.portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w [2]),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode244w[2]~0_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[2]~39_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a18_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .clk0_core_clock_enable = "ena0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .data_interleave_width_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file = "led_patterns.mif";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .init_file_layout = "port_a";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .operation_mode = "single_port";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_byte_enable_clock = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_out_clock = "clock0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_address = 0;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_first_bit_number = 2;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_last_address = 8191;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_depth = 32768;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_logical_ram_width = 8;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .port_b_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .ram_block_type = "M9K";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a18 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X22_Y9_N0
|
|
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a2 (
|
|
.portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w [2]),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode223w[2]~0_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[2]~39_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file = "led_patterns.mif";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "single_port";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 32768;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000024;
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X22_Y12_N0
|
|
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a10 (
|
|
.portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode236w [2]),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(\ram1|altsyncram_component|auto_generated|rden_decode|w_anode284w[2]~0_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[2]~39_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file = "led_patterns.mif";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "single_port";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 32768;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y10_N26
|
|
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2 (
|
|
// Equation(s):
|
|
// \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (\ram1|altsyncram_component|auto_generated|out_address_reg_a [0])) #
|
|
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & ((\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ))) #
|
|
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [0] & (\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ))))
|
|
|
|
.dataa(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]),
|
|
.datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [0]),
|
|
.datac(\ram1|altsyncram_component|auto_generated|ram_block1a2~portadataout ),
|
|
.datad(\ram1|altsyncram_component|auto_generated|ram_block1a10~portadataout ),
|
|
.cin(gnd),
|
|
.combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2 .lut_mask = 16'hDC98;
|
|
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X22_Y5_N0
|
|
cycloneive_ram_block \ram1|altsyncram_component|auto_generated|ram_block1a26 (
|
|
.portawe(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w [2]),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(\ram1|altsyncram_component|auto_generated|decode3|w_anode252w[2]~0_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[2]~39_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram1|altsyncram_component|auto_generated|ram_block1a26_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .clk0_core_clock_enable = "ena0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .data_interleave_width_in_bits = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file = "led_patterns.mif";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .init_file_layout = "port_a";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .logical_ram_name = "ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ALTSYNCRAM";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .operation_mode = "single_port";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_byte_enable_clock = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clear = "none";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_out_clock = "clock0";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_address = 0;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_first_bit_number = 2;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_last_address = 8191;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_depth = 32768;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_logical_ram_width = 8;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_address_width = 13;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .port_b_data_width = 1;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .ram_block_type = "M9K";
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram1|altsyncram_component|auto_generated|ram_block1a26 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y10_N8
|
|
cycloneive_lcell_comb \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3 (
|
|
// Equation(s):
|
|
// \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout = (\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & ((\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout &
|
|
// ((\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ))) # (!\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout & (\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout )))) #
|
|
// (!\ram1|altsyncram_component|auto_generated|out_address_reg_a [1] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ))))
|
|
|
|
.dataa(\ram1|altsyncram_component|auto_generated|ram_block1a18~portadataout ),
|
|
.datab(\ram1|altsyncram_component|auto_generated|out_address_reg_a [1]),
|
|
.datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~2_combout ),
|
|
.datad(\ram1|altsyncram_component|auto_generated|ram_block1a26~portadataout ),
|
|
.cin(gnd),
|
|
.combout(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3 .lut_mask = 16'hF838;
|
|
defparam \ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X22_Y3_N0
|
|
cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a10 (
|
|
.portawe(vcc),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(\z80_|address_pins_|abus[13]~20_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain(1'b0),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\rom|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file = "./rom/gw03.hex";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "rom";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock0";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_a_write_enable_clock = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h8102080042447C443C0C3C402004FC1838787840407A00707C02487E444878428008004042460424402040024A3242124220044022404208520A4A24424A125A0A1028440000524A0A4A4A204A5240460800100010540042002064547E0600001FA9BE02B828694B8A82CB8C8158226808198E9EC6B021F07A2098D5E0ECB639D2B1908129B6A2D646516192D87593189D8B2B26CD6E16234C1CC90AD9831EBD89EAD271ECC39A80507716BB49626B743DFFCF99576C3FAC889860E46618ACB79EC30EEDE42EB1E31F3976CA23243179FAA96DCD66D51535351770D410DC8531866136E6184518410368288C446EC63A4FEE425019C244097049C2B2DC8D93C4;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'hA111466C9493A2A7CA2204102414CC798BF0EEC2995A4814580BD07585585ED92E5172E82E845070000A846100500E84EA1803B8B07B99E1DC75BE6419674597B38F54EB9091AE3320201EE395AD63902282A031CE3E87CC902954AA515D5D6B6A855EC94CFEC4E0172C59A7D054F8F9F4356C312C204E40B05E2059407C8DC84683814663FB910969D1D631A952B381B7F635A33FD38D5CF15DF47D057F7FF555B555C2278100000A24804D7D98EB98602733818A12094F281287422CB40002464C92242004E0AE8518E001D124A7628010115D23C30462FC00A014A12133582A191E00538FC8A5004036A959ACB7A463D23E419EA06B744005385455A71250;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h6C60009CA281AEACDC1762945981B869F93D683EAF4AC7EE52412E85B60B91CD03AD0025F0D509F63202D877ECD8BF8005451F7BD346CF9E17B36F1850A7D80A8CF14A288EAE3BFE00FB2DB45080D4A50C58263A3B398DD51AB9CB554ECAA7B2E73D9D6D2C265859DB844C2C1952AD10241100174FE0444E6707D80A098D8585AAAC4802B74190FB007C0C0206186AFC1B3A2A46864F26118ED1D03ACB1062B7315502751655F60070E6B2C50609369611365AD1E3352327320331A51818030C7D8C4C59396600DC0C420495A0D987501490002BAD38012E20620D556A230B1796450B74E95A860FF3E434C65F1308F16F92395816B914F0CE870C1323347A4E;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h7FC8531A7A319F3EBFC1383FFCDB0E09BD288288B078B4AD220B6FA934CF6187D972662C0D31E34E63B31CFC6EB4B35A69B67D85489E62EA99899A94F6800FDBA5D31B86A0288D29CE2EAAFF86A6A9F7000082293E6BB54F06E98ECCB199973EDA00FADB1D3A630BA18050635DE7DCB13B9B86E0CE6E08DC46331A352F716E3C441A0CC068A0823F8668A00621B779DE35FEC004050469F34866AEE766743D8C00FDF3B9F8DE7B76E97F8D32F0F39E4CAC68D9BBB68EA3915F6225F932CAAFDAD6E60DC661155EC9E80F8CEE659F19CC554B2C67C33EDCDA63BAD91B7D1842A7177AF49DF118FE47ACE3344964EBCADCFBB543F7729CCB340866D1157B6CCDDB;
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X22_Y29_N0
|
|
cycloneive_ram_block \rom|altsyncram_component|auto_generated|ram_block1a2 (
|
|
.portawe(vcc),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.clk1(gnd),
|
|
.ena0(!\z80_|address_pins_|abus[13]~20_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain(1'b0),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain(1'b0),
|
|
.portbaddr(13'b0000000000000),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\rom|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file = "./rom/gw03.hex";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ALTSYNCRAM";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "rom";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock0";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_a_write_enable_clock = "none";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K";
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h77A47C739FF6A22B8B5CDC49E748E9C739BDE6756DB4D22437E74183E12400CBF7D3C6CC8C7841AB49CC538E8A72F2E73C64D3DF3662B19C07D7D299CBEDEF3E7DA5F4A8458A9451315B681ADA9AB0D63218DFB77D3353C32837E954604B9D98144A4566F47B71715BE6CDB8BA64D536762E9224D70F9A5C374B4D1CAB8DF527027170C5DBCC2B6AD72B8E4CCC94DAA139D8BA64E3384337426E7F274CC88A373AB1F9007B8A7F2936D16274F9BF8B6BABD48FCE74047C1E738C5B303E815BA720C76D6362915156A7671331CE657011862E594E46A6D99392E2D640D766869389A4D43867379AB880C1ACE279E451CB3A9063A0B320F65E536B8EEF9CBB9C76;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h9A2921ED6AA0CC8387B267B9E7A182720833CEE061E6450C8E4A72E3C043F21A0AD007E832124E92429C091D167806C10041AF32DDE13A669990457D098CC2FE3AC884B1E69101135CD080022451F20884CCB9CD203C141402A5AD293C3BABA95ADFAF6726384795A7656B753D2369B9EB5595BAA722012DF8DCFBF15BF46D6EB755D1CBF0DCF6FD40BEEC16EAB4A6D16839C98CBE9DBB437C69FB709F8E79993B9DDFE4F823D6E124B75BCE9B29F799F926619184B6C1178389F07349210436293A130C900FBA4EA70D2BA25B343C5B026D8E8766A4E4267CDAEC99E830D2307D94E6ED80D6722F3989B91E31C63B64C363DCE71A861C14382E270FC02868C7;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h386BA04E797A3F8551DAD9D24A8D259A03ECFF5AB81B1C31DFDAE10100544F8CF1A8CCFC0C7A15BD9E7C2557CB00BF2584E16AAD13D7EDB525A85ABF90C0136DD195D748900C29DF7F381280A9738CDC3BF5BBF937D3A4D99CE2BCCD97CEF2C7F00030AFDB7F22E68CBAA4D9BE7633D3B53E90E4B124422A2A4454BACA5A8DC9352CD1DAFC910CC504334DF9E6F1F4F30161A36293CC5CCF1CA13994ED29D34A5699692496359B8E67A7E74D9A0FC504C8465638CF74A0AF9185921A7D2629893091900604017933442359491FBAB63F346F0C5EC8E3A531984B09E605A30A0627271C28420E47B8DEC74738FC3EDF9FBD40EC09FC7B4D3A1475BE433705FB5F;
|
|
defparam \rom|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h973FED2E9BEDBA474B70B121A8D60F3B4EE3F1A238FB3B730EDEEE74EC632DB4D7779D7B79D1C75DF87378E98719C1AF38B1B801C71D180CE86370AE9C2BF38CF84DBBB9878C55457324E92D3DAE91D729AC76BBAD4C6EECA74DAB5EE9A175EE34ABEB9DFAA48538A57E3E5C158947081CA41402E8E65478737F73BB629AAE2EE51D405CAF70F622DD4599602D7910DCAC8214B2A42025110593202C8B164C8DF6369572C3BB8AA1984A8D12F776E224ECEEB21F97FCD6C0CF17A044EC2BBF0571A553CCDD8ABA79BD27B7AF735ED2D34F1EF3A81A160C9ECB1B1FAE6EDEEFF99E28CC30C7C2553DED3378D655AD194B2E6C1BCBED700F6713D960F33E4C361A;
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X22_Y25_N0
|
|
cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a10 (
|
|
.portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[1]~0_combout ),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\CLOCK_50~inputclkctrl_outclk ),
|
|
.clk1(\CLOCK_50~inputclkctrl_outclk ),
|
|
.ena0(\z80_|address_pins_|abus[13]~20_combout ),
|
|
.ena1(gnd),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[2]~39_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain({\~GND~combout }),
|
|
.portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4],
|
|
\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a10_PORTADATAOUT_bus ),
|
|
.portbdataout());
|
|
// synopsys translate_off
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk0_core_clock_enable = "ena0";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .clk1_core_clock_enable = "ena1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .data_interleave_width_in_bits = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file = "ula/test_scr.hex";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .init_file_layout = "port_a";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mixed_port_feed_through_mode = "dont_care";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .operation_mode = "bidir_dual_port";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_address_width = 13;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_byte_enable_clock = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_out_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_data_width = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_address = 0;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_first_bit_number = 2;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_last_address = 8191;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_depth = 16384;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_logical_ram_width = 8;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_address_width = 13;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_in_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_out_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_data_width = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_address = 0;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_first_bit_number = 2;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_last_address = 8191;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_depth = 16384;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_logical_ram_width = 8;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_read_enable_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .port_b_write_enable_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .ram_block_type = "M9K";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init2 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a10 .mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
// synopsys translate_on
|
|
|
|
// Location: M9K_X22_Y27_N0
|
|
cycloneive_ram_block \ram0|altsyncram_component|auto_generated|ram_block1a2 (
|
|
.portawe(\ram0|altsyncram_component|auto_generated|decode2|eq_node[0]~1_combout ),
|
|
.portare(vcc),
|
|
.portaaddrstall(gnd),
|
|
.portbwe(gnd),
|
|
.portbre(vcc),
|
|
.portbaddrstall(gnd),
|
|
.clk0(\CLOCK_50~inputclkctrl_outclk ),
|
|
.clk1(\CLOCK_50~inputclkctrl_outclk ),
|
|
.ena0(!\z80_|address_pins_|abus[13]~20_combout ),
|
|
.ena1(vcc),
|
|
.ena2(vcc),
|
|
.ena3(vcc),
|
|
.clr0(gnd),
|
|
.clr1(gnd),
|
|
.portadatain({\D[2]~39_combout }),
|
|
.portaaddr({\z80_|address_pins_|abus[12]~21_combout ,\z80_|address_pins_|abus[11]~19_combout ,\z80_|address_pins_|abus[10]~24_combout ,\z80_|address_pins_|abus[9]~17_combout ,\z80_|address_pins_|abus[8]~18_combout ,\z80_|address_pins_|abus[7]~31_combout ,
|
|
\z80_|address_pins_|abus[6]~30_combout ,\z80_|address_pins_|abus[5]~29_combout ,\z80_|address_pins_|abus[4]~28_combout ,\z80_|address_pins_|abus[3]~27_combout ,\z80_|address_pins_|abus[2]~26_combout ,\z80_|address_pins_|abus[1]~25_combout ,
|
|
\z80_|address_pins_|abus[0]~16_combout }),
|
|
.portabyteenamasks(1'b1),
|
|
.portbdatain({\~GND~combout }),
|
|
.portbaddr({\ula_|video_|vram_address [12],\ula_|video_|vram_address [11],\ula_|video_|vram_address [10],\ula_|video_|vram_address [9],\ula_|video_|vram_address [8],\ula_|video_|vram_address [7],\ula_|video_|vram_address [6],\ula_|video_|vram_address [5],\ula_|video_|vram_address [4],
|
|
\ula_|video_|vram_address [3],\ula_|video_|vram_address [2],\ula_|video_|vram_address [1],\ula_|video_|vram_address [0]}),
|
|
.portbbyteenamasks(1'b1),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.portadataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTADATAOUT_bus ),
|
|
.portbdataout(\ram0|altsyncram_component|auto_generated|ram_block1a2_PORTBDATAOUT_bus ));
|
|
// synopsys translate_off
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .clk0_core_clock_enable = "ena0";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_offset_in_bits = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .data_interleave_width_in_bits = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file = "ula/test_scr.hex";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .init_file_layout = "port_a";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .logical_ram_name = "ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ALTSYNCRAM";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mixed_port_feed_through_mode = "dont_care";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .operation_mode = "bidir_dual_port";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_address_width = 13;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_byte_enable_clock = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_out_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_data_width = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_address = 0;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_first_bit_number = 2;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_last_address = 8191;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_depth = 16384;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_logical_ram_width = 8;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_a_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_address_width = 13;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_in_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clear = "none";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_out_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_data_width = 1;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_address = 0;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_first_bit_number = 2;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_last_address = 8191;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_depth = 16384;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_logical_ram_width = 8;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_during_write_mode = "new_data_with_nbe_read";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_read_enable_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .port_b_write_enable_clock = "clock1";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .ram_block_type = "M9K";
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init3 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFFFFF68003FFF38003FFF9F403FFF8B003D8F87003FFF8F01BEDFC701FEBFEA01FDBFDC00FDBFDC01FC7FDC0FFC7FDE87FC7FCDC8FC7FCF89FC07071FFC0F873F3E0303FE7FFFFFFFFFFFFFFFF;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init2 = 2048'h000000000000000000000000FFFFFFFF0000000000040078400234B1474928D1000000000000000000000000FFFFFFFF204081024004027153423DA5474928DD000000000000000000000000000000003FFFFFFF40041CB14162378547495999000000000000000000000000000000003FFFFFFF4004189141623485474959F90000000000000000000000003FFFFFFE40000001400400815B6223C15FC913DD0000000000000000000000007FFFFFFE40000001400402E9400333715FC973E5000000000000000000000000604081027FFFFFFD5FE60AE95763353540091361000000000000000000000000400000003FFFFFFC5FE60AE95763081D40011361;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init1 = 2048'h5FE0236948F816F55FE897C10C28028041DC8DE178059BC16900BB4173E47AC15FE8236148E806F55FE891054CA80E8148288DE179E597C169903AC153F13A8140080365486806D55FE891D548080A8148608FE159E493C16BB03FD152BD1AE14008037D482017D15FE881C548A00AC148E08FE159FC9AC16AA02FC15AAF18F1400083F1482007C15EE882C148E00A4148B08FE148F88D4168E436915ABB01E9400092F9480007815C2882C148E00B6149B49F614868FD41436476814AFA42A1400892FD480807C15C0883C149800FE149DC9FE14A60BD41431C3F914AEA01C1400882F1480817C11C0883C041940FE549CC9EE54860BDC143BC7D8108D2C4D0;
|
|
defparam \ram0|altsyncram_component|auto_generated|ram_block1a2 .mem_init0 = 2048'h0B928870484885014DE84481680162815375AC0148D308813FFFFFFC400000004B9288314DC0970149FC44856C0166815375AC8140D108817FFFFFFD6040808249D0A2094F908581481C40814C016099417DA88140D10B01400000017FFFFFFE48D083394B9085814A085081440166814179900140510F01400000013FFFFFFE4A508335498001814BE0608146016E8941799041405107413FFFFFFF000000004B98812149C005814BE0628146836E814179100140510F013FFFFFFF000000004B98A1114BE801814A00668147832C814119904140401F4120408082FFFFFFFF48D881154EA801854800768147C22CC14019900100003E0000000000FFFFFFFF;
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y10_N24
|
|
cycloneive_lcell_comb \Selector0~0 (
|
|
// Equation(s):
|
|
// \Selector0~0_combout = (\Selector3~0_combout & (((\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout )) # (!\z80_|address_pins_|abus[14]~23_combout ))) # (!\Selector3~0_combout & (\z80_|address_pins_|abus[14]~23_combout &
|
|
// ((\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ))))
|
|
|
|
.dataa(\Selector3~0_combout ),
|
|
.datab(\z80_|address_pins_|abus[14]~23_combout ),
|
|
.datac(\ram0|altsyncram_component|auto_generated|ram_block1a10~portadataout ),
|
|
.datad(\ram0|altsyncram_component|auto_generated|ram_block1a2~portadataout ),
|
|
.cin(gnd),
|
|
.combout(\Selector0~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \Selector0~0 .lut_mask = 16'hE6A2;
|
|
defparam \Selector0~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y10_N18
|
|
cycloneive_lcell_comb \Selector0~1 (
|
|
// Equation(s):
|
|
// \Selector0~1_combout = (\z80_|address_pins_|abus[14]~23_combout & (((\Selector0~0_combout )))) # (!\z80_|address_pins_|abus[14]~23_combout & ((\Selector0~0_combout & (\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout )) #
|
|
// (!\Selector0~0_combout & ((\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout )))))
|
|
|
|
.dataa(\z80_|address_pins_|abus[14]~23_combout ),
|
|
.datab(\rom|altsyncram_component|auto_generated|ram_block1a10~portadataout ),
|
|
.datac(\rom|altsyncram_component|auto_generated|ram_block1a2~portadataout ),
|
|
.datad(\Selector0~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\Selector0~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \Selector0~1 .lut_mask = 16'hEE50;
|
|
defparam \Selector0~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y10_N28
|
|
cycloneive_lcell_comb \D[2]~82 (
|
|
// Equation(s):
|
|
// \D[2]~82_combout = (\z80_|address_pins_|DFFE_apin_latch [15] & (((\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout )))) # (!\z80_|address_pins_|DFFE_apin_latch [15] & ((\z80_|resets_|SYNTHESIZED_WIRE_12~q & ((\Selector0~1_combout
|
|
// ))) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q & (\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout ))))
|
|
|
|
.dataa(\z80_|address_pins_|DFFE_apin_latch [15]),
|
|
.datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.datac(\ram1|altsyncram_component|auto_generated|mux2|result_node[2]~3_combout ),
|
|
.datad(\Selector0~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[2]~82_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[2]~82 .lut_mask = 16'hF4B0;
|
|
defparam \D[2]~82 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y10_N12
|
|
cycloneive_lcell_comb \D[2]~38 (
|
|
// Equation(s):
|
|
// \D[2]~38_combout = ((\Equal2~0_combout & (\D[2]~37_combout )) # (!\Equal2~0_combout & ((\D[2]~82_combout )))) # (!\Equal2~1_combout )
|
|
|
|
.dataa(\Equal2~1_combout ),
|
|
.datab(\Equal2~0_combout ),
|
|
.datac(\D[2]~37_combout ),
|
|
.datad(\D[2]~82_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[2]~38_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[2]~38 .lut_mask = 16'hF7D5;
|
|
defparam \D[2]~38 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y10_N30
|
|
cycloneive_lcell_comb \D[2]~39 (
|
|
// Equation(s):
|
|
// \D[2]~39_combout = (\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\z80_|data_pins_|dout [2] & \D[2]~38_combout )))) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout & (((\D[2]~38_combout )) # (!\Equal2~1_combout )))
|
|
|
|
.dataa(\Equal2~1_combout ),
|
|
.datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ),
|
|
.datac(\z80_|data_pins_|dout [2]),
|
|
.datad(\D[2]~38_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[2]~39_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[2]~39 .lut_mask = 16'hF311;
|
|
defparam \D[2]~39 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y13_N4
|
|
cycloneive_lcell_comb \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] (
|
|
// Equation(s):
|
|
// \z80_|data_pins_|SYNTHESIZED_WIRE_0 [2] = (\z80_|execute_|ctl_bus_db_we~7_combout & ((\z80_|bus_control_|db[2]~13_combout ) # ((\D[2]~39_combout & \z80_|pin_control_|bus_db_pin_re~combout )))) # (!\z80_|execute_|ctl_bus_db_we~7_combout &
|
|
// (((\D[2]~39_combout & \z80_|pin_control_|bus_db_pin_re~combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_bus_db_we~7_combout ),
|
|
.datab(\z80_|bus_control_|db[2]~13_combout ),
|
|
.datac(\D[2]~39_combout ),
|
|
.datad(\z80_|pin_control_|bus_db_pin_re~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .lut_mask = 16'hF888;
|
|
defparam \z80_|data_pins_|SYNTHESIZED_WIRE_0[2] .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X30_Y13_N5
|
|
dffeas \z80_|data_pins_|dout[2] (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|data_pins_|SYNTHESIZED_WIRE_0 [2]),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|data_pins_|SYNTHESIZED_WIRE_2~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|data_pins_|dout [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|data_pins_|dout[2] .is_wysiwyg = "true";
|
|
defparam \z80_|data_pins_|dout[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y13_N6
|
|
cycloneive_lcell_comb \z80_|bus_control_|db[2]~12 (
|
|
// Equation(s):
|
|
// \z80_|bus_control_|db[2]~12_combout = (\z80_|bus_control_|db[0]~4_combout & ((\z80_|alu_control_|db[2]~29_combout ) # (!\z80_|execute_|ctl_bus_db_we~7_combout )))
|
|
|
|
.dataa(\z80_|bus_control_|db[0]~4_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|alu_control_|db[2]~29_combout ),
|
|
.datad(\z80_|execute_|ctl_bus_db_we~7_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|bus_control_|db[2]~12_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|bus_control_|db[2]~12 .lut_mask = 16'hA0AA;
|
|
defparam \z80_|bus_control_|db[2]~12 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X30_Y13_N0
|
|
cycloneive_lcell_comb \z80_|bus_control_|db[2]~13 (
|
|
// Equation(s):
|
|
// \z80_|bus_control_|db[2]~13_combout = ((\z80_|bus_control_|db[2]~12_combout & ((\z80_|data_pins_|dout [2]) # (!\z80_|execute_|ctl_bus_db_oe~combout )))) # (!\z80_|bus_control_|db[0]~6_combout )
|
|
|
|
.dataa(\z80_|bus_control_|db[0]~6_combout ),
|
|
.datab(\z80_|execute_|ctl_bus_db_oe~combout ),
|
|
.datac(\z80_|data_pins_|dout [2]),
|
|
.datad(\z80_|bus_control_|db[2]~12_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|bus_control_|db[2]~13_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|bus_control_|db[2]~13 .lut_mask = 16'hF755;
|
|
defparam \z80_|bus_control_|db[2]~13 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X29_Y13_N27
|
|
dffeas \z80_|ir_|opcode[2] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|bus_control_|db[2]~13_combout ),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|execute_|ctl_ir_we~13_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|ir_|opcode [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|ir_|opcode[2] .is_wysiwyg = "true";
|
|
defparam \z80_|ir_|opcode[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y13_N18
|
|
cycloneive_lcell_comb \z80_|pla_decode_|Equal1~4 (
|
|
// Equation(s):
|
|
// \z80_|pla_decode_|Equal1~4_combout = (!\z80_|ir_|opcode [2] & !\z80_|ir_|opcode [1])
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|ir_|opcode [2]),
|
|
.datac(\z80_|ir_|opcode [1]),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|pla_decode_|Equal1~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|pla_decode_|Equal1~4 .lut_mask = 16'h0303;
|
|
defparam \z80_|pla_decode_|Equal1~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y13_N2
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~26 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op_low~26_combout = (\z80_|pla_decode_|Equal1~4_combout & (\z80_|execute_|ctl_mWrite~5_combout & (\z80_|pla_decode_|Equal13~0_combout & !\z80_|ir_|opcode [0])))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal1~4_combout ),
|
|
.datab(\z80_|execute_|ctl_mWrite~5_combout ),
|
|
.datac(\z80_|pla_decode_|Equal13~0_combout ),
|
|
.datad(\z80_|ir_|opcode [0]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op_low~26_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op_low~26 .lut_mask = 16'h0080;
|
|
defparam \z80_|execute_|ctl_alu_op_low~26 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y16_N18
|
|
cycloneive_lcell_comb \z80_|execute_|ctl_alu_op_low~45 (
|
|
// Equation(s):
|
|
// \z80_|execute_|ctl_alu_op_low~45_combout = (!\z80_|execute_|ctl_alu_op_low~26_combout & (((!\z80_|sequencer_|DFFE_T3_ff~q ) # (!\z80_|pla_decode_|Equal13~2_combout )) # (!\z80_|sequencer_|DFFE_M4_ff~q )))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op_low~26_combout ),
|
|
.datab(\z80_|sequencer_|DFFE_M4_ff~q ),
|
|
.datac(\z80_|pla_decode_|Equal13~2_combout ),
|
|
.datad(\z80_|sequencer_|DFFE_T3_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|ctl_alu_op_low~45_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|ctl_alu_op_low~45 .lut_mask = 16'h1555;
|
|
defparam \z80_|execute_|ctl_alu_op_low~45 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y18_N28
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~17 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~17_combout = (!\z80_|execute_|ctl_alu_shift_oe~15_combout & (\z80_|execute_|ctl_sw_2u~1_combout & \z80_|execute_|ctl_state_alu~7_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_shift_oe~15_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|execute_|ctl_sw_2u~1_combout ),
|
|
.datad(\z80_|execute_|ctl_state_alu~7_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~17_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~17 .lut_mask = 16'h5000;
|
|
defparam \z80_|execute_|setM1~17 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y18_N30
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~18 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~18_combout = (\z80_|execute_|ctl_alu_op_low~45_combout & (\z80_|execute_|setM1~17_combout & (!\z80_|execute_|ctl_flags_cf2_sel_daa~combout & !\z80_|execute_|ctl_alu_op1_sel_zero~4_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_op_low~45_combout ),
|
|
.datab(\z80_|execute_|setM1~17_combout ),
|
|
.datac(\z80_|execute_|ctl_flags_cf2_sel_daa~combout ),
|
|
.datad(\z80_|execute_|ctl_alu_op1_sel_zero~4_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~18_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~18 .lut_mask = 16'h0008;
|
|
defparam \z80_|execute_|setM1~18 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y13_N6
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~11 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~11_combout = (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ) # ((!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_mWrite~4_combout & !\z80_|ir_|opcode [4])))
|
|
|
|
.dataa(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ),
|
|
.datab(\z80_|ir_|opcode [2]),
|
|
.datac(\z80_|execute_|ctl_mWrite~4_combout ),
|
|
.datad(\z80_|ir_|opcode [4]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~11_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~11 .lut_mask = 16'hAABA;
|
|
defparam \z80_|execute_|setM1~11 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y12_N10
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~10 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~10_combout = (\z80_|execute_|ctl_mRead~5_combout ) # (((\z80_|execute_|ctl_mWrite~6_combout ) # (\z80_|pla_decode_|Equal6~1_combout )) # (!\z80_|execute_|fMWrite~1_combout ))
|
|
|
|
.dataa(\z80_|execute_|ctl_mRead~5_combout ),
|
|
.datab(\z80_|execute_|fMWrite~1_combout ),
|
|
.datac(\z80_|execute_|ctl_mWrite~6_combout ),
|
|
.datad(\z80_|pla_decode_|Equal6~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~10 .lut_mask = 16'hFFFB;
|
|
defparam \z80_|execute_|setM1~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y12_N20
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~12 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~12_combout = ((\z80_|execute_|setM1~10_combout ) # ((\z80_|execute_|setM1~11_combout & \z80_|execute_|ctl_mWrite~17_combout ))) # (!\z80_|execute_|nextM~2_combout )
|
|
|
|
.dataa(\z80_|execute_|nextM~2_combout ),
|
|
.datab(\z80_|execute_|setM1~11_combout ),
|
|
.datac(\z80_|execute_|ctl_mWrite~17_combout ),
|
|
.datad(\z80_|execute_|setM1~10_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~12_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~12 .lut_mask = 16'hFFD5;
|
|
defparam \z80_|execute_|setM1~12 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y12_N28
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~8 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~8_combout = (\z80_|execute_|ctl_al_we~13_combout & (\z80_|sequencer_|M5~q & ((\z80_|pla_decode_|Equal9~1_combout )))) # (!\z80_|execute_|ctl_al_we~13_combout & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|sequencer_|M5~q &
|
|
// \z80_|pla_decode_|Equal9~1_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_al_we~13_combout ),
|
|
.datab(\z80_|sequencer_|M5~q ),
|
|
.datac(\z80_|sequencer_|DFFE_M4_ff~q ),
|
|
.datad(\z80_|pla_decode_|Equal9~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~8 .lut_mask = 16'hDC50;
|
|
defparam \z80_|execute_|setM1~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y12_N2
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~9 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~9_combout = ((\z80_|sequencer_|DFFE_T5_ff~q & \z80_|execute_|setM1~8_combout )) # (!\z80_|execute_|ctl_flags_xy_we~19_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_xy_we~19_combout ),
|
|
.datab(\z80_|sequencer_|DFFE_T5_ff~q ),
|
|
.datac(gnd),
|
|
.datad(\z80_|execute_|setM1~8_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~9 .lut_mask = 16'hDD55;
|
|
defparam \z80_|execute_|setM1~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y12_N18
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~13 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~13_combout = ((\z80_|execute_|setM1~9_combout ) # ((\z80_|execute_|setM1~12_combout & \z80_|execute_|ixy_d~6_combout ))) # (!\z80_|reg_control_|reg_sel_pc~3_combout )
|
|
|
|
.dataa(\z80_|reg_control_|reg_sel_pc~3_combout ),
|
|
.datab(\z80_|execute_|setM1~12_combout ),
|
|
.datac(\z80_|execute_|ixy_d~6_combout ),
|
|
.datad(\z80_|execute_|setM1~9_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~13_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~13 .lut_mask = 16'hFFD5;
|
|
defparam \z80_|execute_|setM1~13 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y13_N28
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~15 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~15_combout = (\z80_|pla_decode_|Equal33~0_combout & (!\z80_|pla_decode_|Equal13~0_combout & ((!\z80_|pla_decode_|Equal21~2_combout ) # (!\z80_|pla_decode_|Equal32~0_combout )))) # (!\z80_|pla_decode_|Equal33~0_combout &
|
|
// (((!\z80_|pla_decode_|Equal21~2_combout )) # (!\z80_|pla_decode_|Equal32~0_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal33~0_combout ),
|
|
.datab(\z80_|pla_decode_|Equal32~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal13~0_combout ),
|
|
.datad(\z80_|pla_decode_|Equal21~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~15_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~15 .lut_mask = 16'h135F;
|
|
defparam \z80_|execute_|setM1~15 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y13_N24
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~14 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~14_combout = (!\z80_|execute_|ctl_alu_oe~1_combout & (!\z80_|pla_decode_|Equal77~1_combout & (!\z80_|pla_decode_|Equal1~6_combout & !\z80_|pla_decode_|Equal2~2_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_alu_oe~1_combout ),
|
|
.datab(\z80_|pla_decode_|Equal77~1_combout ),
|
|
.datac(\z80_|pla_decode_|Equal1~6_combout ),
|
|
.datad(\z80_|pla_decode_|Equal2~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~14_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~14 .lut_mask = 16'h0001;
|
|
defparam \z80_|execute_|setM1~14 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y13_N30
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~16 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~16_combout = (\z80_|interrupts_|test1~2_combout & (\z80_|execute_|setM1~15_combout & \z80_|execute_|setM1~14_combout ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|interrupts_|test1~2_combout ),
|
|
.datac(\z80_|execute_|setM1~15_combout ),
|
|
.datad(\z80_|execute_|setM1~14_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~16_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~16 .lut_mask = 16'hC000;
|
|
defparam \z80_|execute_|setM1~16 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y12_N28
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~19 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~19_combout = ((\z80_|execute_|setM1~13_combout ) # ((!\z80_|execute_|setM1~16_combout & \z80_|execute_|ctl_eval_cond~0_combout ))) # (!\z80_|execute_|setM1~18_combout )
|
|
|
|
.dataa(\z80_|execute_|setM1~18_combout ),
|
|
.datab(\z80_|execute_|setM1~13_combout ),
|
|
.datac(\z80_|execute_|setM1~16_combout ),
|
|
.datad(\z80_|execute_|ctl_eval_cond~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~19_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~19 .lut_mask = 16'hDFDD;
|
|
defparam \z80_|execute_|setM1~19 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y17_N16
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~23 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~23_combout = (\z80_|execute_|fMWrite~1_combout & (!\z80_|execute_|ctl_mRead~8_combout & (!\z80_|execute_|ctl_mRead~6_combout & \z80_|execute_|fMWrite~6_combout )))
|
|
|
|
.dataa(\z80_|execute_|fMWrite~1_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~8_combout ),
|
|
.datac(\z80_|execute_|ctl_mRead~6_combout ),
|
|
.datad(\z80_|execute_|fMWrite~6_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~23_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~23 .lut_mask = 16'h0200;
|
|
defparam \z80_|execute_|setM1~23 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y13_N2
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~22 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~22_combout = (\z80_|decode_state_|DFFE_instNonRep~q ) # ((!\z80_|ir_|opcode [2] & (\z80_|execute_|ctl_mWrite~4_combout & !\z80_|ir_|opcode [4])))
|
|
|
|
.dataa(\z80_|ir_|opcode [2]),
|
|
.datab(\z80_|execute_|ctl_mWrite~4_combout ),
|
|
.datac(\z80_|decode_state_|DFFE_instNonRep~q ),
|
|
.datad(\z80_|ir_|opcode [4]),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~22_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~22 .lut_mask = 16'hF0F4;
|
|
defparam \z80_|execute_|setM1~22 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y13_N26
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~56 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~56_combout = (\z80_|sequencer_|DFFE_T5_ff~q & ((\z80_|sequencer_|DFFE_M4_ff~q ) # ((\z80_|sequencer_|DFFE_M3_ff~q & \z80_|execute_|setM1~22_combout ))))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_M3_ff~q ),
|
|
.datab(\z80_|sequencer_|DFFE_T5_ff~q ),
|
|
.datac(\z80_|sequencer_|DFFE_M4_ff~q ),
|
|
.datad(\z80_|execute_|setM1~22_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~56_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~56 .lut_mask = 16'hC8C0;
|
|
defparam \z80_|execute_|setM1~56 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y13_N6
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~24 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~24_combout = (\z80_|execute_|setM1~23_combout & (!\z80_|execute_|ctl_flags_bus~1_combout & ((\z80_|execute_|setM1~56_combout )))) # (!\z80_|execute_|setM1~23_combout & ((\z80_|execute_|ctl_reg_in_hi~2_combout ) #
|
|
// ((!\z80_|execute_|ctl_flags_bus~1_combout & \z80_|execute_|setM1~56_combout ))))
|
|
|
|
.dataa(\z80_|execute_|setM1~23_combout ),
|
|
.datab(\z80_|execute_|ctl_flags_bus~1_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_in_hi~2_combout ),
|
|
.datad(\z80_|execute_|setM1~56_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~24_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~24 .lut_mask = 16'h7350;
|
|
defparam \z80_|execute_|setM1~24 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y15_N4
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~25 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~25_combout = (\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & !\z80_|execute_|ctl_mRead~10_combout )) # (!\z80_|alu_control_|flags_cond_true~q ))) #
|
|
// (!\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout & (((\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout & !\z80_|execute_|ctl_mRead~10_combout ))))
|
|
|
|
.dataa(\z80_|execute_|ctl_reg_sys_hilo_pla42M3T3_6~combout ),
|
|
.datab(\z80_|alu_control_|flags_cond_true~q ),
|
|
.datac(\z80_|execute_|ctl_reg_sys_hilo_pla56M3T3_6~combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~10_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~25_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~25 .lut_mask = 16'h22F2;
|
|
defparam \z80_|execute_|setM1~25 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X21_Y12_N12
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~26 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~26_combout = ((\z80_|execute_|ctl_mRead~11_combout ) # ((!\z80_|alu_control_|flags_cond_true~q & \z80_|pla_decode_|Equal40~1_combout ))) # (!\z80_|execute_|ctl_bus_inc_oe~31_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_bus_inc_oe~31_combout ),
|
|
.datab(\z80_|alu_control_|flags_cond_true~q ),
|
|
.datac(\z80_|pla_decode_|Equal40~1_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~11_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~26_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~26 .lut_mask = 16'hFF75;
|
|
defparam \z80_|execute_|setM1~26 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y13_N16
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~27 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~27_combout = (\z80_|execute_|setM1~26_combout ) # (((\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & \z80_|pla_decode_|Equal21~1_combout )) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ))
|
|
|
|
.dataa(\z80_|execute_|setM1~26_combout ),
|
|
.datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ),
|
|
.datad(\z80_|pla_decode_|Equal21~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~27_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~27 .lut_mask = 16'hEFAF;
|
|
defparam \z80_|execute_|setM1~27 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y13_N10
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~28 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~28_combout = (\z80_|execute_|setM1~24_combout ) # ((\z80_|execute_|setM1~25_combout ) # ((\z80_|execute_|ctl_state_alu~2_combout & \z80_|execute_|setM1~27_combout )))
|
|
|
|
.dataa(\z80_|execute_|setM1~24_combout ),
|
|
.datab(\z80_|execute_|ctl_state_alu~2_combout ),
|
|
.datac(\z80_|execute_|setM1~25_combout ),
|
|
.datad(\z80_|execute_|setM1~27_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~28_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~28 .lut_mask = 16'hFEFA;
|
|
defparam \z80_|execute_|setM1~28 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y13_N18
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~55 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~55_combout = ((\z80_|sequencer_|DFFE_M2_ff~q & (\z80_|sequencer_|DFFE_T4_ff~q & \z80_|execute_|ctl_iorw~10_combout ))) # (!\z80_|execute_|ctl_flags_sz_we~0_combout )
|
|
|
|
.dataa(\z80_|execute_|ctl_flags_sz_we~0_combout ),
|
|
.datab(\z80_|sequencer_|DFFE_M2_ff~q ),
|
|
.datac(\z80_|sequencer_|DFFE_T4_ff~q ),
|
|
.datad(\z80_|execute_|ctl_iorw~10_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~55_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~55 .lut_mask = 16'hD555;
|
|
defparam \z80_|execute_|setM1~55 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y13_N4
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~29 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~29_combout = (\z80_|execute_|ctl_mRead~13_combout ) # ((\z80_|execute_|ctl_mRead~5_combout ) # ((\z80_|execute_|ctl_mRead~7_combout ) # (!\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_mRead~13_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~5_combout ),
|
|
.datac(\z80_|execute_|ctl_reg_gp_hilo[1]~44_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~7_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~29_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~29 .lut_mask = 16'hFFEF;
|
|
defparam \z80_|execute_|setM1~29 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y13_N12
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~31 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~31_combout = (((\z80_|execute_|ctl_state_alu~4_combout & \z80_|execute_|setM1~29_combout )) # (!\z80_|execute_|setM1~57_combout )) # (!\z80_|execute_|setM1~30_combout )
|
|
|
|
.dataa(\z80_|execute_|setM1~30_combout ),
|
|
.datab(\z80_|execute_|ctl_state_alu~4_combout ),
|
|
.datac(\z80_|execute_|setM1~29_combout ),
|
|
.datad(\z80_|execute_|setM1~57_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~31_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~31 .lut_mask = 16'hD5FF;
|
|
defparam \z80_|execute_|setM1~31 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y13_N20
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~33 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~33_combout = (\z80_|execute_|ctl_mRead~2_combout ) # ((\z80_|execute_|ctl_mRead~3_combout ) # ((\z80_|execute_|ctl_mRead~34_combout & \z80_|execute_|setM1~11_combout )))
|
|
|
|
.dataa(\z80_|execute_|ctl_mRead~2_combout ),
|
|
.datab(\z80_|execute_|ctl_mRead~34_combout ),
|
|
.datac(\z80_|execute_|setM1~11_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~3_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~33_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~33 .lut_mask = 16'hFFEA;
|
|
defparam \z80_|execute_|setM1~33 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y13_N2
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~32 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~32_combout = (\z80_|pla_decode_|Equal35~0_combout & ((\z80_|execute_|ixy_d~6_combout ) # ((\z80_|execute_|ctl_reg_in_hi~2_combout & \z80_|execute_|ctl_mRead~16_combout )))) # (!\z80_|pla_decode_|Equal35~0_combout &
|
|
// (\z80_|execute_|ctl_reg_in_hi~2_combout & ((\z80_|execute_|ctl_mRead~16_combout ))))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal35~0_combout ),
|
|
.datab(\z80_|execute_|ctl_reg_in_hi~2_combout ),
|
|
.datac(\z80_|execute_|ixy_d~6_combout ),
|
|
.datad(\z80_|execute_|ctl_mRead~16_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~32_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~32 .lut_mask = 16'hECA0;
|
|
defparam \z80_|execute_|setM1~32 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y13_N26
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~34 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~34_combout = (\z80_|execute_|setM1~31_combout ) # ((\z80_|execute_|setM1~32_combout ) # ((\z80_|execute_|setM1~33_combout & \z80_|execute_|ixy_d~9_combout )))
|
|
|
|
.dataa(\z80_|execute_|setM1~31_combout ),
|
|
.datab(\z80_|execute_|setM1~33_combout ),
|
|
.datac(\z80_|execute_|ixy_d~9_combout ),
|
|
.datad(\z80_|execute_|setM1~32_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~34_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~34 .lut_mask = 16'hFFEA;
|
|
defparam \z80_|execute_|setM1~34 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y12_N0
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~20 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~20_combout = (\z80_|execute_|ctl_mRead~9_combout & (((\z80_|pla_decode_|Equal37~0_combout & !\z80_|alu_control_|flags_cond_true~q )) # (!\z80_|execute_|ctl_flags_bus~0_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal37~0_combout ),
|
|
.datab(\z80_|alu_control_|flags_cond_true~q ),
|
|
.datac(\z80_|execute_|ctl_mRead~9_combout ),
|
|
.datad(\z80_|execute_|ctl_flags_bus~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~20_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~20 .lut_mask = 16'h20F0;
|
|
defparam \z80_|execute_|setM1~20 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y13_N0
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~21 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~21_combout = (\z80_|execute_|setM1~20_combout ) # ((\z80_|execute_|ixy_d~8_combout & (\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q & \z80_|pla_decode_|Equal10~0_combout )))
|
|
|
|
.dataa(\z80_|execute_|ixy_d~8_combout ),
|
|
.datab(\z80_|alu_flags_|SYNTHESIZED_WIRE_39~q ),
|
|
.datac(\z80_|pla_decode_|Equal10~0_combout ),
|
|
.datad(\z80_|execute_|setM1~20_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~21_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~21 .lut_mask = 16'hFF80;
|
|
defparam \z80_|execute_|setM1~21 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y13_N28
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~35 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~35_combout = (\z80_|execute_|setM1~28_combout ) # ((\z80_|execute_|setM1~55_combout ) # ((\z80_|execute_|setM1~34_combout ) # (\z80_|execute_|setM1~21_combout )))
|
|
|
|
.dataa(\z80_|execute_|setM1~28_combout ),
|
|
.datab(\z80_|execute_|setM1~55_combout ),
|
|
.datac(\z80_|execute_|setM1~34_combout ),
|
|
.datad(\z80_|execute_|setM1~21_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~35_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~35 .lut_mask = 16'hFFFE;
|
|
defparam \z80_|execute_|setM1~35 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y14_N0
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~43 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~43_combout = (!\z80_|execute_|ctl_mWrite~6_combout & (!\z80_|execute_|ctl_ir_we~10_combout & !\z80_|execute_|ctl_ir_we~9_combout ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|execute_|ctl_mWrite~6_combout ),
|
|
.datac(\z80_|execute_|ctl_ir_we~10_combout ),
|
|
.datad(\z80_|execute_|ctl_ir_we~9_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~43_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~43 .lut_mask = 16'h0003;
|
|
defparam \z80_|execute_|setM1~43 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y14_N6
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~44 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~44_combout = (!\z80_|pla_decode_|Equal47~0_combout & (!\z80_|pla_decode_|Equal37~0_combout & (!\z80_|pla_decode_|Equal38~2_combout & \z80_|sequencer_|DFFE_T4_ff~q )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal47~0_combout ),
|
|
.datab(\z80_|pla_decode_|Equal37~0_combout ),
|
|
.datac(\z80_|pla_decode_|Equal38~2_combout ),
|
|
.datad(\z80_|sequencer_|DFFE_T4_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~44_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~44 .lut_mask = 16'h0100;
|
|
defparam \z80_|execute_|setM1~44 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y14_N18
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~45 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~45_combout = (!\z80_|pla_decode_|Equal21~1_combout & (\z80_|execute_|setM1~43_combout & (!\z80_|pla_decode_|Equal48~0_combout & \z80_|execute_|setM1~44_combout )))
|
|
|
|
.dataa(\z80_|pla_decode_|Equal21~1_combout ),
|
|
.datab(\z80_|execute_|setM1~43_combout ),
|
|
.datac(\z80_|pla_decode_|Equal48~0_combout ),
|
|
.datad(\z80_|execute_|setM1~44_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~45_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~45 .lut_mask = 16'h0400;
|
|
defparam \z80_|execute_|setM1~45 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y12_N20
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~46 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~46_combout = (\z80_|execute_|setM1~45_combout & (\z80_|execute_|setM1~42_combout & ((!\z80_|pla_decode_|Equal1~4_combout ) # (!\z80_|pla_decode_|Equal2~1_combout ))))
|
|
|
|
.dataa(\z80_|execute_|setM1~45_combout ),
|
|
.datab(\z80_|pla_decode_|Equal2~1_combout ),
|
|
.datac(\z80_|pla_decode_|Equal1~4_combout ),
|
|
.datad(\z80_|execute_|setM1~42_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~46_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~46 .lut_mask = 16'h2A00;
|
|
defparam \z80_|execute_|setM1~46 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y12_N6
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~52 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~52_combout = (\z80_|execute_|setM1~48_combout & (\z80_|execute_|setM1~46_combout & (\z80_|execute_|setM1~16_combout & \z80_|execute_|setM1~51_combout )))
|
|
|
|
.dataa(\z80_|execute_|setM1~48_combout ),
|
|
.datab(\z80_|execute_|setM1~46_combout ),
|
|
.datac(\z80_|execute_|setM1~16_combout ),
|
|
.datad(\z80_|execute_|setM1~51_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~52_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~52 .lut_mask = 16'h8000;
|
|
defparam \z80_|execute_|setM1~52 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y12_N4
|
|
cycloneive_lcell_comb \z80_|sequencer_|SYNTHESIZED_WIRE_17 (
|
|
// Equation(s):
|
|
// \z80_|sequencer_|SYNTHESIZED_WIRE_17~combout = (\z80_|execute_|setM1~54_combout & (\z80_|sequencer_|DFFE_T5_ff~q & !\z80_|execute_|nextM~14_combout ))
|
|
|
|
.dataa(\z80_|execute_|setM1~54_combout ),
|
|
.datab(gnd),
|
|
.datac(\z80_|sequencer_|DFFE_T5_ff~q ),
|
|
.datad(\z80_|execute_|nextM~14_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .lut_mask = 16'h00A0;
|
|
defparam \z80_|sequencer_|SYNTHESIZED_WIRE_17 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X27_Y12_N5
|
|
dffeas \z80_|sequencer_|T6 (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|sequencer_|SYNTHESIZED_WIRE_17~combout ),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|clk_delay_|hold_clk_iorq~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|sequencer_|T6~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|sequencer_|T6 .is_wysiwyg = "true";
|
|
defparam \z80_|sequencer_|T6 .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y12_N22
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~53 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~53_combout = (\z80_|execute_|setM1~52_combout & ((\z80_|execute_|setM1~41_combout ) # ((\z80_|sequencer_|T6~q & !\z80_|execute_|setM1~42_combout )))) # (!\z80_|execute_|setM1~52_combout & (((\z80_|sequencer_|T6~q &
|
|
// !\z80_|execute_|setM1~42_combout ))))
|
|
|
|
.dataa(\z80_|execute_|setM1~52_combout ),
|
|
.datab(\z80_|execute_|setM1~41_combout ),
|
|
.datac(\z80_|sequencer_|T6~q ),
|
|
.datad(\z80_|execute_|setM1~42_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~53_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~53 .lut_mask = 16'h88F8;
|
|
defparam \z80_|execute_|setM1~53 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y12_N30
|
|
cycloneive_lcell_comb \z80_|execute_|setM1~54 (
|
|
// Equation(s):
|
|
// \z80_|execute_|setM1~54_combout = (!\z80_|execute_|setM1~19_combout & (!\z80_|execute_|setM1~35_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (!\z80_|execute_|setM1~53_combout ))))
|
|
|
|
.dataa(\z80_|execute_|setM1~19_combout ),
|
|
.datab(\z80_|execute_|setM1~35_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.datad(\z80_|execute_|setM1~53_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|execute_|setM1~54_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|execute_|setM1~54 .lut_mask = 16'h1011;
|
|
defparam \z80_|execute_|setM1~54 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X26_Y13_N28
|
|
cycloneive_lcell_comb \z80_|sequencer_|DFFE_M1_ff~0 (
|
|
// Equation(s):
|
|
// \z80_|sequencer_|DFFE_M1_ff~0_combout = (\z80_|execute_|setM1~54_combout & ((\z80_|sequencer_|DFFE_M1_ff~q ) # (\z80_|execute_|nextM~14_combout )))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|execute_|setM1~54_combout ),
|
|
.datac(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.datad(\z80_|execute_|nextM~14_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|sequencer_|DFFE_M1_ff~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|sequencer_|DFFE_M1_ff~0 .lut_mask = 16'hCCC0;
|
|
defparam \z80_|sequencer_|DFFE_M1_ff~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X26_Y13_N29
|
|
dffeas \z80_|sequencer_|DFFE_M1_ff (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|sequencer_|DFFE_M1_ff~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|sequencer_|DFFE_M1_ff .is_wysiwyg = "true";
|
|
defparam \z80_|sequencer_|DFFE_M1_ff .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X52_Y17_N4
|
|
cycloneive_lcell_comb \z80_|resets_|x1~0 (
|
|
// Equation(s):
|
|
// \z80_|resets_|x1~0_combout = !\reset~combout
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\reset~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|resets_|x1~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|resets_|x1~0 .lut_mask = 16'h00FF;
|
|
defparam \z80_|resets_|x1~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X1_Y16_N16
|
|
cycloneive_lcell_comb \z80_|fpga_reset~feeder (
|
|
// Equation(s):
|
|
// \z80_|fpga_reset~feeder_combout = VCC
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\z80_|fpga_reset~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|fpga_reset~feeder .lut_mask = 16'hFFFF;
|
|
defparam \z80_|fpga_reset~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X1_Y16_N17
|
|
dffeas \z80_|fpga_reset (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|fpga_reset~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|fpga_reset~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|fpga_reset .is_wysiwyg = "true";
|
|
defparam \z80_|fpga_reset .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: CLKCTRL_G2
|
|
cycloneive_clkctrl \z80_|fpga_reset~clkctrl (
|
|
.ena(vcc),
|
|
.inclk({vcc,vcc,vcc,\z80_|fpga_reset~q }),
|
|
.clkselect(2'b00),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.outclk(\z80_|fpga_reset~clkctrl_outclk ));
|
|
// synopsys translate_off
|
|
defparam \z80_|fpga_reset~clkctrl .clock_type = "global clock";
|
|
defparam \z80_|fpga_reset~clkctrl .ena_register_mode = "none";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X52_Y17_N5
|
|
dffeas \z80_|resets_|x1 (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|resets_|x1~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|fpga_reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|resets_|x1~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|resets_|x1 .is_wysiwyg = "true";
|
|
defparam \z80_|resets_|x1 .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X52_Y17_N12
|
|
cycloneive_lcell_comb \z80_|resets_|x3 (
|
|
// Equation(s):
|
|
// \z80_|resets_|x3~combout = (\z80_|resets_|x1~q ) # ((!\z80_|sequencer_|DFFE_M1_ff~q & \z80_|sequencer_|DFFE_T2_ff~q ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.datac(\z80_|resets_|x1~q ),
|
|
.datad(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|resets_|x3~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|resets_|x3 .lut_mask = 16'hF3F0;
|
|
defparam \z80_|resets_|x3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X52_Y17_N13
|
|
dffeas \z80_|resets_|SYNTHESIZED_WIRE_12 (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|resets_|x3~combout ),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|fpga_reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .is_wysiwyg = "true";
|
|
defparam \z80_|resets_|SYNTHESIZED_WIRE_12 .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y13_N28
|
|
cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_10~0 (
|
|
// Equation(s):
|
|
// \z80_|resets_|SYNTHESIZED_WIRE_10~0_combout = !\z80_|resets_|SYNTHESIZED_WIRE_12~q
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .lut_mask = 16'h00FF;
|
|
defparam \z80_|resets_|SYNTHESIZED_WIRE_10~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X36_Y13_N29
|
|
dffeas \z80_|resets_|SYNTHESIZED_WIRE_10 (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|resets_|SYNTHESIZED_WIRE_10~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|resets_|SYNTHESIZED_WIRE_10~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .is_wysiwyg = "true";
|
|
defparam \z80_|resets_|SYNTHESIZED_WIRE_10 .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y13_N22
|
|
cycloneive_lcell_comb \z80_|resets_|SYNTHESIZED_WIRE_9~feeder (
|
|
// Equation(s):
|
|
// \z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout = \z80_|resets_|SYNTHESIZED_WIRE_10~q
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|resets_|SYNTHESIZED_WIRE_10~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|resets_|SYNTHESIZED_WIRE_9~feeder .lut_mask = 16'hFF00;
|
|
defparam \z80_|resets_|SYNTHESIZED_WIRE_9~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X36_Y13_N23
|
|
dffeas \z80_|resets_|SYNTHESIZED_WIRE_9 (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|resets_|SYNTHESIZED_WIRE_9~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|resets_|SYNTHESIZED_WIRE_9~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .is_wysiwyg = "true";
|
|
defparam \z80_|resets_|SYNTHESIZED_WIRE_9 .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X36_Y13_N19
|
|
dffeas \z80_|resets_|DFFE_intr_ff3 (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|resets_|SYNTHESIZED_WIRE_9~q ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|resets_|DFFE_intr_ff3~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|resets_|DFFE_intr_ff3 .is_wysiwyg = "true";
|
|
defparam \z80_|resets_|DFFE_intr_ff3 .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y13_N0
|
|
cycloneive_lcell_comb \z80_|resets_|clrpc_int~0 (
|
|
// Equation(s):
|
|
// \z80_|resets_|clrpc_int~0_combout = (\z80_|sequencer_|DFFE_M1_ff~q & (((\z80_|resets_|clrpc_int~q )))) # (!\z80_|sequencer_|DFFE_M1_ff~q & ((\z80_|sequencer_|DFFE_T2_ff~q & (!\z80_|resets_|clrpc_int~q & !\z80_|resets_|x1~q )) #
|
|
// (!\z80_|sequencer_|DFFE_T2_ff~q & (\z80_|resets_|clrpc_int~q ))))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.datab(\z80_|sequencer_|DFFE_T2_ff~q ),
|
|
.datac(\z80_|resets_|clrpc_int~q ),
|
|
.datad(\z80_|resets_|x1~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|resets_|clrpc_int~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|resets_|clrpc_int~0 .lut_mask = 16'hB0B4;
|
|
defparam \z80_|resets_|clrpc_int~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X36_Y13_N1
|
|
dffeas \z80_|resets_|clrpc_int (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|resets_|clrpc_int~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|resets_|clrpc_int~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|resets_|clrpc_int .is_wysiwyg = "true";
|
|
defparam \z80_|resets_|clrpc_int .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y13_N18
|
|
cycloneive_lcell_comb \z80_|resets_|clrpc~0 (
|
|
// Equation(s):
|
|
// \z80_|resets_|clrpc~0_combout = (\z80_|resets_|SYNTHESIZED_WIRE_9~q ) # ((\z80_|resets_|SYNTHESIZED_WIRE_10~q ) # ((\z80_|resets_|DFFE_intr_ff3~q ) # (\z80_|resets_|clrpc_int~q )))
|
|
|
|
.dataa(\z80_|resets_|SYNTHESIZED_WIRE_9~q ),
|
|
.datab(\z80_|resets_|SYNTHESIZED_WIRE_10~q ),
|
|
.datac(\z80_|resets_|DFFE_intr_ff3~q ),
|
|
.datad(\z80_|resets_|clrpc_int~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|resets_|clrpc~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|resets_|clrpc~0 .lut_mask = 16'hFFFE;
|
|
defparam \z80_|resets_|clrpc~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y11_N2
|
|
cycloneive_lcell_comb \z80_|address_latch_|abusz[0] (
|
|
// Equation(s):
|
|
// \z80_|address_latch_|abusz [0] = (!\z80_|resets_|clrpc~0_combout & \z80_|reg_file_|db_lo_as[0]~3_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(\z80_|resets_|clrpc~0_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|reg_file_|db_lo_as[0]~3_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_latch_|abusz [0]),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_latch_|abusz[0] .lut_mask = 16'h3300;
|
|
defparam \z80_|address_latch_|abusz[0] .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y11_N24
|
|
cycloneive_lcell_comb \z80_|address_pins_|DFFE_apin_latch[0]~0 (
|
|
// Equation(s):
|
|
// \z80_|address_pins_|DFFE_apin_latch[0]~0_combout = (\z80_|execute_|ctl_apin_mux~2_combout & ((\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ))) # (!\z80_|execute_|ctl_apin_mux~2_combout & (\z80_|address_latch_|abusz [0]))
|
|
|
|
.dataa(\z80_|address_latch_|abusz [0]),
|
|
.datab(\z80_|execute_|ctl_apin_mux~2_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|address_latch_|b2v_inst_inc_dec|b2v_dual_adder_0|d0_out~combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|address_pins_|DFFE_apin_latch[0]~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[0]~0 .lut_mask = 16'hEE22;
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[0]~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X34_Y11_N25
|
|
dffeas \z80_|address_pins_|DFFE_apin_latch[0] (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|address_pins_|DFFE_apin_latch[0]~0_combout ),
|
|
.asdata(\z80_|address_latch_|Q [0]),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(\z80_|execute_|ctl_apin_mux2~0_combout ),
|
|
.ena(\z80_|pin_control_|bus_ab_pin_we~1_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|address_pins_|DFFE_apin_latch [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[0] .is_wysiwyg = "true";
|
|
defparam \z80_|address_pins_|DFFE_apin_latch[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y14_N20
|
|
cycloneive_lcell_comb \D[0]~47 (
|
|
// Equation(s):
|
|
// \D[0]~47_combout = (\Equal2~0_combout & (\D[0]~44_combout )) # (!\Equal2~0_combout & ((\D[0]~83_combout )))
|
|
|
|
.dataa(\Equal2~0_combout ),
|
|
.datab(\D[0]~44_combout ),
|
|
.datac(\D[0]~83_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\D[0]~47_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[0]~47 .lut_mask = 16'hD8D8;
|
|
defparam \D[0]~47 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y14_N24
|
|
cycloneive_lcell_comb \D[0]~48 (
|
|
// Equation(s):
|
|
// \D[0]~48_combout = (\z80_|data_pins_|dout [0] & (((\D[0]~47_combout ) # (!\Equal2~1_combout )))) # (!\z80_|data_pins_|dout [0] & (!\z80_|pin_control_|bus_db_pin_oe~15_combout & ((\D[0]~47_combout ) # (!\Equal2~1_combout ))))
|
|
|
|
.dataa(\z80_|data_pins_|dout [0]),
|
|
.datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ),
|
|
.datac(\Equal2~1_combout ),
|
|
.datad(\D[0]~47_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[0]~48_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[0]~48 .lut_mask = 16'hBB0B;
|
|
defparam \D[0]~48 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y10_N12
|
|
cycloneive_lcell_comb \D[1]~49 (
|
|
// Equation(s):
|
|
// \D[1]~49_combout = (\Equal2~0_combout & (\D[1]~30_combout )) # (!\Equal2~0_combout & ((\D[1]~81_combout )))
|
|
|
|
.dataa(\D[1]~30_combout ),
|
|
.datab(gnd),
|
|
.datac(\Equal2~0_combout ),
|
|
.datad(\D[1]~81_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[1]~49_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[1]~49 .lut_mask = 16'hAFA0;
|
|
defparam \D[1]~49 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y10_N18
|
|
cycloneive_lcell_comb \D[1]~50 (
|
|
// Equation(s):
|
|
// \D[1]~50_combout = (\Equal2~1_combout & (\D[1]~49_combout & ((\z80_|data_pins_|dout [1]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) # (!\Equal2~1_combout & ((\z80_|data_pins_|dout [1]) # ((!\z80_|pin_control_|bus_db_pin_oe~15_combout ))))
|
|
|
|
.dataa(\Equal2~1_combout ),
|
|
.datab(\z80_|data_pins_|dout [1]),
|
|
.datac(\z80_|pin_control_|bus_db_pin_oe~15_combout ),
|
|
.datad(\D[1]~49_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[1]~50_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[1]~50 .lut_mask = 16'hCF45;
|
|
defparam \D[1]~50 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y10_N2
|
|
cycloneive_lcell_comb \D[2]~51 (
|
|
// Equation(s):
|
|
// \D[2]~51_combout = (\Equal2~0_combout & (\D[2]~37_combout )) # (!\Equal2~0_combout & ((\D[2]~82_combout )))
|
|
|
|
.dataa(\D[2]~37_combout ),
|
|
.datab(gnd),
|
|
.datac(\Equal2~0_combout ),
|
|
.datad(\D[2]~82_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[2]~51_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[2]~51 .lut_mask = 16'hAFA0;
|
|
defparam \D[2]~51 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y10_N2
|
|
cycloneive_lcell_comb \D[2]~52 (
|
|
// Equation(s):
|
|
// \D[2]~52_combout = (\z80_|data_pins_|dout [2] & (((\D[2]~51_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [2] & (!\z80_|pin_control_|bus_db_pin_oe~15_combout & ((\D[2]~51_combout ) # (!\Equal2~1_combout ))))
|
|
|
|
.dataa(\z80_|data_pins_|dout [2]),
|
|
.datab(\Equal2~1_combout ),
|
|
.datac(\z80_|pin_control_|bus_db_pin_oe~15_combout ),
|
|
.datad(\D[2]~51_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[2]~52_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[2]~52 .lut_mask = 16'hAF23;
|
|
defparam \D[2]~52 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y14_N18
|
|
cycloneive_lcell_comb \D[3]~58 (
|
|
// Equation(s):
|
|
// \D[3]~58_combout = (\Equal2~0_combout & (\D[3]~57_combout )) # (!\Equal2~0_combout & ((\D[3]~85_combout )))
|
|
|
|
.dataa(\Equal2~0_combout ),
|
|
.datab(\D[3]~57_combout ),
|
|
.datac(gnd),
|
|
.datad(\D[3]~85_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[3]~58_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[3]~58 .lut_mask = 16'hDD88;
|
|
defparam \D[3]~58 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y14_N18
|
|
cycloneive_lcell_comb \D[3]~59 (
|
|
// Equation(s):
|
|
// \D[3]~59_combout = (\z80_|data_pins_|dout [3] & (((\D[3]~58_combout ) # (!\Equal2~1_combout )))) # (!\z80_|data_pins_|dout [3] & (!\z80_|pin_control_|bus_db_pin_oe~15_combout & ((\D[3]~58_combout ) # (!\Equal2~1_combout ))))
|
|
|
|
.dataa(\z80_|data_pins_|dout [3]),
|
|
.datab(\z80_|pin_control_|bus_db_pin_oe~15_combout ),
|
|
.datac(\Equal2~1_combout ),
|
|
.datad(\D[3]~58_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[3]~59_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[3]~59 .lut_mask = 16'hBB0B;
|
|
defparam \D[3]~59 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y10_N0
|
|
cycloneive_lcell_comb \D[4]~65 (
|
|
// Equation(s):
|
|
// \D[4]~65_combout = (\Equal2~0_combout & (\D[4]~64_combout )) # (!\Equal2~0_combout & ((\D[4]~86_combout )))
|
|
|
|
.dataa(gnd),
|
|
.datab(\D[4]~64_combout ),
|
|
.datac(\Equal2~0_combout ),
|
|
.datad(\D[4]~86_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[4]~65_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[4]~65 .lut_mask = 16'hCFC0;
|
|
defparam \D[4]~65 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y10_N22
|
|
cycloneive_lcell_comb \D[4]~66 (
|
|
// Equation(s):
|
|
// \D[4]~66_combout = (\Equal2~1_combout & (\D[4]~65_combout & ((\z80_|data_pins_|dout [4]) # (!\z80_|pin_control_|bus_db_pin_oe~15_combout )))) # (!\Equal2~1_combout & ((\z80_|data_pins_|dout [4]) # ((!\z80_|pin_control_|bus_db_pin_oe~15_combout ))))
|
|
|
|
.dataa(\Equal2~1_combout ),
|
|
.datab(\z80_|data_pins_|dout [4]),
|
|
.datac(\z80_|pin_control_|bus_db_pin_oe~15_combout ),
|
|
.datad(\D[4]~65_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[4]~66_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[4]~66 .lut_mask = 16'hCF45;
|
|
defparam \D[4]~66 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y10_N20
|
|
cycloneive_lcell_comb \D[6]~70 (
|
|
// Equation(s):
|
|
// \D[6]~70_combout = (\Equal2~0_combout & ((\D[6]~69_combout ))) # (!\Equal2~0_combout & (\D[6]~88_combout ))
|
|
|
|
.dataa(\Equal2~0_combout ),
|
|
.datab(gnd),
|
|
.datac(\D[6]~88_combout ),
|
|
.datad(\D[6]~69_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[6]~70_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[6]~70 .lut_mask = 16'hFA50;
|
|
defparam \D[6]~70 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y10_N10
|
|
cycloneive_lcell_comb \D[6]~71 (
|
|
// Equation(s):
|
|
// \D[6]~71_combout = (\z80_|data_pins_|dout [6] & (((\D[6]~70_combout )) # (!\Equal2~1_combout ))) # (!\z80_|data_pins_|dout [6] & (!\z80_|pin_control_|bus_db_pin_oe~15_combout & ((\D[6]~70_combout ) # (!\Equal2~1_combout ))))
|
|
|
|
.dataa(\z80_|data_pins_|dout [6]),
|
|
.datab(\Equal2~1_combout ),
|
|
.datac(\z80_|pin_control_|bus_db_pin_oe~15_combout ),
|
|
.datad(\D[6]~70_combout ),
|
|
.cin(gnd),
|
|
.combout(\D[6]~71_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \D[6]~71 .lut_mask = 16'hAF23;
|
|
defparam \D[6]~71 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y13_N28
|
|
cycloneive_lcell_comb \z80_|nM1_int~3 (
|
|
// Equation(s):
|
|
// \z80_|nM1_int~3_combout = (\z80_|execute_|setM1~54_combout & ((\z80_|sequencer_|DFFE_T1_ff~q ) # (\z80_|sequencer_|DFFE_M1_ff~q )))
|
|
|
|
.dataa(\z80_|sequencer_|DFFE_T1_ff~q ),
|
|
.datab(\z80_|execute_|setM1~54_combout ),
|
|
.datac(gnd),
|
|
.datad(\z80_|sequencer_|DFFE_M1_ff~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|nM1_int~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|nM1_int~3 .lut_mask = 16'hCC88;
|
|
defparam \z80_|nM1_int~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X27_Y13_N29
|
|
dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|nM1_int~3_combout ),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|clk_delay_|hold_clk_iorq~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 .is_wysiwyg = "true";
|
|
defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_16 .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y11_N4
|
|
cycloneive_lcell_comb \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder (
|
|
// Equation(s):
|
|
// \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder .lut_mask = 16'hFF00;
|
|
defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X27_Y11_N5
|
|
dffeas \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|clk_delay_|hold_clk_iorq~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 .is_wysiwyg = "true";
|
|
defparam \z80_|memory_ifc_|SYNTHESIZED_WIRE_17 .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X27_Y11_N11
|
|
dffeas \z80_|memory_ifc_|DFFE_mreq_ff2 (
|
|
.clk(!\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q ),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|clk_delay_|hold_clk_iorq~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|memory_ifc_|DFFE_mreq_ff2~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|memory_ifc_|DFFE_mreq_ff2 .is_wysiwyg = "true";
|
|
defparam \z80_|memory_ifc_|DFFE_mreq_ff2 .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y11_N10
|
|
cycloneive_lcell_comb \z80_|memory_ifc_|nMREQ_out~0 (
|
|
// Equation(s):
|
|
// \z80_|memory_ifc_|nMREQ_out~0_combout = (\z80_|memory_ifc_|wait_mwr~q ) # ((\z80_|memory_ifc_|mwr_wr~q ) # ((\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q & !\z80_|memory_ifc_|DFFE_mreq_ff2~q )))
|
|
|
|
.dataa(\z80_|memory_ifc_|wait_mwr~q ),
|
|
.datab(\z80_|memory_ifc_|SYNTHESIZED_WIRE_17~q ),
|
|
.datac(\z80_|memory_ifc_|DFFE_mreq_ff2~q ),
|
|
.datad(\z80_|memory_ifc_|mwr_wr~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|memory_ifc_|nMREQ_out~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|memory_ifc_|nMREQ_out~0 .lut_mask = 16'hFFAE;
|
|
defparam \z80_|memory_ifc_|nMREQ_out~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y11_N16
|
|
cycloneive_lcell_comb \z80_|memory_ifc_|nMREQ_out~1 (
|
|
// Equation(s):
|
|
// \z80_|memory_ifc_|nMREQ_out~1_combout = (!\z80_|memory_ifc_|wait_mrd~q & (!\z80_|memory_ifc_|nRD_out~0_combout & (!\z80_|memory_ifc_|DFFE_mrd_ff3~q & !\z80_|memory_ifc_|nMREQ_out~0_combout )))
|
|
|
|
.dataa(\z80_|memory_ifc_|wait_mrd~q ),
|
|
.datab(\z80_|memory_ifc_|nRD_out~0_combout ),
|
|
.datac(\z80_|memory_ifc_|DFFE_mrd_ff3~q ),
|
|
.datad(\z80_|memory_ifc_|nMREQ_out~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\z80_|memory_ifc_|nMREQ_out~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|memory_ifc_|nMREQ_out~1 .lut_mask = 16'h0001;
|
|
defparam \z80_|memory_ifc_|nMREQ_out~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: CLKCTRL_G19
|
|
cycloneive_clkctrl \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl (
|
|
.ena(vcc),
|
|
.inclk({vcc,vcc,vcc,\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk [2]}),
|
|
.clkselect(2'b00),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.outclk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ));
|
|
// synopsys translate_off
|
|
defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .clock_type = "global clock";
|
|
defparam \ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .ena_register_mode = "none";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X3_Y23_N28
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~feeder (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|state.Idle~feeder_combout = VCC
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|state.Idle~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|state.Idle~feeder .lut_mask = 16'hFFFF;
|
|
defparam \ula_|i2c_loader_|state.Idle~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X1_Y24_N22
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|divider[0]~15 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|divider[0]~15_combout = !\ula_|i2c_loader_|divider [0]
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\ula_|i2c_loader_|divider [0]),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|divider[0]~15_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|divider[0]~15 .lut_mask = 16'h0F0F;
|
|
defparam \ula_|i2c_loader_|divider[0]~15 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X1_Y24_N23
|
|
dffeas \ula_|i2c_loader_|divider[0] (
|
|
.clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2c_loader_|divider[0]~15_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2c_loader_|divider [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|divider[0] .is_wysiwyg = "true";
|
|
defparam \ula_|i2c_loader_|divider[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X1_Y24_N0
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|divider[1]~5 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|divider[1]~5_combout = (\ula_|i2c_loader_|divider [0] & (\ula_|i2c_loader_|divider [1] $ (VCC))) # (!\ula_|i2c_loader_|divider [0] & (\ula_|i2c_loader_|divider [1] & VCC))
|
|
// \ula_|i2c_loader_|divider[1]~6 = CARRY((\ula_|i2c_loader_|divider [0] & \ula_|i2c_loader_|divider [1]))
|
|
|
|
.dataa(\ula_|i2c_loader_|divider [0]),
|
|
.datab(\ula_|i2c_loader_|divider [1]),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|divider[1]~5_combout ),
|
|
.cout(\ula_|i2c_loader_|divider[1]~6 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|divider[1]~5 .lut_mask = 16'h6688;
|
|
defparam \ula_|i2c_loader_|divider[1]~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X1_Y24_N1
|
|
dffeas \ula_|i2c_loader_|divider[1] (
|
|
.clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2c_loader_|divider[1]~5_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2c_loader_|divider [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|divider[1] .is_wysiwyg = "true";
|
|
defparam \ula_|i2c_loader_|divider[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X1_Y24_N2
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|divider[2]~7 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|divider[2]~7_combout = (\ula_|i2c_loader_|divider [2] & (!\ula_|i2c_loader_|divider[1]~6 )) # (!\ula_|i2c_loader_|divider [2] & ((\ula_|i2c_loader_|divider[1]~6 ) # (GND)))
|
|
// \ula_|i2c_loader_|divider[2]~8 = CARRY((!\ula_|i2c_loader_|divider[1]~6 ) # (!\ula_|i2c_loader_|divider [2]))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|i2c_loader_|divider [2]),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\ula_|i2c_loader_|divider[1]~6 ),
|
|
.combout(\ula_|i2c_loader_|divider[2]~7_combout ),
|
|
.cout(\ula_|i2c_loader_|divider[2]~8 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|divider[2]~7 .lut_mask = 16'h3C3F;
|
|
defparam \ula_|i2c_loader_|divider[2]~7 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X1_Y24_N3
|
|
dffeas \ula_|i2c_loader_|divider[2] (
|
|
.clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2c_loader_|divider[2]~7_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2c_loader_|divider [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|divider[2] .is_wysiwyg = "true";
|
|
defparam \ula_|i2c_loader_|divider[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X1_Y24_N4
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|divider[3]~9 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|divider[3]~9_combout = (\ula_|i2c_loader_|divider [3] & (\ula_|i2c_loader_|divider[2]~8 $ (GND))) # (!\ula_|i2c_loader_|divider [3] & (!\ula_|i2c_loader_|divider[2]~8 & VCC))
|
|
// \ula_|i2c_loader_|divider[3]~10 = CARRY((\ula_|i2c_loader_|divider [3] & !\ula_|i2c_loader_|divider[2]~8 ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|i2c_loader_|divider [3]),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\ula_|i2c_loader_|divider[2]~8 ),
|
|
.combout(\ula_|i2c_loader_|divider[3]~9_combout ),
|
|
.cout(\ula_|i2c_loader_|divider[3]~10 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|divider[3]~9 .lut_mask = 16'hC30C;
|
|
defparam \ula_|i2c_loader_|divider[3]~9 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X1_Y24_N5
|
|
dffeas \ula_|i2c_loader_|divider[3] (
|
|
.clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2c_loader_|divider[3]~9_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2c_loader_|divider [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|divider[3] .is_wysiwyg = "true";
|
|
defparam \ula_|i2c_loader_|divider[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X1_Y24_N12
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|WideAnd0~0 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|WideAnd0~0_combout = (((!\ula_|i2c_loader_|divider [2]) # (!\ula_|i2c_loader_|divider [3])) # (!\ula_|i2c_loader_|divider [1])) # (!\ula_|i2c_loader_|divider [0])
|
|
|
|
.dataa(\ula_|i2c_loader_|divider [0]),
|
|
.datab(\ula_|i2c_loader_|divider [1]),
|
|
.datac(\ula_|i2c_loader_|divider [3]),
|
|
.datad(\ula_|i2c_loader_|divider [2]),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|WideAnd0~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|WideAnd0~0 .lut_mask = 16'h7FFF;
|
|
defparam \ula_|i2c_loader_|WideAnd0~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X1_Y24_N6
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|divider[4]~11 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|divider[4]~11_combout = (\ula_|i2c_loader_|divider [4] & (!\ula_|i2c_loader_|divider[3]~10 )) # (!\ula_|i2c_loader_|divider [4] & ((\ula_|i2c_loader_|divider[3]~10 ) # (GND)))
|
|
// \ula_|i2c_loader_|divider[4]~12 = CARRY((!\ula_|i2c_loader_|divider[3]~10 ) # (!\ula_|i2c_loader_|divider [4]))
|
|
|
|
.dataa(\ula_|i2c_loader_|divider [4]),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\ula_|i2c_loader_|divider[3]~10 ),
|
|
.combout(\ula_|i2c_loader_|divider[4]~11_combout ),
|
|
.cout(\ula_|i2c_loader_|divider[4]~12 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|divider[4]~11 .lut_mask = 16'h5A5F;
|
|
defparam \ula_|i2c_loader_|divider[4]~11 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X1_Y24_N7
|
|
dffeas \ula_|i2c_loader_|divider[4] (
|
|
.clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2c_loader_|divider[4]~11_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2c_loader_|divider [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|divider[4] .is_wysiwyg = "true";
|
|
defparam \ula_|i2c_loader_|divider[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X1_Y24_N8
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|divider[5]~13 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|divider[5]~13_combout = \ula_|i2c_loader_|divider [5] $ (!\ula_|i2c_loader_|divider[4]~12 )
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|i2c_loader_|divider [5]),
|
|
.datac(gnd),
|
|
.datad(gnd),
|
|
.cin(\ula_|i2c_loader_|divider[4]~12 ),
|
|
.combout(\ula_|i2c_loader_|divider[5]~13_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|divider[5]~13 .lut_mask = 16'hC3C3;
|
|
defparam \ula_|i2c_loader_|divider[5]~13 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X1_Y24_N9
|
|
dffeas \ula_|i2c_loader_|divider[5] (
|
|
.clk(!\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2c_loader_|divider[5]~13_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2c_loader_|divider [5]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|divider[5] .is_wysiwyg = "true";
|
|
defparam \ula_|i2c_loader_|divider[5] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X1_Y24_N30
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|WideAnd0 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|WideAnd0~combout = (\ula_|i2c_loader_|WideAnd0~0_combout ) # ((!\ula_|i2c_loader_|divider [4]) # (!\ula_|i2c_loader_|divider [5]))
|
|
|
|
.dataa(\ula_|i2c_loader_|WideAnd0~0_combout ),
|
|
.datab(gnd),
|
|
.datac(\ula_|i2c_loader_|divider [5]),
|
|
.datad(\ula_|i2c_loader_|divider [4]),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|WideAnd0~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|WideAnd0 .lut_mask = 16'hAFFF;
|
|
defparam \ula_|i2c_loader_|WideAnd0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X3_Y23_N29
|
|
dffeas \ula_|i2c_loader_|state.Idle (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2c_loader_|state.Idle~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(!\ula_|i2c_loader_|WideAnd0~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2c_loader_|state.Idle~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|state.Idle .is_wysiwyg = "true";
|
|
defparam \ula_|i2c_loader_|state.Idle .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X3_Y23_N0
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|phase~0 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|phase~0_combout = (!\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|state.Idle~q )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\ula_|i2c_loader_|phase [0]),
|
|
.datad(\ula_|i2c_loader_|state.Idle~q ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|phase~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|phase~0 .lut_mask = 16'h0F00;
|
|
defparam \ula_|i2c_loader_|phase~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X3_Y23_N1
|
|
dffeas \ula_|i2c_loader_|phase[0] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2c_loader_|phase~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(!\ula_|i2c_loader_|WideAnd0~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2c_loader_|phase [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|phase[0] .is_wysiwyg = "true";
|
|
defparam \ula_|i2c_loader_|phase[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X3_Y23_N2
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|phase~1 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|phase~1_combout = (\ula_|i2c_loader_|state.Idle~q & (\ula_|i2c_loader_|phase [0] $ (\ula_|i2c_loader_|phase [1])))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|i2c_loader_|phase [0]),
|
|
.datac(\ula_|i2c_loader_|phase [1]),
|
|
.datad(\ula_|i2c_loader_|state.Idle~q ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|phase~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|phase~1 .lut_mask = 16'h3C00;
|
|
defparam \ula_|i2c_loader_|phase~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X3_Y23_N3
|
|
dffeas \ula_|i2c_loader_|phase[1] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2c_loader_|phase~1_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(!\ula_|i2c_loader_|WideAnd0~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2c_loader_|phase [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|phase[1] .is_wysiwyg = "true";
|
|
defparam \ula_|i2c_loader_|phase[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X2_Y24_N2
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|nbit~5 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|nbit~5_combout = (!\ula_|i2c_loader_|state.Data~q ) # (!\ula_|i2c_loader_|nbit [0])
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\ula_|i2c_loader_|nbit [0]),
|
|
.datad(\ula_|i2c_loader_|state.Data~q ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|nbit~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|nbit~5 .lut_mask = 16'h0FFF;
|
|
defparam \ula_|i2c_loader_|nbit~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X2_Y23_N16
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|state.Idle~0 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|state.Idle~0_combout = (!\ula_|i2c_loader_|state.Stop~q & (!\ula_|i2c_loader_|state.Ack~q & (!\ula_|i2c_loader_|state.Start~q & !\ula_|i2c_loader_|state.Pause~q )))
|
|
|
|
.dataa(\ula_|i2c_loader_|state.Stop~q ),
|
|
.datab(\ula_|i2c_loader_|state.Ack~q ),
|
|
.datac(\ula_|i2c_loader_|state.Start~q ),
|
|
.datad(\ula_|i2c_loader_|state.Pause~q ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|state.Idle~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|state.Idle~0 .lut_mask = 16'h0001;
|
|
defparam \ula_|i2c_loader_|state.Idle~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X1_Y23_N30
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|Mux42~0 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|Mux42~0_combout = (\ula_|i2c_loader_|phase [1] & \ula_|i2c_loader_|phase [0])
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|i2c_loader_|phase [1]),
|
|
.datac(\ula_|i2c_loader_|phase [0]),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|Mux42~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|Mux42~0 .lut_mask = 16'hC0C0;
|
|
defparam \ula_|i2c_loader_|Mux42~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X2_Y24_N0
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|nbit~6 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|nbit~6_combout = (\ula_|i2c_loader_|nbit [1] $ (!\ula_|i2c_loader_|nbit [0])) # (!\ula_|i2c_loader_|state.Data~q )
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|i2c_loader_|state.Data~q ),
|
|
.datac(\ula_|i2c_loader_|nbit [1]),
|
|
.datad(\ula_|i2c_loader_|nbit [0]),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|nbit~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|nbit~6 .lut_mask = 16'hF33F;
|
|
defparam \ula_|i2c_loader_|nbit~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X2_Y24_N1
|
|
dffeas \ula_|i2c_loader_|nbit[1] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2c_loader_|nbit~6_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|i2c_loader_|nbit[0]~4_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2c_loader_|nbit [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|nbit[1] .is_wysiwyg = "true";
|
|
defparam \ula_|i2c_loader_|nbit[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X2_Y24_N30
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~0 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|state.Done~0_combout = (!\ula_|i2c_loader_|nbit [2] & (!\ula_|i2c_loader_|nbit [0] & (\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|nbit [1])))
|
|
|
|
.dataa(\ula_|i2c_loader_|nbit [2]),
|
|
.datab(\ula_|i2c_loader_|nbit [0]),
|
|
.datac(\ula_|i2c_loader_|state.Data~q ),
|
|
.datad(\ula_|i2c_loader_|nbit [1]),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|state.Done~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|state.Done~0 .lut_mask = 16'h0010;
|
|
defparam \ula_|i2c_loader_|state.Done~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X2_Y23_N18
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~0 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|state.Ack~0_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Done~0_combout ) # (!\ula_|i2c_loader_|state.Idle~0_combout )))) # (!\ula_|i2c_loader_|state.Idle~q )
|
|
|
|
.dataa(\ula_|i2c_loader_|state.Idle~0_combout ),
|
|
.datab(\ula_|i2c_loader_|Mux42~0_combout ),
|
|
.datac(\ula_|i2c_loader_|state.Done~0_combout ),
|
|
.datad(\ula_|i2c_loader_|state.Idle~q ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|state.Ack~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|state.Ack~0 .lut_mask = 16'hC4FF;
|
|
defparam \ula_|i2c_loader_|state.Ack~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X2_Y23_N24
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|state.Ack~1 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|state.Ack~1_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Ack~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Ack~0_combout & (\ula_|i2c_loader_|state.Data~q )) #
|
|
// (!\ula_|i2c_loader_|state.Ack~0_combout & ((\ula_|i2c_loader_|state.Ack~q )))))
|
|
|
|
.dataa(\ula_|i2c_loader_|WideAnd0~combout ),
|
|
.datab(\ula_|i2c_loader_|state.Data~q ),
|
|
.datac(\ula_|i2c_loader_|state.Ack~q ),
|
|
.datad(\ula_|i2c_loader_|state.Ack~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|state.Ack~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|state.Ack~1 .lut_mask = 16'hE4F0;
|
|
defparam \ula_|i2c_loader_|state.Ack~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X2_Y23_N25
|
|
dffeas \ula_|i2c_loader_|state.Ack (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2c_loader_|state.Ack~1_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2c_loader_|state.Ack~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|state.Ack .is_wysiwyg = "true";
|
|
defparam \ula_|i2c_loader_|state.Ack .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X1_Y23_N2
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~2 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|nbit[0]~2_combout = (\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|phase [0])) # (!\ula_|i2c_loader_|phase [1]))) # (!\ula_|i2c_loader_|state.Data~q & (((!\ula_|i2c_loader_|state.Ack~q ))))
|
|
|
|
.dataa(\ula_|i2c_loader_|phase [1]),
|
|
.datab(\ula_|i2c_loader_|state.Ack~q ),
|
|
.datac(\ula_|i2c_loader_|phase [0]),
|
|
.datad(\ula_|i2c_loader_|state.Data~q ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|nbit[0]~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|nbit[0]~2 .lut_mask = 16'h5F33;
|
|
defparam \ula_|i2c_loader_|nbit[0]~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X2_Y23_N26
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~4 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|nbyte~4_combout = (\ula_|i2c_loader_|state.Start~q ) # ((\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|nbyte [0] $ (!\ula_|i2c_loader_|nbyte [1]))))
|
|
|
|
.dataa(\ula_|i2c_loader_|nbyte [0]),
|
|
.datab(\ula_|i2c_loader_|phase [0]),
|
|
.datac(\ula_|i2c_loader_|nbyte [1]),
|
|
.datad(\ula_|i2c_loader_|state.Start~q ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|nbyte~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|nbyte~4 .lut_mask = 16'hFF84;
|
|
defparam \ula_|i2c_loader_|nbyte~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X1_Y23_N4
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~7 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|thisbyte[0]~7_combout = (\ula_|i2c_loader_|state.Ack~q & \ula_|i2c_loader_|phase [1])
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|i2c_loader_|state.Ack~q ),
|
|
.datac(\ula_|i2c_loader_|phase [1]),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|thisbyte[0]~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|thisbyte[0]~7 .lut_mask = 16'hC0C0;
|
|
defparam \ula_|i2c_loader_|thisbyte[0]~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOIBUF_X0_Y23_N1
|
|
cycloneive_io_ibuf \I2C_SDAT~input (
|
|
.i(I2C_SDAT),
|
|
.ibar(gnd),
|
|
.o(\I2C_SDAT~input_o ));
|
|
// synopsys translate_off
|
|
defparam \I2C_SDAT~input .bus_hold = "false";
|
|
defparam \I2C_SDAT~input .simulate_z_as = "z";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X2_Y23_N20
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~1 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|nbyte[0]~1_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [1]) # ((\ula_|i2c_loader_|nbyte [0])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o ))))
|
|
|
|
.dataa(\ula_|i2c_loader_|nbyte [1]),
|
|
.datab(\ula_|i2c_loader_|nbyte [0]),
|
|
.datac(\ula_|i2c_loader_|phase [0]),
|
|
.datad(\I2C_SDAT~input_o ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|nbyte[0]~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|nbyte[0]~1 .lut_mask = 16'hEFE0;
|
|
defparam \ula_|i2c_loader_|nbyte[0]~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X2_Y23_N10
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~2 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|nbyte[0]~2_combout = (\ula_|i2c_loader_|state.Start~q & (\ula_|i2c_loader_|Mux42~0_combout )) # (!\ula_|i2c_loader_|state.Start~q & (((\ula_|i2c_loader_|thisbyte[0]~7_combout & \ula_|i2c_loader_|nbyte[0]~1_combout ))))
|
|
|
|
.dataa(\ula_|i2c_loader_|state.Start~q ),
|
|
.datab(\ula_|i2c_loader_|Mux42~0_combout ),
|
|
.datac(\ula_|i2c_loader_|thisbyte[0]~7_combout ),
|
|
.datad(\ula_|i2c_loader_|nbyte[0]~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|nbyte[0]~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|nbyte[0]~2 .lut_mask = 16'hD888;
|
|
defparam \ula_|i2c_loader_|nbyte[0]~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X2_Y23_N8
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[0]~3 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|nbyte[0]~3_combout = (\ula_|i2c_loader_|state.Idle~q & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|nbyte[0]~2_combout ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|i2c_loader_|state.Idle~q ),
|
|
.datac(\ula_|i2c_loader_|WideAnd0~combout ),
|
|
.datad(\ula_|i2c_loader_|nbyte[0]~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|nbyte[0]~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|nbyte[0]~3 .lut_mask = 16'h0C00;
|
|
defparam \ula_|i2c_loader_|nbyte[0]~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X2_Y23_N27
|
|
dffeas \ula_|i2c_loader_|nbyte[1] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2c_loader_|nbyte~4_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|i2c_loader_|nbyte[0]~3_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2c_loader_|nbyte [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|nbyte[1] .is_wysiwyg = "true";
|
|
defparam \ula_|i2c_loader_|nbyte[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X2_Y23_N28
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~1 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|nbit[0]~1_combout = (!\ula_|i2c_loader_|nbyte [1] & (!\ula_|i2c_loader_|nbyte [0] & !\ula_|i2c_loader_|state.Data~q ))
|
|
|
|
.dataa(\ula_|i2c_loader_|nbyte [1]),
|
|
.datab(\ula_|i2c_loader_|nbyte [0]),
|
|
.datac(\ula_|i2c_loader_|state.Data~q ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|nbit[0]~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|nbit[0]~1 .lut_mask = 16'h0101;
|
|
defparam \ula_|i2c_loader_|nbit[0]~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X2_Y23_N30
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~3 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|nbit[0]~3_combout = (!\ula_|i2c_loader_|state.Start~q & ((\ula_|i2c_loader_|nbit[0]~2_combout ) # ((\ula_|i2c_loader_|nbit[0]~1_combout ) # (\ula_|i2c_loader_|state.Done~0_combout ))))
|
|
|
|
.dataa(\ula_|i2c_loader_|nbit[0]~2_combout ),
|
|
.datab(\ula_|i2c_loader_|nbit[0]~1_combout ),
|
|
.datac(\ula_|i2c_loader_|state.Done~0_combout ),
|
|
.datad(\ula_|i2c_loader_|state.Start~q ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|nbit[0]~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|nbit[0]~3 .lut_mask = 16'h00FE;
|
|
defparam \ula_|i2c_loader_|nbit[0]~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X2_Y23_N0
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|nbit[0]~4 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|nbit[0]~4_combout = (!\ula_|i2c_loader_|nbit[0]~3_combout & (\ula_|i2c_loader_|Mux42~0_combout & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|state.Idle~q )))
|
|
|
|
.dataa(\ula_|i2c_loader_|nbit[0]~3_combout ),
|
|
.datab(\ula_|i2c_loader_|Mux42~0_combout ),
|
|
.datac(\ula_|i2c_loader_|WideAnd0~combout ),
|
|
.datad(\ula_|i2c_loader_|state.Idle~q ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|nbit[0]~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|nbit[0]~4 .lut_mask = 16'h0400;
|
|
defparam \ula_|i2c_loader_|nbit[0]~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X2_Y24_N3
|
|
dffeas \ula_|i2c_loader_|nbit[0] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2c_loader_|nbit~5_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|i2c_loader_|nbit[0]~4_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2c_loader_|nbit [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|nbit[0] .is_wysiwyg = "true";
|
|
defparam \ula_|i2c_loader_|nbit[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X2_Y24_N12
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|nbit~0 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|nbit~0_combout = (\ula_|i2c_loader_|nbit [2] $ (((!\ula_|i2c_loader_|nbit [0] & !\ula_|i2c_loader_|nbit [1])))) # (!\ula_|i2c_loader_|state.Data~q )
|
|
|
|
.dataa(\ula_|i2c_loader_|state.Data~q ),
|
|
.datab(\ula_|i2c_loader_|nbit [0]),
|
|
.datac(\ula_|i2c_loader_|nbit [2]),
|
|
.datad(\ula_|i2c_loader_|nbit [1]),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|nbit~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|nbit~0 .lut_mask = 16'hF5D7;
|
|
defparam \ula_|i2c_loader_|nbit~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X2_Y24_N13
|
|
dffeas \ula_|i2c_loader_|nbit[2] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2c_loader_|nbit~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|i2c_loader_|nbit[0]~4_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2c_loader_|nbit [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|nbit[2] .is_wysiwyg = "true";
|
|
defparam \ula_|i2c_loader_|nbit[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X2_Y24_N28
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~1 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|state.Done~1_combout = (!\ula_|i2c_loader_|nbit [2] & (!\ula_|i2c_loader_|nbit [0] & !\ula_|i2c_loader_|nbit [1]))
|
|
|
|
.dataa(\ula_|i2c_loader_|nbit [2]),
|
|
.datab(\ula_|i2c_loader_|nbit [0]),
|
|
.datac(gnd),
|
|
.datad(\ula_|i2c_loader_|nbit [1]),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|state.Done~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|state.Done~1 .lut_mask = 16'h0011;
|
|
defparam \ula_|i2c_loader_|state.Done~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X1_Y23_N18
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|state~27 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|state~27_combout = ((!\ula_|i2c_loader_|state.Done~1_combout ) # (!\ula_|i2c_loader_|phase [0])) # (!\ula_|i2c_loader_|phase [1])
|
|
|
|
.dataa(\ula_|i2c_loader_|phase [1]),
|
|
.datab(\ula_|i2c_loader_|phase [0]),
|
|
.datac(\ula_|i2c_loader_|state.Done~1_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|state~27_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|state~27 .lut_mask = 16'h7F7F;
|
|
defparam \ula_|i2c_loader_|state~27 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X2_Y23_N14
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|state~24 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|state~24_combout = (\ula_|i2c_loader_|state.Ack~q & ((\ula_|i2c_loader_|nbyte [0]) # (\ula_|i2c_loader_|nbyte [1])))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|i2c_loader_|nbyte [0]),
|
|
.datac(\ula_|i2c_loader_|nbyte [1]),
|
|
.datad(\ula_|i2c_loader_|state.Ack~q ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|state~24_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|state~24 .lut_mask = 16'hFC00;
|
|
defparam \ula_|i2c_loader_|state~24 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X2_Y23_N2
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|state~26 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|state~26_combout = (\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|state~24_combout & \ula_|i2c_loader_|phase [1]))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|i2c_loader_|phase [0]),
|
|
.datac(\ula_|i2c_loader_|state~24_combout ),
|
|
.datad(\ula_|i2c_loader_|phase [1]),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|state~26_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|state~26 .lut_mask = 16'hC000;
|
|
defparam \ula_|i2c_loader_|state~26 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X1_Y23_N0
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|state.Data~0 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|state.Data~0_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|state~27_combout )) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state~26_combout )))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|i2c_loader_|state~27_combout ),
|
|
.datac(\ula_|i2c_loader_|state.Data~q ),
|
|
.datad(\ula_|i2c_loader_|state~26_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|state.Data~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|state.Data~0 .lut_mask = 16'hCFC0;
|
|
defparam \ula_|i2c_loader_|state.Data~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X1_Y23_N1
|
|
dffeas \ula_|i2c_loader_|state.Data (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2c_loader_|state.Data~0_combout ),
|
|
.asdata(\ula_|i2c_loader_|Mux42~0_combout ),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(\ula_|i2c_loader_|state.Start~q ),
|
|
.ena(!\ula_|i2c_loader_|WideAnd0~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2c_loader_|state.Data~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|state.Data .is_wysiwyg = "true";
|
|
defparam \ula_|i2c_loader_|state.Data .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X1_Y23_N16
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|state.Done~2 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|state.Done~2_combout = (\ula_|i2c_loader_|scl_out~0_combout & (((\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Done~1_combout )) # (!\ula_|i2c_loader_|state.Pause~q ))) # (!\ula_|i2c_loader_|scl_out~0_combout &
|
|
// (\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|state.Done~1_combout )))
|
|
|
|
.dataa(\ula_|i2c_loader_|scl_out~0_combout ),
|
|
.datab(\ula_|i2c_loader_|state.Data~q ),
|
|
.datac(\ula_|i2c_loader_|state.Done~1_combout ),
|
|
.datad(\ula_|i2c_loader_|state.Pause~q ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|state.Done~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|state.Done~2 .lut_mask = 16'h0CAE;
|
|
defparam \ula_|i2c_loader_|state.Done~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X1_Y23_N10
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~1 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|state.Pause~1_combout = ((\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q ) # (!\ula_|i2c_loader_|state.Done~2_combout )))) # (!\ula_|i2c_loader_|state.Idle~q )
|
|
|
|
.dataa(\ula_|i2c_loader_|state.Start~q ),
|
|
.datab(\ula_|i2c_loader_|state.Done~2_combout ),
|
|
.datac(\ula_|i2c_loader_|Mux42~0_combout ),
|
|
.datad(\ula_|i2c_loader_|state.Idle~q ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|state.Pause~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|state.Pause~1 .lut_mask = 16'hB0FF;
|
|
defparam \ula_|i2c_loader_|state.Pause~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X5_Y23_N18
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~8 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|thisbyte[0]~8_combout = \ula_|i2c_loader_|thisbyte [0] $ (VCC)
|
|
// \ula_|i2c_loader_|thisbyte[0]~9 = CARRY(\ula_|i2c_loader_|thisbyte [0])
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|i2c_loader_|thisbyte [0]),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|thisbyte[0]~8_combout ),
|
|
.cout(\ula_|i2c_loader_|thisbyte[0]~9 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|thisbyte[0]~8 .lut_mask = 16'h33CC;
|
|
defparam \ula_|i2c_loader_|thisbyte[0]~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X5_Y23_N28
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|nbyte[1]~5 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|nbyte[1]~5_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|nbyte [0]) # ((\ula_|i2c_loader_|nbyte [1])))) # (!\ula_|i2c_loader_|phase [0] & (((\I2C_SDAT~input_o ))))
|
|
|
|
.dataa(\ula_|i2c_loader_|phase [0]),
|
|
.datab(\ula_|i2c_loader_|nbyte [0]),
|
|
.datac(\ula_|i2c_loader_|nbyte [1]),
|
|
.datad(\I2C_SDAT~input_o ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|nbyte[1]~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|nbyte[1]~5 .lut_mask = 16'hFDA8;
|
|
defparam \ula_|i2c_loader_|nbyte[1]~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X5_Y23_N16
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[0]~18 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|thisbyte[0]~18_combout = (\ula_|i2c_loader_|state.Ack~q & (\ula_|i2c_loader_|phase [1] & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|nbyte[1]~5_combout )))
|
|
|
|
.dataa(\ula_|i2c_loader_|state.Ack~q ),
|
|
.datab(\ula_|i2c_loader_|phase [1]),
|
|
.datac(\ula_|i2c_loader_|WideAnd0~combout ),
|
|
.datad(\ula_|i2c_loader_|nbyte[1]~5_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|thisbyte[0]~18_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|thisbyte[0]~18 .lut_mask = 16'h0800;
|
|
defparam \ula_|i2c_loader_|thisbyte[0]~18 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X5_Y23_N19
|
|
dffeas \ula_|i2c_loader_|thisbyte[0] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2c_loader_|thisbyte[0]~8_combout ),
|
|
.asdata(\~GND~combout ),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(!\ula_|i2c_loader_|phase [0]),
|
|
.ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2c_loader_|thisbyte [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|thisbyte[0] .is_wysiwyg = "true";
|
|
defparam \ula_|i2c_loader_|thisbyte[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X5_Y23_N20
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[1]~10 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|thisbyte[1]~10_combout = (\ula_|i2c_loader_|thisbyte [1] & (!\ula_|i2c_loader_|thisbyte[0]~9 )) # (!\ula_|i2c_loader_|thisbyte [1] & ((\ula_|i2c_loader_|thisbyte[0]~9 ) # (GND)))
|
|
// \ula_|i2c_loader_|thisbyte[1]~11 = CARRY((!\ula_|i2c_loader_|thisbyte[0]~9 ) # (!\ula_|i2c_loader_|thisbyte [1]))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|i2c_loader_|thisbyte [1]),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\ula_|i2c_loader_|thisbyte[0]~9 ),
|
|
.combout(\ula_|i2c_loader_|thisbyte[1]~10_combout ),
|
|
.cout(\ula_|i2c_loader_|thisbyte[1]~11 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|thisbyte[1]~10 .lut_mask = 16'h3C3F;
|
|
defparam \ula_|i2c_loader_|thisbyte[1]~10 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X5_Y23_N21
|
|
dffeas \ula_|i2c_loader_|thisbyte[1] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2c_loader_|thisbyte[1]~10_combout ),
|
|
.asdata(\~GND~combout ),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(!\ula_|i2c_loader_|phase [0]),
|
|
.ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2c_loader_|thisbyte [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|thisbyte[1] .is_wysiwyg = "true";
|
|
defparam \ula_|i2c_loader_|thisbyte[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X5_Y23_N22
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[2]~12 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|thisbyte[2]~12_combout = (\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|thisbyte[1]~11 $ (GND))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte[1]~11 & VCC))
|
|
// \ula_|i2c_loader_|thisbyte[2]~13 = CARRY((\ula_|i2c_loader_|thisbyte [2] & !\ula_|i2c_loader_|thisbyte[1]~11 ))
|
|
|
|
.dataa(\ula_|i2c_loader_|thisbyte [2]),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\ula_|i2c_loader_|thisbyte[1]~11 ),
|
|
.combout(\ula_|i2c_loader_|thisbyte[2]~12_combout ),
|
|
.cout(\ula_|i2c_loader_|thisbyte[2]~13 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|thisbyte[2]~12 .lut_mask = 16'hA50A;
|
|
defparam \ula_|i2c_loader_|thisbyte[2]~12 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X5_Y23_N23
|
|
dffeas \ula_|i2c_loader_|thisbyte[2] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2c_loader_|thisbyte[2]~12_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(!\ula_|i2c_loader_|phase [0]),
|
|
.ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2c_loader_|thisbyte [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|thisbyte[2] .is_wysiwyg = "true";
|
|
defparam \ula_|i2c_loader_|thisbyte[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X5_Y23_N24
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[3]~14 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|thisbyte[3]~14_combout = (\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte[2]~13 )) # (!\ula_|i2c_loader_|thisbyte [3] & ((\ula_|i2c_loader_|thisbyte[2]~13 ) # (GND)))
|
|
// \ula_|i2c_loader_|thisbyte[3]~15 = CARRY((!\ula_|i2c_loader_|thisbyte[2]~13 ) # (!\ula_|i2c_loader_|thisbyte [3]))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|i2c_loader_|thisbyte [3]),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\ula_|i2c_loader_|thisbyte[2]~13 ),
|
|
.combout(\ula_|i2c_loader_|thisbyte[3]~14_combout ),
|
|
.cout(\ula_|i2c_loader_|thisbyte[3]~15 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|thisbyte[3]~14 .lut_mask = 16'h3C3F;
|
|
defparam \ula_|i2c_loader_|thisbyte[3]~14 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X5_Y23_N25
|
|
dffeas \ula_|i2c_loader_|thisbyte[3] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2c_loader_|thisbyte[3]~14_combout ),
|
|
.asdata(\~GND~combout ),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(!\ula_|i2c_loader_|phase [0]),
|
|
.ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2c_loader_|thisbyte [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|thisbyte[3] .is_wysiwyg = "true";
|
|
defparam \ula_|i2c_loader_|thisbyte[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X4_Y23_N4
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|Equal2~0 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|Equal2~0_combout = (\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte [1] & !\ula_|i2c_loader_|thisbyte [0])))
|
|
|
|
.dataa(\ula_|i2c_loader_|thisbyte [2]),
|
|
.datab(\ula_|i2c_loader_|thisbyte [3]),
|
|
.datac(\ula_|i2c_loader_|thisbyte [1]),
|
|
.datad(\ula_|i2c_loader_|thisbyte [0]),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|Equal2~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|Equal2~0 .lut_mask = 16'h0002;
|
|
defparam \ula_|i2c_loader_|Equal2~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X5_Y23_N26
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|thisbyte[4]~16 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|thisbyte[4]~16_combout = \ula_|i2c_loader_|thisbyte [4] $ (!\ula_|i2c_loader_|thisbyte[3]~15 )
|
|
|
|
.dataa(\ula_|i2c_loader_|thisbyte [4]),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(gnd),
|
|
.cin(\ula_|i2c_loader_|thisbyte[3]~15 ),
|
|
.combout(\ula_|i2c_loader_|thisbyte[4]~16_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|thisbyte[4]~16 .lut_mask = 16'hA5A5;
|
|
defparam \ula_|i2c_loader_|thisbyte[4]~16 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X5_Y23_N27
|
|
dffeas \ula_|i2c_loader_|thisbyte[4] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2c_loader_|thisbyte[4]~16_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(!\ula_|i2c_loader_|phase [0]),
|
|
.ena(\ula_|i2c_loader_|thisbyte[0]~18_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2c_loader_|thisbyte [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|thisbyte[4] .is_wysiwyg = "true";
|
|
defparam \ula_|i2c_loader_|thisbyte[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X4_Y23_N30
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|Equal2~1 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|Equal2~1_combout = (\ula_|i2c_loader_|Equal2~0_combout & \ula_|i2c_loader_|thisbyte [4])
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\ula_|i2c_loader_|Equal2~0_combout ),
|
|
.datad(\ula_|i2c_loader_|thisbyte [4]),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|Equal2~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|Equal2~1 .lut_mask = 16'hF000;
|
|
defparam \ula_|i2c_loader_|Equal2~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X2_Y23_N22
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~0 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|state.Pause~0_combout = (!\ula_|i2c_loader_|Equal2~1_combout & ((\ula_|i2c_loader_|state.Data~q & ((!\ula_|i2c_loader_|Mux42~0_combout ))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|state.Stop~q ))))
|
|
|
|
.dataa(\ula_|i2c_loader_|state.Stop~q ),
|
|
.datab(\ula_|i2c_loader_|Mux42~0_combout ),
|
|
.datac(\ula_|i2c_loader_|state.Data~q ),
|
|
.datad(\ula_|i2c_loader_|Equal2~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|state.Pause~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|state.Pause~0 .lut_mask = 16'h003A;
|
|
defparam \ula_|i2c_loader_|state.Pause~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X1_Y23_N24
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|state.Pause~2 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|state.Pause~2_combout = (\ula_|i2c_loader_|state.Pause~1_combout & ((\ula_|i2c_loader_|WideAnd0~combout & (\ula_|i2c_loader_|state.Pause~q )) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|state.Pause~0_combout ))))) #
|
|
// (!\ula_|i2c_loader_|state.Pause~1_combout & (((\ula_|i2c_loader_|state.Pause~q ))))
|
|
|
|
.dataa(\ula_|i2c_loader_|state.Pause~1_combout ),
|
|
.datab(\ula_|i2c_loader_|WideAnd0~combout ),
|
|
.datac(\ula_|i2c_loader_|state.Pause~q ),
|
|
.datad(\ula_|i2c_loader_|state.Pause~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|state.Pause~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|state.Pause~2 .lut_mask = 16'hF2D0;
|
|
defparam \ula_|i2c_loader_|state.Pause~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X1_Y23_N25
|
|
dffeas \ula_|i2c_loader_|state.Pause (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2c_loader_|state.Pause~2_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2c_loader_|state.Pause~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|state.Pause .is_wysiwyg = "true";
|
|
defparam \ula_|i2c_loader_|state.Pause .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X3_Y23_N26
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|state~25 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|state~25_combout = ((\ula_|i2c_loader_|Mux42~0_combout & (\ula_|i2c_loader_|state.Pause~q & !\ula_|i2c_loader_|state.Start~q )) # (!\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Start~q )))) #
|
|
// (!\ula_|i2c_loader_|state.Idle~q )
|
|
|
|
.dataa(\ula_|i2c_loader_|state.Pause~q ),
|
|
.datab(\ula_|i2c_loader_|Mux42~0_combout ),
|
|
.datac(\ula_|i2c_loader_|state.Start~q ),
|
|
.datad(\ula_|i2c_loader_|state.Idle~q ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|state~25_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|state~25 .lut_mask = 16'h38FF;
|
|
defparam \ula_|i2c_loader_|state~25 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X3_Y23_N27
|
|
dffeas \ula_|i2c_loader_|state.Start (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2c_loader_|state~25_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(!\ula_|i2c_loader_|WideAnd0~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2c_loader_|state.Start~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|state.Start .is_wysiwyg = "true";
|
|
defparam \ula_|i2c_loader_|state.Start .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X2_Y23_N4
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|nbyte~0 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|nbyte~0_combout = (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|nbyte [0] & !\ula_|i2c_loader_|state.Start~q ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|i2c_loader_|phase [0]),
|
|
.datac(\ula_|i2c_loader_|nbyte [0]),
|
|
.datad(\ula_|i2c_loader_|state.Start~q ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|nbyte~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|nbyte~0 .lut_mask = 16'h000C;
|
|
defparam \ula_|i2c_loader_|nbyte~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X2_Y23_N5
|
|
dffeas \ula_|i2c_loader_|nbyte[0] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2c_loader_|nbyte~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|i2c_loader_|nbyte[0]~3_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2c_loader_|nbyte [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|nbyte[0] .is_wysiwyg = "true";
|
|
defparam \ula_|i2c_loader_|nbyte[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X2_Y23_N12
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~0 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|state.Stop~0_combout = (!\ula_|i2c_loader_|nbyte [0] & (!\ula_|i2c_loader_|nbyte [1] & \ula_|i2c_loader_|state.Ack~q ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|i2c_loader_|nbyte [0]),
|
|
.datac(\ula_|i2c_loader_|nbyte [1]),
|
|
.datad(\ula_|i2c_loader_|state.Ack~q ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|state.Stop~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|state.Stop~0 .lut_mask = 16'h0300;
|
|
defparam \ula_|i2c_loader_|state.Stop~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X2_Y23_N6
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|state.Stop~1 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|state.Stop~1_combout = (\ula_|i2c_loader_|WideAnd0~combout & (((\ula_|i2c_loader_|state.Stop~q )))) # (!\ula_|i2c_loader_|WideAnd0~combout & ((\ula_|i2c_loader_|Mux42~0_combout & (\ula_|i2c_loader_|state.Stop~0_combout )) #
|
|
// (!\ula_|i2c_loader_|Mux42~0_combout & ((\ula_|i2c_loader_|state.Stop~q )))))
|
|
|
|
.dataa(\ula_|i2c_loader_|state.Stop~0_combout ),
|
|
.datab(\ula_|i2c_loader_|WideAnd0~combout ),
|
|
.datac(\ula_|i2c_loader_|state.Stop~q ),
|
|
.datad(\ula_|i2c_loader_|Mux42~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|state.Stop~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|state.Stop~1 .lut_mask = 16'hE2F0;
|
|
defparam \ula_|i2c_loader_|state.Stop~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X2_Y23_N7
|
|
dffeas \ula_|i2c_loader_|state.Stop (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2c_loader_|state.Stop~1_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2c_loader_|state.Stop~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|state.Stop .is_wysiwyg = "true";
|
|
defparam \ula_|i2c_loader_|state.Stop .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X1_Y23_N22
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~0 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|scl_out~0_combout = (!\ula_|i2c_loader_|state.Stop~q & (!\ula_|i2c_loader_|state.Data~q & !\ula_|i2c_loader_|state.Ack~q ))
|
|
|
|
.dataa(\ula_|i2c_loader_|state.Stop~q ),
|
|
.datab(\ula_|i2c_loader_|state.Data~q ),
|
|
.datac(gnd),
|
|
.datad(\ula_|i2c_loader_|state.Ack~q ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|scl_out~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|scl_out~0 .lut_mask = 16'h0011;
|
|
defparam \ula_|i2c_loader_|scl_out~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X1_Y23_N7
|
|
dffeas \ula_|i2c_loader_|scl_out~_Duplicate_1 (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2c_loader_|scl_out~2_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(!\ula_|i2c_loader_|WideAnd0~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2c_loader_|scl_out~_Duplicate_1_q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|scl_out~_Duplicate_1 .is_wysiwyg = "true";
|
|
defparam \ula_|i2c_loader_|scl_out~_Duplicate_1 .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X1_Y23_N8
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~1 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|scl_out~1_combout = (\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|state.Start~q $ (((!\ula_|i2c_loader_|scl_out~_Duplicate_1_q ))))) # (!\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|phase [1]) #
|
|
// ((\ula_|i2c_loader_|state.Start~q & \ula_|i2c_loader_|scl_out~_Duplicate_1_q ))))
|
|
|
|
.dataa(\ula_|i2c_loader_|state.Start~q ),
|
|
.datab(\ula_|i2c_loader_|phase [0]),
|
|
.datac(\ula_|i2c_loader_|phase [1]),
|
|
.datad(\ula_|i2c_loader_|scl_out~_Duplicate_1_q ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|scl_out~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|scl_out~1 .lut_mask = 16'hBA74;
|
|
defparam \ula_|i2c_loader_|scl_out~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X1_Y23_N6
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|scl_out~2 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|scl_out~2_combout = (\ula_|i2c_loader_|scl_out~1_combout & ((\ula_|i2c_loader_|state.Start~q ))) # (!\ula_|i2c_loader_|scl_out~1_combout & (!\ula_|i2c_loader_|scl_out~0_combout & !\ula_|i2c_loader_|state.Start~q ))
|
|
|
|
.dataa(\ula_|i2c_loader_|scl_out~0_combout ),
|
|
.datab(\ula_|i2c_loader_|scl_out~1_combout ),
|
|
.datac(\ula_|i2c_loader_|state.Start~q ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|scl_out~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|scl_out~2 .lut_mask = 16'hC1C1;
|
|
defparam \ula_|i2c_loader_|scl_out~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: DDIOOUTCELL_X0_Y24_N25
|
|
dffeas \ula_|i2c_loader_|scl_out (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(!\ula_|i2c_loader_|scl_out~2_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(\reset~clkctrl_outclk ),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(!\ula_|i2c_loader_|WideAnd0~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2c_loader_|scl_out~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|scl_out .is_wysiwyg = "true";
|
|
defparam \ula_|i2c_loader_|scl_out .power_up = "high";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X1_Y23_N13
|
|
dffeas \ula_|i2c_loader_|sda_out~_Duplicate_1 (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2c_loader_|sda_out~4_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(!\ula_|i2c_loader_|WideAnd0~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2c_loader_|sda_out~_Duplicate_1_q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|sda_out~_Duplicate_1 .is_wysiwyg = "true";
|
|
defparam \ula_|i2c_loader_|sda_out~_Duplicate_1 .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X4_Y23_N10
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~4 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|shiftreg~4_combout = (!\ula_|i2c_loader_|state.Start~q & !\ula_|i2c_loader_|state.Data~q )
|
|
|
|
.dataa(\ula_|i2c_loader_|state.Start~q ),
|
|
.datab(gnd),
|
|
.datac(\ula_|i2c_loader_|state.Data~q ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|shiftreg~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|shiftreg~4 .lut_mask = 16'h0505;
|
|
defparam \ula_|i2c_loader_|shiftreg~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X4_Y23_N20
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|Mux35~0 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|Mux35~0_combout = (\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|thisbyte [0] & ((!\ula_|i2c_loader_|thisbyte [1]) # (!\ula_|i2c_loader_|thisbyte [3]))))
|
|
|
|
.dataa(\ula_|i2c_loader_|thisbyte [2]),
|
|
.datab(\ula_|i2c_loader_|thisbyte [3]),
|
|
.datac(\ula_|i2c_loader_|thisbyte [1]),
|
|
.datad(\ula_|i2c_loader_|thisbyte [0]),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|Mux35~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|Mux35~0 .lut_mask = 16'h2A00;
|
|
defparam \ula_|i2c_loader_|Mux35~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X5_Y23_N12
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~13 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|shiftreg~13_combout = (!\ula_|i2c_loader_|thisbyte [2] & \ula_|i2c_loader_|thisbyte [4])
|
|
|
|
.dataa(\ula_|i2c_loader_|thisbyte [2]),
|
|
.datab(gnd),
|
|
.datac(\ula_|i2c_loader_|thisbyte [4]),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|shiftreg~13_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|shiftreg~13 .lut_mask = 16'h5050;
|
|
defparam \ula_|i2c_loader_|shiftreg~13 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X5_Y23_N4
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~15 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|shiftreg~15_combout = (\ula_|i2c_loader_|thisbyte [2] & (((!\ula_|i2c_loader_|thisbyte [3])))) # (!\ula_|i2c_loader_|thisbyte [2] & (!\ula_|i2c_loader_|thisbyte [1] & (\ula_|i2c_loader_|thisbyte [4])))
|
|
|
|
.dataa(\ula_|i2c_loader_|thisbyte [2]),
|
|
.datab(\ula_|i2c_loader_|thisbyte [1]),
|
|
.datac(\ula_|i2c_loader_|thisbyte [4]),
|
|
.datad(\ula_|i2c_loader_|thisbyte [3]),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|shiftreg~15_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|shiftreg~15 .lut_mask = 16'h10BA;
|
|
defparam \ula_|i2c_loader_|shiftreg~15 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X5_Y23_N10
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~16 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|shiftreg~16_combout = (\ula_|i2c_loader_|thisbyte [0] & (((\ula_|i2c_loader_|shiftreg~15_combout )))) # (!\ula_|i2c_loader_|thisbyte [0] & (!\ula_|i2c_loader_|shiftreg~13_combout & (\ula_|i2c_loader_|thisbyte [3])))
|
|
|
|
.dataa(\ula_|i2c_loader_|shiftreg~13_combout ),
|
|
.datab(\ula_|i2c_loader_|thisbyte [3]),
|
|
.datac(\ula_|i2c_loader_|shiftreg~15_combout ),
|
|
.datad(\ula_|i2c_loader_|thisbyte [0]),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|shiftreg~16_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|shiftreg~16 .lut_mask = 16'hF044;
|
|
defparam \ula_|i2c_loader_|shiftreg~16 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X4_Y23_N12
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~17 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|shiftreg~17_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [1])) # (!\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [3])))))
|
|
|
|
.dataa(\ula_|i2c_loader_|thisbyte [4]),
|
|
.datab(\ula_|i2c_loader_|thisbyte [0]),
|
|
.datac(\ula_|i2c_loader_|thisbyte [1]),
|
|
.datad(\ula_|i2c_loader_|thisbyte [3]),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|shiftreg~17_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|shiftreg~17 .lut_mask = 16'h084C;
|
|
defparam \ula_|i2c_loader_|shiftreg~17 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X4_Y23_N22
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~18 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|shiftreg~18_combout = ((\ula_|i2c_loader_|thisbyte [2] & ((!\ula_|i2c_loader_|thisbyte [0]))) # (!\ula_|i2c_loader_|thisbyte [2] & (\ula_|i2c_loader_|shiftreg~17_combout ))) # (!\ula_|i2c_loader_|shiftreg~4_combout )
|
|
|
|
.dataa(\ula_|i2c_loader_|shiftreg~17_combout ),
|
|
.datab(\ula_|i2c_loader_|thisbyte [2]),
|
|
.datac(\ula_|i2c_loader_|shiftreg~4_combout ),
|
|
.datad(\ula_|i2c_loader_|thisbyte [0]),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|shiftreg~18_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|shiftreg~18 .lut_mask = 16'h2FEF;
|
|
defparam \ula_|i2c_loader_|shiftreg~18 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X4_Y23_N14
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~20 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|shiftreg~20_combout = (\ula_|i2c_loader_|thisbyte [0] & ((\ula_|i2c_loader_|thisbyte [3] & (\ula_|i2c_loader_|thisbyte [2])) # (!\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|thisbyte [2] & !\ula_|i2c_loader_|thisbyte [4]))))
|
|
|
|
.dataa(\ula_|i2c_loader_|thisbyte [0]),
|
|
.datab(\ula_|i2c_loader_|thisbyte [3]),
|
|
.datac(\ula_|i2c_loader_|thisbyte [2]),
|
|
.datad(\ula_|i2c_loader_|thisbyte [4]),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|shiftreg~20_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|shiftreg~20 .lut_mask = 16'h8082;
|
|
defparam \ula_|i2c_loader_|shiftreg~20 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X4_Y23_N24
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~21 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|shiftreg~21_combout = (\ula_|i2c_loader_|shiftreg~4_combout & ((\ula_|i2c_loader_|shiftreg~20_combout ) # ((\ula_|i2c_loader_|thisbyte [1] & !\ula_|i2c_loader_|thisbyte [0]))))
|
|
|
|
.dataa(\ula_|i2c_loader_|shiftreg~4_combout ),
|
|
.datab(\ula_|i2c_loader_|shiftreg~20_combout ),
|
|
.datac(\ula_|i2c_loader_|thisbyte [1]),
|
|
.datad(\ula_|i2c_loader_|thisbyte [0]),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|shiftreg~21_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|shiftreg~21 .lut_mask = 16'h88A8;
|
|
defparam \ula_|i2c_loader_|shiftreg~21 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X4_Y23_N0
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~23 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|shiftreg[0]~23_combout = (!\ula_|i2c_loader_|thisbyte [3] & (!\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|thisbyte [0]))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|i2c_loader_|thisbyte [3]),
|
|
.datac(\ula_|i2c_loader_|state.Data~q ),
|
|
.datad(\ula_|i2c_loader_|thisbyte [0]),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|shiftreg[0]~23_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|shiftreg[0]~23 .lut_mask = 16'h0300;
|
|
defparam \ula_|i2c_loader_|shiftreg[0]~23 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X3_Y23_N30
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~6 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|shiftreg[0]~6_combout = (\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|state~24_combout ) # ((\ula_|i2c_loader_|state.Start~q )))) # (!\ula_|i2c_loader_|phase [1] & (((\ula_|i2c_loader_|state.Data~q ))))
|
|
|
|
.dataa(\ula_|i2c_loader_|state~24_combout ),
|
|
.datab(\ula_|i2c_loader_|state.Data~q ),
|
|
.datac(\ula_|i2c_loader_|state.Start~q ),
|
|
.datad(\ula_|i2c_loader_|phase [1]),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|shiftreg[0]~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|shiftreg[0]~6 .lut_mask = 16'hFACC;
|
|
defparam \ula_|i2c_loader_|shiftreg[0]~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X3_Y23_N8
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[0]~7 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|shiftreg[0]~7_combout = (\ula_|i2c_loader_|shiftreg[0]~6_combout & (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|state.Idle~q )))
|
|
|
|
.dataa(\ula_|i2c_loader_|shiftreg[0]~6_combout ),
|
|
.datab(\ula_|i2c_loader_|phase [0]),
|
|
.datac(\ula_|i2c_loader_|WideAnd0~combout ),
|
|
.datad(\ula_|i2c_loader_|state.Idle~q ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|shiftreg[0]~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|shiftreg[0]~7 .lut_mask = 16'h0800;
|
|
defparam \ula_|i2c_loader_|shiftreg[0]~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X4_Y23_N1
|
|
dffeas \ula_|i2c_loader_|shiftreg[0] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2c_loader_|shiftreg[0]~23_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(\ula_|i2c_loader_|state.Start~q ),
|
|
.sload(gnd),
|
|
.ena(\ula_|i2c_loader_|shiftreg[0]~7_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2c_loader_|shiftreg [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|shiftreg[0] .is_wysiwyg = "true";
|
|
defparam \ula_|i2c_loader_|shiftreg[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X4_Y23_N28
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~22 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|shiftreg~22_combout = (\ula_|i2c_loader_|shiftreg~21_combout ) # ((\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|shiftreg [0]))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|i2c_loader_|shiftreg~21_combout ),
|
|
.datac(\ula_|i2c_loader_|state.Data~q ),
|
|
.datad(\ula_|i2c_loader_|shiftreg [0]),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|shiftreg~22_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|shiftreg~22 .lut_mask = 16'hFCCC;
|
|
defparam \ula_|i2c_loader_|shiftreg~22 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X3_Y23_N10
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~9 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|shiftreg[6]~9_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state.Start~q $ (!\ula_|i2c_loader_|phase [1])))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|state~24_combout
|
|
// ) # (\ula_|i2c_loader_|state.Start~q ))))
|
|
|
|
.dataa(\ula_|i2c_loader_|state~24_combout ),
|
|
.datab(\ula_|i2c_loader_|state.Data~q ),
|
|
.datac(\ula_|i2c_loader_|state.Start~q ),
|
|
.datad(\ula_|i2c_loader_|phase [1]),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|shiftreg[6]~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|shiftreg[6]~9 .lut_mask = 16'hF20C;
|
|
defparam \ula_|i2c_loader_|shiftreg[6]~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X3_Y23_N12
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[6]~10 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|shiftreg[6]~10_combout = (\ula_|i2c_loader_|shiftreg[6]~9_combout & (\ula_|i2c_loader_|phase [0] & (!\ula_|i2c_loader_|WideAnd0~combout & \ula_|i2c_loader_|state.Idle~q )))
|
|
|
|
.dataa(\ula_|i2c_loader_|shiftreg[6]~9_combout ),
|
|
.datab(\ula_|i2c_loader_|phase [0]),
|
|
.datac(\ula_|i2c_loader_|WideAnd0~combout ),
|
|
.datad(\ula_|i2c_loader_|state.Idle~q ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|shiftreg[6]~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|shiftreg[6]~10 .lut_mask = 16'h0800;
|
|
defparam \ula_|i2c_loader_|shiftreg[6]~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X4_Y23_N29
|
|
dffeas \ula_|i2c_loader_|shiftreg[1] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2c_loader_|shiftreg~22_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|i2c_loader_|shiftreg[6]~10_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2c_loader_|shiftreg [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|shiftreg[1] .is_wysiwyg = "true";
|
|
defparam \ula_|i2c_loader_|shiftreg[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X4_Y23_N2
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~19 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|shiftreg~19_combout = (\ula_|i2c_loader_|shiftreg~18_combout & ((\ula_|i2c_loader_|shiftreg [1]) # (!\ula_|i2c_loader_|state.Data~q )))
|
|
|
|
.dataa(\ula_|i2c_loader_|shiftreg~18_combout ),
|
|
.datab(\ula_|i2c_loader_|shiftreg [1]),
|
|
.datac(\ula_|i2c_loader_|state.Data~q ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|shiftreg~19_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|shiftreg~19 .lut_mask = 16'h8A8A;
|
|
defparam \ula_|i2c_loader_|shiftreg~19 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X4_Y23_N3
|
|
dffeas \ula_|i2c_loader_|shiftreg[2] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2c_loader_|shiftreg~19_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|i2c_loader_|shiftreg[6]~10_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2c_loader_|shiftreg [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|shiftreg[2] .is_wysiwyg = "true";
|
|
defparam \ula_|i2c_loader_|shiftreg[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X4_Y23_N8
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~25 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|shiftreg~25_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|shiftreg [2])))) # (!\ula_|i2c_loader_|state.Data~q & (!\ula_|i2c_loader_|state.Start~q & (\ula_|i2c_loader_|shiftreg~16_combout )))
|
|
|
|
.dataa(\ula_|i2c_loader_|state.Start~q ),
|
|
.datab(\ula_|i2c_loader_|state.Data~q ),
|
|
.datac(\ula_|i2c_loader_|shiftreg~16_combout ),
|
|
.datad(\ula_|i2c_loader_|shiftreg [2]),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|shiftreg~25_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|shiftreg~25 .lut_mask = 16'hDC10;
|
|
defparam \ula_|i2c_loader_|shiftreg~25 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X4_Y23_N9
|
|
dffeas \ula_|i2c_loader_|shiftreg[3] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2c_loader_|shiftreg~25_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|i2c_loader_|shiftreg[6]~10_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2c_loader_|shiftreg [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|shiftreg[3] .is_wysiwyg = "true";
|
|
defparam \ula_|i2c_loader_|shiftreg[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X5_Y23_N14
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~12 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|shiftreg~12_combout = (!\ula_|i2c_loader_|thisbyte [2] & ((\ula_|i2c_loader_|thisbyte [4] & ((!\ula_|i2c_loader_|thisbyte [0]))) # (!\ula_|i2c_loader_|thisbyte [4] & (!\ula_|i2c_loader_|thisbyte [1] & \ula_|i2c_loader_|thisbyte [0]))))
|
|
|
|
.dataa(\ula_|i2c_loader_|thisbyte [2]),
|
|
.datab(\ula_|i2c_loader_|thisbyte [1]),
|
|
.datac(\ula_|i2c_loader_|thisbyte [4]),
|
|
.datad(\ula_|i2c_loader_|thisbyte [0]),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|shiftreg~12_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|shiftreg~12 .lut_mask = 16'h0150;
|
|
defparam \ula_|i2c_loader_|shiftreg~12 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X5_Y23_N6
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~14 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|shiftreg~14_combout = (\ula_|i2c_loader_|shiftreg~12_combout ) # ((!\ula_|i2c_loader_|shiftreg~13_combout & (!\ula_|i2c_loader_|thisbyte [3] & \ula_|i2c_loader_|thisbyte [0])))
|
|
|
|
.dataa(\ula_|i2c_loader_|shiftreg~13_combout ),
|
|
.datab(\ula_|i2c_loader_|thisbyte [3]),
|
|
.datac(\ula_|i2c_loader_|shiftreg~12_combout ),
|
|
.datad(\ula_|i2c_loader_|thisbyte [0]),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|shiftreg~14_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|shiftreg~14 .lut_mask = 16'hF1F0;
|
|
defparam \ula_|i2c_loader_|shiftreg~14 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X4_Y23_N6
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~24 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|shiftreg~24_combout = (\ula_|i2c_loader_|state.Data~q & (((\ula_|i2c_loader_|shiftreg [3])))) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state.Start~q ) # ((\ula_|i2c_loader_|shiftreg~14_combout ))))
|
|
|
|
.dataa(\ula_|i2c_loader_|state.Start~q ),
|
|
.datab(\ula_|i2c_loader_|shiftreg [3]),
|
|
.datac(\ula_|i2c_loader_|state.Data~q ),
|
|
.datad(\ula_|i2c_loader_|shiftreg~14_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|shiftreg~24_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|shiftreg~24 .lut_mask = 16'hCFCA;
|
|
defparam \ula_|i2c_loader_|shiftreg~24 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X4_Y23_N7
|
|
dffeas \ula_|i2c_loader_|shiftreg[4] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2c_loader_|shiftreg~24_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|i2c_loader_|shiftreg[6]~10_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2c_loader_|shiftreg [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|shiftreg[4] .is_wysiwyg = "true";
|
|
defparam \ula_|i2c_loader_|shiftreg[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X3_Y23_N24
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~11 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|shiftreg~11_combout = (\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|shiftreg [4]))) # (!\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|Mux35~0_combout ))
|
|
|
|
.dataa(\ula_|i2c_loader_|Mux35~0_combout ),
|
|
.datab(\ula_|i2c_loader_|state.Data~q ),
|
|
.datac(gnd),
|
|
.datad(\ula_|i2c_loader_|shiftreg [4]),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|shiftreg~11_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|shiftreg~11 .lut_mask = 16'hEE22;
|
|
defparam \ula_|i2c_loader_|shiftreg~11 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X3_Y23_N25
|
|
dffeas \ula_|i2c_loader_|shiftreg[5] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2c_loader_|shiftreg~11_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(\ula_|i2c_loader_|state.Start~q ),
|
|
.ena(\ula_|i2c_loader_|shiftreg[6]~10_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2c_loader_|shiftreg [5]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|shiftreg[5] .is_wysiwyg = "true";
|
|
defparam \ula_|i2c_loader_|shiftreg[5] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X4_Y23_N18
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg~8 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|shiftreg~8_combout = (\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [5])) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|Mux35~0_combout )))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|i2c_loader_|shiftreg [5]),
|
|
.datac(\ula_|i2c_loader_|state.Data~q ),
|
|
.datad(\ula_|i2c_loader_|Mux35~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|shiftreg~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|shiftreg~8 .lut_mask = 16'hCFC0;
|
|
defparam \ula_|i2c_loader_|shiftreg~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X4_Y23_N19
|
|
dffeas \ula_|i2c_loader_|shiftreg[6] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2c_loader_|shiftreg~8_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(\ula_|i2c_loader_|state.Start~q ),
|
|
.sload(gnd),
|
|
.ena(\ula_|i2c_loader_|shiftreg[6]~10_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2c_loader_|shiftreg [6]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|shiftreg[6] .is_wysiwyg = "true";
|
|
defparam \ula_|i2c_loader_|shiftreg[6] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X4_Y23_N16
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|shiftreg[7]~5 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|shiftreg[7]~5_combout = (\ula_|i2c_loader_|state.Data~q & \ula_|i2c_loader_|shiftreg [6])
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\ula_|i2c_loader_|state.Data~q ),
|
|
.datad(\ula_|i2c_loader_|shiftreg [6]),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|shiftreg[7]~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|shiftreg[7]~5 .lut_mask = 16'hF000;
|
|
defparam \ula_|i2c_loader_|shiftreg[7]~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X4_Y23_N17
|
|
dffeas \ula_|i2c_loader_|shiftreg[7] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2c_loader_|shiftreg[7]~5_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(\ula_|i2c_loader_|state.Start~q ),
|
|
.sload(gnd),
|
|
.ena(\ula_|i2c_loader_|shiftreg[0]~7_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2c_loader_|shiftreg [7]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|shiftreg[7] .is_wysiwyg = "true";
|
|
defparam \ula_|i2c_loader_|shiftreg[7] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X1_Y23_N26
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~0 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|sda_out~0_combout = (\ula_|i2c_loader_|phase [0] & ((\ula_|i2c_loader_|state.Data~q & (\ula_|i2c_loader_|shiftreg [7])) # (!\ula_|i2c_loader_|state.Data~q & ((\ula_|i2c_loader_|state.Ack~q ))))) # (!\ula_|i2c_loader_|phase [0] &
|
|
// (((\ula_|i2c_loader_|state.Ack~q ))))
|
|
|
|
.dataa(\ula_|i2c_loader_|shiftreg [7]),
|
|
.datab(\ula_|i2c_loader_|state.Ack~q ),
|
|
.datac(\ula_|i2c_loader_|phase [0]),
|
|
.datad(\ula_|i2c_loader_|state.Data~q ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|sda_out~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|sda_out~0 .lut_mask = 16'hACCC;
|
|
defparam \ula_|i2c_loader_|sda_out~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X1_Y23_N20
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~1 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|sda_out~1_combout = (\ula_|i2c_loader_|sda_out~0_combout & ((\ula_|i2c_loader_|phase [0]) # ((\ula_|i2c_loader_|shiftreg~4_combout & !\I2C_SDAT~input_o ))))
|
|
|
|
.dataa(\ula_|i2c_loader_|shiftreg~4_combout ),
|
|
.datab(\ula_|i2c_loader_|phase [0]),
|
|
.datac(\ula_|i2c_loader_|sda_out~0_combout ),
|
|
.datad(\I2C_SDAT~input_o ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|sda_out~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|sda_out~1 .lut_mask = 16'hC0E0;
|
|
defparam \ula_|i2c_loader_|sda_out~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X1_Y23_N14
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~2 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|sda_out~2_combout = (!\ula_|i2c_loader_|sda_out~_Duplicate_1_q & ((\ula_|i2c_loader_|phase [0]) # ((\ula_|i2c_loader_|phase [1] & !\ula_|i2c_loader_|sda_out~1_combout ))))
|
|
|
|
.dataa(\ula_|i2c_loader_|sda_out~_Duplicate_1_q ),
|
|
.datab(\ula_|i2c_loader_|phase [1]),
|
|
.datac(\ula_|i2c_loader_|phase [0]),
|
|
.datad(\ula_|i2c_loader_|sda_out~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|sda_out~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|sda_out~2 .lut_mask = 16'h5054;
|
|
defparam \ula_|i2c_loader_|sda_out~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X1_Y23_N28
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~3 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|sda_out~3_combout = (\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|sda_out~_Duplicate_1_q ) # ((!\ula_|i2c_loader_|phase [0] & \ula_|i2c_loader_|sda_out~1_combout )))) # (!\ula_|i2c_loader_|phase [1] & ((\ula_|i2c_loader_|phase [0]
|
|
// & ((!\ula_|i2c_loader_|sda_out~1_combout ))) # (!\ula_|i2c_loader_|phase [0] & (\ula_|i2c_loader_|sda_out~_Duplicate_1_q ))))
|
|
|
|
.dataa(\ula_|i2c_loader_|sda_out~_Duplicate_1_q ),
|
|
.datab(\ula_|i2c_loader_|phase [1]),
|
|
.datac(\ula_|i2c_loader_|phase [0]),
|
|
.datad(\ula_|i2c_loader_|sda_out~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|sda_out~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|sda_out~3 .lut_mask = 16'h8EBA;
|
|
defparam \ula_|i2c_loader_|sda_out~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X1_Y23_N12
|
|
cycloneive_lcell_comb \ula_|i2c_loader_|sda_out~4 (
|
|
// Equation(s):
|
|
// \ula_|i2c_loader_|sda_out~4_combout = (\ula_|i2c_loader_|state.Start~q & (((!\ula_|i2c_loader_|sda_out~2_combout )))) # (!\ula_|i2c_loader_|state.Start~q & (!\ula_|i2c_loader_|scl_out~0_combout & ((\ula_|i2c_loader_|sda_out~3_combout ))))
|
|
|
|
.dataa(\ula_|i2c_loader_|scl_out~0_combout ),
|
|
.datab(\ula_|i2c_loader_|state.Start~q ),
|
|
.datac(\ula_|i2c_loader_|sda_out~2_combout ),
|
|
.datad(\ula_|i2c_loader_|sda_out~3_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2c_loader_|sda_out~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|sda_out~4 .lut_mask = 16'h1D0C;
|
|
defparam \ula_|i2c_loader_|sda_out~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: DDIOOUTCELL_X0_Y23_N4
|
|
dffeas \ula_|i2c_loader_|sda_out (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(!\ula_|i2c_loader_|sda_out~4_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(\reset~clkctrl_outclk ),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(!\ula_|i2c_loader_|WideAnd0~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2c_loader_|sda_out~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2c_loader_|sda_out .is_wysiwyg = "true";
|
|
defparam \ula_|i2c_loader_|sda_out .power_up = "high";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y32_N20
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|mclk_r~0 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|mclk_r~0_combout = !\ula_|i2s_intf_|mclk_r~_Duplicate_1_q
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|mclk_r~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|mclk_r~0 .lut_mask = 16'h0F0F;
|
|
defparam \ula_|i2s_intf_|mclk_r~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X25_Y32_N21
|
|
dffeas \ula_|i2s_intf_|mclk_r~_Duplicate_1 (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2s_intf_|mclk_r~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|mclk_r~_Duplicate_1 .is_wysiwyg = "true";
|
|
defparam \ula_|i2s_intf_|mclk_r~_Duplicate_1 .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: DDIOOUTCELL_X20_Y34_N25
|
|
dffeas \ula_|i2s_intf_|mclk_r (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(!\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2s_intf_|mclk_r~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|mclk_r .is_wysiwyg = "true";
|
|
defparam \ula_|i2s_intf_|mclk_r .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y32_N8
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|Add0~1 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|Add0~1_cout = CARRY(!\ula_|i2s_intf_|mclk_r~_Duplicate_1_q )
|
|
|
|
.dataa(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(gnd),
|
|
.combout(),
|
|
.cout(\ula_|i2s_intf_|Add0~1_cout ));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|Add0~1 .lut_mask = 16'h0055;
|
|
defparam \ula_|i2s_intf_|Add0~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y32_N10
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|Add0~2 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|Add0~2_combout = (\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|Add0~1_cout & VCC)) # (!\ula_|i2s_intf_|lrdivider [1] & (!\ula_|i2s_intf_|Add0~1_cout ))
|
|
// \ula_|i2s_intf_|Add0~3 = CARRY((!\ula_|i2s_intf_|lrdivider [1] & !\ula_|i2s_intf_|Add0~1_cout ))
|
|
|
|
.dataa(\ula_|i2s_intf_|lrdivider [1]),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\ula_|i2s_intf_|Add0~1_cout ),
|
|
.combout(\ula_|i2s_intf_|Add0~2_combout ),
|
|
.cout(\ula_|i2s_intf_|Add0~3 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|Add0~2 .lut_mask = 16'hA505;
|
|
defparam \ula_|i2s_intf_|Add0~2 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y32_N10
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~2 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|lrdivider~2_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~2_combout )
|
|
|
|
.dataa(\ula_|i2s_intf_|Equal0~2_combout ),
|
|
.datab(gnd),
|
|
.datac(\ula_|i2s_intf_|Add0~2_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|lrdivider~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|lrdivider~2 .lut_mask = 16'h5050;
|
|
defparam \ula_|i2s_intf_|lrdivider~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X23_Y32_N11
|
|
dffeas \ula_|i2s_intf_|lrdivider[1] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2s_intf_|lrdivider~2_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2s_intf_|lrdivider [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|lrdivider[1] .is_wysiwyg = "true";
|
|
defparam \ula_|i2s_intf_|lrdivider[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y32_N12
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|Add0~4 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|Add0~4_combout = (\ula_|i2s_intf_|lrdivider [2] & (\ula_|i2s_intf_|Add0~3 $ (GND))) # (!\ula_|i2s_intf_|lrdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add0~3 )))
|
|
// \ula_|i2s_intf_|Add0~5 = CARRY((!\ula_|i2s_intf_|Add0~3 ) # (!\ula_|i2s_intf_|lrdivider [2]))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|i2s_intf_|lrdivider [2]),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\ula_|i2s_intf_|Add0~3 ),
|
|
.combout(\ula_|i2s_intf_|Add0~4_combout ),
|
|
.cout(\ula_|i2s_intf_|Add0~5 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|Add0~4 .lut_mask = 16'hC33F;
|
|
defparam \ula_|i2s_intf_|Add0~4 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y32_N22
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[2]~8 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|lrdivider[2]~8_combout = !\ula_|i2s_intf_|Add0~4_combout
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\ula_|i2s_intf_|Add0~4_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|lrdivider[2]~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|lrdivider[2]~8 .lut_mask = 16'h0F0F;
|
|
defparam \ula_|i2s_intf_|lrdivider[2]~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X23_Y32_N23
|
|
dffeas \ula_|i2s_intf_|lrdivider[2] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2s_intf_|lrdivider[2]~8_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2s_intf_|lrdivider [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|lrdivider[2] .is_wysiwyg = "true";
|
|
defparam \ula_|i2s_intf_|lrdivider[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y32_N14
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|Add0~6 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|Add0~6_combout = (\ula_|i2s_intf_|lrdivider [3] & (!\ula_|i2s_intf_|Add0~5 )) # (!\ula_|i2s_intf_|lrdivider [3] & (\ula_|i2s_intf_|Add0~5 & VCC))
|
|
// \ula_|i2s_intf_|Add0~7 = CARRY((\ula_|i2s_intf_|lrdivider [3] & !\ula_|i2s_intf_|Add0~5 ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|i2s_intf_|lrdivider [3]),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\ula_|i2s_intf_|Add0~5 ),
|
|
.combout(\ula_|i2s_intf_|Add0~6_combout ),
|
|
.cout(\ula_|i2s_intf_|Add0~7 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|Add0~6 .lut_mask = 16'h3C0C;
|
|
defparam \ula_|i2s_intf_|Add0~6 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y32_N4
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[3]~7 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|lrdivider[3]~7_combout = !\ula_|i2s_intf_|Add0~6_combout
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\ula_|i2s_intf_|Add0~6_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|lrdivider[3]~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|lrdivider[3]~7 .lut_mask = 16'h00FF;
|
|
defparam \ula_|i2s_intf_|lrdivider[3]~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X23_Y32_N5
|
|
dffeas \ula_|i2s_intf_|lrdivider[3] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2s_intf_|lrdivider[3]~7_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2s_intf_|lrdivider [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|lrdivider[3] .is_wysiwyg = "true";
|
|
defparam \ula_|i2s_intf_|lrdivider[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y32_N16
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|Add0~8 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|Add0~8_combout = (\ula_|i2s_intf_|lrdivider [4] & ((GND) # (!\ula_|i2s_intf_|Add0~7 ))) # (!\ula_|i2s_intf_|lrdivider [4] & (\ula_|i2s_intf_|Add0~7 $ (GND)))
|
|
// \ula_|i2s_intf_|Add0~9 = CARRY((\ula_|i2s_intf_|lrdivider [4]) # (!\ula_|i2s_intf_|Add0~7 ))
|
|
|
|
.dataa(\ula_|i2s_intf_|lrdivider [4]),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\ula_|i2s_intf_|Add0~7 ),
|
|
.combout(\ula_|i2s_intf_|Add0~8_combout ),
|
|
.cout(\ula_|i2s_intf_|Add0~9 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|Add0~8 .lut_mask = 16'h5AAF;
|
|
defparam \ula_|i2s_intf_|Add0~8 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y32_N16
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~1 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|lrdivider~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|Add0~8_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\ula_|i2s_intf_|Equal0~2_combout ),
|
|
.datad(\ula_|i2s_intf_|Add0~8_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|lrdivider~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|lrdivider~1 .lut_mask = 16'h0F00;
|
|
defparam \ula_|i2s_intf_|lrdivider~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X23_Y32_N17
|
|
dffeas \ula_|i2s_intf_|lrdivider[4] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2s_intf_|lrdivider~1_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2s_intf_|lrdivider [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|lrdivider[4] .is_wysiwyg = "true";
|
|
defparam \ula_|i2s_intf_|lrdivider[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y32_N18
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|Add0~10 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|Add0~10_combout = (\ula_|i2s_intf_|lrdivider [5] & (!\ula_|i2s_intf_|Add0~9 )) # (!\ula_|i2s_intf_|lrdivider [5] & (\ula_|i2s_intf_|Add0~9 & VCC))
|
|
// \ula_|i2s_intf_|Add0~11 = CARRY((\ula_|i2s_intf_|lrdivider [5] & !\ula_|i2s_intf_|Add0~9 ))
|
|
|
|
.dataa(\ula_|i2s_intf_|lrdivider [5]),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\ula_|i2s_intf_|Add0~9 ),
|
|
.combout(\ula_|i2s_intf_|Add0~10_combout ),
|
|
.cout(\ula_|i2s_intf_|Add0~11 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|Add0~10 .lut_mask = 16'h5A0A;
|
|
defparam \ula_|i2s_intf_|Add0~10 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y32_N14
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[5]~6 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|lrdivider[5]~6_combout = !\ula_|i2s_intf_|Add0~10_combout
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\ula_|i2s_intf_|Add0~10_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|lrdivider[5]~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|lrdivider[5]~6 .lut_mask = 16'h00FF;
|
|
defparam \ula_|i2s_intf_|lrdivider[5]~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X23_Y32_N15
|
|
dffeas \ula_|i2s_intf_|lrdivider[5] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2s_intf_|lrdivider[5]~6_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2s_intf_|lrdivider [5]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|lrdivider[5] .is_wysiwyg = "true";
|
|
defparam \ula_|i2s_intf_|lrdivider[5] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y32_N0
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~1 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|Equal0~1_combout = (!\ula_|i2s_intf_|lrdivider [4] & (\ula_|i2s_intf_|lrdivider [2] & (\ula_|i2s_intf_|lrdivider [3] & \ula_|i2s_intf_|lrdivider [5])))
|
|
|
|
.dataa(\ula_|i2s_intf_|lrdivider [4]),
|
|
.datab(\ula_|i2s_intf_|lrdivider [2]),
|
|
.datac(\ula_|i2s_intf_|lrdivider [3]),
|
|
.datad(\ula_|i2s_intf_|lrdivider [5]),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|Equal0~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|Equal0~1 .lut_mask = 16'h4000;
|
|
defparam \ula_|i2s_intf_|Equal0~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y32_N20
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|Add0~12 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|Add0~12_combout = (\ula_|i2s_intf_|lrdivider [6] & (\ula_|i2s_intf_|Add0~11 $ (GND))) # (!\ula_|i2s_intf_|lrdivider [6] & ((GND) # (!\ula_|i2s_intf_|Add0~11 )))
|
|
// \ula_|i2s_intf_|Add0~13 = CARRY((!\ula_|i2s_intf_|Add0~11 ) # (!\ula_|i2s_intf_|lrdivider [6]))
|
|
|
|
.dataa(\ula_|i2s_intf_|lrdivider [6]),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\ula_|i2s_intf_|Add0~11 ),
|
|
.combout(\ula_|i2s_intf_|Add0~12_combout ),
|
|
.cout(\ula_|i2s_intf_|Add0~13 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|Add0~12 .lut_mask = 16'hA55F;
|
|
defparam \ula_|i2s_intf_|Add0~12 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y32_N0
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[6]~5 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|lrdivider[6]~5_combout = !\ula_|i2s_intf_|Add0~12_combout
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\ula_|i2s_intf_|Add0~12_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|lrdivider[6]~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|lrdivider[6]~5 .lut_mask = 16'h0F0F;
|
|
defparam \ula_|i2s_intf_|lrdivider[6]~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X23_Y32_N1
|
|
dffeas \ula_|i2s_intf_|lrdivider[6] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2s_intf_|lrdivider[6]~5_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2s_intf_|lrdivider [6]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|lrdivider[6] .is_wysiwyg = "true";
|
|
defparam \ula_|i2s_intf_|lrdivider[6] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y32_N22
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|Add0~14 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|Add0~14_combout = (\ula_|i2s_intf_|lrdivider [7] & (!\ula_|i2s_intf_|Add0~13 )) # (!\ula_|i2s_intf_|lrdivider [7] & (\ula_|i2s_intf_|Add0~13 & VCC))
|
|
// \ula_|i2s_intf_|Add0~15 = CARRY((\ula_|i2s_intf_|lrdivider [7] & !\ula_|i2s_intf_|Add0~13 ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|i2s_intf_|lrdivider [7]),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\ula_|i2s_intf_|Add0~13 ),
|
|
.combout(\ula_|i2s_intf_|Add0~14_combout ),
|
|
.cout(\ula_|i2s_intf_|Add0~15 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|Add0~14 .lut_mask = 16'h3C0C;
|
|
defparam \ula_|i2s_intf_|Add0~14 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y32_N2
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[7]~4 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|lrdivider[7]~4_combout = !\ula_|i2s_intf_|Add0~14_combout
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\ula_|i2s_intf_|Add0~14_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|lrdivider[7]~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|lrdivider[7]~4 .lut_mask = 16'h0F0F;
|
|
defparam \ula_|i2s_intf_|lrdivider[7]~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X24_Y32_N3
|
|
dffeas \ula_|i2s_intf_|lrdivider[7] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2s_intf_|lrdivider[7]~4_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2s_intf_|lrdivider [7]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|lrdivider[7] .is_wysiwyg = "true";
|
|
defparam \ula_|i2s_intf_|lrdivider[7] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y32_N24
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|Add0~16 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|Add0~16_combout = (\ula_|i2s_intf_|lrdivider [8] & ((GND) # (!\ula_|i2s_intf_|Add0~15 ))) # (!\ula_|i2s_intf_|lrdivider [8] & (\ula_|i2s_intf_|Add0~15 $ (GND)))
|
|
// \ula_|i2s_intf_|Add0~17 = CARRY((\ula_|i2s_intf_|lrdivider [8]) # (!\ula_|i2s_intf_|Add0~15 ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|i2s_intf_|lrdivider [8]),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\ula_|i2s_intf_|Add0~15 ),
|
|
.combout(\ula_|i2s_intf_|Add0~16_combout ),
|
|
.cout(\ula_|i2s_intf_|Add0~17 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|Add0~16 .lut_mask = 16'h3CCF;
|
|
defparam \ula_|i2s_intf_|Add0~16 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y32_N28
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider~0 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|lrdivider~0_combout = (\ula_|i2s_intf_|Add0~16_combout & !\ula_|i2s_intf_|Equal0~2_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|i2s_intf_|Add0~16_combout ),
|
|
.datac(\ula_|i2s_intf_|Equal0~2_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|lrdivider~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|lrdivider~0 .lut_mask = 16'h0C0C;
|
|
defparam \ula_|i2s_intf_|lrdivider~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X24_Y32_N29
|
|
dffeas \ula_|i2s_intf_|lrdivider[8] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2s_intf_|lrdivider~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2s_intf_|lrdivider [8]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|lrdivider[8] .is_wysiwyg = "true";
|
|
defparam \ula_|i2s_intf_|lrdivider[8] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y32_N26
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|Add0~18 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|Add0~18_combout = \ula_|i2s_intf_|lrdivider [9] $ (\ula_|i2s_intf_|Add0~17 )
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|i2s_intf_|lrdivider [9]),
|
|
.datac(gnd),
|
|
.datad(gnd),
|
|
.cin(\ula_|i2s_intf_|Add0~17 ),
|
|
.combout(\ula_|i2s_intf_|Add0~18_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|Add0~18 .lut_mask = 16'h3C3C;
|
|
defparam \ula_|i2s_intf_|Add0~18 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y32_N4
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|lrdivider[9]~3 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|lrdivider[9]~3_combout = !\ula_|i2s_intf_|Add0~18_combout
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\ula_|i2s_intf_|Add0~18_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|lrdivider[9]~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|lrdivider[9]~3 .lut_mask = 16'h0F0F;
|
|
defparam \ula_|i2s_intf_|lrdivider[9]~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X24_Y32_N5
|
|
dffeas \ula_|i2s_intf_|lrdivider[9] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2s_intf_|lrdivider[9]~3_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2s_intf_|lrdivider [9]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|lrdivider[9] .is_wysiwyg = "true";
|
|
defparam \ula_|i2s_intf_|lrdivider[9] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y32_N6
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~0 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|Equal0~0_combout = (\ula_|i2s_intf_|lrdivider [6] & (!\ula_|i2s_intf_|lrdivider [8] & (\ula_|i2s_intf_|lrdivider [9] & \ula_|i2s_intf_|lrdivider [7])))
|
|
|
|
.dataa(\ula_|i2s_intf_|lrdivider [6]),
|
|
.datab(\ula_|i2s_intf_|lrdivider [8]),
|
|
.datac(\ula_|i2s_intf_|lrdivider [9]),
|
|
.datad(\ula_|i2s_intf_|lrdivider [7]),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|Equal0~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|Equal0~0 .lut_mask = 16'h2000;
|
|
defparam \ula_|i2s_intf_|Equal0~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y32_N30
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|Equal0~2 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|Equal0~2_combout = (!\ula_|i2s_intf_|lrdivider [1] & (\ula_|i2s_intf_|Equal0~1_combout & (\ula_|i2s_intf_|mclk_r~_Duplicate_1_q & \ula_|i2s_intf_|Equal0~0_combout )))
|
|
|
|
.dataa(\ula_|i2s_intf_|lrdivider [1]),
|
|
.datab(\ula_|i2s_intf_|Equal0~1_combout ),
|
|
.datac(\ula_|i2s_intf_|mclk_r~_Duplicate_1_q ),
|
|
.datad(\ula_|i2s_intf_|Equal0~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|Equal0~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|Equal0~2 .lut_mask = 16'h4000;
|
|
defparam \ula_|i2s_intf_|Equal0~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X23_Y31_N5
|
|
dffeas \ula_|i2s_intf_|lrclk_r~_Duplicate_2 (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2s_intf_|lrclk_r~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .is_wysiwyg = "true";
|
|
defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_2 .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y31_N4
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|lrclk_r~0 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|lrclk_r~0_combout = \ula_|i2s_intf_|Equal0~2_combout $ (\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q )
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|i2s_intf_|Equal0~2_combout ),
|
|
.datac(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|lrclk_r~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|lrclk_r~0 .lut_mask = 16'h3C3C;
|
|
defparam \ula_|i2s_intf_|lrclk_r~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: DDIOOUTCELL_X16_Y34_N18
|
|
dffeas \ula_|i2s_intf_|lrclk_r (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2s_intf_|lrclk_r~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2s_intf_|lrclk_r~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|lrclk_r .is_wysiwyg = "true";
|
|
defparam \ula_|i2s_intf_|lrclk_r .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: DDIOOUTCELL_X18_Y34_N25
|
|
dffeas \ula_|i2s_intf_|lrclk_r~_Duplicate_1 (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2s_intf_|lrclk_r~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2s_intf_|lrclk_r~_Duplicate_1_q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_1 .is_wysiwyg = "true";
|
|
defparam \ula_|i2s_intf_|lrclk_r~_Duplicate_1 .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y31_N0
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[0]~5 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|bitcount[0]~5_combout = !\ula_|i2s_intf_|bitcount [0]
|
|
// \ula_|i2s_intf_|bitcount[0]~6 = CARRY(!\ula_|i2s_intf_|bitcount [0])
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|i2s_intf_|bitcount [0]),
|
|
.datac(gnd),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|bitcount[0]~5_combout ),
|
|
.cout(\ula_|i2s_intf_|bitcount[0]~6 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|bitcount[0]~5 .lut_mask = 16'h3333;
|
|
defparam \ula_|i2s_intf_|bitcount[0]~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y31_N26
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout = \ula_|i2s_intf_|bclk_r~1_combout
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\ula_|i2s_intf_|bclk_r~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder .lut_mask = 16'hFF00;
|
|
defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X25_Y31_N27
|
|
dffeas \ula_|i2s_intf_|bclk_r~_Duplicate_1 (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2s_intf_|bclk_r~_Duplicate_1feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .is_wysiwyg = "true";
|
|
defparam \ula_|i2s_intf_|bclk_r~_Duplicate_1 .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y31_N22
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~15 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|bitcount[4]~15_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((!\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & \ula_|i2s_intf_|shiftreg[4]~1_combout ))
|
|
|
|
.dataa(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ),
|
|
.datab(gnd),
|
|
.datac(\ula_|i2s_intf_|Equal0~2_combout ),
|
|
.datad(\ula_|i2s_intf_|shiftreg[4]~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|bitcount[4]~15_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|bitcount[4]~15 .lut_mask = 16'hF5F0;
|
|
defparam \ula_|i2s_intf_|bitcount[4]~15 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X25_Y31_N1
|
|
dffeas \ula_|i2s_intf_|bitcount[0] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2s_intf_|bitcount[0]~5_combout ),
|
|
.asdata(\~GND~combout ),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(\ula_|i2s_intf_|Equal0~2_combout ),
|
|
.ena(\ula_|i2s_intf_|bitcount[4]~15_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2s_intf_|bitcount [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|bitcount[0] .is_wysiwyg = "true";
|
|
defparam \ula_|i2s_intf_|bitcount[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y31_N2
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[1]~7 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|bitcount[1]~7_combout = (\ula_|i2s_intf_|bitcount [1] & (\ula_|i2s_intf_|bitcount[0]~6 & VCC)) # (!\ula_|i2s_intf_|bitcount [1] & (!\ula_|i2s_intf_|bitcount[0]~6 ))
|
|
// \ula_|i2s_intf_|bitcount[1]~8 = CARRY((!\ula_|i2s_intf_|bitcount [1] & !\ula_|i2s_intf_|bitcount[0]~6 ))
|
|
|
|
.dataa(\ula_|i2s_intf_|bitcount [1]),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\ula_|i2s_intf_|bitcount[0]~6 ),
|
|
.combout(\ula_|i2s_intf_|bitcount[1]~7_combout ),
|
|
.cout(\ula_|i2s_intf_|bitcount[1]~8 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|bitcount[1]~7 .lut_mask = 16'hA505;
|
|
defparam \ula_|i2s_intf_|bitcount[1]~7 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X25_Y31_N3
|
|
dffeas \ula_|i2s_intf_|bitcount[1] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2s_intf_|bitcount[1]~7_combout ),
|
|
.asdata(\~GND~combout ),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(\ula_|i2s_intf_|Equal0~2_combout ),
|
|
.ena(\ula_|i2s_intf_|bitcount[4]~15_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2s_intf_|bitcount [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|bitcount[1] .is_wysiwyg = "true";
|
|
defparam \ula_|i2s_intf_|bitcount[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y31_N4
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[2]~9 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|bitcount[2]~9_combout = (\ula_|i2s_intf_|bitcount [2] & ((GND) # (!\ula_|i2s_intf_|bitcount[1]~8 ))) # (!\ula_|i2s_intf_|bitcount [2] & (\ula_|i2s_intf_|bitcount[1]~8 $ (GND)))
|
|
// \ula_|i2s_intf_|bitcount[2]~10 = CARRY((\ula_|i2s_intf_|bitcount [2]) # (!\ula_|i2s_intf_|bitcount[1]~8 ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|i2s_intf_|bitcount [2]),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\ula_|i2s_intf_|bitcount[1]~8 ),
|
|
.combout(\ula_|i2s_intf_|bitcount[2]~9_combout ),
|
|
.cout(\ula_|i2s_intf_|bitcount[2]~10 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|bitcount[2]~9 .lut_mask = 16'h3CCF;
|
|
defparam \ula_|i2s_intf_|bitcount[2]~9 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X25_Y31_N5
|
|
dffeas \ula_|i2s_intf_|bitcount[2] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2s_intf_|bitcount[2]~9_combout ),
|
|
.asdata(\~GND~combout ),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(\ula_|i2s_intf_|Equal0~2_combout ),
|
|
.ena(\ula_|i2s_intf_|bitcount[4]~15_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2s_intf_|bitcount [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|bitcount[2] .is_wysiwyg = "true";
|
|
defparam \ula_|i2s_intf_|bitcount[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y31_N6
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[3]~11 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|bitcount[3]~11_combout = (\ula_|i2s_intf_|bitcount [3] & (\ula_|i2s_intf_|bitcount[2]~10 & VCC)) # (!\ula_|i2s_intf_|bitcount [3] & (!\ula_|i2s_intf_|bitcount[2]~10 ))
|
|
// \ula_|i2s_intf_|bitcount[3]~12 = CARRY((!\ula_|i2s_intf_|bitcount [3] & !\ula_|i2s_intf_|bitcount[2]~10 ))
|
|
|
|
.dataa(\ula_|i2s_intf_|bitcount [3]),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\ula_|i2s_intf_|bitcount[2]~10 ),
|
|
.combout(\ula_|i2s_intf_|bitcount[3]~11_combout ),
|
|
.cout(\ula_|i2s_intf_|bitcount[3]~12 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|bitcount[3]~11 .lut_mask = 16'hA505;
|
|
defparam \ula_|i2s_intf_|bitcount[3]~11 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X25_Y31_N7
|
|
dffeas \ula_|i2s_intf_|bitcount[3] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2s_intf_|bitcount[3]~11_combout ),
|
|
.asdata(\~GND~combout ),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(\ula_|i2s_intf_|Equal0~2_combout ),
|
|
.ena(\ula_|i2s_intf_|bitcount[4]~15_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2s_intf_|bitcount [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|bitcount[3] .is_wysiwyg = "true";
|
|
defparam \ula_|i2s_intf_|bitcount[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y31_N8
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|bitcount[4]~13 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|bitcount[4]~13_combout = \ula_|i2s_intf_|bitcount [4] $ (\ula_|i2s_intf_|bitcount[3]~12 )
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|i2s_intf_|bitcount [4]),
|
|
.datac(gnd),
|
|
.datad(gnd),
|
|
.cin(\ula_|i2s_intf_|bitcount[3]~12 ),
|
|
.combout(\ula_|i2s_intf_|bitcount[4]~13_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|bitcount[4]~13 .lut_mask = 16'h3C3C;
|
|
defparam \ula_|i2s_intf_|bitcount[4]~13 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X25_Y31_N9
|
|
dffeas \ula_|i2s_intf_|bitcount[4] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2s_intf_|bitcount[4]~13_combout ),
|
|
.asdata(\~GND~combout ),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(\ula_|i2s_intf_|Equal0~2_combout ),
|
|
.ena(\ula_|i2s_intf_|bitcount[4]~15_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2s_intf_|bitcount [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|bitcount[4] .is_wysiwyg = "true";
|
|
defparam \ula_|i2s_intf_|bitcount[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y31_N20
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|LessThan0~0 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|LessThan0~0_combout = (\ula_|i2s_intf_|bitcount [1]) # (((\ula_|i2s_intf_|bitcount [2]) # (\ula_|i2s_intf_|bitcount [3])) # (!\ula_|i2s_intf_|bitcount [0]))
|
|
|
|
.dataa(\ula_|i2s_intf_|bitcount [1]),
|
|
.datab(\ula_|i2s_intf_|bitcount [0]),
|
|
.datac(\ula_|i2s_intf_|bitcount [2]),
|
|
.datad(\ula_|i2s_intf_|bitcount [3]),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|LessThan0~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|LessThan0~0 .lut_mask = 16'hFFFB;
|
|
defparam \ula_|i2s_intf_|LessThan0~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y31_N10
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[4]~1 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|shiftreg[4]~1_combout = (\ula_|i2s_intf_|bdivider [0] & (\ula_|i2s_intf_|Equal1~0_combout & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4]))))
|
|
|
|
.dataa(\ula_|i2s_intf_|bdivider [0]),
|
|
.datab(\ula_|i2s_intf_|Equal1~0_combout ),
|
|
.datac(\ula_|i2s_intf_|bitcount [4]),
|
|
.datad(\ula_|i2s_intf_|LessThan0~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|shiftreg[4]~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|shiftreg[4]~1 .lut_mask = 16'h8808;
|
|
defparam \ula_|i2s_intf_|shiftreg[4]~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y31_N12
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|Add2~18 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|Add2~18_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (!\ula_|i2s_intf_|shiftreg[4]~1_combout & ((\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0]))))
|
|
|
|
.dataa(\ula_|i2s_intf_|Equal0~2_combout ),
|
|
.datab(\ula_|i2s_intf_|shiftreg[4]~1_combout ),
|
|
.datac(\ula_|i2s_intf_|bdivider [0]),
|
|
.datad(\ula_|i2s_intf_|Equal1~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|Add2~18_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|Add2~18 .lut_mask = 16'h1101;
|
|
defparam \ula_|i2s_intf_|Add2~18 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X24_Y31_N13
|
|
dffeas \ula_|i2s_intf_|bdivider[0] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2s_intf_|Add2~18_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2s_intf_|bdivider [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|bdivider[0] .is_wysiwyg = "true";
|
|
defparam \ula_|i2s_intf_|bdivider[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y31_N2
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|Add2~7 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|Add2~7_cout = CARRY(!\ula_|i2s_intf_|bdivider [0])
|
|
|
|
.dataa(\ula_|i2s_intf_|bdivider [0]),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(gnd),
|
|
.combout(),
|
|
.cout(\ula_|i2s_intf_|Add2~7_cout ));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|Add2~7 .lut_mask = 16'h0055;
|
|
defparam \ula_|i2s_intf_|Add2~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y31_N4
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|Add2~8 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|Add2~8_combout = (\ula_|i2s_intf_|bdivider [1] & (\ula_|i2s_intf_|Add2~7_cout & VCC)) # (!\ula_|i2s_intf_|bdivider [1] & (!\ula_|i2s_intf_|Add2~7_cout ))
|
|
// \ula_|i2s_intf_|Add2~9 = CARRY((!\ula_|i2s_intf_|bdivider [1] & !\ula_|i2s_intf_|Add2~7_cout ))
|
|
|
|
.dataa(\ula_|i2s_intf_|bdivider [1]),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\ula_|i2s_intf_|Add2~7_cout ),
|
|
.combout(\ula_|i2s_intf_|Add2~8_combout ),
|
|
.cout(\ula_|i2s_intf_|Add2~9 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|Add2~8 .lut_mask = 16'hA505;
|
|
defparam \ula_|i2s_intf_|Add2~8 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y31_N22
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|Add2~20 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|Add2~20_combout = (\ula_|i2s_intf_|Add2~8_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0]))))
|
|
|
|
.dataa(\ula_|i2s_intf_|bdivider [0]),
|
|
.datab(\ula_|i2s_intf_|Add2~8_combout ),
|
|
.datac(\ula_|i2s_intf_|Equal0~2_combout ),
|
|
.datad(\ula_|i2s_intf_|Equal1~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|Add2~20_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|Add2~20 .lut_mask = 16'h040C;
|
|
defparam \ula_|i2s_intf_|Add2~20 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X24_Y31_N23
|
|
dffeas \ula_|i2s_intf_|bdivider[1] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2s_intf_|Add2~20_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2s_intf_|bdivider [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|bdivider[1] .is_wysiwyg = "true";
|
|
defparam \ula_|i2s_intf_|bdivider[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y31_N6
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|Add2~10 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|Add2~10_combout = (\ula_|i2s_intf_|bdivider [2] & (\ula_|i2s_intf_|Add2~9 $ (GND))) # (!\ula_|i2s_intf_|bdivider [2] & ((GND) # (!\ula_|i2s_intf_|Add2~9 )))
|
|
// \ula_|i2s_intf_|Add2~11 = CARRY((!\ula_|i2s_intf_|Add2~9 ) # (!\ula_|i2s_intf_|bdivider [2]))
|
|
|
|
.dataa(\ula_|i2s_intf_|bdivider [2]),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\ula_|i2s_intf_|Add2~9 ),
|
|
.combout(\ula_|i2s_intf_|Add2~10_combout ),
|
|
.cout(\ula_|i2s_intf_|Add2~11 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|Add2~10 .lut_mask = 16'hA55F;
|
|
defparam \ula_|i2s_intf_|Add2~10 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y31_N26
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|Add2~17 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|Add2~17_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (!\ula_|i2s_intf_|shiftreg[4]~1_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~10_combout ))))
|
|
|
|
.dataa(\ula_|i2s_intf_|Equal0~2_combout ),
|
|
.datab(\ula_|i2s_intf_|Equal1~1_combout ),
|
|
.datac(\ula_|i2s_intf_|shiftreg[4]~1_combout ),
|
|
.datad(\ula_|i2s_intf_|Add2~10_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|Add2~17_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|Add2~17 .lut_mask = 16'h0405;
|
|
defparam \ula_|i2s_intf_|Add2~17 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X24_Y31_N27
|
|
dffeas \ula_|i2s_intf_|bdivider[2] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2s_intf_|Add2~17_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2s_intf_|bdivider [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|bdivider[2] .is_wysiwyg = "true";
|
|
defparam \ula_|i2s_intf_|bdivider[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y31_N8
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|Add2~12 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|Add2~12_combout = (\ula_|i2s_intf_|bdivider [3] & (\ula_|i2s_intf_|Add2~11 & VCC)) # (!\ula_|i2s_intf_|bdivider [3] & (!\ula_|i2s_intf_|Add2~11 ))
|
|
// \ula_|i2s_intf_|Add2~13 = CARRY((!\ula_|i2s_intf_|bdivider [3] & !\ula_|i2s_intf_|Add2~11 ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|i2s_intf_|bdivider [3]),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\ula_|i2s_intf_|Add2~11 ),
|
|
.combout(\ula_|i2s_intf_|Add2~12_combout ),
|
|
.cout(\ula_|i2s_intf_|Add2~13 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|Add2~12 .lut_mask = 16'hC303;
|
|
defparam \ula_|i2s_intf_|Add2~12 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y31_N0
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|Add2~19 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|Add2~19_combout = (\ula_|i2s_intf_|Add2~12_combout & (!\ula_|i2s_intf_|Equal0~2_combout & ((!\ula_|i2s_intf_|Equal1~0_combout ) # (!\ula_|i2s_intf_|bdivider [0]))))
|
|
|
|
.dataa(\ula_|i2s_intf_|bdivider [0]),
|
|
.datab(\ula_|i2s_intf_|Add2~12_combout ),
|
|
.datac(\ula_|i2s_intf_|Equal0~2_combout ),
|
|
.datad(\ula_|i2s_intf_|Equal1~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|Add2~19_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|Add2~19 .lut_mask = 16'h040C;
|
|
defparam \ula_|i2s_intf_|Add2~19 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X24_Y31_N1
|
|
dffeas \ula_|i2s_intf_|bdivider[3] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2s_intf_|Add2~19_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2s_intf_|bdivider [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|bdivider[3] .is_wysiwyg = "true";
|
|
defparam \ula_|i2s_intf_|bdivider[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y31_N10
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|Add2~14 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|Add2~14_combout = \ula_|i2s_intf_|Add2~13 $ (!\ula_|i2s_intf_|bdivider [4])
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\ula_|i2s_intf_|bdivider [4]),
|
|
.cin(\ula_|i2s_intf_|Add2~13 ),
|
|
.combout(\ula_|i2s_intf_|Add2~14_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|Add2~14 .lut_mask = 16'hF00F;
|
|
defparam \ula_|i2s_intf_|Add2~14 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y31_N28
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|Add2~16 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|Add2~16_combout = (!\ula_|i2s_intf_|Equal0~2_combout & (!\ula_|i2s_intf_|shiftreg[4]~1_combout & ((\ula_|i2s_intf_|Equal1~1_combout ) # (!\ula_|i2s_intf_|Add2~14_combout ))))
|
|
|
|
.dataa(\ula_|i2s_intf_|Equal0~2_combout ),
|
|
.datab(\ula_|i2s_intf_|Equal1~1_combout ),
|
|
.datac(\ula_|i2s_intf_|shiftreg[4]~1_combout ),
|
|
.datad(\ula_|i2s_intf_|Add2~14_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|Add2~16_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|Add2~16 .lut_mask = 16'h0405;
|
|
defparam \ula_|i2s_intf_|Add2~16 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X24_Y31_N29
|
|
dffeas \ula_|i2s_intf_|bdivider[4] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2s_intf_|Add2~16_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2s_intf_|bdivider [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|bdivider[4] .is_wysiwyg = "true";
|
|
defparam \ula_|i2s_intf_|bdivider[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y31_N20
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~0 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|Equal1~0_combout = (!\ula_|i2s_intf_|bdivider [1] & (\ula_|i2s_intf_|bdivider [4] & (\ula_|i2s_intf_|bdivider [2] & !\ula_|i2s_intf_|bdivider [3])))
|
|
|
|
.dataa(\ula_|i2s_intf_|bdivider [1]),
|
|
.datab(\ula_|i2s_intf_|bdivider [4]),
|
|
.datac(\ula_|i2s_intf_|bdivider [2]),
|
|
.datad(\ula_|i2s_intf_|bdivider [3]),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|Equal1~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|Equal1~0 .lut_mask = 16'h0040;
|
|
defparam \ula_|i2s_intf_|Equal1~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y31_N14
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|Equal1~1 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|Equal1~1_combout = (\ula_|i2s_intf_|Equal1~0_combout & \ula_|i2s_intf_|bdivider [0])
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|i2s_intf_|Equal1~0_combout ),
|
|
.datac(gnd),
|
|
.datad(\ula_|i2s_intf_|bdivider [0]),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|Equal1~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|Equal1~1 .lut_mask = 16'hCC00;
|
|
defparam \ula_|i2s_intf_|Equal1~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y31_N18
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~0 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|bclk_r~0_combout = \ula_|i2s_intf_|bclk_r~_Duplicate_1_q $ (((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4])))
|
|
|
|
.dataa(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ),
|
|
.datab(\ula_|i2s_intf_|LessThan0~0_combout ),
|
|
.datac(\ula_|i2s_intf_|bitcount [4]),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|bclk_r~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|bclk_r~0 .lut_mask = 16'h6565;
|
|
defparam \ula_|i2s_intf_|bclk_r~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y31_N24
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|bclk_r~1 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|bclk_r~1_combout = (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|Equal1~1_combout & ((\ula_|i2s_intf_|bclk_r~0_combout ))) # (!\ula_|i2s_intf_|Equal1~1_combout & (\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ))))
|
|
|
|
.dataa(\ula_|i2s_intf_|Equal1~1_combout ),
|
|
.datab(\ula_|i2s_intf_|Equal0~2_combout ),
|
|
.datac(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ),
|
|
.datad(\ula_|i2s_intf_|bclk_r~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|bclk_r~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|bclk_r~1 .lut_mask = 16'h3210;
|
|
defparam \ula_|i2s_intf_|bclk_r~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: DDIOOUTCELL_X14_Y34_N18
|
|
dffeas \ula_|i2s_intf_|bclk_r (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2s_intf_|bclk_r~1_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2s_intf_|bclk_r~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|bclk_r .is_wysiwyg = "true";
|
|
defparam \ula_|i2s_intf_|bclk_r .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y11_N14
|
|
cycloneive_lcell_comb \ula_|always0~2 (
|
|
// Equation(s):
|
|
// \ula_|always0~2_combout = (!\z80_|memory_ifc_|nRD_out~2_combout & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \z80_|memory_ifc_|nWR_out~0_combout ))
|
|
|
|
.dataa(\z80_|memory_ifc_|nRD_out~2_combout ),
|
|
.datab(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.datac(gnd),
|
|
.datad(\z80_|memory_ifc_|nWR_out~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|always0~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|always0~2 .lut_mask = 16'h4400;
|
|
defparam \ula_|always0~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X29_Y11_N26
|
|
cycloneive_lcell_comb \ula_|always0~3 (
|
|
// Equation(s):
|
|
// \ula_|always0~3_combout = (\z80_|memory_ifc_|nIORQ_out~0_combout & (!\z80_|address_pins_|DFFE_apin_latch [0] & (\z80_|resets_|SYNTHESIZED_WIRE_12~q & \ula_|always0~2_combout )))
|
|
|
|
.dataa(\z80_|memory_ifc_|nIORQ_out~0_combout ),
|
|
.datab(\z80_|address_pins_|DFFE_apin_latch [0]),
|
|
.datac(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.datad(\ula_|always0~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|always0~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|always0~3 .lut_mask = 16'h2000;
|
|
defparam \ula_|always0~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X31_Y10_N31
|
|
dffeas \ula_|pcm_outl[14] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\D[4]~76_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|always0~3_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|pcm_outl [14]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|pcm_outl[14] .is_wysiwyg = "true";
|
|
defparam \ula_|pcm_outl[14] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y31_N16
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~19 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|shiftreg[0]~19_combout = (\ula_|i2s_intf_|Equal1~1_combout & (!\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & ((\ula_|i2s_intf_|LessThan0~0_combout ) # (!\ula_|i2s_intf_|bitcount [4]))))
|
|
|
|
.dataa(\ula_|i2s_intf_|Equal1~1_combout ),
|
|
.datab(\ula_|i2s_intf_|bitcount [4]),
|
|
.datac(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ),
|
|
.datad(\ula_|i2s_intf_|LessThan0~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|shiftreg[0]~19_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|shiftreg[0]~19 .lut_mask = 16'h0A02;
|
|
defparam \ula_|i2s_intf_|shiftreg[0]~19 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOIBUF_X23_Y34_N22
|
|
cycloneive_io_ibuf \AUD_ADCDAT~input (
|
|
.i(AUD_ADCDAT),
|
|
.ibar(gnd),
|
|
.o(\AUD_ADCDAT~input_o ));
|
|
// synopsys translate_off
|
|
defparam \AUD_ADCDAT~input .bus_hold = "false";
|
|
defparam \AUD_ADCDAT~input .simulate_z_as = "z";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y31_N18
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[0]~20 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|shiftreg[0]~20_combout = (\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|shiftreg [0])))) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg[0]~19_combout & ((\AUD_ADCDAT~input_o ))) #
|
|
// (!\ula_|i2s_intf_|shiftreg[0]~19_combout & (\ula_|i2s_intf_|shiftreg [0]))))
|
|
|
|
.dataa(\ula_|i2s_intf_|Equal0~2_combout ),
|
|
.datab(\ula_|i2s_intf_|shiftreg[0]~19_combout ),
|
|
.datac(\ula_|i2s_intf_|shiftreg [0]),
|
|
.datad(\AUD_ADCDAT~input_o ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|shiftreg[0]~20_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|shiftreg[0]~20 .lut_mask = 16'hF4B0;
|
|
defparam \ula_|i2s_intf_|shiftreg[0]~20 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X24_Y31_N19
|
|
dffeas \ula_|i2s_intf_|shiftreg[0] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2s_intf_|shiftreg[0]~20_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2s_intf_|shiftreg [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|shiftreg[0] .is_wysiwyg = "true";
|
|
defparam \ula_|i2s_intf_|shiftreg[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y31_N26
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~18 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|shiftreg~18_combout = (\ula_|i2s_intf_|shiftreg [0] & !\ula_|i2s_intf_|Equal0~2_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|i2s_intf_|shiftreg [0]),
|
|
.datac(\ula_|i2s_intf_|Equal0~2_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|shiftreg~18_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|shiftreg~18 .lut_mask = 16'h0C0C;
|
|
defparam \ula_|i2s_intf_|shiftreg~18 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X25_Y31_N28
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg[4]~2 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|shiftreg[4]~2_combout = (\ula_|i2s_intf_|Equal0~2_combout ) # ((\ula_|i2s_intf_|bclk_r~_Duplicate_1_q & \ula_|i2s_intf_|shiftreg[4]~1_combout ))
|
|
|
|
.dataa(\ula_|i2s_intf_|bclk_r~_Duplicate_1_q ),
|
|
.datab(gnd),
|
|
.datac(\ula_|i2s_intf_|Equal0~2_combout ),
|
|
.datad(\ula_|i2s_intf_|shiftreg[4]~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|shiftreg[4]~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|shiftreg[4]~2 .lut_mask = 16'hFAF0;
|
|
defparam \ula_|i2s_intf_|shiftreg[4]~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X23_Y31_N27
|
|
dffeas \ula_|i2s_intf_|shiftreg[1] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2s_intf_|shiftreg~18_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2s_intf_|shiftreg [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|shiftreg[1] .is_wysiwyg = "true";
|
|
defparam \ula_|i2s_intf_|shiftreg[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y31_N12
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~17 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|shiftreg~17_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [1])
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|i2s_intf_|Equal0~2_combout ),
|
|
.datac(\ula_|i2s_intf_|shiftreg [1]),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|shiftreg~17_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|shiftreg~17 .lut_mask = 16'h3030;
|
|
defparam \ula_|i2s_intf_|shiftreg~17 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X23_Y31_N13
|
|
dffeas \ula_|i2s_intf_|shiftreg[2] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2s_intf_|shiftreg~17_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2s_intf_|shiftreg [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|shiftreg[2] .is_wysiwyg = "true";
|
|
defparam \ula_|i2s_intf_|shiftreg[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y31_N22
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~16 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|shiftreg~16_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [2])
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\ula_|i2s_intf_|Equal0~2_combout ),
|
|
.datad(\ula_|i2s_intf_|shiftreg [2]),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|shiftreg~16_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|shiftreg~16 .lut_mask = 16'h0F00;
|
|
defparam \ula_|i2s_intf_|shiftreg~16 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X23_Y31_N23
|
|
dffeas \ula_|i2s_intf_|shiftreg[3] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2s_intf_|shiftreg~16_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2s_intf_|shiftreg [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|shiftreg[3] .is_wysiwyg = "true";
|
|
defparam \ula_|i2s_intf_|shiftreg[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y31_N0
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~15 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|shiftreg~15_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [3])
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|i2s_intf_|Equal0~2_combout ),
|
|
.datac(\ula_|i2s_intf_|shiftreg [3]),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|shiftreg~15_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|shiftreg~15 .lut_mask = 16'h3030;
|
|
defparam \ula_|i2s_intf_|shiftreg~15 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X23_Y31_N1
|
|
dffeas \ula_|i2s_intf_|shiftreg[4] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2s_intf_|shiftreg~15_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2s_intf_|shiftreg [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|shiftreg[4] .is_wysiwyg = "true";
|
|
defparam \ula_|i2s_intf_|shiftreg[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y31_N14
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~14 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|shiftreg~14_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [4])
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\ula_|i2s_intf_|Equal0~2_combout ),
|
|
.datad(\ula_|i2s_intf_|shiftreg [4]),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|shiftreg~14_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|shiftreg~14 .lut_mask = 16'h0F00;
|
|
defparam \ula_|i2s_intf_|shiftreg~14 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X23_Y31_N15
|
|
dffeas \ula_|i2s_intf_|shiftreg[5] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2s_intf_|shiftreg~14_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2s_intf_|shiftreg [5]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|shiftreg[5] .is_wysiwyg = "true";
|
|
defparam \ula_|i2s_intf_|shiftreg[5] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y31_N24
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~13 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|shiftreg~13_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [5])
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|i2s_intf_|Equal0~2_combout ),
|
|
.datac(\ula_|i2s_intf_|shiftreg [5]),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|shiftreg~13_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|shiftreg~13 .lut_mask = 16'h3030;
|
|
defparam \ula_|i2s_intf_|shiftreg~13 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X23_Y31_N25
|
|
dffeas \ula_|i2s_intf_|shiftreg[6] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2s_intf_|shiftreg~13_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2s_intf_|shiftreg [6]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|shiftreg[6] .is_wysiwyg = "true";
|
|
defparam \ula_|i2s_intf_|shiftreg[6] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y31_N30
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~12 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|shiftreg~12_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [6])
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\ula_|i2s_intf_|Equal0~2_combout ),
|
|
.datad(\ula_|i2s_intf_|shiftreg [6]),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|shiftreg~12_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|shiftreg~12 .lut_mask = 16'h0F00;
|
|
defparam \ula_|i2s_intf_|shiftreg~12 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X23_Y31_N31
|
|
dffeas \ula_|i2s_intf_|shiftreg[7] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2s_intf_|shiftreg~12_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2s_intf_|shiftreg [7]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|shiftreg[7] .is_wysiwyg = "true";
|
|
defparam \ula_|i2s_intf_|shiftreg[7] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y31_N20
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~11 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|shiftreg~11_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [7])
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|i2s_intf_|Equal0~2_combout ),
|
|
.datac(\ula_|i2s_intf_|shiftreg [7]),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|shiftreg~11_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|shiftreg~11 .lut_mask = 16'h3030;
|
|
defparam \ula_|i2s_intf_|shiftreg~11 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X23_Y31_N21
|
|
dffeas \ula_|i2s_intf_|shiftreg[8] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2s_intf_|shiftreg~11_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2s_intf_|shiftreg [8]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|shiftreg[8] .is_wysiwyg = "true";
|
|
defparam \ula_|i2s_intf_|shiftreg[8] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y31_N6
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~10 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|shiftreg~10_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [8])
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\ula_|i2s_intf_|Equal0~2_combout ),
|
|
.datad(\ula_|i2s_intf_|shiftreg [8]),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|shiftreg~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|shiftreg~10 .lut_mask = 16'h0F00;
|
|
defparam \ula_|i2s_intf_|shiftreg~10 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X23_Y31_N7
|
|
dffeas \ula_|i2s_intf_|shiftreg[9] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2s_intf_|shiftreg~10_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2s_intf_|shiftreg [9]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|shiftreg[9] .is_wysiwyg = "true";
|
|
defparam \ula_|i2s_intf_|shiftreg[9] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y31_N16
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~9 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|shiftreg~9_combout = (\ula_|i2s_intf_|shiftreg [9] & !\ula_|i2s_intf_|Equal0~2_combout )
|
|
|
|
.dataa(\ula_|i2s_intf_|shiftreg [9]),
|
|
.datab(gnd),
|
|
.datac(\ula_|i2s_intf_|Equal0~2_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|shiftreg~9_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|shiftreg~9 .lut_mask = 16'h0A0A;
|
|
defparam \ula_|i2s_intf_|shiftreg~9 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X23_Y31_N17
|
|
dffeas \ula_|i2s_intf_|shiftreg[10] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2s_intf_|shiftreg~9_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2s_intf_|shiftreg [10]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|shiftreg[10] .is_wysiwyg = "true";
|
|
defparam \ula_|i2s_intf_|shiftreg[10] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y31_N18
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~8 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|shiftreg~8_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [10])
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\ula_|i2s_intf_|Equal0~2_combout ),
|
|
.datad(\ula_|i2s_intf_|shiftreg [10]),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|shiftreg~8_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|shiftreg~8 .lut_mask = 16'h0F00;
|
|
defparam \ula_|i2s_intf_|shiftreg~8 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X23_Y31_N19
|
|
dffeas \ula_|i2s_intf_|shiftreg[11] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2s_intf_|shiftreg~8_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2s_intf_|shiftreg [11]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|shiftreg[11] .is_wysiwyg = "true";
|
|
defparam \ula_|i2s_intf_|shiftreg[11] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y31_N28
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~7 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|shiftreg~7_combout = (\ula_|i2s_intf_|shiftreg [11] & !\ula_|i2s_intf_|Equal0~2_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|i2s_intf_|shiftreg [11]),
|
|
.datac(\ula_|i2s_intf_|Equal0~2_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|shiftreg~7_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|shiftreg~7 .lut_mask = 16'h0C0C;
|
|
defparam \ula_|i2s_intf_|shiftreg~7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X23_Y31_N29
|
|
dffeas \ula_|i2s_intf_|shiftreg[12] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2s_intf_|shiftreg~7_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2s_intf_|shiftreg [12]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|shiftreg[12] .is_wysiwyg = "true";
|
|
defparam \ula_|i2s_intf_|shiftreg[12] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y31_N30
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|PCM_INL[14]~0 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|PCM_INL[14]~0_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (\ula_|i2s_intf_|PCM_INL [14])) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|shiftreg [14]))))) #
|
|
// (!\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|PCM_INL [14]))))
|
|
|
|
.dataa(\ula_|i2s_intf_|Equal0~2_combout ),
|
|
.datab(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ),
|
|
.datac(\ula_|i2s_intf_|PCM_INL [14]),
|
|
.datad(\ula_|i2s_intf_|shiftreg [14]),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|PCM_INL[14]~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|PCM_INL[14]~0 .lut_mask = 16'hF2D0;
|
|
defparam \ula_|i2s_intf_|PCM_INL[14]~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X24_Y31_N31
|
|
dffeas \ula_|i2s_intf_|PCM_INL[14] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2s_intf_|PCM_INL[14]~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2s_intf_|PCM_INL [14]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|PCM_INL[14] .is_wysiwyg = "true";
|
|
defparam \ula_|i2s_intf_|PCM_INL[14] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y31_N16
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|PCM_INR[14]~0 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|PCM_INR[14]~0_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & ((\ula_|i2s_intf_|shiftreg [14]))) # (!\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q & (\ula_|i2s_intf_|PCM_INR [14])))) #
|
|
// (!\ula_|i2s_intf_|Equal0~2_combout & (((\ula_|i2s_intf_|PCM_INR [14]))))
|
|
|
|
.dataa(\ula_|i2s_intf_|Equal0~2_combout ),
|
|
.datab(\ula_|i2s_intf_|lrclk_r~_Duplicate_2_q ),
|
|
.datac(\ula_|i2s_intf_|PCM_INR [14]),
|
|
.datad(\ula_|i2s_intf_|shiftreg [14]),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|PCM_INR[14]~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|PCM_INR[14]~0 .lut_mask = 16'hF870;
|
|
defparam \ula_|i2s_intf_|PCM_INR[14]~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X24_Y31_N17
|
|
dffeas \ula_|i2s_intf_|PCM_INR[14] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2s_intf_|PCM_INR[14]~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2s_intf_|PCM_INR [14]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|PCM_INR[14] .is_wysiwyg = "true";
|
|
defparam \ula_|i2s_intf_|PCM_INR[14] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y31_N24
|
|
cycloneive_lcell_comb \ula_|pcm_outr~0 (
|
|
// Equation(s):
|
|
// \ula_|pcm_outr~0_combout = (\ula_|i2s_intf_|PCM_INL [14]) # (\ula_|i2s_intf_|PCM_INR [14])
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\ula_|i2s_intf_|PCM_INL [14]),
|
|
.datad(\ula_|i2s_intf_|PCM_INR [14]),
|
|
.cin(gnd),
|
|
.combout(\ula_|pcm_outr~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|pcm_outr~0 .lut_mask = 16'hFFF0;
|
|
defparam \ula_|pcm_outr~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X24_Y31_N25
|
|
dffeas \ula_|pcm_outl[12] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|pcm_outr~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|always0~3_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|pcm_outl [12]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|pcm_outl[12] .is_wysiwyg = "true";
|
|
defparam \ula_|pcm_outl[12] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y31_N10
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~6 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|shiftreg~6_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|pcm_outl [12]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [12]))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|i2s_intf_|shiftreg [12]),
|
|
.datac(\ula_|i2s_intf_|Equal0~2_combout ),
|
|
.datad(\ula_|pcm_outl [12]),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|shiftreg~6_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|shiftreg~6 .lut_mask = 16'hFC0C;
|
|
defparam \ula_|i2s_intf_|shiftreg~6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X23_Y31_N11
|
|
dffeas \ula_|i2s_intf_|shiftreg[13] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2s_intf_|shiftreg~6_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2s_intf_|shiftreg [13]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|shiftreg[13] .is_wysiwyg = "true";
|
|
defparam \ula_|i2s_intf_|shiftreg[13] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X23_Y14_N9
|
|
dffeas \ula_|pcm_outl[13] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\D[3]~74_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|always0~3_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|pcm_outl [13]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|pcm_outl[13] .is_wysiwyg = "true";
|
|
defparam \ula_|pcm_outl[13] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y31_N8
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~5 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|shiftreg~5_combout = (\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|pcm_outl [13]))) # (!\ula_|i2s_intf_|Equal0~2_combout & (\ula_|i2s_intf_|shiftreg [13]))
|
|
|
|
.dataa(\ula_|i2s_intf_|shiftreg [13]),
|
|
.datab(\ula_|i2s_intf_|Equal0~2_combout ),
|
|
.datac(gnd),
|
|
.datad(\ula_|pcm_outl [13]),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|shiftreg~5_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|shiftreg~5 .lut_mask = 16'hEE22;
|
|
defparam \ula_|i2s_intf_|shiftreg~5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X23_Y31_N9
|
|
dffeas \ula_|i2s_intf_|shiftreg[14] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2s_intf_|shiftreg~5_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2s_intf_|shiftreg [14]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|shiftreg[14] .is_wysiwyg = "true";
|
|
defparam \ula_|i2s_intf_|shiftreg[14] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y31_N2
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~4 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|shiftreg~4_combout = (\ula_|i2s_intf_|Equal0~2_combout & (\ula_|pcm_outl [14])) # (!\ula_|i2s_intf_|Equal0~2_combout & ((\ula_|i2s_intf_|shiftreg [14])))
|
|
|
|
.dataa(\ula_|pcm_outl [14]),
|
|
.datab(\ula_|i2s_intf_|shiftreg [14]),
|
|
.datac(\ula_|i2s_intf_|Equal0~2_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|shiftreg~4_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|shiftreg~4 .lut_mask = 16'hACAC;
|
|
defparam \ula_|i2s_intf_|shiftreg~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X23_Y31_N3
|
|
dffeas \ula_|i2s_intf_|shiftreg[15] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2s_intf_|shiftreg~4_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2s_intf_|shiftreg [15]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|shiftreg[15] .is_wysiwyg = "true";
|
|
defparam \ula_|i2s_intf_|shiftreg[15] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y32_N12
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~3 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|shiftreg~3_combout = (!\ula_|i2s_intf_|Equal0~2_combout & \ula_|i2s_intf_|shiftreg [15])
|
|
|
|
.dataa(\ula_|i2s_intf_|Equal0~2_combout ),
|
|
.datab(gnd),
|
|
.datac(\ula_|i2s_intf_|shiftreg [15]),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|shiftreg~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|shiftreg~3 .lut_mask = 16'h5050;
|
|
defparam \ula_|i2s_intf_|shiftreg~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X23_Y32_N13
|
|
dffeas \ula_|i2s_intf_|shiftreg[16] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2s_intf_|shiftreg~3_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2s_intf_|shiftreg [16]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|shiftreg[16] .is_wysiwyg = "true";
|
|
defparam \ula_|i2s_intf_|shiftreg[16] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X23_Y32_N2
|
|
cycloneive_lcell_comb \ula_|i2s_intf_|shiftreg~0 (
|
|
// Equation(s):
|
|
// \ula_|i2s_intf_|shiftreg~0_combout = (\ula_|i2s_intf_|shiftreg [16] & !\ula_|i2s_intf_|Equal0~2_combout )
|
|
|
|
.dataa(\ula_|i2s_intf_|shiftreg [16]),
|
|
.datab(gnd),
|
|
.datac(\ula_|i2s_intf_|Equal0~2_combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\ula_|i2s_intf_|shiftreg~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|shiftreg~0 .lut_mask = 16'h0A0A;
|
|
defparam \ula_|i2s_intf_|shiftreg~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: DDIOOUTCELL_X23_Y34_N18
|
|
dffeas \ula_|i2s_intf_|shiftreg[17] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ),
|
|
.d(\ula_|i2s_intf_|shiftreg~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\reset~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|i2s_intf_|shiftreg[4]~2_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|i2s_intf_|shiftreg [17]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|i2s_intf_|shiftreg[17] .is_wysiwyg = "true";
|
|
defparam \ula_|i2s_intf_|shiftreg[17] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X31_Y10_N24
|
|
cycloneive_lcell_comb \ula_|border[1]~feeder (
|
|
// Equation(s):
|
|
// \ula_|border[1]~feeder_combout = \D[1]~32_combout
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\D[1]~32_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|border[1]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|border[1]~feeder .lut_mask = 16'hFF00;
|
|
defparam \ula_|border[1]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X31_Y10_N25
|
|
dffeas \ula_|border[1] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|border[1]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|always0~3_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|border [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|border[1] .is_wysiwyg = "true";
|
|
defparam \ula_|border[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y32_N30
|
|
cycloneive_lcell_comb \ula_|video_|LessThan4~0 (
|
|
// Equation(s):
|
|
// \ula_|video_|LessThan4~0_combout = (((!\ula_|video_|vga_hc [4] & !\ula_|video_|vga_hc [5])) # (!\ula_|video_|vga_hc [7])) # (!\ula_|video_|vga_hc [6])
|
|
|
|
.dataa(\ula_|video_|vga_hc [4]),
|
|
.datab(\ula_|video_|vga_hc [6]),
|
|
.datac(\ula_|video_|vga_hc [7]),
|
|
.datad(\ula_|video_|vga_hc [5]),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|LessThan4~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|LessThan4~0 .lut_mask = 16'h3F7F;
|
|
defparam \ula_|video_|LessThan4~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y32_N26
|
|
cycloneive_lcell_comb \ula_|video_|screen_en~0 (
|
|
// Equation(s):
|
|
// \ula_|video_|screen_en~0_combout = (!\ula_|video_|vga_vc [9] & (\ula_|video_|vga_hc [9] $ (((\ula_|video_|vga_hc [8]) # (!\ula_|video_|LessThan4~0_combout )))))
|
|
|
|
.dataa(\ula_|video_|vga_hc [9]),
|
|
.datab(\ula_|video_|vga_vc [9]),
|
|
.datac(\ula_|video_|vga_hc [8]),
|
|
.datad(\ula_|video_|LessThan4~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|screen_en~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|screen_en~0 .lut_mask = 16'h1211;
|
|
defparam \ula_|video_|screen_en~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y32_N28
|
|
cycloneive_lcell_comb \ula_|video_|LessThan6~0 (
|
|
// Equation(s):
|
|
// \ula_|video_|LessThan6~0_combout = (!\ula_|video_|vga_vc [3] & (!\ula_|video_|vga_vc [2] & ((!\ula_|video_|vga_vc [1]) # (!\ula_|video_|vga_vc [0]))))
|
|
|
|
.dataa(\ula_|video_|vga_vc [3]),
|
|
.datab(\ula_|video_|vga_vc [2]),
|
|
.datac(\ula_|video_|vga_vc [0]),
|
|
.datad(\ula_|video_|vga_vc [1]),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|LessThan6~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|LessThan6~0 .lut_mask = 16'h0111;
|
|
defparam \ula_|video_|LessThan6~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y32_N12
|
|
cycloneive_lcell_comb \ula_|video_|LessThan6~1 (
|
|
// Equation(s):
|
|
// \ula_|video_|LessThan6~1_combout = ((!\ula_|video_|vga_vc [5] & ((\ula_|video_|LessThan6~0_combout ) # (!\ula_|video_|vga_vc [4])))) # (!\ula_|video_|vga_vc [6])
|
|
|
|
.dataa(\ula_|video_|vga_vc [4]),
|
|
.datab(\ula_|video_|vga_vc [6]),
|
|
.datac(\ula_|video_|vga_vc [5]),
|
|
.datad(\ula_|video_|LessThan6~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|LessThan6~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|LessThan6~1 .lut_mask = 16'h3F37;
|
|
defparam \ula_|video_|LessThan6~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y32_N22
|
|
cycloneive_lcell_comb \ula_|video_|screen_en~1 (
|
|
// Equation(s):
|
|
// \ula_|video_|screen_en~1_combout = (\ula_|video_|screen_en~0_combout & ((\ula_|video_|vga_vc [7] & ((\ula_|video_|LessThan6~1_combout ) # (!\ula_|video_|vga_vc [8]))) # (!\ula_|video_|vga_vc [7] & ((\ula_|video_|vga_vc [8]) #
|
|
// (!\ula_|video_|LessThan6~1_combout )))))
|
|
|
|
.dataa(\ula_|video_|vga_vc [7]),
|
|
.datab(\ula_|video_|vga_vc [8]),
|
|
.datac(\ula_|video_|screen_en~0_combout ),
|
|
.datad(\ula_|video_|LessThan6~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|screen_en~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|screen_en~1 .lut_mask = 16'hE070;
|
|
defparam \ula_|video_|screen_en~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y32_N14
|
|
cycloneive_lcell_comb \ula_|video_|LessThan2~0 (
|
|
// Equation(s):
|
|
// \ula_|video_|LessThan2~0_combout = (!\ula_|video_|vga_vc [9] & (!\ula_|video_|vga_vc [8] & (!\ula_|video_|vga_vc [6] & !\ula_|video_|vga_vc [7])))
|
|
|
|
.dataa(\ula_|video_|vga_vc [9]),
|
|
.datab(\ula_|video_|vga_vc [8]),
|
|
.datac(\ula_|video_|vga_vc [6]),
|
|
.datad(\ula_|video_|vga_vc [7]),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|LessThan2~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|LessThan2~0 .lut_mask = 16'h0001;
|
|
defparam \ula_|video_|LessThan2~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y32_N12
|
|
cycloneive_lcell_comb \ula_|video_|LessThan2~1 (
|
|
// Equation(s):
|
|
// \ula_|video_|LessThan2~1_combout = (\ula_|video_|LessThan2~0_combout & (((!\ula_|video_|vga_vc [4] & \ula_|video_|LessThan6~0_combout )) # (!\ula_|video_|vga_vc [5])))
|
|
|
|
.dataa(\ula_|video_|vga_vc [4]),
|
|
.datab(\ula_|video_|vga_vc [5]),
|
|
.datac(\ula_|video_|LessThan2~0_combout ),
|
|
.datad(\ula_|video_|LessThan6~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|LessThan2~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|LessThan2~1 .lut_mask = 16'h7030;
|
|
defparam \ula_|video_|LessThan2~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y32_N4
|
|
cycloneive_lcell_comb \ula_|video_|LessThan3~0 (
|
|
// Equation(s):
|
|
// \ula_|video_|LessThan3~0_combout = ((!\ula_|video_|vga_vc [5] & (\ula_|video_|LessThan6~0_combout & \ula_|video_|Equal2~0_combout ))) # (!\ula_|video_|vga_vc [9])
|
|
|
|
.dataa(\ula_|video_|vga_vc [5]),
|
|
.datab(\ula_|video_|LessThan6~0_combout ),
|
|
.datac(\ula_|video_|vga_vc [9]),
|
|
.datad(\ula_|video_|Equal2~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|LessThan3~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|LessThan3~0 .lut_mask = 16'h4F0F;
|
|
defparam \ula_|video_|LessThan3~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y32_N2
|
|
cycloneive_lcell_comb \ula_|video_|LessThan0~0 (
|
|
// Equation(s):
|
|
// \ula_|video_|LessThan0~0_combout = (!\ula_|video_|vga_hc [6] & (!\ula_|video_|vga_hc [4] & !\ula_|video_|vga_hc [5]))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|video_|vga_hc [6]),
|
|
.datac(\ula_|video_|vga_hc [4]),
|
|
.datad(\ula_|video_|vga_hc [5]),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|LessThan0~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|LessThan0~0 .lut_mask = 16'h0003;
|
|
defparam \ula_|video_|LessThan0~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X34_Y32_N0
|
|
cycloneive_lcell_comb \ula_|video_|disp_enable~0 (
|
|
// Equation(s):
|
|
// \ula_|video_|disp_enable~0_combout = (\ula_|video_|vga_hc [8] & (((!\ula_|video_|vga_hc [7] & \ula_|video_|LessThan0~0_combout )) # (!\ula_|video_|vga_hc [9]))) # (!\ula_|video_|vga_hc [8] & ((\ula_|video_|vga_hc [9]) # ((\ula_|video_|vga_hc [7] &
|
|
// !\ula_|video_|LessThan0~0_combout ))))
|
|
|
|
.dataa(\ula_|video_|vga_hc [7]),
|
|
.datab(\ula_|video_|vga_hc [8]),
|
|
.datac(\ula_|video_|vga_hc [9]),
|
|
.datad(\ula_|video_|LessThan0~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|disp_enable~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|disp_enable~0 .lut_mask = 16'h7C3E;
|
|
defparam \ula_|video_|disp_enable~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y32_N6
|
|
cycloneive_lcell_comb \ula_|video_|disp_enable~1 (
|
|
// Equation(s):
|
|
// \ula_|video_|disp_enable~1_combout = (!\ula_|video_|LessThan2~1_combout & (\ula_|video_|LessThan3~0_combout & \ula_|video_|disp_enable~0_combout ))
|
|
|
|
.dataa(\ula_|video_|LessThan2~1_combout ),
|
|
.datab(\ula_|video_|LessThan3~0_combout ),
|
|
.datac(gnd),
|
|
.datad(\ula_|video_|disp_enable~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|disp_enable~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|disp_enable~1 .lut_mask = 16'h4400;
|
|
defparam \ula_|video_|disp_enable~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X38_Y32_N8
|
|
cycloneive_lcell_comb \ula_|video_|attr_prefetch[7]~feeder (
|
|
// Equation(s):
|
|
// \ula_|video_|attr_prefetch[7]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|attr_prefetch[7]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|attr_prefetch[7]~feeder .lut_mask = 16'hFF00;
|
|
defparam \ula_|video_|attr_prefetch[7]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y31_N24
|
|
cycloneive_lcell_comb \ula_|video_|Decoder0~1 (
|
|
// Equation(s):
|
|
// \ula_|video_|Decoder0~1_combout = (\ula_|video_|vga_hc [1] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] & !\ula_|video_|vga_hc [0])))
|
|
|
|
.dataa(\ula_|video_|vga_hc [1]),
|
|
.datab(\ula_|video_|vga_hc [3]),
|
|
.datac(\ula_|video_|vga_hc [2]),
|
|
.datad(\ula_|video_|vga_hc [0]),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|Decoder0~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Decoder0~1 .lut_mask = 16'h0080;
|
|
defparam \ula_|video_|Decoder0~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X38_Y32_N9
|
|
dffeas \ula_|video_|attr_prefetch[7] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|attr_prefetch[7]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|video_|Decoder0~1_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|attr_prefetch [7]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|attr_prefetch[7] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|attr_prefetch[7] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y31_N2
|
|
cycloneive_lcell_comb \ula_|video_|Decoder0~0 (
|
|
// Equation(s):
|
|
// \ula_|video_|Decoder0~0_combout = (\ula_|video_|vga_hc [1] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] & \ula_|video_|vga_hc [0])))
|
|
|
|
.dataa(\ula_|video_|vga_hc [1]),
|
|
.datab(\ula_|video_|vga_hc [3]),
|
|
.datac(\ula_|video_|vga_hc [2]),
|
|
.datad(\ula_|video_|vga_hc [0]),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|Decoder0~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Decoder0~0 .lut_mask = 16'h8000;
|
|
defparam \ula_|video_|Decoder0~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y32_N23
|
|
dffeas \ula_|video_|attr[7] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\ula_|video_|attr_prefetch [7]),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\ula_|video_|Decoder0~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|attr [7]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|attr[7] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|attr[7] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y31_N0
|
|
cycloneive_lcell_comb \ula_|video_|frame[0]~12 (
|
|
// Equation(s):
|
|
// \ula_|video_|frame[0]~12_combout = \ula_|video_|frame [0] $ (\ula_|video_|Equal3~1_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\ula_|video_|frame [0]),
|
|
.datad(\ula_|video_|Equal3~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|frame[0]~12_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|frame[0]~12 .lut_mask = 16'h0FF0;
|
|
defparam \ula_|video_|frame[0]~12 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y31_N1
|
|
dffeas \ula_|video_|frame[0] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|frame[0]~12_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|frame [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|frame[0] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|frame[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y32_N14
|
|
cycloneive_lcell_comb \ula_|video_|frame[1]~4 (
|
|
// Equation(s):
|
|
// \ula_|video_|frame[1]~4_combout = (\ula_|video_|frame [0] & (\ula_|video_|frame [1] $ (VCC))) # (!\ula_|video_|frame [0] & (\ula_|video_|frame [1] & VCC))
|
|
// \ula_|video_|frame[1]~5 = CARRY((\ula_|video_|frame [0] & \ula_|video_|frame [1]))
|
|
|
|
.dataa(\ula_|video_|frame [0]),
|
|
.datab(\ula_|video_|frame [1]),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|frame[1]~4_combout ),
|
|
.cout(\ula_|video_|frame[1]~5 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|frame[1]~4 .lut_mask = 16'h6688;
|
|
defparam \ula_|video_|frame[1]~4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y32_N15
|
|
dffeas \ula_|video_|frame[1] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|frame[1]~4_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|video_|Equal3~1_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|frame [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|frame[1] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|frame[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y32_N16
|
|
cycloneive_lcell_comb \ula_|video_|frame[2]~6 (
|
|
// Equation(s):
|
|
// \ula_|video_|frame[2]~6_combout = (\ula_|video_|frame [2] & (!\ula_|video_|frame[1]~5 )) # (!\ula_|video_|frame [2] & ((\ula_|video_|frame[1]~5 ) # (GND)))
|
|
// \ula_|video_|frame[2]~7 = CARRY((!\ula_|video_|frame[1]~5 ) # (!\ula_|video_|frame [2]))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|video_|frame [2]),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\ula_|video_|frame[1]~5 ),
|
|
.combout(\ula_|video_|frame[2]~6_combout ),
|
|
.cout(\ula_|video_|frame[2]~7 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|frame[2]~6 .lut_mask = 16'h3C3F;
|
|
defparam \ula_|video_|frame[2]~6 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y32_N17
|
|
dffeas \ula_|video_|frame[2] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|frame[2]~6_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|video_|Equal3~1_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|frame [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|frame[2] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|frame[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y32_N18
|
|
cycloneive_lcell_comb \ula_|video_|frame[3]~8 (
|
|
// Equation(s):
|
|
// \ula_|video_|frame[3]~8_combout = (\ula_|video_|frame [3] & (\ula_|video_|frame[2]~7 $ (GND))) # (!\ula_|video_|frame [3] & (!\ula_|video_|frame[2]~7 & VCC))
|
|
// \ula_|video_|frame[3]~9 = CARRY((\ula_|video_|frame [3] & !\ula_|video_|frame[2]~7 ))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|video_|frame [3]),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\ula_|video_|frame[2]~7 ),
|
|
.combout(\ula_|video_|frame[3]~8_combout ),
|
|
.cout(\ula_|video_|frame[3]~9 ));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|frame[3]~8 .lut_mask = 16'hC30C;
|
|
defparam \ula_|video_|frame[3]~8 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y32_N19
|
|
dffeas \ula_|video_|frame[3] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|frame[3]~8_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|video_|Equal3~1_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|frame [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|frame[3] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|frame[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y32_N20
|
|
cycloneive_lcell_comb \ula_|video_|frame[4]~10 (
|
|
// Equation(s):
|
|
// \ula_|video_|frame[4]~10_combout = \ula_|video_|frame[3]~9 $ (\ula_|video_|frame [4])
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\ula_|video_|frame [4]),
|
|
.cin(\ula_|video_|frame[3]~9 ),
|
|
.combout(\ula_|video_|frame[4]~10_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|frame[4]~10 .lut_mask = 16'h0FF0;
|
|
defparam \ula_|video_|frame[4]~10 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y32_N0
|
|
cycloneive_lcell_comb \ula_|video_|frame[4]~feeder (
|
|
// Equation(s):
|
|
// \ula_|video_|frame[4]~feeder_combout = \ula_|video_|frame[4]~10_combout
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\ula_|video_|frame[4]~10_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|frame[4]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|frame[4]~feeder .lut_mask = 16'hFF00;
|
|
defparam \ula_|video_|frame[4]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y32_N1
|
|
dffeas \ula_|video_|frame[4] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|frame[4]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|video_|Equal3~1_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|frame [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|frame[4] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|frame[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y32_N22
|
|
cycloneive_lcell_comb \ula_|video_|inverted (
|
|
// Equation(s):
|
|
// \ula_|video_|inverted~combout = (\ula_|video_|attr [7] & \ula_|video_|frame [4])
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\ula_|video_|attr [7]),
|
|
.datad(\ula_|video_|frame [4]),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|inverted~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|inverted .lut_mask = 16'hF000;
|
|
defparam \ula_|video_|inverted .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X38_Y32_N4
|
|
cycloneive_lcell_comb \ula_|video_|bits_prefetch[6]~feeder (
|
|
// Equation(s):
|
|
// \ula_|video_|bits_prefetch[6]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|bits_prefetch[6]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|bits_prefetch[6]~feeder .lut_mask = 16'hF0F0;
|
|
defparam \ula_|video_|bits_prefetch[6]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y31_N10
|
|
cycloneive_lcell_comb \ula_|video_|Decoder0~2 (
|
|
// Equation(s):
|
|
// \ula_|video_|Decoder0~2_combout = (!\ula_|video_|vga_hc [1] & (\ula_|video_|vga_hc [3] & (\ula_|video_|vga_hc [2] & !\ula_|video_|vga_hc [0])))
|
|
|
|
.dataa(\ula_|video_|vga_hc [1]),
|
|
.datab(\ula_|video_|vga_hc [3]),
|
|
.datac(\ula_|video_|vga_hc [2]),
|
|
.datad(\ula_|video_|vga_hc [0]),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|Decoder0~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Decoder0~2 .lut_mask = 16'h0040;
|
|
defparam \ula_|video_|Decoder0~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X38_Y32_N5
|
|
dffeas \ula_|video_|bits_prefetch[6] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|bits_prefetch[6]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|video_|Decoder0~2_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|bits_prefetch [6]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|bits_prefetch[6] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|bits_prefetch[6] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y32_N27
|
|
dffeas \ula_|video_|bits[6] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\ula_|video_|bits_prefetch [6]),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\ula_|video_|Decoder0~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|bits [6]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|bits[6] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|bits[6] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X38_Y32_N10
|
|
cycloneive_lcell_comb \ula_|video_|bits_prefetch[4]~feeder (
|
|
// Equation(s):
|
|
// \ula_|video_|bits_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|bits_prefetch[4]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|bits_prefetch[4]~feeder .lut_mask = 16'hFF00;
|
|
defparam \ula_|video_|bits_prefetch[4]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X38_Y32_N11
|
|
dffeas \ula_|video_|bits_prefetch[4] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|bits_prefetch[4]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|video_|Decoder0~2_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|bits_prefetch [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|bits_prefetch[4] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|bits_prefetch[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y32_N9
|
|
dffeas \ula_|video_|bits[4] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\ula_|video_|bits_prefetch [4]),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\ula_|video_|Decoder0~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|bits [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|bits[4] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|bits[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X38_Y32_N26
|
|
cycloneive_lcell_comb \ula_|video_|bits_prefetch[5]~feeder (
|
|
// Equation(s):
|
|
// \ula_|video_|bits_prefetch[5]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|bits_prefetch[5]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|bits_prefetch[5]~feeder .lut_mask = 16'hFF00;
|
|
defparam \ula_|video_|bits_prefetch[5]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X38_Y32_N27
|
|
dffeas \ula_|video_|bits_prefetch[5] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|bits_prefetch[5]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|video_|Decoder0~2_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|bits_prefetch [5]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|bits_prefetch[5] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|bits_prefetch[5] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y32_N12
|
|
cycloneive_lcell_comb \ula_|video_|bits[5]~feeder (
|
|
// Equation(s):
|
|
// \ula_|video_|bits[5]~feeder_combout = \ula_|video_|bits_prefetch [5]
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\ula_|video_|bits_prefetch [5]),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|bits[5]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|bits[5]~feeder .lut_mask = 16'hFF00;
|
|
defparam \ula_|video_|bits[5]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y32_N13
|
|
dffeas \ula_|video_|bits[5] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|bits[5]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|video_|Decoder0~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|bits [5]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|bits[5] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|bits[5] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X38_Y32_N12
|
|
cycloneive_lcell_comb \ula_|video_|bits_prefetch[7]~feeder (
|
|
// Equation(s):
|
|
// \ula_|video_|bits_prefetch[7]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\ram0|altsyncram_component|auto_generated|ram_block1a7~PORTBDATAOUT0 ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|bits_prefetch[7]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|bits_prefetch[7]~feeder .lut_mask = 16'hFF00;
|
|
defparam \ula_|video_|bits_prefetch[7]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X38_Y32_N13
|
|
dffeas \ula_|video_|bits_prefetch[7] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|bits_prefetch[7]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|video_|Decoder0~2_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|bits_prefetch [7]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|bits_prefetch[7] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|bits_prefetch[7] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y32_N19
|
|
dffeas \ula_|video_|bits[7] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\ula_|video_|bits_prefetch [7]),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\ula_|video_|Decoder0~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|bits [7]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|bits[7] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|bits[7] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y32_N18
|
|
cycloneive_lcell_comb \ula_|video_|Mux0~0 (
|
|
// Equation(s):
|
|
// \ula_|video_|Mux0~0_combout = (\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [5]) # ((\ula_|video_|vga_hc [1])))) # (!\ula_|video_|vga_hc [2] & (((\ula_|video_|bits [7] & !\ula_|video_|vga_hc [1]))))
|
|
|
|
.dataa(\ula_|video_|bits [5]),
|
|
.datab(\ula_|video_|vga_hc [2]),
|
|
.datac(\ula_|video_|bits [7]),
|
|
.datad(\ula_|video_|vga_hc [1]),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|Mux0~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Mux0~0 .lut_mask = 16'hCCB8;
|
|
defparam \ula_|video_|Mux0~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y32_N8
|
|
cycloneive_lcell_comb \ula_|video_|Mux0~1 (
|
|
// Equation(s):
|
|
// \ula_|video_|Mux0~1_combout = (\ula_|video_|vga_hc [1] & ((\ula_|video_|Mux0~0_combout & ((\ula_|video_|bits [4]))) # (!\ula_|video_|Mux0~0_combout & (\ula_|video_|bits [6])))) # (!\ula_|video_|vga_hc [1] & (((\ula_|video_|Mux0~0_combout ))))
|
|
|
|
.dataa(\ula_|video_|vga_hc [1]),
|
|
.datab(\ula_|video_|bits [6]),
|
|
.datac(\ula_|video_|bits [4]),
|
|
.datad(\ula_|video_|Mux0~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|Mux0~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Mux0~1 .lut_mask = 16'hF588;
|
|
defparam \ula_|video_|Mux0~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X38_Y32_N16
|
|
cycloneive_lcell_comb \ula_|video_|bits_prefetch[2]~feeder (
|
|
// Equation(s):
|
|
// \ula_|video_|bits_prefetch[2]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|bits_prefetch[2]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|bits_prefetch[2]~feeder .lut_mask = 16'hFF00;
|
|
defparam \ula_|video_|bits_prefetch[2]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X38_Y32_N17
|
|
dffeas \ula_|video_|bits_prefetch[2] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|bits_prefetch[2]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|video_|Decoder0~2_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|bits_prefetch [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|bits_prefetch[2] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|bits_prefetch[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y32_N30
|
|
cycloneive_lcell_comb \ula_|video_|bits[2]~feeder (
|
|
// Equation(s):
|
|
// \ula_|video_|bits[2]~feeder_combout = \ula_|video_|bits_prefetch [2]
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\ula_|video_|bits_prefetch [2]),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|bits[2]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|bits[2]~feeder .lut_mask = 16'hFF00;
|
|
defparam \ula_|video_|bits[2]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y32_N31
|
|
dffeas \ula_|video_|bits[2] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|bits[2]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|video_|Decoder0~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|bits [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|bits[2] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|bits[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X38_Y32_N6
|
|
cycloneive_lcell_comb \ula_|video_|bits_prefetch[0]~feeder (
|
|
// Equation(s):
|
|
// \ula_|video_|bits_prefetch[0]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|bits_prefetch[0]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|bits_prefetch[0]~feeder .lut_mask = 16'hFF00;
|
|
defparam \ula_|video_|bits_prefetch[0]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X38_Y32_N7
|
|
dffeas \ula_|video_|bits_prefetch[0] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|bits_prefetch[0]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|video_|Decoder0~2_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|bits_prefetch [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|bits_prefetch[0] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|bits_prefetch[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y32_N25
|
|
dffeas \ula_|video_|bits[0] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\ula_|video_|bits_prefetch [0]),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\ula_|video_|Decoder0~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|bits [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|bits[0] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|bits[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X38_Y32_N2
|
|
cycloneive_lcell_comb \ula_|video_|bits_prefetch[1]~feeder (
|
|
// Equation(s):
|
|
// \ula_|video_|bits_prefetch[1]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|bits_prefetch[1]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|bits_prefetch[1]~feeder .lut_mask = 16'hFF00;
|
|
defparam \ula_|video_|bits_prefetch[1]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X38_Y32_N3
|
|
dffeas \ula_|video_|bits_prefetch[1] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|bits_prefetch[1]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|video_|Decoder0~2_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|bits_prefetch [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|bits_prefetch[1] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|bits_prefetch[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y32_N28
|
|
cycloneive_lcell_comb \ula_|video_|bits[1]~feeder (
|
|
// Equation(s):
|
|
// \ula_|video_|bits[1]~feeder_combout = \ula_|video_|bits_prefetch [1]
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\ula_|video_|bits_prefetch [1]),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|bits[1]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|bits[1]~feeder .lut_mask = 16'hFF00;
|
|
defparam \ula_|video_|bits[1]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y32_N29
|
|
dffeas \ula_|video_|bits[1] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|bits[1]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|video_|Decoder0~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|bits [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|bits[1] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|bits[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X38_Y32_N20
|
|
cycloneive_lcell_comb \ula_|video_|bits_prefetch[3]~feeder (
|
|
// Equation(s):
|
|
// \ula_|video_|bits_prefetch[3]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|bits_prefetch[3]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|bits_prefetch[3]~feeder .lut_mask = 16'hFF00;
|
|
defparam \ula_|video_|bits_prefetch[3]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X38_Y32_N21
|
|
dffeas \ula_|video_|bits_prefetch[3] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|bits_prefetch[3]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|video_|Decoder0~2_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|bits_prefetch [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|bits_prefetch[3] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|bits_prefetch[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y32_N7
|
|
dffeas \ula_|video_|bits[3] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\ula_|video_|bits_prefetch [3]),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\ula_|video_|Decoder0~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|bits [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|bits[3] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|bits[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y32_N6
|
|
cycloneive_lcell_comb \ula_|video_|Mux0~2 (
|
|
// Equation(s):
|
|
// \ula_|video_|Mux0~2_combout = (\ula_|video_|vga_hc [1] & (((\ula_|video_|vga_hc [2])))) # (!\ula_|video_|vga_hc [1] & ((\ula_|video_|vga_hc [2] & (\ula_|video_|bits [1])) # (!\ula_|video_|vga_hc [2] & ((\ula_|video_|bits [3])))))
|
|
|
|
.dataa(\ula_|video_|vga_hc [1]),
|
|
.datab(\ula_|video_|bits [1]),
|
|
.datac(\ula_|video_|bits [3]),
|
|
.datad(\ula_|video_|vga_hc [2]),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|Mux0~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Mux0~2 .lut_mask = 16'hEE50;
|
|
defparam \ula_|video_|Mux0~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y32_N24
|
|
cycloneive_lcell_comb \ula_|video_|Mux0~3 (
|
|
// Equation(s):
|
|
// \ula_|video_|Mux0~3_combout = (\ula_|video_|vga_hc [1] & ((\ula_|video_|Mux0~2_combout & ((\ula_|video_|bits [0]))) # (!\ula_|video_|Mux0~2_combout & (\ula_|video_|bits [2])))) # (!\ula_|video_|vga_hc [1] & (((\ula_|video_|Mux0~2_combout ))))
|
|
|
|
.dataa(\ula_|video_|vga_hc [1]),
|
|
.datab(\ula_|video_|bits [2]),
|
|
.datac(\ula_|video_|bits [0]),
|
|
.datad(\ula_|video_|Mux0~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|Mux0~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Mux0~3 .lut_mask = 16'hF588;
|
|
defparam \ula_|video_|Mux0~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y32_N20
|
|
cycloneive_lcell_comb \ula_|video_|cindex[1]~0 (
|
|
// Equation(s):
|
|
// \ula_|video_|cindex[1]~0_combout = \ula_|video_|inverted~combout $ (((\ula_|video_|vga_hc [3] & ((\ula_|video_|Mux0~3_combout ))) # (!\ula_|video_|vga_hc [3] & (\ula_|video_|Mux0~1_combout ))))
|
|
|
|
.dataa(\ula_|video_|inverted~combout ),
|
|
.datab(\ula_|video_|vga_hc [3]),
|
|
.datac(\ula_|video_|Mux0~1_combout ),
|
|
.datad(\ula_|video_|Mux0~3_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|cindex[1]~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|cindex[1]~0 .lut_mask = 16'h569A;
|
|
defparam \ula_|video_|cindex[1]~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X38_Y32_N14
|
|
cycloneive_lcell_comb \ula_|video_|attr_prefetch[4]~feeder (
|
|
// Equation(s):
|
|
// \ula_|video_|attr_prefetch[4]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\ram0|altsyncram_component|auto_generated|ram_block1a4~PORTBDATAOUT0 ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|attr_prefetch[4]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|attr_prefetch[4]~feeder .lut_mask = 16'hFF00;
|
|
defparam \ula_|video_|attr_prefetch[4]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X38_Y32_N15
|
|
dffeas \ula_|video_|attr_prefetch[4] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|attr_prefetch[4]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|video_|Decoder0~1_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|attr_prefetch [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|attr_prefetch[4] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|attr_prefetch[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X36_Y32_N17
|
|
dffeas \ula_|video_|attr[4] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\ula_|video_|attr_prefetch [4]),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\ula_|video_|Decoder0~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|attr [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|attr[4] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|attr[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X38_Y32_N28
|
|
cycloneive_lcell_comb \ula_|video_|attr_prefetch[1]~feeder (
|
|
// Equation(s):
|
|
// \ula_|video_|attr_prefetch[1]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\ram0|altsyncram_component|auto_generated|ram_block1a1~PORTBDATAOUT0 ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|attr_prefetch[1]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|attr_prefetch[1]~feeder .lut_mask = 16'hFF00;
|
|
defparam \ula_|video_|attr_prefetch[1]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X38_Y32_N29
|
|
dffeas \ula_|video_|attr_prefetch[1] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|attr_prefetch[1]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|video_|Decoder0~1_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|attr_prefetch [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|attr_prefetch[1] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|attr_prefetch[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X36_Y32_N7
|
|
dffeas \ula_|video_|attr[1] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\ula_|video_|attr_prefetch [1]),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\ula_|video_|Decoder0~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|attr [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|attr[1] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|attr[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y32_N16
|
|
cycloneive_lcell_comb \ula_|video_|cindex[1]~1 (
|
|
// Equation(s):
|
|
// \ula_|video_|cindex[1]~1_combout = (\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [1]))) # (!\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [4]))
|
|
|
|
.dataa(\ula_|video_|cindex[1]~0_combout ),
|
|
.datab(gnd),
|
|
.datac(\ula_|video_|attr [4]),
|
|
.datad(\ula_|video_|attr [1]),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|cindex[1]~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|cindex[1]~1 .lut_mask = 16'hFA50;
|
|
defparam \ula_|video_|cindex[1]~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y32_N26
|
|
cycloneive_lcell_comb \ula_|video_|VGA_R[0]~0 (
|
|
// Equation(s):
|
|
// \ula_|video_|VGA_R[0]~0_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[1]~1_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [1]))))
|
|
|
|
.dataa(\ula_|border [1]),
|
|
.datab(\ula_|video_|screen_en~1_combout ),
|
|
.datac(\ula_|video_|disp_enable~1_combout ),
|
|
.datad(\ula_|video_|cindex[1]~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|VGA_R[0]~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|VGA_R[0]~0 .lut_mask = 16'hE020;
|
|
defparam \ula_|video_|VGA_R[0]~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X38_Y32_N18
|
|
cycloneive_lcell_comb \ula_|video_|attr_prefetch[6]~feeder (
|
|
// Equation(s):
|
|
// \ula_|video_|attr_prefetch[6]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\ram0|altsyncram_component|auto_generated|ram_block1a6~PORTBDATAOUT0 ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|attr_prefetch[6]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|attr_prefetch[6]~feeder .lut_mask = 16'hF0F0;
|
|
defparam \ula_|video_|attr_prefetch[6]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X38_Y32_N19
|
|
dffeas \ula_|video_|attr_prefetch[6] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|attr_prefetch[6]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|video_|Decoder0~1_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|attr_prefetch [6]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|attr_prefetch[6] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|attr_prefetch[6] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X36_Y32_N9
|
|
dffeas \ula_|video_|attr[6] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\ula_|video_|attr_prefetch [6]),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\ula_|video_|Decoder0~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|attr [6]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|attr[6] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|attr[6] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y32_N8
|
|
cycloneive_lcell_comb \ula_|video_|VGA_B[1]~0 (
|
|
// Equation(s):
|
|
// \ula_|video_|VGA_B[1]~0_combout = (!\ula_|video_|LessThan2~1_combout & (\ula_|video_|LessThan3~0_combout & (\ula_|video_|attr [6] & \ula_|video_|disp_enable~0_combout )))
|
|
|
|
.dataa(\ula_|video_|LessThan2~1_combout ),
|
|
.datab(\ula_|video_|LessThan3~0_combout ),
|
|
.datac(\ula_|video_|attr [6]),
|
|
.datad(\ula_|video_|disp_enable~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|VGA_B[1]~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|VGA_B[1]~0 .lut_mask = 16'h4000;
|
|
defparam \ula_|video_|VGA_B[1]~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y32_N30
|
|
cycloneive_lcell_comb \ula_|video_|VGA_R[1]~1 (
|
|
// Equation(s):
|
|
// \ula_|video_|VGA_R[1]~1_combout = (\ula_|video_|screen_en~1_combout & (\ula_|video_|VGA_B[1]~0_combout & \ula_|video_|cindex[1]~1_combout ))
|
|
|
|
.dataa(\ula_|video_|screen_en~1_combout ),
|
|
.datab(\ula_|video_|VGA_B[1]~0_combout ),
|
|
.datac(gnd),
|
|
.datad(\ula_|video_|cindex[1]~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|VGA_R[1]~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|VGA_R[1]~1 .lut_mask = 16'h8800;
|
|
defparam \ula_|video_|VGA_R[1]~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X31_Y10_N27
|
|
dffeas \ula_|border[2] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\D[2]~39_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\ula_|always0~3_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|border [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|border[2] .is_wysiwyg = "true";
|
|
defparam \ula_|border[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X38_Y32_N22
|
|
cycloneive_lcell_comb \ula_|video_|attr_prefetch[5]~feeder (
|
|
// Equation(s):
|
|
// \ula_|video_|attr_prefetch[5]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\ram0|altsyncram_component|auto_generated|ram_block1a5~PORTBDATAOUT0 ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|attr_prefetch[5]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|attr_prefetch[5]~feeder .lut_mask = 16'hFF00;
|
|
defparam \ula_|video_|attr_prefetch[5]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X38_Y32_N23
|
|
dffeas \ula_|video_|attr_prefetch[5] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|attr_prefetch[5]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|video_|Decoder0~1_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|attr_prefetch [5]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|attr_prefetch[5] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|attr_prefetch[5] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X36_Y32_N21
|
|
dffeas \ula_|video_|attr[5] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\ula_|video_|attr_prefetch [5]),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\ula_|video_|Decoder0~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|attr [5]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|attr[5] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|attr[5] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X38_Y32_N0
|
|
cycloneive_lcell_comb \ula_|video_|attr_prefetch[2]~feeder (
|
|
// Equation(s):
|
|
// \ula_|video_|attr_prefetch[2]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\ram0|altsyncram_component|auto_generated|ram_block1a2~PORTBDATAOUT0 ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|attr_prefetch[2]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|attr_prefetch[2]~feeder .lut_mask = 16'hFF00;
|
|
defparam \ula_|video_|attr_prefetch[2]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X38_Y32_N1
|
|
dffeas \ula_|video_|attr_prefetch[2] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|attr_prefetch[2]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|video_|Decoder0~1_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|attr_prefetch [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|attr_prefetch[2] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|attr_prefetch[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X36_Y32_N19
|
|
dffeas \ula_|video_|attr[2] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\ula_|video_|attr_prefetch [2]),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\ula_|video_|Decoder0~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|attr [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|attr[2] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|attr[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y32_N20
|
|
cycloneive_lcell_comb \ula_|video_|cindex[2]~2 (
|
|
// Equation(s):
|
|
// \ula_|video_|cindex[2]~2_combout = (\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [2]))) # (!\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [5]))
|
|
|
|
.dataa(\ula_|video_|cindex[1]~0_combout ),
|
|
.datab(gnd),
|
|
.datac(\ula_|video_|attr [5]),
|
|
.datad(\ula_|video_|attr [2]),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|cindex[2]~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|cindex[2]~2 .lut_mask = 16'hFA50;
|
|
defparam \ula_|video_|cindex[2]~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y32_N22
|
|
cycloneive_lcell_comb \ula_|video_|VGA_G[0]~0 (
|
|
// Equation(s):
|
|
// \ula_|video_|VGA_G[0]~0_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[2]~2_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [2]))))
|
|
|
|
.dataa(\ula_|border [2]),
|
|
.datab(\ula_|video_|screen_en~1_combout ),
|
|
.datac(\ula_|video_|disp_enable~1_combout ),
|
|
.datad(\ula_|video_|cindex[2]~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|VGA_G[0]~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|VGA_G[0]~0 .lut_mask = 16'hE020;
|
|
defparam \ula_|video_|VGA_G[0]~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X36_Y32_N18
|
|
cycloneive_lcell_comb \ula_|video_|VGA_G[1]~1 (
|
|
// Equation(s):
|
|
// \ula_|video_|VGA_G[1]~1_combout = (\ula_|video_|VGA_B[1]~0_combout & (\ula_|video_|screen_en~1_combout & \ula_|video_|cindex[2]~2_combout ))
|
|
|
|
.dataa(\ula_|video_|VGA_B[1]~0_combout ),
|
|
.datab(\ula_|video_|screen_en~1_combout ),
|
|
.datac(gnd),
|
|
.datad(\ula_|video_|cindex[2]~2_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|VGA_G[1]~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|VGA_G[1]~1 .lut_mask = 16'h8800;
|
|
defparam \ula_|video_|VGA_G[1]~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X23_Y14_N19
|
|
dffeas \ula_|border[0] (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\D[0]~46_combout ),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\ula_|always0~3_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|border [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|border[0] .is_wysiwyg = "true";
|
|
defparam \ula_|border[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X38_Y32_N24
|
|
cycloneive_lcell_comb \ula_|video_|attr_prefetch[0]~feeder (
|
|
// Equation(s):
|
|
// \ula_|video_|attr_prefetch[0]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\ram0|altsyncram_component|auto_generated|ram_block1a0~PORTBDATAOUT0 ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|attr_prefetch[0]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|attr_prefetch[0]~feeder .lut_mask = 16'hFF00;
|
|
defparam \ula_|video_|attr_prefetch[0]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X38_Y32_N25
|
|
dffeas \ula_|video_|attr_prefetch[0] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|attr_prefetch[0]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|video_|Decoder0~1_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|attr_prefetch [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|attr_prefetch[0] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|attr_prefetch[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y32_N10
|
|
cycloneive_lcell_comb \ula_|video_|attr[0]~feeder (
|
|
// Equation(s):
|
|
// \ula_|video_|attr[0]~feeder_combout = \ula_|video_|attr_prefetch [0]
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\ula_|video_|attr_prefetch [0]),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|attr[0]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|attr[0]~feeder .lut_mask = 16'hFF00;
|
|
defparam \ula_|video_|attr[0]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y32_N11
|
|
dffeas \ula_|video_|attr[0] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|attr[0]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|video_|Decoder0~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|attr [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|attr[0] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|attr[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X38_Y32_N30
|
|
cycloneive_lcell_comb \ula_|video_|attr_prefetch[3]~feeder (
|
|
// Equation(s):
|
|
// \ula_|video_|attr_prefetch[3]~feeder_combout = \ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\ram0|altsyncram_component|auto_generated|ram_block1a3~PORTBDATAOUT0 ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|attr_prefetch[3]~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|attr_prefetch[3]~feeder .lut_mask = 16'hFF00;
|
|
defparam \ula_|video_|attr_prefetch[3]~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X38_Y32_N31
|
|
dffeas \ula_|video_|attr_prefetch[3] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|attr_prefetch[3]~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|video_|Decoder0~1_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|attr_prefetch [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|attr_prefetch[3] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|attr_prefetch[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X37_Y32_N17
|
|
dffeas \ula_|video_|attr[3] (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\ula_|video_|attr_prefetch [3]),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\ula_|video_|Decoder0~0_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|attr [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|attr[3] .is_wysiwyg = "true";
|
|
defparam \ula_|video_|attr[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y32_N16
|
|
cycloneive_lcell_comb \ula_|video_|cindex[0]~3 (
|
|
// Equation(s):
|
|
// \ula_|video_|cindex[0]~3_combout = (\ula_|video_|cindex[1]~0_combout & (\ula_|video_|attr [0])) # (!\ula_|video_|cindex[1]~0_combout & ((\ula_|video_|attr [3])))
|
|
|
|
.dataa(\ula_|video_|attr [0]),
|
|
.datab(gnd),
|
|
.datac(\ula_|video_|attr [3]),
|
|
.datad(\ula_|video_|cindex[1]~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|cindex[0]~3_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|cindex[0]~3 .lut_mask = 16'hAAF0;
|
|
defparam \ula_|video_|cindex[0]~3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y32_N14
|
|
cycloneive_lcell_comb \ula_|video_|VGA_B[0]~1 (
|
|
// Equation(s):
|
|
// \ula_|video_|VGA_B[0]~1_combout = (\ula_|video_|disp_enable~1_combout & ((\ula_|video_|screen_en~1_combout & ((\ula_|video_|cindex[0]~3_combout ))) # (!\ula_|video_|screen_en~1_combout & (\ula_|border [0]))))
|
|
|
|
.dataa(\ula_|video_|screen_en~1_combout ),
|
|
.datab(\ula_|border [0]),
|
|
.datac(\ula_|video_|disp_enable~1_combout ),
|
|
.datad(\ula_|video_|cindex[0]~3_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|VGA_B[0]~1_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|VGA_B[0]~1 .lut_mask = 16'hE040;
|
|
defparam \ula_|video_|VGA_B[0]~1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X37_Y32_N4
|
|
cycloneive_lcell_comb \ula_|video_|VGA_B[1]~2 (
|
|
// Equation(s):
|
|
// \ula_|video_|VGA_B[1]~2_combout = (\ula_|video_|VGA_B[1]~0_combout & (\ula_|video_|screen_en~1_combout & \ula_|video_|cindex[0]~3_combout ))
|
|
|
|
.dataa(\ula_|video_|VGA_B[1]~0_combout ),
|
|
.datab(gnd),
|
|
.datac(\ula_|video_|screen_en~1_combout ),
|
|
.datad(\ula_|video_|cindex[0]~3_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|VGA_B[1]~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|VGA_B[1]~2 .lut_mask = 16'hA000;
|
|
defparam \ula_|video_|VGA_B[1]~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y31_N22
|
|
cycloneive_lcell_comb \ula_|video_|Equal0~2 (
|
|
// Equation(s):
|
|
// \ula_|video_|Equal0~2_combout = (!\ula_|video_|vga_hc [8] & (\ula_|video_|vga_hc [6] & !\ula_|video_|vga_hc [9]))
|
|
|
|
.dataa(gnd),
|
|
.datab(\ula_|video_|vga_hc [8]),
|
|
.datac(\ula_|video_|vga_hc [6]),
|
|
.datad(\ula_|video_|vga_hc [9]),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|Equal0~2_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Equal0~2 .lut_mask = 16'h0030;
|
|
defparam \ula_|video_|Equal0~2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y31_N21
|
|
dffeas \ula_|video_|VGA_HS~_Duplicate_1 (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|Selector0~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|VGA_HS~_Duplicate_1_q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|VGA_HS~_Duplicate_1 .is_wysiwyg = "true";
|
|
defparam \ula_|video_|VGA_HS~_Duplicate_1 .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y31_N20
|
|
cycloneive_lcell_comb \ula_|video_|Selector0~0 (
|
|
// Equation(s):
|
|
// \ula_|video_|Selector0~0_combout = (\ula_|video_|Equal0~2_combout & ((\ula_|video_|Equal0~1_combout ) # ((\ula_|video_|VGA_HS~_Duplicate_1_q & \ula_|video_|Equal1~0_combout )))) # (!\ula_|video_|Equal0~2_combout & (((\ula_|video_|VGA_HS~_Duplicate_1_q
|
|
// & \ula_|video_|Equal1~0_combout ))))
|
|
|
|
.dataa(\ula_|video_|Equal0~2_combout ),
|
|
.datab(\ula_|video_|Equal0~1_combout ),
|
|
.datac(\ula_|video_|VGA_HS~_Duplicate_1_q ),
|
|
.datad(\ula_|video_|Equal1~0_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|Selector0~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Selector0~0 .lut_mask = 16'hF888;
|
|
defparam \ula_|video_|Selector0~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: DDIOOUTCELL_X51_Y34_N25
|
|
dffeas \ula_|video_|VGA_HS (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|Selector0~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|VGA_HS~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|VGA_HS .is_wysiwyg = "true";
|
|
defparam \ula_|video_|VGA_HS .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X35_Y32_N5
|
|
dffeas \ula_|video_|VGA_VS~_Duplicate_1 (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|Selector1~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|VGA_VS~_Duplicate_1_q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|VGA_VS~_Duplicate_1 .is_wysiwyg = "true";
|
|
defparam \ula_|video_|VGA_VS~_Duplicate_1 .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X35_Y32_N4
|
|
cycloneive_lcell_comb \ula_|video_|Selector1~0 (
|
|
// Equation(s):
|
|
// \ula_|video_|Selector1~0_combout = (\ula_|video_|Equal2~2_combout & ((\ula_|video_|vga_vc [1]) # ((\ula_|video_|VGA_VS~_Duplicate_1_q & !\ula_|video_|Equal3~1_combout )))) # (!\ula_|video_|Equal2~2_combout & (((\ula_|video_|VGA_VS~_Duplicate_1_q &
|
|
// !\ula_|video_|Equal3~1_combout ))))
|
|
|
|
.dataa(\ula_|video_|Equal2~2_combout ),
|
|
.datab(\ula_|video_|vga_vc [1]),
|
|
.datac(\ula_|video_|VGA_VS~_Duplicate_1_q ),
|
|
.datad(\ula_|video_|Equal3~1_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|video_|Selector1~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|Selector1~0 .lut_mask = 16'h88F8;
|
|
defparam \ula_|video_|Selector1~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: DDIOOUTCELL_X43_Y34_N25
|
|
dffeas \ula_|video_|VGA_VS (
|
|
.clk(\ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ),
|
|
.d(\ula_|video_|Selector1~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|video_|VGA_VS~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|video_|VGA_VS .is_wysiwyg = "true";
|
|
defparam \ula_|video_|VGA_VS .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y13_N26
|
|
cycloneive_lcell_comb \z80_|memory_ifc_|q1~feeder (
|
|
// Equation(s):
|
|
// \z80_|memory_ifc_|q1~feeder_combout = \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|memory_ifc_|q1~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|memory_ifc_|q1~feeder .lut_mask = 16'hFF00;
|
|
defparam \z80_|memory_ifc_|q1~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X27_Y13_N27
|
|
dffeas \z80_|memory_ifc_|q1 (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\z80_|memory_ifc_|q1~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\z80_|clk_delay_|hold_clk_iorq~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|memory_ifc_|q1~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|memory_ifc_|q1 .is_wysiwyg = "true";
|
|
defparam \z80_|memory_ifc_|q1 .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X27_Y13_N17
|
|
dffeas \z80_|memory_ifc_|q2 (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(gnd),
|
|
.asdata(\z80_|memory_ifc_|q1~q ),
|
|
.clrn(\z80_|resets_|SYNTHESIZED_WIRE_12~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(vcc),
|
|
.ena(\z80_|clk_delay_|hold_clk_iorq~combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\z80_|memory_ifc_|q2~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \z80_|memory_ifc_|q2 .is_wysiwyg = "true";
|
|
defparam \z80_|memory_ifc_|q2 .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y13_N16
|
|
cycloneive_lcell_comb \z80_|memory_ifc_|nRFSH_out~0 (
|
|
// Equation(s):
|
|
// \z80_|memory_ifc_|nRFSH_out~0_combout = (!\z80_|memory_ifc_|q2~q & \z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\z80_|memory_ifc_|q2~q ),
|
|
.datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|memory_ifc_|nRFSH_out~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|memory_ifc_|nRFSH_out~0 .lut_mask = 16'h0F00;
|
|
defparam \z80_|memory_ifc_|nRFSH_out~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X27_Y13_N20
|
|
cycloneive_lcell_comb \z80_|memory_ifc_|nM1_out (
|
|
// Equation(s):
|
|
// \z80_|memory_ifc_|nM1_out~combout = (\z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ) # (!\z80_|resets_|SYNTHESIZED_WIRE_12~q )
|
|
|
|
.dataa(\z80_|resets_|SYNTHESIZED_WIRE_12~q ),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\z80_|memory_ifc_|SYNTHESIZED_WIRE_16~q ),
|
|
.cin(gnd),
|
|
.combout(\z80_|memory_ifc_|nM1_out~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \z80_|memory_ifc_|nM1_out .lut_mask = 16'hFF55;
|
|
defparam \z80_|memory_ifc_|nM1_out .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X24_Y10_N28
|
|
cycloneive_lcell_comb \ula_|beep~0 (
|
|
// Equation(s):
|
|
// \ula_|beep~0_combout = \raw_loader_in~input_o $ (\D[3]~74_combout $ (\D[4]~76_combout ))
|
|
|
|
.dataa(\raw_loader_in~input_o ),
|
|
.datab(\D[3]~74_combout ),
|
|
.datac(gnd),
|
|
.datad(\D[4]~76_combout ),
|
|
.cin(gnd),
|
|
.combout(\ula_|beep~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \ula_|beep~0 .lut_mask = 16'h9966;
|
|
defparam \ula_|beep~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X24_Y10_N29
|
|
dffeas \ula_|beep (
|
|
.clk(\ula_|clocks_|clk_cpu~clkctrl_outclk ),
|
|
.d(\ula_|beep~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(\ula_|always0~3_combout ),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\ula_|beep~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \ula_|beep .is_wysiwyg = "true";
|
|
defparam \ula_|beep .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOIBUF_X0_Y16_N22
|
|
cycloneive_io_ibuf \SW[0]~input (
|
|
.i(SW[0]),
|
|
.ibar(gnd),
|
|
.o(\SW[0]~input_o ));
|
|
// synopsys translate_off
|
|
defparam \SW[0]~input .bus_hold = "false";
|
|
defparam \SW[0]~input .simulate_z_as = "z";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOIBUF_X53_Y17_N15
|
|
cycloneive_io_ibuf \SW[3]~input (
|
|
.i(SW[3]),
|
|
.ibar(gnd),
|
|
.o(\SW[3]~input_o ));
|
|
// synopsys translate_off
|
|
defparam \SW[3]~input .bus_hold = "false";
|
|
defparam \SW[3]~input .simulate_z_as = "z";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOIBUF_X0_Y24_N22
|
|
cycloneive_io_ibuf \I2C_SCLK~input (
|
|
.i(I2C_SCLK),
|
|
.ibar(gnd),
|
|
.o(\I2C_SCLK~input_o ));
|
|
// synopsys translate_off
|
|
defparam \I2C_SCLK~input .bus_hold = "false";
|
|
defparam \I2C_SCLK~input .simulate_z_as = "z";
|
|
// synopsys translate_on
|
|
|
|
endmodule
|