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de0-zx-spectrum/output_files/spectrum.sta.rpt
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benny f114ff0549 Fixed clocks
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TimeQuest Timing Analyzer report for spectrum
Sat Apr 2 15:53:41 2022
Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. TimeQuest Timing Analyzer Summary
3. Parallel Compilation
4. SDC File List
5. Clocks
6. Slow 1200mV 85C Model Fmax Summary
7. Timing Closure Recommendations
8. Slow 1200mV 85C Model Setup Summary
9. Slow 1200mV 85C Model Hold Summary
10. Slow 1200mV 85C Model Recovery Summary
11. Slow 1200mV 85C Model Removal Summary
12. Slow 1200mV 85C Model Minimum Pulse Width Summary
13. Slow 1200mV 85C Model Setup: 'CLOCK_50'
14. Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
15. Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
16. Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
17. Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
18. Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
19. Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
20. Slow 1200mV 85C Model Hold: 'CLOCK_50'
21. Slow 1200mV 85C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
22. Slow 1200mV 85C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
23. Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50'
24. Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
25. Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
26. Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
27. Setup Times
28. Hold Times
29. Clock to Output Times
30. Minimum Clock to Output Times
31. Propagation Delay
32. Minimum Propagation Delay
33. Slow 1200mV 85C Model Metastability Report
34. Slow 1200mV 0C Model Fmax Summary
35. Slow 1200mV 0C Model Setup Summary
36. Slow 1200mV 0C Model Hold Summary
37. Slow 1200mV 0C Model Recovery Summary
38. Slow 1200mV 0C Model Removal Summary
39. Slow 1200mV 0C Model Minimum Pulse Width Summary
40. Slow 1200mV 0C Model Setup: 'CLOCK_50'
41. Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
42. Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
43. Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
44. Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
45. Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
46. Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
47. Slow 1200mV 0C Model Hold: 'CLOCK_50'
48. Slow 1200mV 0C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
49. Slow 1200mV 0C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
50. Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'
51. Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
52. Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
53. Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
54. Setup Times
55. Hold Times
56. Clock to Output Times
57. Minimum Clock to Output Times
58. Propagation Delay
59. Minimum Propagation Delay
60. Slow 1200mV 0C Model Metastability Report
61. Fast 1200mV 0C Model Setup Summary
62. Fast 1200mV 0C Model Hold Summary
63. Fast 1200mV 0C Model Recovery Summary
64. Fast 1200mV 0C Model Removal Summary
65. Fast 1200mV 0C Model Minimum Pulse Width Summary
66. Fast 1200mV 0C Model Setup: 'CLOCK_50'
67. Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
68. Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
69. Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
70. Fast 1200mV 0C Model Hold: 'CLOCK_50'
71. Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
72. Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
73. Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
74. Fast 1200mV 0C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
75. Fast 1200mV 0C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
76. Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'
77. Fast 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]'
78. Fast 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]'
79. Fast 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]'
80. Setup Times
81. Hold Times
82. Clock to Output Times
83. Minimum Clock to Output Times
84. Propagation Delay
85. Minimum Propagation Delay
86. Fast 1200mV 0C Model Metastability Report
87. Multicorner Timing Analysis Summary
88. Setup Times
89. Hold Times
90. Clock to Output Times
91. Minimum Clock to Output Times
92. Propagation Delay
93. Minimum Propagation Delay
94. Board Trace Model Assignments
95. Input Transition Times
96. Signal Integrity Metrics (Slow 1200mv 0c Model)
97. Signal Integrity Metrics (Slow 1200mv 85c Model)
98. Signal Integrity Metrics (Fast 1200mv 0c Model)
99. Setup Transfers
100. Hold Transfers
101. Recovery Transfers
102. Removal Transfers
103. Report TCCS
104. Report RSKM
105. Unconstrained Paths
106. TimeQuest Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary ;
+--------------------+----------------------------------------------------+
; Quartus II Version ; Version 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
; Revision Name ; spectrum ;
; Device Family ; Cyclone IV E ;
; Device Name ; EP4CE22F17C6 ;
; Timing Models ; Final ;
; Delay Model ; Combined ;
; Rise/Fall Delays ; Enabled ;
+--------------------+----------------------------------------------------+
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation ;
+----------------------------+--------+
; Processors ; Number ;
+----------------------------+--------+
; Number detected on machine ; 12 ;
; Maximum allowed ; 1 ;
+----------------------------+--------+
+--------------------------------------------------------------------------------+
; SDC File List ;
+--------------------------------------------------------------------------------+
SDC File Path : spectrum.sdc
Status : OK
Read at : Sat Apr 2 15:53:38 2022
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Clocks ;
+--------------------------------------------------------------------------------+
Clock Name : beep
Type : Base
Period : 10.000
Frequency : 100.0 MHz
Rise : 0.000
Fall : 5.000
Duty Cycle :
Divide by :
Multiply by :
Phase :
Offset :
Edge List :
Edge Shift :
Inverted :
Master :
Source :
Targets : { ula:ula_|beep }
Clock Name : CLOCK_50
Type : Base
Period : 20.000
Frequency : 50.0 MHz
Rise : 0.000
Fall : 10.000
Duty Cycle :
Divide by :
Multiply by :
Phase :
Offset :
Edge List :
Edge Shift :
Inverted :
Master :
Source :
Targets : { CLOCK_50 }
Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Type : Generated
Period : 39.716
Frequency : 25.18 MHz
Rise : 0.000
Fall : 19.858
Duty Cycle : 50.00
Divide by : 280
Multiply by : 141
Phase :
Offset :
Edge List :
Edge Shift :
Inverted : false
Master : CLOCK_50
Source : ula_|pll_|altpll_component|auto_generated|pll1|inclk[0]
Targets : { ula_|pll_|altpll_component|auto_generated|pll1|clk[0] }
Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Type : Generated
Period : 71.489
Frequency : 13.99 MHz
Rise : 0.000
Fall : 35.744
Duty Cycle : 50.00
Divide by : 168
Multiply by : 47
Phase :
Offset :
Edge List :
Edge Shift :
Inverted : false
Master : CLOCK_50
Source : ula_|pll_|altpll_component|auto_generated|pll1|inclk[0]
Targets : { ula_|pll_|altpll_component|auto_generated|pll1|clk[1] }
Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Type : Generated
Period : 41.702
Frequency : 23.98 MHz
Rise : 0.000
Fall : 20.851
Duty Cycle : 50.00
Divide by : 98
Multiply by : 47
Phase :
Offset :
Edge List :
Edge Shift :
Inverted : false
Master : CLOCK_50
Source : ula_|pll_|altpll_component|auto_generated|pll1|inclk[0]
Targets : { ula_|pll_|altpll_component|auto_generated|pll1|clk[2] }
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary ;
+--------------------------------------------------------------------------------+
Fmax : 50.46 MHz
Restricted Fmax : 50.46 MHz
Clock Name : CLOCK_50
Note :
Fmax : 129.4 MHz
Restricted Fmax : 129.4 MHz
Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Note :
Fmax : 173.94 MHz
Restricted Fmax : 173.94 MHz
Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Note :
Fmax : 940.73 MHz
Restricted Fmax : 500.0 MHz
Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Note : limit due to minimum period restriction (tmin)
+--------------------------------------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup Summary ;
+--------------------------------------------------------------------------------+
Clock : CLOCK_50
Slack : -18.425
End Point TNS : -546.891
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Slack : -6.923
End Point TNS : -271.506
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : -4.745
End Point TNS : -42.191
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Slack : -2.915
End Point TNS : -2.915
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold Summary ;
+--------------------------------------------------------------------------------+
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Slack : 0.342
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : 0.342
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Slack : 0.357
End Point TNS : 0.000
Clock : CLOCK_50
Slack : 0.517
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery Summary ;
+--------------------------------------------------------------------------------+
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : -6.263
End Point TNS : -464.840
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal Summary ;
+--------------------------------------------------------------------------------+
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : 3.657
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
+--------------------------------------------------------------------------------+
Clock : CLOCK_50
Slack : 9.488
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Slack : 19.602
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : 20.597
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Slack : 35.503
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : -18.425
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.249
Data Delay : 8.250
Slack : -18.317
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.249
Data Delay : 8.142
Slack : -18.277
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.249
Data Delay : 8.102
Slack : -18.178
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.249
Data Delay : 8.003
Slack : -18.138
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.247
Data Delay : 7.965
Slack : -18.132
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.247
Data Delay : 7.959
Slack : -18.098
From Node : ula:ula_|video:video_|vga_hc[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.249
Data Delay : 7.923
Slack : -18.027
From Node : ula:ula_|video:video_|vga_hc[1]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.249
Data Delay : 7.852
Slack : -17.997
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.249
Data Delay : 7.822
Slack : -17.976
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.249
Data Delay : 7.801
Slack : -17.952
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.247
Data Delay : 7.779
Slack : -17.936
From Node : ula:ula_|video:video_|vga_hc[9]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.249
Data Delay : 7.761
Slack : -17.926
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.227
Data Delay : 7.773
Slack : -17.876
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.247
Data Delay : 7.703
Slack : -17.849
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.227
Data Delay : 7.696
Slack : -17.838
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.515
Data Delay : 7.397
Slack : -17.822
From Node : ula:ula_|video:video_|bits[5]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.247
Data Delay : 7.649
Slack : -17.822
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.247
Data Delay : 7.649
Slack : -17.818
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.249
Data Delay : 7.643
Slack : -17.806
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.249
Data Delay : 7.631
Slack : -17.801
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.249
Data Delay : 7.626
Slack : -17.792
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.249
Data Delay : 7.617
Slack : -17.792
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.227
Data Delay : 7.639
Slack : -17.769
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.526
Data Delay : 7.317
Slack : -17.761
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.232
Data Delay : 7.603
Slack : -17.731
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.232
Data Delay : 7.573
Slack : -17.725
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.511
Data Delay : 7.288
Slack : -17.721
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.232
Data Delay : 7.563
Slack : -17.684
From Node : ula:ula_|video:video_|bits[6]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.247
Data Delay : 7.511
Slack : -17.682
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.232
Data Delay : 7.524
Slack : -17.673
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.526
Data Delay : 7.221
Slack : -17.653
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.515
Data Delay : 7.212
Slack : -17.600
From Node : ula:ula_|video:video_|bits[1]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.247
Data Delay : 7.427
Slack : -17.586
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 7.144
Slack : -17.577
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.227
Data Delay : 7.424
Slack : -17.544
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 7.102
Slack : -17.512
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.523
Data Delay : 7.063
Slack : -17.508
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.513
Data Delay : 7.069
Slack : -17.503
From Node : ula:ula_|video:video_|bits[2]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.247
Data Delay : 7.330
Slack : -17.499
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.509
Data Delay : 7.064
Slack : -17.477
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.227
Data Delay : 7.324
Slack : -17.476
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.522
Data Delay : 7.028
Slack : -17.472
From Node : ula:ula_|video:video_|bits[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.247
Data Delay : 7.299
Slack : -17.464
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 7.014
Slack : -17.462
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.227
Data Delay : 7.309
Slack : -17.457
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.507
Data Delay : 7.024
Slack : -17.455
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.515
Data Delay : 7.014
Slack : -17.452
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.227
Data Delay : 7.299
Slack : -17.451
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.505
Data Delay : 7.020
Slack : -17.438
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.232
Data Delay : 7.280
Slack : -17.435
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.514
Data Delay : 6.995
Slack : -17.420
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.507
Data Delay : 6.987
Slack : -17.417
From Node : ula:ula_|video:video_|vga_hc[3]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.249
Data Delay : 7.242
Slack : -17.416
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.523
Data Delay : 6.967
Slack : -17.401
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.513
Data Delay : 6.962
Slack : -17.398
From Node : ula:ula_|video:video_|frame[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.247
Data Delay : 7.225
Slack : -17.396
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.232
Data Delay : 7.238
Slack : -17.385
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : VGA_R[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.249
Data Delay : 7.210
Slack : -17.374
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.514
Data Delay : 6.934
Slack : -17.357
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.907
Slack : -17.354
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.227
Data Delay : 7.201
Slack : -17.353
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.534
Data Delay : 6.893
Slack : -17.341
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.891
Slack : -17.337
From Node : ula:ula_|video:video_|bits[3]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.247
Data Delay : 7.164
Slack : -17.329
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.879
Slack : -17.329
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.514
Data Delay : 6.889
Slack : -17.327
From Node : ula:ula_|video:video_|attr[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.247
Data Delay : 7.154
Slack : -17.324
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.874
Slack : -17.324
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.515
Data Delay : 6.883
Slack : -17.312
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.514
Data Delay : 6.872
Slack : -17.303
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.853
Slack : -17.282
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.521
Data Delay : 6.835
Slack : -17.277
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.509
Data Delay : 6.842
Slack : -17.266
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.511
Data Delay : 6.829
Slack : -17.238
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.518
Data Delay : 6.794
Slack : -17.237
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : VGA_R[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.249
Data Delay : 7.062
Slack : -17.212
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.533
Data Delay : 6.753
Slack : -17.208
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.758
Slack : -17.165
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : VGA_R[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.249
Data Delay : 6.990
Slack : -17.164
From Node : ula:ula_|video:video_|bits[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.247
Data Delay : 6.991
Slack : -17.161
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.515
Data Delay : 6.720
Slack : -17.160
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : VGA_R[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.249
Data Delay : 6.985
Slack : -17.141
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.691
Slack : -17.138
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.522
Data Delay : 6.690
Slack : -17.113
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : VGA_R[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.247
Data Delay : 6.940
Slack : -17.113
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.520
Data Delay : 6.667
Slack : -17.107
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : VGA_R[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.247
Data Delay : 6.934
Slack : -17.058
From Node : ula:ula_|video:video_|vga_hc[7]
To Node : VGA_R[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.249
Data Delay : 6.883
Slack : -17.050
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.535
Data Delay : 6.589
Slack : -17.034
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.232
Data Delay : 6.876
Slack : -17.027
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.522
Data Delay : 6.579
Slack : -17.025
From Node : ula:ula_|video:video_|bits[0]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.247
Data Delay : 6.852
Slack : -17.025
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.575
Slack : -17.014
From Node : ula:ula_|video:video_|vga_hc[1]
To Node : VGA_R[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.249
Data Delay : 6.839
Slack : -16.986
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.544
Slack : -16.964
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.523
Data Delay : 6.515
Slack : -16.959
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : VGA_R[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.249
Data Delay : 6.784
Slack : -16.957
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : VGA_R[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.249
Data Delay : 6.782
Slack : -16.944
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.502
Slack : -16.927
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.515
Data Delay : 6.486
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : -6.923
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.984
Data Delay : 5.047
Slack : -6.749
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.252
Data Delay : 4.605
Slack : -6.727
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.251
Data Delay : 4.584
Slack : -6.700
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.251
Data Delay : 4.557
Slack : -6.643
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.234
Data Delay : 4.517
Slack : -6.626
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.234
Data Delay : 4.500
Slack : -6.626
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.236
Data Delay : 4.498
Slack : -6.608
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.251
Data Delay : 4.465
Slack : -6.602
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.254
Data Delay : 4.456
Slack : -6.563
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.984
Data Delay : 4.687
Slack : -6.553
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.257
Data Delay : 4.404
Slack : -6.550
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.984
Data Delay : 4.674
Slack : -6.549
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.256
Data Delay : 4.401
Slack : -6.533
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.984
Data Delay : 4.657
Slack : -6.525
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.248
Data Delay : 4.385
Slack : -6.513
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.252
Data Delay : 4.369
Slack : -6.509
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.245
Data Delay : 4.372
Slack : -6.499
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.988
Data Delay : 4.619
Slack : -6.498
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.248
Data Delay : 4.358
Slack : -6.485
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.254
Data Delay : 4.339
Slack : -6.476
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.244
Data Delay : 4.340
Slack : -6.470
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.254
Data Delay : 4.324
Slack : -6.469
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.264
Data Delay : 4.313
Slack : -6.468
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.254
Data Delay : 4.322
Slack : -6.468
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.256
Data Delay : 4.320
Slack : -6.454
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.251
Data Delay : 4.311
Slack : -6.454
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.243
Data Delay : 4.319
Slack : -6.427
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.243
Data Delay : 4.292
Slack : -6.425
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.252
Data Delay : 4.281
Slack : -6.420
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.243
Data Delay : 4.285
Slack : -6.416
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.266
Data Delay : 4.258
Slack : -6.409
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.249
Data Delay : 4.268
Slack : -6.406
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.254
Data Delay : 4.260
Slack : -6.406
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.255
Data Delay : 4.259
Slack : -6.400
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.238
Data Delay : 4.270
Slack : -6.390
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.257
Data Delay : 4.241
Slack : -6.365
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.258
Data Delay : 4.215
Slack : -6.362
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.252
Data Delay : 4.218
Slack : -6.361
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.258
Data Delay : 4.211
Slack : -6.329
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.003
Data Delay : 4.434
Slack : -6.323
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.252
Data Delay : 4.179
Slack : -6.282
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.239
Data Delay : 4.151
Slack : -6.279
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.246
Data Delay : 4.141
Slack : -6.246
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.000
Data Delay : 4.354
Slack : -6.242
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.258
Data Delay : 4.092
Slack : -6.241
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.993
Data Delay : 4.356
Slack : -6.234
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.984
Data Delay : 4.358
Slack : -6.230
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.997
Data Delay : 4.341
Slack : -6.227
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.248
Data Delay : 4.087
Slack : -6.227
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.249
Data Delay : 4.086
Slack : -6.224
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.252
Data Delay : 4.080
Slack : -6.224
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.235
Data Delay : 4.097
Slack : -6.219
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.992
Data Delay : 4.335
Slack : -6.212
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.985
Data Delay : 4.335
Slack : -6.205
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.243
Data Delay : 4.070
Slack : -6.192
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.992
Data Delay : 4.308
Slack : -6.190
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.262
Data Delay : 4.036
Slack : -6.183
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.246
Data Delay : 4.045
Slack : -6.176
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.244
Data Delay : 4.040
Slack : -6.162
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.241
Data Delay : 4.029
Slack : -6.153
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.252
Data Delay : 4.009
Slack : -6.152
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.244
Data Delay : 4.016
Slack : -6.140
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.252
Data Delay : 3.996
Slack : -6.113
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.257
Data Delay : 3.964
Slack : -6.103
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.257
Data Delay : 3.954
Slack : -6.089
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.256
Data Delay : 3.941
Slack : -6.084
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.992
Data Delay : 4.200
Slack : -6.068
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.988
Data Delay : 4.188
Slack : -6.060
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.243
Data Delay : 3.925
Slack : -6.051
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.988
Data Delay : 4.171
Slack : -6.051
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.990
Data Delay : 4.169
Slack : -6.047
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.243
Data Delay : 3.912
Slack : -6.031
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.994
Data Delay : 4.145
Slack : -6.000
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.998
Data Delay : 4.110
Slack : -5.996
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.247
Data Delay : 3.857
Slack : -5.983
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.239
Data Delay : 3.852
Slack : -5.980
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.986
Data Delay : 4.102
Slack : -5.961
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.240
Data Delay : 3.829
Slack : -5.935
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.986
Data Delay : 4.057
Slack : -5.934
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.251
Data Delay : 3.791
Slack : -5.918
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.243
Data Delay : 3.783
Slack : -5.917
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.993
Data Delay : 4.032
Slack : -5.894
From Node : raw_loader_in
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.140
Data Delay : 4.142
Slack : -5.863
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.241
Data Delay : 3.730
Slack : -5.841
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.242
Data Delay : 3.707
Slack : -5.825
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.992
Data Delay : 3.941
Slack : -5.811
From Node : raw_loader_in
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.143
Data Delay : 4.062
Slack : -5.805
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.990
Data Delay : 3.923
Slack : -5.795
From Node : raw_loader_in
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.146
Data Delay : 4.049
Slack : -5.716
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.985
Data Delay : 3.839
Slack : -5.705
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.997
Data Delay : 3.816
Slack : -5.705
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.998
Data Delay : 3.815
Slack : -5.697
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.993
Data Delay : 3.812
Slack : -5.684
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.241
Data Delay : 3.551
Slack : -5.668
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.994
Data Delay : 3.782
Slack : -5.661
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.995
Data Delay : 3.774
Slack : -5.565
From Node : raw_loader_in
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.145
Data Delay : 3.818
Slack : -5.564
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.243
Data Delay : 3.429
Slack : -5.412
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -2.000
Data Delay : 3.520
Slack : -5.410
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.993
Data Delay : 3.525
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : -4.745
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 2.963
Slack : -4.745
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 2.963
Slack : -4.723
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.193
Data Delay : 2.814
Slack : -4.108
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.190
Data Delay : 2.677
Slack : -4.108
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.190
Data Delay : 2.677
Slack : -4.108
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.190
Data Delay : 2.677
Slack : -4.108
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.190
Data Delay : 2.677
Slack : -4.108
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.190
Data Delay : 2.677
Slack : -3.938
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 2.156
Slack : -3.500
From Node : AUD_ADCDAT
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 1.718
Slack : 16.987
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.428
Slack : 16.987
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.428
Slack : 16.987
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.428
Slack : 16.987
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.428
Slack : 16.987
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.428
Slack : 16.988
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.427
Slack : 16.988
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.427
Slack : 16.988
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.427
Slack : 16.988
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.427
Slack : 16.988
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.427
Slack : 17.088
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.327
Slack : 17.088
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.327
Slack : 17.089
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.326
Slack : 17.089
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.326
Slack : 17.132
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.283
Slack : 17.132
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.283
Slack : 17.132
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.283
Slack : 17.132
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.283
Slack : 17.132
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.283
Slack : 17.188
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 3.228
Slack : 17.189
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 3.227
Slack : 17.216
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 3.198
Slack : 17.216
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 3.198
Slack : 17.217
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 3.197
Slack : 17.217
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 3.197
Slack : 17.231
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.184
Slack : 17.231
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.184
Slack : 17.231
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.184
Slack : 17.231
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.184
Slack : 17.231
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.184
Slack : 17.233
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.182
Slack : 17.233
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.182
Slack : 17.332
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.083
Slack : 17.332
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 3.083
Slack : 17.333
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 3.083
Slack : 17.361
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 3.053
Slack : 17.361
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 3.053
Slack : 17.366
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 3.050
Slack : 17.366
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 3.050
Slack : 17.367
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 3.049
Slack : 17.367
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 3.049
Slack : 17.432
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 2.984
Slack : 17.460
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 2.954
Slack : 17.460
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.432
Data Delay : 2.954
Slack : 17.505
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.079
Data Delay : 3.262
Slack : 17.505
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.079
Data Delay : 3.262
Slack : 17.505
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.079
Data Delay : 3.262
Slack : 17.505
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.079
Data Delay : 3.262
Slack : 17.505
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.079
Data Delay : 3.262
Slack : 17.506
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.079
Data Delay : 3.261
Slack : 17.506
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.079
Data Delay : 3.261
Slack : 17.506
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.079
Data Delay : 3.261
Slack : 17.506
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.079
Data Delay : 3.261
Slack : 17.506
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.079
Data Delay : 3.261
Slack : 17.511
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 2.905
Slack : 17.511
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 2.905
Slack : 17.605
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 2.811
Slack : 17.605
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 2.811
Slack : 17.605
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 2.811
Slack : 17.605
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 2.811
Slack : 17.606
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 2.810
Slack : 17.606
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 2.810
Slack : 17.606
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 2.810
Slack : 17.606
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 2.810
Slack : 17.610
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 2.806
Slack : 17.610
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.430
Data Delay : 2.806
Slack : 17.614
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.076
Data Delay : 3.156
Slack : 17.615
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.076
Data Delay : 3.155
Slack : 17.636
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 2.779
Slack : 17.636
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 2.779
Slack : 17.636
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 2.779
Slack : 17.636
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 2.779
Slack : 17.636
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 2.779
Slack : 17.650
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.079
Data Delay : 3.117
Slack : 17.650
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.079
Data Delay : 3.117
Slack : 17.650
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.079
Data Delay : 3.117
Slack : 17.650
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.079
Data Delay : 3.117
Slack : 17.650
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.079
Data Delay : 3.117
Slack : 17.733
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 2.682
Slack : 17.733
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 2.682
Slack : 17.733
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 2.682
Slack : 17.733
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 2.682
Slack : 17.733
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 2.682
Slack : 17.737
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 2.678
Slack : 17.737
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.431
Data Delay : 2.678
Slack : 17.749
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.079
Data Delay : 3.018
Slack : 17.749
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.079
Data Delay : 3.018
Slack : 17.749
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.079
Data Delay : 3.018
Slack : 17.749
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.079
Data Delay : 3.018
Slack : 17.749
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.079
Data Delay : 3.018
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ;
+--------------------------------------------------------------------------------+
Slack : -2.915
From Node : SW[2]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.423
Clock Skew : 0.216
Data Delay : 1.509
Slack : 70.426
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 71.489
Clock Skew : -0.078
Data Delay : 0.980
Slack : 70.747
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|counter[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 71.489
Clock Skew : -0.078
Data Delay : 0.659
Slack : 70.747
From Node : ula:ula_|clocks:clocks_|clk_cpu
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 71.489
Clock Skew : -0.078
Data Delay : 0.659
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ;
+--------------------------------------------------------------------------------+
Slack : 0.342
From Node : ula:ula_|clocks:clocks_|clk_cpu
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.577
Slack : 0.345
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|counter[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.580
Slack : 0.575
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.810
Slack : 1.322
From Node : SW[2]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : -0.017
Clock Skew : 0.636
Data Delay : 1.188
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : 0.342
From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.577
Slack : 0.343
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.577
Slack : 0.343
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.577
Slack : 0.345
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.580
Slack : 0.345
From Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.580
Slack : 0.345
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.580
Slack : 0.358
From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.361
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.580
Slack : 0.361
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.580
Slack : 0.361
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.580
Slack : 0.372
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.592
Slack : 0.373
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.592
Slack : 0.373
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.593
Slack : 0.374
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.593
Slack : 0.374
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.593
Slack : 0.374
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.593
Slack : 0.374
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.593
Slack : 0.375
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.595
Slack : 0.384
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.603
Slack : 0.413
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.632
Slack : 0.424
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.643
Slack : 0.424
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.643
Slack : 0.431
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.432
Data Delay : 1.020
Slack : 0.476
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.435
Data Delay : 1.068
Slack : 0.477
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.432
Data Delay : 1.066
Slack : 0.478
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.697
Slack : 0.479
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.698
Slack : 0.480
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.699
Slack : 0.480
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.699
Slack : 0.514
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.734
Slack : 0.530
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.749
Slack : 0.533
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.752
Slack : 0.540
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.775
Slack : 0.542
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.777
Slack : 0.545
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.780
Slack : 0.547
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.782
Slack : 0.552
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.771
Slack : 0.553
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.788
Slack : 0.554
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.773
Slack : 0.554
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.774
Slack : 0.556
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.775
Slack : 0.556
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.776
Slack : 0.557
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.777
Slack : 0.558
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.778
Slack : 0.559
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.432
Data Delay : 1.148
Slack : 0.559
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 0.794
Slack : 0.567
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.786
Slack : 0.573
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.792
Slack : 0.574
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.808
Slack : 0.576
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.796
Slack : 0.578
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.812
Slack : 0.579
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.813
Slack : 0.579
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.799
Slack : 0.581
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.815
Slack : 0.588
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.807
Slack : 0.591
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.810
Slack : 0.592
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.811
Slack : 0.602
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.077
Data Delay : 0.836
Slack : 0.631
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.850
Slack : 0.633
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.852
Slack : 0.653
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.432
Data Delay : 1.242
Slack : 0.673
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.892
Slack : 0.720
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.939
Slack : 0.725
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.944
Slack : 0.729
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.948
Slack : 0.734
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.954
Slack : 0.738
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.957
Slack : 0.742
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.961
Slack : 0.749
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : -0.294
Data Delay : 0.612
Slack : 0.755
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.432
Data Delay : 1.344
Slack : 0.790
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.428
Data Delay : 1.375
Slack : 0.790
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.428
Data Delay : 1.375
Slack : 0.790
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.428
Data Delay : 1.375
Slack : 0.790
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.428
Data Delay : 1.375
Slack : 0.790
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.428
Data Delay : 1.375
Slack : 0.800
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.019
Slack : 0.813
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.032
Slack : 0.815
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 1.050
Slack : 0.816
From Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.036
Slack : 0.816
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 1.051
Slack : 0.817
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.036
Slack : 0.820
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.039
Slack : 0.823
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.042
Slack : 0.827
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.046
Slack : 0.830
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.050
Slack : 0.831
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.051
Slack : 0.831
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 1.066
Slack : 0.832
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 1.067
Slack : 0.833
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 1.068
Slack : 0.833
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.078
Data Delay : 1.068
Slack : 0.834
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.053
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 0.357
From Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.577
Slack : 0.357
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : ula:ula_|video:video_|vga_vc[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.577
Slack : 0.357
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|vga_vc[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.577
Slack : 0.357
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vga_vc[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.577
Slack : 0.357
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : ula:ula_|video:video_|vga_vc[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.577
Slack : 0.357
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : ula:ula_|video:video_|vga_vc[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vga_vc[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.358
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : ula:ula_|video:video_|vga_vc[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.577
Slack : 0.551
From Node : ula:ula_|video:video_|frame[2]
To Node : ula:ula_|video:video_|frame[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.771
Slack : 0.553
From Node : ula:ula_|video:video_|frame[3]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.773
Slack : 0.562
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 0.782
Slack : 0.825
From Node : ula:ula_|video:video_|frame[2]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.045
Slack : 0.840
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.060
Slack : 0.842
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.062
Slack : 0.903
From Node : ula:ula_|video:video_|bits_prefetch[1]
To Node : ula:ula_|video:video_|bits[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.291
Data Delay : 0.769
Slack : 0.920
From Node : ula:ula_|video:video_|bits_prefetch[5]
To Node : ula:ula_|video:video_|bits[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.291
Data Delay : 0.786
Slack : 0.978
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vram_address[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.197
Slack : 0.980
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vram_address[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.199
Slack : 0.981
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vram_address[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.200
Slack : 1.036
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : ula:ula_|video:video_|vram_address[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.255
Slack : 1.041
From Node : ula:ula_|video:video_|bits_prefetch[3]
To Node : ula:ula_|video:video_|bits[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.291
Data Delay : 0.907
Slack : 1.041
From Node : ula:ula_|video:video_|bits_prefetch[4]
To Node : ula:ula_|video:video_|bits[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.291
Data Delay : 0.907
Slack : 1.051
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.270
Slack : 1.054
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : ula:ula_|video:video_|vram_address[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.273
Slack : 1.060
From Node : ula:ula_|video:video_|vga_hc[1]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.279
Slack : 1.070
From Node : ula:ula_|video:video_|bits_prefetch[7]
To Node : ula:ula_|video:video_|bits[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.291
Data Delay : 0.936
Slack : 1.075
From Node : ula:ula_|video:video_|bits_prefetch[2]
To Node : ula:ula_|video:video_|bits[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.291
Data Delay : 0.941
Slack : 1.099
From Node : ula:ula_|video:video_|attr_prefetch[7]
To Node : ula:ula_|video:video_|attr[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.319
Data Delay : 0.937
Slack : 1.102
From Node : ula:ula_|video:video_|attr_prefetch[3]
To Node : ula:ula_|video:video_|attr[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.319
Data Delay : 0.940
Slack : 1.136
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.356
Slack : 1.144
From Node : ula:ula_|video:video_|attr_prefetch[0]
To Node : ula:ula_|video:video_|attr[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.319
Data Delay : 0.982
Slack : 1.146
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[12]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.366
Slack : 1.146
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.366
Slack : 1.224
From Node : ula:ula_|video:video_|bits_prefetch[6]
To Node : ula:ula_|video:video_|bits[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.291
Data Delay : 1.090
Slack : 1.224
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.444
Slack : 1.227
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.447
Slack : 1.230
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.449
Slack : 1.235
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : ula:ula_|video:video_|vram_address[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.455
Slack : 1.237
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.456
Slack : 1.238
From Node : ula:ula_|video:video_|vga_hc[7]
To Node : ula:ula_|video:video_|vram_address[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.457
Slack : 1.239
From Node : ula:ula_|video:video_|vga_hc[7]
To Node : ula:ula_|video:video_|vram_address[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.458
Slack : 1.280
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.499
Slack : 1.285
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vga_hc[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.504
Slack : 1.286
From Node : ula:ula_|video:video_|vga_hc[7]
To Node : ula:ula_|video:video_|vga_hc[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.505
Slack : 1.289
From Node : ula:ula_|video:video_|attr_prefetch[6]
To Node : ula:ula_|video:video_|attr[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.319
Data Delay : 1.127
Slack : 1.301
From Node : ula:ula_|video:video_|attr_prefetch[4]
To Node : ula:ula_|video:video_|attr[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.319
Data Delay : 1.139
Slack : 1.325
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.544
Slack : 1.329
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.548
Slack : 1.347
From Node : ula:ula_|video:video_|attr_prefetch[5]
To Node : ula:ula_|video:video_|attr[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.319
Data Delay : 1.185
Slack : 1.379
From Node : ula:ula_|video:video_|vga_hc[3]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.597
Slack : 1.389
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.608
Slack : 1.410
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.630
Slack : 1.412
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.632
Slack : 1.435
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.654
Slack : 1.438
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.656
Slack : 1.449
From Node : ula:ula_|video:video_|frame[4]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.669
Slack : 1.470
From Node : ula:ula_|video:video_|frame[3]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.688
Slack : 1.472
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.290
Data Delay : 1.339
Slack : 1.484
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : ula:ula_|video:video_|vram_address[12]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.064
Data Delay : 1.705
Slack : 1.485
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : ula:ula_|video:video_|vram_address[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.064
Data Delay : 1.706
Slack : 1.519
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.738
Slack : 1.565
From Node : ula:ula_|video:video_|frame[2]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.783
Slack : 1.576
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vga_hc[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.795
Slack : 1.582
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.800
Slack : 1.610
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.830
Slack : 1.612
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.832
Slack : 1.623
From Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
To Node : ula:ula_|video:video_|VGA_VS
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.038
Data Delay : 1.758
Slack : 1.633
From Node : ula:ula_|video:video_|vga_hc[9]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.851
Slack : 1.645
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.865
Slack : 1.647
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.867
Slack : 1.653
From Node : ula:ula_|video:video_|vga_hc[3]
To Node : ula:ula_|video:video_|vga_hc[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.872
Slack : 1.673
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.892
Slack : 1.679
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.898
Slack : 1.697
From Node : ula:ula_|video:video_|attr_prefetch[2]
To Node : ula:ula_|video:video_|attr[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.319
Data Delay : 1.535
Slack : 1.712
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.064
Data Delay : 1.933
Slack : 1.721
From Node : ula:ula_|video:video_|vga_hc[3]
To Node : ula:ula_|video:video_|vga_hc[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 1.940
Slack : 1.722
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.942
Slack : 1.729
From Node : ula:ula_|video:video_|bits_prefetch[0]
To Node : ula:ula_|video:video_|bits[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.291
Data Delay : 1.595
Slack : 1.733
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.953
Slack : 1.735
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.955
Slack : 1.755
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 1.973
Slack : 1.757
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.977
Slack : 1.759
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.064
Data Delay : 1.980
Slack : 1.779
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 1.999
Slack : 1.796
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 2.015
Slack : 1.800
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : ula:ula_|video:video_|vga_vc[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 2.018
Slack : 1.801
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : ula:ula_|video:video_|vga_vc[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 2.019
Slack : 1.811
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : ula:ula_|video:video_|vga_vc[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 2.031
Slack : 1.818
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 2.038
Slack : 1.824
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.064
Data Delay : 2.045
Slack : 1.829
From Node : ula:ula_|video:video_|attr_prefetch[1]
To Node : ula:ula_|video:video_|attr[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.319
Data Delay : 1.667
Slack : 1.829
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : ula:ula_|video:video_|vga_hc[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 2.048
Slack : 1.845
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 2.065
Slack : 1.860
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.061
Data Delay : 2.078
Slack : 1.862
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 2.082
Slack : 1.866
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : ula:ula_|video:video_|vram_address[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 2.086
Slack : 1.869
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : ula:ula_|video:video_|vga_vc[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.063
Data Delay : 2.089
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : 0.517
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.062
Data Delay : 0.736
Slack : 0.518
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.651
Data Delay : 3.460
Slack : 0.525
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.637
Data Delay : 3.453
Slack : 1.193
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.366
Data Delay : 3.850
Slack : 1.200
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.559
Data Delay : 4.050
Slack : 1.200
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.352
Data Delay : 3.843
Slack : 1.205
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.563
Data Delay : 4.059
Slack : 1.206
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.577
Data Delay : 4.074
Slack : 1.214
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.566
Data Delay : 4.071
Slack : 1.220
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.562
Data Delay : 4.073
Slack : 1.220
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.656
Data Delay : 4.167
Slack : 1.221
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.564
Data Delay : 4.076
Slack : 1.221
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.572
Data Delay : 4.084
Slack : 1.224
From Node : ula:ula_|video:video_|vram_address[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.576
Data Delay : 4.091
Slack : 1.227
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.642
Data Delay : 4.160
Slack : 1.228
From Node : ula:ula_|video:video_|vram_address[9]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.558
Data Delay : 4.077
Slack : 1.233
From Node : ula:ula_|video:video_|vram_address[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.572
Data Delay : 4.096
Slack : 1.241
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.576
Data Delay : 4.108
Slack : 1.243
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.570
Data Delay : 4.104
Slack : 1.244
From Node : ula:ula_|video:video_|vram_address[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.570
Data Delay : 4.105
Slack : 1.246
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.571
Data Delay : 4.108
Slack : 1.256
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.569
Data Delay : 4.116
Slack : 1.259
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.556
Data Delay : 4.106
Slack : 1.265
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.576
Data Delay : 4.132
Slack : 1.266
From Node : ula:ula_|video:video_|vram_address[9]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.561
Data Delay : 4.118
Slack : 1.267
From Node : ula:ula_|video:video_|vram_address[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.566
Data Delay : 4.124
Slack : 1.269
From Node : ula:ula_|video:video_|vram_address[9]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.568
Data Delay : 4.128
Slack : 1.271
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.562
Data Delay : 4.124
Slack : 1.271
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.555
Data Delay : 4.117
Slack : 1.272
From Node : ula:ula_|video:video_|vram_address[9]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.563
Data Delay : 4.126
Slack : 1.272
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.551
Data Delay : 4.114
Slack : 1.272
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.553
Data Delay : 4.116
Slack : 1.273
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.570
Data Delay : 4.134
Slack : 1.275
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.566
Data Delay : 4.132
Slack : 1.275
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.555
Data Delay : 4.121
Slack : 1.276
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.570
Data Delay : 4.137
Slack : 1.277
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.562
Data Delay : 4.130
Slack : 1.277
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.559
Data Delay : 4.127
Slack : 1.280
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.556
Data Delay : 4.127
Slack : 1.281
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.363
Data Delay : 3.935
Slack : 1.282
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.559
Data Delay : 4.132
Slack : 1.283
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.576
Data Delay : 4.150
Slack : 1.286
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.658
Data Delay : 4.235
Slack : 1.286
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.566
Data Delay : 4.143
Slack : 1.288
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.638
Data Delay : 4.217
Slack : 1.288
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.559
Data Delay : 4.138
Slack : 1.289
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.550
Data Delay : 4.130
Slack : 1.290
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.643
Data Delay : 4.224
Slack : 1.291
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.566
Data Delay : 4.148
Slack : 1.291
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.552
Data Delay : 4.134
Slack : 1.293
From Node : ula:ula_|video:video_|vram_address[9]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.550
Data Delay : 4.134
Slack : 1.293
From Node : ula:ula_|video:video_|vram_address[9]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.552
Data Delay : 4.136
Slack : 1.294
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.561
Data Delay : 4.146
Slack : 1.294
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.554
Data Delay : 4.139
Slack : 1.296
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.564
Data Delay : 4.151
Slack : 1.296
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.556
Data Delay : 4.143
Slack : 1.296
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.570
Data Delay : 4.157
Slack : 1.297
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.555
Data Delay : 4.143
Slack : 1.300
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.550
Data Delay : 4.141
Slack : 1.300
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.563
Data Delay : 4.154
Slack : 1.301
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.563
Data Delay : 4.155
Slack : 1.301
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.576
Data Delay : 4.168
Slack : 1.303
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.558
Data Delay : 4.152
Slack : 1.304
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.559
Data Delay : 4.154
Slack : 1.305
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.564
Data Delay : 4.160
Slack : 1.306
From Node : ula:ula_|video:video_|vram_address[9]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.555
Data Delay : 4.152
Slack : 1.310
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.554
Data Delay : 4.155
Slack : 1.315
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.566
Data Delay : 4.172
Slack : 1.315
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.552
Data Delay : 4.158
Slack : 1.318
From Node : ula:ula_|video:video_|vram_address[9]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.554
Data Delay : 4.163
Slack : 1.318
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.568
Data Delay : 4.177
Slack : 1.319
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.555
Data Delay : 4.165
Slack : 1.319
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.553
Data Delay : 4.163
Slack : 1.320
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.551
Data Delay : 4.162
Slack : 1.321
From Node : ula:ula_|video:video_|vram_address[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.563
Data Delay : 4.175
Slack : 1.328
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.561
Data Delay : 4.180
Slack : 1.328
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.568
Data Delay : 4.187
Slack : 1.330
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.563
Data Delay : 4.184
Slack : 1.331
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.563
Data Delay : 4.185
Slack : 1.333
From Node : ula:ula_|video:video_|vram_address[9]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.555
Data Delay : 4.179
Slack : 1.334
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.556
Data Delay : 4.181
Slack : 1.335
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.573
Data Delay : 4.199
Slack : 1.337
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.339
Data Delay : 3.967
Slack : 1.338
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.555
Data Delay : 4.184
Slack : 1.339
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.559
Data Delay : 4.189
Slack : 1.339
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.560
Data Delay : 4.190
Slack : 1.340
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.563
Data Delay : 4.194
Slack : 1.341
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.570
Data Delay : 4.202
Slack : 1.344
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.561
Data Delay : 4.196
Slack : 1.344
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.561
Data Delay : 4.196
Slack : 1.344
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.569
Data Delay : 4.204
Slack : 1.346
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.558
Data Delay : 4.195
Slack : 1.348
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.555
Data Delay : 4.194
Slack : 1.348
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.552
Data Delay : 4.191
Slack : 1.348
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.358
Data Delay : 3.997
Slack : 1.350
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.572
Data Delay : 4.213
Slack : 1.354
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.561
Data Delay : 4.206
Slack : 1.355
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.566
Data Delay : 4.212
Slack : 1.355
From Node : ula:ula_|video:video_|vram_address[8]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.570
Data Delay : 4.216
Slack : 1.356
From Node : ula:ula_|video:video_|vram_address[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.561
Data Delay : 4.208
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : -6.263
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 4.384
Slack : -6.263
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.163
Data Delay : 4.382
Slack : -6.263
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.164
Data Delay : 4.381
Slack : -6.263
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.165
Data Delay : 4.380
Slack : -6.262
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.164
Data Delay : 4.380
Slack : -6.025
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.193
Data Delay : 4.116
Slack : -6.011
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.195
Data Delay : 4.100
Slack : -5.747
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.965
Slack : -5.747
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.965
Slack : -5.747
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.965
Slack : -5.747
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.965
Slack : -5.747
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.965
Slack : -5.747
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.965
Slack : -5.747
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.162
Data Delay : 3.964
Slack : -5.747
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.162
Data Delay : 3.964
Slack : -5.747
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.162
Data Delay : 3.964
Slack : -5.747
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.162
Data Delay : 3.964
Slack : -5.747
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.162
Data Delay : 3.964
Slack : -5.747
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.162
Data Delay : 3.964
Slack : -5.747
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.162
Data Delay : 3.964
Slack : -5.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.964
Slack : -5.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.964
Slack : -5.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.964
Slack : -5.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.964
Slack : -5.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.964
Slack : -5.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.964
Slack : -5.746
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.964
Slack : -5.746
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.964
Slack : -5.746
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.964
Slack : -5.746
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.964
Slack : -5.746
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.163
Data Delay : 3.962
Slack : -5.746
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.163
Data Delay : 3.962
Slack : -5.746
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.964
Slack : -5.746
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.964
Slack : -5.746
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.964
Slack : -5.746
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.964
Slack : -5.746
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.964
Slack : -5.746
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.964
Slack : -5.746
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.964
Slack : -5.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.964
Slack : -5.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.964
Slack : -5.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.964
Slack : -5.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.964
Slack : -5.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.964
Slack : -5.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.964
Slack : -5.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.964
Slack : -5.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.964
Slack : -5.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.964
Slack : -5.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.964
Slack : -5.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.964
Slack : -5.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.964
Slack : -5.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.964
Slack : -5.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.964
Slack : -5.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.964
Slack : -5.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.964
Slack : -5.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.161
Data Delay : 3.964
Slack : -5.396
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.191
Data Delay : 3.963
Slack : -5.396
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.191
Data Delay : 3.963
Slack : -5.396
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.191
Data Delay : 3.963
Slack : -5.396
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.191
Data Delay : 3.963
Slack : -5.396
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.191
Data Delay : 3.963
Slack : -5.396
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.191
Data Delay : 3.963
Slack : -5.394
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.190
Data Delay : 3.963
Slack : -5.394
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.190
Data Delay : 3.963
Slack : -5.394
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.190
Data Delay : 3.963
Slack : -5.394
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.190
Data Delay : 3.963
Slack : -5.394
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.190
Data Delay : 3.963
Slack : -5.391
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.194
Data Delay : 3.964
Slack : -5.391
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.194
Data Delay : 3.964
Slack : -5.390
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.193
Data Delay : 3.962
Slack : -5.389
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.197
Data Delay : 3.965
Slack : -5.370
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.216
Data Delay : 3.965
Slack : -5.370
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.216
Data Delay : 3.965
Slack : -5.370
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.216
Data Delay : 3.965
Slack : -5.370
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.216
Data Delay : 3.965
Slack : -5.370
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.215
Data Delay : 3.964
Slack : -5.361
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.225
Data Delay : 3.965
Slack : -5.361
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.225
Data Delay : 3.965
Slack : -5.361
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.225
Data Delay : 3.965
Slack : -5.361
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.225
Data Delay : 3.965
Slack : -5.361
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.225
Data Delay : 3.965
Slack : -5.361
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.225
Data Delay : 3.965
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : 3.657
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.646
Data Delay : 3.544
Slack : 3.657
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.646
Data Delay : 3.544
Slack : 3.657
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.646
Data Delay : 3.544
Slack : 3.657
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.646
Data Delay : 3.544
Slack : 3.657
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.646
Data Delay : 3.544
Slack : 3.657
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.646
Data Delay : 3.544
Slack : 3.667
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.636
Data Delay : 3.544
Slack : 3.667
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.636
Data Delay : 3.544
Slack : 3.667
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.636
Data Delay : 3.544
Slack : 3.667
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.635
Data Delay : 3.543
Slack : 3.668
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.636
Data Delay : 3.545
Slack : 3.687
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.616
Data Delay : 3.544
Slack : 3.688
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.613
Data Delay : 3.542
Slack : 3.689
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.610
Data Delay : 3.543
Slack : 3.689
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.610
Data Delay : 3.543
Slack : 3.689
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.610
Data Delay : 3.543
Slack : 3.689
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.610
Data Delay : 3.543
Slack : 3.689
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.610
Data Delay : 3.543
Slack : 3.689
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.610
Data Delay : 3.543
Slack : 3.691
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.613
Data Delay : 3.545
Slack : 3.691
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.613
Data Delay : 3.545
Slack : 3.694
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.609
Data Delay : 3.544
Slack : 3.694
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.609
Data Delay : 3.544
Slack : 3.694
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.609
Data Delay : 3.544
Slack : 3.694
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.609
Data Delay : 3.544
Slack : 3.694
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.609
Data Delay : 3.544
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.244
Data Delay : 3.544
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.244
Data Delay : 3.544
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.244
Data Delay : 3.544
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.244
Data Delay : 3.544
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.244
Data Delay : 3.544
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.244
Data Delay : 3.544
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.543
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.543
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.543
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.543
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.543
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.543
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.543
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.543
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.543
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.543
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.543
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.543
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.543
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.543
Slack : 4.059
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.543
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.544
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.544
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.544
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.544
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.544
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.544
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.544
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.544
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.544
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.241
Data Delay : 3.542
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.241
Data Delay : 3.542
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.544
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.544
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.544
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.544
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.544
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.544
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.544
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.544
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.544
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.544
Slack : 4.060
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.544
Slack : 4.061
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.545
Slack : 4.061
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.545
Slack : 4.061
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.545
Slack : 4.061
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.545
Slack : 4.061
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.545
Slack : 4.061
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.243
Data Delay : 3.545
Slack : 4.280
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.190
Data Delay : 3.655
Slack : 4.294
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.192
Data Delay : 3.671
Slack : 4.505
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.223
Data Delay : 3.909
Slack : 4.505
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.222
Data Delay : 3.908
Slack : 4.505
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.221
Data Delay : 3.907
Slack : 4.506
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.225
Data Delay : 3.912
Slack : 4.506
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.222
Data Delay : 3.909
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : 9.488
Actual Width : 9.718
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_address_reg0
Slack : 9.488
Actual Width : 9.718
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0
Slack : 9.488
Actual Width : 9.718
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_we_reg
Slack : 9.488
Actual Width : 9.718
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_address_reg0
Slack : 9.488
Actual Width : 9.718
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0
Slack : 9.488
Actual Width : 9.718
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_we_reg
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_we_reg
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_we_reg
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~PORTBDATAOUT0
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9
Slack : 9.500
Actual Width : 9.730
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~PORTBDATAOUT0
Slack : 9.500
Actual Width : 9.730
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
Slack : 9.500
Actual Width : 9.730
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~PORTBDATAOUT0
Slack : 9.500
Actual Width : 9.730
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5
Slack : 9.500
Actual Width : 9.730
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~PORTBDATAOUT0
Slack : 9.500
Actual Width : 9.730
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~PORTBDATAOUT0
Slack : 9.501
Actual Width : 9.731
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
Slack : 9.501
Actual Width : 9.731
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Slack : 9.501
Actual Width : 9.731
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
Slack : 9.501
Actual Width : 9.731
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Slack : 9.501
Actual Width : 9.731
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~PORTBDATAOUT0
Slack : 9.502
Actual Width : 9.732
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Slack : 9.502
Actual Width : 9.732
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Slack : 9.502
Actual Width : 9.732
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Slack : 9.502
Actual Width : 9.732
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Slack : 9.502
Actual Width : 9.732
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Slack : 9.502
Actual Width : 9.732
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~PORTBDATAOUT0
Slack : 9.502
Actual Width : 9.732
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Slack : 9.502
Actual Width : 9.732
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~PORTBDATAOUT0
Slack : 9.502
Actual Width : 9.732
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Slack : 9.502
Actual Width : 9.732
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Slack : 9.502
Actual Width : 9.732
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Slack : 9.502
Actual Width : 9.732
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Slack : 9.503
Actual Width : 9.733
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Slack : 9.503
Actual Width : 9.733
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Slack : 9.504
Actual Width : 9.734
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_datain_reg0
Slack : 9.504
Actual Width : 9.734
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Slack : 9.504
Actual Width : 9.734
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Slack : 9.504
Actual Width : 9.734
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_datain_reg0
Slack : 9.505
Actual Width : 9.735
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_datain_reg0
Slack : 9.505
Actual Width : 9.735
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_datain_reg0
Slack : 9.505
Actual Width : 9.735
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_datain_reg0
Slack : 9.505
Actual Width : 9.735
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_datain_reg0
Slack : 9.505
Actual Width : 9.735
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_datain_reg0
Slack : 9.505
Actual Width : 9.735
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_datain_reg0
Slack : 9.505
Actual Width : 9.735
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_datain_reg0
Slack : 9.505
Actual Width : 9.735
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_datain_reg0
Slack : 9.505
Actual Width : 9.735
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_datain_reg0
Slack : 9.505
Actual Width : 9.735
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_datain_reg0
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_we_reg
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0
Slack : 19.602
Actual Width : 19.832
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_we_reg
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : 20.597
Actual Width : 20.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Slack : 20.597
Actual Width : 20.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Slack : 20.597
Actual Width : 20.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Slack : 20.597
Actual Width : 20.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Slack : 20.597
Actual Width : 20.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Slack : 20.597
Actual Width : 20.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Slack : 20.597
Actual Width : 20.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Slack : 20.597
Actual Width : 20.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Slack : 20.597
Actual Width : 20.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Slack : 20.597
Actual Width : 20.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Slack : 20.597
Actual Width : 20.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Slack : 20.597
Actual Width : 20.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Slack : 20.597
Actual Width : 20.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Slack : 20.597
Actual Width : 20.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Slack : 20.597
Actual Width : 20.813
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Data
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Start
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Slack : 20.604
Actual Width : 20.820
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Slack : 20.609
Actual Width : 20.825
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Slack : 20.609
Actual Width : 20.825
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Slack : 20.609
Actual Width : 20.825
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Slack : 20.609
Actual Width : 20.825
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Slack : 20.610
Actual Width : 20.826
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Slack : 20.611
Actual Width : 20.827
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Slack : 20.611
Actual Width : 20.827
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Slack : 20.611
Actual Width : 20.827
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Slack : 20.611
Actual Width : 20.827
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Slack : 20.611
Actual Width : 20.827
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Slack : 20.611
Actual Width : 20.827
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Slack : 20.613
Actual Width : 20.829
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Slack : 20.613
Actual Width : 20.829
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Slack : 20.613
Actual Width : 20.829
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Slack : 20.647
Actual Width : 20.863
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Slack : 20.647
Actual Width : 20.863
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Slack : 20.647
Actual Width : 20.863
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Slack : 20.647
Actual Width : 20.863
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Slack : 20.647
Actual Width : 20.863
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Slack : 20.647
Actual Width : 20.863
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Slack : 20.651
Actual Width : 20.835
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Slack : 20.651
Actual Width : 20.835
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Slack : 20.651
Actual Width : 20.835
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Slack : 20.651
Actual Width : 20.835
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Slack : 20.651
Actual Width : 20.835
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Slack : 20.651
Actual Width : 20.835
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Slack : 20.687
Actual Width : 20.871
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Slack : 20.687
Actual Width : 20.871
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Slack : 20.688
Actual Width : 20.872
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Slack : 20.690
Actual Width : 20.874
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Slack : 20.690
Actual Width : 20.874
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Slack : 20.690
Actual Width : 20.874
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Slack : 20.690
Actual Width : 20.874
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Slack : 20.690
Actual Width : 20.874
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Slack : 20.690
Actual Width : 20.874
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Slack : 20.691
Actual Width : 20.846
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|scl_out
Slack : 20.691
Actual Width : 20.846
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|sda_out
Slack : 20.691
Actual Width : 20.875
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Slack : 20.691
Actual Width : 20.875
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Slack : 20.691
Actual Width : 20.875
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Slack : 20.691
Actual Width : 20.875
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Slack : 20.691
Actual Width : 20.875
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Slack : 20.692
Actual Width : 20.847
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r
Slack : 20.692
Actual Width : 20.847
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1
Slack : 20.692
Actual Width : 20.847
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ;
+--------------------------------------------------------------------------------+
Slack : 35.503
Actual Width : 35.719
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|clk_cpu
Slack : 35.503
Actual Width : 35.719
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|counter[0]
Slack : 35.584
Actual Width : 35.768
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|clk_cpu
Slack : 35.584
Actual Width : 35.768
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|counter[0]
Slack : 35.726
Actual Width : 35.726
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|inclk[0]
Slack : 35.726
Actual Width : 35.726
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|outclk
Slack : 35.743
Actual Width : 35.743
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|clk_cpu|clk
Slack : 35.743
Actual Width : 35.743
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|counter[0]|clk
Slack : 35.746
Actual Width : 35.746
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|clk_cpu|clk
Slack : 35.746
Actual Width : 35.746
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|counter[0]|clk
Slack : 35.762
Actual Width : 35.762
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|inclk[0]
Slack : 35.762
Actual Width : 35.762
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|outclk
Slack : 69.489
Actual Width : 71.489
Required Width : 2.000
Type : Min Period
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|clk_cpu
Slack : 69.489
Actual Width : 71.489
Required Width : 2.000
Type : Min Period
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|counter[0]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Setup Times ;
+--------------------------------------------------------------------------------+
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : 1.693
Fall : 2.046
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : 3.641
Fall : 3.954
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : SW[*]
Clock Port : CLOCK_50
Rise : 1.010
Fall : 1.278
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : SW[2]
Clock Port : CLOCK_50
Rise : 1.010
Fall : 1.278
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : AUD_ADCDAT
Clock Port : CLOCK_50
Rise : 1.624
Fall : 1.864
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 2.876
Fall : 3.109
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Hold Times ;
+--------------------------------------------------------------------------------+
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : -1.306
Fall : -1.657
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : -2.643
Fall : -2.954
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : SW[*]
Clock Port : CLOCK_50
Rise : -0.395
Fall : -0.661
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : SW[2]
Clock Port : CLOCK_50
Rise : -0.395
Fall : -0.661
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : AUD_ADCDAT
Clock Port : CLOCK_50
Rise : -1.019
Fall : -1.250
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : -1.337
Fall : -1.575
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 9.798
Fall : 9.748
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 9.705
Fall : 9.748
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 9.555
Fall : 9.493
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 9.798
Fall : 9.738
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 9.757
Fall : 9.715
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 9.549
Fall : 9.489
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 9.522
Fall : 9.546
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 9.748
Fall : 9.728
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 9.098
Fall : 9.177
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 7.976
Fall : 8.000
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 7.875
Fall : 7.912
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 7.501
Fall : 7.536
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 7.551
Fall : 7.531
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 7.805
Fall : 7.843
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 7.428
Fall : 7.368
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 7.976
Fall : 8.000
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 7.923
Fall : 7.903
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 7.748
Fall : 7.835
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[*]
Clock Port : CLOCK_50
Rise : 8.499
Fall : 8.077
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[0]
Clock Port : CLOCK_50
Rise : 8.499
Fall : 8.077
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[1]
Clock Port : CLOCK_50
Rise : 6.645
Fall : 6.554
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[2]
Clock Port : CLOCK_50
Rise : 6.682
Fall : 6.538
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[3]
Clock Port : CLOCK_50
Rise : 6.778
Fall : 6.679
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[*]
Clock Port : CLOCK_50
Rise : 6.936
Fall : 6.847
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[0]
Clock Port : CLOCK_50
Rise : 6.658
Fall : 6.538
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[1]
Clock Port : CLOCK_50
Rise : 6.936
Fall : 6.847
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[2]
Clock Port : CLOCK_50
Rise : 6.905
Fall : 6.787
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[3]
Clock Port : CLOCK_50
Rise : 6.881
Fall : 6.765
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_HS
Clock Port : CLOCK_50
Rise : 2.863
Fall : 2.776
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[*]
Clock Port : CLOCK_50
Rise : 7.442
Fall : 7.459
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[0]
Clock Port : CLOCK_50
Rise : 7.239
Fall : 7.169
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[1]
Clock Port : CLOCK_50
Rise : 7.442
Fall : 7.459
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[2]
Clock Port : CLOCK_50
Rise : 6.381
Fall : 6.270
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[3]
Clock Port : CLOCK_50
Rise : 6.900
Fall : 6.786
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_VS
Clock Port : CLOCK_50
Rise : 2.861
Fall : 2.774
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCLRCK
Clock Port : CLOCK_50
Rise : 2.859
Fall : 2.772
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_BCLK
Clock Port : CLOCK_50
Rise : 2.858
Fall : 2.771
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACDAT
Clock Port : CLOCK_50
Rise : 2.862
Fall : 2.775
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACLRCK
Clock Port : CLOCK_50
Rise : 4.881
Fall : 4.517
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_XCK
Clock Port : CLOCK_50
Rise : 2.860
Fall : 2.773
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SCLK
Clock Port : CLOCK_50
Rise : 2.951
Fall : 2.866
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 2.953
Fall : 2.868
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 8.372
Fall : 8.404
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 8.723
Fall : 8.730
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 8.620
Fall : 8.564
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 8.672
Fall : 8.618
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 8.614
Fall : 8.575
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 8.452
Fall : 8.404
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 8.677
Fall : 8.704
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 9.019
Fall : 9.006
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 8.372
Fall : 8.423
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 5.700
Fall : 5.689
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 6.735
Fall : 6.742
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 6.344
Fall : 6.354
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 6.577
Fall : 6.551
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 5.700
Fall : 5.689
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 6.064
Fall : 6.051
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 6.607
Fall : 6.635
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 6.771
Fall : 6.823
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 6.392
Fall : 6.494
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[*]
Clock Port : CLOCK_50
Rise : 3.816
Fall : 3.714
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[0]
Clock Port : CLOCK_50
Rise : 5.891
Fall : 5.507
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[1]
Clock Port : CLOCK_50
Rise : 3.816
Fall : 3.714
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[2]
Clock Port : CLOCK_50
Rise : 4.066
Fall : 3.959
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[3]
Clock Port : CLOCK_50
Rise : 4.158
Fall : 4.095
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[*]
Clock Port : CLOCK_50
Rise : 3.866
Fall : 3.768
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[0]
Clock Port : CLOCK_50
Rise : 3.879
Fall : 3.779
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[1]
Clock Port : CLOCK_50
Rise : 3.866
Fall : 3.768
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[2]
Clock Port : CLOCK_50
Rise : 4.116
Fall : 4.018
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[3]
Clock Port : CLOCK_50
Rise : 4.093
Fall : 3.996
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_HS
Clock Port : CLOCK_50
Rise : 2.461
Fall : 2.374
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[*]
Clock Port : CLOCK_50
Rise : 3.614
Fall : 3.521
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[0]
Clock Port : CLOCK_50
Rise : 4.437
Fall : 4.384
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[1]
Clock Port : CLOCK_50
Rise : 4.239
Fall : 4.194
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[2]
Clock Port : CLOCK_50
Rise : 3.614
Fall : 3.521
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[3]
Clock Port : CLOCK_50
Rise : 4.112
Fall : 4.016
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_VS
Clock Port : CLOCK_50
Rise : 2.460
Fall : 2.373
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCLRCK
Clock Port : CLOCK_50
Rise : 2.457
Fall : 2.370
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_BCLK
Clock Port : CLOCK_50
Rise : 2.456
Fall : 2.369
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACDAT
Clock Port : CLOCK_50
Rise : 2.460
Fall : 2.373
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACLRCK
Clock Port : CLOCK_50
Rise : 4.479
Fall : 4.115
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_XCK
Clock Port : CLOCK_50
Rise : 2.458
Fall : 2.371
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SCLK
Clock Port : CLOCK_50
Rise : 2.549
Fall : 2.464
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 2.551
Fall : 2.466
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Propagation Delay ;
+--------------------------------------------------------------------------------+
Input Port : SW[1]
Output Port : LED[0]
RR : 4.640
RF :
FR :
FF : 4.702
Input Port : SW[2]
Output Port : LED[2]
RR : 4.044
RF :
FR :
FF : 4.195
Input Port : raw_loader_in
Output Port : GPIO_1[22]
RR : 6.764
RF :
FR :
FF : 7.009
Input Port : raw_loader_in
Output Port : LED[3]
RR : 4.399
RF :
FR :
FF : 4.625
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Propagation Delay ;
+--------------------------------------------------------------------------------+
Input Port : SW[1]
Output Port : LED[0]
RR : 4.502
RF :
FR :
FF : 4.568
Input Port : SW[2]
Output Port : LED[2]
RR : 3.930
RF :
FR :
FF : 4.081
Input Port : raw_loader_in
Output Port : GPIO_1[22]
RR : 6.534
RF :
FR :
FF : 6.775
Input Port : raw_loader_in
Output Port : LED[3]
RR : 4.263
RF :
FR :
FF : 4.487
+--------------------------------------------------------------------------------+
----------------------------------------------
; Slow 1200mV 85C Model Metastability Report ;
----------------------------------------------
No synchronizer chains to report.
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary ;
+--------------------------------------------------------------------------------+
Fmax : 53.08 MHz
Restricted Fmax : 53.08 MHz
Clock Name : CLOCK_50
Note :
Fmax : 143.6 MHz
Restricted Fmax : 143.6 MHz
Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Note :
Fmax : 190.48 MHz
Restricted Fmax : 190.48 MHz
Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Note :
Fmax : 1054.85 MHz
Restricted Fmax : 500.0 MHz
Clock Name : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Note : limit due to minimum period restriction (tmin)
+--------------------------------------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup Summary ;
+--------------------------------------------------------------------------------+
Clock : CLOCK_50
Slack : -17.572
End Point TNS : -524.603
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Slack : -6.192
End Point TNS : -241.805
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : -4.414
End Point TNS : -39.436
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Slack : -2.786
End Point TNS : -2.786
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold Summary ;
+--------------------------------------------------------------------------------+
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : 0.297
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Slack : 0.298
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Slack : 0.311
End Point TNS : 0.000
Clock : CLOCK_50
Slack : 0.467
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery Summary ;
+--------------------------------------------------------------------------------+
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : -5.773
End Point TNS : -427.930
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal Summary ;
+--------------------------------------------------------------------------------+
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : 3.347
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
+--------------------------------------------------------------------------------+
Clock : CLOCK_50
Slack : 9.489
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Slack : 19.601
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : 20.590
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Slack : 35.491
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : -17.572
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.279
Data Delay : 7.367
Slack : -17.513
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.279
Data Delay : 7.308
Slack : -17.443
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.279
Data Delay : 7.238
Slack : -17.346
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.279
Data Delay : 7.141
Slack : -17.323
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.277
Data Delay : 7.120
Slack : -17.318
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.277
Data Delay : 7.115
Slack : -17.290
From Node : ula:ula_|video:video_|vga_hc[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.279
Data Delay : 7.085
Slack : -17.219
From Node : ula:ula_|video:video_|vga_hc[1]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.279
Data Delay : 7.014
Slack : -17.194
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.279
Data Delay : 6.989
Slack : -17.188
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.279
Data Delay : 6.983
Slack : -17.164
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.277
Data Delay : 6.961
Slack : -17.151
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.257
Data Delay : 6.968
Slack : -17.144
From Node : ula:ula_|video:video_|vga_hc[9]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.279
Data Delay : 6.939
Slack : -17.121
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.257
Data Delay : 6.938
Slack : -17.094
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.277
Data Delay : 6.891
Slack : -17.077
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.635
Slack : -17.068
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.527
Data Delay : 6.615
Slack : -17.059
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.257
Data Delay : 6.876
Slack : -17.058
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.279
Data Delay : 6.853
Slack : -17.038
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.279
Data Delay : 6.833
Slack : -17.032
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.279
Data Delay : 6.827
Slack : -17.031
From Node : ula:ula_|video:video_|bits[5]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.276
Data Delay : 6.829
Slack : -17.025
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.279
Data Delay : 6.820
Slack : -17.016
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.277
Data Delay : 6.813
Slack : -16.986
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.513
Data Delay : 6.547
Slack : -16.986
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.264
Data Delay : 6.796
Slack : -16.978
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.264
Data Delay : 6.788
Slack : -16.939
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.264
Data Delay : 6.749
Slack : -16.938
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.526
Data Delay : 6.486
Slack : -16.917
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.264
Data Delay : 6.727
Slack : -16.907
From Node : ula:ula_|video:video_|bits[6]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.276
Data Delay : 6.705
Slack : -16.884
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.514
Data Delay : 6.444
Slack : -16.883
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.441
Slack : -16.837
From Node : ula:ula_|video:video_|bits[1]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.276
Data Delay : 6.635
Slack : -16.830
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.388
Slack : -16.809
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.523
Data Delay : 6.360
Slack : -16.791
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.257
Data Delay : 6.608
Slack : -16.787
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.510
Data Delay : 6.351
Slack : -16.775
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.515
Data Delay : 6.334
Slack : -16.772
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.330
Slack : -16.771
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.257
Data Delay : 6.588
Slack : -16.767
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.508
Data Delay : 6.333
Slack : -16.765
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.257
Data Delay : 6.582
Slack : -16.748
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.306
Slack : -16.748
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.504
Data Delay : 6.318
Slack : -16.744
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : VGA_R[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.279
Data Delay : 6.539
Slack : -16.743
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.257
Data Delay : 6.560
Slack : -16.740
From Node : ula:ula_|video:video_|bits[2]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.276
Data Delay : 6.538
Slack : -16.721
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.514
Data Delay : 6.281
Slack : -16.720
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.508
Data Delay : 6.286
Slack : -16.717
From Node : ula:ula_|video:video_|bits[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.276
Data Delay : 6.515
Slack : -16.715
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.264
Data Delay : 6.525
Slack : -16.705
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.255
Slack : -16.699
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.264
Data Delay : 6.509
Slack : -16.694
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.257
Data Delay : 6.511
Slack : -16.666
From Node : ula:ula_|video:video_|vga_hc[3]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.279
Data Delay : 6.461
Slack : -16.665
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.523
Data Delay : 6.216
Slack : -16.664
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.515
Data Delay : 6.223
Slack : -16.661
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.515
Data Delay : 6.220
Slack : -16.659
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.512
Data Delay : 6.221
Slack : -16.648
From Node : ula:ula_|video:video_|frame[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.276
Data Delay : 6.446
Slack : -16.644
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.534
Data Delay : 6.184
Slack : -16.640
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.190
Slack : -16.637
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.522
Data Delay : 6.189
Slack : -16.636
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.186
Slack : -16.626
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.184
Slack : -16.615
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : VGA_R[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.279
Data Delay : 6.410
Slack : -16.604
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.513
Data Delay : 6.165
Slack : -16.601
From Node : ula:ula_|video:video_|bits[3]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.276
Data Delay : 6.399
Slack : -16.599
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.523
Data Delay : 6.150
Slack : -16.590
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.140
Slack : -16.588
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.510
Data Delay : 6.152
Slack : -16.584
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.520
Data Delay : 6.138
Slack : -16.582
From Node : ula:ula_|video:video_|attr[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.276
Data Delay : 6.380
Slack : -16.563
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 6.113
Slack : -16.543
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : VGA_R[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.279
Data Delay : 6.338
Slack : -16.533
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 6.091
Slack : -16.527
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.518
Data Delay : 6.083
Slack : -16.522
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : VGA_R[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.277
Data Delay : 6.319
Slack : -16.517
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : VGA_R[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.277
Data Delay : 6.314
Slack : -16.498
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.522
Data Delay : 6.050
Slack : -16.497
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.531
Data Delay : 6.040
Slack : -16.495
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : VGA_R[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.279
Data Delay : 6.290
Slack : -16.462
From Node : ula:ula_|video:video_|vga_hc[7]
To Node : VGA_R[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.279
Data Delay : 6.257
Slack : -16.446
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.521
Data Delay : 5.999
Slack : -16.443
From Node : ula:ula_|video:video_|bits[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.276
Data Delay : 6.241
Slack : -16.432
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 5.982
Slack : -16.421
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.522
Data Delay : 5.973
Slack : -16.413
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 5.963
Slack : -16.401
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.524
Data Delay : 5.951
Slack : -16.389
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.264
Data Delay : 6.199
Slack : -16.371
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.523
Data Delay : 5.922
Slack : -16.368
From Node : ula:ula_|video:video_|vga_hc[1]
To Node : VGA_R[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.279
Data Delay : 6.163
Slack : -16.366
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : VGA_R[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.279
Data Delay : 6.161
Slack : -16.342
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 5.900
Slack : -16.330
From Node : ula:ula_|video:video_|vga_hc[9]
To Node : VGA_R[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.279
Data Delay : 6.125
Slack : -16.316
From Node : ula:ula_|video:video_|bits[0]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.276
Data Delay : 6.114
Slack : -16.311
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.535
Data Delay : 5.850
Slack : -16.310
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 5.868
Slack : -16.309
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.516
Data Delay : 5.867
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : -6.192
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.735
Data Delay : 4.557
Slack : -6.015
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.972
Data Delay : 4.143
Slack : -5.957
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.972
Data Delay : 4.085
Slack : -5.943
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.955
Data Delay : 4.088
Slack : -5.937
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.958
Data Delay : 4.079
Slack : -5.935
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.972
Data Delay : 4.063
Slack : -5.922
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.955
Data Delay : 4.067
Slack : -5.900
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.975
Data Delay : 4.025
Slack : -5.889
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.972
Data Delay : 4.017
Slack : -5.875
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.979
Data Delay : 3.996
Slack : -5.849
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.735
Data Delay : 4.214
Slack : -5.842
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.979
Data Delay : 3.963
Slack : -5.841
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.736
Data Delay : 4.205
Slack : -5.838
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.969
Data Delay : 3.969
Slack : -5.822
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.735
Data Delay : 4.187
Slack : -5.821
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.973
Data Delay : 3.948
Slack : -5.816
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.967
Data Delay : 3.949
Slack : -5.816
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.965
Data Delay : 3.951
Slack : -5.804
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.973
Data Delay : 3.931
Slack : -5.798
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.976
Data Delay : 3.922
Slack : -5.796
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.739
Data Delay : 4.157
Slack : -5.795
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.963
Data Delay : 3.932
Slack : -5.790
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.984
Data Delay : 3.906
Slack : -5.783
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.973
Data Delay : 3.910
Slack : -5.769
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.974
Data Delay : 3.895
Slack : -5.765
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.988
Data Delay : 3.877
Slack : -5.758
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.965
Data Delay : 3.893
Slack : -5.748
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.970
Data Delay : 3.878
Slack : -5.741
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.968
Data Delay : 3.873
Slack : -5.738
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.964
Data Delay : 3.874
Slack : -5.736
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.965
Data Delay : 3.871
Slack : -5.728
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.978
Data Delay : 3.850
Slack : -5.727
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.976
Data Delay : 3.851
Slack : -5.724
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.973
Data Delay : 3.851
Slack : -5.717
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.960
Data Delay : 3.857
Slack : -5.704
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.972
Data Delay : 3.832
Slack : -5.694
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.976
Data Delay : 3.818
Slack : -5.694
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.972
Data Delay : 3.822
Slack : -5.671
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.977
Data Delay : 3.794
Slack : -5.655
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.755
Data Delay : 4.000
Slack : -5.650
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.973
Data Delay : 3.777
Slack : -5.603
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.955
Data Delay : 3.748
Slack : -5.587
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.966
Data Delay : 3.721
Slack : -5.582
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.750
Data Delay : 3.932
Slack : -5.580
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.743
Data Delay : 3.937
Slack : -5.578
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.978
Data Delay : 3.700
Slack : -5.572
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.960
Data Delay : 3.712
Slack : -5.557
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.735
Data Delay : 3.922
Slack : -5.556
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.963
Data Delay : 3.693
Slack : -5.556
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.970
Data Delay : 3.686
Slack : -5.553
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.967
Data Delay : 3.686
Slack : -5.553
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.746
Data Delay : 3.907
Slack : -5.543
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.736
Data Delay : 3.907
Slack : -5.540
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.973
Data Delay : 3.667
Slack : -5.540
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.982
Data Delay : 3.658
Slack : -5.533
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.964
Data Delay : 3.669
Slack : -5.533
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.966
Data Delay : 3.667
Slack : -5.522
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.743
Data Delay : 3.879
Slack : -5.500
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.743
Data Delay : 3.857
Slack : -5.495
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.965
Data Delay : 3.630
Slack : -5.487
From Node : raw_loader_in
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.174
Data Delay : 3.761
Slack : -5.478
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.960
Data Delay : 3.618
Slack : -5.478
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.973
Data Delay : 3.605
Slack : -5.470
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.974
Data Delay : 3.596
Slack : -5.467
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.977
Data Delay : 3.590
Slack : -5.446
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.743
Data Delay : 3.803
Slack : -5.438
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.738
Data Delay : 3.800
Slack : -5.432
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.741
Data Delay : 3.791
Slack : -5.428
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.976
Data Delay : 3.552
Slack : -5.425
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.977
Data Delay : 3.548
Slack : -5.421
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.747
Data Delay : 3.774
Slack : -5.417
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.738
Data Delay : 3.779
Slack : -5.414
From Node : raw_loader_in
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.179
Data Delay : 3.693
Slack : -5.395
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.964
Data Delay : 3.531
Slack : -5.387
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.965
Data Delay : 3.522
Slack : -5.384
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.737
Data Delay : 3.747
Slack : -5.384
From Node : raw_loader_in
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.183
Data Delay : 3.667
Slack : -5.353
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.749
Data Delay : 3.704
Slack : -5.342
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.968
Data Delay : 3.474
Slack : -5.307
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.960
Data Delay : 3.447
Slack : -5.296
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.971
Data Delay : 3.425
Slack : -5.294
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.737
Data Delay : 3.657
Slack : -5.293
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.961
Data Delay : 3.432
Slack : -5.290
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.963
Data Delay : 3.427
Slack : -5.259
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.743
Data Delay : 3.616
Slack : -5.213
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.960
Data Delay : 3.353
Slack : -5.212
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.743
Data Delay : 3.569
Slack : -5.199
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.961
Data Delay : 3.338
Slack : -5.196
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.741
Data Delay : 3.555
Slack : -5.185
From Node : raw_loader_in
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : 0.180
Data Delay : 3.465
Slack : -5.110
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.735
Data Delay : 3.475
Slack : -5.091
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.749
Data Delay : 3.442
Slack : -5.088
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.746
Data Delay : 3.442
Slack : -5.068
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.745
Data Delay : 3.423
Slack : -5.063
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.743
Data Delay : 3.420
Slack : -5.044
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.962
Data Delay : 3.182
Slack : -5.040
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.744
Data Delay : 3.396
Slack : -4.950
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.962
Data Delay : 3.088
Slack : -4.831
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.750
Data Delay : 3.181
Slack : -4.797
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.743
Data Delay : 3.154
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : -4.414
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.115
Data Delay : 2.588
Slack : -4.409
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 2.701
Slack : -4.409
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 2.701
Slack : -3.844
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.229
Data Delay : 2.452
Slack : -3.844
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.229
Data Delay : 2.452
Slack : -3.844
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.229
Data Delay : 2.452
Slack : -3.844
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.229
Data Delay : 2.452
Slack : -3.844
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.229
Data Delay : 2.452
Slack : -3.696
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 1.988
Slack : -3.288
From Node : AUD_ADCDAT
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.084
Data Delay : 1.583
Slack : 17.369
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 3.108
Slack : 17.369
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 3.108
Slack : 17.369
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 3.108
Slack : 17.369
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 3.108
Slack : 17.369
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 3.108
Slack : 17.371
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 3.106
Slack : 17.371
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 3.106
Slack : 17.371
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 3.106
Slack : 17.371
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 3.106
Slack : 17.371
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 3.106
Slack : 17.457
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 3.020
Slack : 17.457
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 3.020
Slack : 17.459
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 3.018
Slack : 17.459
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 3.018
Slack : 17.494
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.983
Slack : 17.494
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.983
Slack : 17.494
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.983
Slack : 17.494
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.983
Slack : 17.494
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.983
Slack : 17.547
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.930
Slack : 17.549
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.928
Slack : 17.582
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.895
Slack : 17.582
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.895
Slack : 17.585
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.892
Slack : 17.585
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.892
Slack : 17.585
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.892
Slack : 17.585
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.892
Slack : 17.585
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.892
Slack : 17.586
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 2.890
Slack : 17.586
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 2.890
Slack : 17.588
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 2.888
Slack : 17.588
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 2.888
Slack : 17.672
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.805
Slack : 17.673
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.804
Slack : 17.673
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.804
Slack : 17.711
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 2.765
Slack : 17.711
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 2.765
Slack : 17.713
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.764
Slack : 17.713
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.764
Slack : 17.715
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.762
Slack : 17.715
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.762
Slack : 17.763
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.714
Slack : 17.802
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 2.674
Slack : 17.802
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.370
Data Delay : 2.674
Slack : 17.835
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.053
Data Delay : 2.958
Slack : 17.835
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.053
Data Delay : 2.958
Slack : 17.835
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.053
Data Delay : 2.958
Slack : 17.835
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.053
Data Delay : 2.958
Slack : 17.835
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.053
Data Delay : 2.958
Slack : 17.837
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.053
Data Delay : 2.956
Slack : 17.837
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.053
Data Delay : 2.956
Slack : 17.837
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.053
Data Delay : 2.956
Slack : 17.837
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.053
Data Delay : 2.956
Slack : 17.837
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.053
Data Delay : 2.956
Slack : 17.838
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.639
Slack : 17.838
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.639
Slack : 17.925
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.552
Slack : 17.925
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.552
Slack : 17.925
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.552
Slack : 17.925
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.552
Slack : 17.927
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.550
Slack : 17.927
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.550
Slack : 17.927
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.550
Slack : 17.927
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.550
Slack : 17.929
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.548
Slack : 17.929
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.548
Slack : 17.943
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.049
Data Delay : 2.854
Slack : 17.945
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.049
Data Delay : 2.852
Slack : 17.950
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.527
Slack : 17.950
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.527
Slack : 17.950
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.527
Slack : 17.950
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.527
Slack : 17.950
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.527
Slack : 17.960
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.053
Data Delay : 2.833
Slack : 17.960
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.053
Data Delay : 2.833
Slack : 17.960
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.053
Data Delay : 2.833
Slack : 17.960
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.053
Data Delay : 2.833
Slack : 17.960
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.053
Data Delay : 2.833
Slack : 18.038
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.439
Slack : 18.038
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.439
Slack : 18.038
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.439
Slack : 18.038
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.439
Slack : 18.038
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.439
Slack : 18.038
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.439
Slack : 18.038
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.439
Slack : 18.050
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.427
Slack : 18.050
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.427
Slack : 18.050
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.427
Slack : 18.050
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.369
Data Delay : 2.427
Slack : 18.051
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.053
Data Delay : 2.742
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ;
+--------------------------------------------------------------------------------+
Slack : -2.786
From Node : SW[2]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.423
Clock Skew : 0.254
Data Delay : 1.418
Slack : 70.541
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 71.489
Clock Skew : -0.069
Data Delay : 0.874
Slack : 70.832
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|counter[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 71.489
Clock Skew : -0.069
Data Delay : 0.583
Slack : 70.832
From Node : ula:ula_|clocks:clocks_|clk_cpu
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 71.489
Clock Skew : -0.069
Data Delay : 0.583
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : 0.297
From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.070
Data Delay : 0.511
Slack : 0.298
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.511
Slack : 0.298
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.511
Slack : 0.305
From Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.070
Data Delay : 0.519
Slack : 0.306
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.519
Slack : 0.306
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.519
Slack : 0.311
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.311
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.311
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.311
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.320
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.519
Slack : 0.320
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.519
Slack : 0.320
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.519
Slack : 0.337
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.537
Slack : 0.338
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.538
Slack : 0.339
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.539
Slack : 0.339
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.539
Slack : 0.339
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.539
Slack : 0.339
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.538
Slack : 0.340
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.539
Slack : 0.341
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.541
Slack : 0.342
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.541
Slack : 0.368
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.567
Slack : 0.386
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.585
Slack : 0.386
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.585
Slack : 0.393
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.389
Data Delay : 0.926
Slack : 0.431
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.631
Slack : 0.431
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.631
Slack : 0.432
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.632
Slack : 0.432
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.632
Slack : 0.434
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.388
Data Delay : 0.966
Slack : 0.453
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.388
Data Delay : 0.985
Slack : 0.476
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.675
Slack : 0.486
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.699
Slack : 0.487
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.687
Slack : 0.488
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.701
Slack : 0.490
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.690
Slack : 0.490
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.703
Slack : 0.492
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.705
Slack : 0.495
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.695
Slack : 0.497
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.697
Slack : 0.498
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.711
Slack : 0.499
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.699
Slack : 0.500
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.699
Slack : 0.501
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.700
Slack : 0.502
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.701
Slack : 0.502
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.701
Slack : 0.504
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.717
Slack : 0.509
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.709
Slack : 0.514
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.714
Slack : 0.514
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 0.726
Slack : 0.516
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.715
Slack : 0.518
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 0.730
Slack : 0.518
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.717
Slack : 0.519
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 0.731
Slack : 0.519
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.388
Data Delay : 1.051
Slack : 0.520
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 0.732
Slack : 0.526
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.725
Slack : 0.540
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.068
Data Delay : 0.752
Slack : 0.540
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.739
Slack : 0.546
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.745
Slack : 0.561
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.760
Slack : 0.562
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.761
Slack : 0.575
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.388
Data Delay : 1.107
Slack : 0.606
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.805
Slack : 0.651
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.850
Slack : 0.657
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.856
Slack : 0.662
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.861
Slack : 0.663
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.862
Slack : 0.664
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.863
Slack : 0.664
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.388
Data Delay : 1.196
Slack : 0.665
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : -0.265
Data Delay : 0.544
Slack : 0.666
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.865
Slack : 0.719
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.918
Slack : 0.719
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.384
Data Delay : 1.247
Slack : 0.719
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.384
Data Delay : 1.247
Slack : 0.719
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.384
Data Delay : 1.247
Slack : 0.719
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.384
Data Delay : 1.247
Slack : 0.719
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.384
Data Delay : 1.247
Slack : 0.730
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.943
Slack : 0.733
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.932
Slack : 0.733
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.946
Slack : 0.735
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.934
Slack : 0.736
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.935
Slack : 0.737
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.950
Slack : 0.739
From Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.938
Slack : 0.739
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.952
Slack : 0.739
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.952
Slack : 0.744
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.943
Slack : 0.744
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.957
Slack : 0.745
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.944
Slack : 0.745
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.944
Slack : 0.746
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.959
Slack : 0.746
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.959
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ;
+--------------------------------------------------------------------------------+
Slack : 0.298
From Node : ula:ula_|clocks:clocks_|clk_cpu
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.511
Slack : 0.306
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|counter[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.519
Slack : 0.517
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.000
Clock Skew : 0.069
Data Delay : 0.730
Slack : 1.246
From Node : SW[2]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : -0.017
Clock Skew : 0.626
Data Delay : 1.089
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 0.311
From Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.311
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : ula:ula_|video:video_|vga_vc[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.311
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|vga_vc[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.311
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vga_vc[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.311
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : ula:ula_|video:video_|vga_vc[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.311
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : ula:ula_|video:video_|vga_vc[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vga_vc[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.312
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : ula:ula_|video:video_|vga_vc[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 0.511
Slack : 0.496
From Node : ula:ula_|video:video_|frame[2]
To Node : ula:ula_|video:video_|frame[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.696
Slack : 0.498
From Node : ula:ula_|video:video_|frame[3]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.698
Slack : 0.508
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.708
Slack : 0.741
From Node : ula:ula_|video:video_|frame[2]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.941
Slack : 0.747
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.947
Slack : 0.754
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 0.954
Slack : 0.824
From Node : ula:ula_|video:video_|bits_prefetch[1]
To Node : ula:ula_|video:video_|bits[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.261
Data Delay : 0.707
Slack : 0.837
From Node : ula:ula_|video:video_|bits_prefetch[5]
To Node : ula:ula_|video:video_|bits[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.261
Data Delay : 0.720
Slack : 0.888
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vram_address[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.086
Slack : 0.890
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vram_address[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.088
Slack : 0.891
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vram_address[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.089
Slack : 0.945
From Node : ula:ula_|video:video_|bits_prefetch[4]
To Node : ula:ula_|video:video_|bits[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.261
Data Delay : 0.828
Slack : 0.946
From Node : ula:ula_|video:video_|bits_prefetch[3]
To Node : ula:ula_|video:video_|bits[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.261
Data Delay : 0.829
Slack : 0.950
From Node : ula:ula_|video:video_|vga_hc[1]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.149
Slack : 0.953
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : ula:ula_|video:video_|vram_address[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.151
Slack : 0.961
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.159
Slack : 0.973
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : ula:ula_|video:video_|vram_address[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.171
Slack : 0.974
From Node : ula:ula_|video:video_|bits_prefetch[7]
To Node : ula:ula_|video:video_|bits[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.261
Data Delay : 0.857
Slack : 0.986
From Node : ula:ula_|video:video_|bits_prefetch[2]
To Node : ula:ula_|video:video_|bits[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.261
Data Delay : 0.869
Slack : 1.002
From Node : ula:ula_|video:video_|attr_prefetch[7]
To Node : ula:ula_|video:video_|attr[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.288
Data Delay : 0.858
Slack : 1.004
From Node : ula:ula_|video:video_|attr_prefetch[3]
To Node : ula:ula_|video:video_|attr[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.288
Data Delay : 0.860
Slack : 1.035
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.235
Slack : 1.041
From Node : ula:ula_|video:video_|attr_prefetch[0]
To Node : ula:ula_|video:video_|attr[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.288
Data Delay : 0.897
Slack : 1.060
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[12]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.259
Slack : 1.060
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.259
Slack : 1.123
From Node : ula:ula_|video:video_|bits_prefetch[6]
To Node : ula:ula_|video:video_|bits[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.261
Data Delay : 1.006
Slack : 1.124
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.322
Slack : 1.127
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.326
Slack : 1.127
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.325
Slack : 1.129
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.328
Slack : 1.130
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : ula:ula_|video:video_|vram_address[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.329
Slack : 1.140
From Node : ula:ula_|video:video_|vga_hc[7]
To Node : ula:ula_|video:video_|vram_address[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.338
Slack : 1.141
From Node : ula:ula_|video:video_|vga_hc[7]
To Node : ula:ula_|video:video_|vram_address[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.339
Slack : 1.160
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.359
Slack : 1.176
From Node : ula:ula_|video:video_|attr_prefetch[6]
To Node : ula:ula_|video:video_|attr[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.287
Data Delay : 1.033
Slack : 1.180
From Node : ula:ula_|video:video_|vga_hc[7]
To Node : ula:ula_|video:video_|vga_hc[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.379
Slack : 1.182
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vga_hc[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.381
Slack : 1.188
From Node : ula:ula_|video:video_|attr_prefetch[4]
To Node : ula:ula_|video:video_|attr[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.287
Data Delay : 1.045
Slack : 1.195
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.394
Slack : 1.206
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.404
Slack : 1.228
From Node : ula:ula_|video:video_|attr_prefetch[5]
To Node : ula:ula_|video:video_|attr[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.287
Data Delay : 1.085
Slack : 1.237
From Node : ula:ula_|video:video_|vga_hc[3]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.435
Slack : 1.266
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.466
Slack : 1.280
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.478
Slack : 1.287
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.487
Slack : 1.295
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.493
Slack : 1.307
From Node : ula:ula_|video:video_|frame[3]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.053
Data Delay : 1.504
Slack : 1.309
From Node : ula:ula_|video:video_|frame[4]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.508
Slack : 1.324
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.522
Slack : 1.337
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.261
Data Delay : 1.220
Slack : 1.345
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : ula:ula_|video:video_|vram_address[12]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.545
Slack : 1.345
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : ula:ula_|video:video_|vram_address[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.545
Slack : 1.365
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.563
Slack : 1.390
From Node : ula:ula_|video:video_|frame[2]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.053
Data Delay : 1.587
Slack : 1.403
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.053
Data Delay : 1.600
Slack : 1.422
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vga_hc[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.621
Slack : 1.455
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.654
Slack : 1.462
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.661
Slack : 1.468
From Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
To Node : ula:ula_|video:video_|VGA_VS
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.030
Data Delay : 1.584
Slack : 1.475
From Node : ula:ula_|video:video_|vga_hc[9]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.673
Slack : 1.476
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.675
Slack : 1.495
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.694
Slack : 1.498
From Node : ula:ula_|video:video_|vga_hc[3]
To Node : ula:ula_|video:video_|vga_hc[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.697
Slack : 1.501
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.700
Slack : 1.519
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.718
Slack : 1.543
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.742
Slack : 1.551
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.750
Slack : 1.555
From Node : ula:ula_|video:video_|attr_prefetch[2]
To Node : ula:ula_|video:video_|attr[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.287
Data Delay : 1.412
Slack : 1.568
From Node : ula:ula_|video:video_|vga_hc[3]
To Node : ula:ula_|video:video_|vga_hc[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.767
Slack : 1.568
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.057
Data Delay : 1.769
Slack : 1.572
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.771
Slack : 1.580
From Node : ula:ula_|video:video_|bits_prefetch[0]
To Node : ula:ula_|video:video_|bits[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.261
Data Delay : 1.463
Slack : 1.580
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.779
Slack : 1.593
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.053
Data Delay : 1.790
Slack : 1.608
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.807
Slack : 1.616
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.816
Slack : 1.617
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.817
Slack : 1.618
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.818
Slack : 1.622
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : ula:ula_|video:video_|vga_vc[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.820
Slack : 1.623
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : ula:ula_|video:video_|vga_vc[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 1.821
Slack : 1.630
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : ula:ula_|video:video_|vga_vc[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.830
Slack : 1.639
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.838
Slack : 1.673
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : ula:ula_|video:video_|vga_hc[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.055
Data Delay : 1.872
Slack : 1.680
From Node : ula:ula_|video:video_|attr_prefetch[1]
To Node : ula:ula_|video:video_|attr[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.287
Data Delay : 1.537
Slack : 1.680
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.880
Slack : 1.686
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : ula:ula_|video:video_|vga_vc[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.886
Slack : 1.686
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : ula:ula_|video:video_|vga_vc[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.886
Slack : 1.686
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : ula:ula_|video:video_|vga_vc[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.886
Slack : 1.688
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : ula:ula_|video:video_|vga_vc[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.056
Data Delay : 1.888
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : 0.467
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.054
Data Delay : 0.665
Slack : 0.574
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.325
Data Delay : 3.172
Slack : 0.580
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.312
Data Delay : 3.165
Slack : 1.158
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.244
Data Delay : 3.675
Slack : 1.163
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.256
Data Delay : 3.692
Slack : 1.166
From Node : ula:ula_|video:video_|vram_address[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.256
Data Delay : 3.695
Slack : 1.171
From Node : ula:ula_|video:video_|vram_address[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.253
Data Delay : 3.697
Slack : 1.172
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.247
Data Delay : 3.692
Slack : 1.183
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.252
Data Delay : 3.708
Slack : 1.192
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.250
Data Delay : 3.715
Slack : 1.194
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.239
Data Delay : 3.706
Slack : 1.194
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.078
Data Delay : 3.545
Slack : 1.200
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.065
Data Delay : 3.538
Slack : 1.203
From Node : ula:ula_|video:video_|vram_address[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.250
Data Delay : 3.726
Slack : 1.217
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.255
Data Delay : 3.745
Slack : 1.219
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.247
Data Delay : 3.739
Slack : 1.219
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.240
Data Delay : 3.732
Slack : 1.221
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.250
Data Delay : 3.744
Slack : 1.221
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.244
Data Delay : 3.738
Slack : 1.223
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.249
Data Delay : 3.745
Slack : 1.225
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.250
Data Delay : 3.748
Slack : 1.226
From Node : ula:ula_|video:video_|vram_address[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.247
Data Delay : 3.746
Slack : 1.228
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.239
Data Delay : 3.740
Slack : 1.230
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.235
Data Delay : 3.738
Slack : 1.231
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.331
Data Delay : 3.835
Slack : 1.232
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.236
Data Delay : 3.741
Slack : 1.236
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.246
Data Delay : 3.755
Slack : 1.237
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.256
Data Delay : 3.766
Slack : 1.237
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.318
Data Delay : 3.828
Slack : 1.242
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.248
Data Delay : 3.763
Slack : 1.243
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.244
Data Delay : 3.760
Slack : 1.248
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.256
Data Delay : 3.777
Slack : 1.248
From Node : ula:ula_|video:video_|vram_address[9]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.239
Data Delay : 3.760
Slack : 1.252
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.242
Data Delay : 3.767
Slack : 1.252
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.232
Data Delay : 3.757
Slack : 1.253
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.256
Data Delay : 3.782
Slack : 1.254
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.242
Data Delay : 3.769
Slack : 1.255
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.244
Data Delay : 3.772
Slack : 1.256
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.235
Data Delay : 3.764
Slack : 1.258
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.232
Data Delay : 3.763
Slack : 1.260
From Node : ula:ula_|video:video_|vram_address[9]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.242
Data Delay : 3.775
Slack : 1.264
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.240
Data Delay : 3.777
Slack : 1.265
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.250
Data Delay : 3.788
Slack : 1.267
From Node : ula:ula_|video:video_|vram_address[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.244
Data Delay : 3.784
Slack : 1.269
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.232
Data Delay : 3.774
Slack : 1.271
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.237
Data Delay : 3.781
Slack : 1.273
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.237
Data Delay : 3.783
Slack : 1.276
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.240
Data Delay : 3.789
Slack : 1.277
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.077
Data Delay : 3.627
Slack : 1.278
From Node : ula:ula_|video:video_|vram_address[9]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.244
Data Delay : 3.795
Slack : 1.279
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.248
Data Delay : 3.800
Slack : 1.280
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.247
Data Delay : 3.800
Slack : 1.280
From Node : ula:ula_|video:video_|vram_address[9]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.248
Data Delay : 3.801
Slack : 1.282
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.333
Data Delay : 3.888
Slack : 1.283
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.239
Data Delay : 3.795
Slack : 1.284
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.247
Data Delay : 3.804
Slack : 1.286
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.236
Data Delay : 3.795
Slack : 1.287
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.244
Data Delay : 3.804
Slack : 1.287
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.250
Data Delay : 3.810
Slack : 1.288
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.240
Data Delay : 3.801
Slack : 1.291
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.232
Data Delay : 3.796
Slack : 1.292
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.240
Data Delay : 3.805
Slack : 1.292
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.235
Data Delay : 3.800
Slack : 1.293
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.232
Data Delay : 3.798
Slack : 1.294
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.319
Data Delay : 3.886
Slack : 1.294
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.244
Data Delay : 3.811
Slack : 1.295
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.236
Data Delay : 3.804
Slack : 1.297
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.248
Data Delay : 3.818
Slack : 1.300
From Node : ula:ula_|video:video_|vram_address[8]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.250
Data Delay : 3.823
Slack : 1.301
From Node : ula:ula_|video:video_|vram_address[9]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.232
Data Delay : 3.806
Slack : 1.303
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.248
Data Delay : 3.824
Slack : 1.304
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.313
Data Delay : 3.890
Slack : 1.305
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.247
Data Delay : 3.825
Slack : 1.306
From Node : ula:ula_|video:video_|vram_address[9]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.232
Data Delay : 3.811
Slack : 1.307
From Node : ula:ula_|video:video_|vram_address[9]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.236
Data Delay : 3.816
Slack : 1.307
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.232
Data Delay : 3.812
Slack : 1.308
From Node : ula:ula_|video:video_|vram_address[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.240
Data Delay : 3.821
Slack : 1.309
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.256
Data Delay : 3.838
Slack : 1.310
From Node : ula:ula_|video:video_|vram_address[8]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.247
Data Delay : 3.830
Slack : 1.310
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.253
Data Delay : 3.836
Slack : 1.311
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.247
Data Delay : 3.831
Slack : 1.311
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.232
Data Delay : 3.816
Slack : 1.311
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.240
Data Delay : 3.824
Slack : 1.312
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.244
Data Delay : 3.829
Slack : 1.313
From Node : ula:ula_|video:video_|vram_address[9]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.237
Data Delay : 3.823
Slack : 1.313
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.253
Data Delay : 3.839
Slack : 1.313
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.240
Data Delay : 3.826
Slack : 1.314
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.256
Data Delay : 3.843
Slack : 1.314
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.253
Data Delay : 3.840
Slack : 1.315
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.242
Data Delay : 3.830
Slack : 1.315
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.232
Data Delay : 3.820
Slack : 1.315
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.240
Data Delay : 3.828
Slack : 1.315
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.240
Data Delay : 3.828
Slack : 1.316
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.240
Data Delay : 3.829
Slack : 1.317
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.052
Data Delay : 3.642
Slack : 1.317
From Node : ula:ula_|video:video_|vram_address[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.244
Data Delay : 3.834
Slack : 1.317
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.232
Data Delay : 3.822
Slack : 1.318
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.240
Data Delay : 3.831
Slack : 1.318
From Node : ula:ula_|video:video_|vram_address[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.248
Data Delay : 3.839
Slack : 1.320
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 2.244
Data Delay : 3.837
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : -5.773
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.088
Data Delay : 3.972
Slack : -5.773
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.090
Data Delay : 3.970
Slack : -5.773
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.091
Data Delay : 3.969
Slack : -5.772
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.091
Data Delay : 3.968
Slack : -5.772
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.092
Data Delay : 3.967
Slack : -5.536
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.115
Data Delay : 3.710
Slack : -5.523
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.116
Data Delay : 3.696
Slack : -5.286
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.088
Data Delay : 3.577
Slack : -5.286
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.088
Data Delay : 3.577
Slack : -5.286
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.578
Slack : -5.286
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.578
Slack : -5.286
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.578
Slack : -5.286
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.578
Slack : -5.286
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.085
Data Delay : 3.580
Slack : -5.286
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.085
Data Delay : 3.580
Slack : -5.286
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.085
Data Delay : 3.580
Slack : -5.286
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.085
Data Delay : 3.580
Slack : -5.286
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.085
Data Delay : 3.580
Slack : -5.286
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.085
Data Delay : 3.580
Slack : -5.286
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.085
Data Delay : 3.580
Slack : -5.286
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.085
Data Delay : 3.580
Slack : -5.286
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.085
Data Delay : 3.580
Slack : -5.286
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.085
Data Delay : 3.580
Slack : -5.286
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.085
Data Delay : 3.580
Slack : -5.286
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.085
Data Delay : 3.580
Slack : -5.286
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.085
Data Delay : 3.580
Slack : -5.286
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.085
Data Delay : 3.580
Slack : -5.286
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.085
Data Delay : 3.580
Slack : -5.285
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.084
Data Delay : 3.580
Slack : -5.285
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.084
Data Delay : 3.580
Slack : -5.285
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.084
Data Delay : 3.580
Slack : -5.285
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.084
Data Delay : 3.580
Slack : -5.285
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.084
Data Delay : 3.580
Slack : -5.285
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.084
Data Delay : 3.580
Slack : -5.285
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.084
Data Delay : 3.580
Slack : -5.285
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.084
Data Delay : 3.580
Slack : -5.285
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.084
Data Delay : 3.580
Slack : -5.285
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.084
Data Delay : 3.580
Slack : -5.285
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.084
Data Delay : 3.580
Slack : -5.285
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.084
Data Delay : 3.580
Slack : -5.285
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.577
Slack : -5.285
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.577
Slack : -5.285
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.577
Slack : -5.285
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.577
Slack : -5.285
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.577
Slack : -5.285
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.577
Slack : -5.285
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.577
Slack : -5.285
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.577
Slack : -5.285
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.577
Slack : -5.285
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.577
Slack : -5.285
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.577
Slack : -5.285
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.577
Slack : -5.285
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.577
Slack : -5.285
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.087
Data Delay : 3.577
Slack : -5.285
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.084
Data Delay : 3.580
Slack : -5.285
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.084
Data Delay : 3.580
Slack : -4.988
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.213
Data Delay : 3.577
Slack : -4.988
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.213
Data Delay : 3.577
Slack : -4.988
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.213
Data Delay : 3.577
Slack : -4.988
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.213
Data Delay : 3.577
Slack : -4.988
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.213
Data Delay : 3.577
Slack : -4.988
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.213
Data Delay : 3.577
Slack : -4.969
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.229
Data Delay : 3.577
Slack : -4.969
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.229
Data Delay : 3.577
Slack : -4.969
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.229
Data Delay : 3.577
Slack : -4.969
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.229
Data Delay : 3.577
Slack : -4.969
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.229
Data Delay : 3.577
Slack : -4.967
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.234
Data Delay : 3.580
Slack : -4.966
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.232
Data Delay : 3.577
Slack : -4.966
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.232
Data Delay : 3.577
Slack : -4.965
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.233
Data Delay : 3.577
Slack : -4.949
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.253
Data Delay : 3.581
Slack : -4.949
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.253
Data Delay : 3.581
Slack : -4.949
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.253
Data Delay : 3.581
Slack : -4.949
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.253
Data Delay : 3.581
Slack : -4.949
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.252
Data Delay : 3.580
Slack : -4.940
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.261
Data Delay : 3.580
Slack : -4.940
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.261
Data Delay : 3.580
Slack : -4.940
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.261
Data Delay : 3.580
Slack : -4.940
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.261
Data Delay : 3.580
Slack : -4.940
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.261
Data Delay : 3.580
Slack : -4.940
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : 0.261
Data Delay : 3.580
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : 3.347
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.634
Data Delay : 3.209
Slack : 3.347
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.634
Data Delay : 3.209
Slack : 3.347
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.634
Data Delay : 3.209
Slack : 3.347
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.634
Data Delay : 3.209
Slack : 3.347
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.634
Data Delay : 3.209
Slack : 3.347
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.634
Data Delay : 3.209
Slack : 3.356
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.626
Data Delay : 3.210
Slack : 3.356
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.626
Data Delay : 3.210
Slack : 3.356
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.626
Data Delay : 3.210
Slack : 3.356
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.626
Data Delay : 3.210
Slack : 3.356
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.625
Data Delay : 3.209
Slack : 3.372
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.605
Data Delay : 3.205
Slack : 3.375
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.604
Data Delay : 3.207
Slack : 3.375
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.604
Data Delay : 3.207
Slack : 3.375
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.606
Data Delay : 3.209
Slack : 3.379
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.600
Data Delay : 3.207
Slack : 3.379
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.600
Data Delay : 3.207
Slack : 3.379
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.600
Data Delay : 3.207
Slack : 3.379
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.600
Data Delay : 3.207
Slack : 3.379
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.600
Data Delay : 3.207
Slack : 3.390
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.584
Data Delay : 3.205
Slack : 3.390
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.584
Data Delay : 3.205
Slack : 3.390
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.584
Data Delay : 3.205
Slack : 3.390
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.584
Data Delay : 3.205
Slack : 3.390
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.584
Data Delay : 3.205
Slack : 3.390
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.584
Data Delay : 3.205
Slack : 3.706
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.205
Slack : 3.706
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.205
Slack : 3.707
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.274
Data Delay : 3.209
Slack : 3.707
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.274
Data Delay : 3.209
Slack : 3.707
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.274
Data Delay : 3.209
Slack : 3.707
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.274
Data Delay : 3.209
Slack : 3.707
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.274
Data Delay : 3.209
Slack : 3.707
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.274
Data Delay : 3.209
Slack : 3.707
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.274
Data Delay : 3.209
Slack : 3.707
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.274
Data Delay : 3.209
Slack : 3.707
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.274
Data Delay : 3.209
Slack : 3.707
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.274
Data Delay : 3.209
Slack : 3.707
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.274
Data Delay : 3.209
Slack : 3.707
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.274
Data Delay : 3.209
Slack : 3.707
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.274
Data Delay : 3.209
Slack : 3.707
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.274
Data Delay : 3.209
Slack : 3.707
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.274
Data Delay : 3.209
Slack : 3.707
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.274
Data Delay : 3.209
Slack : 3.707
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.274
Data Delay : 3.209
Slack : 3.707
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.274
Data Delay : 3.209
Slack : 3.707
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.274
Data Delay : 3.209
Slack : 3.707
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.274
Data Delay : 3.209
Slack : 3.707
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.274
Data Delay : 3.209
Slack : 3.707
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.274
Data Delay : 3.209
Slack : 3.707
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.274
Data Delay : 3.209
Slack : 3.707
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.274
Data Delay : 3.209
Slack : 3.707
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.274
Data Delay : 3.209
Slack : 3.707
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.274
Data Delay : 3.209
Slack : 3.707
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.274
Data Delay : 3.209
Slack : 3.707
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.274
Data Delay : 3.209
Slack : 3.707
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.274
Data Delay : 3.209
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.207
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.207
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.207
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.207
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.207
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.272
Data Delay : 3.208
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.207
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.272
Data Delay : 3.208
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.207
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.207
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.207
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.207
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.207
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.207
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.207
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.271
Data Delay : 3.207
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.272
Data Delay : 3.208
Slack : 3.708
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.272
Data Delay : 3.208
Slack : 3.895
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.226
Data Delay : 3.294
Slack : 3.908
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.227
Data Delay : 3.308
Slack : 4.117
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.254
Data Delay : 3.541
Slack : 4.117
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.252
Data Delay : 3.539
Slack : 4.117
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.250
Data Delay : 3.537
Slack : 4.117
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.251
Data Delay : 3.538
Slack : 4.117
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.250
Data Delay : 3.537
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_we_reg
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_address_reg0
Slack : 9.489
Actual Width : 9.719
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_we_reg
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_address_reg0
Slack : 9.490
Actual Width : 9.720
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_we_reg
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_we_reg
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_address_reg0
Slack : 9.491
Actual Width : 9.721
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_we_reg
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0
Slack : 9.492
Actual Width : 9.722
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0
Slack : 9.493
Actual Width : 9.723
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0
Slack : 9.493
Actual Width : 9.723
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0
Slack : 9.497
Actual Width : 9.727
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
Slack : 9.497
Actual Width : 9.727
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
Slack : 9.497
Actual Width : 9.727
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
Slack : 9.497
Actual Width : 9.727
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
Slack : 9.497
Actual Width : 9.727
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~PORTBDATAOUT0
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~PORTBDATAOUT0
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
Slack : 9.498
Actual Width : 9.728
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~PORTBDATAOUT0
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~PORTBDATAOUT0
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~PORTBDATAOUT0
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~PORTBDATAOUT0
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Slack : 9.499
Actual Width : 9.729
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Slack : 9.500
Actual Width : 9.730
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~PORTBDATAOUT0
Slack : 9.500
Actual Width : 9.730
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Slack : 9.500
Actual Width : 9.730
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~PORTBDATAOUT0
Slack : 9.500
Actual Width : 9.730
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Slack : 9.501
Actual Width : 9.731
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_datain_reg0
Slack : 9.501
Actual Width : 9.731
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_datain_reg0
Slack : 9.501
Actual Width : 9.731
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_datain_reg0
Slack : 9.501
Actual Width : 9.731
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_datain_reg0
Slack : 9.501
Actual Width : 9.731
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_datain_reg0
Slack : 9.502
Actual Width : 9.732
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_datain_reg0
Slack : 9.502
Actual Width : 9.732
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_datain_reg0
Slack : 9.502
Actual Width : 9.732
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_datain_reg0
Slack : 9.502
Actual Width : 9.732
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_datain_reg0
Slack : 9.502
Actual Width : 9.732
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_datain_reg0
Slack : 9.502
Actual Width : 9.732
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_datain_reg0
Slack : 9.502
Actual Width : 9.732
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_datain_reg0
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr[0]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr[1]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr[2]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr[3]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr[4]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr[5]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr[6]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr[7]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits[0]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits[1]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits[2]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits[3]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits[4]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits[5]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits[6]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits[7]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[0]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[1]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[2]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[3]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[4]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[5]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[6]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|bits_prefetch[7]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|frame[0]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|frame[1]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|frame[2]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|frame[3]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|frame[4]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_hc[1]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_hc[2]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_hc[3]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_hc[4]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_hc[5]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_hc[6]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_hc[7]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_hc[8]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_hc[9]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_vc[0]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_vc[1]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_vc[2]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_vc[3]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_vc[4]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_vc[5]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_vc[6]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_vc[7]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_vc[8]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_vc[9]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[0]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[10]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[11]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[12]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[1]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[2]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[3]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[4]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[5]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[6]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[7]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[8]
Slack : 19.601
Actual Width : 19.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vram_address[9]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[1]
Slack : 19.602
Actual Width : 19.818
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0
Slack : 19.603
Actual Width : 19.833
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_we_reg
Slack : 19.603
Actual Width : 19.819
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|vga_hc[0]
Slack : 19.604
Actual Width : 19.820
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0]
Slack : 19.604
Actual Width : 19.820
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
Slack : 19.604
Actual Width : 19.834
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_address_reg0
Slack : 19.604
Actual Width : 19.834
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_we_reg
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_we_reg
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_we_reg
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_we_reg
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_we_reg
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_we_reg
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_we_reg
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_we_reg
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_we_reg
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0
Slack : 19.605
Actual Width : 19.835
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0
Slack : 19.605
Actual Width : 19.821
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr_prefetch[0]
Slack : 19.605
Actual Width : 19.821
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr_prefetch[1]
Slack : 19.605
Actual Width : 19.821
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr_prefetch[2]
Slack : 19.605
Actual Width : 19.821
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr_prefetch[3]
Slack : 19.605
Actual Width : 19.821
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr_prefetch[4]
Slack : 19.605
Actual Width : 19.821
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr_prefetch[5]
Slack : 19.605
Actual Width : 19.821
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr_prefetch[6]
Slack : 19.605
Actual Width : 19.821
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ula:ula_|video:video_|attr_prefetch[7]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : 20.590
Actual Width : 20.806
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Slack : 20.590
Actual Width : 20.806
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Slack : 20.590
Actual Width : 20.806
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Slack : 20.590
Actual Width : 20.806
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Slack : 20.590
Actual Width : 20.806
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Slack : 20.594
Actual Width : 20.810
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Data
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Slack : 20.595
Actual Width : 20.811
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Slack : 20.596
Actual Width : 20.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Slack : 20.596
Actual Width : 20.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Slack : 20.596
Actual Width : 20.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Slack : 20.596
Actual Width : 20.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Slack : 20.596
Actual Width : 20.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Slack : 20.596
Actual Width : 20.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Slack : 20.596
Actual Width : 20.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Start
Slack : 20.596
Actual Width : 20.812
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Slack : 20.598
Actual Width : 20.814
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Slack : 20.599
Actual Width : 20.815
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Slack : 20.601
Actual Width : 20.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Slack : 20.601
Actual Width : 20.817
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Slack : 20.633
Actual Width : 20.817
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Slack : 20.633
Actual Width : 20.817
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Slack : 20.633
Actual Width : 20.817
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Slack : 20.633
Actual Width : 20.817
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Slack : 20.633
Actual Width : 20.817
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Slack : 20.633
Actual Width : 20.817
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Slack : 20.667
Actual Width : 20.883
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Slack : 20.667
Actual Width : 20.883
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Slack : 20.667
Actual Width : 20.883
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Slack : 20.667
Actual Width : 20.883
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Slack : 20.667
Actual Width : 20.883
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Slack : 20.667
Actual Width : 20.883
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Slack : 20.695
Actual Width : 20.845
Required Width : 0.150
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|scl_out
Slack : 20.696
Actual Width : 20.846
Required Width : 0.150
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|sda_out
Slack : 20.697
Actual Width : 20.852
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r
Slack : 20.698
Actual Width : 20.853
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r
Slack : 20.698
Actual Width : 20.853
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1
Slack : 20.698
Actual Width : 20.853
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r
Slack : 20.698
Actual Width : 20.853
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17]
Slack : 20.699
Actual Width : 20.849
Required Width : 0.150
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r
Slack : 20.699
Actual Width : 20.849
Required Width : 0.150
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r
Slack : 20.699
Actual Width : 20.849
Required Width : 0.150
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1
Slack : 20.699
Actual Width : 20.849
Required Width : 0.150
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r
Slack : 20.699
Actual Width : 20.849
Required Width : 0.150
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17]
Slack : 20.700
Actual Width : 20.855
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|sda_out
Slack : 20.700
Actual Width : 20.884
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Slack : 20.700
Actual Width : 20.884
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Slack : 20.702
Actual Width : 20.886
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Slack : 20.702
Actual Width : 20.857
Required Width : 0.155
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|scl_out
Slack : 20.702
Actual Width : 20.886
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Slack : 20.702
Actual Width : 20.886
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ;
+--------------------------------------------------------------------------------+
Slack : 35.491
Actual Width : 35.707
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|clk_cpu
Slack : 35.491
Actual Width : 35.707
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|counter[0]
Slack : 35.597
Actual Width : 35.781
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|clk_cpu
Slack : 35.597
Actual Width : 35.781
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|counter[0]
Slack : 35.725
Actual Width : 35.725
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|inclk[0]
Slack : 35.725
Actual Width : 35.725
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|outclk
Slack : 35.731
Actual Width : 35.731
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|clk_cpu|clk
Slack : 35.731
Actual Width : 35.731
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|counter[0]|clk
Slack : 35.757
Actual Width : 35.757
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|clk_cpu|clk
Slack : 35.757
Actual Width : 35.757
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|counter[0]|clk
Slack : 35.763
Actual Width : 35.763
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|inclk[0]
Slack : 35.763
Actual Width : 35.763
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|outclk
Slack : 69.489
Actual Width : 71.489
Required Width : 2.000
Type : Min Period
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|clk_cpu
Slack : 69.489
Actual Width : 71.489
Required Width : 2.000
Type : Min Period
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|counter[0]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Setup Times ;
+--------------------------------------------------------------------------------+
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : 1.644
Fall : 1.865
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : 3.339
Fall : 3.547
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : SW[*]
Clock Port : CLOCK_50
Rise : 0.868
Fall : 1.149
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : SW[2]
Clock Port : CLOCK_50
Rise : 0.868
Fall : 1.149
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : AUD_ADCDAT
Clock Port : CLOCK_50
Rise : 1.441
Fall : 1.652
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 2.596
Fall : 2.778
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Hold Times ;
+--------------------------------------------------------------------------------+
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : -1.287
Fall : -1.512
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : -2.425
Fall : -2.640
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : SW[*]
Clock Port : CLOCK_50
Rise : -0.319
Fall : -0.593
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : SW[2]
Clock Port : CLOCK_50
Rise : -0.319
Fall : -0.593
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : AUD_ADCDAT
Clock Port : CLOCK_50
Rise : -0.901
Fall : -1.108
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : -1.177
Fall : -1.402
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 8.820
Fall : 8.719
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 8.712
Fall : 8.669
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 8.605
Fall : 8.449
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 8.820
Fall : 8.681
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 8.777
Fall : 8.626
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 8.613
Fall : 8.498
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 8.565
Fall : 8.494
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 8.794
Fall : 8.719
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 8.185
Fall : 8.164
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 7.225
Fall : 7.154
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 7.151
Fall : 7.121
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 6.817
Fall : 6.742
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 6.841
Fall : 6.753
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 7.142
Fall : 7.000
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 6.768
Fall : 6.653
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 7.225
Fall : 7.154
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 7.195
Fall : 7.120
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 6.991
Fall : 6.985
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[*]
Clock Port : CLOCK_50
Rise : 7.646
Fall : 7.177
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[0]
Clock Port : CLOCK_50
Rise : 7.646
Fall : 7.177
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[1]
Clock Port : CLOCK_50
Rise : 6.075
Fall : 5.914
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[2]
Clock Port : CLOCK_50
Rise : 6.071
Fall : 5.947
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[3]
Clock Port : CLOCK_50
Rise : 6.163
Fall : 6.057
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[*]
Clock Port : CLOCK_50
Rise : 6.346
Fall : 6.162
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[0]
Clock Port : CLOCK_50
Rise : 6.083
Fall : 5.897
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[1]
Clock Port : CLOCK_50
Rise : 6.346
Fall : 6.162
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[2]
Clock Port : CLOCK_50
Rise : 6.311
Fall : 6.111
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[3]
Clock Port : CLOCK_50
Rise : 6.287
Fall : 6.091
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_HS
Clock Port : CLOCK_50
Rise : 2.597
Fall : 2.522
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[*]
Clock Port : CLOCK_50
Rise : 6.818
Fall : 6.718
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[0]
Clock Port : CLOCK_50
Rise : 6.617
Fall : 6.456
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[1]
Clock Port : CLOCK_50
Rise : 6.818
Fall : 6.718
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[2]
Clock Port : CLOCK_50
Rise : 5.818
Fall : 5.652
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[3]
Clock Port : CLOCK_50
Rise : 6.304
Fall : 6.116
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_VS
Clock Port : CLOCK_50
Rise : 2.595
Fall : 2.520
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCLRCK
Clock Port : CLOCK_50
Rise : 2.592
Fall : 2.517
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_BCLK
Clock Port : CLOCK_50
Rise : 2.592
Fall : 2.517
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACDAT
Clock Port : CLOCK_50
Rise : 2.596
Fall : 2.521
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACLRCK
Clock Port : CLOCK_50
Rise : 4.361
Fall : 3.948
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_XCK
Clock Port : CLOCK_50
Rise : 2.594
Fall : 2.519
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SCLK
Clock Port : CLOCK_50
Rise : 2.647
Fall : 2.553
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 2.648
Fall : 2.554
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 7.516
Fall : 7.474
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 7.855
Fall : 7.805
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 7.763
Fall : 7.613
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 7.799
Fall : 7.666
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 7.769
Fall : 7.624
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 7.603
Fall : 7.549
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 7.816
Fall : 7.752
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 8.138
Fall : 8.067
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 7.516
Fall : 7.474
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 5.188
Fall : 5.076
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 6.129
Fall : 6.073
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 5.781
Fall : 5.660
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 5.993
Fall : 5.893
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 5.188
Fall : 5.076
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 5.555
Fall : 5.507
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 5.982
Fall : 5.904
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 6.184
Fall : 6.158
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 5.809
Fall : 5.760
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[*]
Clock Port : CLOCK_50
Rise : 3.490
Fall : 3.375
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[0]
Clock Port : CLOCK_50
Rise : 5.302
Fall : 4.831
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[1]
Clock Port : CLOCK_50
Rise : 3.490
Fall : 3.375
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[2]
Clock Port : CLOCK_50
Rise : 3.719
Fall : 3.593
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[3]
Clock Port : CLOCK_50
Rise : 3.808
Fall : 3.699
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[*]
Clock Port : CLOCK_50
Rise : 3.542
Fall : 3.413
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[0]
Clock Port : CLOCK_50
Rise : 3.550
Fall : 3.419
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[1]
Clock Port : CLOCK_50
Rise : 3.542
Fall : 3.413
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[2]
Clock Port : CLOCK_50
Rise : 3.770
Fall : 3.624
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[3]
Clock Port : CLOCK_50
Rise : 3.747
Fall : 3.605
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_HS
Clock Port : CLOCK_50
Rise : 2.241
Fall : 2.165
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[*]
Clock Port : CLOCK_50
Rise : 3.296
Fall : 3.183
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[0]
Clock Port : CLOCK_50
Rise : 4.064
Fall : 3.956
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[1]
Clock Port : CLOCK_50
Rise : 3.885
Fall : 3.786
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[2]
Clock Port : CLOCK_50
Rise : 3.296
Fall : 3.183
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[3]
Clock Port : CLOCK_50
Rise : 3.763
Fall : 3.630
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_VS
Clock Port : CLOCK_50
Rise : 2.240
Fall : 2.164
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCLRCK
Clock Port : CLOCK_50
Rise : 2.237
Fall : 2.161
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_BCLK
Clock Port : CLOCK_50
Rise : 2.236
Fall : 2.160
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACDAT
Clock Port : CLOCK_50
Rise : 2.240
Fall : 2.164
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACLRCK
Clock Port : CLOCK_50
Rise : 4.005
Fall : 3.591
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_XCK
Clock Port : CLOCK_50
Rise : 2.238
Fall : 2.162
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SCLK
Clock Port : CLOCK_50
Rise : 2.290
Fall : 2.196
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 2.291
Fall : 2.197
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Propagation Delay ;
+--------------------------------------------------------------------------------+
Input Port : SW[1]
Output Port : LED[0]
RR : 4.182
RF :
FR :
FF : 4.306
Input Port : SW[2]
Output Port : LED[2]
RR : 3.640
RF :
FR :
FF : 3.830
Input Port : raw_loader_in
Output Port : GPIO_1[22]
RR : 6.181
RF :
FR :
FF : 6.311
Input Port : raw_loader_in
Output Port : LED[3]
RR : 3.999
RF :
FR :
FF : 4.176
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Propagation Delay ;
+--------------------------------------------------------------------------------+
Input Port : SW[1]
Output Port : LED[0]
RR : 4.046
RF :
FR :
FF : 4.172
Input Port : SW[2]
Output Port : LED[2]
RR : 3.527
RF :
FR :
FF : 3.715
Input Port : raw_loader_in
Output Port : GPIO_1[22]
RR : 5.960
RF :
FR :
FF : 6.095
Input Port : raw_loader_in
Output Port : LED[3]
RR : 3.866
RF :
FR :
FF : 4.043
+--------------------------------------------------------------------------------+
---------------------------------------------
; Slow 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup Summary ;
+--------------------------------------------------------------------------------+
Clock : CLOCK_50
Slack : -15.171
End Point TNS : -440.252
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Slack : -4.743
End Point TNS : -163.399
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : -3.815
End Point TNS : -35.260
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Slack : -2.784
End Point TNS : -2.784
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold Summary ;
+--------------------------------------------------------------------------------+
Clock : CLOCK_50
Slack : 0.112
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Slack : 0.177
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : 0.178
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Slack : 0.186
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery Summary ;
+--------------------------------------------------------------------------------+
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : -4.728
End Point TNS : -362.420
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal Summary ;
+--------------------------------------------------------------------------------+
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : 2.503
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
+--------------------------------------------------------------------------------+
Clock : CLOCK_50
Slack : 9.208
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Slack : 19.609
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Slack : 20.600
End Point TNS : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Slack : 35.535
End Point TNS : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : -15.171
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.026
Data Delay : 5.219
Slack : -15.085
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.026
Data Delay : 5.133
Slack : -15.048
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.025
Data Delay : 5.097
Slack : -15.012
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.025
Data Delay : 5.061
Slack : -14.996
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.024
Data Delay : 5.046
Slack : -14.991
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.024
Data Delay : 5.041
Slack : -14.969
From Node : ula:ula_|video:video_|vga_hc[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.026
Data Delay : 5.017
Slack : -14.934
From Node : ula:ula_|video:video_|vga_hc[1]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.025
Data Delay : 4.983
Slack : -14.916
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.026
Data Delay : 4.964
Slack : -14.899
From Node : ula:ula_|video:video_|vga_hc[9]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.026
Data Delay : 4.947
Slack : -14.873
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.025
Data Delay : 4.922
Slack : -14.862
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.024
Data Delay : 4.912
Slack : -14.846
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.024
Data Delay : 4.896
Slack : -14.846
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.024
Data Delay : 4.896
Slack : -14.797
From Node : ula:ula_|video:video_|bits[5]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.024
Data Delay : 4.847
Slack : -14.797
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.025
Data Delay : 4.846
Slack : -14.782
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.025
Data Delay : 4.831
Slack : -14.776
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.025
Data Delay : 4.825
Slack : -14.776
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.025
Data Delay : 4.825
Slack : -14.736
From Node : ula:ula_|video:video_|bits[6]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.024
Data Delay : 4.786
Slack : -14.677
From Node : ula:ula_|video:video_|bits[1]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.024
Data Delay : 4.727
Slack : -14.630
From Node : ula:ula_|video:video_|bits[2]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.024
Data Delay : 4.680
Slack : -14.613
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.178
Data Delay : 4.509
Slack : -14.607
From Node : ula:ula_|video:video_|bits[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.024
Data Delay : 4.657
Slack : -14.601
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.009
Data Delay : 4.666
Slack : -14.600
From Node : ula:ula_|video:video_|vga_hc[3]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.026
Data Delay : 4.648
Slack : -14.593
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.188
Data Delay : 4.479
Slack : -14.578
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.009
Data Delay : 4.643
Slack : -14.566
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.014
Data Delay : 4.626
Slack : -14.565
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.009
Data Delay : 4.630
Slack : -14.564
From Node : ula:ula_|video:video_|frame[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.024
Data Delay : 4.614
Slack : -14.564
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.188
Data Delay : 4.450
Slack : -14.534
From Node : ula:ula_|video:video_|bits[3]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.024
Data Delay : 4.584
Slack : -14.528
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.014
Data Delay : 4.588
Slack : -14.528
From Node : ula:ula_|video:video_|attr[7]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.024
Data Delay : 4.578
Slack : -14.525
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.014
Data Delay : 4.585
Slack : -14.521
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.176
Data Delay : 4.419
Slack : -14.513
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.014
Data Delay : 4.573
Slack : -14.478
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.179
Data Delay : 4.373
Slack : -14.464
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.178
Data Delay : 4.360
Slack : -14.449
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.177
Data Delay : 4.346
Slack : -14.436
From Node : ula:ula_|video:video_|bits[4]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.024
Data Delay : 4.486
Slack : -14.431
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.178
Data Delay : 4.327
Slack : -14.426
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8
To Node : GPIO_1[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.184
Data Delay : 4.316
Slack : -14.416
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.009
Data Delay : 4.481
Slack : -14.406
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.169
Data Delay : 4.311
Slack : -14.401
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.179
Data Delay : 4.296
Slack : -14.393
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.171
Data Delay : 4.296
Slack : -14.392
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a3
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.177
Data Delay : 4.289
Slack : -14.383
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6
To Node : GPIO_1[22]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.174
Data Delay : 4.283
Slack : -14.371
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.009
Data Delay : 4.436
Slack : -14.361
From Node : ula:ula_|video:video_|bits[0]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.024
Data Delay : 4.411
Slack : -14.360
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.171
Data Delay : 4.263
Slack : -14.340
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.014
Data Delay : 4.400
Slack : -14.338
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.177
Data Delay : 4.235
Slack : -14.337
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.183
Data Delay : 4.228
Slack : -14.336
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.185
Data Delay : 4.225
Slack : -14.328
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.014
Data Delay : 4.388
Slack : -14.321
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.193
Data Delay : 4.202
Slack : -14.314
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.182
Data Delay : 4.206
Slack : -14.313
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.185
Data Delay : 4.202
Slack : -14.310
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.009
Data Delay : 4.375
Slack : -14.307
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a10
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.178
Data Delay : 4.203
Slack : -14.297
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.183
Data Delay : 4.188
Slack : -14.293
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : VGA_R[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.026
Data Delay : 4.341
Slack : -14.292
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.184
Data Delay : 4.182
Slack : -14.291
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.185
Data Delay : 4.180
Slack : -14.288
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.176
Data Delay : 4.186
Slack : -14.285
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.174
Data Delay : 4.185
Slack : -14.284
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.009
Data Delay : 4.349
Slack : -14.283
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.178
Data Delay : 4.179
Slack : -14.280
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.184
Data Delay : 4.170
Slack : -14.277
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18
To Node : GPIO_1[18]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.174
Data Delay : 4.177
Slack : -14.263
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a15
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.191
Data Delay : 4.146
Slack : -14.256
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.009
Data Delay : 4.321
Slack : -14.253
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.179
Data Delay : 4.148
Slack : -14.231
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5
To Node : GPIO_1[21]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.180
Data Delay : 4.125
Slack : -14.226
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.184
Data Delay : 4.116
Slack : -14.207
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : VGA_R[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.026
Data Delay : 4.255
Slack : -14.203
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.179
Data Delay : 4.098
Slack : -14.198
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.185
Data Delay : 4.087
Slack : -14.183
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.179
Data Delay : 4.078
Slack : -14.166
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : GPIO_1[23]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.194
Data Delay : 4.046
Slack : -14.163
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.181
Data Delay : 4.056
Slack : -14.162
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.183
Data Delay : 4.053
Slack : -14.160
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.014
Data Delay : 4.220
Slack : -14.131
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.184
Data Delay : 4.021
Slack : -14.125
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.183
Data Delay : 4.016
Slack : -14.121
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.184
Data Delay : 4.011
Slack : -14.118
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : VGA_R[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.024
Data Delay : 4.168
Slack : -14.113
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : VGA_R[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.024
Data Delay : 4.163
Slack : -14.107
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : VGA_R[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.025
Data Delay : 4.156
Slack : -14.104
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : VGA_R[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.025
Data Delay : 4.153
Slack : -14.101
From Node : ula:ula_|video:video_|attr[0]
To Node : VGA_B[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.024
Data Delay : 4.151
Slack : -14.097
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25
To Node : GPIO_1[17]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.177
Data Delay : 3.994
Slack : -14.091
From Node : ula:ula_|video:video_|vga_hc[7]
To Node : VGA_R[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.026
Data Delay : 4.139
Slack : -14.066
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11
To Node : GPIO_1[19]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.179
Data Delay : 3.961
Slack : -14.057
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.177
Data Delay : 3.954
Slack : -14.054
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28
To Node : GPIO_1[20]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.181
Data Delay : 3.947
Slack : -14.038
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : VGA_R[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.164
Clock Skew : -0.026
Data Delay : 4.086
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : -4.743
From Node : raw_loader_in
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -0.062
Data Delay : 2.770
Slack : -4.695
From Node : raw_loader_in
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -0.060
Data Delay : 2.724
Slack : -4.673
From Node : raw_loader_in
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -0.056
Data Delay : 2.706
Slack : -4.529
From Node : raw_loader_in
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -0.058
Data Delay : 2.560
Slack : -4.056
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.193
Data Delay : 2.952
Slack : -3.956
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.349
Data Delay : 2.696
Slack : -3.926
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.348
Data Delay : 2.667
Slack : -3.908
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.348
Data Delay : 2.649
Slack : -3.896
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.347
Data Delay : 2.638
Slack : -3.896
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.333
Data Delay : 2.652
Slack : -3.895
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.334
Data Delay : 2.650
Slack : -3.889
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.333
Data Delay : 2.645
Slack : -3.886
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.350
Data Delay : 2.625
Slack : -3.869
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.352
Data Delay : 2.606
Slack : -3.867
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.353
Data Delay : 2.603
Slack : -3.848
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.345
Data Delay : 2.592
Slack : -3.844
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.358
Data Delay : 2.575
Slack : -3.843
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.349
Data Delay : 2.583
Slack : -3.842
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.350
Data Delay : 2.581
Slack : -3.836
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.349
Data Delay : 2.576
Slack : -3.828
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.348
Data Delay : 2.569
Slack : -3.826
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.341
Data Delay : 2.574
Slack : -3.826
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.345
Data Delay : 2.570
Slack : -3.825
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.361
Data Delay : 2.553
Slack : -3.822
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.342
Data Delay : 2.569
Slack : -3.821
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.350
Data Delay : 2.560
Slack : -3.817
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.194
Data Delay : 2.712
Slack : -3.816
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.193
Data Delay : 2.712
Slack : -3.807
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.194
Data Delay : 2.702
Slack : -3.801
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.349
Data Delay : 2.541
Slack : -3.800
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.351
Data Delay : 2.538
Slack : -3.799
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.346
Data Delay : 2.542
Slack : -3.792
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.341
Data Delay : 2.540
Slack : -3.784
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.353
Data Delay : 2.520
Slack : -3.777
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.350
Data Delay : 2.516
Slack : -3.776
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.347
Data Delay : 2.518
Slack : -3.774
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.341
Data Delay : 2.522
Slack : -3.772
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.345
Data Delay : 2.516
Slack : -3.770
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.197
Data Delay : 2.662
Slack : -3.752
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.351
Data Delay : 2.490
Slack : -3.752
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.340
Data Delay : 2.501
Slack : -3.743
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.336
Data Delay : 2.496
Slack : -3.736
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.347
Data Delay : 2.478
Slack : -3.702
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.348
Data Delay : 2.443
Slack : -3.690
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.352
Data Delay : 2.427
Slack : -3.690
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.208
Data Delay : 2.571
Slack : -3.682
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.343
Data Delay : 2.428
Slack : -3.676
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.343
Data Delay : 2.422
Slack : -3.675
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.345
Data Delay : 2.419
Slack : -3.664
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.338
Data Delay : 2.415
Slack : -3.660
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.356
Data Delay : 2.393
Slack : -3.659
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.333
Data Delay : 2.415
Slack : -3.655
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.348
Data Delay : 2.396
Slack : -3.651
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.341
Data Delay : 2.399
Slack : -3.642
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.206
Data Delay : 2.525
Slack : -3.640
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.335
Data Delay : 2.394
Slack : -3.639
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.339
Data Delay : 2.389
Slack : -3.627
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.200
Data Delay : 2.516
Slack : -3.622
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.194
Data Delay : 2.517
Slack : -3.620
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.202
Data Delay : 2.507
Slack : -3.609
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.353
Data Delay : 2.345
Slack : -3.609
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.195
Data Delay : 2.503
Slack : -3.602
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.340
Data Delay : 2.351
Slack : -3.597
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.199
Data Delay : 2.487
Slack : -3.589
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.349
Data Delay : 2.329
Slack : -3.588
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.337
Data Delay : 2.340
Slack : -3.584
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.351
Data Delay : 2.322
Slack : -3.579
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.349
Data Delay : 2.319
Slack : -3.579
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.199
Data Delay : 2.469
Slack : -3.544
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.200
Data Delay : 2.433
Slack : -3.542
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.352
Data Delay : 2.279
Slack : -3.536
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.197
Data Delay : 2.428
Slack : -3.535
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.198
Data Delay : 2.426
Slack : -3.529
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.197
Data Delay : 2.421
Slack : -3.525
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.203
Data Delay : 2.411
Slack : -3.513
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.341
Data Delay : 2.261
Slack : -3.503
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.341
Data Delay : 2.251
Slack : -3.484
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.347
Data Delay : 2.226
Slack : -3.484
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.195
Data Delay : 2.378
Slack : -3.476
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.204
Data Delay : 2.361
Slack : -3.471
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.339
Data Delay : 2.221
Slack : -3.466
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.344
Data Delay : 2.211
Slack : -3.446
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.336
Data Delay : 2.199
Slack : -3.435
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.196
Data Delay : 2.328
Slack : -3.433
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.337
Data Delay : 2.185
Slack : -3.407
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.198
Data Delay : 2.298
Slack : -3.394
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.338
Data Delay : 2.145
Slack : -3.383
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.200
Data Delay : 2.272
Slack : -3.381
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.339
Data Delay : 2.131
Slack : -3.360
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.198
Data Delay : 2.251
Slack : -3.314
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.198
Data Delay : 2.205
Slack : -3.309
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a27~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.193
Data Delay : 2.205
Slack : -3.305
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.202
Data Delay : 2.192
Slack : -3.304
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.204
Data Delay : 2.189
Slack : -3.289
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.199
Data Delay : 2.179
Slack : -3.280
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.200
Data Delay : 2.169
Slack : -3.259
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.338
Data Delay : 2.010
Slack : -3.207
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.340
Data Delay : 1.956
Slack : -3.121
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.199
Data Delay : 2.011
Slack : -3.113
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.120
Clock Skew : -1.206
Data Delay : 1.996
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : -3.815
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 1.960
Slack : -3.815
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 1.960
Slack : -3.760
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.248
Data Delay : 1.836
Slack : -3.475
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.040
Data Delay : 1.806
Slack : -3.475
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.040
Data Delay : 1.806
Slack : -3.475
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.040
Data Delay : 1.806
Slack : -3.475
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.040
Data Delay : 1.806
Slack : -3.475
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.040
Data Delay : 1.806
Slack : -3.345
From Node : I2C_SDAT
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 1.490
Slack : -3.150
From Node : AUD_ADCDAT
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.222
Data Delay : 1.299
Slack : 18.672
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.890
Slack : 18.672
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.890
Slack : 18.672
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.890
Slack : 18.672
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.890
Slack : 18.672
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.890
Slack : 18.672
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.890
Slack : 18.672
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.890
Slack : 18.672
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.890
Slack : 18.672
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.890
Slack : 18.672
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.890
Slack : 18.713
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.849
Slack : 18.713
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.849
Slack : 18.713
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.849
Slack : 18.713
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.849
Slack : 18.743
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.819
Slack : 18.743
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.819
Slack : 18.743
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.819
Slack : 18.743
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.819
Slack : 18.743
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.819
Slack : 18.769
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.794
Slack : 18.769
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.794
Slack : 18.784
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.778
Slack : 18.784
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.778
Slack : 18.801
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.761
Slack : 18.801
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.761
Slack : 18.801
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.761
Slack : 18.801
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.761
Slack : 18.801
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.761
Slack : 18.805
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.755
Slack : 18.805
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.755
Slack : 18.805
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.755
Slack : 18.805
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.755
Slack : 18.840
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.723
Slack : 18.842
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.720
Slack : 18.842
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.720
Slack : 18.876
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.684
Slack : 18.876
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.684
Slack : 18.885
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.678
Slack : 18.885
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.678
Slack : 18.885
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.678
Slack : 18.885
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.678
Slack : 18.898
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.665
Slack : 18.934
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.626
Slack : 18.934
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.278
Data Delay : 1.626
Slack : 18.952
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.089
Data Delay : 1.797
Slack : 18.952
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.089
Data Delay : 1.797
Slack : 18.952
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.089
Data Delay : 1.797
Slack : 18.952
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.089
Data Delay : 1.797
Slack : 18.952
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.089
Data Delay : 1.797
Slack : 18.952
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.089
Data Delay : 1.797
Slack : 18.952
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.089
Data Delay : 1.797
Slack : 18.952
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.089
Data Delay : 1.797
Slack : 18.952
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.089
Data Delay : 1.797
Slack : 18.952
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.089
Data Delay : 1.797
Slack : 18.956
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.607
Slack : 18.956
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.607
Slack : 18.992
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.571
Slack : 18.992
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.571
Slack : 18.992
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.571
Slack : 18.992
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.571
Slack : 18.992
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.571
Slack : 18.992
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.571
Slack : 18.992
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.571
Slack : 18.992
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.571
Slack : 19.012
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.087
Data Delay : 1.739
Slack : 19.012
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.087
Data Delay : 1.739
Slack : 19.014
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.549
Slack : 19.014
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.549
Slack : 19.023
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.089
Data Delay : 1.726
Slack : 19.023
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.089
Data Delay : 1.726
Slack : 19.023
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.089
Data Delay : 1.726
Slack : 19.023
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.089
Data Delay : 1.726
Slack : 19.023
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.089
Data Delay : 1.726
Slack : 19.051
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.511
Slack : 19.051
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.511
Slack : 19.051
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.511
Slack : 19.051
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.511
Slack : 19.051
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.511
Slack : 19.063
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.500
Slack : 19.063
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.500
Slack : 19.063
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.500
Slack : 19.063
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.275
Data Delay : 1.500
Slack : 19.081
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.089
Data Delay : 1.668
Slack : 19.081
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.089
Data Delay : 1.668
Slack : 19.081
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.089
Data Delay : 1.668
Slack : 19.081
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.089
Data Delay : 1.668
Slack : 19.081
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.089
Data Delay : 1.668
Slack : 19.083
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.087
Data Delay : 1.668
Slack : 19.093
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.469
Slack : 19.093
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 20.851
Clock Skew : -0.276
Data Delay : 1.469
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ;
+--------------------------------------------------------------------------------+
Slack : -2.784
From Node : SW[2]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.423
Clock Skew : -0.021
Data Delay : 1.133
Slack : 70.891
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 71.489
Clock Skew : -0.046
Data Delay : 0.539
Slack : 71.071
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|counter[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 71.489
Clock Skew : -0.046
Data Delay : 0.359
Slack : 71.071
From Node : ula:ula_|clocks:clocks_|clk_cpu
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 71.489
Clock Skew : -0.046
Data Delay : 0.359
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : 0.112
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.562
Data Delay : 1.882
Slack : 0.123
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.574
Data Delay : 1.905
Slack : 0.268
From Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|out_address_reg_a[0]
Launch Clock : CLOCK_50
Latch Clock : CLOCK_50
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.388
Slack : 0.505
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.403
Data Delay : 2.116
Slack : 0.509
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.566
Data Delay : 2.283
Slack : 0.511
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.567
Data Delay : 2.286
Slack : 0.514
From Node : ula:ula_|video:video_|vram_address[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.527
Data Delay : 2.249
Slack : 0.514
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.516
Data Delay : 2.238
Slack : 0.515
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.524
Data Delay : 2.247
Slack : 0.516
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.578
Data Delay : 2.302
Slack : 0.516
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.528
Data Delay : 2.252
Slack : 0.516
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.514
Data Delay : 2.238
Slack : 0.516
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.415
Data Delay : 2.139
Slack : 0.519
From Node : ula:ula_|video:video_|vram_address[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.524
Data Delay : 2.251
Slack : 0.520
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.578
Data Delay : 2.306
Slack : 0.524
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.519
Data Delay : 2.251
Slack : 0.538
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.527
Data Delay : 2.273
Slack : 0.540
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.521
Data Delay : 2.269
Slack : 0.540
From Node : ula:ula_|video:video_|vram_address[9]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.513
Data Delay : 2.261
Slack : 0.544
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.415
Data Delay : 2.167
Slack : 0.552
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.519
Data Delay : 2.279
Slack : 0.553
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.514
Data Delay : 2.275
Slack : 0.554
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.522
Data Delay : 2.284
Slack : 0.555
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.511
Data Delay : 2.274
Slack : 0.555
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.521
Data Delay : 2.284
Slack : 0.556
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.517
Data Delay : 2.281
Slack : 0.556
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.514
Data Delay : 2.278
Slack : 0.557
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.519
Data Delay : 2.284
Slack : 0.558
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.517
Data Delay : 2.283
Slack : 0.559
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.527
Data Delay : 2.294
Slack : 0.561
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.517
Data Delay : 2.286
Slack : 0.561
From Node : ula:ula_|video:video_|vram_address[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.521
Data Delay : 2.290
Slack : 0.562
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.522
Data Delay : 2.292
Slack : 0.568
From Node : ula:ula_|video:video_|vram_address[9]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.516
Data Delay : 2.292
Slack : 0.572
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.506
Data Delay : 2.286
Slack : 0.573
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.573
Data Delay : 2.354
Slack : 0.573
From Node : ula:ula_|video:video_|vram_address[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.519
Data Delay : 2.300
Slack : 0.573
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.516
Data Delay : 2.297
Slack : 0.574
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.403
Data Delay : 2.185
Slack : 0.574
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.521
Data Delay : 2.303
Slack : 0.574
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.510
Data Delay : 2.292
Slack : 0.575
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.509
Data Delay : 2.292
Slack : 0.575
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.510
Data Delay : 2.293
Slack : 0.576
From Node : ula:ula_|video:video_|vram_address[9]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.518
Data Delay : 2.302
Slack : 0.576
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.410
Data Delay : 2.194
Slack : 0.576
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.563
Data Delay : 2.347
Slack : 0.577
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.527
Data Delay : 2.312
Slack : 0.578
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.527
Data Delay : 2.313
Slack : 0.579
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.519
Data Delay : 2.306
Slack : 0.579
From Node : ula:ula_|video:video_|vram_address[9]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.521
Data Delay : 2.308
Slack : 0.580
From Node : ula:ula_|video:video_|vram_address[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.518
Data Delay : 2.306
Slack : 0.580
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.519
Data Delay : 2.307
Slack : 0.581
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.521
Data Delay : 2.310
Slack : 0.583
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.413
Data Delay : 2.204
Slack : 0.585
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.511
Data Delay : 2.304
Slack : 0.585
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.402
Data Delay : 2.195
Slack : 0.587
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.512
Data Delay : 2.307
Slack : 0.589
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.393
Data Delay : 2.190
Slack : 0.591
From Node : ula:ula_|video:video_|vram_address[9]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.510
Data Delay : 2.309
Slack : 0.591
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.521
Data Delay : 2.320
Slack : 0.591
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.410
Data Delay : 2.209
Slack : 0.592
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.506
Data Delay : 2.306
Slack : 0.594
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.519
Data Delay : 2.321
Slack : 0.594
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.509
Data Delay : 2.311
Slack : 0.594
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.522
Data Delay : 2.324
Slack : 0.595
From Node : ula:ula_|video:video_|vram_address[9]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.505
Data Delay : 2.308
Slack : 0.595
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.576
Data Delay : 2.379
Slack : 0.596
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.570
Data Delay : 2.374
Slack : 0.596
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.512
Data Delay : 2.316
Slack : 0.596
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.519
Data Delay : 2.323
Slack : 0.596
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.511
Data Delay : 2.315
Slack : 0.596
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.521
Data Delay : 2.325
Slack : 0.598
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.511
Data Delay : 2.317
Slack : 0.598
From Node : ula:ula_|video:video_|vram_address[9]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.508
Data Delay : 2.314
Slack : 0.598
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.513
Data Delay : 2.319
Slack : 0.599
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.524
Data Delay : 2.331
Slack : 0.604
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.565
Data Delay : 2.377
Slack : 0.604
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.513
Data Delay : 2.325
Slack : 0.605
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.562
Data Delay : 2.375
Slack : 0.605
From Node : ula:ula_|video:video_|vram_address[7]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.520
Data Delay : 2.333
Slack : 0.605
From Node : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a1
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.408
Data Delay : 2.221
Slack : 0.606
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.505
Data Delay : 2.319
Slack : 0.607
From Node : ula:ula_|video:video_|vram_address[2]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.510
Data Delay : 2.325
Slack : 0.607
From Node : ula:ula_|video:video_|vram_address[3]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.521
Data Delay : 2.336
Slack : 0.607
From Node : ula:ula_|video:video_|vram_address[4]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.505
Data Delay : 2.320
Slack : 0.607
From Node : ula:ula_|video:video_|vram_address[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.521
Data Delay : 2.336
Slack : 0.607
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.415
Data Delay : 2.230
Slack : 0.608
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.516
Data Delay : 2.332
Slack : 0.610
From Node : ula:ula_|video:video_|vram_address[11]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.518
Data Delay : 2.336
Slack : 0.610
From Node : ula:ula_|video:video_|vram_address[12]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.513
Data Delay : 2.331
Slack : 0.610
From Node : ula:ula_|video:video_|vram_address[1]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.511
Data Delay : 2.329
Slack : 0.610
From Node : ula:ula_|video:video_|vram_address[9]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.509
Data Delay : 2.327
Slack : 0.611
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.409
Data Delay : 2.228
Slack : 0.611
From Node : ula:ula_|video:video_|vram_address[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.510
Data Delay : 2.329
Slack : 0.611
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.525
Data Delay : 2.344
Slack : 0.612
From Node : ula:ula_|video:video_|vram_address[5]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.528
Data Delay : 2.348
Slack : 0.612
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.514
Data Delay : 2.334
Slack : 0.613
From Node : ula:ula_|video:video_|vram_address[9]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.511
Data Delay : 2.332
Slack : 0.615
From Node : ula:ula_|video:video_|vram_address[0]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.516
Data Delay : 2.339
Slack : 0.615
From Node : ula:ula_|video:video_|vram_address[6]
To Node : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : CLOCK_50
Relationship : 0.044
Clock Skew : 1.517
Data Delay : 2.340
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ;
+--------------------------------------------------------------------------------+
Slack : 0.177
From Node : ula:ula_|clocks:clocks_|clk_cpu
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.000
Clock Skew : 0.046
Data Delay : 0.307
Slack : 0.184
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|counter[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.000
Clock Skew : 0.046
Data Delay : 0.314
Slack : 0.306
From Node : ula:ula_|clocks:clocks_|counter[0]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : 0.000
Clock Skew : 0.046
Data Delay : 0.436
Slack : 1.186
From Node : SW[2]
To Node : ula:ula_|clocks:clocks_|clk_cpu
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Relationship : -0.017
Clock Skew : 0.233
Data Delay : 0.576
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : 0.178
From Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.307
Slack : 0.178
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.307
Slack : 0.178
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.307
Slack : 0.183
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.314
Slack : 0.185
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.314
Slack : 0.185
From Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.314
Slack : 0.186
From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.187
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.307
Slack : 0.187
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.307
Slack : 0.187
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.307
Slack : 0.187
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.307
Slack : 0.187
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.307
Slack : 0.192
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.313
Slack : 0.193
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.314
Slack : 0.193
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.314
Slack : 0.193
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.314
Slack : 0.193
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.314
Slack : 0.194
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.315
Slack : 0.194
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.315
Slack : 0.194
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.315
Slack : 0.194
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.314
Slack : 0.194
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.314
Slack : 0.196
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.317
Slack : 0.201
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.322
Slack : 0.222
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.342
Slack : 0.225
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.345
Slack : 0.226
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.346
Slack : 0.233
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.233
Data Delay : 0.550
Slack : 0.246
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.237
Data Delay : 0.567
Slack : 0.252
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.373
Slack : 0.253
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.374
Slack : 0.253
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.374
Slack : 0.254
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.375
Slack : 0.256
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.235
Data Delay : 0.575
Slack : 0.263
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.384
Slack : 0.273
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.394
Slack : 0.275
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.396
Slack : 0.286
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.417
Slack : 0.287
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.418
Slack : 0.289
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.420
Slack : 0.290
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.421
Slack : 0.293
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.235
Data Delay : 0.612
Slack : 0.293
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.424
Slack : 0.294
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.415
Slack : 0.295
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.416
Slack : 0.295
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.416
Slack : 0.296
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.417
Slack : 0.298
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.419
Slack : 0.298
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.418
Slack : 0.298
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.429
Slack : 0.299
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.419
Slack : 0.300
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.421
Slack : 0.306
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.427
Slack : 0.307
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.436
Slack : 0.307
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.427
Slack : 0.310
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.439
Slack : 0.310
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.439
Slack : 0.310
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.430
Slack : 0.310
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.430
Slack : 0.312
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.441
Slack : 0.314
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.434
Slack : 0.315
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.435
Slack : 0.322
From Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.045
Data Delay : 0.451
Slack : 0.340
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.461
Slack : 0.341
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.462
Slack : 0.357
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.478
Slack : 0.362
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.235
Data Delay : 0.681
Slack : 0.376
From Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.496
Slack : 0.378
From Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.499
Slack : 0.382
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.502
Slack : 0.394
From Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : -0.154
Data Delay : 0.324
Slack : 0.398
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.519
Slack : 0.399
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.520
Slack : 0.403
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.524
Slack : 0.414
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.231
Data Delay : 0.729
Slack : 0.414
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.231
Data Delay : 0.729
Slack : 0.414
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.231
Data Delay : 0.729
Slack : 0.414
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.231
Data Delay : 0.729
Slack : 0.414
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.231
Data Delay : 0.729
Slack : 0.415
From Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.235
Data Delay : 0.734
Slack : 0.427
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.547
Slack : 0.433
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.553
Slack : 0.433
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.554
Slack : 0.434
From Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.554
Slack : 0.435
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.566
Slack : 0.436
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.557
Slack : 0.436
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.567
Slack : 0.439
From Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.560
Slack : 0.441
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.561
Slack : 0.443
From Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.563
Slack : 0.446
From Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.566
Slack : 0.446
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.566
Slack : 0.446
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.577
Slack : 0.447
From Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.567
Slack : 0.447
From Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.047
Data Delay : 0.578
Slack : 0.448
From Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.568
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 0.186
From Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vram_address[10]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : ula:ula_|video:video_|vga_vc[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|vga_vc[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|vga_vc[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vga_vc[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : ula:ula_|video:video_|vga_vc[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : ula:ula_|video:video_|vga_vc[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.186
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : ula:ula_|video:video_|vga_vc[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.307
Slack : 0.293
From Node : ula:ula_|video:video_|frame[2]
To Node : ula:ula_|video:video_|frame[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.414
Slack : 0.295
From Node : ula:ula_|video:video_|frame[3]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.416
Slack : 0.299
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.420
Slack : 0.442
From Node : ula:ula_|video:video_|frame[2]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.563
Slack : 0.452
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.573
Slack : 0.455
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.576
Slack : 0.478
From Node : ula:ula_|video:video_|bits_prefetch[1]
To Node : ula:ula_|video:video_|bits[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.152
Data Delay : 0.410
Slack : 0.484
From Node : ula:ula_|video:video_|bits_prefetch[5]
To Node : ula:ula_|video:video_|bits[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.152
Data Delay : 0.416
Slack : 0.532
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vram_address[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.035
Data Delay : 0.651
Slack : 0.533
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vram_address[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.035
Data Delay : 0.652
Slack : 0.536
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vram_address[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.035
Data Delay : 0.655
Slack : 0.548
From Node : ula:ula_|video:video_|bits_prefetch[3]
To Node : ula:ula_|video:video_|bits[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.152
Data Delay : 0.480
Slack : 0.548
From Node : ula:ula_|video:video_|bits_prefetch[4]
To Node : ula:ula_|video:video_|bits[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.152
Data Delay : 0.480
Slack : 0.548
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : ula:ula_|video:video_|vram_address[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.035
Data Delay : 0.667
Slack : 0.559
From Node : ula:ula_|video:video_|vga_hc[1]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.679
Slack : 0.560
From Node : ula:ula_|video:video_|bits_prefetch[7]
To Node : ula:ula_|video:video_|bits[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.152
Data Delay : 0.492
Slack : 0.562
From Node : ula:ula_|video:video_|vga_hc[4]
To Node : ula:ula_|video:video_|vram_address[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.035
Data Delay : 0.681
Slack : 0.565
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.035
Data Delay : 0.684
Slack : 0.569
From Node : ula:ula_|video:video_|bits_prefetch[2]
To Node : ula:ula_|video:video_|bits[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.152
Data Delay : 0.501
Slack : 0.575
From Node : ula:ula_|video:video_|attr_prefetch[7]
To Node : ula:ula_|video:video_|attr[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.166
Data Delay : 0.493
Slack : 0.576
From Node : ula:ula_|video:video_|attr_prefetch[3]
To Node : ula:ula_|video:video_|attr[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.166
Data Delay : 0.494
Slack : 0.592
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.038
Data Delay : 0.714
Slack : 0.606
From Node : ula:ula_|video:video_|attr_prefetch[0]
To Node : ula:ula_|video:video_|attr[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.166
Data Delay : 0.524
Slack : 0.615
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[12]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.735
Slack : 0.615
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.735
Slack : 0.645
From Node : ula:ula_|video:video_|bits_prefetch[6]
To Node : ula:ula_|video:video_|bits[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.152
Data Delay : 0.577
Slack : 0.652
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.035
Data Delay : 0.771
Slack : 0.659
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : ula:ula_|video:video_|vram_address[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.779
Slack : 0.662
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.782
Slack : 0.662
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.782
Slack : 0.663
From Node : ula:ula_|video:video_|vga_hc[7]
To Node : ula:ula_|video:video_|vram_address[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.035
Data Delay : 0.782
Slack : 0.663
From Node : ula:ula_|video:video_|vga_hc[7]
To Node : ula:ula_|video:video_|vram_address[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.035
Data Delay : 0.782
Slack : 0.664
From Node : ula:ula_|video:video_|vga_vc[6]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.035
Data Delay : 0.783
Slack : 0.669
From Node : ula:ula_|video:video_|vga_hc[7]
To Node : ula:ula_|video:video_|vga_hc[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.790
Slack : 0.671
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vga_hc[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.792
Slack : 0.678
From Node : ula:ula_|video:video_|attr_prefetch[4]
To Node : ula:ula_|video:video_|attr[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.166
Data Delay : 0.596
Slack : 0.684
From Node : ula:ula_|video:video_|attr_prefetch[6]
To Node : ula:ula_|video:video_|attr[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.166
Data Delay : 0.602
Slack : 0.687
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.807
Slack : 0.709
From Node : ula:ula_|video:video_|attr_prefetch[5]
To Node : ula:ula_|video:video_|attr[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.166
Data Delay : 0.627
Slack : 0.714
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.035
Data Delay : 0.833
Slack : 0.728
From Node : ula:ula_|video:video_|vga_hc[8]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.848
Slack : 0.736
From Node : ula:ula_|video:video_|vga_hc[3]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.035
Data Delay : 0.855
Slack : 0.744
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.038
Data Delay : 0.866
Slack : 0.744
From Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|address_reg_a[0]
To Node : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|out_address_reg_a[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.864
Slack : 0.747
From Node : ula:ula_|video:video_|frame[0]
To Node : ula:ula_|video:video_|frame[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.038
Data Delay : 0.869
Slack : 0.764
From Node : ula:ula_|video:video_|frame[4]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.885
Slack : 0.767
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.035
Data Delay : 0.886
Slack : 0.777
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.035
Data Delay : 0.896
Slack : 0.784
From Node : ula:ula_|video:video_|frame[3]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.904
Slack : 0.790
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : ula:ula_|video:video_|vram_address[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.911
Slack : 0.791
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : ula:ula_|video:video_|vram_address[12]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.912
Slack : 0.804
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.155
Data Delay : 0.733
Slack : 0.811
From Node : ula:ula_|video:video_|vga_vc[5]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.035
Data Delay : 0.930
Slack : 0.829
From Node : ula:ula_|video:video_|vga_hc[6]
To Node : ula:ula_|video:video_|vga_hc[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.950
Slack : 0.836
From Node : ula:ula_|video:video_|frame[2]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.956
Slack : 0.849
From Node : ula:ula_|video:video_|frame[1]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.969
Slack : 0.863
From Node : ula:ula_|video:video_|vga_hc[3]
To Node : ula:ula_|video:video_|vga_hc[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 0.984
Slack : 0.876
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.996
Slack : 0.879
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 0.999
Slack : 0.887
From Node : ula:ula_|video:video_|vga_hc[3]
To Node : ula:ula_|video:video_|vga_hc[3]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 1.008
Slack : 0.888
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 1.008
Slack : 0.891
From Node : ula:ula_|video:video_|vga_hc[2]
To Node : ula:ula_|video:video_|vram_address[10]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 1.011
Slack : 0.891
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 1.011
Slack : 0.894
From Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
To Node : ula:ula_|video:video_|VGA_VS
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.020
Data Delay : 0.970
Slack : 0.902
From Node : ula:ula_|video:video_|attr_prefetch[2]
To Node : ula:ula_|video:video_|attr[2]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.166
Data Delay : 0.820
Slack : 0.908
From Node : ula:ula_|video:video_|vga_vc[1]
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.038
Data Delay : 1.030
Slack : 0.909
From Node : ula:ula_|video:video_|vga_hc[9]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.035
Data Delay : 1.028
Slack : 0.919
From Node : ula:ula_|video:video_|bits_prefetch[0]
To Node : ula:ula_|video:video_|bits[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.152
Data Delay : 0.851
Slack : 0.927
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vram_address[5]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 1.047
Slack : 0.928
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 1.048
Slack : 0.930
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vram_address[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 1.050
Slack : 0.939
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 1.060
Slack : 0.942
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 1.062
Slack : 0.943
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : ula:ula_|video:video_|frame[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 1.063
Slack : 0.949
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : ula:ula_|video:video_|vga_hc[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 1.070
Slack : 0.954
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 1.074
Slack : 0.962
From Node : ula:ula_|video:video_|vga_vc[9]
To Node : ula:ula_|video:video_|VGA_VS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 1.083
Slack : 0.968
From Node : ula:ula_|video:video_|vga_vc[2]
To Node : ula:ula_|video:video_|vram_address[9]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 1.089
Slack : 0.979
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : ula:ula_|video:video_|VGA_HS~_Duplicate_1
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.035
Data Delay : 1.098
Slack : 0.987
From Node : ula:ula_|video:video_|vga_vc[0]
To Node : ula:ula_|video:video_|vga_vc[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 1.108
Slack : 0.987
From Node : ula:ula_|video:video_|vga_vc[4]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 1.107
Slack : 0.989
From Node : ula:ula_|video:video_|attr_prefetch[1]
To Node : ula:ula_|video:video_|attr[1]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.166
Data Delay : 0.907
Slack : 0.990
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : ula:ula_|video:video_|vram_address[8]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 1.110
Slack : 0.992
From Node : ula:ula_|video:video_|vga_vc[7]
To Node : ula:ula_|video:video_|vram_address[11]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 1.112
Slack : 0.993
From Node : ula:ula_|video:video_|vga_vc[3]
To Node : ula:ula_|video:video_|vram_address[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.036
Data Delay : 1.113
Slack : 0.996
From Node : ula:ula_|video:video_|vga_hc[3]
To Node : ula:ula_|video:video_|vga_hc[6]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 1.117
Slack : 1.006
From Node : ula:ula_|video:video_|vga_vc[8]
To Node : ula:ula_|video:video_|frame[0]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 1.127
Slack : 1.008
From Node : ula:ula_|video:video_|vga_hc[0]
To Node : ula:ula_|video:video_|vga_hc[4]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : -0.153
Data Delay : 0.939
Slack : 1.012
From Node : ula:ula_|video:video_|vga_hc[5]
To Node : ula:ula_|video:video_|vga_hc[7]
Launch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Relationship : 0.000
Clock Skew : 0.037
Data Delay : 1.133
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : -4.728
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.225
Data Delay : 2.826
Slack : -4.728
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.227
Data Delay : 2.824
Slack : -4.728
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.230
Data Delay : 2.821
Slack : -4.727
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.824
Slack : -4.727
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.228
Data Delay : 2.822
Slack : -4.618
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.248
Data Delay : 2.694
Slack : -4.610
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.251
Data Delay : 2.683
Slack : -4.465
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.222
Data Delay : 2.614
Slack : -4.465
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.222
Data Delay : 2.614
Slack : -4.465
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.222
Data Delay : 2.614
Slack : -4.465
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.222
Data Delay : 2.614
Slack : -4.465
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.222
Data Delay : 2.614
Slack : -4.465
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.222
Data Delay : 2.614
Slack : -4.465
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.607
Slack : -4.465
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.229
Data Delay : 2.607
Slack : -4.465
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.227
Data Delay : 2.609
Slack : -4.465
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.227
Data Delay : 2.609
Slack : -4.465
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.227
Data Delay : 2.609
Slack : -4.465
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.227
Data Delay : 2.609
Slack : -4.465
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.227
Data Delay : 2.609
Slack : -4.465
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.227
Data Delay : 2.609
Slack : -4.465
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.227
Data Delay : 2.609
Slack : -4.465
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.222
Data Delay : 2.614
Slack : -4.465
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.222
Data Delay : 2.614
Slack : -4.465
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.222
Data Delay : 2.614
Slack : -4.465
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.222
Data Delay : 2.614
Slack : -4.465
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.222
Data Delay : 2.614
Slack : -4.465
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.222
Data Delay : 2.614
Slack : -4.465
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.222
Data Delay : 2.614
Slack : -4.465
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.222
Data Delay : 2.614
Slack : -4.465
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.222
Data Delay : 2.614
Slack : -4.465
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.222
Data Delay : 2.614
Slack : -4.465
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.222
Data Delay : 2.614
Slack : -4.465
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.222
Data Delay : 2.614
Slack : -4.465
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.222
Data Delay : 2.614
Slack : -4.465
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.222
Data Delay : 2.614
Slack : -4.465
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.222
Data Delay : 2.614
Slack : -4.465
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.222
Data Delay : 2.614
Slack : -4.465
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.222
Data Delay : 2.614
Slack : -4.464
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.221
Data Delay : 2.614
Slack : -4.464
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.221
Data Delay : 2.614
Slack : -4.464
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.221
Data Delay : 2.614
Slack : -4.464
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.221
Data Delay : 2.614
Slack : -4.464
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.221
Data Delay : 2.614
Slack : -4.464
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.221
Data Delay : 2.614
Slack : -4.464
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.609
Slack : -4.464
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.609
Slack : -4.464
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.609
Slack : -4.464
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.609
Slack : -4.464
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.609
Slack : -4.464
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.609
Slack : -4.464
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.609
Slack : -4.464
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.609
Slack : -4.464
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.609
Slack : -4.464
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.609
Slack : -4.464
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.226
Data Delay : 2.609
Slack : -4.278
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.040
Data Delay : 2.609
Slack : -4.278
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.040
Data Delay : 2.609
Slack : -4.278
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.040
Data Delay : 2.609
Slack : -4.278
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.040
Data Delay : 2.609
Slack : -4.278
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.040
Data Delay : 2.609
Slack : -4.274
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.038
Data Delay : 2.607
Slack : -4.274
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.036
Data Delay : 2.609
Slack : -4.274
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.036
Data Delay : 2.609
Slack : -4.273
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.030
Data Delay : 2.614
Slack : -4.265
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.021
Data Delay : 2.615
Slack : -4.265
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.021
Data Delay : 2.615
Slack : -4.265
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.021
Data Delay : 2.615
Slack : -4.265
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.021
Data Delay : 2.615
Slack : -4.265
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.022
Data Delay : 2.614
Slack : -4.259
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.016
Data Delay : 2.614
Slack : -4.259
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.016
Data Delay : 2.614
Slack : -4.259
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.016
Data Delay : 2.614
Slack : -4.259
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.016
Data Delay : 2.614
Slack : -4.259
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.016
Data Delay : 2.614
Slack : -4.259
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.424
Clock Skew : -0.016
Data Delay : 2.614
Slack : -4.237
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.002
Data Delay : 2.607
Slack : -4.237
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.002
Data Delay : 2.607
Slack : -4.237
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.002
Data Delay : 2.607
Slack : -4.237
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.002
Data Delay : 2.607
Slack : -4.237
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.002
Data Delay : 2.607
Slack : -4.237
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : 0.421
Clock Skew : 0.002
Data Delay : 2.607
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : 2.503
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.257
Data Delay : 1.931
Slack : 2.503
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.257
Data Delay : 1.931
Slack : 2.503
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.257
Data Delay : 1.931
Slack : 2.503
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.257
Data Delay : 1.931
Slack : 2.503
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.257
Data Delay : 1.931
Slack : 2.503
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.003
Clock Skew : 0.257
Data Delay : 1.931
Slack : 2.532
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.238
Data Delay : 1.938
Slack : 2.532
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.238
Data Delay : 1.938
Slack : 2.532
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.238
Data Delay : 1.938
Slack : 2.532
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.238
Data Delay : 1.938
Slack : 2.532
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.238
Data Delay : 1.938
Slack : 2.532
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.238
Data Delay : 1.938
Slack : 2.538
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.232
Data Delay : 1.938
Slack : 2.538
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.232
Data Delay : 1.938
Slack : 2.538
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.232
Data Delay : 1.938
Slack : 2.538
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.232
Data Delay : 1.938
Slack : 2.538
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.231
Data Delay : 1.937
Slack : 2.547
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.223
Data Delay : 1.938
Slack : 2.548
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.215
Data Delay : 1.931
Slack : 2.548
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.217
Data Delay : 1.933
Slack : 2.548
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.217
Data Delay : 1.933
Slack : 2.551
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.213
Data Delay : 1.932
Slack : 2.551
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.213
Data Delay : 1.932
Slack : 2.551
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.213
Data Delay : 1.932
Slack : 2.551
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.213
Data Delay : 1.932
Slack : 2.551
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.213
Data Delay : 1.932
Slack : 2.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.023
Data Delay : 1.937
Slack : 2.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.023
Data Delay : 1.937
Slack : 2.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.023
Data Delay : 1.937
Slack : 2.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.023
Data Delay : 1.937
Slack : 2.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.023
Data Delay : 1.937
Slack : 2.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.023
Data Delay : 1.937
Slack : 2.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.023
Data Delay : 1.937
Slack : 2.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.023
Data Delay : 1.937
Slack : 2.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.023
Data Delay : 1.937
Slack : 2.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.023
Data Delay : 1.937
Slack : 2.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.023
Data Delay : 1.937
Slack : 2.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.023
Data Delay : 1.937
Slack : 2.746
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.932
Slack : 2.746
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.932
Slack : 2.746
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.932
Slack : 2.746
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.932
Slack : 2.746
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.932
Slack : 2.746
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.932
Slack : 2.746
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.932
Slack : 2.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.023
Data Delay : 1.937
Slack : 2.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.023
Data Delay : 1.937
Slack : 2.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.023
Data Delay : 1.937
Slack : 2.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.023
Data Delay : 1.937
Slack : 2.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.023
Data Delay : 1.937
Slack : 2.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.023
Data Delay : 1.937
Slack : 2.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.023
Data Delay : 1.937
Slack : 2.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.023
Data Delay : 1.937
Slack : 2.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.023
Data Delay : 1.937
Slack : 2.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.023
Data Delay : 1.937
Slack : 2.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.023
Data Delay : 1.937
Slack : 2.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.023
Data Delay : 1.937
Slack : 2.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.023
Data Delay : 1.937
Slack : 2.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.023
Data Delay : 1.937
Slack : 2.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.023
Data Delay : 1.937
Slack : 2.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.023
Data Delay : 1.937
Slack : 2.746
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.023
Data Delay : 1.937
Slack : 2.747
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.933
Slack : 2.747
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.933
Slack : 2.747
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.933
Slack : 2.747
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.933
Slack : 2.747
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.016
Data Delay : 1.931
Slack : 2.747
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.016
Data Delay : 1.931
Slack : 2.747
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.933
Slack : 2.747
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.933
Slack : 2.747
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Start
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.933
Slack : 2.747
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|state.Data
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.933
Slack : 2.747
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.933
Slack : 2.747
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.933
Slack : 2.747
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.018
Data Delay : 1.933
Slack : 2.882
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|scl_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : -0.019
Data Delay : 2.005
Slack : 2.888
From Node : KEY[0]
To Node : ula:ula_|i2c_loader:i2c_loader_|sda_out
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : -0.016
Data Delay : 2.014
Slack : 2.993
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|shiftreg[17]
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.009
Data Delay : 2.142
Slack : 2.993
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_1
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.007
Data Delay : 2.140
Slack : 2.994
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|mclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.007
Data Delay : 2.141
Slack : 2.994
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|lrclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.005
Data Delay : 2.139
Slack : 2.994
From Node : KEY[0]
To Node : ula:ula_|i2s_intf:i2s_intf_|bclk_r
Launch Clock : CLOCK_50
Latch Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Relationship : -0.006
Clock Skew : 0.004
Data Delay : 2.138
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50' ;
+--------------------------------------------------------------------------------+
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_address_reg0
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_we_reg
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_address_reg0
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_we_reg
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_address_reg0
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_we_reg
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_address_reg0
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_we_reg
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_address_reg0
Slack : 9.208
Actual Width : 9.438
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_we_reg
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_address_reg0
Slack : 9.209
Actual Width : 9.439
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_we_reg
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~porta_datain_reg0
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~porta_datain_reg0
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~porta_datain_reg0
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~porta_datain_reg0
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~porta_datain_reg0
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_address_reg0
Slack : 9.210
Actual Width : 9.440
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_we_reg
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~PORTBDATAOUT0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_address_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~porta_datain_reg0
Slack : 9.211
Actual Width : 9.441
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~porta_datain_reg0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~PORTBDATAOUT0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_address_reg0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_address_reg0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_address_reg0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_address_reg0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_address_reg0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_address_reg0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~PORTBDATAOUT0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_address_reg0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~PORTBDATAOUT0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_address_reg0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~PORTBDATAOUT0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_address_reg0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~PORTBDATAOUT0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_address_reg0
Slack : 9.212
Actual Width : 9.442
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~porta_datain_reg0
Slack : 9.213
Actual Width : 9.443
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13
Slack : 9.213
Actual Width : 9.443
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_address_reg0
Slack : 9.213
Actual Width : 9.443
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a4~portb_datain_reg0
Slack : 9.213
Actual Width : 9.443
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5
Slack : 9.213
Actual Width : 9.443
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~PORTBDATAOUT0
Slack : 9.213
Actual Width : 9.443
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a5~portb_address_reg0
Slack : 9.213
Actual Width : 9.443
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6
Slack : 9.213
Actual Width : 9.443
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~PORTBDATAOUT0
Slack : 9.213
Actual Width : 9.443
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a6~portb_address_reg0
Slack : 9.213
Actual Width : 9.443
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8
Slack : 9.213
Actual Width : 9.443
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a8~portb_address_reg0
Slack : 9.213
Actual Width : 9.443
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9
Slack : 9.213
Actual Width : 9.443
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a9~portb_address_reg0
Slack : 9.214
Actual Width : 9.444
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a0~portb_datain_reg0
Slack : 9.214
Actual Width : 9.444
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a10~portb_datain_reg0
Slack : 9.214
Actual Width : 9.444
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a11~portb_datain_reg0
Slack : 9.214
Actual Width : 9.444
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a12~portb_datain_reg0
Slack : 9.214
Actual Width : 9.444
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a14~portb_datain_reg0
Slack : 9.214
Actual Width : 9.444
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a15~portb_datain_reg0
Slack : 9.214
Actual Width : 9.444
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a1~portb_datain_reg0
Slack : 9.214
Actual Width : 9.444
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a2~portb_datain_reg0
Slack : 9.214
Actual Width : 9.444
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a3~portb_datain_reg0
Slack : 9.214
Actual Width : 9.444
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a7~portb_datain_reg0
Slack : 9.215
Actual Width : 9.445
Required Width : 0.230
Type : Low Pulse Width
Clock : CLOCK_50
Clock Edge : Rise
Target : ram16:ram0|altsyncram:altsyncram_component|altsyncram_7ti2:auto_generated|ram_block1a13~portb_datain_reg0
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[0]' ;
+--------------------------------------------------------------------------------+
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_address_reg0
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_we_reg
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_address_reg0
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_we_reg
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_address_reg0
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_we_reg
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_address_reg0
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_we_reg
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_address_reg0
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28~porta_we_reg
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_address_reg0
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2~porta_we_reg
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_address_reg0
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30~porta_we_reg
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_address_reg0
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6~porta_we_reg
Slack : 19.609
Actual Width : 19.839
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a2
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a28
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a29~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a30
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a31~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a3~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a4~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a5~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a6
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a7~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a8~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a9~porta_we_reg
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a0~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a11
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a12~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a13~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a14~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a2~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a4~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a5~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a6~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a7~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a8~porta_address_reg0
Slack : 19.610
Actual Width : 19.840
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : rom0:rom|altsyncram:altsyncram_component|altsyncram_qh91:auto_generated|ram_block1a9~porta_address_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a1
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a10
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a11
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a12~porta_datain_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a13
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a14
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a15
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a16
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a17~porta_datain_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a18~porta_datain_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_address_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a19~porta_we_reg
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a20
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a21
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a22~porta_datain_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_address_reg0
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a23~porta_we_reg
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a24
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a25
Slack : 19.611
Actual Width : 19.841
Required Width : 0.230
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Clock Edge : Rise
Target : ram32:ram1|altsyncram:altsyncram_component|altsyncram_g9i1:auto_generated|ram_block1a26
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[2]' ;
+--------------------------------------------------------------------------------+
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[0]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[1]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[2]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[3]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[4]
Slack : 20.600
Actual Width : 20.816
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Fall
Target : ula:ula_|i2c_loader:i2c_loader_|divider[5]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|phase[0]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|phase[1]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|scl_out~_Duplicate_1
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|sda_out~_Duplicate_1
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[5]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Data
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Idle
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Pause
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Start
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INL[14]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|PCM_INR[14]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bclk_r~_Duplicate_1
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[0]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[1]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[2]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[3]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bdivider[4]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[0]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[1]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[2]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[3]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|bitcount[4]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[0]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[10]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[11]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[12]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[13]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[14]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[15]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[1]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[2]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[3]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[4]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[5]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[6]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[7]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[8]
Slack : 20.633
Actual Width : 20.849
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[9]
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[0]
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[1]
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[2]
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[3]
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[4]
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[6]
Slack : 20.634
Actual Width : 20.850
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|shiftreg[7]
Slack : 20.637
Actual Width : 20.821
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Slack : 20.638
Actual Width : 20.822
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Slack : 20.638
Actual Width : 20.822
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Slack : 20.638
Actual Width : 20.822
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Slack : 20.638
Actual Width : 20.822
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Slack : 20.638
Actual Width : 20.822
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Slack : 20.638
Actual Width : 20.822
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Slack : 20.639
Actual Width : 20.823
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Slack : 20.639
Actual Width : 20.823
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Slack : 20.639
Actual Width : 20.823
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Slack : 20.639
Actual Width : 20.823
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Slack : 20.639
Actual Width : 20.823
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Slack : 20.639
Actual Width : 20.823
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Slack : 20.639
Actual Width : 20.823
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Slack : 20.645
Actual Width : 20.829
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Slack : 20.648
Actual Width : 20.832
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Slack : 20.648
Actual Width : 20.832
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Slack : 20.648
Actual Width : 20.832
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Slack : 20.648
Actual Width : 20.832
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Slack : 20.648
Actual Width : 20.832
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Slack : 20.653
Actual Width : 20.869
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[0]
Slack : 20.653
Actual Width : 20.869
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[1]
Slack : 20.653
Actual Width : 20.869
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[2]
Slack : 20.653
Actual Width : 20.869
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[3]
Slack : 20.653
Actual Width : 20.869
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|thisbyte[4]
Slack : 20.655
Actual Width : 20.871
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|shiftreg[16]
Slack : 20.661
Actual Width : 20.877
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Ack
Slack : 20.661
Actual Width : 20.877
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|state.Stop
Slack : 20.661
Actual Width : 20.877
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrclk_r~_Duplicate_2
Slack : 20.661
Actual Width : 20.877
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[7]
Slack : 20.661
Actual Width : 20.877
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[8]
Slack : 20.661
Actual Width : 20.877
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[9]
Slack : 20.661
Actual Width : 20.877
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|mclk_r~_Duplicate_1
Slack : 20.662
Actual Width : 20.878
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[1]
Slack : 20.662
Actual Width : 20.878
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[2]
Slack : 20.662
Actual Width : 20.878
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[3]
Slack : 20.662
Actual Width : 20.878
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[4]
Slack : 20.662
Actual Width : 20.878
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[5]
Slack : 20.662
Actual Width : 20.878
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2s_intf:i2s_intf_|lrdivider[6]
Slack : 20.663
Actual Width : 20.879
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[0]
Slack : 20.667
Actual Width : 20.851
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[1]
Slack : 20.667
Actual Width : 20.851
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbit[2]
Slack : 20.667
Actual Width : 20.851
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[0]
Slack : 20.667
Actual Width : 20.851
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|nbyte[1]
Slack : 20.667
Actual Width : 20.851
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Clock Edge : Rise
Target : ula:ula_|i2c_loader:i2c_loader_|phase[0]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'ula_|pll_|altpll_component|auto_generated|pll1|clk[1]' ;
+--------------------------------------------------------------------------------+
Slack : 35.535
Actual Width : 35.719
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|clk_cpu
Slack : 35.535
Actual Width : 35.719
Required Width : 0.184
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|counter[0]
Slack : 35.552
Actual Width : 35.768
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|clk_cpu
Slack : 35.552
Actual Width : 35.768
Required Width : 0.216
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|counter[0]
Slack : 35.715
Actual Width : 35.715
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|clk_cpu|clk
Slack : 35.715
Actual Width : 35.715
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|counter[0]|clk
Slack : 35.739
Actual Width : 35.739
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|inclk[0]
Slack : 35.739
Actual Width : 35.739
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|outclk
Slack : 35.749
Actual Width : 35.749
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|inclk[0]
Slack : 35.749
Actual Width : 35.749
Required Width : 0.000
Type : Low Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|pll_|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl|outclk
Slack : 35.774
Actual Width : 35.774
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|clk_cpu|clk
Slack : 35.774
Actual Width : 35.774
Required Width : 0.000
Type : High Pulse Width
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula_|clocks_|counter[0]|clk
Slack : 69.489
Actual Width : 71.489
Required Width : 2.000
Type : Min Period
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|clk_cpu
Slack : 69.489
Actual Width : 71.489
Required Width : 2.000
Type : Min Period
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Clock Edge : Rise
Target : ula:ula_|clocks:clocks_|counter[0]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Setup Times ;
+--------------------------------------------------------------------------------+
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : 0.855
Fall : 1.653
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : 2.034
Fall : 2.803
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : SW[*]
Clock Port : CLOCK_50
Rise : 0.624
Fall : 1.147
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : SW[2]
Clock Port : CLOCK_50
Rise : 0.624
Fall : 1.147
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : AUD_ADCDAT
Clock Port : CLOCK_50
Rise : 0.918
Fall : 1.514
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 1.571
Fall : 2.179
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Hold Times ;
+--------------------------------------------------------------------------------+
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : -0.631
Fall : -1.422
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : -1.454
Fall : -2.187
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : SW[*]
Clock Port : CLOCK_50
Rise : -0.259
Fall : -0.788
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : SW[2]
Clock Port : CLOCK_50
Rise : -0.259
Fall : -0.788
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : AUD_ADCDAT
Clock Port : CLOCK_50
Rise : -0.566
Fall : -1.152
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : -0.730
Fall : -1.282
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 5.707
Fall : 5.789
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 5.633
Fall : 5.747
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 5.550
Fall : 5.607
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 5.707
Fall : 5.789
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 5.683
Fall : 5.753
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 5.541
Fall : 5.625
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 5.535
Fall : 5.610
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 5.680
Fall : 5.780
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 5.303
Fall : 5.400
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 4.600
Fall : 4.687
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 4.578
Fall : 4.687
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 4.320
Fall : 4.402
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 4.317
Fall : 4.434
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 4.448
Fall : 4.667
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 4.246
Fall : 4.330
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 4.600
Fall : 4.675
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 4.539
Fall : 4.640
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 4.508
Fall : 4.602
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[*]
Clock Port : CLOCK_50
Rise : 5.245
Fall : 4.941
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[0]
Clock Port : CLOCK_50
Rise : 5.245
Fall : 4.941
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[1]
Clock Port : CLOCK_50
Rise : 3.747
Fall : 3.799
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[2]
Clock Port : CLOCK_50
Rise : 3.833
Fall : 3.780
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[3]
Clock Port : CLOCK_50
Rise : 3.893
Fall : 3.863
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[*]
Clock Port : CLOCK_50
Rise : 3.942
Fall : 3.968
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[0]
Clock Port : CLOCK_50
Rise : 3.813
Fall : 3.787
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[1]
Clock Port : CLOCK_50
Rise : 3.892
Fall : 3.968
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[2]
Clock Port : CLOCK_50
Rise : 3.942
Fall : 3.931
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[3]
Clock Port : CLOCK_50
Rise : 3.928
Fall : 3.917
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_HS
Clock Port : CLOCK_50
Rise : 1.713
Fall : 1.658
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[*]
Clock Port : CLOCK_50
Rise : 4.204
Fall : 4.367
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[0]
Clock Port : CLOCK_50
Rise : 4.144
Fall : 4.181
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[1]
Clock Port : CLOCK_50
Rise : 4.204
Fall : 4.367
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[2]
Clock Port : CLOCK_50
Rise : 3.660
Fall : 3.615
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[3]
Clock Port : CLOCK_50
Rise : 3.950
Fall : 3.945
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_VS
Clock Port : CLOCK_50
Rise : 1.712
Fall : 1.657
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCLRCK
Clock Port : CLOCK_50
Rise : 1.709
Fall : 1.654
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_BCLK
Clock Port : CLOCK_50
Rise : 1.708
Fall : 1.653
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACDAT
Clock Port : CLOCK_50
Rise : 1.713
Fall : 1.658
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACLRCK
Clock Port : CLOCK_50
Rise : 3.245
Fall : 2.951
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_XCK
Clock Port : CLOCK_50
Rise : 1.711
Fall : 1.656
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SCLK
Clock Port : CLOCK_50
Rise : 1.755
Fall : 1.683
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 1.758
Fall : 1.686
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 4.814
Fall : 4.889
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 4.986
Fall : 5.076
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 4.899
Fall : 4.961
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 4.915
Fall : 5.000
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 4.914
Fall : 4.986
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 4.819
Fall : 4.894
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 4.961
Fall : 5.038
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 5.139
Fall : 5.242
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 4.814
Fall : 4.889
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 3.215
Fall : 3.294
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 3.794
Fall : 3.884
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 3.590
Fall : 3.708
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 3.672
Fall : 3.764
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 3.215
Fall : 3.294
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 3.409
Fall : 3.498
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 3.716
Fall : 3.793
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 3.823
Fall : 3.933
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 3.656
Fall : 3.803
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[*]
Clock Port : CLOCK_50
Rise : 2.186
Fall : 2.187
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[0]
Clock Port : CLOCK_50
Rise : 3.738
Fall : 3.497
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[1]
Clock Port : CLOCK_50
Rise : 2.186
Fall : 2.187
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[2]
Clock Port : CLOCK_50
Rise : 2.321
Fall : 2.331
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[3]
Clock Port : CLOCK_50
Rise : 2.379
Fall : 2.411
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[*]
Clock Port : CLOCK_50
Rise : 2.209
Fall : 2.213
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[0]
Clock Port : CLOCK_50
Rise : 2.214
Fall : 2.222
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[1]
Clock Port : CLOCK_50
Rise : 2.209
Fall : 2.213
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[2]
Clock Port : CLOCK_50
Rise : 2.338
Fall : 2.360
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[3]
Clock Port : CLOCK_50
Rise : 2.325
Fall : 2.347
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_HS
Clock Port : CLOCK_50
Rise : 1.471
Fall : 1.416
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[*]
Clock Port : CLOCK_50
Rise : 2.066
Fall : 2.055
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[0]
Clock Port : CLOCK_50
Rise : 2.531
Fall : 2.598
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[1]
Clock Port : CLOCK_50
Rise : 2.429
Fall : 2.479
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[2]
Clock Port : CLOCK_50
Rise : 2.066
Fall : 2.055
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[3]
Clock Port : CLOCK_50
Rise : 2.345
Fall : 2.372
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_VS
Clock Port : CLOCK_50
Rise : 1.469
Fall : 1.414
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCLRCK
Clock Port : CLOCK_50
Rise : 1.467
Fall : 1.412
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_BCLK
Clock Port : CLOCK_50
Rise : 1.465
Fall : 1.410
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACDAT
Clock Port : CLOCK_50
Rise : 1.470
Fall : 1.415
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACLRCK
Clock Port : CLOCK_50
Rise : 3.002
Fall : 2.708
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_XCK
Clock Port : CLOCK_50
Rise : 1.469
Fall : 1.414
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SCLK
Clock Port : CLOCK_50
Rise : 1.513
Fall : 1.442
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 1.516
Fall : 1.445
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Propagation Delay ;
+--------------------------------------------------------------------------------+
Input Port : SW[1]
Output Port : LED[0]
RR : 2.827
RF :
FR :
FF : 3.187
Input Port : SW[2]
Output Port : LED[2]
RR : 2.437
RF :
FR :
FF : 2.866
Input Port : raw_loader_in
Output Port : GPIO_1[22]
RR : 3.882
RF :
FR :
FF : 4.619
Input Port : raw_loader_in
Output Port : LED[3]
RR : 2.598
RF :
FR :
FF : 3.199
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Propagation Delay ;
+--------------------------------------------------------------------------------+
Input Port : SW[1]
Output Port : LED[0]
RR : 2.741
RF :
FR :
FF : 3.106
Input Port : SW[2]
Output Port : LED[2]
RR : 2.366
RF :
FR :
FF : 2.798
Input Port : raw_loader_in
Output Port : GPIO_1[22]
RR : 3.748
RF :
FR :
FF : 4.479
Input Port : raw_loader_in
Output Port : LED[3]
RR : 2.517
RF :
FR :
FF : 3.114
+--------------------------------------------------------------------------------+
---------------------------------------------
; Fast 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.
+--------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary ;
+--------------------------------------------------------------------------------+
Clock : Worst-case Slack
Setup : -18.425
Hold : 0.112
Recovery : -6.263
Removal : 2.503
Minimum Pulse Width : 9.208
Clock : CLOCK_50
Setup : -18.425
Hold : 0.112
Recovery : N/A
Removal : N/A
Minimum Pulse Width : 9.208
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Setup : -6.923
Hold : 0.186
Recovery : N/A
Removal : N/A
Minimum Pulse Width : 19.601
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Setup : -2.915
Hold : 0.177
Recovery : N/A
Removal : N/A
Minimum Pulse Width : 35.491
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Setup : -4.745
Hold : 0.178
Recovery : -6.263
Removal : 2.503
Minimum Pulse Width : 20.590
Clock : Design-wide TNS
Setup : -863.503
Hold : 0.0
Recovery : -464.84
Removal : 0.0
Minimum Pulse Width : 0.0
Clock : CLOCK_50
Setup : -546.891
Hold : 0.000
Recovery : N/A
Removal : N/A
Minimum Pulse Width : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Setup : -271.506
Hold : 0.000
Recovery : N/A
Removal : N/A
Minimum Pulse Width : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Setup : -2.915
Hold : 0.000
Recovery : N/A
Removal : N/A
Minimum Pulse Width : 0.000
Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Setup : -42.191
Hold : 0.000
Recovery : -464.840
Removal : 0.000
Minimum Pulse Width : 0.000
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Setup Times ;
+--------------------------------------------------------------------------------+
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : 1.693
Fall : 2.046
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : 3.641
Fall : 3.954
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : SW[*]
Clock Port : CLOCK_50
Rise : 1.010
Fall : 1.278
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : SW[2]
Clock Port : CLOCK_50
Rise : 1.010
Fall : 1.278
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : AUD_ADCDAT
Clock Port : CLOCK_50
Rise : 1.624
Fall : 1.864
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 2.876
Fall : 3.109
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Hold Times ;
+--------------------------------------------------------------------------------+
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : -0.631
Fall : -1.422
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : raw_loader_in
Clock Port : CLOCK_50
Rise : -1.454
Fall : -2.187
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : SW[*]
Clock Port : CLOCK_50
Rise : -0.259
Fall : -0.593
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : SW[2]
Clock Port : CLOCK_50
Rise : -0.259
Fall : -0.593
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Data Port : AUD_ADCDAT
Clock Port : CLOCK_50
Rise : -0.566
Fall : -1.108
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : -0.730
Fall : -1.282
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 9.798
Fall : 9.748
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 9.705
Fall : 9.748
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 9.555
Fall : 9.493
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 9.798
Fall : 9.738
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 9.757
Fall : 9.715
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 9.549
Fall : 9.489
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 9.522
Fall : 9.546
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 9.748
Fall : 9.728
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 9.098
Fall : 9.177
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 7.976
Fall : 8.000
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 7.875
Fall : 7.912
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 7.501
Fall : 7.536
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 7.551
Fall : 7.531
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 7.805
Fall : 7.843
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 7.428
Fall : 7.368
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 7.976
Fall : 8.000
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 7.923
Fall : 7.903
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 7.748
Fall : 7.835
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[*]
Clock Port : CLOCK_50
Rise : 8.499
Fall : 8.077
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[0]
Clock Port : CLOCK_50
Rise : 8.499
Fall : 8.077
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[1]
Clock Port : CLOCK_50
Rise : 6.645
Fall : 6.554
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[2]
Clock Port : CLOCK_50
Rise : 6.682
Fall : 6.538
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[3]
Clock Port : CLOCK_50
Rise : 6.778
Fall : 6.679
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[*]
Clock Port : CLOCK_50
Rise : 6.936
Fall : 6.847
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[0]
Clock Port : CLOCK_50
Rise : 6.658
Fall : 6.538
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[1]
Clock Port : CLOCK_50
Rise : 6.936
Fall : 6.847
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[2]
Clock Port : CLOCK_50
Rise : 6.905
Fall : 6.787
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[3]
Clock Port : CLOCK_50
Rise : 6.881
Fall : 6.765
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_HS
Clock Port : CLOCK_50
Rise : 2.863
Fall : 2.776
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[*]
Clock Port : CLOCK_50
Rise : 7.442
Fall : 7.459
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[0]
Clock Port : CLOCK_50
Rise : 7.239
Fall : 7.169
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[1]
Clock Port : CLOCK_50
Rise : 7.442
Fall : 7.459
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[2]
Clock Port : CLOCK_50
Rise : 6.381
Fall : 6.270
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[3]
Clock Port : CLOCK_50
Rise : 6.900
Fall : 6.786
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_VS
Clock Port : CLOCK_50
Rise : 2.861
Fall : 2.774
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCLRCK
Clock Port : CLOCK_50
Rise : 2.859
Fall : 2.772
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_BCLK
Clock Port : CLOCK_50
Rise : 2.858
Fall : 2.771
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACDAT
Clock Port : CLOCK_50
Rise : 2.862
Fall : 2.775
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACLRCK
Clock Port : CLOCK_50
Rise : 4.881
Fall : 4.517
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_XCK
Clock Port : CLOCK_50
Rise : 2.860
Fall : 2.773
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SCLK
Clock Port : CLOCK_50
Rise : 2.951
Fall : 2.866
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 2.953
Fall : 2.868
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Clock to Output Times ;
+--------------------------------------------------------------------------------+
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 4.814
Fall : 4.889
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 4.986
Fall : 5.076
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 4.899
Fall : 4.961
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 4.915
Fall : 5.000
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 4.914
Fall : 4.986
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 4.819
Fall : 4.894
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 4.961
Fall : 5.038
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 5.139
Fall : 5.242
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 4.814
Fall : 4.889
Clock Edge : Rise
Clock Reference : CLOCK_50
Data Port : GPIO_1[*]
Clock Port : CLOCK_50
Rise : 3.215
Fall : 3.294
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[16]
Clock Port : CLOCK_50
Rise : 3.794
Fall : 3.884
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[17]
Clock Port : CLOCK_50
Rise : 3.590
Fall : 3.708
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[18]
Clock Port : CLOCK_50
Rise : 3.672
Fall : 3.764
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[19]
Clock Port : CLOCK_50
Rise : 3.215
Fall : 3.294
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[20]
Clock Port : CLOCK_50
Rise : 3.409
Fall : 3.498
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[21]
Clock Port : CLOCK_50
Rise : 3.716
Fall : 3.793
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[22]
Clock Port : CLOCK_50
Rise : 3.823
Fall : 3.933
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : GPIO_1[23]
Clock Port : CLOCK_50
Rise : 3.656
Fall : 3.803
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[*]
Clock Port : CLOCK_50
Rise : 2.186
Fall : 2.187
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[0]
Clock Port : CLOCK_50
Rise : 3.738
Fall : 3.497
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[1]
Clock Port : CLOCK_50
Rise : 2.186
Fall : 2.187
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[2]
Clock Port : CLOCK_50
Rise : 2.321
Fall : 2.331
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_B[3]
Clock Port : CLOCK_50
Rise : 2.379
Fall : 2.411
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[*]
Clock Port : CLOCK_50
Rise : 2.209
Fall : 2.213
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[0]
Clock Port : CLOCK_50
Rise : 2.214
Fall : 2.222
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[1]
Clock Port : CLOCK_50
Rise : 2.209
Fall : 2.213
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[2]
Clock Port : CLOCK_50
Rise : 2.338
Fall : 2.360
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_G[3]
Clock Port : CLOCK_50
Rise : 2.325
Fall : 2.347
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_HS
Clock Port : CLOCK_50
Rise : 1.471
Fall : 1.416
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[*]
Clock Port : CLOCK_50
Rise : 2.066
Fall : 2.055
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[0]
Clock Port : CLOCK_50
Rise : 2.531
Fall : 2.598
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[1]
Clock Port : CLOCK_50
Rise : 2.429
Fall : 2.479
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[2]
Clock Port : CLOCK_50
Rise : 2.066
Fall : 2.055
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_R[3]
Clock Port : CLOCK_50
Rise : 2.345
Fall : 2.372
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : VGA_VS
Clock Port : CLOCK_50
Rise : 1.469
Fall : 1.414
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Data Port : AUD_ADCLRCK
Clock Port : CLOCK_50
Rise : 1.467
Fall : 1.412
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_BCLK
Clock Port : CLOCK_50
Rise : 1.465
Fall : 1.410
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACDAT
Clock Port : CLOCK_50
Rise : 1.470
Fall : 1.415
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_DACLRCK
Clock Port : CLOCK_50
Rise : 3.002
Fall : 2.708
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : AUD_XCK
Clock Port : CLOCK_50
Rise : 1.469
Fall : 1.414
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SCLK
Clock Port : CLOCK_50
Rise : 1.513
Fall : 1.442
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Data Port : I2C_SDAT
Clock Port : CLOCK_50
Rise : 1.516
Fall : 1.445
Clock Edge : Rise
Clock Reference : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Propagation Delay ;
+--------------------------------------------------------------------------------+
Input Port : SW[1]
Output Port : LED[0]
RR : 4.640
RF :
FR :
FF : 4.702
Input Port : SW[2]
Output Port : LED[2]
RR : 4.044
RF :
FR :
FF : 4.195
Input Port : raw_loader_in
Output Port : GPIO_1[22]
RR : 6.764
RF :
FR :
FF : 7.009
Input Port : raw_loader_in
Output Port : LED[3]
RR : 4.399
RF :
FR :
FF : 4.625
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Minimum Propagation Delay ;
+--------------------------------------------------------------------------------+
Input Port : SW[1]
Output Port : LED[0]
RR : 2.741
RF :
FR :
FF : 3.106
Input Port : SW[2]
Output Port : LED[2]
RR : 2.366
RF :
FR :
FF : 2.798
Input Port : raw_loader_in
Output Port : GPIO_1[22]
RR : 3.748
RF :
FR :
FF : 4.479
Input Port : raw_loader_in
Output Port : LED[3]
RR : 2.517
RF :
FR :
FF : 3.114
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Board Trace Model Assignments ;
+--------------------------------------------------------------------------------+
Pin : LED[0]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : LED[1]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : LED[2]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : LED[3]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : LED[4]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : LED[5]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : LED[6]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : LED[7]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : AUD_XCK
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : AUD_ADCLRCK
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : AUD_DACLRCK
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : AUD_BCLK
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : AUD_DACDAT
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_R[0]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_R[1]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_R[2]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_R[3]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_G[0]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_G[1]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_G[2]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_G[3]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_B[0]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_B[1]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_B[2]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_B[3]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_HS
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : VGA_VS
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[0]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[1]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[2]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[3]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[4]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[5]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[6]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[7]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[8]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[9]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[10]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[11]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[12]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[13]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[14]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[15]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[16]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[17]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[18]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[19]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[20]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[21]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[22]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[23]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[24]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[25]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[26]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[27]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[28]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[29]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[30]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[31]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[32]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : GPIO_1[33]
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : buzzer_out
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : I2C_SCLK
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : I2C_SDAT
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : ~ALTERA_DCLK~
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
Pin : ~ALTERA_nCEO~
I/O Standard : 3.3-V LVTTL
Near Tline Length : 0 in
Near Tline L per Length : 0 H/in
Near Tline C per Length : 0 F/in
Near Series R : short
Near Differential R : -
Near Pull-up R : open
Near Pull-down R : open
Near C : open
Far Tline Length : 0 in
Far Tline L per Length : 0 H/in
Far Tline C per Length : 0 F/in
Far Series R : short
Far Pull-up R : open
Far Pull-down R : open
Far C : open
Termination Voltage : 0 V
Far Differential R : -
EBD File Name : n/a
EBD Signal Name : n/a
EBD Far-end : n/a
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Input Transition Times ;
+--------------------------------------------------------------------------------+
Pin : SW[0]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : SW[3]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : I2C_SCLK
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : I2C_SDAT
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : SW[1]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : SW[2]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : raw_loader_in
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : KEY[0]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : CLOCK_50
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : PS2_DAT
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : KEY[1]
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : PS2_CLK
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : AUD_ADCDAT
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : ~ALTERA_ASDO_DATA1~
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : ~ALTERA_FLASH_nCE_nCSO~
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
Pin : ~ALTERA_DATA0~
I/O Standard : 3.3-V LVTTL
10-90 Rise Time : 2640 ps
90-10 Fall Time : 2640 ps
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 0c Model) ;
+--------------------------------------------------------------------------------+
Pin : LED[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.09 V
Vol Min at FPGA Pin : -0.0119 V
Ringback Voltage on Rise at FPGA Pin : 0.277 V
Ringback Voltage on Fall at FPGA Pin : 0.297 V
10-90 Rise Time at FPGA Pin : 4.54e-09 s
90-10 Fall Time at FPGA Pin : 3.32e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.09 V
Vol Min at Far-end : -0.0119 V
Ringback Voltage on Rise at Far-end : 0.277 V
Ringback Voltage on Fall at Far-end : 0.297 V
10-90 Rise Time at Far-end : 4.54e-09 s
90-10 Fall Time at Far-end : 3.32e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.16 V
Vol Min at FPGA Pin : -0.11 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.22 V
10-90 Rise Time at FPGA Pin : 4.82e-10 s
90-10 Fall Time at FPGA Pin : 4.27e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.16 V
Vol Min at Far-end : -0.11 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.22 V
10-90 Rise Time at Far-end : 4.82e-10 s
90-10 Fall Time at Far-end : 4.27e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : LED[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.09 V
Vol Min at FPGA Pin : -0.0119 V
Ringback Voltage on Rise at FPGA Pin : 0.277 V
Ringback Voltage on Fall at FPGA Pin : 0.297 V
10-90 Rise Time at FPGA Pin : 4.54e-09 s
90-10 Fall Time at FPGA Pin : 3.32e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.09 V
Vol Min at Far-end : -0.0119 V
Ringback Voltage on Rise at Far-end : 0.277 V
Ringback Voltage on Fall at Far-end : 0.297 V
10-90 Rise Time at Far-end : 4.54e-09 s
90-10 Fall Time at Far-end : 3.32e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_XCK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_ADCLRCK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_DACLRCK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.09 V
Vol Min at FPGA Pin : -0.0123 V
Ringback Voltage on Rise at FPGA Pin : 0.281 V
Ringback Voltage on Fall at FPGA Pin : 0.305 V
10-90 Rise Time at FPGA Pin : 4.54e-09 s
90-10 Fall Time at FPGA Pin : 3.32e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.09 V
Vol Min at Far-end : -0.0123 V
Ringback Voltage on Rise at Far-end : 0.281 V
Ringback Voltage on Fall at Far-end : 0.305 V
10-90 Rise Time at Far-end : 4.54e-09 s
90-10 Fall Time at Far-end : 3.32e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_BCLK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_DACDAT
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_R[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_R[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_R[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_R[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_G[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_G[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_G[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_G[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_B[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.09 V
Vol Min at FPGA Pin : -0.0123 V
Ringback Voltage on Rise at FPGA Pin : 0.281 V
Ringback Voltage on Fall at FPGA Pin : 0.305 V
10-90 Rise Time at FPGA Pin : 4.54e-09 s
90-10 Fall Time at FPGA Pin : 3.32e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.09 V
Vol Min at Far-end : -0.0123 V
Ringback Voltage on Rise at Far-end : 0.281 V
Ringback Voltage on Fall at Far-end : 0.305 V
10-90 Rise Time at Far-end : 4.54e-09 s
90-10 Fall Time at Far-end : 3.32e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_B[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_B[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_B[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_HS
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_VS
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.16 V
Vol Min at FPGA Pin : -0.11 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.22 V
10-90 Rise Time at FPGA Pin : 4.82e-10 s
90-10 Fall Time at FPGA Pin : 4.27e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.16 V
Vol Min at Far-end : -0.11 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.22 V
10-90 Rise Time at Far-end : 4.82e-10 s
90-10 Fall Time at Far-end : 4.27e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[8]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[9]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[10]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.09 V
Vol Min at FPGA Pin : -0.0123 V
Ringback Voltage on Rise at FPGA Pin : 0.281 V
Ringback Voltage on Fall at FPGA Pin : 0.305 V
10-90 Rise Time at FPGA Pin : 4.54e-09 s
90-10 Fall Time at FPGA Pin : 3.32e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.09 V
Vol Min at Far-end : -0.0123 V
Ringback Voltage on Rise at Far-end : 0.281 V
Ringback Voltage on Fall at Far-end : 0.305 V
10-90 Rise Time at Far-end : 4.54e-09 s
90-10 Fall Time at Far-end : 3.32e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[11]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[12]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[13]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[14]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[15]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[16]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[17]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[18]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[19]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[20]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.16 V
Vol Min at FPGA Pin : -0.11 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.22 V
10-90 Rise Time at FPGA Pin : 4.82e-10 s
90-10 Fall Time at FPGA Pin : 4.27e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.16 V
Vol Min at Far-end : -0.11 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.22 V
10-90 Rise Time at Far-end : 4.82e-10 s
90-10 Fall Time at Far-end : 4.27e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[21]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[22]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[23]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[24]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[25]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[26]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.09 V
Vol Min at FPGA Pin : -0.0119 V
Ringback Voltage on Rise at FPGA Pin : 0.277 V
Ringback Voltage on Fall at FPGA Pin : 0.297 V
10-90 Rise Time at FPGA Pin : 4.54e-09 s
90-10 Fall Time at FPGA Pin : 3.32e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.09 V
Vol Min at Far-end : -0.0119 V
Ringback Voltage on Rise at Far-end : 0.277 V
Ringback Voltage on Fall at Far-end : 0.297 V
10-90 Rise Time at Far-end : 4.54e-09 s
90-10 Fall Time at Far-end : 3.32e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[27]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.16 V
Vol Min at FPGA Pin : -0.11 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.22 V
10-90 Rise Time at FPGA Pin : 4.82e-10 s
90-10 Fall Time at FPGA Pin : 4.27e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.16 V
Vol Min at Far-end : -0.11 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.22 V
10-90 Rise Time at Far-end : 4.82e-10 s
90-10 Fall Time at Far-end : 4.27e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[28]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[29]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[30]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[31]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[32]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[33]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : buzzer_out
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.24e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.115 V
Ringback Voltage on Rise at FPGA Pin : 0.31 V
Ringback Voltage on Fall at FPGA Pin : 0.241 V
10-90 Rise Time at FPGA Pin : 5.06e-10 s
90-10 Fall Time at FPGA Pin : 4.37e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.24e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.115 V
Ringback Voltage on Rise at Far-end : 0.31 V
Ringback Voltage on Fall at Far-end : 0.241 V
10-90 Rise Time at Far-end : 5.06e-10 s
90-10 Fall Time at Far-end : 4.37e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : I2C_SCLK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : I2C_SDAT
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : ~ALTERA_DCLK~
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 8.05e-09 V
Voh Max at FPGA Pin : 3.21 V
Vol Min at FPGA Pin : -0.181 V
Ringback Voltage on Rise at FPGA Pin : 0.16 V
Ringback Voltage on Fall at FPGA Pin : 0.253 V
10-90 Rise Time at FPGA Pin : 2.77e-10 s
90-10 Fall Time at FPGA Pin : 2.32e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : Yes
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 8.05e-09 V
Voh Max at Far-end : 3.21 V
Vol Min at Far-end : -0.181 V
Ringback Voltage on Rise at Far-end : 0.16 V
Ringback Voltage on Fall at Far-end : 0.253 V
10-90 Rise Time at Far-end : 2.77e-10 s
90-10 Fall Time at Far-end : 2.32e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : Yes
Pin : ~ALTERA_nCEO~
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.54e-08 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.074 V
Ringback Voltage on Rise at FPGA Pin : 0.343 V
Ringback Voltage on Fall at FPGA Pin : 0.194 V
10-90 Rise Time at FPGA Pin : 7.35e-10 s
90-10 Fall Time at FPGA Pin : 6.36e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.54e-08 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.074 V
Ringback Voltage on Rise at Far-end : 0.343 V
Ringback Voltage on Fall at Far-end : 0.194 V
10-90 Rise Time at Far-end : 7.35e-10 s
90-10 Fall Time at Far-end : 6.36e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 85c Model) ;
+--------------------------------------------------------------------------------+
Pin : LED[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : LED[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : LED[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : LED[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : LED[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : LED[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.08 V
Vol Min at FPGA Pin : -0.00666 V
Ringback Voltage on Rise at FPGA Pin : 0.298 V
Ringback Voltage on Fall at FPGA Pin : 0.277 V
10-90 Rise Time at FPGA Pin : 5.29e-09 s
90-10 Fall Time at FPGA Pin : 4.2e-09 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.08 V
Vol Min at Far-end : -0.00666 V
Ringback Voltage on Rise at Far-end : 0.298 V
Ringback Voltage on Fall at Far-end : 0.277 V
10-90 Rise Time at Far-end : 5.29e-09 s
90-10 Fall Time at Far-end : 4.2e-09 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : LED[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.13 V
Vol Min at FPGA Pin : -0.0781 V
Ringback Voltage on Rise at FPGA Pin : 0.202 V
Ringback Voltage on Fall at FPGA Pin : 0.359 V
10-90 Rise Time at FPGA Pin : 6.54e-10 s
90-10 Fall Time at FPGA Pin : 5e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.13 V
Vol Min at Far-end : -0.0781 V
Ringback Voltage on Rise at Far-end : 0.202 V
Ringback Voltage on Fall at Far-end : 0.359 V
10-90 Rise Time at Far-end : 6.54e-10 s
90-10 Fall Time at Far-end : 5e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.08 V
Vol Min at FPGA Pin : -0.00666 V
Ringback Voltage on Rise at FPGA Pin : 0.298 V
Ringback Voltage on Fall at FPGA Pin : 0.277 V
10-90 Rise Time at FPGA Pin : 5.29e-09 s
90-10 Fall Time at FPGA Pin : 4.2e-09 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.08 V
Vol Min at Far-end : -0.00666 V
Ringback Voltage on Rise at Far-end : 0.298 V
Ringback Voltage on Fall at Far-end : 0.277 V
10-90 Rise Time at Far-end : 5.29e-09 s
90-10 Fall Time at Far-end : 4.2e-09 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : AUD_XCK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : AUD_ADCLRCK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : AUD_DACLRCK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.08 V
Vol Min at FPGA Pin : -0.00675 V
Ringback Voltage on Rise at FPGA Pin : 0.232 V
Ringback Voltage on Fall at FPGA Pin : 0.283 V
10-90 Rise Time at FPGA Pin : 5.31e-09 s
90-10 Fall Time at FPGA Pin : 4.2e-09 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.08 V
Vol Min at Far-end : -0.00675 V
Ringback Voltage on Rise at Far-end : 0.232 V
Ringback Voltage on Fall at Far-end : 0.283 V
10-90 Rise Time at Far-end : 5.31e-09 s
90-10 Fall Time at Far-end : 4.2e-09 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : AUD_BCLK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : AUD_DACDAT
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_R[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_R[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_R[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_R[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_G[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_G[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_G[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_G[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_B[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.08 V
Vol Min at FPGA Pin : -0.00675 V
Ringback Voltage on Rise at FPGA Pin : 0.232 V
Ringback Voltage on Fall at FPGA Pin : 0.283 V
10-90 Rise Time at FPGA Pin : 5.31e-09 s
90-10 Fall Time at FPGA Pin : 4.2e-09 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.08 V
Vol Min at Far-end : -0.00675 V
Ringback Voltage on Rise at Far-end : 0.232 V
Ringback Voltage on Fall at Far-end : 0.283 V
10-90 Rise Time at Far-end : 5.31e-09 s
90-10 Fall Time at Far-end : 4.2e-09 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_B[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_B[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_B[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_HS
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : VGA_VS
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.13 V
Vol Min at FPGA Pin : -0.0781 V
Ringback Voltage on Rise at FPGA Pin : 0.202 V
Ringback Voltage on Fall at FPGA Pin : 0.359 V
10-90 Rise Time at FPGA Pin : 6.54e-10 s
90-10 Fall Time at FPGA Pin : 5e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.13 V
Vol Min at Far-end : -0.0781 V
Ringback Voltage on Rise at Far-end : 0.202 V
Ringback Voltage on Fall at Far-end : 0.359 V
10-90 Rise Time at Far-end : 6.54e-10 s
90-10 Fall Time at Far-end : 5e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[8]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[9]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[10]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.08 V
Vol Min at FPGA Pin : -0.00675 V
Ringback Voltage on Rise at FPGA Pin : 0.232 V
Ringback Voltage on Fall at FPGA Pin : 0.283 V
10-90 Rise Time at FPGA Pin : 5.31e-09 s
90-10 Fall Time at FPGA Pin : 4.2e-09 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.08 V
Vol Min at Far-end : -0.00675 V
Ringback Voltage on Rise at Far-end : 0.232 V
Ringback Voltage on Fall at Far-end : 0.283 V
10-90 Rise Time at Far-end : 5.31e-09 s
90-10 Fall Time at Far-end : 4.2e-09 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[11]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[12]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[13]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[14]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[15]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[16]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[17]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[18]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[19]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[20]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.13 V
Vol Min at FPGA Pin : -0.0781 V
Ringback Voltage on Rise at FPGA Pin : 0.202 V
Ringback Voltage on Fall at FPGA Pin : 0.359 V
10-90 Rise Time at FPGA Pin : 6.54e-10 s
90-10 Fall Time at FPGA Pin : 5e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.13 V
Vol Min at Far-end : -0.0781 V
Ringback Voltage on Rise at Far-end : 0.202 V
Ringback Voltage on Fall at Far-end : 0.359 V
10-90 Rise Time at Far-end : 6.54e-10 s
90-10 Fall Time at Far-end : 5e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[21]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[22]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[23]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[24]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[25]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[26]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.08 V
Vol Min at FPGA Pin : -0.00666 V
Ringback Voltage on Rise at FPGA Pin : 0.298 V
Ringback Voltage on Fall at FPGA Pin : 0.277 V
10-90 Rise Time at FPGA Pin : 5.29e-09 s
90-10 Fall Time at FPGA Pin : 4.2e-09 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.08 V
Vol Min at Far-end : -0.00666 V
Ringback Voltage on Rise at Far-end : 0.298 V
Ringback Voltage on Fall at Far-end : 0.277 V
10-90 Rise Time at Far-end : 5.29e-09 s
90-10 Fall Time at Far-end : 4.2e-09 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[27]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.13 V
Vol Min at FPGA Pin : -0.0781 V
Ringback Voltage on Rise at FPGA Pin : 0.202 V
Ringback Voltage on Fall at FPGA Pin : 0.359 V
10-90 Rise Time at FPGA Pin : 6.54e-10 s
90-10 Fall Time at FPGA Pin : 5e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.13 V
Vol Min at Far-end : -0.0781 V
Ringback Voltage on Rise at Far-end : 0.202 V
Ringback Voltage on Fall at Far-end : 0.359 V
10-90 Rise Time at Far-end : 6.54e-10 s
90-10 Fall Time at Far-end : 5e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[28]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[29]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[30]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[31]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[32]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : GPIO_1[33]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : buzzer_out
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2.99e-06 V
Voh Max at FPGA Pin : 3.11 V
Vol Min at FPGA Pin : -0.0717 V
Ringback Voltage on Rise at FPGA Pin : 0.209 V
Ringback Voltage on Fall at FPGA Pin : 0.168 V
10-90 Rise Time at FPGA Pin : 6.66e-10 s
90-10 Fall Time at FPGA Pin : 6.19e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2.99e-06 V
Voh Max at Far-end : 3.11 V
Vol Min at Far-end : -0.0717 V
Ringback Voltage on Rise at Far-end : 0.209 V
Ringback Voltage on Fall at Far-end : 0.168 V
10-90 Rise Time at Far-end : 6.66e-10 s
90-10 Fall Time at Far-end : 6.19e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : I2C_SCLK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : I2C_SDAT
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : ~ALTERA_DCLK~
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 1.02e-06 V
Voh Max at FPGA Pin : 3.14 V
Vol Min at FPGA Pin : -0.124 V
Ringback Voltage on Rise at FPGA Pin : 0.134 V
Ringback Voltage on Fall at FPGA Pin : 0.323 V
10-90 Rise Time at FPGA Pin : 3.02e-10 s
90-10 Fall Time at FPGA Pin : 2.85e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 1.02e-06 V
Voh Max at Far-end : 3.14 V
Vol Min at Far-end : -0.124 V
Ringback Voltage on Rise at Far-end : 0.134 V
Ringback Voltage on Fall at Far-end : 0.323 V
10-90 Rise Time at Far-end : 3.02e-10 s
90-10 Fall Time at Far-end : 2.85e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
Pin : ~ALTERA_nCEO~
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.08 V
Steady State Vol at FPGA Pin : 2e-06 V
Voh Max at FPGA Pin : 3.12 V
Vol Min at FPGA Pin : -0.0547 V
Ringback Voltage on Rise at FPGA Pin : 0.276 V
Ringback Voltage on Fall at FPGA Pin : 0.181 V
10-90 Rise Time at FPGA Pin : 9.17e-10 s
90-10 Fall Time at FPGA Pin : 8.31e-10 s
Monotonic Rise at FPGA Pin : Yes
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.08 V
Steady State Vol at Far-end : 2e-06 V
Voh Max at Far-end : 3.12 V
Vol Min at Far-end : -0.0547 V
Ringback Voltage on Rise at Far-end : 0.276 V
Ringback Voltage on Fall at Far-end : 0.181 V
10-90 Rise Time at Far-end : 9.17e-10 s
90-10 Fall Time at Far-end : 8.31e-10 s
Monotonic Rise at Far-end : Yes
Monotonic Fall at Far-end : No
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 1200mv 0c Model) ;
+--------------------------------------------------------------------------------+
Pin : LED[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.48 V
Vol Min at FPGA Pin : -0.0162 V
Ringback Voltage on Rise at FPGA Pin : 0.354 V
Ringback Voltage on Fall at FPGA Pin : 0.317 V
10-90 Rise Time at FPGA Pin : 3.88e-09 s
90-10 Fall Time at FPGA Pin : 3.06e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.48 V
Vol Min at Far-end : -0.0162 V
Ringback Voltage on Rise at Far-end : 0.354 V
Ringback Voltage on Fall at Far-end : 0.317 V
10-90 Rise Time at Far-end : 3.88e-09 s
90-10 Fall Time at Far-end : 3.06e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.6 V
Vol Min at FPGA Pin : -0.127 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.21 V
10-90 Rise Time at FPGA Pin : 4.55e-10 s
90-10 Fall Time at FPGA Pin : 4.11e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.6 V
Vol Min at Far-end : -0.127 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.21 V
10-90 Rise Time at Far-end : 4.55e-10 s
90-10 Fall Time at Far-end : 4.11e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : LED[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.48 V
Vol Min at FPGA Pin : -0.0162 V
Ringback Voltage on Rise at FPGA Pin : 0.354 V
Ringback Voltage on Fall at FPGA Pin : 0.317 V
10-90 Rise Time at FPGA Pin : 3.88e-09 s
90-10 Fall Time at FPGA Pin : 3.06e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.48 V
Vol Min at Far-end : -0.0162 V
Ringback Voltage on Rise at Far-end : 0.354 V
Ringback Voltage on Fall at Far-end : 0.317 V
10-90 Rise Time at Far-end : 3.88e-09 s
90-10 Fall Time at Far-end : 3.06e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_XCK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_ADCLRCK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_DACLRCK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.48 V
Vol Min at FPGA Pin : -0.0173 V
Ringback Voltage on Rise at FPGA Pin : 0.356 V
Ringback Voltage on Fall at FPGA Pin : 0.324 V
10-90 Rise Time at FPGA Pin : 3.89e-09 s
90-10 Fall Time at FPGA Pin : 3.06e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.48 V
Vol Min at Far-end : -0.0173 V
Ringback Voltage on Rise at Far-end : 0.356 V
Ringback Voltage on Fall at Far-end : 0.324 V
10-90 Rise Time at Far-end : 3.89e-09 s
90-10 Fall Time at Far-end : 3.06e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_BCLK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : AUD_DACDAT
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_R[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_R[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_R[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_R[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_G[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_G[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_G[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_G[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_B[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.48 V
Vol Min at FPGA Pin : -0.0173 V
Ringback Voltage on Rise at FPGA Pin : 0.356 V
Ringback Voltage on Fall at FPGA Pin : 0.324 V
10-90 Rise Time at FPGA Pin : 3.89e-09 s
90-10 Fall Time at FPGA Pin : 3.06e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.48 V
Vol Min at Far-end : -0.0173 V
Ringback Voltage on Rise at Far-end : 0.356 V
Ringback Voltage on Fall at Far-end : 0.324 V
10-90 Rise Time at Far-end : 3.89e-09 s
90-10 Fall Time at Far-end : 3.06e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_B[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_B[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_B[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_HS
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : VGA_VS
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[0]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.6 V
Vol Min at FPGA Pin : -0.127 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.21 V
10-90 Rise Time at FPGA Pin : 4.55e-10 s
90-10 Fall Time at FPGA Pin : 4.11e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.6 V
Vol Min at Far-end : -0.127 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.21 V
10-90 Rise Time at Far-end : 4.55e-10 s
90-10 Fall Time at Far-end : 4.11e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[1]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[2]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[3]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[4]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[5]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[6]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[7]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[8]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[9]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[10]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.48 V
Vol Min at FPGA Pin : -0.0173 V
Ringback Voltage on Rise at FPGA Pin : 0.356 V
Ringback Voltage on Fall at FPGA Pin : 0.324 V
10-90 Rise Time at FPGA Pin : 3.89e-09 s
90-10 Fall Time at FPGA Pin : 3.06e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.48 V
Vol Min at Far-end : -0.0173 V
Ringback Voltage on Rise at Far-end : 0.356 V
Ringback Voltage on Fall at Far-end : 0.324 V
10-90 Rise Time at Far-end : 3.89e-09 s
90-10 Fall Time at Far-end : 3.06e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[11]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[12]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[13]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[14]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[15]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[16]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[17]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[18]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[19]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[20]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.6 V
Vol Min at FPGA Pin : -0.127 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.21 V
10-90 Rise Time at FPGA Pin : 4.55e-10 s
90-10 Fall Time at FPGA Pin : 4.11e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.6 V
Vol Min at Far-end : -0.127 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.21 V
10-90 Rise Time at Far-end : 4.55e-10 s
90-10 Fall Time at Far-end : 4.11e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[21]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[22]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[23]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[24]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[25]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[26]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.48 V
Vol Min at FPGA Pin : -0.0162 V
Ringback Voltage on Rise at FPGA Pin : 0.354 V
Ringback Voltage on Fall at FPGA Pin : 0.317 V
10-90 Rise Time at FPGA Pin : 3.88e-09 s
90-10 Fall Time at FPGA Pin : 3.06e-09 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.48 V
Vol Min at Far-end : -0.0162 V
Ringback Voltage on Rise at Far-end : 0.354 V
Ringback Voltage on Fall at Far-end : 0.317 V
10-90 Rise Time at Far-end : 3.88e-09 s
90-10 Fall Time at Far-end : 3.06e-09 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[27]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.6 V
Vol Min at FPGA Pin : -0.127 V
Ringback Voltage on Rise at FPGA Pin : 0.302 V
Ringback Voltage on Fall at FPGA Pin : 0.21 V
10-90 Rise Time at FPGA Pin : 4.55e-10 s
90-10 Fall Time at FPGA Pin : 4.11e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.6 V
Vol Min at Far-end : -0.127 V
Ringback Voltage on Rise at Far-end : 0.302 V
Ringback Voltage on Fall at Far-end : 0.21 V
10-90 Rise Time at Far-end : 4.55e-10 s
90-10 Fall Time at Far-end : 4.11e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[28]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[29]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[30]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[31]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[32]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : GPIO_1[33]
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : buzzer_out
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.85e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.141 V
Ringback Voltage on Rise at FPGA Pin : 0.301 V
Ringback Voltage on Fall at FPGA Pin : 0.239 V
10-90 Rise Time at FPGA Pin : 4.61e-10 s
90-10 Fall Time at FPGA Pin : 4.2e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.85e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.141 V
Ringback Voltage on Rise at Far-end : 0.301 V
Ringback Voltage on Fall at Far-end : 0.239 V
10-90 Rise Time at Far-end : 4.61e-10 s
90-10 Fall Time at Far-end : 4.2e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : I2C_SCLK
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : I2C_SDAT
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
Pin : ~ALTERA_DCLK~
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 6.54e-08 V
Voh Max at FPGA Pin : 3.66 V
Vol Min at FPGA Pin : -0.258 V
Ringback Voltage on Rise at FPGA Pin : 0.41 V
Ringback Voltage on Fall at FPGA Pin : 0.318 V
10-90 Rise Time at FPGA Pin : 1.57e-10 s
90-10 Fall Time at FPGA Pin : 2.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : Yes
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 6.54e-08 V
Voh Max at Far-end : 3.66 V
Vol Min at Far-end : -0.258 V
Ringback Voltage on Rise at Far-end : 0.41 V
Ringback Voltage on Fall at Far-end : 0.318 V
10-90 Rise Time at Far-end : 1.57e-10 s
90-10 Fall Time at Far-end : 2.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : Yes
Pin : ~ALTERA_nCEO~
I/O Standard : 3.3-V LVTTL
Board Delay on Rise : 0 s
Board Delay on Fall : 0 s
Steady State Voh at FPGA Pin : 3.46 V
Steady State Vol at FPGA Pin : 1.25e-07 V
Voh Max at FPGA Pin : 3.57 V
Vol Min at FPGA Pin : -0.0855 V
Ringback Voltage on Rise at FPGA Pin : 0.315 V
Ringback Voltage on Fall at FPGA Pin : 0.175 V
10-90 Rise Time at FPGA Pin : 6.79e-10 s
90-10 Fall Time at FPGA Pin : 6.15e-10 s
Monotonic Rise at FPGA Pin : No
Monotonic Fall at FPGA Pin : No
Steady State Voh at Far-end : 3.46 V
Steady State Vol at Far-end : 1.25e-07 V
Voh Max at Far-end : 3.57 V
Vol Min at Far-end : -0.0855 V
Ringback Voltage on Rise at Far-end : 0.315 V
Ringback Voltage on Fall at Far-end : 0.175 V
10-90 Rise Time at Far-end : 6.79e-10 s
90-10 Fall Time at Far-end : 6.15e-10 s
Monotonic Rise at Far-end : No
Monotonic Fall at Far-end : No
+--------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------+
; Setup Transfers ;
+--------------------------------------------------------------------------------+
From Clock : CLOCK_50
To Clock : beep
RR Paths : false path
FR Paths : 0
RF Paths : false path
FF Paths : 0
From Clock : beep
To Clock : CLOCK_50
RR Paths : false path
FR Paths : false path
RF Paths : 0
FF Paths : 0
From Clock : CLOCK_50
To Clock : CLOCK_50
RR Paths : 106
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
To Clock : CLOCK_50
RR Paths : 1188
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
To Clock : CLOCK_50
RR Paths : 7
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : CLOCK_50
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
RR Paths : 120
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
RR Paths : 1154
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : CLOCK_50
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
RR Paths : 1
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
RR Paths : 3
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : CLOCK_50
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
RR Paths : 12
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
RR Paths : 1424
FR Paths : 180
RF Paths : 0
FF Paths : 21
+--------------------------------------------------------------------------------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+--------------------------------------------------------------------------------+
; Hold Transfers ;
+--------------------------------------------------------------------------------+
From Clock : CLOCK_50
To Clock : beep
RR Paths : false path
FR Paths : 0
RF Paths : false path
FF Paths : 0
From Clock : beep
To Clock : CLOCK_50
RR Paths : false path
FR Paths : false path
RF Paths : 0
FF Paths : 0
From Clock : CLOCK_50
To Clock : CLOCK_50
RR Paths : 106
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
To Clock : CLOCK_50
RR Paths : 1188
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
To Clock : CLOCK_50
RR Paths : 7
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : CLOCK_50
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
RR Paths : 120
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
RR Paths : 1154
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : CLOCK_50
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
RR Paths : 1
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
RR Paths : 3
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : CLOCK_50
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
RR Paths : 12
FR Paths : 0
RF Paths : 0
FF Paths : 0
From Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
RR Paths : 1424
FR Paths : 180
RF Paths : 0
FF Paths : 21
+--------------------------------------------------------------------------------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+--------------------------------------------------------------------------------+
; Recovery Transfers ;
+--------------------------------------------------------------------------------+
From Clock : CLOCK_50
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
RR Paths : 76
FR Paths : 0
RF Paths : 6
FF Paths : 0
+--------------------------------------------------------------------------------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+--------------------------------------------------------------------------------+
; Removal Transfers ;
+--------------------------------------------------------------------------------+
From Clock : CLOCK_50
To Clock : ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
RR Paths : 76
FR Paths : 0
RF Paths : 6
FF Paths : 0
+--------------------------------------------------------------------------------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design
---------------
; Report RSKM ;
---------------
No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+--------------------------------------------------------------------------------+
; Unconstrained Paths ;
+--------------------------------------------------------------------------------+
Property : Illegal Clocks
Setup : 0
Hold : 0
Property : Unconstrained Clocks
Setup : 2
Hold : 2
Property : Unconstrained Input Ports
Setup : 0
Hold : 0
Property : Unconstrained Input Port Paths
Setup : 0
Hold : 0
Property : Unconstrained Output Ports
Setup : 0
Hold : 0
Property : Unconstrained Output Port Paths
Setup : 0
Hold : 0
+--------------------------------------------------------------------------------+
+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
Info: Processing started: Sat Apr 2 15:53:37 2022
Info: Command: quartus_sta spectrum -c spectrum
Info: qsta_default_script.tcl version: #1
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (21077): Core supply voltage is 1.2V
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (332104): Reading SDC File: 'spectrum.sdc'
Warning (332174): Ignored filter at spectrum.sdc(12): KEY1 could not be matched with a port
Warning (332049): Ignored create_clock at spectrum.sdc(12): Argument <targets> is an empty collection
Info (332050): create_clock -name KEY1 -period 10.000 [get_ports {KEY1}]
Info (332110): Deriving PLL clocks
Info (332110): create_generated_clock -source {ula_|pll_|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 280 -multiply_by 141 -duty_cycle 50.00 -name {ula_|pll_|altpll_component|auto_generated|pll1|clk[0]} {ula_|pll_|altpll_component|auto_generated|pll1|clk[0]}
Info (332110): create_generated_clock -source {ula_|pll_|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 168 -multiply_by 47 -duty_cycle 50.00 -name {ula_|pll_|altpll_component|auto_generated|pll1|clk[1]} {ula_|pll_|altpll_component|auto_generated|pll1|clk[1]}
Info (332110): create_generated_clock -source {ula_|pll_|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 98 -multiply_by 47 -duty_cycle 50.00 -name {ula_|pll_|altpll_component|auto_generated|pll1|clk[2]} {ula_|pll_|altpll_component|auto_generated|pll1|clk[2]}
Warning (332174): Ignored filter at spectrum.sdc(21): ula_|clocks_|clk_cpu|regout could not be matched with a pin
Warning (332049): Ignored create_generated_clock at spectrum.sdc(21): Argument <targets> is an empty collection
Info (332050): create_generated_clock -name clk_cpu -source [get_pins {ula_|clocks_|clk_cpu|clk}] -divide_by 4 [get_pins {ula_|clocks_|clk_cpu|regout}]
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
Warning (332174): Ignored filter at spectrum.sdc(56): clk_cpu could not be matched with a clock
Warning (332174): Ignored filter at spectrum.sdc(57): KEY1 could not be matched with a clock
Warning (332174): Ignored filter at spectrum.sdc(54): ula_|pll_|altpll_component|pll|clk[0] could not be matched with a clock
Warning (332174): Ignored filter at spectrum.sdc(54): ula_|pll_|altpll_component|pll|clk[1] could not be matched with a clock
Warning (332174): Ignored filter at spectrum.sdc(54): ula_|pll_|altpll_component|pll|clk[2] could not be matched with a clock
Warning (332125): Found combinational loop of 517 nodes
Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~3|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~0|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~0|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~1|datac"
Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~1|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[0]~3|datab"
Warning (332126): Node "z80_|alu_control_|db[0]~9|datac"
Warning (332126): Node "z80_|alu_control_|db[0]~9|combout"
Warning (332126): Node "z80_|alu_control_|db[0]~12|datac"
Warning (332126): Node "z80_|alu_control_|db[0]~12|combout"
Warning (332126): Node "z80_|bus_control_|db[0]~17|datab"
Warning (332126): Node "z80_|bus_control_|db[0]~17|combout"
Warning (332126): Node "z80_|alu_control_|db[0]~8|datad"
Warning (332126): Node "z80_|alu_control_|db[0]~8|combout"
Warning (332126): Node "z80_|alu_control_|db[0]~9|datab"
Warning (332126): Node "z80_|alu_|db[0]~14|dataa"
Warning (332126): Node "z80_|alu_|db[0]~14|combout"
Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|datad"
Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|combout"
Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~2|dataa"
Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~2|combout"
Warning (332126): Node "z80_|alu_|db_low[0]~2|datab"
Warning (332126): Node "z80_|alu_|db_low[0]~2|combout"
Warning (332126): Node "z80_|alu_|db_low[0]~3|datac"
Warning (332126): Node "z80_|alu_|db_low[0]~3|combout"
Warning (332126): Node "z80_|alu_|db_low[0]~24|datab"
Warning (332126): Node "z80_|alu_|db_low[0]~24|combout"
Warning (332126): Node "z80_|alu_|db[0]~13|datac"
Warning (332126): Node "z80_|alu_|db[0]~13|combout"
Warning (332126): Node "z80_|alu_|db[0]~14|datad"
Warning (332126): Node "z80_|alu_|db_high[3]~4|datab"
Warning (332126): Node "z80_|alu_|db_high[3]~4|combout"
Warning (332126): Node "z80_|alu_|db_high[3]~5|datad"
Warning (332126): Node "z80_|alu_|db_high[3]~5|combout"
Warning (332126): Node "z80_|alu_|db_high[3]~6|datab"
Warning (332126): Node "z80_|alu_|db_high[3]~6|combout"
Warning (332126): Node "z80_|alu_|db_high[3]~7|datad"
Warning (332126): Node "z80_|alu_|db_high[3]~7|combout"
Warning (332126): Node "z80_|alu_|db[7]~12|datac"
Warning (332126): Node "z80_|alu_|db[7]~12|combout"
Warning (332126): Node "z80_|alu_|db_high[3]~5|dataa"
Warning (332126): Node "z80_|alu_control_|b2v_inst_shift_mux|out~1|dataa"
Warning (332126): Node "z80_|alu_|db_high[2]~8|datac"
Warning (332126): Node "z80_|alu_|db_high[2]~8|combout"
Warning (332126): Node "z80_|alu_|db_high[2]~9|datac"
Warning (332126): Node "z80_|alu_|db_high[2]~9|combout"
Warning (332126): Node "z80_|alu_|db_high[2]~12|dataa"
Warning (332126): Node "z80_|alu_|db_high[2]~12|combout"
Warning (332126): Node "z80_|alu_|db_high[2]~13|datab"
Warning (332126): Node "z80_|alu_|db_high[2]~13|combout"
Warning (332126): Node "z80_|alu_|db[6]~22|datac"
Warning (332126): Node "z80_|alu_|db[6]~22|combout"
Warning (332126): Node "z80_|alu_|db_high[3]~4|dataa"
Warning (332126): Node "z80_|alu_|db_high[2]~9|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~80|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~80|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~82|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~82|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~83|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~83|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~84|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~84|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~22|datab"
Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~22|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~23|dataa"
Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~23|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~24|datac"
Warning (332126): Node "z80_|reg_file_|db_hi_as[6]~24|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[6]~84|datac"
Warning (332126): Node "z80_|alu_|db[6]~21|datad"
Warning (332126): Node "z80_|alu_|db[6]~21|combout"
Warning (332126): Node "z80_|alu_|db[6]~22|datad"
Warning (332126): Node "z80_|alu_control_|db[6]~20|dataa"
Warning (332126): Node "z80_|alu_control_|db[6]~20|combout"
Warning (332126): Node "z80_|alu_control_|db[6]~21|datad"
Warning (332126): Node "z80_|alu_control_|db[6]~21|combout"
Warning (332126): Node "z80_|alu_control_|db[6]~22|datac"
Warning (332126): Node "z80_|alu_control_|db[6]~22|combout"
Warning (332126): Node "z80_|bus_control_|db[6]~8|datad"
Warning (332126): Node "z80_|bus_control_|db[6]~8|combout"
Warning (332126): Node "z80_|bus_control_|db[6]~9|datab"
Warning (332126): Node "z80_|bus_control_|db[6]~9|combout"
Warning (332126): Node "z80_|sw1_|db_down[6]~1|datab"
Warning (332126): Node "z80_|sw1_|db_down[6]~1|combout"
Warning (332126): Node "z80_|alu_control_|db[6]~22|datab"
Warning (332126): Node "z80_|alu_|db[6]~21|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~79|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~79|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~80|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~81|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~81|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~82|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~82|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_ds[6]~0|datad"
Warning (332126): Node "z80_|reg_file_|db_lo_ds[6]~0|combout"
Warning (332126): Node "z80_|alu_control_|db[6]~22|dataa"
Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~19|dataa"
Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~19|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~20|datad"
Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~20|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~21|datac"
Warning (332126): Node "z80_|reg_file_|db_lo_as[6]~21|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[6]~82|datad"
Warning (332126): Node "z80_|alu_|db_high[1]~16|dataa"
Warning (332126): Node "z80_|alu_|db_high[1]~16|combout"
Warning (332126): Node "z80_|alu_|db_high[1]~17|datab"
Warning (332126): Node "z80_|alu_|db_high[1]~17|combout"
Warning (332126): Node "z80_|alu_|db_high[1]~18|datad"
Warning (332126): Node "z80_|alu_|db_high[1]~18|combout"
Warning (332126): Node "z80_|alu_|db_high[1]~19|datad"
Warning (332126): Node "z80_|alu_|db_high[1]~19|combout"
Warning (332126): Node "z80_|alu_|db[5]~24|datab"
Warning (332126): Node "z80_|alu_|db[5]~24|combout"
Warning (332126): Node "z80_|alu_|db_high[2]~8|datab"
Warning (332126): Node "z80_|alu_|db_high[0]~22|datac"
Warning (332126): Node "z80_|alu_|db_high[0]~22|combout"
Warning (332126): Node "z80_|alu_|db_high[0]~23|datad"
Warning (332126): Node "z80_|alu_|db_high[0]~23|combout"
Warning (332126): Node "z80_|alu_|db_high[0]~24|datad"
Warning (332126): Node "z80_|alu_|db_high[0]~24|combout"
Warning (332126): Node "z80_|alu_|db_high[0]~25|dataa"
Warning (332126): Node "z80_|alu_|db_high[0]~25|combout"
Warning (332126): Node "z80_|alu_|db[4]~18|datad"
Warning (332126): Node "z80_|alu_|db[4]~18|combout"
Warning (332126): Node "z80_|alu_control_|db[4]~30|dataa"
Warning (332126): Node "z80_|alu_control_|db[4]~30|combout"
Warning (332126): Node "z80_|alu_control_|db[4]~31|datad"
Warning (332126): Node "z80_|alu_control_|db[4]~31|combout"
Warning (332126): Node "z80_|alu_control_|db[4]~32|datab"
Warning (332126): Node "z80_|alu_control_|db[4]~32|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~54|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~54|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~61|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~61|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~62|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~62|combout"
Warning (332126): Node "z80_|alu_control_|db[4]~30|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~13|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~13|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~14|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~14|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~15|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[4]~15|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[4]~62|datad"
Warning (332126): Node "z80_|alu_|db[4]~17|datab"
Warning (332126): Node "z80_|alu_|db[4]~17|combout"
Warning (332126): Node "z80_|alu_|db[4]~18|datac"
Warning (332126): Node "z80_|bus_control_|db[4]~19|datac"
Warning (332126): Node "z80_|bus_control_|db[4]~19|combout"
Warning (332126): Node "z80_|alu_control_|db[4]~32|dataa"
Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|datab"
Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|combout"
Warning (332126): Node "z80_|alu_|db_low[3]~16|dataa"
Warning (332126): Node "z80_|alu_|db_low[3]~16|combout"
Warning (332126): Node "z80_|alu_|db_low[3]~17|datab"
Warning (332126): Node "z80_|alu_|db_low[3]~17|combout"
Warning (332126): Node "z80_|alu_|db_low[3]~25|datad"
Warning (332126): Node "z80_|alu_|db_low[3]~25|combout"
Warning (332126): Node "z80_|alu_|db[3]~19|datab"
Warning (332126): Node "z80_|alu_|db[3]~19|combout"
Warning (332126): Node "z80_|alu_|db[3]~20|datad"
Warning (332126): Node "z80_|alu_|db[3]~20|combout"
Warning (332126): Node "z80_|alu_|db_high[0]~22|datab"
Warning (332126): Node "z80_|alu_control_|db[3]~35|datac"
Warning (332126): Node "z80_|alu_control_|db[3]~35|combout"
Warning (332126): Node "z80_|bus_control_|db[3]~21|datab"
Warning (332126): Node "z80_|bus_control_|db[3]~21|combout"
Warning (332126): Node "z80_|alu_|db_high[2]~11|datac"
Warning (332126): Node "z80_|alu_|db_high[2]~11|combout"
Warning (332126): Node "z80_|alu_|db_high[2]~12|datac"
Warning (332126): Node "z80_|alu_|db_high[0]~20|dataa"
Warning (332126): Node "z80_|alu_|db_high[0]~20|combout"
Warning (332126): Node "z80_|alu_|db_high[0]~24|dataa"
Warning (332126): Node "z80_|alu_|db_high[1]~14|dataa"
Warning (332126): Node "z80_|alu_|db_high[1]~14|combout"
Warning (332126): Node "z80_|alu_|db_high[1]~18|dataa"
Warning (332126): Node "z80_|alu_|db_low[0]~4|dataa"
Warning (332126): Node "z80_|alu_|db_low[0]~4|combout"
Warning (332126): Node "z80_|alu_|db_low[0]~6|datab"
Warning (332126): Node "z80_|alu_|db_low[0]~6|combout"
Warning (332126): Node "z80_|alu_|db_low[0]~24|dataa"
Warning (332126): Node "z80_|sw1_|db_down[3]~2|datad"
Warning (332126): Node "z80_|sw1_|db_down[3]~2|combout"
Warning (332126): Node "z80_|alu_control_|db[3]~34|datad"
Warning (332126): Node "z80_|alu_control_|db[3]~34|combout"
Warning (332126): Node "z80_|alu_control_|db[3]~35|dataa"
Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|datac"
Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|combout"
Warning (332126): Node "z80_|alu_|db_low[2]~19|dataa"
Warning (332126): Node "z80_|alu_|db_low[2]~19|combout"
Warning (332126): Node "z80_|alu_|db_low[2]~20|datad"
Warning (332126): Node "z80_|alu_|db_low[2]~20|combout"
Warning (332126): Node "z80_|alu_|db_low[2]~23|datad"
Warning (332126): Node "z80_|alu_|db_low[2]~23|combout"
Warning (332126): Node "z80_|alu_|db[2]~16|datad"
Warning (332126): Node "z80_|alu_|db[2]~16|combout"
Warning (332126): Node "z80_|alu_control_|db[2]~27|dataa"
Warning (332126): Node "z80_|alu_control_|db[2]~27|combout"
Warning (332126): Node "z80_|alu_control_|db[2]~29|datab"
Warning (332126): Node "z80_|alu_control_|db[2]~29|combout"
Warning (332126): Node "z80_|bus_control_|db[2]~12|datac"
Warning (332126): Node "z80_|bus_control_|db[2]~12|combout"
Warning (332126): Node "z80_|bus_control_|db[2]~13|datad"
Warning (332126): Node "z80_|bus_control_|db[2]~13|combout"
Warning (332126): Node "z80_|alu_control_|db[2]~28|datab"
Warning (332126): Node "z80_|alu_control_|db[2]~28|combout"
Warning (332126): Node "z80_|alu_control_|db[2]~29|dataa"
Warning (332126): Node "z80_|alu_|db[2]~15|datad"
Warning (332126): Node "z80_|alu_|db[2]~15|combout"
Warning (332126): Node "z80_|alu_|db[2]~16|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~39|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~39|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~40|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~40|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~41|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~41|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_ds[2]~2|datad"
Warning (332126): Node "z80_|reg_file_|db_lo_ds[2]~2|combout"
Warning (332126): Node "z80_|alu_control_|db[2]~28|datad"
Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~7|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~7|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~8|datac"
Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~8|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~9|dataa"
Warning (332126): Node "z80_|reg_file_|db_lo_as[2]~9|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[2]~42|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~35|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~35|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~37|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~37|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~38|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~38|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~39|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~39|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~7|dataa"
Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~7|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~8|dataa"
Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~8|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~9|datac"
Warning (332126): Node "z80_|reg_file_|db_hi_as[2]~9|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[2]~39|datac"
Warning (332126): Node "z80_|alu_|db[2]~15|datab"
Warning (332126): Node "z80_|alu_|db_low[3]~13|datad"
Warning (332126): Node "z80_|alu_|db_low[3]~13|combout"
Warning (332126): Node "z80_|alu_|db_low[3]~14|dataa"
Warning (332126): Node "z80_|alu_|db_low[3]~14|combout"
Warning (332126): Node "z80_|alu_|db_low[3]~17|datad"
Warning (332126): Node "z80_|alu_|db_low[2]~22|datac"
Warning (332126): Node "z80_|alu_|db_low[2]~22|combout"
Warning (332126): Node "z80_|alu_|db_low[2]~23|dataa"
Warning (332126): Node "z80_|alu_|db_low[1]~10|dataa"
Warning (332126): Node "z80_|alu_|db_low[1]~10|combout"
Warning (332126): Node "z80_|alu_|db_low[1]~11|datad"
Warning (332126): Node "z80_|alu_|db_low[1]~11|combout"
Warning (332126): Node "z80_|alu_|db_low[1]~12|dataa"
Warning (332126): Node "z80_|alu_|db_low[1]~12|combout"
Warning (332126): Node "z80_|alu_|db[1]~10|datac"
Warning (332126): Node "z80_|alu_|db[1]~10|combout"
Warning (332126): Node "z80_|alu_control_|db[1]~24|datab"
Warning (332126): Node "z80_|alu_control_|db[1]~24|combout"
Warning (332126): Node "z80_|alu_control_|db[1]~26|datab"
Warning (332126): Node "z80_|alu_control_|db[1]~26|combout"
Warning (332126): Node "z80_|bus_control_|db[1]~10|datad"
Warning (332126): Node "z80_|bus_control_|db[1]~10|combout"
Warning (332126): Node "z80_|bus_control_|db[1]~11|datab"
Warning (332126): Node "z80_|bus_control_|db[1]~11|combout"
Warning (332126): Node "z80_|alu_control_|db[1]~25|datab"
Warning (332126): Node "z80_|alu_control_|db[1]~25|combout"
Warning (332126): Node "z80_|alu_control_|db[1]~26|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~29|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~29|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~30|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~30|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~31|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~31|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_ds[1]~1|datad"
Warning (332126): Node "z80_|reg_file_|db_lo_ds[1]~1|combout"
Warning (332126): Node "z80_|alu_control_|db[1]~25|dataa"
Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~4|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~4|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~5|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~5|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~6|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[1]~6|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[1]~32|datab"
Warning (332126): Node "z80_|alu_|db[1]~8|datad"
Warning (332126): Node "z80_|alu_|db[1]~8|combout"
Warning (332126): Node "z80_|alu_|db[1]~10|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~12|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~12|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~14|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~14|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~15|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~15|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|combout"
Warning (332126): Node "z80_|alu_|db[1]~8|datac"
Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~0|dataa"
Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~0|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~1|datab"
Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~1|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~3|datab"
Warning (332126): Node "z80_|reg_file_|db_hi_as[1]~3|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[1]~21|datac"
Warning (332126): Node "z80_|alu_|db_low[1]~11|dataa"
Warning (332126): Node "z80_|alu_|db_low[2]~21|datad"
Warning (332126): Node "z80_|alu_|db_low[2]~21|combout"
Warning (332126): Node "z80_|alu_|db_low[2]~22|datab"
Warning (332126): Node "z80_|alu_|db_low[0]~2|dataa"
Warning (332126): Node "z80_|alu_|db_low[1]~7|dataa"
Warning (332126): Node "z80_|alu_|db_low[1]~7|combout"
Warning (332126): Node "z80_|alu_|db_low[1]~9|datab"
Warning (332126): Node "z80_|alu_|db_low[1]~9|combout"
Warning (332126): Node "z80_|alu_|db_low[1]~12|datad"
Warning (332126): Node "z80_|alu_|db_high[3]~2|dataa"
Warning (332126): Node "z80_|alu_|db_high[3]~2|combout"
Warning (332126): Node "z80_|alu_|db_high[3]~6|datad"
Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~2|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~46|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~46|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~47|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~47|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~50|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~50|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~51|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~51|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~52|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~52|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~10|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~10|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~11|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~11|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~12|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[3]~12|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[3]~52|datac"
Warning (332126): Node "z80_|alu_control_|db[3]~34|dataa"
Warning (332126): Node "z80_|alu_|db[3]~20|dataa"
Warning (332126): Node "z80_|alu_|db_low[3]~14|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~44|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~44|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~46|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~46|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~47|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~47|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~48|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~48|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~10|dataa"
Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~10|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~11|datad"
Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~11|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~12|datac"
Warning (332126): Node "z80_|reg_file_|db_hi_as[3]~12|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[3]~48|dataa"
Warning (332126): Node "z80_|alu_|db[3]~19|datac"
Warning (332126): Node "z80_|alu_|db_low[2]~21|dataa"
Warning (332126): Node "z80_|alu_|db_high[2]~11|datab"
Warning (332126): Node "z80_|alu_|db_high[0]~20|datad"
Warning (332126): Node "z80_|alu_|db_high[1]~14|datad"
Warning (332126): Node "z80_|alu_|db_low[0]~4|datad"
Warning (332126): Node "z80_|alu_|b2v_input_bit_select|bs_out_high_ALTERA_SYNTHESIZED~3|datab"
Warning (332126): Node "z80_|alu_|db_low[1]~7|datad"
Warning (332126): Node "z80_|alu_|db_high[3]~2|datad"
Warning (332126): Node "z80_|alu_|db_high[0]~23|dataa"
Warning (332126): Node "z80_|alu_|db_low[3]~13|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~62|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~62|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~64|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~64|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~65|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~65|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~66|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~66|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~16|datab"
Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~16|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~17|dataa"
Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~17|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~18|datab"
Warning (332126): Node "z80_|reg_file_|db_hi_as[4]~18|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[4]~66|datab"
Warning (332126): Node "z80_|alu_|db[4]~17|datad"
Warning (332126): Node "z80_|alu_|db_high[1]~16|datad"
Warning (332126): Node "z80_|alu_|db_high[1]~17|dataa"
Warning (332126): Node "z80_|alu_control_|db[5]~15|dataa"
Warning (332126): Node "z80_|alu_control_|db[5]~15|combout"
Warning (332126): Node "z80_|bus_control_|db[5]~15|datab"
Warning (332126): Node "z80_|bus_control_|db[5]~15|combout"
Warning (332126): Node "z80_|alu_|db_high[2]~11|datad"
Warning (332126): Node "z80_|alu_|db_high[0]~20|datab"
Warning (332126): Node "z80_|alu_|db_high[1]~14|datab"
Warning (332126): Node "z80_|sw1_|db_down[5]~0|datac"
Warning (332126): Node "z80_|sw1_|db_down[5]~0|combout"
Warning (332126): Node "z80_|alu_control_|db[5]~14|dataa"
Warning (332126): Node "z80_|alu_control_|db[5]~14|combout"
Warning (332126): Node "z80_|alu_control_|db[5]~15|datac"
Warning (332126): Node "z80_|alu_|db_low[0]~4|datab"
Warning (332126): Node "z80_|alu_|db_low[3]~16|datab"
Warning (332126): Node "z80_|alu_|db_low[2]~19|datab"
Warning (332126): Node "z80_|alu_|db_low[1]~7|datab"
Warning (332126): Node "z80_|alu_|db_high[3]~2|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~66|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~66|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~67|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~67|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~70|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~70|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~71|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~71|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~72|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~72|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~16|dataa"
Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~16|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~17|datad"
Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~17|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~18|datac"
Warning (332126): Node "z80_|reg_file_|db_lo_as[5]~18|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[5]~72|datab"
Warning (332126): Node "z80_|alu_control_|db[5]~14|datac"
Warning (332126): Node "z80_|alu_|db[5]~23|dataa"
Warning (332126): Node "z80_|alu_|db[5]~23|combout"
Warning (332126): Node "z80_|alu_|db[5]~24|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~53|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~53|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~55|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~55|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~56|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~56|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|combout"
Warning (332126): Node "z80_|alu_|db[5]~23|datab"
Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~13|dataa"
Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~13|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~14|datad"
Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~14|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~15|datad"
Warning (332126): Node "z80_|reg_file_|db_hi_as[5]~15|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[5]~57|dataa"
Warning (332126): Node "z80_|alu_control_|db[7]~16|datab"
Warning (332126): Node "z80_|alu_control_|db[7]~16|combout"
Warning (332126): Node "z80_|alu_control_|db[7]~17|datab"
Warning (332126): Node "z80_|alu_control_|db[7]~17|combout"
Warning (332126): Node "z80_|alu_control_|db[7]~18|datad"
Warning (332126): Node "z80_|alu_control_|db[7]~18|combout"
Warning (332126): Node "z80_|alu_control_|db[7]~19|dataa"
Warning (332126): Node "z80_|alu_control_|db[7]~19|combout"
Warning (332126): Node "z80_|bus_control_|db[7]~5|datad"
Warning (332126): Node "z80_|bus_control_|db[7]~5|combout"
Warning (332126): Node "z80_|bus_control_|db[7]~7|datab"
Warning (332126): Node "z80_|bus_control_|db[7]~7|combout"
Warning (332126): Node "z80_|alu_control_|db[7]~18|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~88|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~88|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~89|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~89|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|datac"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~90|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~91|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~91|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~22|dataa"
Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~22|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~23|dataa"
Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~23|combout"
Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~24|datab"
Warning (332126): Node "z80_|reg_file_|db_lo_as[7]~24|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[7]~91|datad"
Warning (332126): Node "z80_|alu_control_|db[7]~17|dataa"
Warning (332126): Node "z80_|alu_|db[7]~11|datab"
Warning (332126): Node "z80_|alu_|db[7]~11|combout"
Warning (332126): Node "z80_|alu_|db[7]~12|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~71|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~71|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~73|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~73|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~74|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~74|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~75|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~75|combout"
Warning (332126): Node "z80_|alu_|db[7]~11|datad"
Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~19|datad"
Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~19|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~20|datad"
Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~20|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~21|datad"
Warning (332126): Node "z80_|reg_file_|db_hi_as[7]~21|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[7]~75|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~26|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~26|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~28|datad"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~28|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~29|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~29|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|combout"
Warning (332126): Node "z80_|alu_|db[0]~13|datab"
Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~4|datad"
Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~4|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~5|datad"
Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~5|combout"
Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~6|datab"
Warning (332126): Node "z80_|reg_file_|db_hi_as[0]~6|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp1[0]~30|dataa"
Warning (332126): Node "z80_|alu_|db_low[1]~10|datab"
Warning (332126): Node "z80_|alu_|db_low[0]~3|datad"
Warning (332126): Node "z80_|sw2_|db_up[0]~0|datac"
Warning (332126): Node "z80_|sw2_|db_up[0]~0|combout"
Warning (332126): Node "z80_|alu_control_|db[0]~9|dataa"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~12|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~12|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~17|datab"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~17|combout"
Warning (332126): Node "z80_|reg_file_|gdfx_temp0[0]~22|datad"
Critical Warning (332081): Design contains combinational loop of 517 nodes. Estimating the delays through the loop.
Warning (332060): Node: ula:ula_|clocks:clocks_|clk_cpu was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: KEY[1] was determined to be a clock but was found without an associated clock assignment.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1200mV 85C Model
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -18.425
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -18.425 -546.891 CLOCK_50
Info (332119): -6.923 -271.506 ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Info (332119): -4.745 -42.191 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332119): -2.915 -2.915 ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Info (332146): Worst-case hold slack is 0.342
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 0.342 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Info (332119): 0.342 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332119): 0.357 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 0.517 0.000 CLOCK_50
Info (332146): Worst-case recovery slack is -6.263
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -6.263 -464.840 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332146): Worst-case removal slack is 3.657
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 3.657 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332146): Worst-case minimum pulse width slack is 9.488
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 9.488 0.000 CLOCK_50
Info (332119): 19.602 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 20.597 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332119): 35.503 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Warning (332060): Node: ula:ula_|clocks:clocks_|clk_cpu was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: KEY[1] was determined to be a clock but was found without an associated clock assignment.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -17.572
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -17.572 -524.603 CLOCK_50
Info (332119): -6.192 -241.805 ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Info (332119): -4.414 -39.436 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332119): -2.786 -2.786 ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Info (332146): Worst-case hold slack is 0.297
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 0.297 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332119): 0.298 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Info (332119): 0.311 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 0.467 0.000 CLOCK_50
Info (332146): Worst-case recovery slack is -5.773
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -5.773 -427.930 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332146): Worst-case removal slack is 3.347
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 3.347 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332146): Worst-case minimum pulse width slack is 9.489
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 9.489 0.000 CLOCK_50
Info (332119): 19.601 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 20.590 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332119): 35.491 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Info: Analyzing Fast 1200mV 0C Model
Warning (332060): Node: ula:ula_|clocks:clocks_|clk_cpu was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: KEY[1] was determined to be a clock but was found without an associated clock assignment.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -15.171
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -15.171 -440.252 CLOCK_50
Info (332119): -4.743 -163.399 ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Info (332119): -3.815 -35.260 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332119): -2.784 -2.784 ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Info (332146): Worst-case hold slack is 0.112
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 0.112 0.000 CLOCK_50
Info (332119): 0.177 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Info (332119): 0.178 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332119): 0.186 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Info (332146): Worst-case recovery slack is -4.728
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -4.728 -362.420 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332146): Worst-case removal slack is 2.503
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 2.503 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332146): Worst-case minimum pulse width slack is 9.208
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 9.208 0.000 CLOCK_50
Info (332119): 19.609 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 20.600 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[2]
Info (332119): 35.535 0.000 ula_|pll_|altpll_component|auto_generated|pll1|clk[1]
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 538 warnings
Info: Peak virtual memory: 440 megabytes
Info: Processing ended: Sat Apr 2 15:53:41 2022
Info: Elapsed time: 00:00:04
Info: Total CPU time (on all processors): 00:00:04
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