42 lines
1.1 KiB
Systemverilog
42 lines
1.1 KiB
Systemverilog
//--------------------------------------------------------------
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// Implements RAM Model for simulation
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// Loads in a file "ram.hexdump" before execution.
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//--------------------------------------------------------------
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module ram (Address, Data, CS, WE, OE);
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// Set this to 1 if you want debug printout on each RAM access
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int debug = 0;
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input [15:0] Address;
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inout [7:0] Data;
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input CS, WE, OE;
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reg [7:0] Mem [0:1<<16];
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// Return data at the specified memory address; return 0x76 for non-initialized memory
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assign Data = (!CS && !OE) ? (Mem[Address]===8'hxx) ? 8'h76 : Mem[Address] : {8{1'bz}};
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// Read the initial content of the RAM memory from a file
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initial begin : init
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// Read the CPU code (address 0) to simulate
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$readmemh("ram.hexdump", Mem, 0);
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end : init
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always @(!CS && !OE) begin
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if (debug)
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$strobe("[ram] RD A=%H, D=%H", Address, Data);
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end
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always @(CS or WE)
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if (!CS && !WE) begin
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if (debug)
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$strobe("[ram] WR A=%H, D=%H", Address, Data);
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Mem[Address] = Data;
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end
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always @(WE or OE)
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if (!WE && !OE)
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$display("[ram] error: OE and WE both active!");
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endmodule
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