62 lines
1.8 KiB
Systemverilog
62 lines
1.8 KiB
Systemverilog
//--------------------------------------------------------------
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// Implements I/O Model for simulation
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//--------------------------------------------------------------
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module io (Address, Data, CS, WE, OE);
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// Set to 1 to have text output to the file "iolog.txt"
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int iolog = 1;
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// Set to 1 if you want debug printout on each IO access
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int debug = 0;
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int fd;
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input [15:0] Address;
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inout [7:0] Data;
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input CS, WE, OE;
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reg [7:0] IO [0:1<<16];
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// Return data for the specified IO address:
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// 1. If the current address is 0A00, that's the UART busy bit (which is never busy for ModelSim), so return 00
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// 2. If the IO map is not defined for the current address, return FF
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// 3. If the IO map is defined, return the value from it
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// 4. Lastly, if !CS and !OE (not selecting the IO), tri-state the data bus
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assign Data = (!CS && !OE) ? (Address==16'h0A00)? 8'h00 : (IO[Address]===8'hxx) ? 8'hFF : IO[Address] : {8{1'bz}};
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// Read the initial content of the IO map from file
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initial begin : init
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$readmemh("io.hex", IO);
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// If logging to a file was enabled, clear the file so we can append
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if (iolog) begin
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fd = $fopen("iolog.txt", "wb");
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$fclose(fd);
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end
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end : init
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always @(!CS && !OE) begin
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if (debug)
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$strobe("[IO] IN A=%H, D=%H", Address, Data);
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end
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always @(CS or WE)
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if (!CS && !WE) begin
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if (debug)
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$strobe("[IO] OUT A=%H, D=%H", Address, Data);
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if (Address==8*256) begin
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$write("%c", Data);
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// If logging to a file was enabled, append a character
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if (iolog) begin
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fd = $fopen("iolog.txt", "ab");
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$fwrite(fd, "%c", Data);
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$fclose(fd);
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end
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end
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IO[Address] = Data;
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end
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always @(WE or OE)
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if (!WE && !OE)
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$display("[IO] error: OE and WE both active!");
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endmodule
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